drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 /*
  76  * High threshold controlling when to start sending XOFF frames. Must be at
  77  * least 8 bytes less than receive packet buffer size. This value is in units
  78  * of 1024 bytes.
  79  */
  80 #define IXGBE_FC_HI    0x80
  81
  82 /*
  83  * Low threshold controlling when to start sending XON frames. This value is
  84  * in units of 1024 bytes.
  85  */
  86 #define IXGBE_FC_LO    0x40
  87
  88 /* Default minimum inter-interrupt interval for EITR configuration */
  89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  90
  91 /* Timer value included in XOFF frames. */
  92 #define IXGBE_FC_PAUSE 0x680
  93
  94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  95 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  96 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  97
  98 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  99 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 100 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 101
 102 /*
 103  *  Default values for RX/TX configuration
 104  */
 105 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 106 #define IXGBE_DEFAULT_RX_PTHRESH      8
 107 #define IXGBE_DEFAULT_RX_HTHRESH      8
 108 #define IXGBE_DEFAULT_RX_WTHRESH      0
 109
 110 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_TX_PTHRESH      32
 112 #define IXGBE_DEFAULT_TX_HTHRESH      0
 113 #define IXGBE_DEFAULT_TX_WTHRESH      0
 114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 115
 116 /* Bit shift and mask */
 117 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 118 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 119 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 120 #define IXGBE_8_BIT_MASK   UINT8_MAX
 121
 122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 123
 124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 125
 126 #define IXGBE_HKEY_MAX_INDEX 10
 127
 128 /* Additional timesync values. */
 129 #define IXGBE_TIMINCA_16NS_SHIFT 24
 130 #define IXGBE_TIMINCA_INCVALUE   16000000
 131 #define IXGBE_TIMINCA_INIT       ((0x02 << IXGBE_TIMINCA_16NS_SHIFT) \
 132                                   | IXGBE_TIMINCA_INCVALUE)
 133
 134 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 135 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 136 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 137 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 138 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 139 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 140 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 141 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 142 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 143 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 144 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 145 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 146 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 147                                 int wait_to_complete);
 148 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 149                                 struct rte_eth_stats *stats);
 150 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 151                                 struct rte_eth_xstats *xstats, unsigned n);
 152 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 153                                   struct rte_eth_xstats *xstats, unsigned n);
 154 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 155 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 156 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 157                                              uint16_t queue_id,
 158                                              uint8_t stat_idx,
 159                                              uint8_t is_rx);
 160 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 161                                struct rte_eth_dev_info *dev_info);
 162 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 163                                  struct rte_eth_dev_info *dev_info);
 164 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 165
 166 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 167                 uint16_t vlan_id, int on);
 168 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 169 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 170                 uint16_t queue, bool on);
 171 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 172                 int on);
 173 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 174 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 175 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 176 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 177 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 178
 179 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 180 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 181 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 182                                struct rte_eth_fc_conf *fc_conf);
 183 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 184                                struct rte_eth_fc_conf *fc_conf);
 185 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 186                 struct rte_eth_pfc_conf *pfc_conf);
 187 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 188                         struct rte_eth_rss_reta_entry64 *reta_conf,
 189                         uint16_t reta_size);
 190 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 191                         struct rte_eth_rss_reta_entry64 *reta_conf,
 192                         uint16_t reta_size);
 193 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 194 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 195 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 196 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 197 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 198 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 199                 void *param);
 200 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 201 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 202                 uint32_t index, uint32_t pool);
 203 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 204 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 205                                            struct ether_addr *mac_addr);
 206 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 207
 208 /* For Virtual Function support */
 209 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 210 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 211 static int ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev);
 212 static int ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev);
 213 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 214 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 215 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 216 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 217 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 218 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 219 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 220                 struct rte_eth_stats *stats);
 221 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 222 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 223                 uint16_t vlan_id, int on);
 224 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 225                 uint16_t queue, int on);
 226 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 227 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 228 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
 229                                           void *param);
 230 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 231                                             uint16_t queue_id);
 232 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 233                                              uint16_t queue_id);
 234 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 235                                  uint8_t queue, uint8_t msix_vector);
 236 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 237
 238 /* For Eth VMDQ APIs support */
 239 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 240                 ether_addr* mac_addr,uint8_t on);
 241 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 242 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 243                 uint16_t rx_mask, uint8_t on);
 244 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 245 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 246 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 247                 uint64_t pool_mask,uint8_t vlan_on);
 248 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 249                 struct rte_eth_mirror_conf *mirror_conf,
 250                 uint8_t rule_id, uint8_t on);
 251 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 252                 uint8_t rule_id);
 253 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 254                                           uint16_t queue_id);
 255 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 256                                            uint16_t queue_id);
 257 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 258                                uint8_t queue, uint8_t msix_vector);
 259 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 260
 261 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 262                 uint16_t queue_idx, uint16_t tx_rate);
 263 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 264                 uint16_t tx_rate, uint64_t q_msk);
 265
 266 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 267                                  struct ether_addr *mac_addr,
 268                                  uint32_t index, uint32_t pool);
 269 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 270 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 271                                              struct ether_addr *mac_addr);
 272 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 273                         struct rte_eth_syn_filter *filter,
 274                         bool add);
 275 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 276                         struct rte_eth_syn_filter *filter);
 277 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 278                         enum rte_filter_op filter_op,
 279                         void *arg);
 280 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 281                         struct ixgbe_5tuple_filter *filter);
 282 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 283                         struct ixgbe_5tuple_filter *filter);
 284 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 285                         struct rte_eth_ntuple_filter *filter,
 286                         bool add);
 287 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 288                                 enum rte_filter_op filter_op,
 289                                 void *arg);
 290 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 291                         struct rte_eth_ntuple_filter *filter);
 292 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 293                         struct rte_eth_ethertype_filter *filter,
 294                         bool add);
 295 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 296                                 enum rte_filter_op filter_op,
 297                                 void *arg);
 298 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 299                         struct rte_eth_ethertype_filter *filter);
 300 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 301                      enum rte_filter_type filter_type,
 302                      enum rte_filter_op filter_op,
 303                      void *arg);
 304 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 305
 306 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 307                                       struct ether_addr *mc_addr_set,
 308                                       uint32_t nb_mc_addr);
 309 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 310                                    struct rte_eth_dcb_info *dcb_info);
 311
 312 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 313 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 314                             struct rte_dev_reg_info *regs);
 315 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 316 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 317                                 struct rte_dev_eeprom_info *eeprom);
 318 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 319                                 struct rte_dev_eeprom_info *eeprom);
 320
 321 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 322 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 323                                 struct rte_dev_reg_info *regs);
 324
 325 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 326 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 327 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 328                                             struct timespec *timestamp,
 329                                             uint32_t flags);
 330 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 331                                             struct timespec *timestamp);
 332
 333 /*
 334  * Define VF Stats MACRO for Non "cleared on read" register
 335  */
 336 #define UPDATE_VF_STAT(reg, last, cur)                          \
 337 {                                                               \
 338         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 339         cur += (latest - last) & UINT_MAX;                      \
 340         last = latest;                                          \
 341 }
 342
 343 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 344 {                                                                \
 345         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 346         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 347         u64 latest = ((new_msb << 32) | new_lsb);                \
 348         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 349         last = latest;                                           \
 350 }
 351
 352 #define IXGBE_SET_HWSTRIP(h, q) do{\
 353                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 354                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 355                 (h)->bitmap[idx] |= 1 << bit;\
 356         }while(0)
 357
 358 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 359                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 360                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 361                 (h)->bitmap[idx] &= ~(1 << bit);\
 362         }while(0)
 363
 364 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 365                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 366                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 367                 (r) = (h)->bitmap[idx] >> bit & 1;\
 368         }while(0)
 369
 370 /*
 371  * The set of PCI devices this driver supports
 372  */
 373 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 374
 375 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 376 #include "rte_pci_dev_ids.h"
 377
 378 { .vendor_id = 0, /* sentinel */ },
 379 };
 380
 381
 382 /*
 383  * The set of PCI devices this driver supports (for 82599 VF)
 384  */
 385 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 386
 387 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 388 #include "rte_pci_dev_ids.h"
 389 { .vendor_id = 0, /* sentinel */ },
 390
 391 };
 392
 393 static const struct rte_eth_desc_lim rx_desc_lim = {
 394         .nb_max = IXGBE_MAX_RING_DESC,
 395         .nb_min = IXGBE_MIN_RING_DESC,
 396         .nb_align = IXGBE_RXD_ALIGN,
 397 };
 398
 399 static const struct rte_eth_desc_lim tx_desc_lim = {
 400         .nb_max = IXGBE_MAX_RING_DESC,
 401         .nb_min = IXGBE_MIN_RING_DESC,
 402         .nb_align = IXGBE_TXD_ALIGN,
 403 };
 404
 405 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 406         .dev_configure        = ixgbe_dev_configure,
 407         .dev_start            = ixgbe_dev_start,
 408         .dev_stop             = ixgbe_dev_stop,
 409         .dev_set_link_up    = ixgbe_dev_set_link_up,
 410         .dev_set_link_down  = ixgbe_dev_set_link_down,
 411         .dev_close            = ixgbe_dev_close,
 412         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 413         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 414         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 415         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 416         .link_update          = ixgbe_dev_link_update,
 417         .stats_get            = ixgbe_dev_stats_get,
 418         .xstats_get           = ixgbe_dev_xstats_get,
 419         .stats_reset          = ixgbe_dev_stats_reset,
 420         .xstats_reset         = ixgbe_dev_xstats_reset,
 421         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 422         .dev_infos_get        = ixgbe_dev_info_get,
 423         .mtu_set              = ixgbe_dev_mtu_set,
 424         .vlan_filter_set      = ixgbe_vlan_filter_set,
 425         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 426         .vlan_offload_set     = ixgbe_vlan_offload_set,
 427         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 428         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 429         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 430         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 431         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 432         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 433         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 434         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 435         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 436         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 437         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 438         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 439         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 440         .dev_led_on           = ixgbe_dev_led_on,
 441         .dev_led_off          = ixgbe_dev_led_off,
 442         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 443         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 444         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 445         .mac_addr_add         = ixgbe_add_rar,
 446         .mac_addr_remove      = ixgbe_remove_rar,
 447         .mac_addr_set         = ixgbe_set_default_mac_addr,
 448         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 449         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 450         .mirror_rule_set      = ixgbe_mirror_rule_set,
 451         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 452         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 453         .set_vf_rx            = ixgbe_set_pool_rx,
 454         .set_vf_tx            = ixgbe_set_pool_tx,
 455         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 456         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 457         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 458         .reta_update          = ixgbe_dev_rss_reta_update,
 459         .reta_query           = ixgbe_dev_rss_reta_query,
 460 #ifdef RTE_NIC_BYPASS
 461         .bypass_init          = ixgbe_bypass_init,
 462         .bypass_state_set     = ixgbe_bypass_state_store,
 463         .bypass_state_show    = ixgbe_bypass_state_show,
 464         .bypass_event_set     = ixgbe_bypass_event_store,
 465         .bypass_event_show    = ixgbe_bypass_event_show,
 466         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 467         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 468         .bypass_ver_show      = ixgbe_bypass_ver_show,
 469         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 470 #endif /* RTE_NIC_BYPASS */
 471         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 472         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 473         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 474         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 475         .rxq_info_get         = ixgbe_rxq_info_get,
 476         .txq_info_get         = ixgbe_txq_info_get,
 477         .timesync_enable      = ixgbe_timesync_enable,
 478         .timesync_disable     = ixgbe_timesync_disable,
 479         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 480         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 481         .get_reg_length       = ixgbe_get_reg_length,
 482         .get_reg              = ixgbe_get_regs,
 483         .get_eeprom_length    = ixgbe_get_eeprom_length,
 484         .get_eeprom           = ixgbe_get_eeprom,
 485         .set_eeprom           = ixgbe_set_eeprom,
 486         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 487 };
 488
 489 /*
 490  * dev_ops for virtual function, bare necessities for basic vf
 491  * operation have been implemented
 492  */
 493 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 494         .dev_configure        = ixgbevf_dev_configure,
 495         .dev_start            = ixgbevf_dev_start,
 496         .dev_stop             = ixgbevf_dev_stop,
 497         .link_update          = ixgbe_dev_link_update,
 498         .stats_get            = ixgbevf_dev_stats_get,
 499         .xstats_get           = ixgbevf_dev_xstats_get,
 500         .stats_reset          = ixgbevf_dev_stats_reset,
 501         .xstats_reset         = ixgbevf_dev_stats_reset,
 502         .dev_close            = ixgbevf_dev_close,
 503         .dev_infos_get        = ixgbevf_dev_info_get,
 504         .mtu_set              = ixgbevf_dev_set_mtu,
 505         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 506         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 507         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 508         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 509         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 510         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 511         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 512         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 513         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 514         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 515         .mac_addr_add         = ixgbevf_add_mac_addr,
 516         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 517         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 518         .rxq_info_get         = ixgbe_rxq_info_get,
 519         .txq_info_get         = ixgbe_txq_info_get,
 520         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 521         .get_reg_length       = ixgbevf_get_reg_length,
 522         .get_reg              = ixgbevf_get_regs,
 523         .reta_update          = ixgbe_dev_rss_reta_update,
 524         .reta_query           = ixgbe_dev_rss_reta_query,
 525         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 526         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 527 };
 528
 529 /* store statistics names and its offset in stats structure */
 530 struct rte_ixgbe_xstats_name_off {
 531         char name[RTE_ETH_XSTATS_NAME_SIZE];
 532         unsigned offset;
 533 };
 534
 535 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 536         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 537         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 538         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 539         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 540         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 541         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 542         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 543         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 544         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 545         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 546         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 547         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 548         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 549         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 550         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 551                 prc1023)},
 552         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 553                 prc1522)},
 554         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 555         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 556         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 557         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 558         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 559         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 560         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 561         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 562         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 563         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 564         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 565         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 566         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 567         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 568         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 569         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 570         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 571                 ptc1023)},
 572         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 573                 ptc1522)},
 574         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 575         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 576         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 577         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 578
 579         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 580                 fdirustat_add)},
 581         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 582                 fdirustat_remove)},
 583         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 584                 fdirfstat_fadd)},
 585         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 586                 fdirfstat_fremove)},
 587         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 588                 fdirmatch)},
 589         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 590                 fdirmiss)},
 591
 592         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 593         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 594         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 595                 fclast)},
 596         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 597         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 598         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 599         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 600         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 601                 fcoe_noddp)},
 602         {"rx_fcoe_no_direct_data_placement_ext_buff",
 603                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 604
 605         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 606                 lxontxc)},
 607         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 608                 lxonrxc)},
 609         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 610                 lxofftxc)},
 611         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 612                 lxoffrxc)},
 613         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 614 };
 615
 616 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 617                            sizeof(rte_ixgbe_stats_strings[0]))
 618
 619 /* Per-queue statistics */
 620 #define IXBGE_NB_8_PER_Q_STATS (8 * 7)
 621 #define IXBGE_NB_16_PER_Q_STATS (16 * 5)
 622 #define IXGBE_NB_Q_STATS (IXBGE_NB_8_PER_Q_STATS + IXBGE_NB_16_PER_Q_STATS)
 623
 624 #define IXGBE_NB_XSTATS (IXGBE_NB_HW_STATS + IXGBE_NB_Q_STATS)
 625
 626 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 627         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 628 };
 629
 630 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 631                 sizeof(rte_ixgbevf_stats_strings[0]))
 632
 633 /**
 634  * Atomically reads the link status information from global
 635  * structure rte_eth_dev.
 636  *
 637  * @param dev
 638  *   - Pointer to the structure rte_eth_dev to read from.
 639  *   - Pointer to the buffer to be saved with the link status.
 640  *
 641  * @return
 642  *   - On success, zero.
 643  *   - On failure, negative value.
 644  */
 645 static inline int
 646 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 647                                 struct rte_eth_link *link)
 648 {
 649         struct rte_eth_link *dst = link;
 650         struct rte_eth_link *src = &(dev->data->dev_link);
 651
 652         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 653                                         *(uint64_t *)src) == 0)
 654                 return -1;
 655
 656         return 0;
 657 }
 658
 659 /**
 660  * Atomically writes the link status information into global
 661  * structure rte_eth_dev.
 662  *
 663  * @param dev
 664  *   - Pointer to the structure rte_eth_dev to read from.
 665  *   - Pointer to the buffer to be saved with the link status.
 666  *
 667  * @return
 668  *   - On success, zero.
 669  *   - On failure, negative value.
 670  */
 671 static inline int
 672 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 673                                 struct rte_eth_link *link)
 674 {
 675         struct rte_eth_link *dst = &(dev->data->dev_link);
 676         struct rte_eth_link *src = link;
 677
 678         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 679                                         *(uint64_t *)src) == 0)
 680                 return -1;
 681
 682         return 0;
 683 }
 684
 685 /*
 686  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 687  */
 688 static inline int
 689 ixgbe_is_sfp(struct ixgbe_hw *hw)
 690 {
 691         switch (hw->phy.type) {
 692         case ixgbe_phy_sfp_avago:
 693         case ixgbe_phy_sfp_ftl:
 694         case ixgbe_phy_sfp_intel:
 695         case ixgbe_phy_sfp_unknown:
 696         case ixgbe_phy_sfp_passive_tyco:
 697         case ixgbe_phy_sfp_passive_unknown:
 698                 return 1;
 699         default:
 700                 return 0;
 701         }
 702 }
 703
 704 static inline int32_t
 705 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 706 {
 707         uint32_t ctrl_ext;
 708         int32_t status;
 709
 710         status = ixgbe_reset_hw(hw);
 711
 712         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 713         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 714         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 715         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 716         IXGBE_WRITE_FLUSH(hw);
 717
 718         return status;
 719 }
 720
 721 static inline void
 722 ixgbe_enable_intr(struct rte_eth_dev *dev)
 723 {
 724         struct ixgbe_interrupt *intr =
 725                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 726         struct ixgbe_hw *hw =
 727                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 728
 729         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 730         IXGBE_WRITE_FLUSH(hw);
 731 }
 732
 733 /*
 734  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 735  */
 736 static void
 737 ixgbe_disable_intr(struct ixgbe_hw *hw)
 738 {
 739         PMD_INIT_FUNC_TRACE();
 740
 741         if (hw->mac.type == ixgbe_mac_82598EB) {
 742                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 743         } else {
 744                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 745                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 746                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 747         }
 748         IXGBE_WRITE_FLUSH(hw);
 749 }
 750
 751 /*
 752  * This function resets queue statistics mapping registers.
 753  * From Niantic datasheet, Initialization of Statistics section:
 754  * "...if software requires the queue counters, the RQSMR and TQSM registers
 755  * must be re-programmed following a device reset.
 756  */
 757 static void
 758 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 759 {
 760         uint32_t i;
 761
 762         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 763                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 764                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 765         }
 766 }
 767
 768
 769 static int
 770 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 771                                   uint16_t queue_id,
 772                                   uint8_t stat_idx,
 773                                   uint8_t is_rx)
 774 {
 775 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 776 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 777 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 778
 779         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 780         struct ixgbe_stat_mapping_registers *stat_mappings =
 781                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 782         uint32_t qsmr_mask = 0;
 783         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 784         uint32_t q_map;
 785         uint8_t n, offset;
 786
 787         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 788                 (hw->mac.type != ixgbe_mac_X540) &&
 789                 (hw->mac.type != ixgbe_mac_X550) &&
 790                 (hw->mac.type != ixgbe_mac_X550EM_x))
 791                 return -ENOSYS;
 792
 793         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 794                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 795                      queue_id, stat_idx);
 796
 797         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 798         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 799                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 800                 return -EIO;
 801         }
 802         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 803
 804         /* Now clear any previous stat_idx set */
 805         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 806         if (!is_rx)
 807                 stat_mappings->tqsm[n] &= ~clearing_mask;
 808         else
 809                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 810
 811         q_map = (uint32_t)stat_idx;
 812         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 813         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 814         if (!is_rx)
 815                 stat_mappings->tqsm[n] |= qsmr_mask;
 816         else
 817                 stat_mappings->rqsmr[n] |= qsmr_mask;
 818
 819         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 820                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 821                      queue_id, stat_idx);
 822         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 823                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 824
 825         /* Now write the mapping in the appropriate register */
 826         if (is_rx) {
 827                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 828                              stat_mappings->rqsmr[n], n);
 829                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 830         }
 831         else {
 832                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 833                              stat_mappings->tqsm[n], n);
 834                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 835         }
 836         return 0;
 837 }
 838
 839 static void
 840 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 841 {
 842         struct ixgbe_stat_mapping_registers *stat_mappings =
 843                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 844         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 845         int i;
 846
 847         /* write whatever was in stat mapping table to the NIC */
 848         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 849                 /* rx */
 850                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 851
 852                 /* tx */
 853                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 854         }
 855 }
 856
 857 static void
 858 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 859 {
 860         uint8_t i;
 861         struct ixgbe_dcb_tc_config *tc;
 862         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 863
 864         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 865         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 866         for (i = 0; i < dcb_max_tc; i++) {
 867                 tc = &dcb_config->tc_config[i];
 868                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 869                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 870                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 871                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 872                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 873                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 874                 tc->pfc = ixgbe_dcb_pfc_disabled;
 875         }
 876
 877         /* Initialize default user to priority mapping, UPx->TC0 */
 878         tc = &dcb_config->tc_config[0];
 879         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 880         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 881         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 882                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 883                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 884         }
 885         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 886         dcb_config->pfc_mode_enable = false;
 887         dcb_config->vt_mode = true;
 888         dcb_config->round_robin_enable = false;
 889         /* support all DCB capabilities in 82599 */
 890         dcb_config->support.capabilities = 0xFF;
 891
 892         /*we only support 4 Tcs for X540, X550 */
 893         if (hw->mac.type == ixgbe_mac_X540 ||
 894                 hw->mac.type == ixgbe_mac_X550 ||
 895                 hw->mac.type == ixgbe_mac_X550EM_x) {
 896                 dcb_config->num_tcs.pg_tcs = 4;
 897                 dcb_config->num_tcs.pfc_tcs = 4;
 898         }
 899 }
 900
 901 /*
 902  * Ensure that all locks are released before first NVM or PHY access
 903  */
 904 static void
 905 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 906 {
 907         uint16_t mask;
 908
 909         /*
 910          * Phy lock should not fail in this early stage. If this is the case,
 911          * it is due to an improper exit of the application.
 912          * So force the release of the faulty lock. Release of common lock
 913          * is done automatically by swfw_sync function.
 914          */
 915         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 916         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 917                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 918         }
 919         ixgbe_release_swfw_semaphore(hw, mask);
 920
 921         /*
 922          * These ones are more tricky since they are common to all ports; but
 923          * swfw_sync retries last long enough (1s) to be almost sure that if
 924          * lock can not be taken it is due to an improper lock of the
 925          * semaphore.
 926          */
 927         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 928         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 929                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 930         }
 931         ixgbe_release_swfw_semaphore(hw, mask);
 932 }
 933
 934 /*
 935  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
 936  * It returns 0 on success.
 937  */
 938 static int
 939 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
 940 {
 941         struct rte_pci_device *pci_dev;
 942         struct ixgbe_hw *hw =
 943                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 944         struct ixgbe_vfta * shadow_vfta =
 945                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 946         struct ixgbe_hwstrip *hwstrip =
 947                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 948         struct ixgbe_dcb_config *dcb_config =
 949                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 950         struct ixgbe_filter_info *filter_info =
 951                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 952         uint32_t ctrl_ext;
 953         uint16_t csum;
 954         int diag, i;
 955
 956         PMD_INIT_FUNC_TRACE();
 957
 958         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 959         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 960         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 961
 962         /*
 963          * For secondary processes, we don't initialise any further as primary
 964          * has already done this work. Only check we don't need a different
 965          * RX and TX function.
 966          */
 967         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 968                 struct ixgbe_tx_queue *txq;
 969                 /* TX queue function in primary, set by last queue initialized
 970                  * Tx queue may not initialized by primary process */
 971                 if (eth_dev->data->tx_queues) {
 972                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
 973                         ixgbe_set_tx_function(eth_dev, txq);
 974                 } else {
 975                         /* Use default TX function if we get here */
 976                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
 977                                              "Using default TX function.");
 978                 }
 979
 980                 ixgbe_set_rx_function(eth_dev);
 981
 982                 return 0;
 983         }
 984         pci_dev = eth_dev->pci_dev;
 985
 986         rte_eth_copy_pci_info(eth_dev, pci_dev);
 987
 988         /* Vendor and Device ID need to be set before init of shared code */
 989         hw->device_id = pci_dev->id.device_id;
 990         hw->vendor_id = pci_dev->id.vendor_id;
 991         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 992         hw->allow_unsupported_sfp = 1;
 993
 994         /* Initialize the shared code (base driver) */
 995 #ifdef RTE_NIC_BYPASS
 996         diag = ixgbe_bypass_init_shared_code(hw);
 997 #else
 998         diag = ixgbe_init_shared_code(hw);
 999 #endif /* RTE_NIC_BYPASS */
1000
1001         if (diag != IXGBE_SUCCESS) {
1002                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1003                 return -EIO;
1004         }
1005
1006         /* pick up the PCI bus settings for reporting later */
1007         ixgbe_get_bus_info(hw);
1008
1009         /* Unlock any pending hardware semaphore */
1010         ixgbe_swfw_lock_reset(hw);
1011
1012         /* Initialize DCB configuration*/
1013         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1014         ixgbe_dcb_init(hw,dcb_config);
1015         /* Get Hardware Flow Control setting */
1016         hw->fc.requested_mode = ixgbe_fc_full;
1017         hw->fc.current_mode = ixgbe_fc_full;
1018         hw->fc.pause_time = IXGBE_FC_PAUSE;
1019         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1020                 hw->fc.low_water[i] = IXGBE_FC_LO;
1021                 hw->fc.high_water[i] = IXGBE_FC_HI;
1022         }
1023         hw->fc.send_xon = 1;
1024
1025         /* Make sure we have a good EEPROM before we read from it */
1026         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1027         if (diag != IXGBE_SUCCESS) {
1028                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1029                 return -EIO;
1030         }
1031
1032 #ifdef RTE_NIC_BYPASS
1033         diag = ixgbe_bypass_init_hw(hw);
1034 #else
1035         diag = ixgbe_init_hw(hw);
1036 #endif /* RTE_NIC_BYPASS */
1037
1038         /*
1039          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1040          * is called too soon after the kernel driver unbinding/binding occurs.
1041          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1042          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1043          * also called. See ixgbe_identify_phy_82599(). The reason for the
1044          * failure is not known, and only occuts when virtualisation features
1045          * are disabled in the bios. A delay of 100ms  was found to be enough by
1046          * trial-and-error, and is doubled to be safe.
1047          */
1048         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1049                 rte_delay_ms(200);
1050                 diag = ixgbe_init_hw(hw);
1051         }
1052
1053         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1054                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1055                     "LOM.  Please be aware there may be issues associated "
1056                     "with your hardware.");
1057                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1058                     "please contact your Intel or hardware representative "
1059                     "who provided you with this hardware.");
1060         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1061                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1062         if (diag) {
1063                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1064                 return -EIO;
1065         }
1066
1067         /* Reset the hw statistics */
1068         ixgbe_dev_stats_reset(eth_dev);
1069
1070         /* disable interrupt */
1071         ixgbe_disable_intr(hw);
1072
1073         /* reset mappings for queue statistics hw counters*/
1074         ixgbe_reset_qstat_mappings(hw);
1075
1076         /* Allocate memory for storing MAC addresses */
1077         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1078                         hw->mac.num_rar_entries, 0);
1079         if (eth_dev->data->mac_addrs == NULL) {
1080                 PMD_INIT_LOG(ERR,
1081                         "Failed to allocate %u bytes needed to store "
1082                         "MAC addresses",
1083                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1084                 return -ENOMEM;
1085         }
1086         /* Copy the permanent MAC address */
1087         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1088                         &eth_dev->data->mac_addrs[0]);
1089
1090         /* Allocate memory for storing hash filter MAC addresses */
1091         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1092                         IXGBE_VMDQ_NUM_UC_MAC, 0);
1093         if (eth_dev->data->hash_mac_addrs == NULL) {
1094                 PMD_INIT_LOG(ERR,
1095                         "Failed to allocate %d bytes needed to store MAC addresses",
1096                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1097                 return -ENOMEM;
1098         }
1099
1100         /* initialize the vfta */
1101         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1102
1103         /* initialize the hw strip bitmap*/
1104         memset(hwstrip, 0, sizeof(*hwstrip));
1105
1106         /* initialize PF if max_vfs not zero */
1107         ixgbe_pf_host_init(eth_dev);
1108
1109         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1110         /* let hardware know driver is loaded */
1111         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1112         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1113         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1114         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1115         IXGBE_WRITE_FLUSH(hw);
1116
1117         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1118                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1119                              (int) hw->mac.type, (int) hw->phy.type,
1120                              (int) hw->phy.sfp_type);
1121         else
1122                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1123                              (int) hw->mac.type, (int) hw->phy.type);
1124
1125         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1126                         eth_dev->data->port_id, pci_dev->id.vendor_id,
1127                         pci_dev->id.device_id);
1128
1129         /* enable support intr */
1130         ixgbe_enable_intr(eth_dev);
1131
1132         /* initialize 5tuple filter list */
1133         TAILQ_INIT(&filter_info->fivetuple_list);
1134         memset(filter_info->fivetuple_mask, 0,
1135                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1136
1137         return 0;
1138 }
1139
1140 static int
1141 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1142 {
1143         struct rte_pci_device *pci_dev;
1144         struct ixgbe_hw *hw;
1145
1146         PMD_INIT_FUNC_TRACE();
1147
1148         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1149                 return -EPERM;
1150
1151         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1152         pci_dev = eth_dev->pci_dev;
1153
1154         if (hw->adapter_stopped == 0)
1155                 ixgbe_dev_close(eth_dev);
1156
1157         eth_dev->dev_ops = NULL;
1158         eth_dev->rx_pkt_burst = NULL;
1159         eth_dev->tx_pkt_burst = NULL;
1160
1161         /* Unlock any pending hardware semaphore */
1162         ixgbe_swfw_lock_reset(hw);
1163
1164         /* disable uio intr before callback unregister */
1165         rte_intr_disable(&(pci_dev->intr_handle));
1166         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1167                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1168
1169         /* uninitialize PF if max_vfs not zero */
1170         ixgbe_pf_host_uninit(eth_dev);
1171
1172         rte_free(eth_dev->data->mac_addrs);
1173         eth_dev->data->mac_addrs = NULL;
1174
1175         rte_free(eth_dev->data->hash_mac_addrs);
1176         eth_dev->data->hash_mac_addrs = NULL;
1177
1178         return 0;
1179 }
1180
1181 /*
1182  * Negotiate mailbox API version with the PF.
1183  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1184  * Then we try to negotiate starting with the most recent one.
1185  * If all negotiation attempts fail, then we will proceed with
1186  * the default one (ixgbe_mbox_api_10).
1187  */
1188 static void
1189 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1190 {
1191         int32_t i;
1192
1193         /* start with highest supported, proceed down */
1194         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1195                 ixgbe_mbox_api_11,
1196                 ixgbe_mbox_api_10,
1197         };
1198
1199         for (i = 0;
1200                         i != RTE_DIM(sup_ver) &&
1201                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1202                         i++)
1203                 ;
1204 }
1205
1206 static void
1207 generate_random_mac_addr(struct ether_addr *mac_addr)
1208 {
1209         uint64_t random;
1210
1211         /* Set Organizationally Unique Identifier (OUI) prefix. */
1212         mac_addr->addr_bytes[0] = 0x00;
1213         mac_addr->addr_bytes[1] = 0x09;
1214         mac_addr->addr_bytes[2] = 0xC0;
1215         /* Force indication of locally assigned MAC address. */
1216         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1217         /* Generate the last 3 bytes of the MAC address with a random number. */
1218         random = rte_rand();
1219         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1220 }
1221
1222 /*
1223  * Virtual Function device init
1224  */
1225 static int
1226 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1227 {
1228         int diag;
1229         uint32_t tc, tcs;
1230         struct rte_pci_device *pci_dev;
1231         struct ixgbe_hw *hw =
1232                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1233         struct ixgbe_vfta * shadow_vfta =
1234                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1235         struct ixgbe_hwstrip *hwstrip =
1236                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1237         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1238
1239         PMD_INIT_FUNC_TRACE();
1240
1241         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1242         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1243         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1244
1245         /* for secondary processes, we don't initialise any further as primary
1246          * has already done this work. Only check we don't need a different
1247          * RX function */
1248         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1249                 if (eth_dev->data->scattered_rx)
1250                         eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
1251                 return 0;
1252         }
1253
1254         pci_dev = eth_dev->pci_dev;
1255
1256         rte_eth_copy_pci_info(eth_dev, pci_dev);
1257
1258         hw->device_id = pci_dev->id.device_id;
1259         hw->vendor_id = pci_dev->id.vendor_id;
1260         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1261
1262         /* initialize the vfta */
1263         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1264
1265         /* initialize the hw strip bitmap*/
1266         memset(hwstrip, 0, sizeof(*hwstrip));
1267
1268         /* Initialize the shared code (base driver) */
1269         diag = ixgbe_init_shared_code(hw);
1270         if (diag != IXGBE_SUCCESS) {
1271                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1272                 return -EIO;
1273         }
1274
1275         /* init_mailbox_params */
1276         hw->mbx.ops.init_params(hw);
1277
1278         /* Reset the hw statistics */
1279         ixgbevf_dev_stats_reset(eth_dev);
1280
1281         /* Disable the interrupts for VF */
1282         ixgbevf_intr_disable(hw);
1283
1284         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1285         diag = hw->mac.ops.reset_hw(hw);
1286
1287         /*
1288          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1289          * the underlying PF driver has not assigned a MAC address to the VF.
1290          * In this case, assign a random MAC address.
1291          */
1292         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1293                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1294                 return (diag);
1295         }
1296
1297         /* negotiate mailbox API version to use with the PF. */
1298         ixgbevf_negotiate_api(hw);
1299
1300         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1301         ixgbevf_get_queues(hw, &tcs, &tc);
1302
1303         /* Allocate memory for storing MAC addresses */
1304         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1305                         hw->mac.num_rar_entries, 0);
1306         if (eth_dev->data->mac_addrs == NULL) {
1307                 PMD_INIT_LOG(ERR,
1308                         "Failed to allocate %u bytes needed to store "
1309                         "MAC addresses",
1310                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1311                 return -ENOMEM;
1312         }
1313
1314         /* Generate a random MAC address, if none was assigned by PF. */
1315         if (is_zero_ether_addr(perm_addr)) {
1316                 generate_random_mac_addr(perm_addr);
1317                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1318                 if (diag) {
1319                         rte_free(eth_dev->data->mac_addrs);
1320                         eth_dev->data->mac_addrs = NULL;
1321                         return diag;
1322                 }
1323                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1324                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1325                              "%02x:%02x:%02x:%02x:%02x:%02x",
1326                              perm_addr->addr_bytes[0],
1327                              perm_addr->addr_bytes[1],
1328                              perm_addr->addr_bytes[2],
1329                              perm_addr->addr_bytes[3],
1330                              perm_addr->addr_bytes[4],
1331                              perm_addr->addr_bytes[5]);
1332         }
1333
1334         /* Copy the permanent MAC address */
1335         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1336
1337         /* reset the hardware with the new settings */
1338         diag = hw->mac.ops.start_hw(hw);
1339         switch (diag) {
1340                 case  0:
1341                         break;
1342
1343                 default:
1344                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1345                         return (-EIO);
1346         }
1347
1348         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1349                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1350                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1351
1352         return 0;
1353 }
1354
1355 /* Virtual Function device uninit */
1356
1357 static int
1358 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1359 {
1360         struct ixgbe_hw *hw;
1361         unsigned i;
1362
1363         PMD_INIT_FUNC_TRACE();
1364
1365         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1366                 return -EPERM;
1367
1368         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1369
1370         if (hw->adapter_stopped == 0)
1371                 ixgbevf_dev_close(eth_dev);
1372
1373         eth_dev->dev_ops = NULL;
1374         eth_dev->rx_pkt_burst = NULL;
1375         eth_dev->tx_pkt_burst = NULL;
1376
1377         /* Disable the interrupts for VF */
1378         ixgbevf_intr_disable(hw);
1379
1380         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1381                 ixgbe_dev_rx_queue_release(eth_dev->data->rx_queues[i]);
1382                 eth_dev->data->rx_queues[i] = NULL;
1383         }
1384         eth_dev->data->nb_rx_queues = 0;
1385
1386         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1387                 ixgbe_dev_tx_queue_release(eth_dev->data->tx_queues[i]);
1388                 eth_dev->data->tx_queues[i] = NULL;
1389         }
1390         eth_dev->data->nb_tx_queues = 0;
1391
1392         rte_free(eth_dev->data->mac_addrs);
1393         eth_dev->data->mac_addrs = NULL;
1394
1395         return 0;
1396 }
1397
1398 static struct eth_driver rte_ixgbe_pmd = {
1399         .pci_drv = {
1400                 .name = "rte_ixgbe_pmd",
1401                 .id_table = pci_id_ixgbe_map,
1402                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1403                         RTE_PCI_DRV_DETACHABLE,
1404         },
1405         .eth_dev_init = eth_ixgbe_dev_init,
1406         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1407         .dev_private_size = sizeof(struct ixgbe_adapter),
1408 };
1409
1410 /*
1411  * virtual function driver struct
1412  */
1413 static struct eth_driver rte_ixgbevf_pmd = {
1414         .pci_drv = {
1415                 .name = "rte_ixgbevf_pmd",
1416                 .id_table = pci_id_ixgbevf_map,
1417                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1418         },
1419         .eth_dev_init = eth_ixgbevf_dev_init,
1420         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1421         .dev_private_size = sizeof(struct ixgbe_adapter),
1422 };
1423
1424 /*
1425  * Driver initialization routine.
1426  * Invoked once at EAL init time.
1427  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1428  */
1429 static int
1430 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1431 {
1432         PMD_INIT_FUNC_TRACE();
1433
1434         rte_eth_driver_register(&rte_ixgbe_pmd);
1435         return 0;
1436 }
1437
1438 /*
1439  * VF Driver initialization routine.
1440  * Invoked one at EAL init time.
1441  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1442  */
1443 static int
1444 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1445 {
1446         PMD_INIT_FUNC_TRACE();
1447
1448         rte_eth_driver_register(&rte_ixgbevf_pmd);
1449         return (0);
1450 }
1451
1452 static int
1453 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1454 {
1455         struct ixgbe_hw *hw =
1456                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1457         struct ixgbe_vfta * shadow_vfta =
1458                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1459         uint32_t vfta;
1460         uint32_t vid_idx;
1461         uint32_t vid_bit;
1462
1463         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1464         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1465         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1466         if (on)
1467                 vfta |= vid_bit;
1468         else
1469                 vfta &= ~vid_bit;
1470         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1471
1472         /* update local VFTA copy */
1473         shadow_vfta->vfta[vid_idx] = vfta;
1474
1475         return 0;
1476 }
1477
1478 static void
1479 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1480 {
1481         if (on)
1482                 ixgbe_vlan_hw_strip_enable(dev, queue);
1483         else
1484                 ixgbe_vlan_hw_strip_disable(dev, queue);
1485 }
1486
1487 static void
1488 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1489 {
1490         struct ixgbe_hw *hw =
1491                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1492
1493         /* Only the high 16-bits is valid */
1494         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1495 }
1496
1497 void
1498 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1499 {
1500         struct ixgbe_hw *hw =
1501                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1502         uint32_t vlnctrl;
1503
1504         PMD_INIT_FUNC_TRACE();
1505
1506         /* Filter Table Disable */
1507         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1508         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1509
1510         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1511 }
1512
1513 void
1514 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1515 {
1516         struct ixgbe_hw *hw =
1517                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1518         struct ixgbe_vfta * shadow_vfta =
1519                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1520         uint32_t vlnctrl;
1521         uint16_t i;
1522
1523         PMD_INIT_FUNC_TRACE();
1524
1525         /* Filter Table Enable */
1526         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1527         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1528         vlnctrl |= IXGBE_VLNCTRL_VFE;
1529
1530         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1531
1532         /* write whatever is in local vfta copy */
1533         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1534                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1535 }
1536
1537 static void
1538 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1539 {
1540         struct ixgbe_hwstrip *hwstrip =
1541                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1542
1543         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1544                 return;
1545
1546         if (on)
1547                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1548         else
1549                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1550 }
1551
1552 static void
1553 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1554 {
1555         struct ixgbe_hw *hw =
1556                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1557         uint32_t ctrl;
1558
1559         PMD_INIT_FUNC_TRACE();
1560
1561         if (hw->mac.type == ixgbe_mac_82598EB) {
1562                 /* No queue level support */
1563                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1564                 return;
1565         }
1566         else {
1567                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1568                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1569                 ctrl &= ~IXGBE_RXDCTL_VME;
1570                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1571         }
1572         /* record those setting for HW strip per queue */
1573         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1574 }
1575
1576 static void
1577 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1578 {
1579         struct ixgbe_hw *hw =
1580                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1581         uint32_t ctrl;
1582
1583         PMD_INIT_FUNC_TRACE();
1584
1585         if (hw->mac.type == ixgbe_mac_82598EB) {
1586                 /* No queue level supported */
1587                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1588                 return;
1589         }
1590         else {
1591                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1592                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1593                 ctrl |= IXGBE_RXDCTL_VME;
1594                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1595         }
1596         /* record those setting for HW strip per queue */
1597         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1598 }
1599
1600 void
1601 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1602 {
1603         struct ixgbe_hw *hw =
1604                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1605         uint32_t ctrl;
1606         uint16_t i;
1607
1608         PMD_INIT_FUNC_TRACE();
1609
1610         if (hw->mac.type == ixgbe_mac_82598EB) {
1611                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1612                 ctrl &= ~IXGBE_VLNCTRL_VME;
1613                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1614         }
1615         else {
1616                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1617                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1618                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1619                         ctrl &= ~IXGBE_RXDCTL_VME;
1620                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1621
1622                         /* record those setting for HW strip per queue */
1623                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1624                 }
1625         }
1626 }
1627
1628 void
1629 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1630 {
1631         struct ixgbe_hw *hw =
1632                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1633         uint32_t ctrl;
1634         uint16_t i;
1635
1636         PMD_INIT_FUNC_TRACE();
1637
1638         if (hw->mac.type == ixgbe_mac_82598EB) {
1639                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1640                 ctrl |= IXGBE_VLNCTRL_VME;
1641                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1642         }
1643         else {
1644                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1645                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1646                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1647                         ctrl |= IXGBE_RXDCTL_VME;
1648                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1649
1650                         /* record those setting for HW strip per queue */
1651                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1652                 }
1653         }
1654 }
1655
1656 static void
1657 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1658 {
1659         struct ixgbe_hw *hw =
1660                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1661         uint32_t ctrl;
1662
1663         PMD_INIT_FUNC_TRACE();
1664
1665         /* DMATXCTRL: Geric Double VLAN Disable */
1666         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1667         ctrl &= ~IXGBE_DMATXCTL_GDV;
1668         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1669
1670         /* CTRL_EXT: Global Double VLAN Disable */
1671         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1672         ctrl &= ~IXGBE_EXTENDED_VLAN;
1673         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1674
1675 }
1676
1677 static void
1678 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1679 {
1680         struct ixgbe_hw *hw =
1681                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1682         uint32_t ctrl;
1683
1684         PMD_INIT_FUNC_TRACE();
1685
1686         /* DMATXCTRL: Geric Double VLAN Enable */
1687         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1688         ctrl |= IXGBE_DMATXCTL_GDV;
1689         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1690
1691         /* CTRL_EXT: Global Double VLAN Enable */
1692         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1693         ctrl |= IXGBE_EXTENDED_VLAN;
1694         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1695
1696         /*
1697          * VET EXT field in the EXVET register = 0x8100 by default
1698          * So no need to change. Same to VT field of DMATXCTL register
1699          */
1700 }
1701
1702 static void
1703 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1704 {
1705         if(mask & ETH_VLAN_STRIP_MASK){
1706                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1707                         ixgbe_vlan_hw_strip_enable_all(dev);
1708                 else
1709                         ixgbe_vlan_hw_strip_disable_all(dev);
1710         }
1711
1712         if(mask & ETH_VLAN_FILTER_MASK){
1713                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1714                         ixgbe_vlan_hw_filter_enable(dev);
1715                 else
1716                         ixgbe_vlan_hw_filter_disable(dev);
1717         }
1718
1719         if(mask & ETH_VLAN_EXTEND_MASK){
1720                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1721                         ixgbe_vlan_hw_extend_enable(dev);
1722                 else
1723                         ixgbe_vlan_hw_extend_disable(dev);
1724         }
1725 }
1726
1727 static void
1728 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1729 {
1730         struct ixgbe_hw *hw =
1731                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1732         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1733         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1734         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1735         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1736 }
1737
1738 static int
1739 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1740 {
1741         switch (nb_rx_q) {
1742         case 1:
1743         case 2:
1744                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1745                 break;
1746         case 4:
1747                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1748                 break;
1749         default:
1750                 return -EINVAL;
1751         }
1752
1753         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1754         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1755
1756         return 0;
1757 }
1758
1759 static int
1760 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1761 {
1762         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1763         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1764         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1765
1766         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1767                 /* check multi-queue mode */
1768                 switch (dev_conf->rxmode.mq_mode) {
1769                 case ETH_MQ_RX_VMDQ_DCB:
1770                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1771                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1772                         PMD_INIT_LOG(ERR, "SRIOV active,"
1773                                         " unsupported mq_mode rx %d.",
1774                                         dev_conf->rxmode.mq_mode);
1775                         return -EINVAL;
1776                 case ETH_MQ_RX_RSS:
1777                 case ETH_MQ_RX_VMDQ_RSS:
1778                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1779                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1780                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1781                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1782                                                 " invalid queue number"
1783                                                 " for VMDQ RSS, allowed"
1784                                                 " value are 1, 2 or 4.");
1785                                         return -EINVAL;
1786                                 }
1787                         break;
1788                 case ETH_MQ_RX_VMDQ_ONLY:
1789                 case ETH_MQ_RX_NONE:
1790                         /* if nothing mq mode configure, use default scheme */
1791                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1792                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1793                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1794                         break;
1795                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1796                         /* SRIOV only works in VMDq enable mode */
1797                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1798                                         " wrong mq_mode rx %d.",
1799                                         dev_conf->rxmode.mq_mode);
1800                         return -EINVAL;
1801                 }
1802
1803                 switch (dev_conf->txmode.mq_mode) {
1804                 case ETH_MQ_TX_VMDQ_DCB:
1805                         /* DCB VMDQ in SRIOV mode, not implement yet */
1806                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1807                                         " unsupported VMDQ mq_mode tx %d.",
1808                                         dev_conf->txmode.mq_mode);
1809                         return -EINVAL;
1810                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1811                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1812                         break;
1813                 }
1814
1815                 /* check valid queue number */
1816                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1817                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1818                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1819                                         " queue number must less equal to %d.",
1820                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1821                         return -EINVAL;
1822                 }
1823         } else {
1824                 /* check configuration for vmdb+dcb mode */
1825                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1826                         const struct rte_eth_vmdq_dcb_conf *conf;
1827
1828                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1829                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1830                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
1831                                 return -EINVAL;
1832                         }
1833                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1834                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1835                                conf->nb_queue_pools == ETH_32_POOLS)) {
1836                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1837                                                 " nb_queue_pools must be %d or %d.",
1838                                                 ETH_16_POOLS, ETH_32_POOLS);
1839                                 return -EINVAL;
1840                         }
1841                 }
1842                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1843                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1844
1845                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1846                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1847                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
1848                                 return -EINVAL;
1849                         }
1850                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1851                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1852                                conf->nb_queue_pools == ETH_32_POOLS)) {
1853                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1854                                                 " nb_queue_pools != %d and"
1855                                                 " nb_queue_pools != %d.",
1856                                                 ETH_16_POOLS, ETH_32_POOLS);
1857                                 return -EINVAL;
1858                         }
1859                 }
1860
1861                 /* For DCB mode check our configuration before we go further */
1862                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1863                         const struct rte_eth_dcb_rx_conf *conf;
1864
1865                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1866                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1867                                                  IXGBE_DCB_NB_QUEUES);
1868                                 return -EINVAL;
1869                         }
1870                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1871                         if (!(conf->nb_tcs == ETH_4_TCS ||
1872                                conf->nb_tcs == ETH_8_TCS)) {
1873                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1874                                                 " and nb_tcs != %d.",
1875                                                 ETH_4_TCS, ETH_8_TCS);
1876                                 return -EINVAL;
1877                         }
1878                 }
1879
1880                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1881                         const struct rte_eth_dcb_tx_conf *conf;
1882
1883                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
1884                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
1885                                                  IXGBE_DCB_NB_QUEUES);
1886                                 return -EINVAL;
1887                         }
1888                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1889                         if (!(conf->nb_tcs == ETH_4_TCS ||
1890                                conf->nb_tcs == ETH_8_TCS)) {
1891                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1892                                                 " and nb_tcs != %d.",
1893                                                 ETH_4_TCS, ETH_8_TCS);
1894                                 return -EINVAL;
1895                         }
1896                 }
1897         }
1898         return 0;
1899 }
1900
1901 static int
1902 ixgbe_dev_configure(struct rte_eth_dev *dev)
1903 {
1904         struct ixgbe_interrupt *intr =
1905                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1906         struct ixgbe_adapter *adapter =
1907                 (struct ixgbe_adapter *)dev->data->dev_private;
1908         int ret;
1909
1910         PMD_INIT_FUNC_TRACE();
1911         /* multipe queue mode checking */
1912         ret  = ixgbe_check_mq_mode(dev);
1913         if (ret != 0) {
1914                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
1915                             ret);
1916                 return ret;
1917         }
1918
1919         /* set flag to update link status after init */
1920         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1921
1922         /*
1923          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1924          * allocation or vector Rx preconditions we will reset it.
1925          */
1926         adapter->rx_bulk_alloc_allowed = true;
1927         adapter->rx_vec_allowed = true;
1928
1929         return 0;
1930 }
1931
1932 /*
1933  * Configure device link speed and setup link.
1934  * It returns 0 on success.
1935  */
1936 static int
1937 ixgbe_dev_start(struct rte_eth_dev *dev)
1938 {
1939         struct ixgbe_hw *hw =
1940                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1941         struct ixgbe_vf_info *vfinfo =
1942                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1943         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1944         uint32_t intr_vector = 0;
1945         int err, link_up = 0, negotiate = 0;
1946         uint32_t speed = 0;
1947         int mask = 0;
1948         int status;
1949         uint16_t vf, idx;
1950
1951         PMD_INIT_FUNC_TRACE();
1952
1953         /* IXGBE devices don't support half duplex */
1954         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1955                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1956                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1957                              dev->data->dev_conf.link_duplex,
1958                              dev->data->port_id);
1959                 return -EINVAL;
1960         }
1961
1962         /* stop adapter */
1963         hw->adapter_stopped = 0;
1964         ixgbe_stop_adapter(hw);
1965
1966         /* reinitialize adapter
1967          * this calls reset and start */
1968         status = ixgbe_pf_reset_hw(hw);
1969         if (status != 0)
1970                 return -1;
1971         hw->mac.ops.start_hw(hw);
1972         hw->mac.get_link_status = true;
1973
1974         /* configure PF module if SRIOV enabled */
1975         ixgbe_pf_host_configure(dev);
1976
1977         /* check and configure queue intr-vector mapping */
1978         if (dev->data->dev_conf.intr_conf.rxq != 0)
1979                 intr_vector = dev->data->nb_rx_queues;
1980
1981         if (rte_intr_efd_enable(intr_handle, intr_vector))
1982                 return -1;
1983
1984         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1985                 intr_handle->intr_vec =
1986                         rte_zmalloc("intr_vec",
1987                                     dev->data->nb_rx_queues * sizeof(int),
1988                                     0);
1989                 if (intr_handle->intr_vec == NULL) {
1990                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1991                                      " intr_vec\n", dev->data->nb_rx_queues);
1992                         return -ENOMEM;
1993                 }
1994         }
1995
1996         /* confiugre msix for sleep until rx interrupt */
1997         ixgbe_configure_msix(dev);
1998
1999         /* initialize transmission unit */
2000         ixgbe_dev_tx_init(dev);
2001
2002         /* This can fail when allocating mbufs for descriptor rings */
2003         err = ixgbe_dev_rx_init(dev);
2004         if (err) {
2005                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2006                 goto error;
2007         }
2008
2009         err = ixgbe_dev_rxtx_start(dev);
2010         if (err < 0) {
2011                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2012                 goto error;
2013         }
2014
2015         /* Skip link setup if loopback mode is enabled for 82599. */
2016         if (hw->mac.type == ixgbe_mac_82599EB &&
2017                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2018                 goto skip_link_setup;
2019
2020         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2021                 err = hw->mac.ops.setup_sfp(hw);
2022                 if (err)
2023                         goto error;
2024         }
2025
2026         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2027                 /* Turn on the copper */
2028                 ixgbe_set_phy_power(hw, true);
2029         } else {
2030                 /* Turn on the laser */
2031                 ixgbe_enable_tx_laser(hw);
2032         }
2033
2034         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2035         if (err)
2036                 goto error;
2037         dev->data->dev_link.link_status = link_up;
2038
2039         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2040         if (err)
2041                 goto error;
2042
2043         switch(dev->data->dev_conf.link_speed) {
2044         case ETH_LINK_SPEED_AUTONEG:
2045                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2046                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2047                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2048                 break;
2049         case ETH_LINK_SPEED_100:
2050                 /*
2051                  * Invalid for 82598 but error will be detected by
2052                  * ixgbe_setup_link()
2053                  */
2054                 speed = IXGBE_LINK_SPEED_100_FULL;
2055                 break;
2056         case ETH_LINK_SPEED_1000:
2057                 speed = IXGBE_LINK_SPEED_1GB_FULL;
2058                 break;
2059         case ETH_LINK_SPEED_10000:
2060                 speed = IXGBE_LINK_SPEED_10GB_FULL;
2061                 break;
2062         default:
2063                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
2064                              dev->data->dev_conf.link_speed,
2065                              dev->data->port_id);
2066                 goto error;
2067         }
2068
2069         err = ixgbe_setup_link(hw, speed, link_up);
2070         if (err)
2071                 goto error;
2072
2073 skip_link_setup:
2074
2075         /* check if lsc interrupt is enabled */
2076         if (dev->data->dev_conf.intr_conf.lsc != 0) {
2077                 if (rte_intr_allow_others(intr_handle)) {
2078                         rte_intr_callback_register(intr_handle,
2079                                                    ixgbe_dev_interrupt_handler,
2080                                                    (void *)dev);
2081                         ixgbe_dev_lsc_interrupt_setup(dev);
2082                 } else
2083                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2084                                      " no intr multiplex\n");
2085         }
2086
2087         /* check if rxq interrupt is enabled */
2088         if (dev->data->dev_conf.intr_conf.rxq != 0)
2089                 ixgbe_dev_rxq_interrupt_setup(dev);
2090
2091         /* enable uio/vfio intr/eventfd mapping */
2092         rte_intr_enable(intr_handle);
2093
2094         /* resume enabled intr since hw reset */
2095         ixgbe_enable_intr(dev);
2096
2097         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2098                 ETH_VLAN_EXTEND_MASK;
2099         ixgbe_vlan_offload_set(dev, mask);
2100
2101         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2102                 /* Enable vlan filtering for VMDq */
2103                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2104         }
2105
2106         /* Configure DCB hw */
2107         ixgbe_configure_dcb(dev);
2108
2109         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2110                 err = ixgbe_fdir_configure(dev);
2111                 if (err)
2112                         goto error;
2113         }
2114
2115         /* Restore vf rate limit */
2116         if (vfinfo != NULL) {
2117                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2118                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2119                                 if (vfinfo[vf].tx_rate[idx] != 0)
2120                                         ixgbe_set_vf_rate_limit(dev, vf,
2121                                                 vfinfo[vf].tx_rate[idx],
2122                                                 1 << idx);
2123         }
2124
2125         ixgbe_restore_statistics_mapping(dev);
2126
2127         return (0);
2128
2129 error:
2130         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2131         ixgbe_dev_clear_queues(dev);
2132         return -EIO;
2133 }
2134
2135 /*
2136  * Stop device: disable rx and tx functions to allow for reconfiguring.
2137  */
2138 static void
2139 ixgbe_dev_stop(struct rte_eth_dev *dev)
2140 {
2141         struct rte_eth_link link;
2142         struct ixgbe_hw *hw =
2143                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2144         struct ixgbe_vf_info *vfinfo =
2145                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2146         struct ixgbe_filter_info *filter_info =
2147                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2148         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2149         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2150         int vf;
2151
2152         PMD_INIT_FUNC_TRACE();
2153
2154         /* disable interrupts */
2155         ixgbe_disable_intr(hw);
2156
2157         /* disable intr eventfd mapping */
2158         rte_intr_disable(intr_handle);
2159
2160         /* reset the NIC */
2161         ixgbe_pf_reset_hw(hw);
2162         hw->adapter_stopped = 0;
2163
2164         /* stop adapter */
2165         ixgbe_stop_adapter(hw);
2166
2167         for (vf = 0; vfinfo != NULL &&
2168                      vf < dev->pci_dev->max_vfs; vf++)
2169                 vfinfo[vf].clear_to_send = false;
2170
2171         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2172                 /* Turn off the copper */
2173                 ixgbe_set_phy_power(hw, false);
2174         } else {
2175                 /* Turn off the laser */
2176                 ixgbe_disable_tx_laser(hw);
2177         }
2178
2179         ixgbe_dev_clear_queues(dev);
2180
2181         /* Clear stored conf */
2182         dev->data->scattered_rx = 0;
2183         dev->data->lro = 0;
2184
2185         /* Clear recorded link status */
2186         memset(&link, 0, sizeof(link));
2187         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2188
2189         /* Remove all ntuple filters of the device */
2190         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2191              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2192                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2193                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2194                              p_5tuple, entries);
2195                 rte_free(p_5tuple);
2196         }
2197         memset(filter_info->fivetuple_mask, 0,
2198                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2199
2200         /* Clean datapath event and queue/vec mapping */
2201         rte_intr_efd_disable(intr_handle);
2202         if (intr_handle->intr_vec != NULL) {
2203                 rte_free(intr_handle->intr_vec);
2204                 intr_handle->intr_vec = NULL;
2205         }
2206 }
2207
2208 /*
2209  * Set device link up: enable tx.
2210  */
2211 static int
2212 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2213 {
2214         struct ixgbe_hw *hw =
2215                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2216         if (hw->mac.type == ixgbe_mac_82599EB) {
2217 #ifdef RTE_NIC_BYPASS
2218                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2219                         /* Not suported in bypass mode */
2220                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2221                                      "by device id 0x%x", hw->device_id);
2222                         return -ENOTSUP;
2223                 }
2224 #endif
2225         }
2226
2227         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2228                 /* Turn on the copper */
2229                 ixgbe_set_phy_power(hw, true);
2230         } else {
2231                 /* Turn on the laser */
2232                 ixgbe_enable_tx_laser(hw);
2233         }
2234
2235         return 0;
2236 }
2237
2238 /*
2239  * Set device link down: disable tx.
2240  */
2241 static int
2242 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2243 {
2244         struct ixgbe_hw *hw =
2245                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2246         if (hw->mac.type == ixgbe_mac_82599EB) {
2247 #ifdef RTE_NIC_BYPASS
2248                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2249                         /* Not suported in bypass mode */
2250                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2251                                      "by device id 0x%x", hw->device_id);
2252                         return -ENOTSUP;
2253                 }
2254 #endif
2255         }
2256
2257         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2258                 /* Turn off the copper */
2259                 ixgbe_set_phy_power(hw, false);
2260         } else {
2261                 /* Turn off the laser */
2262                 ixgbe_disable_tx_laser(hw);
2263         }
2264
2265         return 0;
2266 }
2267
2268 /*
2269  * Reest and stop device.
2270  */
2271 static void
2272 ixgbe_dev_close(struct rte_eth_dev *dev)
2273 {
2274         struct ixgbe_hw *hw =
2275                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2276
2277         PMD_INIT_FUNC_TRACE();
2278
2279         ixgbe_pf_reset_hw(hw);
2280
2281         ixgbe_dev_stop(dev);
2282         hw->adapter_stopped = 1;
2283
2284         ixgbe_dev_free_queues(dev);
2285
2286         ixgbe_disable_pcie_master(hw);
2287
2288         /* reprogram the RAR[0] in case user changed it. */
2289         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2290 }
2291
2292 static void
2293 ixgbe_read_stats_registers(struct ixgbe_hw *hw, struct ixgbe_hw_stats
2294                                                    *hw_stats, uint64_t *total_missed_rx,
2295                                                    uint64_t *total_qbrc, uint64_t *total_qprc,
2296                                                    uint64_t *total_qprdc)
2297 {
2298         uint32_t bprc, lxon, lxoff, total;
2299         unsigned i;
2300
2301         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2302         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2303         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2304         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2305
2306         for (i = 0; i < 8; i++) {
2307                 uint32_t mp;
2308                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2309                 /* global total per queue */
2310                 hw_stats->mpc[i] += mp;
2311                 /* Running comprehensive total for stats display */
2312                 *total_missed_rx += hw_stats->mpc[i];
2313                 if (hw->mac.type == ixgbe_mac_82598EB) {
2314                         hw_stats->rnbc[i] +=
2315                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2316                         hw_stats->pxonrxc[i] +=
2317                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2318                         hw_stats->pxoffrxc[i] +=
2319                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2320                 } else {
2321                         hw_stats->pxonrxc[i] +=
2322                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2323                         hw_stats->pxoffrxc[i] +=
2324                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2325                         hw_stats->pxon2offc[i] +=
2326                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2327                 }
2328                 hw_stats->pxontxc[i] +=
2329                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2330                 hw_stats->pxofftxc[i] +=
2331                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2332         }
2333         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2334                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2335                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2336                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2337                 hw_stats->qbrc[i] +=
2338                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2339                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2340                 hw_stats->qbtc[i] +=
2341                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2342                 *total_qprdc += hw_stats->qprdc[i] +=
2343                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2344
2345                 *total_qprc += hw_stats->qprc[i];
2346                 *total_qbrc += hw_stats->qbrc[i];
2347         }
2348         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2349         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2350         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2351
2352         /* Note that gprc counts missed packets */
2353         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
2354
2355         if (hw->mac.type != ixgbe_mac_82598EB) {
2356                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2357                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2358                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2359                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2360                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2361                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2362                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2363                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2364         } else {
2365                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2366                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2367                 /* 82598 only has a counter in the high register */
2368                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2369                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2370                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2371         }
2372
2373         /*
2374          * Workaround: mprc hardware is incorrectly counting
2375          * broadcasts, so for now we subtract those.
2376          */
2377         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2378         hw_stats->bprc += bprc;
2379         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2380         if (hw->mac.type == ixgbe_mac_82598EB)
2381                 hw_stats->mprc -= bprc;
2382
2383         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2384         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2385         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2386         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2387         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2388         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2389
2390         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2391         hw_stats->lxontxc += lxon;
2392         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2393         hw_stats->lxofftxc += lxoff;
2394         total = lxon + lxoff;
2395
2396         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
2397         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2398         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2399         hw_stats->gptc -= total;
2400         hw_stats->mptc -= total;
2401         hw_stats->ptc64 -= total;
2402         hw_stats->gotc -= total * ETHER_MIN_LEN;
2403
2404         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2405         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2406         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2407         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2408         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2409         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2410         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2411         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2412         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2413         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2414         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2415         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2416         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2417         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2418         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2419         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2420         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2421         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2422         /* Only read FCOE on 82599 */
2423         if (hw->mac.type != ixgbe_mac_82598EB) {
2424                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2425                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2426                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2427                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2428                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2429         }
2430
2431         /* Flow Director Stats registers */
2432         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2433         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2434 }
2435
2436 /*
2437  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2438  */
2439 static void
2440 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2441 {
2442         struct ixgbe_hw *hw =
2443                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2444         struct ixgbe_hw_stats *hw_stats =
2445                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2446         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2447         unsigned i;
2448
2449         total_missed_rx = 0;
2450         total_qbrc = 0;
2451         total_qprc = 0;
2452         total_qprdc = 0;
2453
2454         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2455                         &total_qprc, &total_qprdc);
2456
2457         if (stats == NULL)
2458                 return;
2459
2460         /* Fill out the rte_eth_stats statistics structure */
2461         stats->ipackets = total_qprc;
2462         stats->ibytes = total_qbrc;
2463         stats->opackets = hw_stats->gptc;
2464         stats->obytes = hw_stats->gotc;
2465
2466         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2467                 stats->q_ipackets[i] = hw_stats->qprc[i];
2468                 stats->q_opackets[i] = hw_stats->qptc[i];
2469                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2470                 stats->q_obytes[i] = hw_stats->qbtc[i];
2471                 stats->q_errors[i] = hw_stats->qprdc[i];
2472         }
2473
2474         /* Rx Errors */
2475         stats->ierrors  = hw_stats->crcerrs +
2476                           hw_stats->mspdc +
2477                           hw_stats->rlec +
2478                           hw_stats->ruc +
2479                           hw_stats->roc +
2480                           total_missed_rx +
2481                           hw_stats->illerrc +
2482                           hw_stats->errbc +
2483                           hw_stats->xec +
2484                           hw_stats->rfc +
2485                           hw_stats->fccrc +
2486                           hw_stats->fclast;
2487
2488         /* Tx Errors */
2489         stats->oerrors  = 0;
2490 }
2491
2492 static void
2493 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2494 {
2495         struct ixgbe_hw_stats *stats =
2496                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2497
2498         /* HW registers are cleared on read */
2499         ixgbe_dev_stats_get(dev, NULL);
2500
2501         /* Reset software totals */
2502         memset(stats, 0, sizeof(*stats));
2503 }
2504
2505 static int
2506 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2507                                          unsigned n)
2508 {
2509         struct ixgbe_hw *hw =
2510                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2511         struct ixgbe_hw_stats *hw_stats =
2512                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2513         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2514         unsigned i, count = IXGBE_NB_XSTATS;
2515
2516         if (n < count)
2517                 return count;
2518
2519         total_missed_rx = 0;
2520         total_qbrc = 0;
2521         total_qprc = 0;
2522         total_qprdc = 0;
2523
2524         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2525                                    &total_qprc, &total_qprdc);
2526
2527         /* If this is a reset xstats is NULL, and we have cleared the
2528          * registers by reading them.
2529          */
2530         if (!xstats)
2531                 return 0;
2532
2533         /* Extended stats from ixgbe_hw_stats */
2534         count = 0;
2535         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2536                 snprintf(xstats[count].name, sizeof(xstats[count].name), "%s",
2537                          rte_ixgbe_stats_strings[i].name);
2538                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2539                                 rte_ixgbe_stats_strings[i].offset);
2540                 count++;
2541         }
2542
2543         /* Per-Q stats, with 8 queues available */
2544         for (i = 0; i < 8; i++) {
2545                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2546                          "rx_q%u_mbuf_allocation_errors", i);
2547                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2548                                 offsetof(struct ixgbe_hw_stats, rnbc[i]));
2549                 count++;
2550
2551                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2552                          "rx_q%u_missed_packets", i);
2553                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2554                                 offsetof(struct ixgbe_hw_stats, mpc[i]));
2555                 count++;
2556
2557                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2558                          "rx_q%u_xon_priority_packets", i);
2559                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2560                                 offsetof(struct ixgbe_hw_stats, pxonrxc[i]));
2561                 count++;
2562
2563                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2564                          "tx_q%u_xon_priority_packets", i);
2565                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2566                                 offsetof(struct ixgbe_hw_stats, pxontxc[i]));
2567                 count++;
2568
2569                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2570                          "rx_q%u_xoff_priority_packets", i);
2571                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2572                                 offsetof(struct ixgbe_hw_stats, pxoffrxc[i]));
2573                 count++;
2574
2575                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2576                          "tx_q%u_xoff_priority_packets", i);
2577                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2578                                 offsetof(struct ixgbe_hw_stats, pxofftxc[i]));
2579                 count++;
2580
2581                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2582                          "xx_q%u_xon_to_xoff_priority_packets", i);
2583                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2584                                 offsetof(struct ixgbe_hw_stats, pxon2offc[i]));
2585                 count++;
2586         }
2587
2588         for (i = 0; i < 16; i++) {
2589                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2590                          "rx_q%u_packets", i);
2591                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2592                                 offsetof(struct ixgbe_hw_stats, qprc[i]));
2593                 count++;
2594
2595                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2596                          "rx_q%u_bytes", i);
2597                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2598                                 offsetof(struct ixgbe_hw_stats, qbrc[i]));
2599                 count++;
2600
2601                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2602                          "tx_q%u_packets", i);
2603                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2604                                 offsetof(struct ixgbe_hw_stats, qptc[i]));
2605                 count++;
2606
2607                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2608                          "tx_q%u_bytes", i);
2609                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2610                                 offsetof(struct ixgbe_hw_stats, qbtc[i]));
2611                 count++;
2612
2613                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2614                          "rx_q%u_dropped", i);
2615                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2616                                 offsetof(struct ixgbe_hw_stats, qprdc[i]));
2617                 count++;
2618         }
2619
2620         return count;
2621 }
2622
2623 static void
2624 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2625 {
2626         struct ixgbe_hw_stats *stats =
2627                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2628
2629         /* HW registers are cleared on read */
2630         ixgbe_dev_xstats_get(dev, NULL, IXGBE_NB_XSTATS);
2631
2632         /* Reset software totals */
2633         memset(stats, 0, sizeof(*stats));
2634 }
2635
2636 static void
2637 ixgbevf_update_stats(struct rte_eth_dev *dev)
2638 {
2639         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2640         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2641                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2642
2643         /* Good Rx packet, include VF loopback */
2644         UPDATE_VF_STAT(IXGBE_VFGPRC,
2645             hw_stats->last_vfgprc, hw_stats->vfgprc);
2646
2647         /* Good Rx octets, include VF loopback */
2648         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2649             hw_stats->last_vfgorc, hw_stats->vfgorc);
2650
2651         /* Good Tx packet, include VF loopback */
2652         UPDATE_VF_STAT(IXGBE_VFGPTC,
2653             hw_stats->last_vfgptc, hw_stats->vfgptc);
2654
2655         /* Good Tx octets, include VF loopback */
2656         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2657             hw_stats->last_vfgotc, hw_stats->vfgotc);
2658
2659         /* Rx Multicst Packet */
2660         UPDATE_VF_STAT(IXGBE_VFMPRC,
2661             hw_stats->last_vfmprc, hw_stats->vfmprc);
2662 }
2663
2664 static int
2665 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2666                        unsigned n)
2667 {
2668         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2669                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2670         unsigned i;
2671
2672         if (n < IXGBEVF_NB_XSTATS)
2673                 return IXGBEVF_NB_XSTATS;
2674
2675         ixgbevf_update_stats(dev);
2676
2677         if (!xstats)
2678                 return 0;
2679
2680         /* Extended stats */
2681         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2682                 snprintf(xstats[i].name, sizeof(xstats[i].name),
2683                          "%s", rte_ixgbevf_stats_strings[i].name);
2684                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2685                         rte_ixgbevf_stats_strings[i].offset);
2686         }
2687
2688         return IXGBEVF_NB_XSTATS;
2689 }
2690
2691 static void
2692 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2693 {
2694         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2695                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2696
2697         ixgbevf_update_stats(dev);
2698
2699         if (stats == NULL)
2700                 return;
2701
2702         stats->ipackets = hw_stats->vfgprc;
2703         stats->ibytes = hw_stats->vfgorc;
2704         stats->opackets = hw_stats->vfgptc;
2705         stats->obytes = hw_stats->vfgotc;
2706         stats->imcasts = hw_stats->vfmprc;
2707         /* stats->imcasts should be removed as imcasts is deprecated */
2708 }
2709
2710 static void
2711 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2712 {
2713         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2714                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2715
2716         /* Sync HW register to the last stats */
2717         ixgbevf_dev_stats_get(dev, NULL);
2718
2719         /* reset HW current stats*/
2720         hw_stats->vfgprc = 0;
2721         hw_stats->vfgorc = 0;
2722         hw_stats->vfgptc = 0;
2723         hw_stats->vfgotc = 0;
2724         hw_stats->vfmprc = 0;
2725
2726 }
2727
2728 static void
2729 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2730 {
2731         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2732
2733         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2734         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2735         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2736         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2737         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2738         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2739         dev_info->max_vfs = dev->pci_dev->max_vfs;
2740         if (hw->mac.type == ixgbe_mac_82598EB)
2741                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2742         else
2743                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2744         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2745         dev_info->rx_offload_capa =
2746                 DEV_RX_OFFLOAD_VLAN_STRIP |
2747                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2748                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2749                 DEV_RX_OFFLOAD_TCP_CKSUM;
2750
2751         /*
2752          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2753          * mode.
2754          */
2755         if ((hw->mac.type == ixgbe_mac_82599EB ||
2756              hw->mac.type == ixgbe_mac_X540) &&
2757             !RTE_ETH_DEV_SRIOV(dev).active)
2758                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2759
2760         dev_info->tx_offload_capa =
2761                 DEV_TX_OFFLOAD_VLAN_INSERT |
2762                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2763                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2764                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2765                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2766                 DEV_TX_OFFLOAD_TCP_TSO;
2767
2768         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2769                 .rx_thresh = {
2770                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2771                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2772                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2773                 },
2774                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2775                 .rx_drop_en = 0,
2776         };
2777
2778         dev_info->default_txconf = (struct rte_eth_txconf) {
2779                 .tx_thresh = {
2780                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2781                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2782                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2783                 },
2784                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2785                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2786                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2787                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2788         };
2789
2790         dev_info->rx_desc_lim = rx_desc_lim;
2791         dev_info->tx_desc_lim = tx_desc_lim;
2792
2793         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2794         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2795         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2796 }
2797
2798 static void
2799 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2800                      struct rte_eth_dev_info *dev_info)
2801 {
2802         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2803
2804         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2805         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2806         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2807         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2808         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2809         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2810         dev_info->max_vfs = dev->pci_dev->max_vfs;
2811         if (hw->mac.type == ixgbe_mac_82598EB)
2812                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2813         else
2814                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2815         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2816                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2817                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2818                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2819         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2820                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2821                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2822                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2823                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2824                                 DEV_TX_OFFLOAD_TCP_TSO;
2825
2826         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2827                 .rx_thresh = {
2828                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2829                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2830                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2831                 },
2832                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2833                 .rx_drop_en = 0,
2834         };
2835
2836         dev_info->default_txconf = (struct rte_eth_txconf) {
2837                 .tx_thresh = {
2838                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2839                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2840                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2841                 },
2842                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2843                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2844                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2845                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2846         };
2847
2848         dev_info->rx_desc_lim = rx_desc_lim;
2849         dev_info->tx_desc_lim = tx_desc_lim;
2850 }
2851
2852 /* return 0 means link status changed, -1 means not changed */
2853 static int
2854 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2855 {
2856         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2857         struct rte_eth_link link, old;
2858         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2859         int link_up;
2860         int diag;
2861
2862         link.link_status = 0;
2863         link.link_speed = 0;
2864         link.link_duplex = 0;
2865         memset(&old, 0, sizeof(old));
2866         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2867
2868         hw->mac.get_link_status = true;
2869
2870         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2871         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2872                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2873         else
2874                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2875
2876         if (diag != 0) {
2877                 link.link_speed = ETH_LINK_SPEED_100;
2878                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2879                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2880                 if (link.link_status == old.link_status)
2881                         return -1;
2882                 return 0;
2883         }
2884
2885         if (link_up == 0) {
2886                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2887                 if (link.link_status == old.link_status)
2888                         return -1;
2889                 return 0;
2890         }
2891         link.link_status = 1;
2892         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2893
2894         switch (link_speed) {
2895         default:
2896         case IXGBE_LINK_SPEED_UNKNOWN:
2897                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2898                 link.link_speed = ETH_LINK_SPEED_100;
2899                 break;
2900
2901         case IXGBE_LINK_SPEED_100_FULL:
2902                 link.link_speed = ETH_LINK_SPEED_100;
2903                 break;
2904
2905         case IXGBE_LINK_SPEED_1GB_FULL:
2906                 link.link_speed = ETH_LINK_SPEED_1000;
2907                 break;
2908
2909         case IXGBE_LINK_SPEED_10GB_FULL:
2910                 link.link_speed = ETH_LINK_SPEED_10000;
2911                 break;
2912         }
2913         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2914
2915         if (link.link_status == old.link_status)
2916                 return -1;
2917
2918         return 0;
2919 }
2920
2921 static void
2922 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2923 {
2924         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2925         uint32_t fctrl;
2926
2927         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2928         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2929         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2930 }
2931
2932 static void
2933 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2934 {
2935         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2936         uint32_t fctrl;
2937
2938         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2939         fctrl &= (~IXGBE_FCTRL_UPE);
2940         if (dev->data->all_multicast == 1)
2941                 fctrl |= IXGBE_FCTRL_MPE;
2942         else
2943                 fctrl &= (~IXGBE_FCTRL_MPE);
2944         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2945 }
2946
2947 static void
2948 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2949 {
2950         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2951         uint32_t fctrl;
2952
2953         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2954         fctrl |= IXGBE_FCTRL_MPE;
2955         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2956 }
2957
2958 static void
2959 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2960 {
2961         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2962         uint32_t fctrl;
2963
2964         if (dev->data->promiscuous == 1)
2965                 return; /* must remain in all_multicast mode */
2966
2967         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2968         fctrl &= (~IXGBE_FCTRL_MPE);
2969         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2970 }
2971
2972 /**
2973  * It clears the interrupt causes and enables the interrupt.
2974  * It will be called once only during nic initialized.
2975  *
2976  * @param dev
2977  *  Pointer to struct rte_eth_dev.
2978  *
2979  * @return
2980  *  - On success, zero.
2981  *  - On failure, a negative value.
2982  */
2983 static int
2984 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2985 {
2986         struct ixgbe_interrupt *intr =
2987                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2988
2989         ixgbe_dev_link_status_print(dev);
2990         intr->mask |= IXGBE_EICR_LSC;
2991
2992         return 0;
2993 }
2994
2995 /**
2996  * It clears the interrupt causes and enables the interrupt.
2997  * It will be called once only during nic initialized.
2998  *
2999  * @param dev
3000  *  Pointer to struct rte_eth_dev.
3001  *
3002  * @return
3003  *  - On success, zero.
3004  *  - On failure, a negative value.
3005  */
3006 static int
3007 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3008 {
3009         struct ixgbe_interrupt *intr =
3010                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3011
3012         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3013
3014         return 0;
3015 }
3016
3017 /*
3018  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3019  *
3020  * @param dev
3021  *  Pointer to struct rte_eth_dev.
3022  *
3023  * @return
3024  *  - On success, zero.
3025  *  - On failure, a negative value.
3026  */
3027 static int
3028 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3029 {
3030         uint32_t eicr;
3031         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3032         struct ixgbe_interrupt *intr =
3033                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3034
3035         /* clear all cause mask */
3036         ixgbe_disable_intr(hw);
3037
3038         /* read-on-clear nic registers here */
3039         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3040         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3041
3042         intr->flags = 0;
3043
3044         /* set flag for async link update */
3045         if (eicr & IXGBE_EICR_LSC)
3046                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3047
3048         if (eicr & IXGBE_EICR_MAILBOX)
3049                 intr->flags |= IXGBE_FLAG_MAILBOX;
3050
3051         return 0;
3052 }
3053
3054 static int
3055 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
3056 {
3057         uint32_t eicr;
3058         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3059         struct ixgbe_interrupt *intr =
3060                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3061
3062         /* clear all cause mask */
3063         ixgbevf_intr_disable(hw);
3064
3065         /* read-on-clear nic registers here */
3066         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
3067         PMD_DRV_LOG(INFO, "eicr %x", eicr);
3068
3069         intr->flags = 0;
3070
3071         /* set flag for async link update */
3072         if (eicr & IXGBE_EICR_LSC)
3073                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3074
3075         return 0;
3076 }
3077
3078 /**
3079  * It gets and then prints the link status.
3080  *
3081  * @param dev
3082  *  Pointer to struct rte_eth_dev.
3083  *
3084  * @return
3085  *  - On success, zero.
3086  *  - On failure, a negative value.
3087  */
3088 static void
3089 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3090 {
3091         struct rte_eth_link link;
3092
3093         memset(&link, 0, sizeof(link));
3094         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3095         if (link.link_status) {
3096                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3097                                         (int)(dev->data->port_id),
3098                                         (unsigned)link.link_speed,
3099                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3100                                         "full-duplex" : "half-duplex");
3101         } else {
3102                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3103                                 (int)(dev->data->port_id));
3104         }
3105         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3106                                 dev->pci_dev->addr.domain,
3107                                 dev->pci_dev->addr.bus,
3108                                 dev->pci_dev->addr.devid,
3109                                 dev->pci_dev->addr.function);
3110 }
3111
3112 /*
3113  * It executes link_update after knowing an interrupt occurred.
3114  *
3115  * @param dev
3116  *  Pointer to struct rte_eth_dev.
3117  *
3118  * @return
3119  *  - On success, zero.
3120  *  - On failure, a negative value.
3121  */
3122 static int
3123 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3124 {
3125         struct ixgbe_interrupt *intr =
3126                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3127         int64_t timeout;
3128         struct rte_eth_link link;
3129         int intr_enable_delay = false;
3130
3131         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3132
3133         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3134                 ixgbe_pf_mbx_process(dev);
3135                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3136         }
3137
3138         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3139                 /* get the link status before link update, for predicting later */
3140                 memset(&link, 0, sizeof(link));
3141                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3142
3143                 ixgbe_dev_link_update(dev, 0);
3144
3145                 /* likely to up */
3146                 if (!link.link_status)
3147                         /* handle it 1 sec later, wait it being stable */
3148                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3149                 /* likely to down */
3150                 else
3151                         /* handle it 4 sec later, wait it being stable */
3152                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3153
3154                 ixgbe_dev_link_status_print(dev);
3155
3156                 intr_enable_delay = true;
3157         }
3158
3159         if (intr_enable_delay) {
3160                 if (rte_eal_alarm_set(timeout * 1000,
3161                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
3162                         PMD_DRV_LOG(ERR, "Error setting alarm");
3163         } else {
3164                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3165                 ixgbe_enable_intr(dev);
3166                 rte_intr_enable(&(dev->pci_dev->intr_handle));
3167         }
3168
3169
3170         return 0;
3171 }
3172
3173 static int
3174 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
3175 {
3176         struct ixgbe_hw *hw =
3177                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3178
3179         PMD_DRV_LOG(DEBUG, "enable intr immediately");
3180         ixgbevf_intr_enable(hw);
3181         rte_intr_enable(&dev->pci_dev->intr_handle);
3182         return 0;
3183 }
3184
3185 /**
3186  * Interrupt handler which shall be registered for alarm callback for delayed
3187  * handling specific interrupt to wait for the stable nic state. As the
3188  * NIC interrupt state is not stable for ixgbe after link is just down,
3189  * it needs to wait 4 seconds to get the stable status.
3190  *
3191  * @param handle
3192  *  Pointer to interrupt handle.
3193  * @param param
3194  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3195  *
3196  * @return
3197  *  void
3198  */
3199 static void
3200 ixgbe_dev_interrupt_delayed_handler(void *param)
3201 {
3202         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3203         struct ixgbe_interrupt *intr =
3204                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3205         struct ixgbe_hw *hw =
3206                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3207         uint32_t eicr;
3208
3209         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3210         if (eicr & IXGBE_EICR_MAILBOX)
3211                 ixgbe_pf_mbx_process(dev);
3212
3213         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3214                 ixgbe_dev_link_update(dev, 0);
3215                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3216                 ixgbe_dev_link_status_print(dev);
3217                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3218         }
3219
3220         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3221         ixgbe_enable_intr(dev);
3222         rte_intr_enable(&(dev->pci_dev->intr_handle));
3223 }
3224
3225 /**
3226  * Interrupt handler triggered by NIC  for handling
3227  * specific interrupt.
3228  *
3229  * @param handle
3230  *  Pointer to interrupt handle.
3231  * @param param
3232  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3233  *
3234  * @return
3235  *  void
3236  */
3237 static void
3238 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3239                             void *param)
3240 {
3241         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3242
3243         ixgbe_dev_interrupt_get_status(dev);
3244         ixgbe_dev_interrupt_action(dev);
3245 }
3246
3247 static void
3248 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3249                               void *param)
3250 {
3251         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3252
3253         ixgbevf_dev_interrupt_get_status(dev);
3254         ixgbevf_dev_interrupt_action(dev);
3255 }
3256
3257 static int
3258 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3259 {
3260         struct ixgbe_hw *hw;
3261
3262         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3263         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
3264 }
3265
3266 static int
3267 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3268 {
3269         struct ixgbe_hw *hw;
3270
3271         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3272         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
3273 }
3274
3275 static int
3276 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3277 {
3278         struct ixgbe_hw *hw;
3279         uint32_t mflcn_reg;
3280         uint32_t fccfg_reg;
3281         int rx_pause;
3282         int tx_pause;
3283
3284         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3285
3286         fc_conf->pause_time = hw->fc.pause_time;
3287         fc_conf->high_water = hw->fc.high_water[0];
3288         fc_conf->low_water = hw->fc.low_water[0];
3289         fc_conf->send_xon = hw->fc.send_xon;
3290         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3291
3292         /*
3293          * Return rx_pause status according to actual setting of
3294          * MFLCN register.
3295          */
3296         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3297         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3298                 rx_pause = 1;
3299         else
3300                 rx_pause = 0;
3301
3302         /*
3303          * Return tx_pause status according to actual setting of
3304          * FCCFG register.
3305          */
3306         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3307         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3308                 tx_pause = 1;
3309         else
3310                 tx_pause = 0;
3311
3312         if (rx_pause && tx_pause)
3313                 fc_conf->mode = RTE_FC_FULL;
3314         else if (rx_pause)
3315                 fc_conf->mode = RTE_FC_RX_PAUSE;
3316         else if (tx_pause)
3317                 fc_conf->mode = RTE_FC_TX_PAUSE;
3318         else
3319                 fc_conf->mode = RTE_FC_NONE;
3320
3321         return 0;
3322 }
3323
3324 static int
3325 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3326 {
3327         struct ixgbe_hw *hw;
3328         int err;
3329         uint32_t rx_buf_size;
3330         uint32_t max_high_water;
3331         uint32_t mflcn;
3332         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3333                 ixgbe_fc_none,
3334                 ixgbe_fc_rx_pause,
3335                 ixgbe_fc_tx_pause,
3336                 ixgbe_fc_full
3337         };
3338
3339         PMD_INIT_FUNC_TRACE();
3340
3341         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3342         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3343         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3344
3345         /*
3346          * At least reserve one Ethernet frame for watermark
3347          * high_water/low_water in kilo bytes for ixgbe
3348          */
3349         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3350         if ((fc_conf->high_water > max_high_water) ||
3351                 (fc_conf->high_water < fc_conf->low_water)) {
3352                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3353                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3354                 return (-EINVAL);
3355         }
3356
3357         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3358         hw->fc.pause_time     = fc_conf->pause_time;
3359         hw->fc.high_water[0]  = fc_conf->high_water;
3360         hw->fc.low_water[0]   = fc_conf->low_water;
3361         hw->fc.send_xon       = fc_conf->send_xon;
3362         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3363
3364         err = ixgbe_fc_enable(hw);
3365
3366         /* Not negotiated is not an error case */
3367         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3368
3369                 /* check if we want to forward MAC frames - driver doesn't have native
3370                  * capability to do that, so we'll write the registers ourselves */
3371
3372                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3373
3374                 /* set or clear MFLCN.PMCF bit depending on configuration */
3375                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3376                         mflcn |= IXGBE_MFLCN_PMCF;
3377                 else
3378                         mflcn &= ~IXGBE_MFLCN_PMCF;
3379
3380                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3381                 IXGBE_WRITE_FLUSH(hw);
3382
3383                 return 0;
3384         }
3385
3386         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3387         return -EIO;
3388 }
3389
3390 /**
3391  *  ixgbe_pfc_enable_generic - Enable flow control
3392  *  @hw: pointer to hardware structure
3393  *  @tc_num: traffic class number
3394  *  Enable flow control according to the current settings.
3395  */
3396 static int
3397 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3398 {
3399         int ret_val = 0;
3400         uint32_t mflcn_reg, fccfg_reg;
3401         uint32_t reg;
3402         uint32_t fcrtl, fcrth;
3403         uint8_t i;
3404         uint8_t nb_rx_en;
3405
3406         /* Validate the water mark configuration */
3407         if (!hw->fc.pause_time) {
3408                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3409                 goto out;
3410         }
3411
3412         /* Low water mark of zero causes XOFF floods */
3413         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3414                  /* High/Low water can not be 0 */
3415                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
3416                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3417                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3418                         goto out;
3419                 }
3420
3421                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3422                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3423                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3424                         goto out;
3425                 }
3426         }
3427         /* Negotiate the fc mode to use */
3428         ixgbe_fc_autoneg(hw);
3429
3430         /* Disable any previous flow control settings */
3431         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3432         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3433
3434         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3435         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3436
3437         switch (hw->fc.current_mode) {
3438         case ixgbe_fc_none:
3439                 /*
3440                  * If the count of enabled RX Priority Flow control >1,
3441                  * and the TX pause can not be disabled
3442                  */
3443                 nb_rx_en = 0;
3444                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3445                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3446                         if (reg & IXGBE_FCRTH_FCEN)
3447                                 nb_rx_en++;
3448                 }
3449                 if (nb_rx_en > 1)
3450                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3451                 break;
3452         case ixgbe_fc_rx_pause:
3453                 /*
3454                  * Rx Flow control is enabled and Tx Flow control is
3455                  * disabled by software override. Since there really
3456                  * isn't a way to advertise that we are capable of RX
3457                  * Pause ONLY, we will advertise that we support both
3458                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3459                  * disable the adapter's ability to send PAUSE frames.
3460                  */
3461                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3462                 /*
3463                  * If the count of enabled RX Priority Flow control >1,
3464                  * and the TX pause can not be disabled
3465                  */
3466                 nb_rx_en = 0;
3467                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3468                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3469                         if (reg & IXGBE_FCRTH_FCEN)
3470                                 nb_rx_en++;
3471                 }
3472                 if (nb_rx_en > 1)
3473                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3474                 break;
3475         case ixgbe_fc_tx_pause:
3476                 /*
3477                  * Tx Flow control is enabled, and Rx Flow control is
3478                  * disabled by software override.
3479                  */
3480                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3481                 break;
3482         case ixgbe_fc_full:
3483                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3484                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3485                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3486                 break;
3487         default:
3488                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3489                 ret_val = IXGBE_ERR_CONFIG;
3490                 goto out;
3491                 break;
3492         }
3493
3494         /* Set 802.3x based flow control settings. */
3495         mflcn_reg |= IXGBE_MFLCN_DPF;
3496         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3497         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3498
3499         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3500         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3501                 hw->fc.high_water[tc_num]) {
3502                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3503                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3504                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3505         } else {
3506                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3507                 /*
3508                  * In order to prevent Tx hangs when the internal Tx
3509                  * switch is enabled we must set the high water mark
3510                  * to the maximum FCRTH value.  This allows the Tx
3511                  * switch to function even under heavy Rx workloads.
3512                  */
3513                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3514         }
3515         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3516
3517         /* Configure pause time (2 TCs per register) */
3518         reg = hw->fc.pause_time * 0x00010001;
3519         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3520                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3521
3522         /* Configure flow control refresh threshold value */
3523         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3524
3525 out:
3526         return ret_val;
3527 }
3528
3529 static int
3530 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3531 {
3532         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3533         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3534
3535         if(hw->mac.type != ixgbe_mac_82598EB) {
3536                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3537         }
3538         return ret_val;
3539 }
3540
3541 static int
3542 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3543 {
3544         int err;
3545         uint32_t rx_buf_size;
3546         uint32_t max_high_water;
3547         uint8_t tc_num;
3548         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3549         struct ixgbe_hw *hw =
3550                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3551         struct ixgbe_dcb_config *dcb_config =
3552                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3553
3554         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3555                 ixgbe_fc_none,
3556                 ixgbe_fc_rx_pause,
3557                 ixgbe_fc_tx_pause,
3558                 ixgbe_fc_full
3559         };
3560
3561         PMD_INIT_FUNC_TRACE();
3562
3563         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3564         tc_num = map[pfc_conf->priority];
3565         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3566         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3567         /*
3568          * At least reserve one Ethernet frame for watermark
3569          * high_water/low_water in kilo bytes for ixgbe
3570          */
3571         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3572         if ((pfc_conf->fc.high_water > max_high_water) ||
3573             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3574                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3575                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3576                 return (-EINVAL);
3577         }
3578
3579         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3580         hw->fc.pause_time = pfc_conf->fc.pause_time;
3581         hw->fc.send_xon = pfc_conf->fc.send_xon;
3582         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3583         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3584
3585         err = ixgbe_dcb_pfc_enable(dev,tc_num);
3586
3587         /* Not negotiated is not an error case */
3588         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3589                 return 0;
3590
3591         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3592         return -EIO;
3593 }
3594
3595 static int
3596 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3597                           struct rte_eth_rss_reta_entry64 *reta_conf,
3598                           uint16_t reta_size)
3599 {
3600         uint8_t i, j, mask;
3601         uint32_t reta, r;
3602         uint16_t idx, shift;
3603         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3604         uint16_t sp_reta_size;
3605         uint32_t reta_reg;
3606
3607         PMD_INIT_FUNC_TRACE();
3608
3609         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3610                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3611                         "NIC.");
3612                 return -ENOTSUP;
3613         }
3614
3615         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3616         if (reta_size != sp_reta_size) {
3617                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3618                         "(%d) doesn't match the number hardware can supported "
3619                         "(%d)\n", reta_size, sp_reta_size);
3620                 return -EINVAL;
3621         }
3622
3623         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3624                 idx = i / RTE_RETA_GROUP_SIZE;
3625                 shift = i % RTE_RETA_GROUP_SIZE;
3626                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3627                                                 IXGBE_4_BIT_MASK);
3628                 if (!mask)
3629                         continue;
3630                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3631                 if (mask == IXGBE_4_BIT_MASK)
3632                         r = 0;
3633                 else
3634                         r = IXGBE_READ_REG(hw, reta_reg);
3635                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3636                         if (mask & (0x1 << j))
3637                                 reta |= reta_conf[idx].reta[shift + j] <<
3638                                                         (CHAR_BIT * j);
3639                         else
3640                                 reta |= r & (IXGBE_8_BIT_MASK <<
3641                                                 (CHAR_BIT * j));
3642                 }
3643                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3644         }
3645
3646         return 0;
3647 }
3648
3649 static int
3650 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3651                          struct rte_eth_rss_reta_entry64 *reta_conf,
3652                          uint16_t reta_size)
3653 {
3654         uint8_t i, j, mask;
3655         uint32_t reta;
3656         uint16_t idx, shift;
3657         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3658         uint16_t sp_reta_size;
3659         uint32_t reta_reg;
3660
3661         PMD_INIT_FUNC_TRACE();
3662         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3663         if (reta_size != sp_reta_size) {
3664                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3665                         "(%d) doesn't match the number hardware can supported "
3666                         "(%d)\n", reta_size, sp_reta_size);
3667                 return -EINVAL;
3668         }
3669
3670         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3671                 idx = i / RTE_RETA_GROUP_SIZE;
3672                 shift = i % RTE_RETA_GROUP_SIZE;
3673                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3674                                                 IXGBE_4_BIT_MASK);
3675                 if (!mask)
3676                         continue;
3677
3678                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3679                 reta = IXGBE_READ_REG(hw, reta_reg);
3680                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3681                         if (mask & (0x1 << j))
3682                                 reta_conf[idx].reta[shift + j] =
3683                                         ((reta >> (CHAR_BIT * j)) &
3684                                                 IXGBE_8_BIT_MASK);
3685                 }
3686         }
3687
3688         return 0;
3689 }
3690
3691 static void
3692 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3693                                 uint32_t index, uint32_t pool)
3694 {
3695         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3696         uint32_t enable_addr = 1;
3697
3698         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3699 }
3700
3701 static void
3702 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3703 {
3704         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3705
3706         ixgbe_clear_rar(hw, index);
3707 }
3708
3709 static void
3710 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3711 {
3712         ixgbe_remove_rar(dev, 0);
3713
3714         ixgbe_add_rar(dev, addr, 0, 0);
3715 }
3716
3717 static int
3718 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3719 {
3720         uint32_t hlreg0;
3721         uint32_t maxfrs;
3722         struct ixgbe_hw *hw;
3723         struct rte_eth_dev_info dev_info;
3724         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3725
3726         ixgbe_dev_info_get(dev, &dev_info);
3727
3728         /* check that mtu is within the allowed range */
3729         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3730                 return -EINVAL;
3731
3732         /* refuse mtu that requires the support of scattered packets when this
3733          * feature has not been enabled before. */
3734         if (!dev->data->scattered_rx &&
3735             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3736              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3737                 return -EINVAL;
3738
3739         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3740         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3741
3742         /* switch to jumbo mode if needed */
3743         if (frame_size > ETHER_MAX_LEN) {
3744                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3745                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3746         } else {
3747                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3748                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3749         }
3750         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3751
3752         /* update max frame size */
3753         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3754
3755         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3756         maxfrs &= 0x0000FFFF;
3757         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3758         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3759
3760         return 0;
3761 }
3762
3763 /*
3764  * Virtual Function operations
3765  */
3766 static void
3767 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3768 {
3769         PMD_INIT_FUNC_TRACE();
3770
3771         /* Clear interrupt mask to stop from interrupts being generated */
3772         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3773
3774         IXGBE_WRITE_FLUSH(hw);
3775 }
3776
3777 static void
3778 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3779 {
3780         PMD_INIT_FUNC_TRACE();
3781
3782         /* VF enable interrupt autoclean */
3783         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3784         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3785         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3786
3787         IXGBE_WRITE_FLUSH(hw);
3788 }
3789
3790 static int
3791 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3792 {
3793         struct rte_eth_conf* conf = &dev->data->dev_conf;
3794         struct ixgbe_adapter *adapter =
3795                         (struct ixgbe_adapter *)dev->data->dev_private;
3796
3797         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3798                      dev->data->port_id);
3799
3800         /*
3801          * VF has no ability to enable/disable HW CRC
3802          * Keep the persistent behavior the same as Host PF
3803          */
3804 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3805         if (!conf->rxmode.hw_strip_crc) {
3806                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3807                 conf->rxmode.hw_strip_crc = 1;
3808         }
3809 #else
3810         if (conf->rxmode.hw_strip_crc) {
3811                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3812                 conf->rxmode.hw_strip_crc = 0;
3813         }
3814 #endif
3815
3816         /*
3817          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3818          * allocation or vector Rx preconditions we will reset it.
3819          */
3820         adapter->rx_bulk_alloc_allowed = true;
3821         adapter->rx_vec_allowed = true;
3822
3823         return 0;
3824 }
3825
3826 static int
3827 ixgbevf_dev_start(struct rte_eth_dev *dev)
3828 {
3829         struct ixgbe_hw *hw =
3830                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3831         uint32_t intr_vector = 0;
3832         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3833
3834         int err, mask = 0;
3835
3836         PMD_INIT_FUNC_TRACE();
3837
3838         hw->mac.ops.reset_hw(hw);
3839         hw->mac.get_link_status = true;
3840
3841         /* negotiate mailbox API version to use with the PF. */
3842         ixgbevf_negotiate_api(hw);
3843
3844         ixgbevf_dev_tx_init(dev);
3845
3846         /* This can fail when allocating mbufs for descriptor rings */
3847         err = ixgbevf_dev_rx_init(dev);
3848         if (err) {
3849                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3850                 ixgbe_dev_clear_queues(dev);
3851                 return err;
3852         }
3853
3854         /* Set vfta */
3855         ixgbevf_set_vfta_all(dev,1);
3856
3857         /* Set HW strip */
3858         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3859                 ETH_VLAN_EXTEND_MASK;
3860         ixgbevf_vlan_offload_set(dev, mask);
3861
3862         ixgbevf_dev_rxtx_start(dev);
3863
3864         /* check and configure queue intr-vector mapping */
3865         if (dev->data->dev_conf.intr_conf.rxq != 0)
3866                 intr_vector = dev->data->nb_rx_queues;
3867
3868         if (rte_intr_efd_enable(intr_handle, intr_vector))
3869                 return -1;
3870
3871         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3872                 intr_handle->intr_vec =
3873                         rte_zmalloc("intr_vec",
3874                                     dev->data->nb_rx_queues * sizeof(int), 0);
3875                 if (intr_handle->intr_vec == NULL) {
3876                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3877                                      " intr_vec\n", dev->data->nb_rx_queues);
3878                         return -ENOMEM;
3879                 }
3880         }
3881         ixgbevf_configure_msix(dev);
3882
3883         if (dev->data->dev_conf.intr_conf.lsc != 0) {
3884                 if (rte_intr_allow_others(intr_handle))
3885                         rte_intr_callback_register(intr_handle,
3886                                         ixgbevf_dev_interrupt_handler,
3887                                         (void *)dev);
3888                 else
3889                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
3890                                      " no intr multiplex\n");
3891         }
3892
3893         rte_intr_enable(intr_handle);
3894
3895         /* Re-enable interrupt for VF */
3896         ixgbevf_intr_enable(hw);
3897
3898         return 0;
3899 }
3900
3901 static void
3902 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3903 {
3904         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3905         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3906
3907         PMD_INIT_FUNC_TRACE();
3908
3909         hw->adapter_stopped = 1;
3910         ixgbe_stop_adapter(hw);
3911
3912         /*
3913           * Clear what we set, but we still keep shadow_vfta to
3914           * restore after device starts
3915           */
3916         ixgbevf_set_vfta_all(dev,0);
3917
3918         /* Clear stored conf */
3919         dev->data->scattered_rx = 0;
3920
3921         ixgbe_dev_clear_queues(dev);
3922
3923         /* disable intr eventfd mapping */
3924         rte_intr_disable(intr_handle);
3925
3926         /* Clean datapath event and queue/vec mapping */
3927         rte_intr_efd_disable(intr_handle);
3928         if (intr_handle->intr_vec != NULL) {
3929                 rte_free(intr_handle->intr_vec);
3930                 intr_handle->intr_vec = NULL;
3931         }
3932 }
3933
3934 static void
3935 ixgbevf_dev_close(struct rte_eth_dev *dev)
3936 {
3937         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3938         struct rte_pci_device *pci_dev;
3939
3940         PMD_INIT_FUNC_TRACE();
3941
3942         ixgbe_reset_hw(hw);
3943
3944         ixgbevf_dev_stop(dev);
3945
3946         ixgbe_dev_free_queues(dev);
3947
3948         /* reprogram the RAR[0] in case user changed it. */
3949         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3950
3951         pci_dev = dev->pci_dev;
3952         if (pci_dev->intr_handle.intr_vec) {
3953                 rte_free(pci_dev->intr_handle.intr_vec);
3954                 pci_dev->intr_handle.intr_vec = NULL;
3955         }
3956 }
3957
3958 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3959 {
3960         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3961         struct ixgbe_vfta * shadow_vfta =
3962                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3963         int i = 0, j = 0, vfta = 0, mask = 1;
3964
3965         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3966                 vfta = shadow_vfta->vfta[i];
3967                 if(vfta){
3968                         mask = 1;
3969                         for (j = 0; j < 32; j++){
3970                                 if(vfta & mask)
3971                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3972                                 mask<<=1;
3973                         }
3974                 }
3975         }
3976
3977 }
3978
3979 static int
3980 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3981 {
3982         struct ixgbe_hw *hw =
3983                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3984         struct ixgbe_vfta * shadow_vfta =
3985                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3986         uint32_t vid_idx = 0;
3987         uint32_t vid_bit = 0;
3988         int ret = 0;
3989
3990         PMD_INIT_FUNC_TRACE();
3991
3992         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3993         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3994         if(ret){
3995                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3996                 return ret;
3997         }
3998         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3999         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4000
4001         /* Save what we set and retore it after device reset */
4002         if (on)
4003                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4004         else
4005                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4006
4007         return 0;
4008 }
4009
4010 static void
4011 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4012 {
4013         struct ixgbe_hw *hw =
4014                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4015         uint32_t ctrl;
4016
4017         PMD_INIT_FUNC_TRACE();
4018
4019         if(queue >= hw->mac.max_rx_queues)
4020                 return;
4021
4022         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4023         if(on)
4024                 ctrl |= IXGBE_RXDCTL_VME;
4025         else
4026                 ctrl &= ~IXGBE_RXDCTL_VME;
4027         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4028
4029         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
4030 }
4031
4032 static void
4033 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4034 {
4035         struct ixgbe_hw *hw =
4036                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4037         uint16_t i;
4038         int on = 0;
4039
4040         /* VF function only support hw strip feature, others are not support */
4041         if(mask & ETH_VLAN_STRIP_MASK){
4042                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4043
4044                 for(i=0; i < hw->mac.max_rx_queues; i++)
4045                         ixgbevf_vlan_strip_queue_set(dev,i,on);
4046         }
4047 }
4048
4049 static int
4050 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4051 {
4052         uint32_t reg_val;
4053
4054         /* we only need to do this if VMDq is enabled */
4055         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4056         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4057                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4058                 return (-1);
4059         }
4060
4061         return 0;
4062 }
4063
4064 static uint32_t
4065 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
4066 {
4067         uint32_t vector = 0;
4068         switch (hw->mac.mc_filter_type) {
4069         case 0:   /* use bits [47:36] of the address */
4070                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4071                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4072                 break;
4073         case 1:   /* use bits [46:35] of the address */
4074                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4075                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4076                 break;
4077         case 2:   /* use bits [45:34] of the address */
4078                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4079                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4080                 break;
4081         case 3:   /* use bits [43:32] of the address */
4082                 vector = ((uc_addr->addr_bytes[4]) |
4083                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4084                 break;
4085         default:  /* Invalid mc_filter_type */
4086                 break;
4087         }
4088
4089         /* vector can only be 12-bits or boundary will be exceeded */
4090         vector &= 0xFFF;
4091         return vector;
4092 }
4093
4094 static int
4095 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
4096                                uint8_t on)
4097 {
4098         uint32_t vector;
4099         uint32_t uta_idx;
4100         uint32_t reg_val;
4101         uint32_t uta_shift;
4102         uint32_t rc;
4103         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4104         const uint32_t ixgbe_uta_bit_shift = 5;
4105         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4106         const uint32_t bit1 = 0x1;
4107
4108         struct ixgbe_hw *hw =
4109                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4110         struct ixgbe_uta_info *uta_info =
4111                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4112
4113         /* The UTA table only exists on 82599 hardware and newer */
4114         if (hw->mac.type < ixgbe_mac_82599EB)
4115                 return (-ENOTSUP);
4116
4117         vector = ixgbe_uta_vector(hw,mac_addr);
4118         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4119         uta_shift = vector & ixgbe_uta_bit_mask;
4120
4121         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4122         if(rc == on)
4123                 return 0;
4124
4125         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4126         if (on) {
4127                 uta_info->uta_in_use++;
4128                 reg_val |= (bit1 << uta_shift);
4129                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4130         } else {
4131                 uta_info->uta_in_use--;
4132                 reg_val &= ~(bit1 << uta_shift);
4133                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4134         }
4135
4136         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4137
4138         if (uta_info->uta_in_use > 0)
4139                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4140                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4141         else
4142                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
4143
4144         return 0;
4145 }
4146
4147 static int
4148 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4149 {
4150         int i;
4151         struct ixgbe_hw *hw =
4152                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4153         struct ixgbe_uta_info *uta_info =
4154                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4155
4156         /* The UTA table only exists on 82599 hardware and newer */
4157         if (hw->mac.type < ixgbe_mac_82599EB)
4158                 return (-ENOTSUP);
4159
4160         if(on) {
4161                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4162                         uta_info->uta_shadow[i] = ~0;
4163                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4164                 }
4165         } else {
4166                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4167                         uta_info->uta_shadow[i] = 0;
4168                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4169                 }
4170         }
4171         return 0;
4172
4173 }
4174
4175 uint32_t
4176 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4177 {
4178         uint32_t new_val = orig_val;
4179
4180         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4181                 new_val |= IXGBE_VMOLR_AUPE;
4182         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4183                 new_val |= IXGBE_VMOLR_ROMPE;
4184         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4185                 new_val |= IXGBE_VMOLR_ROPE;
4186         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4187                 new_val |= IXGBE_VMOLR_BAM;
4188         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4189                 new_val |= IXGBE_VMOLR_MPE;
4190
4191         return new_val;
4192 }
4193
4194 static int
4195 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4196                                uint16_t rx_mask, uint8_t on)
4197 {
4198         int val = 0;
4199
4200         struct ixgbe_hw *hw =
4201                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4202         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4203
4204         if (hw->mac.type == ixgbe_mac_82598EB) {
4205                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4206                              " on 82599 hardware and newer");
4207                 return (-ENOTSUP);
4208         }
4209         if (ixgbe_vmdq_mode_check(hw) < 0)
4210                 return (-ENOTSUP);
4211
4212         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4213
4214         if (on)
4215                 vmolr |= val;
4216         else
4217                 vmolr &= ~val;
4218
4219         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4220
4221         return 0;
4222 }
4223
4224 static int
4225 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4226 {
4227         uint32_t reg,addr;
4228         uint32_t val;
4229         const uint8_t bit1 = 0x1;
4230
4231         struct ixgbe_hw *hw =
4232                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4233
4234         if (ixgbe_vmdq_mode_check(hw) < 0)
4235                 return (-ENOTSUP);
4236
4237         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
4238         reg = IXGBE_READ_REG(hw, addr);
4239         val = bit1 << pool;
4240
4241         if (on)
4242                 reg |= val;
4243         else
4244                 reg &= ~val;
4245
4246         IXGBE_WRITE_REG(hw, addr,reg);
4247
4248         return 0;
4249 }
4250
4251 static int
4252 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4253 {
4254         uint32_t reg,addr;
4255         uint32_t val;
4256         const uint8_t bit1 = 0x1;
4257
4258         struct ixgbe_hw *hw =
4259                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4260
4261         if (ixgbe_vmdq_mode_check(hw) < 0)
4262                 return (-ENOTSUP);
4263
4264         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
4265         reg = IXGBE_READ_REG(hw, addr);
4266         val = bit1 << pool;
4267
4268         if (on)
4269                 reg |= val;
4270         else
4271                 reg &= ~val;
4272
4273         IXGBE_WRITE_REG(hw, addr,reg);
4274
4275         return 0;
4276 }
4277
4278 static int
4279 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4280                         uint64_t pool_mask, uint8_t vlan_on)
4281 {
4282         int ret = 0;
4283         uint16_t pool_idx;
4284         struct ixgbe_hw *hw =
4285                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4286
4287         if (ixgbe_vmdq_mode_check(hw) < 0)
4288                 return (-ENOTSUP);
4289         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4290                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
4291                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
4292                         if (ret < 0)
4293                                 return ret;
4294         }
4295
4296         return ret;
4297 }
4298
4299 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4300 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4301 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4302 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4303 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4304         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4305         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4306
4307 static int
4308 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4309                         struct rte_eth_mirror_conf *mirror_conf,
4310                         uint8_t rule_id, uint8_t on)
4311 {
4312         uint32_t mr_ctl,vlvf;
4313         uint32_t mp_lsb = 0;
4314         uint32_t mv_msb = 0;
4315         uint32_t mv_lsb = 0;
4316         uint32_t mp_msb = 0;
4317         uint8_t i = 0;
4318         int reg_index = 0;
4319         uint64_t vlan_mask = 0;
4320
4321         const uint8_t pool_mask_offset = 32;
4322         const uint8_t vlan_mask_offset = 32;
4323         const uint8_t dst_pool_offset = 8;
4324         const uint8_t rule_mr_offset  = 4;
4325         const uint8_t mirror_rule_mask= 0x0F;
4326
4327         struct ixgbe_mirror_info *mr_info =
4328                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4329         struct ixgbe_hw *hw =
4330                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4331         uint8_t mirror_type = 0;
4332
4333         if (ixgbe_vmdq_mode_check(hw) < 0)
4334                 return -ENOTSUP;
4335
4336         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4337                 return -EINVAL;
4338
4339         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4340                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4341                         mirror_conf->rule_type);
4342                 return -EINVAL;
4343         }
4344
4345         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4346                 mirror_type |= IXGBE_MRCTL_VLME;
4347                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4348                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
4349                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4350                                 /* search vlan id related pool vlan filter index */
4351                                 reg_index = ixgbe_find_vlvf_slot(hw,
4352                                                 mirror_conf->vlan.vlan_id[i]);
4353                                 if(reg_index < 0)
4354                                         return -EINVAL;
4355                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4356                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4357                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4358                                       mirror_conf->vlan.vlan_id[i]))
4359                                         vlan_mask |= (1ULL << reg_index);
4360                                 else
4361                                         return -EINVAL;
4362                         }
4363                 }
4364
4365                 if (on) {
4366                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4367                         mv_msb = vlan_mask >> vlan_mask_offset;
4368
4369                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4370                                                 mirror_conf->vlan.vlan_mask;
4371                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4372                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
4373                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4374                                                 mirror_conf->vlan.vlan_id[i];
4375                         }
4376                 } else {
4377                         mv_lsb = 0;
4378                         mv_msb = 0;
4379                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4380                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4381                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4382                 }
4383         }
4384
4385         /*
4386          * if enable pool mirror, write related pool mask register,if disable
4387          * pool mirror, clear PFMRVM register
4388          */
4389         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4390                 mirror_type |= IXGBE_MRCTL_VPME;
4391                 if (on) {
4392                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4393                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4394                         mr_info->mr_conf[rule_id].pool_mask =
4395                                         mirror_conf->pool_mask;
4396
4397                 } else {
4398                         mp_lsb = 0;
4399                         mp_msb = 0;
4400                         mr_info->mr_conf[rule_id].pool_mask = 0;
4401                 }
4402         }
4403         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4404                 mirror_type |= IXGBE_MRCTL_UPME;
4405         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4406                 mirror_type |= IXGBE_MRCTL_DPME;
4407
4408         /* read  mirror control register and recalculate it */
4409         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4410
4411         if (on) {
4412                 mr_ctl |= mirror_type;
4413                 mr_ctl &= mirror_rule_mask;
4414                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4415         } else
4416                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4417
4418         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4419         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4420
4421         /* write mirrror control  register */
4422         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4423
4424         /* write pool mirrror control  register */
4425         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4426                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4427                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4428                                 mp_msb);
4429         }
4430         /* write VLAN mirrror control  register */
4431         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4432                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4433                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4434                                 mv_msb);
4435         }
4436
4437         return 0;
4438 }
4439
4440 static int
4441 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4442 {
4443         int mr_ctl = 0;
4444         uint32_t lsb_val = 0;
4445         uint32_t msb_val = 0;
4446         const uint8_t rule_mr_offset = 4;
4447
4448         struct ixgbe_hw *hw =
4449                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4450         struct ixgbe_mirror_info *mr_info =
4451                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4452
4453         if (ixgbe_vmdq_mode_check(hw) < 0)
4454                 return (-ENOTSUP);
4455
4456         memset(&mr_info->mr_conf[rule_id], 0,
4457                 sizeof(struct rte_eth_mirror_conf));
4458
4459         /* clear PFVMCTL register */
4460         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4461
4462         /* clear pool mask register */
4463         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4464         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4465
4466         /* clear vlan mask register */
4467         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4468         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4469
4470         return 0;
4471 }
4472
4473 static int
4474 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4475 {
4476         uint32_t mask;
4477         struct ixgbe_hw *hw =
4478                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4479
4480         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4481         mask |= (1 << IXGBE_MISC_VEC_ID);
4482         RTE_SET_USED(queue_id);
4483         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4484
4485         rte_intr_enable(&dev->pci_dev->intr_handle);
4486
4487         return 0;
4488 }
4489
4490 static int
4491 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4492 {
4493         uint32_t mask;
4494         struct ixgbe_hw *hw =
4495                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4496
4497         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4498         mask &= ~(1 << IXGBE_MISC_VEC_ID);
4499         RTE_SET_USED(queue_id);
4500         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4501
4502         return 0;
4503 }
4504
4505 static int
4506 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4507 {
4508         uint32_t mask;
4509         struct ixgbe_hw *hw =
4510                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4511         struct ixgbe_interrupt *intr =
4512                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4513
4514         if (queue_id < 16) {
4515                 ixgbe_disable_intr(hw);
4516                 intr->mask |= (1 << queue_id);
4517                 ixgbe_enable_intr(dev);
4518         } else if (queue_id < 32) {
4519                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4520                 mask &= (1 << queue_id);
4521                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4522         } else if (queue_id < 64) {
4523                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4524                 mask &= (1 << (queue_id - 32));
4525                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4526         }
4527         rte_intr_enable(&dev->pci_dev->intr_handle);
4528
4529         return 0;
4530 }
4531
4532 static int
4533 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4534 {
4535         uint32_t mask;
4536         struct ixgbe_hw *hw =
4537                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4538         struct ixgbe_interrupt *intr =
4539                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4540
4541         if (queue_id < 16) {
4542                 ixgbe_disable_intr(hw);
4543                 intr->mask &= ~(1 << queue_id);
4544                 ixgbe_enable_intr(dev);
4545         } else if (queue_id < 32) {
4546                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4547                 mask &= ~(1 << queue_id);
4548                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4549         } else if (queue_id < 64) {
4550                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4551                 mask &= ~(1 << (queue_id - 32));
4552                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4553         }
4554
4555         return 0;
4556 }
4557
4558 static void
4559 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4560                      uint8_t queue, uint8_t msix_vector)
4561 {
4562         uint32_t tmp, idx;
4563
4564         if (direction == -1) {
4565                 /* other causes */
4566                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4567                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4568                 tmp &= ~0xFF;
4569                 tmp |= msix_vector;
4570                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4571         } else {
4572                 /* rx or tx cause */
4573                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4574                 idx = ((16 * (queue & 1)) + (8 * direction));
4575                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4576                 tmp &= ~(0xFF << idx);
4577                 tmp |= (msix_vector << idx);
4578                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4579         }
4580 }
4581
4582 /**
4583  * set the IVAR registers, mapping interrupt causes to vectors
4584  * @param hw
4585  *  pointer to ixgbe_hw struct
4586  * @direction
4587  *  0 for Rx, 1 for Tx, -1 for other causes
4588  * @queue
4589  *  queue to map the corresponding interrupt to
4590  * @msix_vector
4591  *  the vector to map to the corresponding queue
4592  */
4593 static void
4594 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4595                    uint8_t queue, uint8_t msix_vector)
4596 {
4597         uint32_t tmp, idx;
4598
4599         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4600         if (hw->mac.type == ixgbe_mac_82598EB) {
4601                 if (direction == -1)
4602                         direction = 0;
4603                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4604                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4605                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4606                 tmp |= (msix_vector << (8 * (queue & 0x3)));
4607                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4608         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4609                         (hw->mac.type == ixgbe_mac_X540)) {
4610                 if (direction == -1) {
4611                         /* other causes */
4612                         idx = ((queue & 1) * 8);
4613                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4614                         tmp &= ~(0xFF << idx);
4615                         tmp |= (msix_vector << idx);
4616                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4617                 } else {
4618                         /* rx or tx causes */
4619                         idx = ((16 * (queue & 1)) + (8 * direction));
4620                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4621                         tmp &= ~(0xFF << idx);
4622                         tmp |= (msix_vector << idx);
4623                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4624                 }
4625         }
4626 }
4627
4628 static void
4629 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4630 {
4631         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4632         struct ixgbe_hw *hw =
4633                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4634         uint32_t q_idx;
4635         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4636
4637         /* won't configure msix register if no mapping is done
4638          * between intr vector and event fd.
4639          */
4640         if (!rte_intr_dp_is_en(intr_handle))
4641                 return;
4642
4643         /* Configure all RX queues of VF */
4644         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4645                 /* Force all queue use vector 0,
4646                  * as IXGBE_VF_MAXMSIVECOTR = 1
4647                  */
4648                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4649                 intr_handle->intr_vec[q_idx] = vector_idx;
4650         }
4651
4652         /* Configure VF Rx queue ivar */
4653         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4654 }
4655
4656 /**
4657  * Sets up the hardware to properly generate MSI-X interrupts
4658  * @hw
4659  *  board private structure
4660  */
4661 static void
4662 ixgbe_configure_msix(struct rte_eth_dev *dev)
4663 {
4664         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4665         struct ixgbe_hw *hw =
4666                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4667         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4668         uint32_t vec = IXGBE_MISC_VEC_ID;
4669         uint32_t mask;
4670         uint32_t gpie;
4671
4672         /* won't configure msix register if no mapping is done
4673          * between intr vector and event fd
4674          */
4675         if (!rte_intr_dp_is_en(intr_handle))
4676                 return;
4677
4678         if (rte_intr_allow_others(intr_handle))
4679                 vec = base = IXGBE_RX_VEC_START;
4680
4681         /* setup GPIE for MSI-x mode */
4682         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4683         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4684                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4685         /* auto clearing and auto setting corresponding bits in EIMS
4686          * when MSI-X interrupt is triggered
4687          */
4688         if (hw->mac.type == ixgbe_mac_82598EB) {
4689                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4690         } else {
4691                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4692                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4693         }
4694         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4695
4696         /* Populate the IVAR table and set the ITR values to the
4697          * corresponding register.
4698          */
4699         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4700              queue_id++) {
4701                 /* by default, 1:1 mapping */
4702                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4703                 intr_handle->intr_vec[queue_id] = vec;
4704                 if (vec < base + intr_handle->nb_efd - 1)
4705                         vec++;
4706         }
4707
4708         switch (hw->mac.type) {
4709         case ixgbe_mac_82598EB:
4710                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4711                                    IXGBE_MISC_VEC_ID);
4712                 break;
4713         case ixgbe_mac_82599EB:
4714         case ixgbe_mac_X540:
4715                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
4716                 break;
4717         default:
4718                 break;
4719         }
4720         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
4721                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4722
4723         /* set up to autoclear timer, and the vectors */
4724         mask = IXGBE_EIMS_ENABLE_MASK;
4725         mask &= ~(IXGBE_EIMS_OTHER |
4726                   IXGBE_EIMS_MAILBOX |
4727                   IXGBE_EIMS_LSC);
4728
4729         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4730 }
4731
4732 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4733         uint16_t queue_idx, uint16_t tx_rate)
4734 {
4735         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4736         uint32_t rf_dec, rf_int;
4737         uint32_t bcnrc_val;
4738         uint16_t link_speed = dev->data->dev_link.link_speed;
4739
4740         if (queue_idx >= hw->mac.max_tx_queues)
4741                 return -EINVAL;
4742
4743         if (tx_rate != 0) {
4744                 /* Calculate the rate factor values to set */
4745                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4746                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4747                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4748
4749                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4750                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4751                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4752                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4753         } else {
4754                 bcnrc_val = 0;
4755         }
4756
4757         /*
4758          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4759          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4760          * set as 0x4.
4761          */
4762         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4763                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4764                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
4765                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4766                         IXGBE_MMW_SIZE_JUMBO_FRAME);
4767         else
4768                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4769                         IXGBE_MMW_SIZE_DEFAULT);
4770
4771         /* Set RTTBCNRC of queue X */
4772         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4773         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4774         IXGBE_WRITE_FLUSH(hw);
4775
4776         return 0;
4777 }
4778
4779 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4780         uint16_t tx_rate, uint64_t q_msk)
4781 {
4782         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4783         struct ixgbe_vf_info *vfinfo =
4784                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4785         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4786         uint32_t queue_stride =
4787                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4788         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4789         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4790         uint16_t total_rate = 0;
4791
4792         if (queue_end >= hw->mac.max_tx_queues)
4793                 return -EINVAL;
4794
4795         if (vfinfo != NULL) {
4796                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4797                         if (vf_idx == vf)
4798                                 continue;
4799                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4800                                 idx++)
4801                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
4802                 }
4803         } else
4804                 return -EINVAL;
4805
4806         /* Store tx_rate for this vf. */
4807         for (idx = 0; idx < nb_q_per_pool; idx++) {
4808                 if (((uint64_t)0x1 << idx) & q_msk) {
4809                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
4810                                 vfinfo[vf].tx_rate[idx] = tx_rate;
4811                         total_rate += tx_rate;
4812                 }
4813         }
4814
4815         if (total_rate > dev->data->dev_link.link_speed) {
4816                 /*
4817                  * Reset stored TX rate of the VF if it causes exceed
4818                  * link speed.
4819                  */
4820                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4821                 return -EINVAL;
4822         }
4823
4824         /* Set RTTBCNRC of each queue/pool for vf X  */
4825         for (; queue_idx <= queue_end; queue_idx++) {
4826                 if (0x1 & q_msk)
4827                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4828                 q_msk = q_msk >> 1;
4829         }
4830
4831         return 0;
4832 }
4833
4834 static void
4835 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4836                      __attribute__((unused)) uint32_t index,
4837                      __attribute__((unused)) uint32_t pool)
4838 {
4839         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4840         int diag;
4841
4842         /*
4843          * On a 82599 VF, adding again the same MAC addr is not an idempotent
4844          * operation. Trap this case to avoid exhausting the [very limited]
4845          * set of PF resources used to store VF MAC addresses.
4846          */
4847         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4848                 return;
4849         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4850         if (diag == 0)
4851                 return;
4852         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
4853 }
4854
4855 static void
4856 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
4857 {
4858         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4859         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
4860         struct ether_addr *mac_addr;
4861         uint32_t i;
4862         int diag;
4863
4864         /*
4865          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
4866          * not support the deletion of a given MAC address.
4867          * Instead, it imposes to delete all MAC addresses, then to add again
4868          * all MAC addresses with the exception of the one to be deleted.
4869          */
4870         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
4871
4872         /*
4873          * Add again all MAC addresses, with the exception of the deleted one
4874          * and of the permanent MAC address.
4875          */
4876         for (i = 0, mac_addr = dev->data->mac_addrs;
4877              i < hw->mac.num_rar_entries; i++, mac_addr++) {
4878                 /* Skip the deleted MAC address */
4879                 if (i == index)
4880                         continue;
4881                 /* Skip NULL MAC addresses */
4882                 if (is_zero_ether_addr(mac_addr))
4883                         continue;
4884                 /* Skip the permanent MAC address */
4885                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4886                         continue;
4887                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4888                 if (diag != 0)
4889                         PMD_DRV_LOG(ERR,
4890                                     "Adding again MAC address "
4891                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
4892                                     "diag=%d",
4893                                     mac_addr->addr_bytes[0],
4894                                     mac_addr->addr_bytes[1],
4895                                     mac_addr->addr_bytes[2],
4896                                     mac_addr->addr_bytes[3],
4897                                     mac_addr->addr_bytes[4],
4898                                     mac_addr->addr_bytes[5],
4899                                     diag);
4900         }
4901 }
4902
4903 static void
4904 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4905 {
4906         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4907
4908         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
4909 }
4910
4911 #define MAC_TYPE_FILTER_SUP(type)    do {\
4912         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4913                 (type) != ixgbe_mac_X550)\
4914                 return -ENOTSUP;\
4915 } while (0)
4916
4917 static int
4918 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
4919                         struct rte_eth_syn_filter *filter,
4920                         bool add)
4921 {
4922         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4923         uint32_t synqf;
4924
4925         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4926                 return -EINVAL;
4927
4928         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4929
4930         if (add) {
4931                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
4932                         return -EINVAL;
4933                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
4934                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
4935
4936                 if (filter->hig_pri)
4937                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
4938                 else
4939                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
4940         } else {
4941                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
4942                         return -ENOENT;
4943                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
4944         }
4945         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
4946         IXGBE_WRITE_FLUSH(hw);
4947         return 0;
4948 }
4949
4950 static int
4951 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
4952                         struct rte_eth_syn_filter *filter)
4953 {
4954         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4955         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4956
4957         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
4958                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
4959                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
4960                 return 0;
4961         }
4962         return -ENOENT;
4963 }
4964
4965 static int
4966 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
4967                         enum rte_filter_op filter_op,
4968                         void *arg)
4969 {
4970         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4971         int ret;
4972
4973         MAC_TYPE_FILTER_SUP(hw->mac.type);
4974
4975         if (filter_op == RTE_ETH_FILTER_NOP)
4976                 return 0;
4977
4978         if (arg == NULL) {
4979                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4980                             filter_op);
4981                 return -EINVAL;
4982         }
4983
4984         switch (filter_op) {
4985         case RTE_ETH_FILTER_ADD:
4986                 ret = ixgbe_syn_filter_set(dev,
4987                                 (struct rte_eth_syn_filter *)arg,
4988                                 TRUE);
4989                 break;
4990         case RTE_ETH_FILTER_DELETE:
4991                 ret = ixgbe_syn_filter_set(dev,
4992                                 (struct rte_eth_syn_filter *)arg,
4993                                 FALSE);
4994                 break;
4995         case RTE_ETH_FILTER_GET:
4996                 ret = ixgbe_syn_filter_get(dev,
4997                                 (struct rte_eth_syn_filter *)arg);
4998                 break;
4999         default:
5000                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5001                 ret = -EINVAL;
5002                 break;
5003         }
5004
5005         return ret;
5006 }
5007
5008
5009 static inline enum ixgbe_5tuple_protocol
5010 convert_protocol_type(uint8_t protocol_value)
5011 {
5012         if (protocol_value == IPPROTO_TCP)
5013                 return IXGBE_FILTER_PROTOCOL_TCP;
5014         else if (protocol_value == IPPROTO_UDP)
5015                 return IXGBE_FILTER_PROTOCOL_UDP;
5016         else if (protocol_value == IPPROTO_SCTP)
5017                 return IXGBE_FILTER_PROTOCOL_SCTP;
5018         else
5019                 return IXGBE_FILTER_PROTOCOL_NONE;
5020 }
5021
5022 /*
5023  * add a 5tuple filter
5024  *
5025  * @param
5026  * dev: Pointer to struct rte_eth_dev.
5027  * index: the index the filter allocates.
5028  * filter: ponter to the filter that will be added.
5029  * rx_queue: the queue id the filter assigned to.
5030  *
5031  * @return
5032  *    - On success, zero.
5033  *    - On failure, a negative value.
5034  */
5035 static int
5036 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5037                         struct ixgbe_5tuple_filter *filter)
5038 {
5039         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5040         struct ixgbe_filter_info *filter_info =
5041                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5042         int i, idx, shift;
5043         uint32_t ftqf, sdpqf;
5044         uint32_t l34timir = 0;
5045         uint8_t mask = 0xff;
5046
5047         /*
5048          * look for an unused 5tuple filter index,
5049          * and insert the filter to list.
5050          */
5051         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5052                 idx = i / (sizeof(uint32_t) * NBBY);
5053                 shift = i % (sizeof(uint32_t) * NBBY);
5054                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5055                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5056                         filter->index = i;
5057                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5058                                           filter,
5059                                           entries);
5060                         break;
5061                 }
5062         }
5063         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5064                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5065                 return -ENOSYS;
5066         }
5067
5068         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5069                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5070         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5071
5072         ftqf = (uint32_t)(filter->filter_info.proto &
5073                 IXGBE_FTQF_PROTOCOL_MASK);
5074         ftqf |= (uint32_t)((filter->filter_info.priority &
5075                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5076         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5077                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5078         if (filter->filter_info.dst_ip_mask == 0)
5079                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5080         if (filter->filter_info.src_port_mask == 0)
5081                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5082         if (filter->filter_info.dst_port_mask == 0)
5083                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5084         if (filter->filter_info.proto_mask == 0)
5085                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5086         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5087         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5088         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5089
5090         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5091         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5092         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5093         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5094
5095         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5096         l34timir |= (uint32_t)(filter->queue <<
5097                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5098         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5099         return 0;
5100 }
5101
5102 /*
5103  * remove a 5tuple filter
5104  *
5105  * @param
5106  * dev: Pointer to struct rte_eth_dev.
5107  * filter: the pointer of the filter will be removed.
5108  */
5109 static void
5110 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5111                         struct ixgbe_5tuple_filter *filter)
5112 {
5113         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5114         struct ixgbe_filter_info *filter_info =
5115                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5116         uint16_t index = filter->index;
5117
5118         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5119                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5120         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5121         rte_free(filter);
5122
5123         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5124         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5125         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5126         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5127         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5128 }
5129
5130 static int
5131 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5132 {
5133         struct ixgbe_hw *hw;
5134         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5135
5136         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5137
5138         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5139                 return -EINVAL;
5140
5141         /* refuse mtu that requires the support of scattered packets when this
5142          * feature has not been enabled before. */
5143         if (!dev->data->scattered_rx &&
5144             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5145              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5146                 return -EINVAL;
5147
5148         /*
5149          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5150          * request of the version 2.0 of the mailbox API.
5151          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5152          * of the mailbox API.
5153          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5154          * prior to 3.11.33 which contains the following change:
5155          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5156          */
5157         ixgbevf_rlpml_set_vf(hw, max_frame);
5158
5159         /* update max frame size */
5160         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5161         return 0;
5162 }
5163
5164 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5165         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5166                 return -ENOTSUP;\
5167 } while (0)
5168
5169 static inline struct ixgbe_5tuple_filter *
5170 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5171                         struct ixgbe_5tuple_filter_info *key)
5172 {
5173         struct ixgbe_5tuple_filter *it;
5174
5175         TAILQ_FOREACH(it, filter_list, entries) {
5176                 if (memcmp(key, &it->filter_info,
5177                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5178                         return it;
5179                 }
5180         }
5181         return NULL;
5182 }
5183
5184 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5185 static inline int
5186 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5187                         struct ixgbe_5tuple_filter_info *filter_info)
5188 {
5189         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5190                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5191                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5192                 return -EINVAL;
5193
5194         switch (filter->dst_ip_mask) {
5195         case UINT32_MAX:
5196                 filter_info->dst_ip_mask = 0;
5197                 filter_info->dst_ip = filter->dst_ip;
5198                 break;
5199         case 0:
5200                 filter_info->dst_ip_mask = 1;
5201                 break;
5202         default:
5203                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5204                 return -EINVAL;
5205         }
5206
5207         switch (filter->src_ip_mask) {
5208         case UINT32_MAX:
5209                 filter_info->src_ip_mask = 0;
5210                 filter_info->src_ip = filter->src_ip;
5211                 break;
5212         case 0:
5213                 filter_info->src_ip_mask = 1;
5214                 break;
5215         default:
5216                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5217                 return -EINVAL;
5218         }
5219
5220         switch (filter->dst_port_mask) {
5221         case UINT16_MAX:
5222                 filter_info->dst_port_mask = 0;
5223                 filter_info->dst_port = filter->dst_port;
5224                 break;
5225         case 0:
5226                 filter_info->dst_port_mask = 1;
5227                 break;
5228         default:
5229                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5230                 return -EINVAL;
5231         }
5232
5233         switch (filter->src_port_mask) {
5234         case UINT16_MAX:
5235                 filter_info->src_port_mask = 0;
5236                 filter_info->src_port = filter->src_port;
5237                 break;
5238         case 0:
5239                 filter_info->src_port_mask = 1;
5240                 break;
5241         default:
5242                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5243                 return -EINVAL;
5244         }
5245
5246         switch (filter->proto_mask) {
5247         case UINT8_MAX:
5248                 filter_info->proto_mask = 0;
5249                 filter_info->proto =
5250                         convert_protocol_type(filter->proto);
5251                 break;
5252         case 0:
5253                 filter_info->proto_mask = 1;
5254                 break;
5255         default:
5256                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5257                 return -EINVAL;
5258         }
5259
5260         filter_info->priority = (uint8_t)filter->priority;
5261         return 0;
5262 }
5263
5264 /*
5265  * add or delete a ntuple filter
5266  *
5267  * @param
5268  * dev: Pointer to struct rte_eth_dev.
5269  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5270  * add: if true, add filter, if false, remove filter
5271  *
5272  * @return
5273  *    - On success, zero.
5274  *    - On failure, a negative value.
5275  */
5276 static int
5277 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5278                         struct rte_eth_ntuple_filter *ntuple_filter,
5279                         bool add)
5280 {
5281         struct ixgbe_filter_info *filter_info =
5282                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5283         struct ixgbe_5tuple_filter_info filter_5tuple;
5284         struct ixgbe_5tuple_filter *filter;
5285         int ret;
5286
5287         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5288                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5289                 return -EINVAL;
5290         }
5291
5292         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5293         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5294         if (ret < 0)
5295                 return ret;
5296
5297         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5298                                          &filter_5tuple);
5299         if (filter != NULL && add) {
5300                 PMD_DRV_LOG(ERR, "filter exists.");
5301                 return -EEXIST;
5302         }
5303         if (filter == NULL && !add) {
5304                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5305                 return -ENOENT;
5306         }
5307
5308         if (add) {
5309                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5310                                 sizeof(struct ixgbe_5tuple_filter), 0);
5311                 if (filter == NULL)
5312                         return -ENOMEM;
5313                 (void)rte_memcpy(&filter->filter_info,
5314                                  &filter_5tuple,
5315                                  sizeof(struct ixgbe_5tuple_filter_info));
5316                 filter->queue = ntuple_filter->queue;
5317                 ret = ixgbe_add_5tuple_filter(dev, filter);
5318                 if (ret < 0) {
5319                         rte_free(filter);
5320                         return ret;
5321                 }
5322         } else
5323                 ixgbe_remove_5tuple_filter(dev, filter);
5324
5325         return 0;
5326 }
5327
5328 /*
5329  * get a ntuple filter
5330  *
5331  * @param
5332  * dev: Pointer to struct rte_eth_dev.
5333  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5334  *
5335  * @return
5336  *    - On success, zero.
5337  *    - On failure, a negative value.
5338  */
5339 static int
5340 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5341                         struct rte_eth_ntuple_filter *ntuple_filter)
5342 {
5343         struct ixgbe_filter_info *filter_info =
5344                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5345         struct ixgbe_5tuple_filter_info filter_5tuple;
5346         struct ixgbe_5tuple_filter *filter;
5347         int ret;
5348
5349         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5350                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5351                 return -EINVAL;
5352         }
5353
5354         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5355         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5356         if (ret < 0)
5357                 return ret;
5358
5359         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5360                                          &filter_5tuple);
5361         if (filter == NULL) {
5362                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5363                 return -ENOENT;
5364         }
5365         ntuple_filter->queue = filter->queue;
5366         return 0;
5367 }
5368
5369 /*
5370  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5371  * @dev: pointer to rte_eth_dev structure
5372  * @filter_op:operation will be taken.
5373  * @arg: a pointer to specific structure corresponding to the filter_op
5374  *
5375  * @return
5376  *    - On success, zero.
5377  *    - On failure, a negative value.
5378  */
5379 static int
5380 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5381                                 enum rte_filter_op filter_op,
5382                                 void *arg)
5383 {
5384         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5385         int ret;
5386
5387         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5388
5389         if (filter_op == RTE_ETH_FILTER_NOP)
5390                 return 0;
5391
5392         if (arg == NULL) {
5393                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5394                             filter_op);
5395                 return -EINVAL;
5396         }
5397
5398         switch (filter_op) {
5399         case RTE_ETH_FILTER_ADD:
5400                 ret = ixgbe_add_del_ntuple_filter(dev,
5401                         (struct rte_eth_ntuple_filter *)arg,
5402                         TRUE);
5403                 break;
5404         case RTE_ETH_FILTER_DELETE:
5405                 ret = ixgbe_add_del_ntuple_filter(dev,
5406                         (struct rte_eth_ntuple_filter *)arg,
5407                         FALSE);
5408                 break;
5409         case RTE_ETH_FILTER_GET:
5410                 ret = ixgbe_get_ntuple_filter(dev,
5411                         (struct rte_eth_ntuple_filter *)arg);
5412                 break;
5413         default:
5414                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5415                 ret = -EINVAL;
5416                 break;
5417         }
5418         return ret;
5419 }
5420
5421 static inline int
5422 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5423                         uint16_t ethertype)
5424 {
5425         int i;
5426
5427         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5428                 if (filter_info->ethertype_filters[i] == ethertype &&
5429                     (filter_info->ethertype_mask & (1 << i)))
5430                         return i;
5431         }
5432         return -1;
5433 }
5434
5435 static inline int
5436 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5437                         uint16_t ethertype)
5438 {
5439         int i;
5440
5441         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5442                 if (!(filter_info->ethertype_mask & (1 << i))) {
5443                         filter_info->ethertype_mask |= 1 << i;
5444                         filter_info->ethertype_filters[i] = ethertype;
5445                         return i;
5446                 }
5447         }
5448         return -1;
5449 }
5450
5451 static inline int
5452 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5453                         uint8_t idx)
5454 {
5455         if (idx >= IXGBE_MAX_ETQF_FILTERS)
5456                 return -1;
5457         filter_info->ethertype_mask &= ~(1 << idx);
5458         filter_info->ethertype_filters[idx] = 0;
5459         return idx;
5460 }
5461
5462 static int
5463 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5464                         struct rte_eth_ethertype_filter *filter,
5465                         bool add)
5466 {
5467         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5468         struct ixgbe_filter_info *filter_info =
5469                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5470         uint32_t etqf = 0;
5471         uint32_t etqs = 0;
5472         int ret;
5473
5474         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5475                 return -EINVAL;
5476
5477         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5478                 filter->ether_type == ETHER_TYPE_IPv6) {
5479                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5480                         " ethertype filter.", filter->ether_type);
5481                 return -EINVAL;
5482         }
5483
5484         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5485                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5486                 return -EINVAL;
5487         }
5488         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5489                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5490                 return -EINVAL;
5491         }
5492
5493         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5494         if (ret >= 0 && add) {
5495                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5496                             filter->ether_type);
5497                 return -EEXIST;
5498         }
5499         if (ret < 0 && !add) {
5500                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5501                             filter->ether_type);
5502                 return -ENOENT;
5503         }
5504
5505         if (add) {
5506                 ret = ixgbe_ethertype_filter_insert(filter_info,
5507                         filter->ether_type);
5508                 if (ret < 0) {
5509                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
5510                         return -ENOSYS;
5511                 }
5512                 etqf = IXGBE_ETQF_FILTER_EN;
5513                 etqf |= (uint32_t)filter->ether_type;
5514                 etqs |= (uint32_t)((filter->queue <<
5515                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
5516                                     IXGBE_ETQS_RX_QUEUE);
5517                 etqs |= IXGBE_ETQS_QUEUE_EN;
5518         } else {
5519                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5520                 if (ret < 0)
5521                         return -ENOSYS;
5522         }
5523         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5524         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5525         IXGBE_WRITE_FLUSH(hw);
5526
5527         return 0;
5528 }
5529
5530 static int
5531 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5532                         struct rte_eth_ethertype_filter *filter)
5533 {
5534         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5535         struct ixgbe_filter_info *filter_info =
5536                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5537         uint32_t etqf, etqs;
5538         int ret;
5539
5540         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5541         if (ret < 0) {
5542                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5543                             filter->ether_type);
5544                 return -ENOENT;
5545         }
5546
5547         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5548         if (etqf & IXGBE_ETQF_FILTER_EN) {
5549                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5550                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5551                 filter->flags = 0;
5552                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5553                                IXGBE_ETQS_RX_QUEUE_SHIFT;
5554                 return 0;
5555         }
5556         return -ENOENT;
5557 }
5558
5559 /*
5560  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5561  * @dev: pointer to rte_eth_dev structure
5562  * @filter_op:operation will be taken.
5563  * @arg: a pointer to specific structure corresponding to the filter_op
5564  */
5565 static int
5566 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5567                                 enum rte_filter_op filter_op,
5568                                 void *arg)
5569 {
5570         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5571         int ret;
5572
5573         MAC_TYPE_FILTER_SUP(hw->mac.type);
5574
5575         if (filter_op == RTE_ETH_FILTER_NOP)
5576                 return 0;
5577
5578         if (arg == NULL) {
5579                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5580                             filter_op);
5581                 return -EINVAL;
5582         }
5583
5584         switch (filter_op) {
5585         case RTE_ETH_FILTER_ADD:
5586                 ret = ixgbe_add_del_ethertype_filter(dev,
5587                         (struct rte_eth_ethertype_filter *)arg,
5588                         TRUE);
5589                 break;
5590         case RTE_ETH_FILTER_DELETE:
5591                 ret = ixgbe_add_del_ethertype_filter(dev,
5592                         (struct rte_eth_ethertype_filter *)arg,
5593                         FALSE);
5594                 break;
5595         case RTE_ETH_FILTER_GET:
5596                 ret = ixgbe_get_ethertype_filter(dev,
5597                         (struct rte_eth_ethertype_filter *)arg);
5598                 break;
5599         default:
5600                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5601                 ret = -EINVAL;
5602                 break;
5603         }
5604         return ret;
5605 }
5606
5607 static int
5608 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5609                      enum rte_filter_type filter_type,
5610                      enum rte_filter_op filter_op,
5611                      void *arg)
5612 {
5613         int ret = -EINVAL;
5614
5615         switch (filter_type) {
5616         case RTE_ETH_FILTER_NTUPLE:
5617                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5618                 break;
5619         case RTE_ETH_FILTER_ETHERTYPE:
5620                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5621                 break;
5622         case RTE_ETH_FILTER_SYN:
5623                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5624                 break;
5625         case RTE_ETH_FILTER_FDIR:
5626                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5627                 break;
5628         default:
5629                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5630                                                         filter_type);
5631                 break;
5632         }
5633
5634         return ret;
5635 }
5636
5637 static u8 *
5638 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5639                         u8 **mc_addr_ptr, u32 *vmdq)
5640 {
5641         u8 *mc_addr;
5642
5643         *vmdq = 0;
5644         mc_addr = *mc_addr_ptr;
5645         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5646         return mc_addr;
5647 }
5648
5649 static int
5650 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5651                           struct ether_addr *mc_addr_set,
5652                           uint32_t nb_mc_addr)
5653 {
5654         struct ixgbe_hw *hw;
5655         u8 *mc_addr_list;
5656
5657         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5658         mc_addr_list = (u8 *)mc_addr_set;
5659         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5660                                          ixgbe_dev_addr_list_itr, TRUE);
5661 }
5662
5663 static int
5664 ixgbe_timesync_enable(struct rte_eth_dev *dev)
5665 {
5666         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5667         uint32_t tsync_ctl;
5668         uint32_t tsauxc;
5669
5670         /* Enable system time for platforms where it isn't on by default. */
5671         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
5672         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
5673         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
5674
5675         /* Start incrementing the register used to timestamp PTP packets. */
5676         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, IXGBE_TIMINCA_INIT);
5677
5678         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5679         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
5680                         (ETHER_TYPE_1588 |
5681                          IXGBE_ETQF_FILTER_EN |
5682                          IXGBE_ETQF_1588));
5683
5684         /* Enable timestamping of received PTP packets. */
5685         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5686         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
5687         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5688
5689         /* Enable timestamping of transmitted PTP packets. */
5690         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5691         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
5692         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5693
5694         return 0;
5695 }
5696
5697 static int
5698 ixgbe_timesync_disable(struct rte_eth_dev *dev)
5699 {
5700         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5701         uint32_t tsync_ctl;
5702
5703         /* Disable timestamping of transmitted PTP packets. */
5704         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5705         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
5706         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5707
5708         /* Disable timestamping of received PTP packets. */
5709         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5710         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
5711         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5712
5713         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5714         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
5715
5716         /* Stop incrementating the System Time registers. */
5717         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
5718
5719         return 0;
5720 }
5721
5722 static int
5723 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5724                                  struct timespec *timestamp,
5725                                  uint32_t flags __rte_unused)
5726 {
5727         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5728         uint32_t tsync_rxctl;
5729         uint32_t rx_stmpl;
5730         uint32_t rx_stmph;
5731
5732         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5733         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
5734                 return -EINVAL;
5735
5736         rx_stmpl = IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5737         rx_stmph = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
5738
5739         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
5740         timestamp->tv_nsec = 0;
5741
5742         return  0;
5743 }
5744
5745 static int
5746 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5747                                  struct timespec *timestamp)
5748 {
5749         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5750         uint32_t tsync_txctl;
5751         uint32_t tx_stmpl;
5752         uint32_t tx_stmph;
5753
5754         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5755         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
5756                 return -EINVAL;
5757
5758         tx_stmpl = IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5759         tx_stmph = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
5760
5761         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
5762         timestamp->tv_nsec = 0;
5763
5764         return  0;
5765 }
5766
5767 static int
5768 ixgbe_get_reg_length(struct rte_eth_dev *dev)
5769 {
5770         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5771         int count = 0;
5772         int g_ind = 0;
5773         const struct reg_info *reg_group;
5774         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5775                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5776
5777         while ((reg_group = reg_set[g_ind++]))
5778                 count += ixgbe_regs_group_count(reg_group);
5779
5780         return count;
5781 }
5782
5783 static int
5784 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5785 {
5786         int count = 0;
5787         int g_ind = 0;
5788         const struct reg_info *reg_group;
5789
5790         while ((reg_group = ixgbevf_regs[g_ind++]))
5791                 count += ixgbe_regs_group_count(reg_group);
5792
5793         return count;
5794 }
5795
5796 static int
5797 ixgbe_get_regs(struct rte_eth_dev *dev,
5798               struct rte_dev_reg_info *regs)
5799 {
5800         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5801         uint32_t *data = regs->data;
5802         int g_ind = 0;
5803         int count = 0;
5804         const struct reg_info *reg_group;
5805         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5806                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5807
5808         /* Support only full register dump */
5809         if ((regs->length == 0) ||
5810             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
5811                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5812                         hw->device_id;
5813                 while ((reg_group = reg_set[g_ind++]))
5814                         count += ixgbe_read_regs_group(dev, &data[count],
5815                                 reg_group);
5816                 return 0;
5817         }
5818
5819         return -ENOTSUP;
5820 }
5821
5822 static int
5823 ixgbevf_get_regs(struct rte_eth_dev *dev,
5824                 struct rte_dev_reg_info *regs)
5825 {
5826         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5827         uint32_t *data = regs->data;
5828         int g_ind = 0;
5829         int count = 0;
5830         const struct reg_info *reg_group;
5831
5832         /* Support only full register dump */
5833         if ((regs->length == 0) ||
5834             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
5835                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5836                         hw->device_id;
5837                 while ((reg_group = ixgbevf_regs[g_ind++]))
5838                         count += ixgbe_read_regs_group(dev, &data[count],
5839                                                       reg_group);
5840                 return 0;
5841         }
5842
5843         return -ENOTSUP;
5844 }
5845
5846 static int
5847 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
5848 {
5849         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5850
5851         /* Return unit is byte count */
5852         return hw->eeprom.word_size * 2;
5853 }
5854
5855 static int
5856 ixgbe_get_eeprom(struct rte_eth_dev *dev,
5857                 struct rte_dev_eeprom_info *in_eeprom)
5858 {
5859         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5860         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5861         uint16_t *data = in_eeprom->data;
5862         int first, length;
5863
5864         first = in_eeprom->offset >> 1;
5865         length = in_eeprom->length >> 1;
5866         if ((first > hw->eeprom.word_size) ||
5867             ((first + length) > hw->eeprom.word_size))
5868                 return -EINVAL;
5869
5870         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5871
5872         return eeprom->ops.read_buffer(hw, first, length, data);
5873 }
5874
5875 static int
5876 ixgbe_set_eeprom(struct rte_eth_dev *dev,
5877                 struct rte_dev_eeprom_info *in_eeprom)
5878 {
5879         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5880         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5881         uint16_t *data = in_eeprom->data;
5882         int first, length;
5883
5884         first = in_eeprom->offset >> 1;
5885         length = in_eeprom->length >> 1;
5886         if ((first > hw->eeprom.word_size) ||
5887             ((first + length) > hw->eeprom.word_size))
5888                 return -EINVAL;
5889
5890         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5891
5892         return eeprom->ops.write_buffer(hw,  first, length, data);
5893 }
5894
5895 uint16_t
5896 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
5897         switch (mac_type) {
5898         case ixgbe_mac_X550:
5899         case ixgbe_mac_X550EM_x:
5900                 return ETH_RSS_RETA_SIZE_512;
5901         case ixgbe_mac_X550_vf:
5902         case ixgbe_mac_X550EM_x_vf:
5903                 return ETH_RSS_RETA_SIZE_64;
5904         default:
5905                 return ETH_RSS_RETA_SIZE_128;
5906         }
5907 }
5908
5909 uint32_t
5910 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
5911         switch (mac_type) {
5912         case ixgbe_mac_X550:
5913         case ixgbe_mac_X550EM_x:
5914                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
5915                         return IXGBE_RETA(reta_idx >> 2);
5916                 else
5917                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
5918         case ixgbe_mac_X550_vf:
5919         case ixgbe_mac_X550EM_x_vf:
5920                 return IXGBE_VFRETA(reta_idx >> 2);
5921         default:
5922                 return IXGBE_RETA(reta_idx >> 2);
5923         }
5924 }
5925
5926 uint32_t
5927 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
5928         switch (mac_type) {
5929         case ixgbe_mac_X550_vf:
5930         case ixgbe_mac_X550EM_x_vf:
5931                 return IXGBE_VFMRQC;
5932         default:
5933                 return IXGBE_MRQC;
5934         }
5935 }
5936
5937 uint32_t
5938 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
5939         switch (mac_type) {
5940         case ixgbe_mac_X550_vf:
5941         case ixgbe_mac_X550EM_x_vf:
5942                 return IXGBE_VFRSSRK(i);
5943         default:
5944                 return IXGBE_RSSRK(i);
5945         }
5946 }
5947
5948 bool
5949 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
5950         switch (mac_type) {
5951         case ixgbe_mac_82599_vf:
5952         case ixgbe_mac_X540_vf:
5953                 return 0;
5954         default:
5955                 return 1;
5956         }
5957 }
5958
5959 static int
5960 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
5961                         struct rte_eth_dcb_info *dcb_info)
5962 {
5963         struct ixgbe_dcb_config *dcb_config =
5964                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
5965         struct ixgbe_dcb_tc_config *tc;
5966         uint8_t i, j;
5967
5968         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
5969                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
5970         else
5971                 dcb_info->nb_tcs = 1;
5972
5973         if (dcb_config->vt_mode) { /* vt is enabled*/
5974                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
5975                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
5976                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
5977                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
5978                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
5979                         for (j = 0; j < dcb_info->nb_tcs; j++) {
5980                                 dcb_info->tc_queue.tc_rxq[i][j].base =
5981                                                 i * dcb_info->nb_tcs + j;
5982                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
5983                                 dcb_info->tc_queue.tc_txq[i][j].base =
5984                                                 i * dcb_info->nb_tcs + j;
5985                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
5986                         }
5987                 }
5988         } else { /* vt is disabled*/
5989                 struct rte_eth_dcb_rx_conf *rx_conf =
5990                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
5991                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
5992                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
5993                 if (dcb_info->nb_tcs == ETH_4_TCS) {
5994                         for (i = 0; i < dcb_info->nb_tcs; i++) {
5995                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
5996                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
5997                         }
5998                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
5999                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6000                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6001                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6002                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6003                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6004                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6005                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6006                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6007                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6008                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6009                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6010                         }
6011                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6012                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6013                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6014                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6015                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6016                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6017                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6018                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6019                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6020                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6021                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6022                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6023                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6024                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6025                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6026                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6027                 }
6028         }
6029         for (i = 0; i < dcb_info->nb_tcs; i++) {
6030                 tc = &dcb_config->tc_config[i];
6031                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6032         }
6033         return 0;
6034 }
6035
6036 static struct rte_driver rte_ixgbe_driver = {
6037         .type = PMD_PDEV,
6038         .init = rte_ixgbe_pmd_init,
6039 };
6040
6041 static struct rte_driver rte_ixgbevf_driver = {
6042         .type = PMD_PDEV,
6043         .init = rte_ixgbevf_pmd_init,
6044 };
6045
6046 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
6047 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);