drivers/net/ixgbe/ixgbe_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation.
   3  * Copyright 2014 6WIND S.A.
   4  */
   5
   6 #include <sys/queue.h>
   7
   8 #include <stdio.h>
   9 #include <stdlib.h>
  10 #include <string.h>
  11 #include <errno.h>
  12 #include <stdint.h>
  13 #include <stdarg.h>
  14 #include <unistd.h>
  15 #include <inttypes.h>
  16
  17 #include <rte_byteorder.h>
  18 #include <rte_common.h>
  19 #include <rte_cycles.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_interrupts.h>
  23 #include <rte_pci.h>
  24 #include <rte_memory.h>
  25 #include <rte_memzone.h>
  26 #include <rte_launch.h>
  27 #include <rte_eal.h>
  28 #include <rte_per_lcore.h>
  29 #include <rte_lcore.h>
  30 #include <rte_atomic.h>
  31 #include <rte_branch_prediction.h>
  32 #include <rte_mempool.h>
  33 #include <rte_malloc.h>
  34 #include <rte_mbuf.h>
  35 #include <rte_ether.h>
  36 #include <rte_ethdev_driver.h>
  37 #include <rte_prefetch.h>
  38 #include <rte_udp.h>
  39 #include <rte_tcp.h>
  40 #include <rte_sctp.h>
  41 #include <rte_string_fns.h>
  42 #include <rte_errno.h>
  43 #include <rte_ip.h>
  44 #include <rte_net.h>
  45
  46 #include "ixgbe_logs.h"
  47 #include "base/ixgbe_api.h"
  48 #include "base/ixgbe_vf.h"
  49 #include "ixgbe_ethdev.h"
  50 #include "base/ixgbe_dcb.h"
  51 #include "base/ixgbe_common.h"
  52 #include "ixgbe_rxtx.h"
  53
  54 #ifdef RTE_LIBRTE_IEEE1588
  55 #define IXGBE_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST
  56 #else
  57 #define IXGBE_TX_IEEE1588_TMST 0
  58 #endif
  59 /* Bit Mask to indicate what bits required for building TX context */
  60 #define IXGBE_TX_OFFLOAD_MASK (                  \
  61                 PKT_TX_VLAN_PKT |                \
  62                 PKT_TX_IP_CKSUM |                \
  63                 PKT_TX_L4_MASK |                 \
  64                 PKT_TX_TCP_SEG |                 \
  65                 PKT_TX_MACSEC |                  \
  66                 PKT_TX_OUTER_IP_CKSUM |          \
  67                 PKT_TX_SEC_OFFLOAD |     \
  68                 IXGBE_TX_IEEE1588_TMST)
  69
  70 #define IXGBE_TX_OFFLOAD_NOTSUP_MASK \
  71                 (PKT_TX_OFFLOAD_MASK ^ IXGBE_TX_OFFLOAD_MASK)
  72
  73 #if 1
  74 #define RTE_PMD_USE_PREFETCH
  75 #endif
  76
  77 #ifdef RTE_PMD_USE_PREFETCH
  78 /*
  79  * Prefetch a cache line into all cache levels.
  80  */
  81 #define rte_ixgbe_prefetch(p)   rte_prefetch0(p)
  82 #else
  83 #define rte_ixgbe_prefetch(p)   do {} while (0)
  84 #endif
  85
  86 #ifdef RTE_IXGBE_INC_VECTOR
  87 uint16_t ixgbe_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
  88                                     uint16_t nb_pkts);
  89 #endif
  90
  91 /*********************************************************************
  92  *
  93  *  TX functions
  94  *
  95  **********************************************************************/
  96
  97 /*
  98  * Check for descriptors with their DD bit set and free mbufs.
  99  * Return the total number of buffers freed.
 100  */
 101 static __rte_always_inline int
 102 ixgbe_tx_free_bufs(struct ixgbe_tx_queue *txq)
 103 {
 104         struct ixgbe_tx_entry *txep;
 105         uint32_t status;
 106         int i, nb_free = 0;
 107         struct rte_mbuf *m, *free[RTE_IXGBE_TX_MAX_FREE_BUF_SZ];
 108
 109         /* check DD bit on threshold descriptor */
 110         status = txq->tx_ring[txq->tx_next_dd].wb.status;
 111         if (!(status & rte_cpu_to_le_32(IXGBE_ADVTXD_STAT_DD)))
 112                 return 0;
 113
 114         /*
 115          * first buffer to free from S/W ring is at index
 116          * tx_next_dd - (tx_rs_thresh-1)
 117          */
 118         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
 119
 120         for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
 121                 /* free buffers one at a time */
 122                 m = rte_pktmbuf_prefree_seg(txep->mbuf);
 123                 txep->mbuf = NULL;
 124
 125                 if (unlikely(m == NULL))
 126                         continue;
 127
 128                 if (nb_free >= RTE_IXGBE_TX_MAX_FREE_BUF_SZ ||
 129                     (nb_free > 0 && m->pool != free[0]->pool)) {
 130                         rte_mempool_put_bulk(free[0]->pool,
 131                                              (void **)free, nb_free);
 132                         nb_free = 0;
 133                 }
 134
 135                 free[nb_free++] = m;
 136         }
 137
 138         if (nb_free > 0)
 139                 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
 140
 141         /* buffers were freed, update counters */
 142         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
 143         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
 144         if (txq->tx_next_dd >= txq->nb_tx_desc)
 145                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
 146
 147         return txq->tx_rs_thresh;
 148 }
 149
 150 /* Populate 4 descriptors with data from 4 mbufs */
 151 static inline void
 152 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
 153 {
 154         uint64_t buf_dma_addr;
 155         uint32_t pkt_len;
 156         int i;
 157
 158         for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
 159                 buf_dma_addr = rte_mbuf_data_iova(*pkts);
 160                 pkt_len = (*pkts)->data_len;
 161
 162                 /* write data to descriptor */
 163                 txdp->read.buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
 164
 165                 txdp->read.cmd_type_len =
 166                         rte_cpu_to_le_32((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
 167
 168                 txdp->read.olinfo_status =
 169                         rte_cpu_to_le_32(pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
 170
 171                 rte_prefetch0(&(*pkts)->pool);
 172         }
 173 }
 174
 175 /* Populate 1 descriptor with data from 1 mbuf */
 176 static inline void
 177 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
 178 {
 179         uint64_t buf_dma_addr;
 180         uint32_t pkt_len;
 181
 182         buf_dma_addr = rte_mbuf_data_iova(*pkts);
 183         pkt_len = (*pkts)->data_len;
 184
 185         /* write data to descriptor */
 186         txdp->read.buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
 187         txdp->read.cmd_type_len =
 188                         rte_cpu_to_le_32((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
 189         txdp->read.olinfo_status =
 190                         rte_cpu_to_le_32(pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
 191         rte_prefetch0(&(*pkts)->pool);
 192 }
 193
 194 /*
 195  * Fill H/W descriptor ring with mbuf data.
 196  * Copy mbuf pointers to the S/W ring.
 197  */
 198 static inline void
 199 ixgbe_tx_fill_hw_ring(struct ixgbe_tx_queue *txq, struct rte_mbuf **pkts,
 200                       uint16_t nb_pkts)
 201 {
 202         volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
 203         struct ixgbe_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
 204         const int N_PER_LOOP = 4;
 205         const int N_PER_LOOP_MASK = N_PER_LOOP-1;
 206         int mainpart, leftover;
 207         int i, j;
 208
 209         /*
 210          * Process most of the packets in chunks of N pkts.  Any
 211          * leftover packets will get processed one at a time.
 212          */
 213         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
 214         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
 215         for (i = 0; i < mainpart; i += N_PER_LOOP) {
 216                 /* Copy N mbuf pointers to the S/W ring */
 217                 for (j = 0; j < N_PER_LOOP; ++j) {
 218                         (txep + i + j)->mbuf = *(pkts + i + j);
 219                 }
 220                 tx4(txdp + i, pkts + i);
 221         }
 222
 223         if (unlikely(leftover > 0)) {
 224                 for (i = 0; i < leftover; ++i) {
 225                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
 226                         tx1(txdp + mainpart + i, pkts + mainpart + i);
 227                 }
 228         }
 229 }
 230
 231 static inline uint16_t
 232 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 233              uint16_t nb_pkts)
 234 {
 235         struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
 236         volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
 237         uint16_t n = 0;
 238
 239         /*
 240          * Begin scanning the H/W ring for done descriptors when the
 241          * number of available descriptors drops below tx_free_thresh.  For
 242          * each done descriptor, free the associated buffer.
 243          */
 244         if (txq->nb_tx_free < txq->tx_free_thresh)
 245                 ixgbe_tx_free_bufs(txq);
 246
 247         /* Only use descriptors that are available */
 248         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
 249         if (unlikely(nb_pkts == 0))
 250                 return 0;
 251
 252         /* Use exactly nb_pkts descriptors */
 253         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
 254
 255         /*
 256          * At this point, we know there are enough descriptors in the
 257          * ring to transmit all the packets.  This assumes that each
 258          * mbuf contains a single segment, and that no new offloads
 259          * are expected, which would require a new context descriptor.
 260          */
 261
 262         /*
 263          * See if we're going to wrap-around. If so, handle the top
 264          * of the descriptor ring first, then do the bottom.  If not,
 265          * the processing looks just like the "bottom" part anyway...
 266          */
 267         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
 268                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
 269                 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
 270
 271                 /*
 272                  * We know that the last descriptor in the ring will need to
 273                  * have its RS bit set because tx_rs_thresh has to be
 274                  * a divisor of the ring size
 275                  */
 276                 tx_r[txq->tx_next_rs].read.cmd_type_len |=
 277                         rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
 278                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 279
 280                 txq->tx_tail = 0;
 281         }
 282
 283         /* Fill H/W descriptor ring with mbuf data */
 284         ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
 285         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
 286
 287         /*
 288          * Determine if RS bit should be set
 289          * This is what we actually want:
 290          *   if ((txq->tx_tail - 1) >= txq->tx_next_rs)
 291          * but instead of subtracting 1 and doing >=, we can just do
 292          * greater than without subtracting.
 293          */
 294         if (txq->tx_tail > txq->tx_next_rs) {
 295                 tx_r[txq->tx_next_rs].read.cmd_type_len |=
 296                         rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
 297                 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
 298                                                 txq->tx_rs_thresh);
 299                 if (txq->tx_next_rs >= txq->nb_tx_desc)
 300                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 301         }
 302
 303         /*
 304          * Check for wrap-around. This would only happen if we used
 305          * up to the last descriptor in the ring, no more, no less.
 306          */
 307         if (txq->tx_tail >= txq->nb_tx_desc)
 308                 txq->tx_tail = 0;
 309
 310         /* update tail pointer */
 311         rte_wmb();
 312         IXGBE_PCI_REG_WRITE_RELAXED(txq->tdt_reg_addr, txq->tx_tail);
 313
 314         return nb_pkts;
 315 }
 316
 317 uint16_t
 318 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
 319                        uint16_t nb_pkts)
 320 {
 321         uint16_t nb_tx;
 322
 323         /* Try to transmit at least chunks of TX_MAX_BURST pkts */
 324         if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
 325                 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
 326
 327         /* transmit more than the max burst, in chunks of TX_MAX_BURST */
 328         nb_tx = 0;
 329         while (nb_pkts) {
 330                 uint16_t ret, n;
 331
 332                 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
 333                 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
 334                 nb_tx = (uint16_t)(nb_tx + ret);
 335                 nb_pkts = (uint16_t)(nb_pkts - ret);
 336                 if (ret < n)
 337                         break;
 338         }
 339
 340         return nb_tx;
 341 }
 342
 343 #ifdef RTE_IXGBE_INC_VECTOR
 344 static uint16_t
 345 ixgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 346                     uint16_t nb_pkts)
 347 {
 348         uint16_t nb_tx = 0;
 349         struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
 350
 351         while (nb_pkts) {
 352                 uint16_t ret, num;
 353
 354                 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
 355                 ret = ixgbe_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
 356                                                  num);
 357                 nb_tx += ret;
 358                 nb_pkts -= ret;
 359                 if (ret < num)
 360                         break;
 361         }
 362
 363         return nb_tx;
 364 }
 365 #endif
 366
 367 static inline void
 368 ixgbe_set_xmit_ctx(struct ixgbe_tx_queue *txq,
 369                 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
 370                 uint64_t ol_flags, union ixgbe_tx_offload tx_offload,
 371                 __rte_unused uint64_t *mdata)
 372 {
 373         uint32_t type_tucmd_mlhl;
 374         uint32_t mss_l4len_idx = 0;
 375         uint32_t ctx_idx;
 376         uint32_t vlan_macip_lens;
 377         union ixgbe_tx_offload tx_offload_mask;
 378         uint32_t seqnum_seed = 0;
 379
 380         ctx_idx = txq->ctx_curr;
 381         tx_offload_mask.data[0] = 0;
 382         tx_offload_mask.data[1] = 0;
 383         type_tucmd_mlhl = 0;
 384
 385         /* Specify which HW CTX to upload. */
 386         mss_l4len_idx |= (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
 387
 388         if (ol_flags & PKT_TX_VLAN_PKT) {
 389                 tx_offload_mask.vlan_tci |= ~0;
 390         }
 391
 392         /* check if TCP segmentation required for this packet */
 393         if (ol_flags & PKT_TX_TCP_SEG) {
 394                 /* implies IP cksum in IPv4 */
 395                 if (ol_flags & PKT_TX_IP_CKSUM)
 396                         type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4 |
 397                                 IXGBE_ADVTXD_TUCMD_L4T_TCP |
 398                                 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
 399                 else
 400                         type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV6 |
 401                                 IXGBE_ADVTXD_TUCMD_L4T_TCP |
 402                                 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
 403
 404                 tx_offload_mask.l2_len |= ~0;
 405                 tx_offload_mask.l3_len |= ~0;
 406                 tx_offload_mask.l4_len |= ~0;
 407                 tx_offload_mask.tso_segsz |= ~0;
 408                 mss_l4len_idx |= tx_offload.tso_segsz << IXGBE_ADVTXD_MSS_SHIFT;
 409                 mss_l4len_idx |= tx_offload.l4_len << IXGBE_ADVTXD_L4LEN_SHIFT;
 410         } else { /* no TSO, check if hardware checksum is needed */
 411                 if (ol_flags & PKT_TX_IP_CKSUM) {
 412                         type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
 413                         tx_offload_mask.l2_len |= ~0;
 414                         tx_offload_mask.l3_len |= ~0;
 415                 }
 416
 417                 switch (ol_flags & PKT_TX_L4_MASK) {
 418                 case PKT_TX_UDP_CKSUM:
 419                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
 420                                 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
 421                         mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
 422                         tx_offload_mask.l2_len |= ~0;
 423                         tx_offload_mask.l3_len |= ~0;
 424                         break;
 425                 case PKT_TX_TCP_CKSUM:
 426                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
 427                                 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
 428                         mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
 429                         tx_offload_mask.l2_len |= ~0;
 430                         tx_offload_mask.l3_len |= ~0;
 431                         break;
 432                 case PKT_TX_SCTP_CKSUM:
 433                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
 434                                 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
 435                         mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
 436                         tx_offload_mask.l2_len |= ~0;
 437                         tx_offload_mask.l3_len |= ~0;
 438                         break;
 439                 default:
 440                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
 441                                 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
 442                         break;
 443                 }
 444         }
 445
 446         if (ol_flags & PKT_TX_OUTER_IP_CKSUM) {
 447                 tx_offload_mask.outer_l2_len |= ~0;
 448                 tx_offload_mask.outer_l3_len |= ~0;
 449                 tx_offload_mask.l2_len |= ~0;
 450                 seqnum_seed |= tx_offload.outer_l3_len
 451                                << IXGBE_ADVTXD_OUTER_IPLEN;
 452                 seqnum_seed |= tx_offload.l2_len
 453                                << IXGBE_ADVTXD_TUNNEL_LEN;
 454         }
 455 #ifdef RTE_LIBRTE_SECURITY
 456         if (ol_flags & PKT_TX_SEC_OFFLOAD) {
 457                 union ixgbe_crypto_tx_desc_md *md =
 458                                 (union ixgbe_crypto_tx_desc_md *)mdata;
 459                 seqnum_seed |=
 460                         (IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK & md->sa_idx);
 461                 type_tucmd_mlhl |= md->enc ?
 462                                 (IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP |
 463                                 IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN) : 0;
 464                 type_tucmd_mlhl |=
 465                         (md->pad_len & IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK);
 466                 tx_offload_mask.sa_idx |= ~0;
 467                 tx_offload_mask.sec_pad_len |= ~0;
 468         }
 469 #endif
 470
 471         txq->ctx_cache[ctx_idx].flags = ol_flags;
 472         txq->ctx_cache[ctx_idx].tx_offload.data[0]  =
 473                 tx_offload_mask.data[0] & tx_offload.data[0];
 474         txq->ctx_cache[ctx_idx].tx_offload.data[1]  =
 475                 tx_offload_mask.data[1] & tx_offload.data[1];
 476         txq->ctx_cache[ctx_idx].tx_offload_mask    = tx_offload_mask;
 477
 478         ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
 479         vlan_macip_lens = tx_offload.l3_len;
 480         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 481                 vlan_macip_lens |= (tx_offload.outer_l2_len <<
 482                                     IXGBE_ADVTXD_MACLEN_SHIFT);
 483         else
 484                 vlan_macip_lens |= (tx_offload.l2_len <<
 485                                     IXGBE_ADVTXD_MACLEN_SHIFT);
 486         vlan_macip_lens |= ((uint32_t)tx_offload.vlan_tci << IXGBE_ADVTXD_VLAN_SHIFT);
 487         ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
 488         ctx_txd->mss_l4len_idx   = rte_cpu_to_le_32(mss_l4len_idx);
 489         ctx_txd->seqnum_seed     = seqnum_seed;
 490 }
 491
 492 /*
 493  * Check which hardware context can be used. Use the existing match
 494  * or create a new context descriptor.
 495  */
 496 static inline uint32_t
 497 what_advctx_update(struct ixgbe_tx_queue *txq, uint64_t flags,
 498                    union ixgbe_tx_offload tx_offload)
 499 {
 500         /* If match with the current used context */
 501         if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
 502                    (txq->ctx_cache[txq->ctx_curr].tx_offload.data[0] ==
 503                     (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[0]
 504                      & tx_offload.data[0])) &&
 505                    (txq->ctx_cache[txq->ctx_curr].tx_offload.data[1] ==
 506                     (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[1]
 507                      & tx_offload.data[1]))))
 508                 return txq->ctx_curr;
 509
 510         /* What if match with the next context  */
 511         txq->ctx_curr ^= 1;
 512         if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
 513                    (txq->ctx_cache[txq->ctx_curr].tx_offload.data[0] ==
 514                     (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[0]
 515                      & tx_offload.data[0])) &&
 516                    (txq->ctx_cache[txq->ctx_curr].tx_offload.data[1] ==
 517                     (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[1]
 518                      & tx_offload.data[1]))))
 519                 return txq->ctx_curr;
 520
 521         /* Mismatch, use the previous context */
 522         return IXGBE_CTX_NUM;
 523 }
 524
 525 static inline uint32_t
 526 tx_desc_cksum_flags_to_olinfo(uint64_t ol_flags)
 527 {
 528         uint32_t tmp = 0;
 529
 530         if ((ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM)
 531                 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
 532         if (ol_flags & PKT_TX_IP_CKSUM)
 533                 tmp |= IXGBE_ADVTXD_POPTS_IXSM;
 534         if (ol_flags & PKT_TX_TCP_SEG)
 535                 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
 536         return tmp;
 537 }
 538
 539 static inline uint32_t
 540 tx_desc_ol_flags_to_cmdtype(uint64_t ol_flags)
 541 {
 542         uint32_t cmdtype = 0;
 543
 544         if (ol_flags & PKT_TX_VLAN_PKT)
 545                 cmdtype |= IXGBE_ADVTXD_DCMD_VLE;
 546         if (ol_flags & PKT_TX_TCP_SEG)
 547                 cmdtype |= IXGBE_ADVTXD_DCMD_TSE;
 548         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 549                 cmdtype |= (1 << IXGBE_ADVTXD_OUTERIPCS_SHIFT);
 550         if (ol_flags & PKT_TX_MACSEC)
 551                 cmdtype |= IXGBE_ADVTXD_MAC_LINKSEC;
 552         return cmdtype;
 553 }
 554
 555 /* Default RS bit threshold values */
 556 #ifndef DEFAULT_TX_RS_THRESH
 557 #define DEFAULT_TX_RS_THRESH   32
 558 #endif
 559 #ifndef DEFAULT_TX_FREE_THRESH
 560 #define DEFAULT_TX_FREE_THRESH 32
 561 #endif
 562
 563 /* Reset transmit descriptors after they have been used */
 564 static inline int
 565 ixgbe_xmit_cleanup(struct ixgbe_tx_queue *txq)
 566 {
 567         struct ixgbe_tx_entry *sw_ring = txq->sw_ring;
 568         volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
 569         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 570         uint16_t nb_tx_desc = txq->nb_tx_desc;
 571         uint16_t desc_to_clean_to;
 572         uint16_t nb_tx_to_clean;
 573         uint32_t status;
 574
 575         /* Determine the last descriptor needing to be cleaned */
 576         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 577         if (desc_to_clean_to >= nb_tx_desc)
 578                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 579
 580         /* Check to make sure the last descriptor to clean is done */
 581         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 582         status = txr[desc_to_clean_to].wb.status;
 583         if (!(status & rte_cpu_to_le_32(IXGBE_TXD_STAT_DD))) {
 584                 PMD_TX_FREE_LOG(DEBUG,
 585                                 "TX descriptor %4u is not done"
 586                                 "(port=%d queue=%d)",
 587                                 desc_to_clean_to,
 588                                 txq->port_id, txq->queue_id);
 589                 /* Failed to clean any descriptors, better luck next time */
 590                 return -(1);
 591         }
 592
 593         /* Figure out how many descriptors will be cleaned */
 594         if (last_desc_cleaned > desc_to_clean_to)
 595                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 596                                                         desc_to_clean_to);
 597         else
 598                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 599                                                 last_desc_cleaned);
 600
 601         PMD_TX_FREE_LOG(DEBUG,
 602                         "Cleaning %4u TX descriptors: %4u to %4u "
 603                         "(port=%d queue=%d)",
 604                         nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
 605                         txq->port_id, txq->queue_id);
 606
 607         /*
 608          * The last descriptor to clean is done, so that means all the
 609          * descriptors from the last descriptor that was cleaned
 610          * up to the last descriptor with the RS bit set
 611          * are done. Only reset the threshold descriptor.
 612          */
 613         txr[desc_to_clean_to].wb.status = 0;
 614
 615         /* Update the txq to reflect the last descriptor that was cleaned */
 616         txq->last_desc_cleaned = desc_to_clean_to;
 617         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 618
 619         /* No Error */
 620         return 0;
 621 }
 622
 623 uint16_t
 624 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 625                 uint16_t nb_pkts)
 626 {
 627         struct ixgbe_tx_queue *txq;
 628         struct ixgbe_tx_entry *sw_ring;
 629         struct ixgbe_tx_entry *txe, *txn;
 630         volatile union ixgbe_adv_tx_desc *txr;
 631         volatile union ixgbe_adv_tx_desc *txd, *txp;
 632         struct rte_mbuf     *tx_pkt;
 633         struct rte_mbuf     *m_seg;
 634         uint64_t buf_dma_addr;
 635         uint32_t olinfo_status;
 636         uint32_t cmd_type_len;
 637         uint32_t pkt_len;
 638         uint16_t slen;
 639         uint64_t ol_flags;
 640         uint16_t tx_id;
 641         uint16_t tx_last;
 642         uint16_t nb_tx;
 643         uint16_t nb_used;
 644         uint64_t tx_ol_req;
 645         uint32_t ctx = 0;
 646         uint32_t new_ctx;
 647         union ixgbe_tx_offload tx_offload;
 648 #ifdef RTE_LIBRTE_SECURITY
 649         uint8_t use_ipsec;
 650 #endif
 651
 652         tx_offload.data[0] = 0;
 653         tx_offload.data[1] = 0;
 654         txq = tx_queue;
 655         sw_ring = txq->sw_ring;
 656         txr     = txq->tx_ring;
 657         tx_id   = txq->tx_tail;
 658         txe = &sw_ring[tx_id];
 659         txp = NULL;
 660
 661         /* Determine if the descriptor ring needs to be cleaned. */
 662         if (txq->nb_tx_free < txq->tx_free_thresh)
 663                 ixgbe_xmit_cleanup(txq);
 664
 665         rte_prefetch0(&txe->mbuf->pool);
 666
 667         /* TX loop */
 668         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
 669                 new_ctx = 0;
 670                 tx_pkt = *tx_pkts++;
 671                 pkt_len = tx_pkt->pkt_len;
 672
 673                 /*
 674                  * Determine how many (if any) context descriptors
 675                  * are needed for offload functionality.
 676                  */
 677                 ol_flags = tx_pkt->ol_flags;
 678 #ifdef RTE_LIBRTE_SECURITY
 679                 use_ipsec = txq->using_ipsec && (ol_flags & PKT_TX_SEC_OFFLOAD);
 680 #endif
 681
 682                 /* If hardware offload required */
 683                 tx_ol_req = ol_flags & IXGBE_TX_OFFLOAD_MASK;
 684                 if (tx_ol_req) {
 685                         tx_offload.l2_len = tx_pkt->l2_len;
 686                         tx_offload.l3_len = tx_pkt->l3_len;
 687                         tx_offload.l4_len = tx_pkt->l4_len;
 688                         tx_offload.vlan_tci = tx_pkt->vlan_tci;
 689                         tx_offload.tso_segsz = tx_pkt->tso_segsz;
 690                         tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
 691                         tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
 692 #ifdef RTE_LIBRTE_SECURITY
 693                         if (use_ipsec) {
 694                                 union ixgbe_crypto_tx_desc_md *ipsec_mdata =
 695                                         (union ixgbe_crypto_tx_desc_md *)
 696                                                         &tx_pkt->udata64;
 697                                 tx_offload.sa_idx = ipsec_mdata->sa_idx;
 698                                 tx_offload.sec_pad_len = ipsec_mdata->pad_len;
 699                         }
 700 #endif
 701
 702                         /* If new context need be built or reuse the exist ctx. */
 703                         ctx = what_advctx_update(txq, tx_ol_req,
 704                                 tx_offload);
 705                         /* Only allocate context descriptor if required*/
 706                         new_ctx = (ctx == IXGBE_CTX_NUM);
 707                         ctx = txq->ctx_curr;
 708                 }
 709
 710                 /*
 711                  * Keep track of how many descriptors are used this loop
 712                  * This will always be the number of segments + the number of
 713                  * Context descriptors required to transmit the packet
 714                  */
 715                 nb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);
 716
 717                 if (txp != NULL &&
 718                                 nb_used + txq->nb_tx_used >= txq->tx_rs_thresh)
 719                         /* set RS on the previous packet in the burst */
 720                         txp->read.cmd_type_len |=
 721                                 rte_cpu_to_le_32(IXGBE_TXD_CMD_RS);
 722
 723                 /*
 724                  * The number of descriptors that must be allocated for a
 725                  * packet is the number of segments of that packet, plus 1
 726                  * Context Descriptor for the hardware offload, if any.
 727                  * Determine the last TX descriptor to allocate in the TX ring
 728                  * for the packet, starting from the current position (tx_id)
 729                  * in the ring.
 730                  */
 731                 tx_last = (uint16_t) (tx_id + nb_used - 1);
 732
 733                 /* Circular ring */
 734                 if (tx_last >= txq->nb_tx_desc)
 735                         tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
 736
 737                 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
 738                            " tx_first=%u tx_last=%u",
 739                            (unsigned) txq->port_id,
 740                            (unsigned) txq->queue_id,
 741                            (unsigned) pkt_len,
 742                            (unsigned) tx_id,
 743                            (unsigned) tx_last);
 744
 745                 /*
 746                  * Make sure there are enough TX descriptors available to
 747                  * transmit the entire packet.
 748                  * nb_used better be less than or equal to txq->tx_rs_thresh
 749                  */
 750                 if (nb_used > txq->nb_tx_free) {
 751                         PMD_TX_FREE_LOG(DEBUG,
 752                                         "Not enough free TX descriptors "
 753                                         "nb_used=%4u nb_free=%4u "
 754                                         "(port=%d queue=%d)",
 755                                         nb_used, txq->nb_tx_free,
 756                                         txq->port_id, txq->queue_id);
 757
 758                         if (ixgbe_xmit_cleanup(txq) != 0) {
 759                                 /* Could not clean any descriptors */
 760                                 if (nb_tx == 0)
 761                                         return 0;
 762                                 goto end_of_tx;
 763                         }
 764
 765                         /* nb_used better be <= txq->tx_rs_thresh */
 766                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
 767                                 PMD_TX_FREE_LOG(DEBUG,
 768                                         "The number of descriptors needed to "
 769                                         "transmit the packet exceeds the "
 770                                         "RS bit threshold. This will impact "
 771                                         "performance."
 772                                         "nb_used=%4u nb_free=%4u "
 773                                         "tx_rs_thresh=%4u. "
 774                                         "(port=%d queue=%d)",
 775                                         nb_used, txq->nb_tx_free,
 776                                         txq->tx_rs_thresh,
 777                                         txq->port_id, txq->queue_id);
 778                                 /*
 779                                  * Loop here until there are enough TX
 780                                  * descriptors or until the ring cannot be
 781                                  * cleaned.
 782                                  */
 783                                 while (nb_used > txq->nb_tx_free) {
 784                                         if (ixgbe_xmit_cleanup(txq) != 0) {
 785                                                 /*
 786                                                  * Could not clean any
 787                                                  * descriptors
 788                                                  */
 789                                                 if (nb_tx == 0)
 790                                                         return 0;
 791                                                 goto end_of_tx;
 792                                         }
 793                                 }
 794                         }
 795                 }
 796
 797                 /*
 798                  * By now there are enough free TX descriptors to transmit
 799                  * the packet.
 800                  */
 801
 802                 /*
 803                  * Set common flags of all TX Data Descriptors.
 804                  *
 805                  * The following bits must be set in all Data Descriptors:
 806                  *   - IXGBE_ADVTXD_DTYP_DATA
 807                  *   - IXGBE_ADVTXD_DCMD_DEXT
 808                  *
 809                  * The following bits must be set in the first Data Descriptor
 810                  * and are ignored in the other ones:
 811                  *   - IXGBE_ADVTXD_DCMD_IFCS
 812                  *   - IXGBE_ADVTXD_MAC_1588
 813                  *   - IXGBE_ADVTXD_DCMD_VLE
 814                  *
 815                  * The following bits must only be set in the last Data
 816                  * Descriptor:
 817                  *   - IXGBE_TXD_CMD_EOP
 818                  *
 819                  * The following bits can be set in any Data Descriptor, but
 820                  * are only set in the last Data Descriptor:
 821                  *   - IXGBE_TXD_CMD_RS
 822                  */
 823                 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
 824                         IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
 825
 826 #ifdef RTE_LIBRTE_IEEE1588
 827                 if (ol_flags & PKT_TX_IEEE1588_TMST)
 828                         cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
 829 #endif
 830
 831                 olinfo_status = 0;
 832                 if (tx_ol_req) {
 833
 834                         if (ol_flags & PKT_TX_TCP_SEG) {
 835                                 /* when TSO is on, paylen in descriptor is the
 836                                  * not the packet len but the tcp payload len */
 837                                 pkt_len -= (tx_offload.l2_len +
 838                                         tx_offload.l3_len + tx_offload.l4_len);
 839                         }
 840
 841                         /*
 842                          * Setup the TX Advanced Context Descriptor if required
 843                          */
 844                         if (new_ctx) {
 845                                 volatile struct ixgbe_adv_tx_context_desc *
 846                                     ctx_txd;
 847
 848                                 ctx_txd = (volatile struct
 849                                     ixgbe_adv_tx_context_desc *)
 850                                     &txr[tx_id];
 851
 852                                 txn = &sw_ring[txe->next_id];
 853                                 rte_prefetch0(&txn->mbuf->pool);
 854
 855                                 if (txe->mbuf != NULL) {
 856                                         rte_pktmbuf_free_seg(txe->mbuf);
 857                                         txe->mbuf = NULL;
 858                                 }
 859
 860                                 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
 861                                         tx_offload, &tx_pkt->udata64);
 862
 863                                 txe->last_id = tx_last;
 864                                 tx_id = txe->next_id;
 865                                 txe = txn;
 866                         }
 867
 868                         /*
 869                          * Setup the TX Advanced Data Descriptor,
 870                          * This path will go through
 871                          * whatever new/reuse the context descriptor
 872                          */
 873                         cmd_type_len  |= tx_desc_ol_flags_to_cmdtype(ol_flags);
 874                         olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
 875                         olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
 876                 }
 877
 878                 olinfo_status |= (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
 879 #ifdef RTE_LIBRTE_SECURITY
 880                 if (use_ipsec)
 881                         olinfo_status |= IXGBE_ADVTXD_POPTS_IPSEC;
 882 #endif
 883
 884                 m_seg = tx_pkt;
 885                 do {
 886                         txd = &txr[tx_id];
 887                         txn = &sw_ring[txe->next_id];
 888                         rte_prefetch0(&txn->mbuf->pool);
 889
 890                         if (txe->mbuf != NULL)
 891                                 rte_pktmbuf_free_seg(txe->mbuf);
 892                         txe->mbuf = m_seg;
 893
 894                         /*
 895                          * Set up Transmit Data Descriptor.
 896                          */
 897                         slen = m_seg->data_len;
 898                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
 899                         txd->read.buffer_addr =
 900                                 rte_cpu_to_le_64(buf_dma_addr);
 901                         txd->read.cmd_type_len =
 902                                 rte_cpu_to_le_32(cmd_type_len | slen);
 903                         txd->read.olinfo_status =
 904                                 rte_cpu_to_le_32(olinfo_status);
 905                         txe->last_id = tx_last;
 906                         tx_id = txe->next_id;
 907                         txe = txn;
 908                         m_seg = m_seg->next;
 909                 } while (m_seg != NULL);
 910
 911                 /*
 912                  * The last packet data descriptor needs End Of Packet (EOP)
 913                  */
 914                 cmd_type_len |= IXGBE_TXD_CMD_EOP;
 915                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
 916                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
 917
 918                 /* Set RS bit only on threshold packets' last descriptor */
 919                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
 920                         PMD_TX_FREE_LOG(DEBUG,
 921                                         "Setting RS bit on TXD id="
 922                                         "%4u (port=%d queue=%d)",
 923                                         tx_last, txq->port_id, txq->queue_id);
 924
 925                         cmd_type_len |= IXGBE_TXD_CMD_RS;
 926
 927                         /* Update txq RS bit counters */
 928                         txq->nb_tx_used = 0;
 929                         txp = NULL;
 930                 } else
 931                         txp = txd;
 932
 933                 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
 934         }
 935
 936 end_of_tx:
 937         /* set RS on last packet in the burst */
 938         if (txp != NULL)
 939                 txp->read.cmd_type_len |= rte_cpu_to_le_32(IXGBE_TXD_CMD_RS);
 940
 941         rte_wmb();
 942
 943         /*
 944          * Set the Transmit Descriptor Tail (TDT)
 945          */
 946         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
 947                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
 948                    (unsigned) tx_id, (unsigned) nb_tx);
 949         IXGBE_PCI_REG_WRITE_RELAXED(txq->tdt_reg_addr, tx_id);
 950         txq->tx_tail = tx_id;
 951
 952         return nb_tx;
 953 }
 954
 955 /*********************************************************************
 956  *
 957  *  TX prep functions
 958  *
 959  **********************************************************************/
 960 uint16_t
 961 ixgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
 962 {
 963         int i, ret;
 964         uint64_t ol_flags;
 965         struct rte_mbuf *m;
 966         struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
 967
 968         for (i = 0; i < nb_pkts; i++) {
 969                 m = tx_pkts[i];
 970                 ol_flags = m->ol_flags;
 971
 972                 /**
 973                  * Check if packet meets requirements for number of segments
 974                  *
 975                  * NOTE: for ixgbe it's always (40 - WTHRESH) for both TSO and
 976                  *       non-TSO
 977                  */
 978
 979                 if (m->nb_segs > IXGBE_TX_MAX_SEG - txq->wthresh) {
 980                         rte_errno = -EINVAL;
 981                         return i;
 982                 }
 983
 984                 if (ol_flags & IXGBE_TX_OFFLOAD_NOTSUP_MASK) {
 985                         rte_errno = -ENOTSUP;
 986                         return i;
 987                 }
 988
 989 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
 990                 ret = rte_validate_tx_offload(m);
 991                 if (ret != 0) {
 992                         rte_errno = ret;
 993                         return i;
 994                 }
 995 #endif
 996                 ret = rte_net_intel_cksum_prepare(m);
 997                 if (ret != 0) {
 998                         rte_errno = ret;
 999                         return i;
1000                 }
1001         }
1002
1003         return i;
1004 }
1005
1006 /*********************************************************************
1007  *
1008  *  RX functions
1009  *
1010  **********************************************************************/
1011
1012 #define IXGBE_PACKET_TYPE_ETHER                         0X00
1013 #define IXGBE_PACKET_TYPE_IPV4                          0X01
1014 #define IXGBE_PACKET_TYPE_IPV4_TCP                      0X11
1015 #define IXGBE_PACKET_TYPE_IPV4_UDP                      0X21
1016 #define IXGBE_PACKET_TYPE_IPV4_SCTP                     0X41
1017 #define IXGBE_PACKET_TYPE_IPV4_EXT                      0X03
1018 #define IXGBE_PACKET_TYPE_IPV4_EXT_TCP                  0X13
1019 #define IXGBE_PACKET_TYPE_IPV4_EXT_UDP                  0X23
1020 #define IXGBE_PACKET_TYPE_IPV4_EXT_SCTP                 0X43
1021 #define IXGBE_PACKET_TYPE_IPV6                          0X04
1022 #define IXGBE_PACKET_TYPE_IPV6_TCP                      0X14
1023 #define IXGBE_PACKET_TYPE_IPV6_UDP                      0X24
1024 #define IXGBE_PACKET_TYPE_IPV6_SCTP                     0X44
1025 #define IXGBE_PACKET_TYPE_IPV6_EXT                      0X0C
1026 #define IXGBE_PACKET_TYPE_IPV6_EXT_TCP                  0X1C
1027 #define IXGBE_PACKET_TYPE_IPV6_EXT_UDP                  0X2C
1028 #define IXGBE_PACKET_TYPE_IPV6_EXT_SCTP                 0X4C
1029 #define IXGBE_PACKET_TYPE_IPV4_IPV6                     0X05
1030 #define IXGBE_PACKET_TYPE_IPV4_IPV6_TCP                 0X15
1031 #define IXGBE_PACKET_TYPE_IPV4_IPV6_UDP                 0X25
1032 #define IXGBE_PACKET_TYPE_IPV4_IPV6_SCTP                0X45
1033 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6                 0X07
1034 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_TCP             0X17
1035 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_UDP             0X27
1036 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_SCTP            0X47
1037 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT                 0X0D
1038 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_TCP             0X1D
1039 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_UDP             0X2D
1040 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_SCTP            0X4D
1041 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT             0X0F
1042 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_TCP         0X1F
1043 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_UDP         0X2F
1044 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_SCTP        0X4F
1045
1046 #define IXGBE_PACKET_TYPE_NVGRE                   0X00
1047 #define IXGBE_PACKET_TYPE_NVGRE_IPV4              0X01
1048 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_TCP          0X11
1049 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_UDP          0X21
1050 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_SCTP         0X41
1051 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT          0X03
1052 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_TCP      0X13
1053 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_UDP      0X23
1054 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_SCTP     0X43
1055 #define IXGBE_PACKET_TYPE_NVGRE_IPV6              0X04
1056 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_TCP          0X14
1057 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_UDP          0X24
1058 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_SCTP         0X44
1059 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT          0X0C
1060 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_TCP      0X1C
1061 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_UDP      0X2C
1062 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_SCTP     0X4C
1063 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6         0X05
1064 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_TCP     0X15
1065 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_UDP     0X25
1066 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT     0X0D
1067 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_TCP 0X1D
1068 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_UDP 0X2D
1069
1070 #define IXGBE_PACKET_TYPE_VXLAN                   0X80
1071 #define IXGBE_PACKET_TYPE_VXLAN_IPV4              0X81
1072 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_TCP          0x91
1073 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_UDP          0xA1
1074 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_SCTP         0xC1
1075 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT          0x83
1076 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_TCP      0X93
1077 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_UDP      0XA3
1078 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_SCTP     0XC3
1079 #define IXGBE_PACKET_TYPE_VXLAN_IPV6              0X84
1080 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_TCP          0X94
1081 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_UDP          0XA4
1082 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_SCTP         0XC4
1083 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT          0X8C
1084 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_TCP      0X9C
1085 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_UDP      0XAC
1086 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_SCTP     0XCC
1087 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6         0X85
1088 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_TCP     0X95
1089 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_UDP     0XA5
1090 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT     0X8D
1091 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_TCP 0X9D
1092 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_UDP 0XAD
1093
1094 /**
1095  * Use 2 different table for normal packet and tunnel packet
1096  * to save the space.
1097  */
1098 const uint32_t
1099         ptype_table[IXGBE_PACKET_TYPE_MAX] __rte_cache_aligned = {
1100         [IXGBE_PACKET_TYPE_ETHER] = RTE_PTYPE_L2_ETHER,
1101         [IXGBE_PACKET_TYPE_IPV4] = RTE_PTYPE_L2_ETHER |
1102                 RTE_PTYPE_L3_IPV4,
1103         [IXGBE_PACKET_TYPE_IPV4_TCP] = RTE_PTYPE_L2_ETHER |
1104                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP,
1105         [IXGBE_PACKET_TYPE_IPV4_UDP] = RTE_PTYPE_L2_ETHER |
1106                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
1107         [IXGBE_PACKET_TYPE_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |
1108                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_SCTP,
1109         [IXGBE_PACKET_TYPE_IPV4_EXT] = RTE_PTYPE_L2_ETHER |
1110                 RTE_PTYPE_L3_IPV4_EXT,
1111         [IXGBE_PACKET_TYPE_IPV4_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1112                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_TCP,
1113         [IXGBE_PACKET_TYPE_IPV4_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1114                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_UDP,
1115         [IXGBE_PACKET_TYPE_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1116                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_SCTP,
1117         [IXGBE_PACKET_TYPE_IPV6] = RTE_PTYPE_L2_ETHER |
1118                 RTE_PTYPE_L3_IPV6,
1119         [IXGBE_PACKET_TYPE_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1120                 RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP,
1121         [IXGBE_PACKET_TYPE_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1122                 RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
1123         [IXGBE_PACKET_TYPE_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
1124                 RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_SCTP,
1125         [IXGBE_PACKET_TYPE_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1126                 RTE_PTYPE_L3_IPV6_EXT,
1127         [IXGBE_PACKET_TYPE_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1128                 RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_TCP,
1129         [IXGBE_PACKET_TYPE_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1130                 RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_UDP,
1131         [IXGBE_PACKET_TYPE_IPV6_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1132                 RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_SCTP,
1133         [IXGBE_PACKET_TYPE_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |
1134                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1135                 RTE_PTYPE_INNER_L3_IPV6,
1136         [IXGBE_PACKET_TYPE_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1137                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1138                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_TCP,
1139         [IXGBE_PACKET_TYPE_IPV4_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1140                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1141         RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_UDP,
1142         [IXGBE_PACKET_TYPE_IPV4_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
1143                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1144                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_SCTP,
1145         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6] = RTE_PTYPE_L2_ETHER |
1146                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1147                 RTE_PTYPE_INNER_L3_IPV6,
1148         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1149                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1150                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_TCP,
1151         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1152                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1153                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_UDP,
1154         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
1155                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1156                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_SCTP,
1157         [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1158                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1159                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1160         [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1161                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1162                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_TCP,
1163         [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1164                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1165                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_UDP,
1166         [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1167                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1168                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_SCTP,
1169         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1170                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1171                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1172         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1173                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1174                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_TCP,
1175         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1176                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1177                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_UDP,
1178         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_SCTP] =
1179                 RTE_PTYPE_L2_ETHER |
1180                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1181                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_SCTP,
1182 };
1183
1184 const uint32_t
1185         ptype_table_tn[IXGBE_PACKET_TYPE_TN_MAX] __rte_cache_aligned = {
1186         [IXGBE_PACKET_TYPE_NVGRE] = RTE_PTYPE_L2_ETHER |
1187                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1188                 RTE_PTYPE_INNER_L2_ETHER,
1189         [IXGBE_PACKET_TYPE_NVGRE_IPV4] = RTE_PTYPE_L2_ETHER |
1190                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1191                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1192         [IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT] = RTE_PTYPE_L2_ETHER |
1193                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1194                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4_EXT,
1195         [IXGBE_PACKET_TYPE_NVGRE_IPV6] = RTE_PTYPE_L2_ETHER |
1196                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1197                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6,
1198         [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |
1199                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1200                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1201         [IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1202                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1203                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6_EXT,
1204         [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1205                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1206                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1207         [IXGBE_PACKET_TYPE_NVGRE_IPV4_TCP] = RTE_PTYPE_L2_ETHER |
1208                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1209                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4 |
1210                 RTE_PTYPE_INNER_L4_TCP,
1211         [IXGBE_PACKET_TYPE_NVGRE_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1212                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1213                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6 |
1214                 RTE_PTYPE_INNER_L4_TCP,
1215         [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1216                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1217                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1218         [IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1219                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1220                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6_EXT |
1221                 RTE_PTYPE_INNER_L4_TCP,
1222         [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_TCP] =
1223                 RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1224                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_INNER_L2_ETHER |
1225                 RTE_PTYPE_INNER_L3_IPV4,
1226         [IXGBE_PACKET_TYPE_NVGRE_IPV4_UDP] = RTE_PTYPE_L2_ETHER |
1227                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1228                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4 |
1229                 RTE_PTYPE_INNER_L4_UDP,
1230         [IXGBE_PACKET_TYPE_NVGRE_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1231                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1232                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6 |
1233                 RTE_PTYPE_INNER_L4_UDP,
1234         [IXGBE_PACKET_TYPE_NVGRE_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
1235                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1236                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6 |
1237                 RTE_PTYPE_INNER_L4_SCTP,
1238         [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1239                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1240                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1241         [IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1242                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1243                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6_EXT |
1244                 RTE_PTYPE_INNER_L4_UDP,
1245         [IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1246                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1247                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6_EXT |
1248                 RTE_PTYPE_INNER_L4_SCTP,
1249         [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_UDP] =
1250                 RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1251                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_INNER_L2_ETHER |
1252                 RTE_PTYPE_INNER_L3_IPV4,
1253         [IXGBE_PACKET_TYPE_NVGRE_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |
1254                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1255                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4 |
1256                 RTE_PTYPE_INNER_L4_SCTP,
1257         [IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1258                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1259                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4_EXT |
1260                 RTE_PTYPE_INNER_L4_SCTP,
1261         [IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1262                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1263                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4_EXT |
1264                 RTE_PTYPE_INNER_L4_TCP,
1265         [IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1266                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1267                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4_EXT |
1268                 RTE_PTYPE_INNER_L4_UDP,
1269
1270         [IXGBE_PACKET_TYPE_VXLAN] = RTE_PTYPE_L2_ETHER |
1271                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1272                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER,
1273         [IXGBE_PACKET_TYPE_VXLAN_IPV4] = RTE_PTYPE_L2_ETHER |
1274                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1275                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1276                 RTE_PTYPE_INNER_L3_IPV4,
1277         [IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT] = RTE_PTYPE_L2_ETHER |
1278                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1279                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1280                 RTE_PTYPE_INNER_L3_IPV4_EXT,
1281         [IXGBE_PACKET_TYPE_VXLAN_IPV6] = RTE_PTYPE_L2_ETHER |
1282                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1283                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1284                 RTE_PTYPE_INNER_L3_IPV6,
1285         [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |
1286                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1287                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1288                 RTE_PTYPE_INNER_L3_IPV4,
1289         [IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1290                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1291                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1292                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1293         [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1294                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1295                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1296                 RTE_PTYPE_INNER_L3_IPV4,
1297         [IXGBE_PACKET_TYPE_VXLAN_IPV4_TCP] = RTE_PTYPE_L2_ETHER |
1298                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1299                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1300                 RTE_PTYPE_INNER_L3_IPV4 | RTE_PTYPE_INNER_L4_TCP,
1301         [IXGBE_PACKET_TYPE_VXLAN_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1302                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1303                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1304                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_TCP,
1305         [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1306                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1307                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1308                 RTE_PTYPE_INNER_L3_IPV4,
1309         [IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1310                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1311                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1312                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_TCP,
1313         [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_TCP] =
1314                 RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1315                 RTE_PTYPE_L4_UDP | RTE_PTYPE_TUNNEL_VXLAN |
1316                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1317         [IXGBE_PACKET_TYPE_VXLAN_IPV4_UDP] = RTE_PTYPE_L2_ETHER |
1318                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1319                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1320                 RTE_PTYPE_INNER_L3_IPV4 | RTE_PTYPE_INNER_L4_UDP,
1321         [IXGBE_PACKET_TYPE_VXLAN_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1322                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1323                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1324                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_UDP,
1325         [IXGBE_PACKET_TYPE_VXLAN_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
1326                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1327                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1328                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_SCTP,
1329         [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1330                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1331                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1332                 RTE_PTYPE_INNER_L3_IPV4,
1333         [IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1334                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1335                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1336                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_UDP,
1337         [IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1338                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1339                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1340                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_SCTP,
1341         [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_UDP] =
1342                 RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1343                 RTE_PTYPE_L4_UDP | RTE_PTYPE_TUNNEL_VXLAN |
1344                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1345         [IXGBE_PACKET_TYPE_VXLAN_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |
1346                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1347                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1348                 RTE_PTYPE_INNER_L3_IPV4 | RTE_PTYPE_INNER_L4_SCTP,
1349         [IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1350                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1351                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1352                 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_SCTP,
1353         [IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1354                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1355                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1356                 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_TCP,
1357         [IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1358                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1359                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1360                 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_UDP,
1361 };
1362
1363 /* @note: fix ixgbe_dev_supported_ptypes_get() if any change here. */
1364 static inline uint32_t
1365 ixgbe_rxd_pkt_info_to_pkt_type(uint32_t pkt_info, uint16_t ptype_mask)
1366 {
1367
1368         if (unlikely(pkt_info & IXGBE_RXDADV_PKTTYPE_ETQF))
1369                 return RTE_PTYPE_UNKNOWN;
1370
1371         pkt_info = (pkt_info >> IXGBE_PACKET_TYPE_SHIFT) & ptype_mask;
1372
1373         /* For tunnel packet */
1374         if (pkt_info & IXGBE_PACKET_TYPE_TUNNEL_BIT) {
1375                 /* Remove the tunnel bit to save the space. */
1376                 pkt_info &= IXGBE_PACKET_TYPE_MASK_TUNNEL;
1377                 return ptype_table_tn[pkt_info];
1378         }
1379
1380         /**
1381          * For x550, if it's not tunnel,
1382          * tunnel type bit should be set to 0.
1383          * Reuse 82599's mask.
1384          */
1385         pkt_info &= IXGBE_PACKET_TYPE_MASK_82599;
1386
1387         return ptype_table[pkt_info];
1388 }
1389
1390 static inline uint64_t
1391 ixgbe_rxd_pkt_info_to_pkt_flags(uint16_t pkt_info)
1392 {
1393         static uint64_t ip_rss_types_map[16] __rte_cache_aligned = {
1394                 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
1395                 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
1396                 PKT_RX_RSS_HASH, 0, 0, 0,
1397                 0, 0, 0,  PKT_RX_FDIR,
1398         };
1399 #ifdef RTE_LIBRTE_IEEE1588
1400         static uint64_t ip_pkt_etqf_map[8] = {
1401                 0, 0, 0, PKT_RX_IEEE1588_PTP,
1402                 0, 0, 0, 0,
1403         };
1404
1405         if (likely(pkt_info & IXGBE_RXDADV_PKTTYPE_ETQF))
1406                 return ip_pkt_etqf_map[(pkt_info >> 4) & 0X07] |
1407                                 ip_rss_types_map[pkt_info & 0XF];
1408         else
1409                 return ip_rss_types_map[pkt_info & 0XF];
1410 #else
1411         return ip_rss_types_map[pkt_info & 0XF];
1412 #endif
1413 }
1414
1415 static inline uint64_t
1416 rx_desc_status_to_pkt_flags(uint32_t rx_status, uint64_t vlan_flags)
1417 {
1418         uint64_t pkt_flags;
1419
1420         /*
1421          * Check if VLAN present only.
1422          * Do not check whether L3/L4 rx checksum done by NIC or not,
1423          * That can be found from rte_eth_rxmode.hw_ip_checksum flag
1424          */
1425         pkt_flags = (rx_status & IXGBE_RXD_STAT_VP) ?  vlan_flags : 0;
1426
1427 #ifdef RTE_LIBRTE_IEEE1588
1428         if (rx_status & IXGBE_RXD_STAT_TMST)
1429                 pkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;
1430 #endif
1431         return pkt_flags;
1432 }
1433
1434 static inline uint64_t
1435 rx_desc_error_to_pkt_flags(uint32_t rx_status)
1436 {
1437         uint64_t pkt_flags;
1438
1439         /*
1440          * Bit 31: IPE, IPv4 checksum error
1441          * Bit 30: L4I, L4I integrity error
1442          */
1443         static uint64_t error_to_pkt_flags_map[4] = {
1444                 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD,
1445                 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD,
1446                 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD,
1447                 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
1448         };
1449         pkt_flags = error_to_pkt_flags_map[(rx_status >>
1450                 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
1451
1452         if ((rx_status & IXGBE_RXD_STAT_OUTERIPCS) &&
1453             (rx_status & IXGBE_RXDADV_ERR_OUTERIPER)) {
1454                 pkt_flags |= PKT_RX_EIP_CKSUM_BAD;
1455         }
1456
1457 #ifdef RTE_LIBRTE_SECURITY
1458         if (rx_status & IXGBE_RXD_STAT_SECP) {
1459                 pkt_flags |= PKT_RX_SEC_OFFLOAD;
1460                 if (rx_status & IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG)
1461                         pkt_flags |= PKT_RX_SEC_OFFLOAD_FAILED;
1462         }
1463 #endif
1464
1465         return pkt_flags;
1466 }
1467
1468 /*
1469  * LOOK_AHEAD defines how many desc statuses to check beyond the
1470  * current descriptor.
1471  * It must be a pound define for optimal performance.
1472  * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
1473  * function only works with LOOK_AHEAD=8.
1474  */
1475 #define LOOK_AHEAD 8
1476 #if (LOOK_AHEAD != 8)
1477 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
1478 #endif
1479 static inline int
1480 ixgbe_rx_scan_hw_ring(struct ixgbe_rx_queue *rxq)
1481 {
1482         volatile union ixgbe_adv_rx_desc *rxdp;
1483         struct ixgbe_rx_entry *rxep;
1484         struct rte_mbuf *mb;
1485         uint16_t pkt_len;
1486         uint64_t pkt_flags;
1487         int nb_dd;
1488         uint32_t s[LOOK_AHEAD];
1489         uint32_t pkt_info[LOOK_AHEAD];
1490         int i, j, nb_rx = 0;
1491         uint32_t status;
1492         uint64_t vlan_flags = rxq->vlan_flags;
1493
1494         /* get references to current descriptor and S/W ring entry */
1495         rxdp = &rxq->rx_ring[rxq->rx_tail];
1496         rxep = &rxq->sw_ring[rxq->rx_tail];
1497
1498         status = rxdp->wb.upper.status_error;
1499         /* check to make sure there is at least 1 packet to receive */
1500         if (!(status & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1501                 return 0;
1502
1503         /*
1504          * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
1505          * reference packets that are ready to be received.
1506          */
1507         for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
1508              i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD) {
1509                 /* Read desc statuses backwards to avoid race condition */
1510                 for (j = 0; j < LOOK_AHEAD; j++)
1511                         s[j] = rte_le_to_cpu_32(rxdp[j].wb.upper.status_error);
1512
1513                 rte_smp_rmb();
1514
1515                 /* Compute how many status bits were set */
1516                 for (nb_dd = 0; nb_dd < LOOK_AHEAD &&
1517                                 (s[nb_dd] & IXGBE_RXDADV_STAT_DD); nb_dd++)
1518                         ;
1519
1520                 for (j = 0; j < nb_dd; j++)
1521                         pkt_info[j] = rte_le_to_cpu_32(rxdp[j].wb.lower.
1522                                                        lo_dword.data);
1523
1524                 nb_rx += nb_dd;
1525
1526                 /* Translate descriptor info to mbuf format */
1527                 for (j = 0; j < nb_dd; ++j) {
1528                         mb = rxep[j].mbuf;
1529                         pkt_len = rte_le_to_cpu_16(rxdp[j].wb.upper.length) -
1530                                   rxq->crc_len;
1531                         mb->data_len = pkt_len;
1532                         mb->pkt_len = pkt_len;
1533                         mb->vlan_tci = rte_le_to_cpu_16(rxdp[j].wb.upper.vlan);
1534
1535                         /* convert descriptor fields to rte mbuf flags */
1536                         pkt_flags = rx_desc_status_to_pkt_flags(s[j],
1537                                 vlan_flags);
1538                         pkt_flags |= rx_desc_error_to_pkt_flags(s[j]);
1539                         pkt_flags |= ixgbe_rxd_pkt_info_to_pkt_flags
1540                                         ((uint16_t)pkt_info[j]);
1541                         mb->ol_flags = pkt_flags;
1542                         mb->packet_type =
1543                                 ixgbe_rxd_pkt_info_to_pkt_type
1544                                         (pkt_info[j], rxq->pkt_type_mask);
1545
1546                         if (likely(pkt_flags & PKT_RX_RSS_HASH))
1547                                 mb->hash.rss = rte_le_to_cpu_32(
1548                                     rxdp[j].wb.lower.hi_dword.rss);
1549                         else if (pkt_flags & PKT_RX_FDIR) {
1550                                 mb->hash.fdir.hash = rte_le_to_cpu_16(
1551                                     rxdp[j].wb.lower.hi_dword.csum_ip.csum) &
1552                                     IXGBE_ATR_HASH_MASK;
1553                                 mb->hash.fdir.id = rte_le_to_cpu_16(
1554                                     rxdp[j].wb.lower.hi_dword.csum_ip.ip_id);
1555                         }
1556                 }
1557
1558                 /* Move mbuf pointers from the S/W ring to the stage */
1559                 for (j = 0; j < LOOK_AHEAD; ++j) {
1560                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1561                 }
1562
1563                 /* stop if all requested packets could not be received */
1564                 if (nb_dd != LOOK_AHEAD)
1565                         break;
1566         }
1567
1568         /* clear software ring entries so we can cleanup correctly */
1569         for (i = 0; i < nb_rx; ++i) {
1570                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1571         }
1572
1573
1574         return nb_rx;
1575 }
1576
1577 static inline int
1578 ixgbe_rx_alloc_bufs(struct ixgbe_rx_queue *rxq, bool reset_mbuf)
1579 {
1580         volatile union ixgbe_adv_rx_desc *rxdp;
1581         struct ixgbe_rx_entry *rxep;
1582         struct rte_mbuf *mb;
1583         uint16_t alloc_idx;
1584         __le64 dma_addr;
1585         int diag, i;
1586
1587         /* allocate buffers in bulk directly into the S/W ring */
1588         alloc_idx = rxq->rx_free_trigger - (rxq->rx_free_thresh - 1);
1589         rxep = &rxq->sw_ring[alloc_idx];
1590         diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
1591                                     rxq->rx_free_thresh);
1592         if (unlikely(diag != 0))
1593                 return -ENOMEM;
1594
1595         rxdp = &rxq->rx_ring[alloc_idx];
1596         for (i = 0; i < rxq->rx_free_thresh; ++i) {
1597                 /* populate the static rte mbuf fields */
1598                 mb = rxep[i].mbuf;
1599                 if (reset_mbuf) {
1600                         mb->port = rxq->port_id;
1601                 }
1602
1603                 rte_mbuf_refcnt_set(mb, 1);
1604                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1605
1606                 /* populate the descriptors */
1607                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1608                 rxdp[i].read.hdr_addr = 0;
1609                 rxdp[i].read.pkt_addr = dma_addr;
1610         }
1611
1612         /* update state of internal queue structure */
1613         rxq->rx_free_trigger = rxq->rx_free_trigger + rxq->rx_free_thresh;
1614         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1615                 rxq->rx_free_trigger = rxq->rx_free_thresh - 1;
1616
1617         /* no errors */
1618         return 0;
1619 }
1620
1621 static inline uint16_t
1622 ixgbe_rx_fill_from_stage(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1623                          uint16_t nb_pkts)
1624 {
1625         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1626         int i;
1627
1628         /* how many packets are ready to return? */
1629         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1630
1631         /* copy mbuf pointers to the application's packet list */
1632         for (i = 0; i < nb_pkts; ++i)
1633                 rx_pkts[i] = stage[i];
1634
1635         /* update internal queue state */
1636         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1637         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1638
1639         return nb_pkts;
1640 }
1641
1642 static inline uint16_t
1643 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1644              uint16_t nb_pkts)
1645 {
1646         struct ixgbe_rx_queue *rxq = (struct ixgbe_rx_queue *)rx_queue;
1647         uint16_t nb_rx = 0;
1648
1649         /* Any previously recv'd pkts will be returned from the Rx stage */
1650         if (rxq->rx_nb_avail)
1651                 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1652
1653         /* Scan the H/W ring for packets to receive */
1654         nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);
1655
1656         /* update internal queue state */
1657         rxq->rx_next_avail = 0;
1658         rxq->rx_nb_avail = nb_rx;
1659         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1660
1661         /* if required, allocate new buffers to replenish descriptors */
1662         if (rxq->rx_tail > rxq->rx_free_trigger) {
1663                 uint16_t cur_free_trigger = rxq->rx_free_trigger;
1664
1665                 if (ixgbe_rx_alloc_bufs(rxq, true) != 0) {
1666                         int i, j;
1667
1668                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1669                                    "queue_id=%u", (unsigned) rxq->port_id,
1670                                    (unsigned) rxq->queue_id);
1671
1672                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1673                                 rxq->rx_free_thresh;
1674
1675                         /*
1676                          * Need to rewind any previous receives if we cannot
1677                          * allocate new buffers to replenish the old ones.
1678                          */
1679                         rxq->rx_nb_avail = 0;
1680                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1681                         for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1682                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1683
1684                         return 0;
1685                 }
1686
1687                 /* update tail pointer */
1688                 rte_wmb();
1689                 IXGBE_PCI_REG_WRITE_RELAXED(rxq->rdt_reg_addr,
1690                                             cur_free_trigger);
1691         }
1692
1693         if (rxq->rx_tail >= rxq->nb_rx_desc)
1694                 rxq->rx_tail = 0;
1695
1696         /* received any packets this loop? */
1697         if (rxq->rx_nb_avail)
1698                 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1699
1700         return 0;
1701 }
1702
1703 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1704 uint16_t
1705 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1706                            uint16_t nb_pkts)
1707 {
1708         uint16_t nb_rx;
1709
1710         if (unlikely(nb_pkts == 0))
1711                 return 0;
1712
1713         if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1714                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1715
1716         /* request is relatively large, chunk it up */
1717         nb_rx = 0;
1718         while (nb_pkts) {
1719                 uint16_t ret, n;
1720
1721                 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1722                 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1723                 nb_rx = (uint16_t)(nb_rx + ret);
1724                 nb_pkts = (uint16_t)(nb_pkts - ret);
1725                 if (ret < n)
1726                         break;
1727         }
1728
1729         return nb_rx;
1730 }
1731
1732 uint16_t
1733 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1734                 uint16_t nb_pkts)
1735 {
1736         struct ixgbe_rx_queue *rxq;
1737         volatile union ixgbe_adv_rx_desc *rx_ring;
1738         volatile union ixgbe_adv_rx_desc *rxdp;
1739         struct ixgbe_rx_entry *sw_ring;
1740         struct ixgbe_rx_entry *rxe;
1741         struct rte_mbuf *rxm;
1742         struct rte_mbuf *nmb;
1743         union ixgbe_adv_rx_desc rxd;
1744         uint64_t dma_addr;
1745         uint32_t staterr;
1746         uint32_t pkt_info;
1747         uint16_t pkt_len;
1748         uint16_t rx_id;
1749         uint16_t nb_rx;
1750         uint16_t nb_hold;
1751         uint64_t pkt_flags;
1752         uint64_t vlan_flags;
1753
1754         nb_rx = 0;
1755         nb_hold = 0;
1756         rxq = rx_queue;
1757         rx_id = rxq->rx_tail;
1758         rx_ring = rxq->rx_ring;
1759         sw_ring = rxq->sw_ring;
1760         vlan_flags = rxq->vlan_flags;
1761         while (nb_rx < nb_pkts) {
1762                 /*
1763                  * The order of operations here is important as the DD status
1764                  * bit must not be read after any other descriptor fields.
1765                  * rx_ring and rxdp are pointing to volatile data so the order
1766                  * of accesses cannot be reordered by the compiler. If they were
1767                  * not volatile, they could be reordered which could lead to
1768                  * using invalid descriptor fields when read from rxd.
1769                  */
1770                 rxdp = &rx_ring[rx_id];
1771                 staterr = rxdp->wb.upper.status_error;
1772                 if (!(staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1773                         break;
1774                 rxd = *rxdp;
1775
1776                 /*
1777                  * End of packet.
1778                  *
1779                  * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1780                  * is likely to be invalid and to be dropped by the various
1781                  * validation checks performed by the network stack.
1782                  *
1783                  * Allocate a new mbuf to replenish the RX ring descriptor.
1784                  * If the allocation fails:
1785                  *    - arrange for that RX descriptor to be the first one
1786                  *      being parsed the next time the receive function is
1787                  *      invoked [on the same queue].
1788                  *
1789                  *    - Stop parsing the RX ring and return immediately.
1790                  *
1791                  * This policy do not drop the packet received in the RX
1792                  * descriptor for which the allocation of a new mbuf failed.
1793                  * Thus, it allows that packet to be later retrieved if
1794                  * mbuf have been freed in the mean time.
1795                  * As a side effect, holding RX descriptors instead of
1796                  * systematically giving them back to the NIC may lead to
1797                  * RX ring exhaustion situations.
1798                  * However, the NIC can gracefully prevent such situations
1799                  * to happen by sending specific "back-pressure" flow control
1800                  * frames to its peer(s).
1801                  */
1802                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1803                            "ext_err_stat=0x%08x pkt_len=%u",
1804                            (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1805                            (unsigned) rx_id, (unsigned) staterr,
1806                            (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1807
1808                 nmb = rte_mbuf_raw_alloc(rxq->mb_pool);
1809                 if (nmb == NULL) {
1810                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1811                                    "queue_id=%u", (unsigned) rxq->port_id,
1812                                    (unsigned) rxq->queue_id);
1813                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1814                         break;
1815                 }
1816
1817                 nb_hold++;
1818                 rxe = &sw_ring[rx_id];
1819                 rx_id++;
1820                 if (rx_id == rxq->nb_rx_desc)
1821                         rx_id = 0;
1822
1823                 /* Prefetch next mbuf while processing current one. */
1824                 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1825
1826                 /*
1827                  * When next RX descriptor is on a cache-line boundary,
1828                  * prefetch the next 4 RX descriptors and the next 8 pointers
1829                  * to mbufs.
1830                  */
1831                 if ((rx_id & 0x3) == 0) {
1832                         rte_ixgbe_prefetch(&rx_ring[rx_id]);
1833                         rte_ixgbe_prefetch(&sw_ring[rx_id]);
1834                 }
1835
1836                 rxm = rxe->mbuf;
1837                 rxe->mbuf = nmb;
1838                 dma_addr =
1839                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1840                 rxdp->read.hdr_addr = 0;
1841                 rxdp->read.pkt_addr = dma_addr;
1842
1843                 /*
1844                  * Initialize the returned mbuf.
1845                  * 1) setup generic mbuf fields:
1846                  *    - number of segments,
1847                  *    - next segment,
1848                  *    - packet length,
1849                  *    - RX port identifier.
1850                  * 2) integrate hardware offload data, if any:
1851                  *    - RSS flag & hash,
1852                  *    - IP checksum flag,
1853                  *    - VLAN TCI, if any,
1854                  *    - error flags.
1855                  */
1856                 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1857                                       rxq->crc_len);
1858                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1859                 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
1860                 rxm->nb_segs = 1;
1861                 rxm->next = NULL;
1862                 rxm->pkt_len = pkt_len;
1863                 rxm->data_len = pkt_len;
1864                 rxm->port = rxq->port_id;
1865
1866                 pkt_info = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1867                 /* Only valid if PKT_RX_VLAN set in pkt_flags */
1868                 rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1869
1870                 pkt_flags = rx_desc_status_to_pkt_flags(staterr, vlan_flags);
1871                 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
1872                 pkt_flags = pkt_flags |
1873                         ixgbe_rxd_pkt_info_to_pkt_flags((uint16_t)pkt_info);
1874                 rxm->ol_flags = pkt_flags;
1875                 rxm->packet_type =
1876                         ixgbe_rxd_pkt_info_to_pkt_type(pkt_info,
1877                                                        rxq->pkt_type_mask);
1878
1879                 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1880                         rxm->hash.rss = rte_le_to_cpu_32(
1881                                                 rxd.wb.lower.hi_dword.rss);
1882                 else if (pkt_flags & PKT_RX_FDIR) {
1883                         rxm->hash.fdir.hash = rte_le_to_cpu_16(
1884                                         rxd.wb.lower.hi_dword.csum_ip.csum) &
1885                                         IXGBE_ATR_HASH_MASK;
1886                         rxm->hash.fdir.id = rte_le_to_cpu_16(
1887                                         rxd.wb.lower.hi_dword.csum_ip.ip_id);
1888                 }
1889                 /*
1890                  * Store the mbuf address into the next entry of the array
1891                  * of returned packets.
1892                  */
1893                 rx_pkts[nb_rx++] = rxm;
1894         }
1895         rxq->rx_tail = rx_id;
1896
1897         /*
1898          * If the number of free RX descriptors is greater than the RX free
1899          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1900          * register.
1901          * Update the RDT with the value of the last processed RX descriptor
1902          * minus 1, to guarantee that the RDT register is never equal to the
1903          * RDH register, which creates a "full" ring situtation from the
1904          * hardware point of view...
1905          */
1906         nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1907         if (nb_hold > rxq->rx_free_thresh) {
1908                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1909                            "nb_hold=%u nb_rx=%u",
1910                            (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1911                            (unsigned) rx_id, (unsigned) nb_hold,
1912                            (unsigned) nb_rx);
1913                 rx_id = (uint16_t) ((rx_id == 0) ?
1914                                      (rxq->nb_rx_desc - 1) : (rx_id - 1));
1915                 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1916                 nb_hold = 0;
1917         }
1918         rxq->nb_rx_hold = nb_hold;
1919         return nb_rx;
1920 }
1921
1922 /**
1923  * Detect an RSC descriptor.
1924  */
1925 static inline uint32_t
1926 ixgbe_rsc_count(union ixgbe_adv_rx_desc *rx)
1927 {
1928         return (rte_le_to_cpu_32(rx->wb.lower.lo_dword.data) &
1929                 IXGBE_RXDADV_RSCCNT_MASK) >> IXGBE_RXDADV_RSCCNT_SHIFT;
1930 }
1931
1932 /**
1933  * ixgbe_fill_cluster_head_buf - fill the first mbuf of the returned packet
1934  *
1935  * Fill the following info in the HEAD buffer of the Rx cluster:
1936  *    - RX port identifier
1937  *    - hardware offload data, if any:
1938  *      - RSS flag & hash
1939  *      - IP checksum flag
1940  *      - VLAN TCI, if any
1941  *      - error flags
1942  * @head HEAD of the packet cluster
1943  * @desc HW descriptor to get data from
1944  * @rxq Pointer to the Rx queue
1945  */
1946 static inline void
1947 ixgbe_fill_cluster_head_buf(
1948         struct rte_mbuf *head,
1949         union ixgbe_adv_rx_desc *desc,
1950         struct ixgbe_rx_queue *rxq,
1951         uint32_t staterr)
1952 {
1953         uint32_t pkt_info;
1954         uint64_t pkt_flags;
1955
1956         head->port = rxq->port_id;
1957
1958         /* The vlan_tci field is only valid when PKT_RX_VLAN is
1959          * set in the pkt_flags field.
1960          */
1961         head->vlan_tci = rte_le_to_cpu_16(desc->wb.upper.vlan);
1962         pkt_info = rte_le_to_cpu_32(desc->wb.lower.lo_dword.data);
1963         pkt_flags = rx_desc_status_to_pkt_flags(staterr, rxq->vlan_flags);
1964         pkt_flags |= rx_desc_error_to_pkt_flags(staterr);
1965         pkt_flags |= ixgbe_rxd_pkt_info_to_pkt_flags((uint16_t)pkt_info);
1966         head->ol_flags = pkt_flags;
1967         head->packet_type =
1968                 ixgbe_rxd_pkt_info_to_pkt_type(pkt_info, rxq->pkt_type_mask);
1969
1970         if (likely(pkt_flags & PKT_RX_RSS_HASH))
1971                 head->hash.rss = rte_le_to_cpu_32(desc->wb.lower.hi_dword.rss);
1972         else if (pkt_flags & PKT_RX_FDIR) {
1973                 head->hash.fdir.hash =
1974                         rte_le_to_cpu_16(desc->wb.lower.hi_dword.csum_ip.csum)
1975                                                           & IXGBE_ATR_HASH_MASK;
1976                 head->hash.fdir.id =
1977                         rte_le_to_cpu_16(desc->wb.lower.hi_dword.csum_ip.ip_id);
1978         }
1979 }
1980
1981 /**
1982  * ixgbe_recv_pkts_lro - receive handler for and LRO case.
1983  *
1984  * @rx_queue Rx queue handle
1985  * @rx_pkts table of received packets
1986  * @nb_pkts size of rx_pkts table
1987  * @bulk_alloc if TRUE bulk allocation is used for a HW ring refilling
1988  *
1989  * Handles the Rx HW ring completions when RSC feature is configured. Uses an
1990  * additional ring of ixgbe_rsc_entry's that will hold the relevant RSC info.
1991  *
1992  * We use the same logic as in Linux and in FreeBSD ixgbe drivers:
1993  * 1) When non-EOP RSC completion arrives:
1994  *    a) Update the HEAD of the current RSC aggregation cluster with the new
1995  *       segment's data length.
1996  *    b) Set the "next" pointer of the current segment to point to the segment
1997  *       at the NEXTP index.
1998  *    c) Pass the HEAD of RSC aggregation cluster on to the next NEXTP entry
1999  *       in the sw_rsc_ring.
2000  * 2) When EOP arrives we just update the cluster's total length and offload
2001  *    flags and deliver the cluster up to the upper layers. In our case - put it
2002  *    in the rx_pkts table.
2003  *
2004  * Returns the number of received packets/clusters (according to the "bulk
2005  * receive" interface).
2006  */
2007 static inline uint16_t
2008 ixgbe_recv_pkts_lro(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts,
2009                     bool bulk_alloc)
2010 {
2011         struct ixgbe_rx_queue *rxq = rx_queue;
2012         volatile union ixgbe_adv_rx_desc *rx_ring = rxq->rx_ring;
2013         struct ixgbe_rx_entry *sw_ring = rxq->sw_ring;
2014         struct ixgbe_scattered_rx_entry *sw_sc_ring = rxq->sw_sc_ring;
2015         uint16_t rx_id = rxq->rx_tail;
2016         uint16_t nb_rx = 0;
2017         uint16_t nb_hold = rxq->nb_rx_hold;
2018         uint16_t prev_id = rxq->rx_tail;
2019
2020         while (nb_rx < nb_pkts) {
2021                 bool eop;
2022                 struct ixgbe_rx_entry *rxe;
2023                 struct ixgbe_scattered_rx_entry *sc_entry;
2024                 struct ixgbe_scattered_rx_entry *next_sc_entry;
2025                 struct ixgbe_rx_entry *next_rxe = NULL;
2026                 struct rte_mbuf *first_seg;
2027                 struct rte_mbuf *rxm;
2028                 struct rte_mbuf *nmb;
2029                 union ixgbe_adv_rx_desc rxd;
2030                 uint16_t data_len;
2031                 uint16_t next_id;
2032                 volatile union ixgbe_adv_rx_desc *rxdp;
2033                 uint32_t staterr;
2034
2035 next_desc:
2036                 /*
2037                  * The code in this whole file uses the volatile pointer to
2038                  * ensure the read ordering of the status and the rest of the
2039                  * descriptor fields (on the compiler level only!!!). This is so
2040                  * UGLY - why not to just use the compiler barrier instead? DPDK
2041                  * even has the rte_compiler_barrier() for that.
2042                  *
2043                  * But most importantly this is just wrong because this doesn't
2044                  * ensure memory ordering in a general case at all. For
2045                  * instance, DPDK is supposed to work on Power CPUs where
2046                  * compiler barrier may just not be enough!
2047                  *
2048                  * I tried to write only this function properly to have a
2049                  * starting point (as a part of an LRO/RSC series) but the
2050                  * compiler cursed at me when I tried to cast away the
2051                  * "volatile" from rx_ring (yes, it's volatile too!!!). So, I'm
2052                  * keeping it the way it is for now.
2053                  *
2054                  * The code in this file is broken in so many other places and
2055                  * will just not work on a big endian CPU anyway therefore the
2056                  * lines below will have to be revisited together with the rest
2057                  * of the ixgbe PMD.
2058                  *
2059                  * TODO:
2060                  *    - Get rid of "volatile" crap and let the compiler do its
2061                  *      job.
2062                  *    - Use the proper memory barrier (rte_rmb()) to ensure the
2063                  *      memory ordering below.
2064                  */
2065                 rxdp = &rx_ring[rx_id];
2066                 staterr = rte_le_to_cpu_32(rxdp->wb.upper.status_error);
2067
2068                 if (!(staterr & IXGBE_RXDADV_STAT_DD))
2069                         break;
2070
2071                 rxd = *rxdp;
2072
2073                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
2074                                   "staterr=0x%x data_len=%u",
2075                            rxq->port_id, rxq->queue_id, rx_id, staterr,
2076                            rte_le_to_cpu_16(rxd.wb.upper.length));
2077
2078                 if (!bulk_alloc) {
2079                         nmb = rte_mbuf_raw_alloc(rxq->mb_pool);
2080                         if (nmb == NULL) {
2081                                 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed "
2082                                                   "port_id=%u queue_id=%u",
2083                                            rxq->port_id, rxq->queue_id);
2084
2085                                 rte_eth_devices[rxq->port_id].data->
2086                                                         rx_mbuf_alloc_failed++;
2087                                 break;
2088                         }
2089                 } else if (nb_hold > rxq->rx_free_thresh) {
2090                         uint16_t next_rdt = rxq->rx_free_trigger;
2091
2092                         if (!ixgbe_rx_alloc_bufs(rxq, false)) {
2093                                 rte_wmb();
2094                                 IXGBE_PCI_REG_WRITE_RELAXED(rxq->rdt_reg_addr,
2095                                                             next_rdt);
2096                                 nb_hold -= rxq->rx_free_thresh;
2097                         } else {
2098                                 PMD_RX_LOG(DEBUG, "RX bulk alloc failed "
2099                                                   "port_id=%u queue_id=%u",
2100                                            rxq->port_id, rxq->queue_id);
2101
2102                                 rte_eth_devices[rxq->port_id].data->
2103                                                         rx_mbuf_alloc_failed++;
2104                                 break;
2105                         }
2106                 }
2107
2108                 nb_hold++;
2109                 rxe = &sw_ring[rx_id];
2110                 eop = staterr & IXGBE_RXDADV_STAT_EOP;
2111
2112                 next_id = rx_id + 1;
2113                 if (next_id == rxq->nb_rx_desc)
2114                         next_id = 0;
2115
2116                 /* Prefetch next mbuf while processing current one. */
2117                 rte_ixgbe_prefetch(sw_ring[next_id].mbuf);
2118
2119                 /*
2120                  * When next RX descriptor is on a cache-line boundary,
2121                  * prefetch the next 4 RX descriptors and the next 4 pointers
2122                  * to mbufs.
2123                  */
2124                 if ((next_id & 0x3) == 0) {
2125                         rte_ixgbe_prefetch(&rx_ring[next_id]);
2126                         rte_ixgbe_prefetch(&sw_ring[next_id]);
2127                 }
2128
2129                 rxm = rxe->mbuf;
2130
2131                 if (!bulk_alloc) {
2132                         __le64 dma =
2133                           rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
2134                         /*
2135                          * Update RX descriptor with the physical address of the
2136                          * new data buffer of the new allocated mbuf.
2137                          */
2138                         rxe->mbuf = nmb;
2139
2140                         rxm->data_off = RTE_PKTMBUF_HEADROOM;
2141                         rxdp->read.hdr_addr = 0;
2142                         rxdp->read.pkt_addr = dma;
2143                 } else
2144                         rxe->mbuf = NULL;
2145
2146                 /*
2147                  * Set data length & data buffer address of mbuf.
2148                  */
2149                 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
2150                 rxm->data_len = data_len;
2151
2152                 if (!eop) {
2153                         uint16_t nextp_id;
2154                         /*
2155                          * Get next descriptor index:
2156                          *  - For RSC it's in the NEXTP field.
2157                          *  - For a scattered packet - it's just a following
2158                          *    descriptor.
2159                          */
2160                         if (ixgbe_rsc_count(&rxd))
2161                                 nextp_id =
2162                                         (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
2163                                                        IXGBE_RXDADV_NEXTP_SHIFT;
2164                         else
2165                                 nextp_id = next_id;
2166
2167                         next_sc_entry = &sw_sc_ring[nextp_id];
2168                         next_rxe = &sw_ring[nextp_id];
2169                         rte_ixgbe_prefetch(next_rxe);
2170                 }
2171
2172                 sc_entry = &sw_sc_ring[rx_id];
2173                 first_seg = sc_entry->fbuf;
2174                 sc_entry->fbuf = NULL;
2175
2176                 /*
2177                  * If this is the first buffer of the received packet,
2178                  * set the pointer to the first mbuf of the packet and
2179                  * initialize its context.
2180                  * Otherwise, update the total length and the number of segments
2181                  * of the current scattered packet, and update the pointer to
2182                  * the last mbuf of the current packet.
2183                  */
2184                 if (first_seg == NULL) {
2185                         first_seg = rxm;
2186                         first_seg->pkt_len = data_len;
2187                         first_seg->nb_segs = 1;
2188                 } else {
2189                         first_seg->pkt_len += data_len;
2190                         first_seg->nb_segs++;
2191                 }
2192
2193                 prev_id = rx_id;
2194                 rx_id = next_id;
2195
2196                 /*
2197                  * If this is not the last buffer of the received packet, update
2198                  * the pointer to the first mbuf at the NEXTP entry in the
2199                  * sw_sc_ring and continue to parse the RX ring.
2200                  */
2201                 if (!eop && next_rxe) {
2202                         rxm->next = next_rxe->mbuf;
2203                         next_sc_entry->fbuf = first_seg;
2204                         goto next_desc;
2205                 }
2206
2207                 /* Initialize the first mbuf of the returned packet */
2208                 ixgbe_fill_cluster_head_buf(first_seg, &rxd, rxq, staterr);
2209
2210                 /*
2211                  * Deal with the case, when HW CRC srip is disabled.
2212                  * That can't happen when LRO is enabled, but still could
2213                  * happen for scattered RX mode.
2214                  */
2215                 first_seg->pkt_len -= rxq->crc_len;
2216                 if (unlikely(rxm->data_len <= rxq->crc_len)) {
2217                         struct rte_mbuf *lp;
2218
2219                         for (lp = first_seg; lp->next != rxm; lp = lp->next)
2220                                 ;
2221
2222                         first_seg->nb_segs--;
2223                         lp->data_len -= rxq->crc_len - rxm->data_len;
2224                         lp->next = NULL;
2225                         rte_pktmbuf_free_seg(rxm);
2226                 } else
2227                         rxm->data_len -= rxq->crc_len;
2228
2229                 /* Prefetch data of first segment, if configured to do so. */
2230                 rte_packet_prefetch((char *)first_seg->buf_addr +
2231                         first_seg->data_off);
2232
2233                 /*
2234                  * Store the mbuf address into the next entry of the array
2235                  * of returned packets.
2236                  */
2237                 rx_pkts[nb_rx++] = first_seg;
2238         }
2239
2240         /*
2241          * Record index of the next RX descriptor to probe.
2242          */
2243         rxq->rx_tail = rx_id;
2244
2245         /*
2246          * If the number of free RX descriptors is greater than the RX free
2247          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
2248          * register.
2249          * Update the RDT with the value of the last processed RX descriptor
2250          * minus 1, to guarantee that the RDT register is never equal to the
2251          * RDH register, which creates a "full" ring situtation from the
2252          * hardware point of view...
2253          */
2254         if (!bulk_alloc && nb_hold > rxq->rx_free_thresh) {
2255                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
2256                            "nb_hold=%u nb_rx=%u",
2257                            rxq->port_id, rxq->queue_id, rx_id, nb_hold, nb_rx);
2258
2259                 rte_wmb();
2260                 IXGBE_PCI_REG_WRITE_RELAXED(rxq->rdt_reg_addr, prev_id);
2261                 nb_hold = 0;
2262         }
2263
2264         rxq->nb_rx_hold = nb_hold;
2265         return nb_rx;
2266 }
2267
2268 uint16_t
2269 ixgbe_recv_pkts_lro_single_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
2270                                  uint16_t nb_pkts)
2271 {
2272         return ixgbe_recv_pkts_lro(rx_queue, rx_pkts, nb_pkts, false);
2273 }
2274
2275 uint16_t
2276 ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
2277                                uint16_t nb_pkts)
2278 {
2279         return ixgbe_recv_pkts_lro(rx_queue, rx_pkts, nb_pkts, true);
2280 }
2281
2282 /*********************************************************************
2283  *
2284  *  Queue management functions
2285  *
2286  **********************************************************************/
2287
2288 static void __attribute__((cold))
2289 ixgbe_tx_queue_release_mbufs(struct ixgbe_tx_queue *txq)
2290 {
2291         unsigned i;
2292
2293         if (txq->sw_ring != NULL) {
2294                 for (i = 0; i < txq->nb_tx_desc; i++) {
2295                         if (txq->sw_ring[i].mbuf != NULL) {
2296                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2297                                 txq->sw_ring[i].mbuf = NULL;
2298                         }
2299                 }
2300         }
2301 }
2302
2303 static void __attribute__((cold))
2304 ixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)
2305 {
2306         if (txq != NULL &&
2307             txq->sw_ring != NULL)
2308                 rte_free(txq->sw_ring);
2309 }
2310
2311 static void __attribute__((cold))
2312 ixgbe_tx_queue_release(struct ixgbe_tx_queue *txq)
2313 {
2314         if (txq != NULL && txq->ops != NULL) {
2315                 txq->ops->release_mbufs(txq);
2316                 txq->ops->free_swring(txq);
2317                 rte_free(txq);
2318         }
2319 }
2320
2321 void __attribute__((cold))
2322 ixgbe_dev_tx_queue_release(void *txq)
2323 {
2324         ixgbe_tx_queue_release(txq);
2325 }
2326
2327 /* (Re)set dynamic ixgbe_tx_queue fields to defaults */
2328 static void __attribute__((cold))
2329 ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)
2330 {
2331         static const union ixgbe_adv_tx_desc zeroed_desc = {{0}};
2332         struct ixgbe_tx_entry *txe = txq->sw_ring;
2333         uint16_t prev, i;
2334
2335         /* Zero out HW ring memory */
2336         for (i = 0; i < txq->nb_tx_desc; i++) {
2337                 txq->tx_ring[i] = zeroed_desc;
2338         }
2339
2340         /* Initialize SW ring entries */
2341         prev = (uint16_t) (txq->nb_tx_desc - 1);
2342         for (i = 0; i < txq->nb_tx_desc; i++) {
2343                 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
2344
2345                 txd->wb.status = rte_cpu_to_le_32(IXGBE_TXD_STAT_DD);
2346                 txe[i].mbuf = NULL;
2347                 txe[i].last_id = i;
2348                 txe[prev].next_id = i;
2349                 prev = i;
2350         }
2351
2352         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2353         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2354
2355         txq->tx_tail = 0;
2356         txq->nb_tx_used = 0;
2357         /*
2358          * Always allow 1 descriptor to be un-allocated to avoid
2359          * a H/W race condition
2360          */
2361         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2362         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2363         txq->ctx_curr = 0;
2364         memset((void *)&txq->ctx_cache, 0,
2365                 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
2366 }
2367
2368 static const struct ixgbe_txq_ops def_txq_ops = {
2369         .release_mbufs = ixgbe_tx_queue_release_mbufs,
2370         .free_swring = ixgbe_tx_free_swring,
2371         .reset = ixgbe_reset_tx_queue,
2372 };
2373
2374 /* Takes an ethdev and a queue and sets up the tx function to be used based on
2375  * the queue parameters. Used in tx_queue_setup by primary process and then
2376  * in dev_init by secondary process when attaching to an existing ethdev.
2377  */
2378 void __attribute__((cold))
2379 ixgbe_set_tx_function(struct rte_eth_dev *dev, struct ixgbe_tx_queue *txq)
2380 {
2381         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
2382         if (((txq->txq_flags & IXGBE_SIMPLE_FLAGS) == IXGBE_SIMPLE_FLAGS) &&
2383 #ifdef RTE_LIBRTE_SECURITY
2384                         !(txq->using_ipsec) &&
2385 #endif
2386                         (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
2387                 PMD_INIT_LOG(DEBUG, "Using simple tx code path");
2388                 dev->tx_pkt_prepare = NULL;
2389 #ifdef RTE_IXGBE_INC_VECTOR
2390                 if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
2391                                 (rte_eal_process_type() != RTE_PROC_PRIMARY ||
2392                                         ixgbe_txq_vec_setup(txq) == 0)) {
2393                         PMD_INIT_LOG(DEBUG, "Vector tx enabled.");
2394                         dev->tx_pkt_burst = ixgbe_xmit_pkts_vec;
2395                 } else
2396 #endif
2397                 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
2398         } else {
2399                 PMD_INIT_LOG(DEBUG, "Using full-featured tx code path");
2400                 PMD_INIT_LOG(DEBUG,
2401                                 " - txq_flags = %lx " "[IXGBE_SIMPLE_FLAGS=%lx]",
2402                                 (unsigned long)txq->txq_flags,
2403                                 (unsigned long)IXGBE_SIMPLE_FLAGS);
2404                 PMD_INIT_LOG(DEBUG,
2405                                 " - tx_rs_thresh = %lu " "[RTE_PMD_IXGBE_TX_MAX_BURST=%lu]",
2406                                 (unsigned long)txq->tx_rs_thresh,
2407                                 (unsigned long)RTE_PMD_IXGBE_TX_MAX_BURST);
2408                 dev->tx_pkt_burst = ixgbe_xmit_pkts;
2409                 dev->tx_pkt_prepare = ixgbe_prep_pkts;
2410         }
2411 }
2412
2413 int __attribute__((cold))
2414 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
2415                          uint16_t queue_idx,
2416                          uint16_t nb_desc,
2417                          unsigned int socket_id,
2418                          const struct rte_eth_txconf *tx_conf)
2419 {
2420         const struct rte_memzone *tz;
2421         struct ixgbe_tx_queue *txq;
2422         struct ixgbe_hw     *hw;
2423         uint16_t tx_rs_thresh, tx_free_thresh;
2424
2425         PMD_INIT_FUNC_TRACE();
2426         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2427
2428         /*
2429          * Validate number of transmit descriptors.
2430          * It must not exceed hardware maximum, and must be multiple
2431          * of IXGBE_ALIGN.
2432          */
2433         if (nb_desc % IXGBE_TXD_ALIGN != 0 ||
2434                         (nb_desc > IXGBE_MAX_RING_DESC) ||
2435                         (nb_desc < IXGBE_MIN_RING_DESC)) {
2436                 return -EINVAL;
2437         }
2438
2439         /*
2440          * The following two parameters control the setting of the RS bit on
2441          * transmit descriptors.
2442          * TX descriptors will have their RS bit set after txq->tx_rs_thresh
2443          * descriptors have been used.
2444          * The TX descriptor ring will be cleaned after txq->tx_free_thresh
2445          * descriptors are used or if the number of descriptors required
2446          * to transmit a packet is greater than the number of free TX
2447          * descriptors.
2448          * The following constraints must be satisfied:
2449          *  tx_rs_thresh must be greater than 0.
2450          *  tx_rs_thresh must be less than the size of the ring minus 2.
2451          *  tx_rs_thresh must be less than or equal to tx_free_thresh.
2452          *  tx_rs_thresh must be a divisor of the ring size.
2453          *  tx_free_thresh must be greater than 0.
2454          *  tx_free_thresh must be less than the size of the ring minus 3.
2455          * One descriptor in the TX ring is used as a sentinel to avoid a
2456          * H/W race condition, hence the maximum threshold constraints.
2457          * When set to zero use default values.
2458          */
2459         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2460                         tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2461         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2462                         tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2463         if (tx_rs_thresh >= (nb_desc - 2)) {
2464                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the number "
2465                         "of TX descriptors minus 2. (tx_rs_thresh=%u "
2466                         "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2467                         (int)dev->data->port_id, (int)queue_idx);
2468                 return -(EINVAL);
2469         }
2470         if (tx_rs_thresh > DEFAULT_TX_RS_THRESH) {
2471                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less or equal than %u. "
2472                         "(tx_rs_thresh=%u port=%d queue=%d)",
2473                         DEFAULT_TX_RS_THRESH, (unsigned int)tx_rs_thresh,
2474                         (int)dev->data->port_id, (int)queue_idx);
2475                 return -(EINVAL);
2476         }
2477         if (tx_free_thresh >= (nb_desc - 3)) {
2478                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2479                              "tx_free_thresh must be less than the number of "
2480                              "TX descriptors minus 3. (tx_free_thresh=%u "
2481                              "port=%d queue=%d)",
2482                              (unsigned int)tx_free_thresh,
2483                              (int)dev->data->port_id, (int)queue_idx);
2484                 return -(EINVAL);
2485         }
2486         if (tx_rs_thresh > tx_free_thresh) {
2487                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or equal to "
2488                              "tx_free_thresh. (tx_free_thresh=%u "
2489                              "tx_rs_thresh=%u port=%d queue=%d)",
2490                              (unsigned int)tx_free_thresh,
2491                              (unsigned int)tx_rs_thresh,
2492                              (int)dev->data->port_id,
2493                              (int)queue_idx);
2494                 return -(EINVAL);
2495         }
2496         if ((nb_desc % tx_rs_thresh) != 0) {
2497                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2498                              "number of TX descriptors. (tx_rs_thresh=%u "
2499                              "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2500                              (int)dev->data->port_id, (int)queue_idx);
2501                 return -(EINVAL);
2502         }
2503
2504         /*
2505          * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
2506          * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
2507          * by the NIC and all descriptors are written back after the NIC
2508          * accumulates WTHRESH descriptors.
2509          */
2510         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2511                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2512                              "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
2513                              "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2514                              (int)dev->data->port_id, (int)queue_idx);
2515                 return -(EINVAL);
2516         }
2517
2518         /* Free memory prior to re-allocation if needed... */
2519         if (dev->data->tx_queues[queue_idx] != NULL) {
2520                 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
2521                 dev->data->tx_queues[queue_idx] = NULL;
2522         }
2523
2524         /* First allocate the tx queue data structure */
2525         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct ixgbe_tx_queue),
2526                                  RTE_CACHE_LINE_SIZE, socket_id);
2527         if (txq == NULL)
2528                 return -ENOMEM;
2529
2530         /*
2531          * Allocate TX ring hardware descriptors. A memzone large enough to
2532          * handle the maximum ring size is allocated in order to allow for
2533          * resizing in later calls to the queue setup function.
2534          */
2535         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2536                         sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
2537                         IXGBE_ALIGN, socket_id);
2538         if (tz == NULL) {
2539                 ixgbe_tx_queue_release(txq);
2540                 return -ENOMEM;
2541         }
2542
2543         txq->nb_tx_desc = nb_desc;
2544         txq->tx_rs_thresh = tx_rs_thresh;
2545         txq->tx_free_thresh = tx_free_thresh;
2546         txq->pthresh = tx_conf->tx_thresh.pthresh;
2547         txq->hthresh = tx_conf->tx_thresh.hthresh;
2548         txq->wthresh = tx_conf->tx_thresh.wthresh;
2549         txq->queue_id = queue_idx;
2550         txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2551                 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2552         txq->port_id = dev->data->port_id;
2553         txq->txq_flags = tx_conf->txq_flags;
2554         txq->ops = &def_txq_ops;
2555         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2556 #ifdef RTE_LIBRTE_SECURITY
2557         txq->using_ipsec = !!(dev->data->dev_conf.txmode.offloads &
2558                         DEV_TX_OFFLOAD_SECURITY);
2559 #endif
2560
2561         /*
2562          * Modification to set VFTDT for virtual function if vf is detected
2563          */
2564         if (hw->mac.type == ixgbe_mac_82599_vf ||
2565             hw->mac.type == ixgbe_mac_X540_vf ||
2566             hw->mac.type == ixgbe_mac_X550_vf ||
2567             hw->mac.type == ixgbe_mac_X550EM_x_vf ||
2568             hw->mac.type == ixgbe_mac_X550EM_a_vf)
2569                 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
2570         else
2571                 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));
2572
2573         txq->tx_ring_phys_addr = tz->iova;
2574         txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
2575
2576         /* Allocate software ring */
2577         txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
2578                                 sizeof(struct ixgbe_tx_entry) * nb_desc,
2579                                 RTE_CACHE_LINE_SIZE, socket_id);
2580         if (txq->sw_ring == NULL) {
2581                 ixgbe_tx_queue_release(txq);
2582                 return -ENOMEM;
2583         }
2584         PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
2585                      txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
2586
2587         /* set up vector or scalar TX function as appropriate */
2588         ixgbe_set_tx_function(dev, txq);
2589
2590         txq->ops->reset(txq);
2591
2592         dev->data->tx_queues[queue_idx] = txq;
2593
2594
2595         return 0;
2596 }
2597
2598 /**
2599  * ixgbe_free_sc_cluster - free the not-yet-completed scattered cluster
2600  *
2601  * The "next" pointer of the last segment of (not-yet-completed) RSC clusters
2602  * in the sw_rsc_ring is not set to NULL but rather points to the next
2603  * mbuf of this RSC aggregation (that has not been completed yet and still
2604  * resides on the HW ring). So, instead of calling for rte_pktmbuf_free() we
2605  * will just free first "nb_segs" segments of the cluster explicitly by calling
2606  * an rte_pktmbuf_free_seg().
2607  *
2608  * @m scattered cluster head
2609  */
2610 static void __attribute__((cold))
2611 ixgbe_free_sc_cluster(struct rte_mbuf *m)
2612 {
2613         uint16_t i, nb_segs = m->nb_segs;
2614         struct rte_mbuf *next_seg;
2615
2616         for (i = 0; i < nb_segs; i++) {
2617                 next_seg = m->next;
2618                 rte_pktmbuf_free_seg(m);
2619                 m = next_seg;
2620         }
2621 }
2622
2623 static void __attribute__((cold))
2624 ixgbe_rx_queue_release_mbufs(struct ixgbe_rx_queue *rxq)
2625 {
2626         unsigned i;
2627
2628 #ifdef RTE_IXGBE_INC_VECTOR
2629         /* SSE Vector driver has a different way of releasing mbufs. */
2630         if (rxq->rx_using_sse) {
2631                 ixgbe_rx_queue_release_mbufs_vec(rxq);
2632                 return;
2633         }
2634 #endif
2635
2636         if (rxq->sw_ring != NULL) {
2637                 for (i = 0; i < rxq->nb_rx_desc; i++) {
2638                         if (rxq->sw_ring[i].mbuf != NULL) {
2639                                 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2640                                 rxq->sw_ring[i].mbuf = NULL;
2641                         }
2642                 }
2643                 if (rxq->rx_nb_avail) {
2644                         for (i = 0; i < rxq->rx_nb_avail; ++i) {
2645                                 struct rte_mbuf *mb;
2646
2647                                 mb = rxq->rx_stage[rxq->rx_next_avail + i];
2648                                 rte_pktmbuf_free_seg(mb);
2649                         }
2650                         rxq->rx_nb_avail = 0;
2651                 }
2652         }
2653
2654         if (rxq->sw_sc_ring)
2655                 for (i = 0; i < rxq->nb_rx_desc; i++)
2656                         if (rxq->sw_sc_ring[i].fbuf) {
2657                                 ixgbe_free_sc_cluster(rxq->sw_sc_ring[i].fbuf);
2658                                 rxq->sw_sc_ring[i].fbuf = NULL;
2659                         }
2660 }
2661
2662 static void __attribute__((cold))
2663 ixgbe_rx_queue_release(struct ixgbe_rx_queue *rxq)
2664 {
2665         if (rxq != NULL) {
2666                 ixgbe_rx_queue_release_mbufs(rxq);
2667                 rte_free(rxq->sw_ring);
2668                 rte_free(rxq->sw_sc_ring);
2669                 rte_free(rxq);
2670         }
2671 }
2672
2673 void __attribute__((cold))
2674 ixgbe_dev_rx_queue_release(void *rxq)
2675 {
2676         ixgbe_rx_queue_release(rxq);
2677 }
2678
2679 /*
2680  * Check if Rx Burst Bulk Alloc function can be used.
2681  * Return
2682  *        0: the preconditions are satisfied and the bulk allocation function
2683  *           can be used.
2684  *  -EINVAL: the preconditions are NOT satisfied and the default Rx burst
2685  *           function must be used.
2686  */
2687 static inline int __attribute__((cold))
2688 check_rx_burst_bulk_alloc_preconditions(struct ixgbe_rx_queue *rxq)
2689 {
2690         int ret = 0;
2691
2692         /*
2693          * Make sure the following pre-conditions are satisfied:
2694          *   rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
2695          *   rxq->rx_free_thresh < rxq->nb_rx_desc
2696          *   (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
2697          * Scattered packets are not supported.  This should be checked
2698          * outside of this function.
2699          */
2700         if (!(rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST)) {
2701                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2702                              "rxq->rx_free_thresh=%d, "
2703                              "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2704                              rxq->rx_free_thresh, RTE_PMD_IXGBE_RX_MAX_BURST);
2705                 ret = -EINVAL;
2706         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
2707                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2708                              "rxq->rx_free_thresh=%d, "
2709                              "rxq->nb_rx_desc=%d",
2710                              rxq->rx_free_thresh, rxq->nb_rx_desc);
2711                 ret = -EINVAL;
2712         } else if (!((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0)) {
2713                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2714                              "rxq->nb_rx_desc=%d, "
2715                              "rxq->rx_free_thresh=%d",
2716                              rxq->nb_rx_desc, rxq->rx_free_thresh);
2717                 ret = -EINVAL;
2718         }
2719
2720         return ret;
2721 }
2722
2723 /* Reset dynamic ixgbe_rx_queue fields back to defaults */
2724 static void __attribute__((cold))
2725 ixgbe_reset_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_rx_queue *rxq)
2726 {
2727         static const union ixgbe_adv_rx_desc zeroed_desc = {{0}};
2728         unsigned i;
2729         uint16_t len = rxq->nb_rx_desc;
2730
2731         /*
2732          * By default, the Rx queue setup function allocates enough memory for
2733          * IXGBE_MAX_RING_DESC.  The Rx Burst bulk allocation function requires
2734          * extra memory at the end of the descriptor ring to be zero'd out.
2735          */
2736         if (adapter->rx_bulk_alloc_allowed)
2737                 /* zero out extra memory */
2738                 len += RTE_PMD_IXGBE_RX_MAX_BURST;
2739
2740         /*
2741          * Zero out HW ring memory. Zero out extra memory at the end of
2742          * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2743          * reads extra memory as zeros.
2744          */
2745         for (i = 0; i < len; i++) {
2746                 rxq->rx_ring[i] = zeroed_desc;
2747         }
2748
2749         /*
2750          * initialize extra software ring entries. Space for these extra
2751          * entries is always allocated
2752          */
2753         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2754         for (i = rxq->nb_rx_desc; i < len; ++i) {
2755                 rxq->sw_ring[i].mbuf = &rxq->fake_mbuf;
2756         }
2757
2758         rxq->rx_nb_avail = 0;
2759         rxq->rx_next_avail = 0;
2760         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2761         rxq->rx_tail = 0;
2762         rxq->nb_rx_hold = 0;
2763         rxq->pkt_first_seg = NULL;
2764         rxq->pkt_last_seg = NULL;
2765
2766 #ifdef RTE_IXGBE_INC_VECTOR
2767         rxq->rxrearm_start = 0;
2768         rxq->rxrearm_nb = 0;
2769 #endif
2770 }
2771
2772 int __attribute__((cold))
2773 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2774                          uint16_t queue_idx,
2775                          uint16_t nb_desc,
2776                          unsigned int socket_id,
2777                          const struct rte_eth_rxconf *rx_conf,
2778                          struct rte_mempool *mp)
2779 {
2780         const struct rte_memzone *rz;
2781         struct ixgbe_rx_queue *rxq;
2782         struct ixgbe_hw     *hw;
2783         uint16_t len;
2784         struct ixgbe_adapter *adapter =
2785                 (struct ixgbe_adapter *)dev->data->dev_private;
2786
2787         PMD_INIT_FUNC_TRACE();
2788         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2789
2790         /*
2791          * Validate number of receive descriptors.
2792          * It must not exceed hardware maximum, and must be multiple
2793          * of IXGBE_ALIGN.
2794          */
2795         if (nb_desc % IXGBE_RXD_ALIGN != 0 ||
2796                         (nb_desc > IXGBE_MAX_RING_DESC) ||
2797                         (nb_desc < IXGBE_MIN_RING_DESC)) {
2798                 return -EINVAL;
2799         }
2800
2801         /* Free memory prior to re-allocation if needed... */
2802         if (dev->data->rx_queues[queue_idx] != NULL) {
2803                 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2804                 dev->data->rx_queues[queue_idx] = NULL;
2805         }
2806
2807         /* First allocate the rx queue data structure */
2808         rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct ixgbe_rx_queue),
2809                                  RTE_CACHE_LINE_SIZE, socket_id);
2810         if (rxq == NULL)
2811                 return -ENOMEM;
2812         rxq->mb_pool = mp;
2813         rxq->nb_rx_desc = nb_desc;
2814         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2815         rxq->queue_id = queue_idx;
2816         rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2817                 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2818         rxq->port_id = dev->data->port_id;
2819         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2820                                                         0 : ETHER_CRC_LEN);
2821         rxq->drop_en = rx_conf->rx_drop_en;
2822         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2823         rxq->offloads = rx_conf->offloads;
2824
2825         /*
2826          * The packet type in RX descriptor is different for different NICs.
2827          * Some bits are used for x550 but reserved for other NICS.
2828          * So set different masks for different NICs.
2829          */
2830         if (hw->mac.type == ixgbe_mac_X550 ||
2831             hw->mac.type == ixgbe_mac_X550EM_x ||
2832             hw->mac.type == ixgbe_mac_X550EM_a ||
2833             hw->mac.type == ixgbe_mac_X550_vf ||
2834             hw->mac.type == ixgbe_mac_X550EM_x_vf ||
2835             hw->mac.type == ixgbe_mac_X550EM_a_vf)
2836                 rxq->pkt_type_mask = IXGBE_PACKET_TYPE_MASK_X550;
2837         else
2838                 rxq->pkt_type_mask = IXGBE_PACKET_TYPE_MASK_82599;
2839
2840         /*
2841          * Allocate RX ring hardware descriptors. A memzone large enough to
2842          * handle the maximum ring size is allocated in order to allow for
2843          * resizing in later calls to the queue setup function.
2844          */
2845         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
2846                                       RX_RING_SZ, IXGBE_ALIGN, socket_id);
2847         if (rz == NULL) {
2848                 ixgbe_rx_queue_release(rxq);
2849                 return -ENOMEM;
2850         }
2851
2852         /*
2853          * Zero init all the descriptors in the ring.
2854          */
2855         memset(rz->addr, 0, RX_RING_SZ);
2856
2857         /*
2858          * Modified to setup VFRDT for Virtual Function
2859          */
2860         if (hw->mac.type == ixgbe_mac_82599_vf ||
2861             hw->mac.type == ixgbe_mac_X540_vf ||
2862             hw->mac.type == ixgbe_mac_X550_vf ||
2863             hw->mac.type == ixgbe_mac_X550EM_x_vf ||
2864             hw->mac.type == ixgbe_mac_X550EM_a_vf) {
2865                 rxq->rdt_reg_addr =
2866                         IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
2867                 rxq->rdh_reg_addr =
2868                         IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));
2869         } else {
2870                 rxq->rdt_reg_addr =
2871                         IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));
2872                 rxq->rdh_reg_addr =
2873                         IXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));
2874         }
2875
2876         rxq->rx_ring_phys_addr = rz->iova;
2877         rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
2878
2879         /*
2880          * Certain constraints must be met in order to use the bulk buffer
2881          * allocation Rx burst function. If any of Rx queues doesn't meet them
2882          * the feature should be disabled for the whole port.
2883          */
2884         if (check_rx_burst_bulk_alloc_preconditions(rxq)) {
2885                 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Rx Bulk Alloc "
2886                                     "preconditions - canceling the feature for "
2887                                     "the whole port[%d]",
2888                              rxq->queue_id, rxq->port_id);
2889                 adapter->rx_bulk_alloc_allowed = false;
2890         }
2891
2892         /*
2893          * Allocate software ring. Allow for space at the end of the
2894          * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
2895          * function does not access an invalid memory region.
2896          */
2897         len = nb_desc;
2898         if (adapter->rx_bulk_alloc_allowed)
2899                 len += RTE_PMD_IXGBE_RX_MAX_BURST;
2900
2901         rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
2902                                           sizeof(struct ixgbe_rx_entry) * len,
2903                                           RTE_CACHE_LINE_SIZE, socket_id);
2904         if (!rxq->sw_ring) {
2905                 ixgbe_rx_queue_release(rxq);
2906                 return -ENOMEM;
2907         }
2908
2909         /*
2910          * Always allocate even if it's not going to be needed in order to
2911          * simplify the code.
2912          *
2913          * This ring is used in LRO and Scattered Rx cases and Scattered Rx may
2914          * be requested in ixgbe_dev_rx_init(), which is called later from
2915          * dev_start() flow.
2916          */
2917         rxq->sw_sc_ring =
2918                 rte_zmalloc_socket("rxq->sw_sc_ring",
2919                                    sizeof(struct ixgbe_scattered_rx_entry) * len,
2920                                    RTE_CACHE_LINE_SIZE, socket_id);
2921         if (!rxq->sw_sc_ring) {
2922                 ixgbe_rx_queue_release(rxq);
2923                 return -ENOMEM;
2924         }
2925
2926         PMD_INIT_LOG(DEBUG, "sw_ring=%p sw_sc_ring=%p hw_ring=%p "
2927                             "dma_addr=0x%"PRIx64,
2928                      rxq->sw_ring, rxq->sw_sc_ring, rxq->rx_ring,
2929                      rxq->rx_ring_phys_addr);
2930
2931         if (!rte_is_power_of_2(nb_desc)) {
2932                 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Vector Rx "
2933                                     "preconditions - canceling the feature for "
2934                                     "the whole port[%d]",
2935                              rxq->queue_id, rxq->port_id);
2936                 adapter->rx_vec_allowed = false;
2937         } else
2938                 ixgbe_rxq_vec_setup(rxq);
2939
2940         dev->data->rx_queues[queue_idx] = rxq;
2941
2942         ixgbe_reset_rx_queue(adapter, rxq);
2943
2944         return 0;
2945 }
2946
2947 uint32_t
2948 ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2949 {
2950 #define IXGBE_RXQ_SCAN_INTERVAL 4
2951         volatile union ixgbe_adv_rx_desc *rxdp;
2952         struct ixgbe_rx_queue *rxq;
2953         uint32_t desc = 0;
2954
2955         rxq = dev->data->rx_queues[rx_queue_id];
2956         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2957
2958         while ((desc < rxq->nb_rx_desc) &&
2959                 (rxdp->wb.upper.status_error &
2960                         rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD))) {
2961                 desc += IXGBE_RXQ_SCAN_INTERVAL;
2962                 rxdp += IXGBE_RXQ_SCAN_INTERVAL;
2963                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2964                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
2965                                 desc - rxq->nb_rx_desc]);
2966         }
2967
2968         return desc;
2969 }
2970
2971 int
2972 ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2973 {
2974         volatile union ixgbe_adv_rx_desc *rxdp;
2975         struct ixgbe_rx_queue *rxq = rx_queue;
2976         uint32_t desc;
2977
2978         if (unlikely(offset >= rxq->nb_rx_desc))
2979                 return 0;
2980         desc = rxq->rx_tail + offset;
2981         if (desc >= rxq->nb_rx_desc)
2982                 desc -= rxq->nb_rx_desc;
2983
2984         rxdp = &rxq->rx_ring[desc];
2985         return !!(rxdp->wb.upper.status_error &
2986                         rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD));
2987 }
2988
2989 int
2990 ixgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
2991 {
2992         struct ixgbe_rx_queue *rxq = rx_queue;
2993         volatile uint32_t *status;
2994         uint32_t nb_hold, desc;
2995
2996         if (unlikely(offset >= rxq->nb_rx_desc))
2997                 return -EINVAL;
2998
2999 #ifdef RTE_IXGBE_INC_VECTOR
3000         if (rxq->rx_using_sse)
3001                 nb_hold = rxq->rxrearm_nb;
3002         else
3003 #endif
3004                 nb_hold = rxq->nb_rx_hold;
3005         if (offset >= rxq->nb_rx_desc - nb_hold)
3006                 return RTE_ETH_RX_DESC_UNAVAIL;
3007
3008         desc = rxq->rx_tail + offset;
3009         if (desc >= rxq->nb_rx_desc)
3010                 desc -= rxq->nb_rx_desc;
3011
3012         status = &rxq->rx_ring[desc].wb.upper.status_error;
3013         if (*status & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD))
3014                 return RTE_ETH_RX_DESC_DONE;
3015
3016         return RTE_ETH_RX_DESC_AVAIL;
3017 }
3018
3019 int
3020 ixgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
3021 {
3022         struct ixgbe_tx_queue *txq = tx_queue;
3023         volatile uint32_t *status;
3024         uint32_t desc;
3025
3026         if (unlikely(offset >= txq->nb_tx_desc))
3027                 return -EINVAL;
3028
3029         desc = txq->tx_tail + offset;
3030         /* go to next desc that has the RS bit */
3031         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
3032                 txq->tx_rs_thresh;
3033         if (desc >= txq->nb_tx_desc) {
3034                 desc -= txq->nb_tx_desc;
3035                 if (desc >= txq->nb_tx_desc)
3036                         desc -= txq->nb_tx_desc;
3037         }
3038
3039         status = &txq->tx_ring[desc].wb.status;
3040         if (*status & rte_cpu_to_le_32(IXGBE_ADVTXD_STAT_DD))
3041                 return RTE_ETH_TX_DESC_DONE;
3042
3043         return RTE_ETH_TX_DESC_FULL;
3044 }
3045
3046 void __attribute__((cold))
3047 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
3048 {
3049         unsigned i;
3050         struct ixgbe_adapter *adapter =
3051                 (struct ixgbe_adapter *)dev->data->dev_private;
3052
3053         PMD_INIT_FUNC_TRACE();
3054
3055         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3056                 struct ixgbe_tx_queue *txq = dev->data->tx_queues[i];
3057
3058                 if (txq != NULL) {
3059                         txq->ops->release_mbufs(txq);
3060                         txq->ops->reset(txq);
3061                 }
3062         }
3063
3064         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3065                 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
3066
3067                 if (rxq != NULL) {
3068                         ixgbe_rx_queue_release_mbufs(rxq);
3069                         ixgbe_reset_rx_queue(adapter, rxq);
3070                 }
3071         }
3072 }
3073
3074 void
3075 ixgbe_dev_free_queues(struct rte_eth_dev *dev)
3076 {
3077         unsigned i;
3078
3079         PMD_INIT_FUNC_TRACE();
3080
3081         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3082                 ixgbe_dev_rx_queue_release(dev->data->rx_queues[i]);
3083                 dev->data->rx_queues[i] = NULL;
3084         }
3085         dev->data->nb_rx_queues = 0;
3086
3087         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3088                 ixgbe_dev_tx_queue_release(dev->data->tx_queues[i]);
3089                 dev->data->tx_queues[i] = NULL;
3090         }
3091         dev->data->nb_tx_queues = 0;
3092 }
3093
3094 /*********************************************************************
3095  *
3096  *  Device RX/TX init functions
3097  *
3098  **********************************************************************/
3099
3100 /**
3101  * Receive Side Scaling (RSS)
3102  * See section 7.1.2.8 in the following document:
3103  *     "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
3104  *
3105  * Principles:
3106  * The source and destination IP addresses of the IP header and the source
3107  * and destination ports of TCP/UDP headers, if any, of received packets are
3108  * hashed against a configurable random key to compute a 32-bit RSS hash result.
3109  * The seven (7) LSBs of the 32-bit hash result are used as an index into a
3110  * 128-entry redirection table (RETA).  Each entry of the RETA provides a 3-bit
3111  * RSS output index which is used as the RX queue index where to store the
3112  * received packets.
3113  * The following output is supplied in the RX write-back descriptor:
3114  *     - 32-bit result of the Microsoft RSS hash function,
3115  *     - 4-bit RSS type field.
3116  */
3117
3118 /*
3119  * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
3120  * Used as the default key.
3121  */
3122 static uint8_t rss_intel_key[40] = {
3123         0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
3124         0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
3125         0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
3126         0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
3127         0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
3128 };
3129
3130 static void
3131 ixgbe_rss_disable(struct rte_eth_dev *dev)
3132 {
3133         struct ixgbe_hw *hw;
3134         uint32_t mrqc;
3135         uint32_t mrqc_reg;
3136
3137         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3138         mrqc_reg = ixgbe_mrqc_reg_get(hw->mac.type);
3139         mrqc = IXGBE_READ_REG(hw, mrqc_reg);
3140         mrqc &= ~IXGBE_MRQC_RSSEN;
3141         IXGBE_WRITE_REG(hw, mrqc_reg, mrqc);
3142 }
3143
3144 static void
3145 ixgbe_hw_rss_hash_set(struct ixgbe_hw *hw, struct rte_eth_rss_conf *rss_conf)
3146 {
3147         uint8_t  *hash_key;
3148         uint32_t mrqc;
3149         uint32_t rss_key;
3150         uint64_t rss_hf;
3151         uint16_t i;
3152         uint32_t mrqc_reg;
3153         uint32_t rssrk_reg;
3154
3155         mrqc_reg = ixgbe_mrqc_reg_get(hw->mac.type);
3156         rssrk_reg = ixgbe_rssrk_reg_get(hw->mac.type, 0);
3157
3158         hash_key = rss_conf->rss_key;
3159         if (hash_key != NULL) {
3160                 /* Fill in RSS hash key */
3161                 for (i = 0; i < 10; i++) {
3162                         rss_key  = hash_key[(i * 4)];
3163                         rss_key |= hash_key[(i * 4) + 1] << 8;
3164                         rss_key |= hash_key[(i * 4) + 2] << 16;
3165                         rss_key |= hash_key[(i * 4) + 3] << 24;
3166                         IXGBE_WRITE_REG_ARRAY(hw, rssrk_reg, i, rss_key);
3167                 }
3168         }
3169
3170         /* Set configured hashing protocols in MRQC register */
3171         rss_hf = rss_conf->rss_hf;
3172         mrqc = IXGBE_MRQC_RSSEN; /* Enable RSS */
3173         if (rss_hf & ETH_RSS_IPV4)
3174                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
3175         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
3176                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
3177         if (rss_hf & ETH_RSS_IPV6)
3178                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
3179         if (rss_hf & ETH_RSS_IPV6_EX)
3180                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
3181         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
3182                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3183         if (rss_hf & ETH_RSS_IPV6_TCP_EX)
3184                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
3185         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
3186                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3187         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
3188                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3189         if (rss_hf & ETH_RSS_IPV6_UDP_EX)
3190                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
3191         IXGBE_WRITE_REG(hw, mrqc_reg, mrqc);
3192 }
3193
3194 int
3195 ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
3196                           struct rte_eth_rss_conf *rss_conf)
3197 {
3198         struct ixgbe_hw *hw;
3199         uint32_t mrqc;
3200         uint64_t rss_hf;
3201         uint32_t mrqc_reg;
3202
3203         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3204
3205         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3206                 PMD_DRV_LOG(ERR, "RSS hash update is not supported on this "
3207                         "NIC.");
3208                 return -ENOTSUP;
3209         }
3210         mrqc_reg = ixgbe_mrqc_reg_get(hw->mac.type);
3211
3212         /*
3213          * Excerpt from section 7.1.2.8 Receive-Side Scaling (RSS):
3214          *     "RSS enabling cannot be done dynamically while it must be
3215          *      preceded by a software reset"
3216          * Before changing anything, first check that the update RSS operation
3217          * does not attempt to disable RSS, if RSS was enabled at
3218          * initialization time, or does not attempt to enable RSS, if RSS was
3219          * disabled at initialization time.
3220          */
3221         rss_hf = rss_conf->rss_hf & IXGBE_RSS_OFFLOAD_ALL;
3222         mrqc = IXGBE_READ_REG(hw, mrqc_reg);
3223         if (!(mrqc & IXGBE_MRQC_RSSEN)) { /* RSS disabled */
3224                 if (rss_hf != 0) /* Enable RSS */
3225                         return -(EINVAL);
3226                 return 0; /* Nothing to do */
3227         }
3228         /* RSS enabled */
3229         if (rss_hf == 0) /* Disable RSS */
3230                 return -(EINVAL);
3231         ixgbe_hw_rss_hash_set(hw, rss_conf);
3232         return 0;
3233 }
3234
3235 int
3236 ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
3237                             struct rte_eth_rss_conf *rss_conf)
3238 {
3239         struct ixgbe_hw *hw;
3240         uint8_t *hash_key;
3241         uint32_t mrqc;
3242         uint32_t rss_key;
3243         uint64_t rss_hf;
3244         uint16_t i;
3245         uint32_t mrqc_reg;
3246         uint32_t rssrk_reg;
3247
3248         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3249         mrqc_reg = ixgbe_mrqc_reg_get(hw->mac.type);
3250         rssrk_reg = ixgbe_rssrk_reg_get(hw->mac.type, 0);
3251         hash_key = rss_conf->rss_key;
3252         if (hash_key != NULL) {
3253                 /* Return RSS hash key */
3254                 for (i = 0; i < 10; i++) {
3255                         rss_key = IXGBE_READ_REG_ARRAY(hw, rssrk_reg, i);
3256                         hash_key[(i * 4)] = rss_key & 0x000000FF;
3257                         hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;
3258                         hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;
3259                         hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;
3260                 }
3261         }
3262
3263         /* Get RSS functions configured in MRQC register */
3264         mrqc = IXGBE_READ_REG(hw, mrqc_reg);
3265         if ((mrqc & IXGBE_MRQC_RSSEN) == 0) { /* RSS is disabled */
3266                 rss_conf->rss_hf = 0;
3267                 return 0;
3268         }
3269         rss_hf = 0;
3270         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4)
3271                 rss_hf |= ETH_RSS_IPV4;
3272         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_TCP)
3273                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
3274         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6)
3275                 rss_hf |= ETH_RSS_IPV6;
3276         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX)
3277                 rss_hf |= ETH_RSS_IPV6_EX;
3278         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_TCP)
3279                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
3280         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP)
3281                 rss_hf |= ETH_RSS_IPV6_TCP_EX;
3282         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_UDP)
3283                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
3284         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_UDP)
3285                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
3286         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP)
3287                 rss_hf |= ETH_RSS_IPV6_UDP_EX;
3288         rss_conf->rss_hf = rss_hf;
3289         return 0;
3290 }
3291
3292 static void
3293 ixgbe_rss_configure(struct rte_eth_dev *dev)
3294 {
3295         struct rte_eth_rss_conf rss_conf;
3296         struct ixgbe_hw *hw;
3297         uint32_t reta;
3298         uint16_t i;
3299         uint16_t j;
3300         uint16_t sp_reta_size;
3301         uint32_t reta_reg;
3302
3303         PMD_INIT_FUNC_TRACE();
3304         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3305
3306         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3307
3308         /*
3309          * Fill in redirection table
3310          * The byte-swap is needed because NIC registers are in
3311          * little-endian order.
3312          */
3313         reta = 0;
3314         for (i = 0, j = 0; i < sp_reta_size; i++, j++) {
3315                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3316
3317                 if (j == dev->data->nb_rx_queues)
3318                         j = 0;
3319                 reta = (reta << 8) | j;
3320                 if ((i & 3) == 3)
3321                         IXGBE_WRITE_REG(hw, reta_reg,
3322                                         rte_bswap32(reta));
3323         }
3324
3325         /*
3326          * Configure the RSS key and the RSS protocols used to compute
3327          * the RSS hash of input packets.
3328          */
3329         rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
3330         if ((rss_conf.rss_hf & IXGBE_RSS_OFFLOAD_ALL) == 0) {
3331                 ixgbe_rss_disable(dev);
3332                 return;
3333         }
3334         if (rss_conf.rss_key == NULL)
3335                 rss_conf.rss_key = rss_intel_key; /* Default hash key */
3336         ixgbe_hw_rss_hash_set(hw, &rss_conf);
3337 }
3338
3339 #define NUM_VFTA_REGISTERS 128
3340 #define NIC_RX_BUFFER_SIZE 0x200
3341 #define X550_RX_BUFFER_SIZE 0x180
3342
3343 static void
3344 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
3345 {
3346         struct rte_eth_vmdq_dcb_conf *cfg;
3347         struct ixgbe_hw *hw;
3348         enum rte_eth_nb_pools num_pools;
3349         uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
3350         uint16_t pbsize;
3351         uint8_t nb_tcs; /* number of traffic classes */
3352         int i;
3353
3354         PMD_INIT_FUNC_TRACE();
3355         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3356         cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
3357         num_pools = cfg->nb_queue_pools;
3358         /* Check we have a valid number of pools */
3359         if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
3360                 ixgbe_rss_disable(dev);
3361                 return;
3362         }
3363         /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
3364         nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
3365
3366         /*
3367          * RXPBSIZE
3368          * split rx buffer up into sections, each for 1 traffic class
3369          */
3370         switch (hw->mac.type) {
3371         case ixgbe_mac_X550:
3372         case ixgbe_mac_X550EM_x:
3373         case ixgbe_mac_X550EM_a:
3374                 pbsize = (uint16_t)(X550_RX_BUFFER_SIZE / nb_tcs);
3375                 break;
3376         default:
3377                 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
3378                 break;
3379         }
3380         for (i = 0; i < nb_tcs; i++) {
3381                 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
3382
3383                 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
3384                 /* clear 10 bits. */
3385                 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
3386                 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
3387         }
3388         /* zero alloc all unused TCs */
3389         for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3390                 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
3391
3392                 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
3393                 /* clear 10 bits. */
3394                 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
3395         }
3396
3397         /* MRQC: enable vmdq and dcb */
3398         mrqc = (num_pools == ETH_16_POOLS) ?
3399                 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN;
3400         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3401
3402         /* PFVTCTL: turn on virtualisation and set the default pool */
3403         vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3404         if (cfg->enable_default_pool) {
3405                 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3406         } else {
3407                 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3408         }
3409
3410         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3411
3412         /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
3413         queue_mapping = 0;
3414         for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
3415                 /*
3416                  * mapping is done with 3 bits per priority,
3417                  * so shift by i*3 each time
3418                  */
3419                 queue_mapping |= ((cfg->dcb_tc[i] & 0x07) << (i * 3));
3420
3421         IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
3422
3423         /* RTRPCS: DCB related */
3424         IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
3425
3426         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3427         vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3428         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
3429         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3430
3431         /* VFTA - enable all vlan filters */
3432         for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
3433                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
3434         }
3435
3436         /* VFRE: pool enabling for receive - 16 or 32 */
3437         IXGBE_WRITE_REG(hw, IXGBE_VFRE(0),
3438                         num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
3439
3440         /*
3441          * MPSAR - allow pools to read specific mac addresses
3442          * In this case, all pools should be able to read from mac addr 0
3443          */
3444         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
3445         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
3446
3447         /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3448         for (i = 0; i < cfg->nb_pool_maps; i++) {
3449                 /* set vlan id in VF register and set the valid bit */
3450                 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN |
3451                                 (cfg->pool_map[i].vlan_id & 0xFFF)));
3452                 /*
3453                  * Put the allowed pools in VFB reg. As we only have 16 or 32
3454                  * pools, we only need to use the first half of the register
3455                  * i.e. bits 0-31
3456                  */
3457                 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
3458         }
3459 }
3460
3461 /**
3462  * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
3463  * @dev: pointer to eth_dev structure
3464  * @dcb_config: pointer to ixgbe_dcb_config structure
3465  */
3466 static void
3467 ixgbe_dcb_tx_hw_config(struct rte_eth_dev *dev,
3468                        struct ixgbe_dcb_config *dcb_config)
3469 {
3470         uint32_t reg;
3471         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3472
3473         PMD_INIT_FUNC_TRACE();
3474         if (hw->mac.type != ixgbe_mac_82598EB) {
3475                 /* Disable the Tx desc arbiter so that MTQC can be changed */
3476                 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3477                 reg |= IXGBE_RTTDCS_ARBDIS;
3478                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3479
3480                 /* Enable DCB for Tx with 8 TCs */
3481                 if (dcb_config->num_tcs.pg_tcs == 8) {
3482                         reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3483                 } else {
3484                         reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3485                 }
3486                 if (dcb_config->vt_mode)
3487                         reg |= IXGBE_MTQC_VT_ENA;
3488                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3489
3490                 /* Enable the Tx desc arbiter */
3491                 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3492                 reg &= ~IXGBE_RTTDCS_ARBDIS;
3493                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3494
3495                 /* Enable Security TX Buffer IFG for DCB */
3496                 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3497                 reg |= IXGBE_SECTX_DCB;
3498                 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
3499         }
3500 }
3501
3502 /**
3503  * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
3504  * @dev: pointer to rte_eth_dev structure
3505  * @dcb_config: pointer to ixgbe_dcb_config structure
3506  */
3507 static void
3508 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
3509                         struct ixgbe_dcb_config *dcb_config)
3510 {
3511         struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
3512                         &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
3513         struct ixgbe_hw *hw =
3514                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3515
3516         PMD_INIT_FUNC_TRACE();
3517         if (hw->mac.type != ixgbe_mac_82598EB)
3518                 /*PF VF Transmit Enable*/
3519                 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
3520                         vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
3521
3522         /*Configure general DCB TX parameters*/
3523         ixgbe_dcb_tx_hw_config(dev, dcb_config);
3524 }
3525
3526 static void
3527 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
3528                         struct ixgbe_dcb_config *dcb_config)
3529 {
3530         struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
3531                         &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
3532         struct ixgbe_dcb_tc_config *tc;
3533         uint8_t i, j;
3534
3535         /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
3536         if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS) {
3537                 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
3538                 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
3539         } else {
3540                 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
3541                 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
3542         }
3543
3544         /* Initialize User Priority to Traffic Class mapping */
3545         for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {
3546                 tc = &dcb_config->tc_config[j];
3547                 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0;
3548         }
3549
3550         /* User Priority to Traffic Class mapping */
3551         for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3552                 j = vmdq_rx_conf->dcb_tc[i];
3553                 tc = &dcb_config->tc_config[j];
3554                 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap |=
3555                                                 (uint8_t)(1 << i);
3556         }
3557 }
3558
3559 static void
3560 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
3561                         struct ixgbe_dcb_config *dcb_config)
3562 {
3563         struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
3564                         &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
3565         struct ixgbe_dcb_tc_config *tc;
3566         uint8_t i, j;
3567
3568         /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
3569         if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS) {
3570                 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
3571                 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
3572         } else {
3573                 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
3574                 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
3575         }
3576
3577         /* Initialize User Priority to Traffic Class mapping */
3578         for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {
3579                 tc = &dcb_config->tc_config[j];
3580                 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0;
3581         }
3582
3583         /* User Priority to Traffic Class mapping */
3584         for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3585                 j = vmdq_tx_conf->dcb_tc[i];
3586                 tc = &dcb_config->tc_config[j];
3587                 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap |=
3588                                                 (uint8_t)(1 << i);
3589         }
3590 }
3591
3592 static void
3593 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,
3594                 struct ixgbe_dcb_config *dcb_config)
3595 {
3596         struct rte_eth_dcb_rx_conf *rx_conf =
3597                         &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
3598         struct ixgbe_dcb_tc_config *tc;
3599         uint8_t i, j;
3600
3601         dcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;
3602         dcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;
3603
3604         /* Initialize User Priority to Traffic Class mapping */
3605         for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {
3606                 tc = &dcb_config->tc_config[j];
3607                 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0;
3608         }
3609
3610         /* User Priority to Traffic Class mapping */
3611         for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3612                 j = rx_conf->dcb_tc[i];
3613                 tc = &dcb_config->tc_config[j];
3614                 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap |=
3615                                                 (uint8_t)(1 << i);
3616         }
3617 }
3618
3619 static void
3620 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,
3621                 struct ixgbe_dcb_config *dcb_config)
3622 {
3623         struct rte_eth_dcb_tx_conf *tx_conf =
3624                         &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
3625         struct ixgbe_dcb_tc_config *tc;
3626         uint8_t i, j;
3627
3628         dcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;
3629         dcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;
3630
3631         /* Initialize User Priority to Traffic Class mapping */
3632         for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {
3633                 tc = &dcb_config->tc_config[j];
3634                 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0;
3635         }
3636
3637         /* User Priority to Traffic Class mapping */
3638         for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3639                 j = tx_conf->dcb_tc[i];
3640                 tc = &dcb_config->tc_config[j];
3641                 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap |=
3642                                                 (uint8_t)(1 << i);
3643         }
3644 }
3645
3646 /**
3647  * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
3648  * @dev: pointer to eth_dev structure
3649  * @dcb_config: pointer to ixgbe_dcb_config structure
3650  */
3651 static void
3652 ixgbe_dcb_rx_hw_config(struct rte_eth_dev *dev,
3653                        struct ixgbe_dcb_config *dcb_config)
3654 {
3655         uint32_t reg;
3656         uint32_t vlanctrl;
3657         uint8_t i;
3658         uint32_t q;
3659         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3660
3661         PMD_INIT_FUNC_TRACE();
3662         /*
3663          * Disable the arbiter before changing parameters
3664          * (always enable recycle mode; WSP)
3665          */
3666         reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
3667         IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
3668
3669         if (hw->mac.type != ixgbe_mac_82598EB) {
3670                 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
3671                 if (dcb_config->num_tcs.pg_tcs == 4) {
3672                         if (dcb_config->vt_mode)
3673                                 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3674                                         IXGBE_MRQC_VMDQRT4TCEN;
3675                         else {
3676                                 /* no matter the mode is DCB or DCB_RSS, just
3677                                  * set the MRQE to RSSXTCEN. RSS is controlled
3678                                  * by RSS_FIELD
3679                                  */
3680                                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
3681                                 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3682                                         IXGBE_MRQC_RTRSS4TCEN;
3683                         }
3684                 }
3685                 if (dcb_config->num_tcs.pg_tcs == 8) {
3686                         if (dcb_config->vt_mode)
3687                                 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3688                                         IXGBE_MRQC_VMDQRT8TCEN;
3689                         else {
3690                                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
3691                                 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3692                                         IXGBE_MRQC_RTRSS8TCEN;
3693                         }
3694                 }
3695
3696                 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
3697
3698                 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3699                         /* Disable drop for all queues in VMDQ mode*/
3700                         for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3701                                 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3702                                                 (IXGBE_QDE_WRITE |
3703                                                  (q << IXGBE_QDE_IDX_SHIFT)));
3704                 } else {
3705                         /* Enable drop for all queues in SRIOV mode */
3706                         for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3707                                 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3708                                                 (IXGBE_QDE_WRITE |
3709                                                  (q << IXGBE_QDE_IDX_SHIFT) |
3710                                                  IXGBE_QDE_ENABLE));
3711                 }
3712         }
3713
3714         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3715         vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3716         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
3717         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3718
3719         /* VFTA - enable all vlan filters */
3720         for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
3721                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
3722         }
3723
3724         /*
3725          * Configure Rx packet plane (recycle mode; WSP) and
3726          * enable arbiter
3727          */
3728         reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
3729         IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
3730 }
3731
3732 static void
3733 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
3734                         uint16_t *max, uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
3735 {
3736         switch (hw->mac.type) {
3737         case ixgbe_mac_82598EB:
3738                 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
3739                 break;
3740         case ixgbe_mac_82599EB:
3741         case ixgbe_mac_X540:
3742         case ixgbe_mac_X550:
3743         case ixgbe_mac_X550EM_x:
3744         case ixgbe_mac_X550EM_a:
3745                 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
3746                                                   tsa, map);
3747                 break;
3748         default:
3749                 break;
3750         }
3751 }
3752
3753 static void
3754 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
3755                             uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
3756 {
3757         switch (hw->mac.type) {
3758         case ixgbe_mac_82598EB:
3759                 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id, tsa);
3760                 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id, tsa);
3761                 break;
3762         case ixgbe_mac_82599EB:
3763         case ixgbe_mac_X540:
3764         case ixgbe_mac_X550:
3765         case ixgbe_mac_X550EM_x:
3766         case ixgbe_mac_X550EM_a:
3767                 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id, tsa);
3768                 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id, tsa, map);
3769                 break;
3770         default:
3771                 break;
3772         }
3773 }
3774
3775 #define DCB_RX_CONFIG  1
3776 #define DCB_TX_CONFIG  1
3777 #define DCB_TX_PB      1024
3778 /**
3779  * ixgbe_dcb_hw_configure - Enable DCB and configure
3780  * general DCB in VT mode and non-VT mode parameters
3781  * @dev: pointer to rte_eth_dev structure
3782  * @dcb_config: pointer to ixgbe_dcb_config structure
3783  */
3784 static int
3785 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
3786                         struct ixgbe_dcb_config *dcb_config)
3787 {
3788         int     ret = 0;
3789         uint8_t i, pfc_en, nb_tcs;
3790         uint16_t pbsize, rx_buffer_size;
3791         uint8_t config_dcb_rx = 0;
3792         uint8_t config_dcb_tx = 0;
3793         uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3794         uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3795         uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3796         uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3797         uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3798         struct ixgbe_dcb_tc_config *tc;
3799         uint32_t max_frame = dev->data->mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3800         struct ixgbe_hw *hw =
3801                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3802         struct ixgbe_bw_conf *bw_conf =
3803                 IXGBE_DEV_PRIVATE_TO_BW_CONF(dev->data->dev_private);
3804
3805         switch (dev->data->dev_conf.rxmode.mq_mode) {
3806         case ETH_MQ_RX_VMDQ_DCB:
3807                 dcb_config->vt_mode = true;
3808                 if (hw->mac.type != ixgbe_mac_82598EB) {
3809                         config_dcb_rx = DCB_RX_CONFIG;
3810                         /*
3811                          *get dcb and VT rx configuration parameters
3812                          *from rte_eth_conf
3813                          */
3814                         ixgbe_vmdq_dcb_rx_config(dev, dcb_config);
3815                         /*Configure general VMDQ and DCB RX parameters*/
3816                         ixgbe_vmdq_dcb_configure(dev);
3817                 }
3818                 break;
3819         case ETH_MQ_RX_DCB:
3820         case ETH_MQ_RX_DCB_RSS:
3821                 dcb_config->vt_mode = false;
3822                 config_dcb_rx = DCB_RX_CONFIG;
3823                 /* Get dcb TX configuration parameters from rte_eth_conf */
3824                 ixgbe_dcb_rx_config(dev, dcb_config);
3825                 /*Configure general DCB RX parameters*/
3826                 ixgbe_dcb_rx_hw_config(dev, dcb_config);
3827                 break;
3828         default:
3829                 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration");
3830                 break;
3831         }
3832         switch (dev->data->dev_conf.txmode.mq_mode) {
3833         case ETH_MQ_TX_VMDQ_DCB:
3834                 dcb_config->vt_mode = true;
3835                 config_dcb_tx = DCB_TX_CONFIG;
3836                 /* get DCB and VT TX configuration parameters
3837                  * from rte_eth_conf
3838                  */
3839                 ixgbe_dcb_vt_tx_config(dev, dcb_config);
3840                 /*Configure general VMDQ and DCB TX parameters*/
3841                 ixgbe_vmdq_dcb_hw_tx_config(dev, dcb_config);
3842                 break;
3843
3844         case ETH_MQ_TX_DCB:
3845                 dcb_config->vt_mode = false;
3846                 config_dcb_tx = DCB_TX_CONFIG;
3847                 /*get DCB TX configuration parameters from rte_eth_conf*/
3848                 ixgbe_dcb_tx_config(dev, dcb_config);
3849                 /*Configure general DCB TX parameters*/
3850                 ixgbe_dcb_tx_hw_config(dev, dcb_config);
3851                 break;
3852         default:
3853                 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration");
3854                 break;
3855         }
3856
3857         nb_tcs = dcb_config->num_tcs.pfc_tcs;
3858         /* Unpack map */
3859         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3860         if (nb_tcs == ETH_4_TCS) {
3861                 /* Avoid un-configured priority mapping to TC0 */
3862                 uint8_t j = 4;
3863                 uint8_t mask = 0xFF;
3864
3865                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
3866                         mask = (uint8_t)(mask & (~(1 << map[i])));
3867                 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
3868                         if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
3869                                 map[j++] = i;
3870                         mask >>= 1;
3871                 }
3872                 /* Re-configure 4 TCs BW */
3873                 for (i = 0; i < nb_tcs; i++) {
3874                         tc = &dcb_config->tc_config[i];
3875                         if (bw_conf->tc_num != nb_tcs)
3876                                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
3877                                         (uint8_t)(100 / nb_tcs);
3878                         tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
3879                                                 (uint8_t)(100 / nb_tcs);
3880                 }
3881                 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3882                         tc = &dcb_config->tc_config[i];
3883                         tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
3884                         tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
3885                 }
3886         } else {
3887                 /* Re-configure 8 TCs BW */
3888                 for (i = 0; i < nb_tcs; i++) {
3889                         tc = &dcb_config->tc_config[i];
3890                         if (bw_conf->tc_num != nb_tcs)
3891                                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
3892                                         (uint8_t)(100 / nb_tcs + (i & 1));
3893                         tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
3894                                 (uint8_t)(100 / nb_tcs + (i & 1));
3895                 }
3896         }
3897
3898         switch (hw->mac.type) {
3899         case ixgbe_mac_X550:
3900         case ixgbe_mac_X550EM_x:
3901         case ixgbe_mac_X550EM_a:
3902                 rx_buffer_size = X550_RX_BUFFER_SIZE;
3903                 break;
3904         default:
3905                 rx_buffer_size = NIC_RX_BUFFER_SIZE;
3906                 break;
3907         }
3908
3909         if (config_dcb_rx) {
3910                 /* Set RX buffer size */
3911                 pbsize = (uint16_t)(rx_buffer_size / nb_tcs);
3912                 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
3913
3914                 for (i = 0; i < nb_tcs; i++) {
3915                         IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
3916                 }
3917                 /* zero alloc all unused TCs */
3918                 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3919                         IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3920                 }
3921         }
3922         if (config_dcb_tx) {
3923                 /* Only support an equally distributed
3924                  *  Tx packet buffer strategy.
3925                  */
3926                 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
3927                 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
3928
3929                 for (i = 0; i < nb_tcs; i++) {
3930                         IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3931                         IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3932                 }
3933                 /* Clear unused TCs, if any, to zero buffer size*/
3934                 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3935                         IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3936                         IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3937                 }
3938         }
3939
3940         /*Calculates traffic class credits*/
3941         ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config, max_frame,
3942                                 IXGBE_DCB_TX_CONFIG);
3943         ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config, max_frame,
3944                                 IXGBE_DCB_RX_CONFIG);
3945
3946         if (config_dcb_rx) {
3947                 /* Unpack CEE standard containers */
3948                 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
3949                 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3950                 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
3951                 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
3952                 /* Configure PG(ETS) RX */
3953                 ixgbe_dcb_hw_arbite_rx_config(hw, refill, max, bwgid, tsa, map);
3954         }
3955
3956         if (config_dcb_tx) {
3957                 /* Unpack CEE standard containers */
3958                 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
3959                 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3960                 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
3961                 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
3962                 /* Configure PG(ETS) TX */
3963                 ixgbe_dcb_hw_arbite_tx_config(hw, refill, max, bwgid, tsa, map);
3964         }
3965
3966         /*Configure queue statistics registers*/
3967         ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
3968
3969         /* Check if the PFC is supported */
3970         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
3971                 pbsize = (uint16_t)(rx_buffer_size / nb_tcs);
3972                 for (i = 0; i < nb_tcs; i++) {
3973                         /*
3974                         * If the TC count is 8,and the default high_water is 48,
3975                         * the low_water is 16 as default.
3976                         */
3977                         hw->fc.high_water[i] = (pbsize * 3) / 4;
3978                         hw->fc.low_water[i] = pbsize / 4;
3979                         /* Enable pfc for this TC */
3980                         tc = &dcb_config->tc_config[i];
3981                         tc->pfc = ixgbe_dcb_pfc_enabled;
3982                 }
3983                 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
3984                 if (dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
3985                         pfc_en &= 0x0F;
3986                 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
3987         }
3988
3989         return ret;
3990 }
3991
3992 /**
3993  * ixgbe_configure_dcb - Configure DCB  Hardware
3994  * @dev: pointer to rte_eth_dev
3995  */
3996 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
3997 {
3998         struct ixgbe_dcb_config *dcb_cfg =
3999                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4000         struct rte_eth_conf *dev_conf = &(dev->data->dev_conf);
4001
4002         PMD_INIT_FUNC_TRACE();
4003
4004         /* check support mq_mode for DCB */
4005         if ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) &&
4006             (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB) &&
4007             (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB_RSS))
4008                 return;
4009
4010         if (dev->data->nb_rx_queues > ETH_DCB_NUM_QUEUES)
4011                 return;
4012
4013         /** Configure DCB hardware **/
4014         ixgbe_dcb_hw_configure(dev, dcb_cfg);
4015 }
4016
4017 /*
4018  * VMDq only support for 10 GbE NIC.
4019  */
4020 static void
4021 ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
4022 {
4023         struct rte_eth_vmdq_rx_conf *cfg;
4024         struct ixgbe_hw *hw;
4025         enum rte_eth_nb_pools num_pools;
4026         uint32_t mrqc, vt_ctl, vlanctrl;
4027         uint32_t vmolr = 0;
4028         int i;
4029
4030         PMD_INIT_FUNC_TRACE();
4031         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4032         cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
4033         num_pools = cfg->nb_queue_pools;
4034
4035         ixgbe_rss_disable(dev);
4036
4037         /* MRQC: enable vmdq */
4038         mrqc = IXGBE_MRQC_VMDQEN;
4039         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
4040
4041         /* PFVTCTL: turn on virtualisation and set the default pool */
4042         vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
4043         if (cfg->enable_default_pool)
4044                 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
4045         else
4046                 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
4047
4048         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
4049
4050         for (i = 0; i < (int)num_pools; i++) {
4051                 vmolr = ixgbe_convert_vm_rx_mask_to_val(cfg->rx_mode, vmolr);
4052                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(i), vmolr);
4053         }
4054
4055         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
4056         vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4057         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
4058         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
4059
4060         /* VFTA - enable all vlan filters */
4061         for (i = 0; i < NUM_VFTA_REGISTERS; i++)
4062                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), UINT32_MAX);
4063
4064         /* VFRE: pool enabling for receive - 64 */
4065         IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), UINT32_MAX);
4066         if (num_pools == ETH_64_POOLS)
4067                 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), UINT32_MAX);
4068
4069         /*
4070          * MPSAR - allow pools to read specific mac addresses
4071          * In this case, all pools should be able to read from mac addr 0
4072          */
4073         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), UINT32_MAX);
4074         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), UINT32_MAX);
4075
4076         /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
4077         for (i = 0; i < cfg->nb_pool_maps; i++) {
4078                 /* set vlan id in VF register and set the valid bit */
4079                 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN |
4080                                 (cfg->pool_map[i].vlan_id & IXGBE_RXD_VLAN_ID_MASK)));
4081                 /*
4082                  * Put the allowed pools in VFB reg. As we only have 16 or 64
4083                  * pools, we only need to use the first half of the register
4084                  * i.e. bits 0-31
4085                  */
4086                 if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
4087                         IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i * 2),
4088                                         (cfg->pool_map[i].pools & UINT32_MAX));
4089                 else
4090                         IXGBE_WRITE_REG(hw, IXGBE_VLVFB((i * 2 + 1)),
4091                                         ((cfg->pool_map[i].pools >> 32) & UINT32_MAX));
4092
4093         }
4094
4095         /* PFDMA Tx General Switch Control Enables VMDQ loopback */
4096         if (cfg->enable_loop_back) {
4097                 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
4098                 for (i = 0; i < RTE_IXGBE_VMTXSW_REGISTER_COUNT; i++)
4099                         IXGBE_WRITE_REG(hw, IXGBE_VMTXSW(i), UINT32_MAX);
4100         }
4101
4102         IXGBE_WRITE_FLUSH(hw);
4103 }
4104
4105 /*
4106  * ixgbe_dcb_config_tx_hw_config - Configure general VMDq TX parameters
4107  * @hw: pointer to hardware structure
4108  */
4109 static void
4110 ixgbe_vmdq_tx_hw_configure(struct ixgbe_hw *hw)
4111 {
4112         uint32_t reg;
4113         uint32_t q;
4114
4115         PMD_INIT_FUNC_TRACE();
4116         /*PF VF Transmit Enable*/
4117         IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), UINT32_MAX);
4118         IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), UINT32_MAX);
4119
4120         /* Disable the Tx desc arbiter so that MTQC can be changed */
4121         reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
4122         reg |= IXGBE_RTTDCS_ARBDIS;
4123         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
4124
4125         reg = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
4126         IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
4127
4128         /* Disable drop for all queues */
4129         for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
4130                 IXGBE_WRITE_REG(hw, IXGBE_QDE,
4131                   (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
4132
4133         /* Enable the Tx desc arbiter */
4134         reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
4135         reg &= ~IXGBE_RTTDCS_ARBDIS;
4136         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
4137
4138         IXGBE_WRITE_FLUSH(hw);
4139 }
4140
4141 static int __attribute__((cold))
4142 ixgbe_alloc_rx_queue_mbufs(struct ixgbe_rx_queue *rxq)
4143 {
4144         struct ixgbe_rx_entry *rxe = rxq->sw_ring;
4145         uint64_t dma_addr;
4146         unsigned int i;
4147
4148         /* Initialize software ring entries */
4149         for (i = 0; i < rxq->nb_rx_desc; i++) {
4150                 volatile union ixgbe_adv_rx_desc *rxd;
4151                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
4152
4153                 if (mbuf == NULL) {
4154                         PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
4155                                      (unsigned) rxq->queue_id);
4156                         return -ENOMEM;
4157                 }
4158
4159                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
4160                 mbuf->port = rxq->port_id;
4161
4162                 dma_addr =
4163                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
4164                 rxd = &rxq->rx_ring[i];
4165                 rxd->read.hdr_addr = 0;
4166                 rxd->read.pkt_addr = dma_addr;
4167                 rxe[i].mbuf = mbuf;
4168         }
4169
4170         return 0;
4171 }
4172
4173 static int
4174 ixgbe_config_vf_rss(struct rte_eth_dev *dev)
4175 {
4176         struct ixgbe_hw *hw;
4177         uint32_t mrqc;
4178
4179         ixgbe_rss_configure(dev);
4180
4181         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4182
4183         /* MRQC: enable VF RSS */
4184         mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
4185         mrqc &= ~IXGBE_MRQC_MRQE_MASK;
4186         switch (RTE_ETH_DEV_SRIOV(dev).active) {
4187         case ETH_64_POOLS:
4188                 mrqc |= IXGBE_MRQC_VMDQRSS64EN;
4189                 break;
4190
4191         case ETH_32_POOLS:
4192                 mrqc |= IXGBE_MRQC_VMDQRSS32EN;
4193                 break;
4194
4195         default:
4196                 PMD_INIT_LOG(ERR, "Invalid pool number in IOV mode with VMDQ RSS");
4197                 return -EINVAL;
4198         }
4199
4200         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
4201
4202         return 0;
4203 }
4204
4205 static int
4206 ixgbe_config_vf_default(struct rte_eth_dev *dev)
4207 {
4208         struct ixgbe_hw *hw =
4209                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4210
4211         switch (RTE_ETH_DEV_SRIOV(dev).active) {
4212         case ETH_64_POOLS:
4213                 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
4214                         IXGBE_MRQC_VMDQEN);
4215                 break;
4216
4217         case ETH_32_POOLS:
4218                 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
4219                         IXGBE_MRQC_VMDQRT4TCEN);
4220                 break;
4221
4222         case ETH_16_POOLS:
4223                 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
4224                         IXGBE_MRQC_VMDQRT8TCEN);
4225                 break;
4226         default:
4227                 PMD_INIT_LOG(ERR,
4228                         "invalid pool number in IOV mode");
4229                 break;
4230         }
4231         return 0;
4232 }
4233
4234 static int
4235 ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
4236 {
4237         struct ixgbe_hw *hw =
4238                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4239
4240         if (hw->mac.type == ixgbe_mac_82598EB)
4241                 return 0;
4242
4243         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
4244                 /*
4245                  * SRIOV inactive scheme
4246                  * any DCB/RSS w/o VMDq multi-queue setting
4247                  */
4248                 switch (dev->data->dev_conf.rxmode.mq_mode) {
4249                 case ETH_MQ_RX_RSS:
4250                 case ETH_MQ_RX_DCB_RSS:
4251                 case ETH_MQ_RX_VMDQ_RSS:
4252                         ixgbe_rss_configure(dev);
4253                         break;
4254
4255                 case ETH_MQ_RX_VMDQ_DCB:
4256                         ixgbe_vmdq_dcb_configure(dev);
4257                         break;
4258
4259                 case ETH_MQ_RX_VMDQ_ONLY:
4260                         ixgbe_vmdq_rx_hw_configure(dev);
4261                         break;
4262
4263                 case ETH_MQ_RX_NONE:
4264                 default:
4265                         /* if mq_mode is none, disable rss mode.*/
4266                         ixgbe_rss_disable(dev);
4267                         break;
4268                 }
4269         } else {
4270                 /* SRIOV active scheme
4271                  * Support RSS together with SRIOV.
4272                  */
4273                 switch (dev->data->dev_conf.rxmode.mq_mode) {
4274                 case ETH_MQ_RX_RSS:
4275                 case ETH_MQ_RX_VMDQ_RSS:
4276                         ixgbe_config_vf_rss(dev);
4277                         break;
4278                 case ETH_MQ_RX_VMDQ_DCB:
4279                 case ETH_MQ_RX_DCB:
4280                 /* In SRIOV, the configuration is the same as VMDq case */
4281                         ixgbe_vmdq_dcb_configure(dev);
4282                         break;
4283                 /* DCB/RSS together with SRIOV is not supported */
4284                 case ETH_MQ_RX_VMDQ_DCB_RSS:
4285                 case ETH_MQ_RX_DCB_RSS:
4286                         PMD_INIT_LOG(ERR,
4287                                 "Could not support DCB/RSS with VMDq & SRIOV");
4288                         return -1;
4289                 default:
4290                         ixgbe_config_vf_default(dev);
4291                         break;
4292                 }
4293         }
4294
4295         return 0;
4296 }
4297
4298 static int
4299 ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)
4300 {
4301         struct ixgbe_hw *hw =
4302                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4303         uint32_t mtqc;
4304         uint32_t rttdcs;
4305
4306         if (hw->mac.type == ixgbe_mac_82598EB)
4307                 return 0;
4308
4309         /* disable arbiter before setting MTQC */
4310         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
4311         rttdcs |= IXGBE_RTTDCS_ARBDIS;
4312         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
4313
4314         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
4315                 /*
4316                  * SRIOV inactive scheme
4317                  * any DCB w/o VMDq multi-queue setting
4318                  */
4319                 if (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)
4320                         ixgbe_vmdq_tx_hw_configure(hw);
4321                 else {
4322                         mtqc = IXGBE_MTQC_64Q_1PB;
4323                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
4324                 }
4325         } else {
4326                 switch (RTE_ETH_DEV_SRIOV(dev).active) {
4327
4328                 /*
4329                  * SRIOV active scheme
4330                  * FIXME if support DCB together with VMDq & SRIOV
4331                  */
4332                 case ETH_64_POOLS:
4333                         mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
4334                         break;
4335                 case ETH_32_POOLS:
4336                         mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;
4337                         break;
4338                 case ETH_16_POOLS:
4339                         mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |
4340                                 IXGBE_MTQC_8TC_8TQ;
4341                         break;
4342                 default:
4343                         mtqc = IXGBE_MTQC_64Q_1PB;
4344                         PMD_INIT_LOG(ERR, "invalid pool number in IOV mode");
4345                 }
4346                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
4347         }
4348
4349         /* re-enable arbiter */
4350         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
4351         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
4352
4353         return 0;
4354 }
4355
4356 /**
4357  * ixgbe_get_rscctl_maxdesc - Calculate the RSCCTL[n].MAXDESC for PF
4358  *
4359  * Return the RSCCTL[n].MAXDESC for 82599 and x540 PF devices according to the
4360  * spec rev. 3.0 chapter 8.2.3.8.13.
4361  *
4362  * @pool Memory pool of the Rx queue
4363  */
4364 static inline uint32_t
4365 ixgbe_get_rscctl_maxdesc(struct rte_mempool *pool)
4366 {
4367         struct rte_pktmbuf_pool_private *mp_priv = rte_mempool_get_priv(pool);
4368
4369         /* MAXDESC * SRRCTL.BSIZEPKT must not exceed 64 KB minus one */
4370         uint16_t maxdesc =
4371                 IPV4_MAX_PKT_LEN /
4372                         (mp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM);
4373
4374         if (maxdesc >= 16)
4375                 return IXGBE_RSCCTL_MAXDESC_16;
4376         else if (maxdesc >= 8)
4377                 return IXGBE_RSCCTL_MAXDESC_8;
4378         else if (maxdesc >= 4)
4379                 return IXGBE_RSCCTL_MAXDESC_4;
4380         else
4381                 return IXGBE_RSCCTL_MAXDESC_1;
4382 }
4383
4384 /**
4385  * ixgbe_set_ivar - Setup the correct IVAR register for a particular MSIX
4386  * interrupt
4387  *
4388  * (Taken from FreeBSD tree)
4389  * (yes this is all very magic and confusing :)
4390  *
4391  * @dev port handle
4392  * @entry the register array entry
4393  * @vector the MSIX vector for this queue
4394  * @type RX/TX/MISC
4395  */
4396 static void
4397 ixgbe_set_ivar(struct rte_eth_dev *dev, u8 entry, u8 vector, s8 type)
4398 {
4399         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4400         u32 ivar, index;
4401
4402         vector |= IXGBE_IVAR_ALLOC_VAL;
4403
4404         switch (hw->mac.type) {
4405
4406         case ixgbe_mac_82598EB:
4407                 if (type == -1)
4408                         entry = IXGBE_IVAR_OTHER_CAUSES_INDEX;
4409                 else
4410                         entry += (type * 64);
4411                 index = (entry >> 2) & 0x1F;
4412                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
4413                 ivar &= ~(0xFF << (8 * (entry & 0x3)));
4414                 ivar |= (vector << (8 * (entry & 0x3)));
4415                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
4416                 break;
4417
4418         case ixgbe_mac_82599EB:
4419         case ixgbe_mac_X540:
4420                 if (type == -1) { /* MISC IVAR */
4421                         index = (entry & 1) * 8;
4422                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4423                         ivar &= ~(0xFF << index);
4424                         ivar |= (vector << index);
4425                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, ivar);
4426                 } else {        /* RX/TX IVARS */
4427                         index = (16 * (entry & 1)) + (8 * type);
4428                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(entry >> 1));
4429                         ivar &= ~(0xFF << index);
4430                         ivar |= (vector << index);
4431                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(entry >> 1), ivar);
4432                 }
4433
4434                 break;
4435
4436         default:
4437                 break;
4438         }
4439 }
4440
4441 void __attribute__((cold))
4442 ixgbe_set_rx_function(struct rte_eth_dev *dev)
4443 {
4444         uint16_t i, rx_using_sse;
4445         struct ixgbe_adapter *adapter =
4446                 (struct ixgbe_adapter *)dev->data->dev_private;
4447
4448         /*
4449          * In order to allow Vector Rx there are a few configuration
4450          * conditions to be met and Rx Bulk Allocation should be allowed.
4451          */
4452         if (ixgbe_rx_vec_dev_conf_condition_check(dev) ||
4453             !adapter->rx_bulk_alloc_allowed) {
4454                 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet Vector Rx "
4455                                     "preconditions or RTE_IXGBE_INC_VECTOR is "
4456                                     "not enabled",
4457                              dev->data->port_id);
4458
4459                 adapter->rx_vec_allowed = false;
4460         }
4461
4462         /*
4463          * Initialize the appropriate LRO callback.
4464          *
4465          * If all queues satisfy the bulk allocation preconditions
4466          * (hw->rx_bulk_alloc_allowed is TRUE) then we may use bulk allocation.
4467          * Otherwise use a single allocation version.
4468          */
4469         if (dev->data->lro) {
4470                 if (adapter->rx_bulk_alloc_allowed) {
4471                         PMD_INIT_LOG(DEBUG, "LRO is requested. Using a bulk "
4472                                            "allocation version");
4473                         dev->rx_pkt_burst = ixgbe_recv_pkts_lro_bulk_alloc;
4474                 } else {
4475                         PMD_INIT_LOG(DEBUG, "LRO is requested. Using a single "
4476                                            "allocation version");
4477                         dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
4478                 }
4479         } else if (dev->data->scattered_rx) {
4480                 /*
4481                  * Set the non-LRO scattered callback: there are Vector and
4482                  * single allocation versions.
4483                  */
4484                 if (adapter->rx_vec_allowed) {
4485                         PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
4486                                             "callback (port=%d).",
4487                                      dev->data->port_id);
4488
4489                         dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
4490                 } else if (adapter->rx_bulk_alloc_allowed) {
4491                         PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
4492                                            "allocation callback (port=%d).",
4493                                      dev->data->port_id);
4494                         dev->rx_pkt_burst = ixgbe_recv_pkts_lro_bulk_alloc;
4495                 } else {
4496                         PMD_INIT_LOG(DEBUG, "Using Regualr (non-vector, "
4497                                             "single allocation) "
4498                                             "Scattered Rx callback "
4499                                             "(port=%d).",
4500                                      dev->data->port_id);
4501
4502                         dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
4503                 }
4504         /*
4505          * Below we set "simple" callbacks according to port/queues parameters.
4506          * If parameters allow we are going to choose between the following
4507          * callbacks:
4508          *    - Vector
4509          *    - Bulk Allocation
4510          *    - Single buffer allocation (the simplest one)
4511          */
4512         } else if (adapter->rx_vec_allowed) {
4513                 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
4514                                     "burst size no less than %d (port=%d).",
4515                              RTE_IXGBE_DESCS_PER_LOOP,
4516                              dev->data->port_id);
4517
4518                 dev->rx_pkt_burst = ixgbe_recv_pkts_vec;
4519         } else if (adapter->rx_bulk_alloc_allowed) {
4520                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
4521                                     "satisfied. Rx Burst Bulk Alloc function "
4522                                     "will be used on port=%d.",
4523                              dev->data->port_id);
4524
4525                 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
4526         } else {
4527                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
4528                                     "satisfied, or Scattered Rx is requested "
4529                                     "(port=%d).",
4530                              dev->data->port_id);
4531
4532                 dev->rx_pkt_burst = ixgbe_recv_pkts;
4533         }
4534
4535         /* Propagate information about RX function choice through all queues. */
4536
4537         rx_using_sse =
4538                 (dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec ||
4539                 dev->rx_pkt_burst == ixgbe_recv_pkts_vec);
4540
4541         for (i = 0; i < dev->data->nb_rx_queues; i++) {
4542                 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
4543
4544                 rxq->rx_using_sse = rx_using_sse;
4545 #ifdef RTE_LIBRTE_SECURITY
4546                 rxq->using_ipsec = !!(dev->data->dev_conf.rxmode.offloads &
4547                                 DEV_RX_OFFLOAD_SECURITY);
4548 #endif
4549         }
4550 }
4551
4552 /**
4553  * ixgbe_set_rsc - configure RSC related port HW registers
4554  *
4555  * Configures the port's RSC related registers according to the 4.6.7.2 chapter
4556  * of 82599 Spec (x540 configuration is virtually the same).
4557  *
4558  * @dev port handle
4559  *
4560  * Returns 0 in case of success or a non-zero error code
4561  */
4562 static int
4563 ixgbe_set_rsc(struct rte_eth_dev *dev)
4564 {
4565         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
4566         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4567         struct rte_eth_dev_info dev_info = { 0 };
4568         bool rsc_capable = false;
4569         uint16_t i;
4570         uint32_t rdrxctl;
4571         uint32_t rfctl;
4572
4573         /* Sanity check */
4574         dev->dev_ops->dev_infos_get(dev, &dev_info);
4575         if (dev_info.rx_offload_capa & DEV_RX_OFFLOAD_TCP_LRO)
4576                 rsc_capable = true;
4577
4578         if (!rsc_capable && rx_conf->enable_lro) {
4579                 PMD_INIT_LOG(CRIT, "LRO is requested on HW that doesn't "
4580                                    "support it");
4581                 return -EINVAL;
4582         }
4583
4584         /* RSC global configuration (chapter 4.6.7.2.1 of 82599 Spec) */
4585
4586         if (!rx_conf->hw_strip_crc && rx_conf->enable_lro) {
4587                 /*
4588                  * According to chapter of 4.6.7.2.1 of the Spec Rev.
4589                  * 3.0 RSC configuration requires HW CRC stripping being
4590                  * enabled. If user requested both HW CRC stripping off
4591                  * and RSC on - return an error.
4592                  */
4593                 PMD_INIT_LOG(CRIT, "LRO can't be enabled when HW CRC "
4594                                     "is disabled");
4595                 return -EINVAL;
4596         }
4597
4598         /* RFCTL configuration  */
4599         rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
4600         if ((rsc_capable) && (rx_conf->enable_lro))
4601                 /*
4602                  * Since NFS packets coalescing is not supported - clear
4603                  * RFCTL.NFSW_DIS and RFCTL.NFSR_DIS when RSC is
4604                  * enabled.
4605                  */
4606                 rfctl &= ~(IXGBE_RFCTL_RSC_DIS | IXGBE_RFCTL_NFSW_DIS |
4607                            IXGBE_RFCTL_NFSR_DIS);
4608         else
4609                 rfctl |= IXGBE_RFCTL_RSC_DIS;
4610         IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
4611
4612         /* If LRO hasn't been requested - we are done here. */
4613         if (!rx_conf->enable_lro)
4614                 return 0;
4615
4616         /* Set RDRXCTL.RSCACKC bit */
4617         rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4618         rdrxctl |= IXGBE_RDRXCTL_RSCACKC;
4619         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4620
4621         /* Per-queue RSC configuration (chapter 4.6.7.2.2 of 82599 Spec) */
4622         for (i = 0; i < dev->data->nb_rx_queues; i++) {
4623                 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
4624                 uint32_t srrctl =
4625                         IXGBE_READ_REG(hw, IXGBE_SRRCTL(rxq->reg_idx));
4626                 uint32_t rscctl =
4627                         IXGBE_READ_REG(hw, IXGBE_RSCCTL(rxq->reg_idx));
4628                 uint32_t psrtype =
4629                         IXGBE_READ_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx));
4630                 uint32_t eitr =
4631                         IXGBE_READ_REG(hw, IXGBE_EITR(rxq->reg_idx));
4632
4633                 /*
4634                  * ixgbe PMD doesn't support header-split at the moment.
4635                  *
4636                  * Following the 4.6.7.2.1 chapter of the 82599/x540
4637                  * Spec if RSC is enabled the SRRCTL[n].BSIZEHEADER
4638                  * should be configured even if header split is not
4639                  * enabled. We will configure it 128 bytes following the
4640                  * recommendation in the spec.
4641                  */
4642                 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
4643                 srrctl |= (128 << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4644                                             IXGBE_SRRCTL_BSIZEHDR_MASK;
4645
4646                 /*
4647                  * TODO: Consider setting the Receive Descriptor Minimum
4648                  * Threshold Size for an RSC case. This is not an obviously
4649                  * beneficiary option but the one worth considering...
4650                  */
4651
4652                 rscctl |= IXGBE_RSCCTL_RSCEN;
4653                 rscctl |= ixgbe_get_rscctl_maxdesc(rxq->mb_pool);
4654                 psrtype |= IXGBE_PSRTYPE_TCPHDR;
4655
4656                 /*
4657                  * RSC: Set ITR interval corresponding to 2K ints/s.
4658                  *
4659                  * Full-sized RSC aggregations for a 10Gb/s link will
4660                  * arrive at about 20K aggregation/s rate.
4661                  *
4662                  * 2K inst/s rate will make only 10% of the
4663                  * aggregations to be closed due to the interrupt timer
4664                  * expiration for a streaming at wire-speed case.
4665                  *
4666                  * For a sparse streaming case this setting will yield
4667                  * at most 500us latency for a single RSC aggregation.
4668                  */
4669                 eitr &= ~IXGBE_EITR_ITR_INT_MASK;
4670                 eitr |= IXGBE_EITR_INTERVAL_US(500) | IXGBE_EITR_CNT_WDIS;
4671
4672                 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
4673                 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(rxq->reg_idx), rscctl);
4674                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
4675                 IXGBE_WRITE_REG(hw, IXGBE_EITR(rxq->reg_idx), eitr);
4676
4677                 /*
4678                  * RSC requires the mapping of the queue to the
4679                  * interrupt vector.
4680                  */
4681                 ixgbe_set_ivar(dev, rxq->reg_idx, i, 0);
4682         }
4683
4684         dev->data->lro = 1;
4685
4686         PMD_INIT_LOG(DEBUG, "enabling LRO mode");
4687
4688         return 0;
4689 }
4690
4691 /*
4692  * Initializes Receive Unit.
4693  */
4694 int __attribute__((cold))
4695 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
4696 {
4697         struct ixgbe_hw     *hw;
4698         struct ixgbe_rx_queue *rxq;
4699         uint64_t bus_addr;
4700         uint32_t rxctrl;
4701         uint32_t fctrl;
4702         uint32_t hlreg0;
4703         uint32_t maxfrs;
4704         uint32_t srrctl;
4705         uint32_t rdrxctl;
4706         uint32_t rxcsum;
4707         uint16_t buf_size;
4708         uint16_t i;
4709         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
4710         int rc;
4711
4712         PMD_INIT_FUNC_TRACE();
4713         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4714
4715         /*
4716          * Make sure receives are disabled while setting
4717          * up the RX context (registers, descriptor rings, etc.).
4718          */
4719         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4720         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4721
4722         /* Enable receipt of broadcasted frames */
4723         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4724         fctrl |= IXGBE_FCTRL_BAM;
4725         fctrl |= IXGBE_FCTRL_DPF;
4726         fctrl |= IXGBE_FCTRL_PMCF;
4727         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4728
4729         /*
4730          * Configure CRC stripping, if any.
4731          */
4732         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4733         if (rx_conf->hw_strip_crc)
4734                 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
4735         else
4736                 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
4737
4738         /*
4739          * Configure jumbo frame support, if any.
4740          */
4741         if (rx_conf->jumbo_frame == 1) {
4742                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4743                 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4744                 maxfrs &= 0x0000FFFF;
4745                 maxfrs |= (rx_conf->max_rx_pkt_len << 16);
4746                 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4747         } else
4748                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4749
4750         /*
4751          * If loopback mode is configured for 82599, set LPBK bit.
4752          */
4753         if (hw->mac.type == ixgbe_mac_82599EB &&
4754                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
4755                 hlreg0 |= IXGBE_HLREG0_LPBK;
4756         else
4757                 hlreg0 &= ~IXGBE_HLREG0_LPBK;
4758
4759         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4760
4761         /* Setup RX queues */
4762         for (i = 0; i < dev->data->nb_rx_queues; i++) {
4763                 rxq = dev->data->rx_queues[i];
4764
4765                 /*
4766                  * Reset crc_len in case it was changed after queue setup by a
4767                  * call to configure.
4768                  */
4769                 rxq->crc_len = rx_conf->hw_strip_crc ? 0 : ETHER_CRC_LEN;
4770
4771                 /* Setup the Base and Length of the Rx Descriptor Rings */
4772                 bus_addr = rxq->rx_ring_phys_addr;
4773                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),
4774                                 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4775                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),
4776                                 (uint32_t)(bus_addr >> 32));
4777                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),
4778                                 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
4779                 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
4780                 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);
4781
4782                 /* Configure the SRRCTL register */
4783 #ifdef RTE_HEADER_SPLIT_ENABLE
4784                 /*
4785                  * Configure Header Split
4786                  */
4787                 if (rx_conf->header_split) {
4788                         if (hw->mac.type == ixgbe_mac_82599EB) {
4789                                 /* Must setup the PSRTYPE register */
4790                                 uint32_t psrtype;
4791
4792                                 psrtype = IXGBE_PSRTYPE_TCPHDR |
4793                                         IXGBE_PSRTYPE_UDPHDR   |
4794                                         IXGBE_PSRTYPE_IPV4HDR  |
4795                                         IXGBE_PSRTYPE_IPV6HDR;
4796                                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
4797                         }
4798                         srrctl = ((rx_conf->split_hdr_size <<
4799                                 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4800                                 IXGBE_SRRCTL_BSIZEHDR_MASK);
4801                         srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
4802                 } else
4803 #endif
4804                         srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
4805
4806                 /* Set if packets are dropped when no descriptors available */
4807                 if (rxq->drop_en)
4808                         srrctl |= IXGBE_SRRCTL_DROP_EN;
4809
4810                 /*
4811                  * Configure the RX buffer size in the BSIZEPACKET field of
4812                  * the SRRCTL register of the queue.
4813                  * The value is in 1 KB resolution. Valid values can be from
4814                  * 1 KB to 16 KB.
4815                  */
4816                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
4817                         RTE_PKTMBUF_HEADROOM);
4818                 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
4819                            IXGBE_SRRCTL_BSIZEPKT_MASK);
4820
4821                 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
4822
4823                 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
4824                                        IXGBE_SRRCTL_BSIZEPKT_SHIFT);
4825
4826                 /* It adds dual VLAN length for supporting dual VLAN */
4827                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len +
4828                                             2 * IXGBE_VLAN_TAG_SIZE > buf_size)
4829                         dev->data->scattered_rx = 1;
4830         }
4831
4832         if (rx_conf->enable_scatter)
4833                 dev->data->scattered_rx = 1;
4834
4835         /*
4836          * Device configured with multiple RX queues.
4837          */
4838         ixgbe_dev_mq_rx_configure(dev);
4839
4840         /*
4841          * Setup the Checksum Register.
4842          * Disable Full-Packet Checksum which is mutually exclusive with RSS.
4843          * Enable IP/L4 checkum computation by hardware if requested to do so.
4844          */
4845         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
4846         rxcsum |= IXGBE_RXCSUM_PCSD;
4847         if (rx_conf->hw_ip_checksum)
4848                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
4849         else
4850                 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
4851
4852         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
4853
4854         if (hw->mac.type == ixgbe_mac_82599EB ||
4855             hw->mac.type == ixgbe_mac_X540) {
4856                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4857                 if (rx_conf->hw_strip_crc)
4858                         rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
4859                 else
4860                         rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
4861                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
4862                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4863         }
4864
4865         rc = ixgbe_set_rsc(dev);
4866         if (rc)
4867                 return rc;
4868
4869         ixgbe_set_rx_function(dev);
4870
4871         return 0;
4872 }
4873
4874 /*
4875  * Initializes Transmit Unit.
4876  */
4877 void __attribute__((cold))
4878 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
4879 {
4880         struct ixgbe_hw     *hw;
4881         struct ixgbe_tx_queue *txq;
4882         uint64_t bus_addr;
4883         uint32_t hlreg0;
4884         uint32_t txctrl;
4885         uint16_t i;
4886
4887         PMD_INIT_FUNC_TRACE();
4888         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4889
4890         /* Enable TX CRC (checksum offload requirement) and hw padding
4891          * (TSO requirement)
4892          */
4893         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4894         hlreg0 |= (IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_TXPADEN);
4895         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4896
4897         /* Setup the Base and Length of the Tx Descriptor Rings */
4898         for (i = 0; i < dev->data->nb_tx_queues; i++) {
4899                 txq = dev->data->tx_queues[i];
4900
4901                 bus_addr = txq->tx_ring_phys_addr;
4902                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),
4903                                 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4904                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),
4905                                 (uint32_t)(bus_addr >> 32));
4906                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),
4907                                 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
4908                 /* Setup the HW Tx Head and TX Tail descriptor pointers */
4909                 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
4910                 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
4911
4912                 /*
4913                  * Disable Tx Head Writeback RO bit, since this hoses
4914                  * bookkeeping if things aren't delivered in order.
4915                  */
4916                 switch (hw->mac.type) {
4917                 case ixgbe_mac_82598EB:
4918                         txctrl = IXGBE_READ_REG(hw,
4919                                                 IXGBE_DCA_TXCTRL(txq->reg_idx));
4920                         txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4921                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),
4922                                         txctrl);
4923                         break;
4924
4925                 case ixgbe_mac_82599EB:
4926                 case ixgbe_mac_X540:
4927                 case ixgbe_mac_X550:
4928                 case ixgbe_mac_X550EM_x:
4929                 case ixgbe_mac_X550EM_a:
4930                 default:
4931                         txctrl = IXGBE_READ_REG(hw,
4932                                                 IXGBE_DCA_TXCTRL_82599(txq->reg_idx));
4933                         txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4934                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),
4935                                         txctrl);
4936                         break;
4937                 }
4938         }
4939
4940         /* Device configured with multiple TX queues. */
4941         ixgbe_dev_mq_tx_configure(dev);
4942 }
4943
4944 /*
4945  * Set up link for 82599 loopback mode Tx->Rx.
4946  */
4947 static inline void __attribute__((cold))
4948 ixgbe_setup_loopback_link_82599(struct ixgbe_hw *hw)
4949 {
4950         PMD_INIT_FUNC_TRACE();
4951
4952         if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
4953                 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM) !=
4954                                 IXGBE_SUCCESS) {
4955                         PMD_INIT_LOG(ERR, "Could not enable loopback mode");
4956                         /* ignore error */
4957                         return;
4958                 }
4959         }
4960
4961         /* Restart link */
4962         IXGBE_WRITE_REG(hw,
4963                         IXGBE_AUTOC,
4964                         IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU);
4965         ixgbe_reset_pipeline_82599(hw);
4966
4967         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
4968         msec_delay(50);
4969 }
4970
4971
4972 /*
4973  * Start Transmit and Receive Units.
4974  */
4975 int __attribute__((cold))
4976 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
4977 {
4978         struct ixgbe_hw     *hw;
4979         struct ixgbe_tx_queue *txq;
4980         struct ixgbe_rx_queue *rxq;
4981         uint32_t txdctl;
4982         uint32_t dmatxctl;
4983         uint32_t rxctrl;
4984         uint16_t i;
4985         int ret = 0;
4986
4987         PMD_INIT_FUNC_TRACE();
4988         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4989
4990         for (i = 0; i < dev->data->nb_tx_queues; i++) {
4991                 txq = dev->data->tx_queues[i];
4992                 /* Setup Transmit Threshold Registers */
4993                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
4994                 txdctl |= txq->pthresh & 0x7F;
4995                 txdctl |= ((txq->hthresh & 0x7F) << 8);
4996                 txdctl |= ((txq->wthresh & 0x7F) << 16);
4997                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
4998         }
4999
5000         if (hw->mac.type != ixgbe_mac_82598EB) {
5001                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
5002                 dmatxctl |= IXGBE_DMATXCTL_TE;
5003                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
5004         }
5005
5006         for (i = 0; i < dev->data->nb_tx_queues; i++) {
5007                 txq = dev->data->tx_queues[i];
5008                 if (!txq->tx_deferred_start) {
5009                         ret = ixgbe_dev_tx_queue_start(dev, i);
5010                         if (ret < 0)
5011                                 return ret;
5012                 }
5013         }
5014
5015         for (i = 0; i < dev->data->nb_rx_queues; i++) {
5016                 rxq = dev->data->rx_queues[i];
5017                 if (!rxq->rx_deferred_start) {
5018                         ret = ixgbe_dev_rx_queue_start(dev, i);
5019                         if (ret < 0)
5020                                 return ret;
5021                 }
5022         }
5023
5024         /* Enable Receive engine */
5025         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5026         if (hw->mac.type == ixgbe_mac_82598EB)
5027                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
5028         rxctrl |= IXGBE_RXCTRL_RXEN;
5029         hw->mac.ops.enable_rx_dma(hw, rxctrl);
5030
5031         /* If loopback mode is enabled for 82599, set up the link accordingly */
5032         if (hw->mac.type == ixgbe_mac_82599EB &&
5033                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
5034                 ixgbe_setup_loopback_link_82599(hw);
5035
5036 #ifdef RTE_LIBRTE_SECURITY
5037         if ((dev->data->dev_conf.rxmode.offloads &
5038                         DEV_RX_OFFLOAD_SECURITY) ||
5039                 (dev->data->dev_conf.txmode.offloads &
5040                         DEV_TX_OFFLOAD_SECURITY)) {
5041                 ret = ixgbe_crypto_enable_ipsec(dev);
5042                 if (ret != 0) {
5043                         PMD_DRV_LOG(ERR,
5044                                     "ixgbe_crypto_enable_ipsec fails with %d.",
5045                                     ret);
5046                         return ret;
5047                 }
5048         }
5049 #endif
5050
5051         return 0;
5052 }
5053
5054 /*
5055  * Start Receive Units for specified queue.
5056  */
5057 int __attribute__((cold))
5058 ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
5059 {
5060         struct ixgbe_hw     *hw;
5061         struct ixgbe_rx_queue *rxq;
5062         uint32_t rxdctl;
5063         int poll_ms;
5064
5065         PMD_INIT_FUNC_TRACE();
5066         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5067
5068         if (rx_queue_id < dev->data->nb_rx_queues) {
5069                 rxq = dev->data->rx_queues[rx_queue_id];
5070
5071                 /* Allocate buffers for descriptor rings */
5072                 if (ixgbe_alloc_rx_queue_mbufs(rxq) != 0) {
5073                         PMD_INIT_LOG(ERR, "Could not alloc mbuf for queue:%d",
5074                                      rx_queue_id);
5075                         return -1;
5076                 }
5077                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
5078                 rxdctl |= IXGBE_RXDCTL_ENABLE;
5079                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
5080
5081                 /* Wait until RX Enable ready */
5082                 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
5083                 do {
5084                         rte_delay_ms(1);
5085                         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
5086                 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
5087                 if (!poll_ms)
5088                         PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d",
5089                                      rx_queue_id);
5090                 rte_wmb();
5091                 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
5092                 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
5093                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
5094         } else
5095                 return -1;
5096
5097         return 0;
5098 }
5099
5100 /*
5101  * Stop Receive Units for specified queue.
5102  */
5103 int __attribute__((cold))
5104 ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
5105 {
5106         struct ixgbe_hw     *hw;
5107         struct ixgbe_adapter *adapter =
5108                 (struct ixgbe_adapter *)dev->data->dev_private;
5109         struct ixgbe_rx_queue *rxq;
5110         uint32_t rxdctl;
5111         int poll_ms;
5112
5113         PMD_INIT_FUNC_TRACE();
5114         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5115
5116         if (rx_queue_id < dev->data->nb_rx_queues) {
5117                 rxq = dev->data->rx_queues[rx_queue_id];
5118
5119                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
5120                 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
5121                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
5122
5123                 /* Wait until RX Enable bit clear */
5124                 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
5125                 do {
5126                         rte_delay_ms(1);
5127                         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
5128                 } while (--poll_ms && (rxdctl & IXGBE_RXDCTL_ENABLE));
5129                 if (!poll_ms)
5130                         PMD_INIT_LOG(ERR, "Could not disable Rx Queue %d",
5131                                      rx_queue_id);
5132
5133                 rte_delay_us(RTE_IXGBE_WAIT_100_US);
5134
5135                 ixgbe_rx_queue_release_mbufs(rxq);
5136                 ixgbe_reset_rx_queue(adapter, rxq);
5137                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
5138         } else
5139                 return -1;
5140
5141         return 0;
5142 }
5143
5144
5145 /*
5146  * Start Transmit Units for specified queue.
5147  */
5148 int __attribute__((cold))
5149 ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
5150 {
5151         struct ixgbe_hw     *hw;
5152         struct ixgbe_tx_queue *txq;
5153         uint32_t txdctl;
5154         int poll_ms;
5155
5156         PMD_INIT_FUNC_TRACE();
5157         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5158
5159         if (tx_queue_id < dev->data->nb_tx_queues) {
5160                 txq = dev->data->tx_queues[tx_queue_id];
5161                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
5162                 txdctl |= IXGBE_TXDCTL_ENABLE;
5163                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
5164
5165                 /* Wait until TX Enable ready */
5166                 if (hw->mac.type == ixgbe_mac_82599EB) {
5167                         poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
5168                         do {
5169                                 rte_delay_ms(1);
5170                                 txdctl = IXGBE_READ_REG(hw,
5171                                         IXGBE_TXDCTL(txq->reg_idx));
5172                         } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
5173                         if (!poll_ms)
5174                                 PMD_INIT_LOG(ERR, "Could not enable "
5175                                              "Tx Queue %d", tx_queue_id);
5176                 }
5177                 rte_wmb();
5178                 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
5179                 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
5180                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
5181         } else
5182                 return -1;
5183
5184         return 0;
5185 }
5186
5187 /*
5188  * Stop Transmit Units for specified queue.
5189  */
5190 int __attribute__((cold))
5191 ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
5192 {
5193         struct ixgbe_hw     *hw;
5194         struct ixgbe_tx_queue *txq;
5195         uint32_t txdctl;
5196         uint32_t txtdh, txtdt;
5197         int poll_ms;
5198
5199         PMD_INIT_FUNC_TRACE();
5200         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5201
5202         if (tx_queue_id >= dev->data->nb_tx_queues)
5203                 return -1;
5204
5205         txq = dev->data->tx_queues[tx_queue_id];
5206
5207         /* Wait until TX queue is empty */
5208         if (hw->mac.type == ixgbe_mac_82599EB) {
5209                 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
5210                 do {
5211                         rte_delay_us(RTE_IXGBE_WAIT_100_US);
5212                         txtdh = IXGBE_READ_REG(hw,
5213                                                IXGBE_TDH(txq->reg_idx));
5214                         txtdt = IXGBE_READ_REG(hw,
5215                                                IXGBE_TDT(txq->reg_idx));
5216                 } while (--poll_ms && (txtdh != txtdt));
5217                 if (!poll_ms)
5218                         PMD_INIT_LOG(ERR, "Tx Queue %d is not empty "
5219                                      "when stopping.", tx_queue_id);
5220         }
5221
5222         txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
5223         txdctl &= ~IXGBE_TXDCTL_ENABLE;
5224         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
5225
5226         /* Wait until TX Enable bit clear */
5227         if (hw->mac.type == ixgbe_mac_82599EB) {
5228                 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
5229                 do {
5230                         rte_delay_ms(1);
5231                         txdctl = IXGBE_READ_REG(hw,
5232                                                 IXGBE_TXDCTL(txq->reg_idx));
5233                 } while (--poll_ms && (txdctl & IXGBE_TXDCTL_ENABLE));
5234                 if (!poll_ms)
5235                         PMD_INIT_LOG(ERR, "Could not disable "
5236                                      "Tx Queue %d", tx_queue_id);
5237         }
5238
5239         if (txq->ops != NULL) {
5240                 txq->ops->release_mbufs(txq);
5241                 txq->ops->reset(txq);
5242         }
5243         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
5244
5245         return 0;
5246 }
5247
5248 void
5249 ixgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
5250         struct rte_eth_rxq_info *qinfo)
5251 {
5252         struct ixgbe_rx_queue *rxq;
5253
5254         rxq = dev->data->rx_queues[queue_id];
5255
5256         qinfo->mp = rxq->mb_pool;
5257         qinfo->scattered_rx = dev->data->scattered_rx;
5258         qinfo->nb_desc = rxq->nb_rx_desc;
5259
5260         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
5261         qinfo->conf.rx_drop_en = rxq->drop_en;
5262         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
5263 }
5264
5265 void
5266 ixgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
5267         struct rte_eth_txq_info *qinfo)
5268 {
5269         struct ixgbe_tx_queue *txq;
5270
5271         txq = dev->data->tx_queues[queue_id];
5272
5273         qinfo->nb_desc = txq->nb_tx_desc;
5274
5275         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
5276         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
5277         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
5278
5279         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
5280         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
5281         qinfo->conf.txq_flags = txq->txq_flags;
5282         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
5283 }
5284
5285 /*
5286  * [VF] Initializes Receive Unit.
5287  */
5288 int __attribute__((cold))
5289 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
5290 {
5291         struct ixgbe_hw     *hw;
5292         struct ixgbe_rx_queue *rxq;
5293         uint64_t bus_addr;
5294         uint32_t srrctl, psrtype = 0;
5295         uint16_t buf_size;
5296         uint16_t i;
5297         int ret;
5298
5299         PMD_INIT_FUNC_TRACE();
5300         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5301
5302         if (rte_is_power_of_2(dev->data->nb_rx_queues) == 0) {
5303                 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
5304                         "it should be power of 2");
5305                 return -1;
5306         }
5307
5308         if (dev->data->nb_rx_queues > hw->mac.max_rx_queues) {
5309                 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
5310                         "it should be equal to or less than %d",
5311                         hw->mac.max_rx_queues);
5312                 return -1;
5313         }
5314
5315         /*
5316          * When the VF driver issues a IXGBE_VF_RESET request, the PF driver
5317          * disables the VF receipt of packets if the PF MTU is > 1500.
5318          * This is done to deal with 82599 limitations that imposes
5319          * the PF and all VFs to share the same MTU.
5320          * Then, the PF driver enables again the VF receipt of packet when
5321          * the VF driver issues a IXGBE_VF_SET_LPE request.
5322          * In the meantime, the VF device cannot be used, even if the VF driver
5323          * and the Guest VM network stack are ready to accept packets with a
5324          * size up to the PF MTU.
5325          * As a work-around to this PF behaviour, force the call to
5326          * ixgbevf_rlpml_set_vf even if jumbo frames are not used. This way,
5327          * VF packets received can work in all cases.
5328          */
5329         ixgbevf_rlpml_set_vf(hw,
5330                 (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len);
5331
5332         /* Setup RX queues */
5333         for (i = 0; i < dev->data->nb_rx_queues; i++) {
5334                 rxq = dev->data->rx_queues[i];
5335
5336                 /* Allocate buffers for descriptor rings */
5337                 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
5338                 if (ret)
5339                         return ret;
5340
5341                 /* Setup the Base and Length of the Rx Descriptor Rings */
5342                 bus_addr = rxq->rx_ring_phys_addr;
5343
5344                 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
5345                                 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
5346                 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
5347                                 (uint32_t)(bus_addr >> 32));
5348                 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
5349                                 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
5350                 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
5351                 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
5352
5353
5354                 /* Configure the SRRCTL register */
5355 #ifdef RTE_HEADER_SPLIT_ENABLE
5356                 /*
5357                  * Configure Header Split
5358                  */
5359                 if (dev->data->dev_conf.rxmode.header_split) {
5360                         srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
5361                                 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
5362                                 IXGBE_SRRCTL_BSIZEHDR_MASK);
5363                         srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
5364                 } else
5365 #endif
5366                         srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
5367
5368                 /* Set if packets are dropped when no descriptors available */
5369                 if (rxq->drop_en)
5370                         srrctl |= IXGBE_SRRCTL_DROP_EN;
5371
5372                 /*
5373                  * Configure the RX buffer size in the BSIZEPACKET field of
5374                  * the SRRCTL register of the queue.
5375                  * The value is in 1 KB resolution. Valid values can be from
5376                  * 1 KB to 16 KB.
5377                  */
5378                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
5379                         RTE_PKTMBUF_HEADROOM);
5380                 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
5381                            IXGBE_SRRCTL_BSIZEPKT_MASK);
5382
5383                 /*
5384                  * VF modification to write virtual function SRRCTL register
5385                  */
5386                 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
5387
5388                 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
5389                                        IXGBE_SRRCTL_BSIZEPKT_SHIFT);
5390
5391                 if (dev->data->dev_conf.rxmode.enable_scatter ||
5392                     /* It adds dual VLAN length for supporting dual VLAN */
5393                     (dev->data->dev_conf.rxmode.max_rx_pkt_len +
5394                                 2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {
5395                         if (!dev->data->scattered_rx)
5396                                 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
5397                         dev->data->scattered_rx = 1;
5398                 }
5399         }
5400
5401 #ifdef RTE_HEADER_SPLIT_ENABLE
5402         if (dev->data->dev_conf.rxmode.header_split)
5403                 /* Must setup the PSRTYPE register */
5404                 psrtype = IXGBE_PSRTYPE_TCPHDR |
5405                         IXGBE_PSRTYPE_UDPHDR   |
5406                         IXGBE_PSRTYPE_IPV4HDR  |
5407                         IXGBE_PSRTYPE_IPV6HDR;
5408 #endif
5409
5410         /* Set RQPL for VF RSS according to max Rx queue */
5411         psrtype |= (dev->data->nb_rx_queues >> 1) <<
5412                 IXGBE_PSRTYPE_RQPL_SHIFT;
5413         IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, psrtype);
5414
5415         ixgbe_set_rx_function(dev);
5416
5417         return 0;
5418 }
5419
5420 /*
5421  * [VF] Initializes Transmit Unit.
5422  */
5423 void __attribute__((cold))
5424 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
5425 {
5426         struct ixgbe_hw     *hw;
5427         struct ixgbe_tx_queue *txq;
5428         uint64_t bus_addr;
5429         uint32_t txctrl;
5430         uint16_t i;
5431
5432         PMD_INIT_FUNC_TRACE();
5433         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5434
5435         /* Setup the Base and Length of the Tx Descriptor Rings */
5436         for (i = 0; i < dev->data->nb_tx_queues; i++) {
5437                 txq = dev->data->tx_queues[i];
5438                 bus_addr = txq->tx_ring_phys_addr;
5439                 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
5440                                 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
5441                 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
5442                                 (uint32_t)(bus_addr >> 32));
5443                 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
5444                                 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
5445                 /* Setup the HW Tx Head and TX Tail descriptor pointers */
5446                 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
5447                 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
5448
5449                 /*
5450                  * Disable Tx Head Writeback RO bit, since this hoses
5451                  * bookkeeping if things aren't delivered in order.
5452                  */
5453                 txctrl = IXGBE_READ_REG(hw,
5454                                 IXGBE_VFDCA_TXCTRL(i));
5455                 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
5456                 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
5457                                 txctrl);
5458         }
5459 }
5460
5461 /*
5462  * [VF] Start Transmit and Receive Units.
5463  */
5464 void __attribute__((cold))
5465 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
5466 {
5467         struct ixgbe_hw     *hw;
5468         struct ixgbe_tx_queue *txq;
5469         struct ixgbe_rx_queue *rxq;
5470         uint32_t txdctl;
5471         uint32_t rxdctl;
5472         uint16_t i;
5473         int poll_ms;
5474
5475         PMD_INIT_FUNC_TRACE();
5476         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5477
5478         for (i = 0; i < dev->data->nb_tx_queues; i++) {
5479                 txq = dev->data->tx_queues[i];
5480                 /* Setup Transmit Threshold Registers */
5481                 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
5482                 txdctl |= txq->pthresh & 0x7F;
5483                 txdctl |= ((txq->hthresh & 0x7F) << 8);
5484                 txdctl |= ((txq->wthresh & 0x7F) << 16);
5485                 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
5486         }
5487
5488         for (i = 0; i < dev->data->nb_tx_queues; i++) {
5489
5490                 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
5491                 txdctl |= IXGBE_TXDCTL_ENABLE;
5492                 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
5493
5494                 poll_ms = 10;
5495                 /* Wait until TX Enable ready */
5496                 do {
5497                         rte_delay_ms(1);
5498                         txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
5499                 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
5500                 if (!poll_ms)
5501                         PMD_INIT_LOG(ERR, "Could not enable Tx Queue %d", i);
5502         }
5503         for (i = 0; i < dev->data->nb_rx_queues; i++) {
5504
5505                 rxq = dev->data->rx_queues[i];
5506
5507                 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
5508                 rxdctl |= IXGBE_RXDCTL_ENABLE;
5509                 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
5510
5511                 /* Wait until RX Enable ready */
5512                 poll_ms = 10;
5513                 do {
5514                         rte_delay_ms(1);
5515                         rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
5516                 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
5517                 if (!poll_ms)
5518                         PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d", i);
5519                 rte_wmb();
5520                 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);
5521
5522         }
5523 }
5524
5525 int
5526 ixgbe_config_rss_filter(struct rte_eth_dev *dev,
5527                 struct ixgbe_rte_flow_rss_conf *conf, bool add)
5528 {
5529         struct ixgbe_hw *hw;
5530         uint32_t reta;
5531         uint16_t i;
5532         uint16_t j;
5533         uint16_t sp_reta_size;
5534         uint32_t reta_reg;
5535         struct rte_eth_rss_conf rss_conf = conf->rss_conf;
5536         struct ixgbe_filter_info *filter_info =
5537                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5538
5539         PMD_INIT_FUNC_TRACE();
5540         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5541
5542         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5543
5544         if (!add) {
5545                 if (memcmp(conf, &filter_info->rss_info,
5546                         sizeof(struct ixgbe_rte_flow_rss_conf)) == 0) {
5547                         ixgbe_rss_disable(dev);
5548                         memset(&filter_info->rss_info, 0,
5549                                 sizeof(struct ixgbe_rte_flow_rss_conf));
5550                         return 0;
5551                 }
5552                 return -EINVAL;
5553         }
5554
5555         if (filter_info->rss_info.num)
5556                 return -EINVAL;
5557         /* Fill in redirection table
5558          * The byte-swap is needed because NIC registers are in
5559          * little-endian order.
5560          */
5561         reta = 0;
5562         for (i = 0, j = 0; i < sp_reta_size; i++, j++) {
5563                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5564
5565                 if (j == conf->num)
5566                         j = 0;
5567                 reta = (reta << 8) | conf->queue[j];
5568                 if ((i & 3) == 3)
5569                         IXGBE_WRITE_REG(hw, reta_reg,
5570                                         rte_bswap32(reta));
5571         }
5572
5573         /* Configure the RSS key and the RSS protocols used to compute
5574          * the RSS hash of input packets.
5575          */
5576         if ((rss_conf.rss_hf & IXGBE_RSS_OFFLOAD_ALL) == 0) {
5577                 ixgbe_rss_disable(dev);
5578                 return -EINVAL;
5579         }
5580         if (rss_conf.rss_key == NULL)
5581                 rss_conf.rss_key = rss_intel_key; /* Default hash key */
5582         ixgbe_hw_rss_hash_set(hw, &rss_conf);
5583
5584         rte_memcpy(&filter_info->rss_info,
5585                 conf, sizeof(struct ixgbe_rte_flow_rss_conf));
5586
5587         return 0;
5588 }
5589
5590 /* Stubs needed for linkage when CONFIG_RTE_IXGBE_INC_VECTOR is set to 'n' */
5591 int __attribute__((weak))
5592 ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
5593 {
5594         return -1;
5595 }
5596
5597 uint16_t __attribute__((weak))
5598 ixgbe_recv_pkts_vec(
5599         void __rte_unused *rx_queue,
5600         struct rte_mbuf __rte_unused **rx_pkts,
5601         uint16_t __rte_unused nb_pkts)
5602 {
5603         return 0;
5604 }
5605
5606 uint16_t __attribute__((weak))
5607 ixgbe_recv_scattered_pkts_vec(
5608         void __rte_unused *rx_queue,
5609         struct rte_mbuf __rte_unused **rx_pkts,
5610         uint16_t __rte_unused nb_pkts)
5611 {
5612         return 0;
5613 }
5614
5615 int __attribute__((weak))
5616 ixgbe_rxq_vec_setup(struct ixgbe_rx_queue __rte_unused *rxq)
5617 {
5618         return -1;
5619 }