drivers/net/ixgbe/ixgbe_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation.
   3  * Copyright 2014 6WIND S.A.
   4  */
   5
   6 #include <sys/queue.h>
   7
   8 #include <stdio.h>
   9 #include <stdlib.h>
  10 #include <string.h>
  11 #include <errno.h>
  12 #include <stdint.h>
  13 #include <stdarg.h>
  14 #include <unistd.h>
  15 #include <inttypes.h>
  16
  17 #include <rte_byteorder.h>
  18 #include <rte_common.h>
  19 #include <rte_cycles.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_interrupts.h>
  23 #include <rte_pci.h>
  24 #include <rte_memory.h>
  25 #include <rte_memzone.h>
  26 #include <rte_launch.h>
  27 #include <rte_eal.h>
  28 #include <rte_per_lcore.h>
  29 #include <rte_lcore.h>
  30 #include <rte_atomic.h>
  31 #include <rte_branch_prediction.h>
  32 #include <rte_mempool.h>
  33 #include <rte_malloc.h>
  34 #include <rte_mbuf.h>
  35 #include <rte_ether.h>
  36 #include <rte_ethdev_driver.h>
  37 #include <rte_prefetch.h>
  38 #include <rte_udp.h>
  39 #include <rte_tcp.h>
  40 #include <rte_sctp.h>
  41 #include <rte_string_fns.h>
  42 #include <rte_errno.h>
  43 #include <rte_ip.h>
  44 #include <rte_net.h>
  45
  46 #include "ixgbe_logs.h"
  47 #include "base/ixgbe_api.h"
  48 #include "base/ixgbe_vf.h"
  49 #include "ixgbe_ethdev.h"
  50 #include "base/ixgbe_dcb.h"
  51 #include "base/ixgbe_common.h"
  52 #include "ixgbe_rxtx.h"
  53
  54 #ifdef RTE_LIBRTE_IEEE1588
  55 #define IXGBE_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST
  56 #else
  57 #define IXGBE_TX_IEEE1588_TMST 0
  58 #endif
  59 /* Bit Mask to indicate what bits required for building TX context */
  60 #define IXGBE_TX_OFFLOAD_MASK (                  \
  61                 PKT_TX_VLAN_PKT |                \
  62                 PKT_TX_IP_CKSUM |                \
  63                 PKT_TX_L4_MASK |                 \
  64                 PKT_TX_TCP_SEG |                 \
  65                 PKT_TX_MACSEC |                  \
  66                 PKT_TX_OUTER_IP_CKSUM |          \
  67                 PKT_TX_SEC_OFFLOAD |     \
  68                 IXGBE_TX_IEEE1588_TMST)
  69
  70 #define IXGBE_TX_OFFLOAD_NOTSUP_MASK \
  71                 (PKT_TX_OFFLOAD_MASK ^ IXGBE_TX_OFFLOAD_MASK)
  72
  73 #if 1
  74 #define RTE_PMD_USE_PREFETCH
  75 #endif
  76
  77 #ifdef RTE_PMD_USE_PREFETCH
  78 /*
  79  * Prefetch a cache line into all cache levels.
  80  */
  81 #define rte_ixgbe_prefetch(p)   rte_prefetch0(p)
  82 #else
  83 #define rte_ixgbe_prefetch(p)   do {} while (0)
  84 #endif
  85
  86 #ifdef RTE_IXGBE_INC_VECTOR
  87 uint16_t ixgbe_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
  88                                     uint16_t nb_pkts);
  89 #endif
  90
  91 /*********************************************************************
  92  *
  93  *  TX functions
  94  *
  95  **********************************************************************/
  96
  97 /*
  98  * Check for descriptors with their DD bit set and free mbufs.
  99  * Return the total number of buffers freed.
 100  */
 101 static __rte_always_inline int
 102 ixgbe_tx_free_bufs(struct ixgbe_tx_queue *txq)
 103 {
 104         struct ixgbe_tx_entry *txep;
 105         uint32_t status;
 106         int i, nb_free = 0;
 107         struct rte_mbuf *m, *free[RTE_IXGBE_TX_MAX_FREE_BUF_SZ];
 108
 109         /* check DD bit on threshold descriptor */
 110         status = txq->tx_ring[txq->tx_next_dd].wb.status;
 111         if (!(status & rte_cpu_to_le_32(IXGBE_ADVTXD_STAT_DD)))
 112                 return 0;
 113
 114         /*
 115          * first buffer to free from S/W ring is at index
 116          * tx_next_dd - (tx_rs_thresh-1)
 117          */
 118         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
 119
 120         for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
 121                 /* free buffers one at a time */
 122                 m = rte_pktmbuf_prefree_seg(txep->mbuf);
 123                 txep->mbuf = NULL;
 124
 125                 if (unlikely(m == NULL))
 126                         continue;
 127
 128                 if (nb_free >= RTE_IXGBE_TX_MAX_FREE_BUF_SZ ||
 129                     (nb_free > 0 && m->pool != free[0]->pool)) {
 130                         rte_mempool_put_bulk(free[0]->pool,
 131                                              (void **)free, nb_free);
 132                         nb_free = 0;
 133                 }
 134
 135                 free[nb_free++] = m;
 136         }
 137
 138         if (nb_free > 0)
 139                 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
 140
 141         /* buffers were freed, update counters */
 142         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
 143         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
 144         if (txq->tx_next_dd >= txq->nb_tx_desc)
 145                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
 146
 147         return txq->tx_rs_thresh;
 148 }
 149
 150 /* Populate 4 descriptors with data from 4 mbufs */
 151 static inline void
 152 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
 153 {
 154         uint64_t buf_dma_addr;
 155         uint32_t pkt_len;
 156         int i;
 157
 158         for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
 159                 buf_dma_addr = rte_mbuf_data_iova(*pkts);
 160                 pkt_len = (*pkts)->data_len;
 161
 162                 /* write data to descriptor */
 163                 txdp->read.buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
 164
 165                 txdp->read.cmd_type_len =
 166                         rte_cpu_to_le_32((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
 167
 168                 txdp->read.olinfo_status =
 169                         rte_cpu_to_le_32(pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
 170
 171                 rte_prefetch0(&(*pkts)->pool);
 172         }
 173 }
 174
 175 /* Populate 1 descriptor with data from 1 mbuf */
 176 static inline void
 177 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
 178 {
 179         uint64_t buf_dma_addr;
 180         uint32_t pkt_len;
 181
 182         buf_dma_addr = rte_mbuf_data_iova(*pkts);
 183         pkt_len = (*pkts)->data_len;
 184
 185         /* write data to descriptor */
 186         txdp->read.buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
 187         txdp->read.cmd_type_len =
 188                         rte_cpu_to_le_32((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
 189         txdp->read.olinfo_status =
 190                         rte_cpu_to_le_32(pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
 191         rte_prefetch0(&(*pkts)->pool);
 192 }
 193
 194 /*
 195  * Fill H/W descriptor ring with mbuf data.
 196  * Copy mbuf pointers to the S/W ring.
 197  */
 198 static inline void
 199 ixgbe_tx_fill_hw_ring(struct ixgbe_tx_queue *txq, struct rte_mbuf **pkts,
 200                       uint16_t nb_pkts)
 201 {
 202         volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
 203         struct ixgbe_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
 204         const int N_PER_LOOP = 4;
 205         const int N_PER_LOOP_MASK = N_PER_LOOP-1;
 206         int mainpart, leftover;
 207         int i, j;
 208
 209         /*
 210          * Process most of the packets in chunks of N pkts.  Any
 211          * leftover packets will get processed one at a time.
 212          */
 213         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
 214         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
 215         for (i = 0; i < mainpart; i += N_PER_LOOP) {
 216                 /* Copy N mbuf pointers to the S/W ring */
 217                 for (j = 0; j < N_PER_LOOP; ++j) {
 218                         (txep + i + j)->mbuf = *(pkts + i + j);
 219                 }
 220                 tx4(txdp + i, pkts + i);
 221         }
 222
 223         if (unlikely(leftover > 0)) {
 224                 for (i = 0; i < leftover; ++i) {
 225                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
 226                         tx1(txdp + mainpart + i, pkts + mainpart + i);
 227                 }
 228         }
 229 }
 230
 231 static inline uint16_t
 232 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 233              uint16_t nb_pkts)
 234 {
 235         struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
 236         volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
 237         uint16_t n = 0;
 238
 239         /*
 240          * Begin scanning the H/W ring for done descriptors when the
 241          * number of available descriptors drops below tx_free_thresh.  For
 242          * each done descriptor, free the associated buffer.
 243          */
 244         if (txq->nb_tx_free < txq->tx_free_thresh)
 245                 ixgbe_tx_free_bufs(txq);
 246
 247         /* Only use descriptors that are available */
 248         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
 249         if (unlikely(nb_pkts == 0))
 250                 return 0;
 251
 252         /* Use exactly nb_pkts descriptors */
 253         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
 254
 255         /*
 256          * At this point, we know there are enough descriptors in the
 257          * ring to transmit all the packets.  This assumes that each
 258          * mbuf contains a single segment, and that no new offloads
 259          * are expected, which would require a new context descriptor.
 260          */
 261
 262         /*
 263          * See if we're going to wrap-around. If so, handle the top
 264          * of the descriptor ring first, then do the bottom.  If not,
 265          * the processing looks just like the "bottom" part anyway...
 266          */
 267         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
 268                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
 269                 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
 270
 271                 /*
 272                  * We know that the last descriptor in the ring will need to
 273                  * have its RS bit set because tx_rs_thresh has to be
 274                  * a divisor of the ring size
 275                  */
 276                 tx_r[txq->tx_next_rs].read.cmd_type_len |=
 277                         rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
 278                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 279
 280                 txq->tx_tail = 0;
 281         }
 282
 283         /* Fill H/W descriptor ring with mbuf data */
 284         ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
 285         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
 286
 287         /*
 288          * Determine if RS bit should be set
 289          * This is what we actually want:
 290          *   if ((txq->tx_tail - 1) >= txq->tx_next_rs)
 291          * but instead of subtracting 1 and doing >=, we can just do
 292          * greater than without subtracting.
 293          */
 294         if (txq->tx_tail > txq->tx_next_rs) {
 295                 tx_r[txq->tx_next_rs].read.cmd_type_len |=
 296                         rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
 297                 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
 298                                                 txq->tx_rs_thresh);
 299                 if (txq->tx_next_rs >= txq->nb_tx_desc)
 300                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 301         }
 302
 303         /*
 304          * Check for wrap-around. This would only happen if we used
 305          * up to the last descriptor in the ring, no more, no less.
 306          */
 307         if (txq->tx_tail >= txq->nb_tx_desc)
 308                 txq->tx_tail = 0;
 309
 310         /* update tail pointer */
 311         rte_wmb();
 312         IXGBE_PCI_REG_WRITE_RELAXED(txq->tdt_reg_addr, txq->tx_tail);
 313
 314         return nb_pkts;
 315 }
 316
 317 uint16_t
 318 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
 319                        uint16_t nb_pkts)
 320 {
 321         uint16_t nb_tx;
 322
 323         /* Try to transmit at least chunks of TX_MAX_BURST pkts */
 324         if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
 325                 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
 326
 327         /* transmit more than the max burst, in chunks of TX_MAX_BURST */
 328         nb_tx = 0;
 329         while (nb_pkts) {
 330                 uint16_t ret, n;
 331
 332                 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
 333                 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
 334                 nb_tx = (uint16_t)(nb_tx + ret);
 335                 nb_pkts = (uint16_t)(nb_pkts - ret);
 336                 if (ret < n)
 337                         break;
 338         }
 339
 340         return nb_tx;
 341 }
 342
 343 #ifdef RTE_IXGBE_INC_VECTOR
 344 static uint16_t
 345 ixgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 346                     uint16_t nb_pkts)
 347 {
 348         uint16_t nb_tx = 0;
 349         struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
 350
 351         while (nb_pkts) {
 352                 uint16_t ret, num;
 353
 354                 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
 355                 ret = ixgbe_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
 356                                                  num);
 357                 nb_tx += ret;
 358                 nb_pkts -= ret;
 359                 if (ret < num)
 360                         break;
 361         }
 362
 363         return nb_tx;
 364 }
 365 #endif
 366
 367 static inline void
 368 ixgbe_set_xmit_ctx(struct ixgbe_tx_queue *txq,
 369                 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
 370                 uint64_t ol_flags, union ixgbe_tx_offload tx_offload,
 371                 __rte_unused uint64_t *mdata)
 372 {
 373         uint32_t type_tucmd_mlhl;
 374         uint32_t mss_l4len_idx = 0;
 375         uint32_t ctx_idx;
 376         uint32_t vlan_macip_lens;
 377         union ixgbe_tx_offload tx_offload_mask;
 378         uint32_t seqnum_seed = 0;
 379
 380         ctx_idx = txq->ctx_curr;
 381         tx_offload_mask.data[0] = 0;
 382         tx_offload_mask.data[1] = 0;
 383         type_tucmd_mlhl = 0;
 384
 385         /* Specify which HW CTX to upload. */
 386         mss_l4len_idx |= (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
 387
 388         if (ol_flags & PKT_TX_VLAN_PKT) {
 389                 tx_offload_mask.vlan_tci |= ~0;
 390         }
 391
 392         /* check if TCP segmentation required for this packet */
 393         if (ol_flags & PKT_TX_TCP_SEG) {
 394                 /* implies IP cksum in IPv4 */
 395                 if (ol_flags & PKT_TX_IP_CKSUM)
 396                         type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4 |
 397                                 IXGBE_ADVTXD_TUCMD_L4T_TCP |
 398                                 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
 399                 else
 400                         type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV6 |
 401                                 IXGBE_ADVTXD_TUCMD_L4T_TCP |
 402                                 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
 403
 404                 tx_offload_mask.l2_len |= ~0;
 405                 tx_offload_mask.l3_len |= ~0;
 406                 tx_offload_mask.l4_len |= ~0;
 407                 tx_offload_mask.tso_segsz |= ~0;
 408                 mss_l4len_idx |= tx_offload.tso_segsz << IXGBE_ADVTXD_MSS_SHIFT;
 409                 mss_l4len_idx |= tx_offload.l4_len << IXGBE_ADVTXD_L4LEN_SHIFT;
 410         } else { /* no TSO, check if hardware checksum is needed */
 411                 if (ol_flags & PKT_TX_IP_CKSUM) {
 412                         type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
 413                         tx_offload_mask.l2_len |= ~0;
 414                         tx_offload_mask.l3_len |= ~0;
 415                 }
 416
 417                 switch (ol_flags & PKT_TX_L4_MASK) {
 418                 case PKT_TX_UDP_CKSUM:
 419                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
 420                                 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
 421                         mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
 422                         tx_offload_mask.l2_len |= ~0;
 423                         tx_offload_mask.l3_len |= ~0;
 424                         break;
 425                 case PKT_TX_TCP_CKSUM:
 426                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
 427                                 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
 428                         mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
 429                         tx_offload_mask.l2_len |= ~0;
 430                         tx_offload_mask.l3_len |= ~0;
 431                         break;
 432                 case PKT_TX_SCTP_CKSUM:
 433                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
 434                                 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
 435                         mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
 436                         tx_offload_mask.l2_len |= ~0;
 437                         tx_offload_mask.l3_len |= ~0;
 438                         break;
 439                 default:
 440                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
 441                                 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
 442                         break;
 443                 }
 444         }
 445
 446         if (ol_flags & PKT_TX_OUTER_IP_CKSUM) {
 447                 tx_offload_mask.outer_l2_len |= ~0;
 448                 tx_offload_mask.outer_l3_len |= ~0;
 449                 tx_offload_mask.l2_len |= ~0;
 450                 seqnum_seed |= tx_offload.outer_l3_len
 451                                << IXGBE_ADVTXD_OUTER_IPLEN;
 452                 seqnum_seed |= tx_offload.l2_len
 453                                << IXGBE_ADVTXD_TUNNEL_LEN;
 454         }
 455 #ifdef RTE_LIBRTE_SECURITY
 456         if (ol_flags & PKT_TX_SEC_OFFLOAD) {
 457                 union ixgbe_crypto_tx_desc_md *md =
 458                                 (union ixgbe_crypto_tx_desc_md *)mdata;
 459                 seqnum_seed |=
 460                         (IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK & md->sa_idx);
 461                 type_tucmd_mlhl |= md->enc ?
 462                                 (IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP |
 463                                 IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN) : 0;
 464                 type_tucmd_mlhl |=
 465                         (md->pad_len & IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK);
 466                 tx_offload_mask.sa_idx |= ~0;
 467                 tx_offload_mask.sec_pad_len |= ~0;
 468         }
 469 #endif
 470
 471         txq->ctx_cache[ctx_idx].flags = ol_flags;
 472         txq->ctx_cache[ctx_idx].tx_offload.data[0]  =
 473                 tx_offload_mask.data[0] & tx_offload.data[0];
 474         txq->ctx_cache[ctx_idx].tx_offload.data[1]  =
 475                 tx_offload_mask.data[1] & tx_offload.data[1];
 476         txq->ctx_cache[ctx_idx].tx_offload_mask    = tx_offload_mask;
 477
 478         ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
 479         vlan_macip_lens = tx_offload.l3_len;
 480         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 481                 vlan_macip_lens |= (tx_offload.outer_l2_len <<
 482                                     IXGBE_ADVTXD_MACLEN_SHIFT);
 483         else
 484                 vlan_macip_lens |= (tx_offload.l2_len <<
 485                                     IXGBE_ADVTXD_MACLEN_SHIFT);
 486         vlan_macip_lens |= ((uint32_t)tx_offload.vlan_tci << IXGBE_ADVTXD_VLAN_SHIFT);
 487         ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
 488         ctx_txd->mss_l4len_idx   = rte_cpu_to_le_32(mss_l4len_idx);
 489         ctx_txd->seqnum_seed     = seqnum_seed;
 490 }
 491
 492 /*
 493  * Check which hardware context can be used. Use the existing match
 494  * or create a new context descriptor.
 495  */
 496 static inline uint32_t
 497 what_advctx_update(struct ixgbe_tx_queue *txq, uint64_t flags,
 498                    union ixgbe_tx_offload tx_offload)
 499 {
 500         /* If match with the current used context */
 501         if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
 502                    (txq->ctx_cache[txq->ctx_curr].tx_offload.data[0] ==
 503                     (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[0]
 504                      & tx_offload.data[0])) &&
 505                    (txq->ctx_cache[txq->ctx_curr].tx_offload.data[1] ==
 506                     (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[1]
 507                      & tx_offload.data[1]))))
 508                 return txq->ctx_curr;
 509
 510         /* What if match with the next context  */
 511         txq->ctx_curr ^= 1;
 512         if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
 513                    (txq->ctx_cache[txq->ctx_curr].tx_offload.data[0] ==
 514                     (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[0]
 515                      & tx_offload.data[0])) &&
 516                    (txq->ctx_cache[txq->ctx_curr].tx_offload.data[1] ==
 517                     (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[1]
 518                      & tx_offload.data[1]))))
 519                 return txq->ctx_curr;
 520
 521         /* Mismatch, use the previous context */
 522         return IXGBE_CTX_NUM;
 523 }
 524
 525 static inline uint32_t
 526 tx_desc_cksum_flags_to_olinfo(uint64_t ol_flags)
 527 {
 528         uint32_t tmp = 0;
 529
 530         if ((ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM)
 531                 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
 532         if (ol_flags & PKT_TX_IP_CKSUM)
 533                 tmp |= IXGBE_ADVTXD_POPTS_IXSM;
 534         if (ol_flags & PKT_TX_TCP_SEG)
 535                 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
 536         return tmp;
 537 }
 538
 539 static inline uint32_t
 540 tx_desc_ol_flags_to_cmdtype(uint64_t ol_flags)
 541 {
 542         uint32_t cmdtype = 0;
 543
 544         if (ol_flags & PKT_TX_VLAN_PKT)
 545                 cmdtype |= IXGBE_ADVTXD_DCMD_VLE;
 546         if (ol_flags & PKT_TX_TCP_SEG)
 547                 cmdtype |= IXGBE_ADVTXD_DCMD_TSE;
 548         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 549                 cmdtype |= (1 << IXGBE_ADVTXD_OUTERIPCS_SHIFT);
 550         if (ol_flags & PKT_TX_MACSEC)
 551                 cmdtype |= IXGBE_ADVTXD_MAC_LINKSEC;
 552         return cmdtype;
 553 }
 554
 555 /* Default RS bit threshold values */
 556 #ifndef DEFAULT_TX_RS_THRESH
 557 #define DEFAULT_TX_RS_THRESH   32
 558 #endif
 559 #ifndef DEFAULT_TX_FREE_THRESH
 560 #define DEFAULT_TX_FREE_THRESH 32
 561 #endif
 562
 563 /* Reset transmit descriptors after they have been used */
 564 static inline int
 565 ixgbe_xmit_cleanup(struct ixgbe_tx_queue *txq)
 566 {
 567         struct ixgbe_tx_entry *sw_ring = txq->sw_ring;
 568         volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
 569         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 570         uint16_t nb_tx_desc = txq->nb_tx_desc;
 571         uint16_t desc_to_clean_to;
 572         uint16_t nb_tx_to_clean;
 573         uint32_t status;
 574
 575         /* Determine the last descriptor needing to be cleaned */
 576         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 577         if (desc_to_clean_to >= nb_tx_desc)
 578                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 579
 580         /* Check to make sure the last descriptor to clean is done */
 581         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 582         status = txr[desc_to_clean_to].wb.status;
 583         if (!(status & rte_cpu_to_le_32(IXGBE_TXD_STAT_DD))) {
 584                 PMD_TX_FREE_LOG(DEBUG,
 585                                 "TX descriptor %4u is not done"
 586                                 "(port=%d queue=%d)",
 587                                 desc_to_clean_to,
 588                                 txq->port_id, txq->queue_id);
 589                 /* Failed to clean any descriptors, better luck next time */
 590                 return -(1);
 591         }
 592
 593         /* Figure out how many descriptors will be cleaned */
 594         if (last_desc_cleaned > desc_to_clean_to)
 595                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 596                                                         desc_to_clean_to);
 597         else
 598                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 599                                                 last_desc_cleaned);
 600
 601         PMD_TX_FREE_LOG(DEBUG,
 602                         "Cleaning %4u TX descriptors: %4u to %4u "
 603                         "(port=%d queue=%d)",
 604                         nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
 605                         txq->port_id, txq->queue_id);
 606
 607         /*
 608          * The last descriptor to clean is done, so that means all the
 609          * descriptors from the last descriptor that was cleaned
 610          * up to the last descriptor with the RS bit set
 611          * are done. Only reset the threshold descriptor.
 612          */
 613         txr[desc_to_clean_to].wb.status = 0;
 614
 615         /* Update the txq to reflect the last descriptor that was cleaned */
 616         txq->last_desc_cleaned = desc_to_clean_to;
 617         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 618
 619         /* No Error */
 620         return 0;
 621 }
 622
 623 uint16_t
 624 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 625                 uint16_t nb_pkts)
 626 {
 627         struct ixgbe_tx_queue *txq;
 628         struct ixgbe_tx_entry *sw_ring;
 629         struct ixgbe_tx_entry *txe, *txn;
 630         volatile union ixgbe_adv_tx_desc *txr;
 631         volatile union ixgbe_adv_tx_desc *txd, *txp;
 632         struct rte_mbuf     *tx_pkt;
 633         struct rte_mbuf     *m_seg;
 634         uint64_t buf_dma_addr;
 635         uint32_t olinfo_status;
 636         uint32_t cmd_type_len;
 637         uint32_t pkt_len;
 638         uint16_t slen;
 639         uint64_t ol_flags;
 640         uint16_t tx_id;
 641         uint16_t tx_last;
 642         uint16_t nb_tx;
 643         uint16_t nb_used;
 644         uint64_t tx_ol_req;
 645         uint32_t ctx = 0;
 646         uint32_t new_ctx;
 647         union ixgbe_tx_offload tx_offload;
 648 #ifdef RTE_LIBRTE_SECURITY
 649         uint8_t use_ipsec;
 650 #endif
 651
 652         tx_offload.data[0] = 0;
 653         tx_offload.data[1] = 0;
 654         txq = tx_queue;
 655         sw_ring = txq->sw_ring;
 656         txr     = txq->tx_ring;
 657         tx_id   = txq->tx_tail;
 658         txe = &sw_ring[tx_id];
 659         txp = NULL;
 660
 661         /* Determine if the descriptor ring needs to be cleaned. */
 662         if (txq->nb_tx_free < txq->tx_free_thresh)
 663                 ixgbe_xmit_cleanup(txq);
 664
 665         rte_prefetch0(&txe->mbuf->pool);
 666
 667         /* TX loop */
 668         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
 669                 new_ctx = 0;
 670                 tx_pkt = *tx_pkts++;
 671                 pkt_len = tx_pkt->pkt_len;
 672
 673                 /*
 674                  * Determine how many (if any) context descriptors
 675                  * are needed for offload functionality.
 676                  */
 677                 ol_flags = tx_pkt->ol_flags;
 678 #ifdef RTE_LIBRTE_SECURITY
 679                 use_ipsec = txq->using_ipsec && (ol_flags & PKT_TX_SEC_OFFLOAD);
 680 #endif
 681
 682                 /* If hardware offload required */
 683                 tx_ol_req = ol_flags & IXGBE_TX_OFFLOAD_MASK;
 684                 if (tx_ol_req) {
 685                         tx_offload.l2_len = tx_pkt->l2_len;
 686                         tx_offload.l3_len = tx_pkt->l3_len;
 687                         tx_offload.l4_len = tx_pkt->l4_len;
 688                         tx_offload.vlan_tci = tx_pkt->vlan_tci;
 689                         tx_offload.tso_segsz = tx_pkt->tso_segsz;
 690                         tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
 691                         tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
 692 #ifdef RTE_LIBRTE_SECURITY
 693                         if (use_ipsec) {
 694                                 union ixgbe_crypto_tx_desc_md *ipsec_mdata =
 695                                         (union ixgbe_crypto_tx_desc_md *)
 696                                                         &tx_pkt->udata64;
 697                                 tx_offload.sa_idx = ipsec_mdata->sa_idx;
 698                                 tx_offload.sec_pad_len = ipsec_mdata->pad_len;
 699                         }
 700 #endif
 701
 702                         /* If new context need be built or reuse the exist ctx. */
 703                         ctx = what_advctx_update(txq, tx_ol_req,
 704                                 tx_offload);
 705                         /* Only allocate context descriptor if required*/
 706                         new_ctx = (ctx == IXGBE_CTX_NUM);
 707                         ctx = txq->ctx_curr;
 708                 }
 709
 710                 /*
 711                  * Keep track of how many descriptors are used this loop
 712                  * This will always be the number of segments + the number of
 713                  * Context descriptors required to transmit the packet
 714                  */
 715                 nb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);
 716
 717                 if (txp != NULL &&
 718                                 nb_used + txq->nb_tx_used >= txq->tx_rs_thresh)
 719                         /* set RS on the previous packet in the burst */
 720                         txp->read.cmd_type_len |=
 721                                 rte_cpu_to_le_32(IXGBE_TXD_CMD_RS);
 722
 723                 /*
 724                  * The number of descriptors that must be allocated for a
 725                  * packet is the number of segments of that packet, plus 1
 726                  * Context Descriptor for the hardware offload, if any.
 727                  * Determine the last TX descriptor to allocate in the TX ring
 728                  * for the packet, starting from the current position (tx_id)
 729                  * in the ring.
 730                  */
 731                 tx_last = (uint16_t) (tx_id + nb_used - 1);
 732
 733                 /* Circular ring */
 734                 if (tx_last >= txq->nb_tx_desc)
 735                         tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
 736
 737                 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
 738                            " tx_first=%u tx_last=%u",
 739                            (unsigned) txq->port_id,
 740                            (unsigned) txq->queue_id,
 741                            (unsigned) pkt_len,
 742                            (unsigned) tx_id,
 743                            (unsigned) tx_last);
 744
 745                 /*
 746                  * Make sure there are enough TX descriptors available to
 747                  * transmit the entire packet.
 748                  * nb_used better be less than or equal to txq->tx_rs_thresh
 749                  */
 750                 if (nb_used > txq->nb_tx_free) {
 751                         PMD_TX_FREE_LOG(DEBUG,
 752                                         "Not enough free TX descriptors "
 753                                         "nb_used=%4u nb_free=%4u "
 754                                         "(port=%d queue=%d)",
 755                                         nb_used, txq->nb_tx_free,
 756                                         txq->port_id, txq->queue_id);
 757
 758                         if (ixgbe_xmit_cleanup(txq) != 0) {
 759                                 /* Could not clean any descriptors */
 760                                 if (nb_tx == 0)
 761                                         return 0;
 762                                 goto end_of_tx;
 763                         }
 764
 765                         /* nb_used better be <= txq->tx_rs_thresh */
 766                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
 767                                 PMD_TX_FREE_LOG(DEBUG,
 768                                         "The number of descriptors needed to "
 769                                         "transmit the packet exceeds the "
 770                                         "RS bit threshold. This will impact "
 771                                         "performance."
 772                                         "nb_used=%4u nb_free=%4u "
 773                                         "tx_rs_thresh=%4u. "
 774                                         "(port=%d queue=%d)",
 775                                         nb_used, txq->nb_tx_free,
 776                                         txq->tx_rs_thresh,
 777                                         txq->port_id, txq->queue_id);
 778                                 /*
 779                                  * Loop here until there are enough TX
 780                                  * descriptors or until the ring cannot be
 781                                  * cleaned.
 782                                  */
 783                                 while (nb_used > txq->nb_tx_free) {
 784                                         if (ixgbe_xmit_cleanup(txq) != 0) {
 785                                                 /*
 786                                                  * Could not clean any
 787                                                  * descriptors
 788                                                  */
 789                                                 if (nb_tx == 0)
 790                                                         return 0;
 791                                                 goto end_of_tx;
 792                                         }
 793                                 }
 794                         }
 795                 }
 796
 797                 /*
 798                  * By now there are enough free TX descriptors to transmit
 799                  * the packet.
 800                  */
 801
 802                 /*
 803                  * Set common flags of all TX Data Descriptors.
 804                  *
 805                  * The following bits must be set in all Data Descriptors:
 806                  *   - IXGBE_ADVTXD_DTYP_DATA
 807                  *   - IXGBE_ADVTXD_DCMD_DEXT
 808                  *
 809                  * The following bits must be set in the first Data Descriptor
 810                  * and are ignored in the other ones:
 811                  *   - IXGBE_ADVTXD_DCMD_IFCS
 812                  *   - IXGBE_ADVTXD_MAC_1588
 813                  *   - IXGBE_ADVTXD_DCMD_VLE
 814                  *
 815                  * The following bits must only be set in the last Data
 816                  * Descriptor:
 817                  *   - IXGBE_TXD_CMD_EOP
 818                  *
 819                  * The following bits can be set in any Data Descriptor, but
 820                  * are only set in the last Data Descriptor:
 821                  *   - IXGBE_TXD_CMD_RS
 822                  */
 823                 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
 824                         IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
 825
 826 #ifdef RTE_LIBRTE_IEEE1588
 827                 if (ol_flags & PKT_TX_IEEE1588_TMST)
 828                         cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
 829 #endif
 830
 831                 olinfo_status = 0;
 832                 if (tx_ol_req) {
 833
 834                         if (ol_flags & PKT_TX_TCP_SEG) {
 835                                 /* when TSO is on, paylen in descriptor is the
 836                                  * not the packet len but the tcp payload len */
 837                                 pkt_len -= (tx_offload.l2_len +
 838                                         tx_offload.l3_len + tx_offload.l4_len);
 839                         }
 840
 841                         /*
 842                          * Setup the TX Advanced Context Descriptor if required
 843                          */
 844                         if (new_ctx) {
 845                                 volatile struct ixgbe_adv_tx_context_desc *
 846                                     ctx_txd;
 847
 848                                 ctx_txd = (volatile struct
 849                                     ixgbe_adv_tx_context_desc *)
 850                                     &txr[tx_id];
 851
 852                                 txn = &sw_ring[txe->next_id];
 853                                 rte_prefetch0(&txn->mbuf->pool);
 854
 855                                 if (txe->mbuf != NULL) {
 856                                         rte_pktmbuf_free_seg(txe->mbuf);
 857                                         txe->mbuf = NULL;
 858                                 }
 859
 860                                 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
 861                                         tx_offload, &tx_pkt->udata64);
 862
 863                                 txe->last_id = tx_last;
 864                                 tx_id = txe->next_id;
 865                                 txe = txn;
 866                         }
 867
 868                         /*
 869                          * Setup the TX Advanced Data Descriptor,
 870                          * This path will go through
 871                          * whatever new/reuse the context descriptor
 872                          */
 873                         cmd_type_len  |= tx_desc_ol_flags_to_cmdtype(ol_flags);
 874                         olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
 875                         olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
 876                 }
 877
 878                 olinfo_status |= (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
 879 #ifdef RTE_LIBRTE_SECURITY
 880                 if (use_ipsec)
 881                         olinfo_status |= IXGBE_ADVTXD_POPTS_IPSEC;
 882 #endif
 883
 884                 m_seg = tx_pkt;
 885                 do {
 886                         txd = &txr[tx_id];
 887                         txn = &sw_ring[txe->next_id];
 888                         rte_prefetch0(&txn->mbuf->pool);
 889
 890                         if (txe->mbuf != NULL)
 891                                 rte_pktmbuf_free_seg(txe->mbuf);
 892                         txe->mbuf = m_seg;
 893
 894                         /*
 895                          * Set up Transmit Data Descriptor.
 896                          */
 897                         slen = m_seg->data_len;
 898                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
 899                         txd->read.buffer_addr =
 900                                 rte_cpu_to_le_64(buf_dma_addr);
 901                         txd->read.cmd_type_len =
 902                                 rte_cpu_to_le_32(cmd_type_len | slen);
 903                         txd->read.olinfo_status =
 904                                 rte_cpu_to_le_32(olinfo_status);
 905                         txe->last_id = tx_last;
 906                         tx_id = txe->next_id;
 907                         txe = txn;
 908                         m_seg = m_seg->next;
 909                 } while (m_seg != NULL);
 910
 911                 /*
 912                  * The last packet data descriptor needs End Of Packet (EOP)
 913                  */
 914                 cmd_type_len |= IXGBE_TXD_CMD_EOP;
 915                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
 916                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
 917
 918                 /* Set RS bit only on threshold packets' last descriptor */
 919                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
 920                         PMD_TX_FREE_LOG(DEBUG,
 921                                         "Setting RS bit on TXD id="
 922                                         "%4u (port=%d queue=%d)",
 923                                         tx_last, txq->port_id, txq->queue_id);
 924
 925                         cmd_type_len |= IXGBE_TXD_CMD_RS;
 926
 927                         /* Update txq RS bit counters */
 928                         txq->nb_tx_used = 0;
 929                         txp = NULL;
 930                 } else
 931                         txp = txd;
 932
 933                 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
 934         }
 935
 936 end_of_tx:
 937         /* set RS on last packet in the burst */
 938         if (txp != NULL)
 939                 txp->read.cmd_type_len |= rte_cpu_to_le_32(IXGBE_TXD_CMD_RS);
 940
 941         rte_wmb();
 942
 943         /*
 944          * Set the Transmit Descriptor Tail (TDT)
 945          */
 946         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
 947                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
 948                    (unsigned) tx_id, (unsigned) nb_tx);
 949         IXGBE_PCI_REG_WRITE_RELAXED(txq->tdt_reg_addr, tx_id);
 950         txq->tx_tail = tx_id;
 951
 952         return nb_tx;
 953 }
 954
 955 /*********************************************************************
 956  *
 957  *  TX prep functions
 958  *
 959  **********************************************************************/
 960 uint16_t
 961 ixgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
 962 {
 963         int i, ret;
 964         uint64_t ol_flags;
 965         struct rte_mbuf *m;
 966         struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
 967
 968         for (i = 0; i < nb_pkts; i++) {
 969                 m = tx_pkts[i];
 970                 ol_flags = m->ol_flags;
 971
 972                 /**
 973                  * Check if packet meets requirements for number of segments
 974                  *
 975                  * NOTE: for ixgbe it's always (40 - WTHRESH) for both TSO and
 976                  *       non-TSO
 977                  */
 978
 979                 if (m->nb_segs > IXGBE_TX_MAX_SEG - txq->wthresh) {
 980                         rte_errno = -EINVAL;
 981                         return i;
 982                 }
 983
 984                 if (ol_flags & IXGBE_TX_OFFLOAD_NOTSUP_MASK) {
 985                         rte_errno = -ENOTSUP;
 986                         return i;
 987                 }
 988
 989 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
 990                 ret = rte_validate_tx_offload(m);
 991                 if (ret != 0) {
 992                         rte_errno = ret;
 993                         return i;
 994                 }
 995 #endif
 996                 ret = rte_net_intel_cksum_prepare(m);
 997                 if (ret != 0) {
 998                         rte_errno = ret;
 999                         return i;
1000                 }
1001         }
1002
1003         return i;
1004 }
1005
1006 /*********************************************************************
1007  *
1008  *  RX functions
1009  *
1010  **********************************************************************/
1011
1012 #define IXGBE_PACKET_TYPE_ETHER                         0X00
1013 #define IXGBE_PACKET_TYPE_IPV4                          0X01
1014 #define IXGBE_PACKET_TYPE_IPV4_TCP                      0X11
1015 #define IXGBE_PACKET_TYPE_IPV4_UDP                      0X21
1016 #define IXGBE_PACKET_TYPE_IPV4_SCTP                     0X41
1017 #define IXGBE_PACKET_TYPE_IPV4_EXT                      0X03
1018 #define IXGBE_PACKET_TYPE_IPV4_EXT_TCP                  0X13
1019 #define IXGBE_PACKET_TYPE_IPV4_EXT_UDP                  0X23
1020 #define IXGBE_PACKET_TYPE_IPV4_EXT_SCTP                 0X43
1021 #define IXGBE_PACKET_TYPE_IPV6                          0X04
1022 #define IXGBE_PACKET_TYPE_IPV6_TCP                      0X14
1023 #define IXGBE_PACKET_TYPE_IPV6_UDP                      0X24
1024 #define IXGBE_PACKET_TYPE_IPV6_SCTP                     0X44
1025 #define IXGBE_PACKET_TYPE_IPV6_EXT                      0X0C
1026 #define IXGBE_PACKET_TYPE_IPV6_EXT_TCP                  0X1C
1027 #define IXGBE_PACKET_TYPE_IPV6_EXT_UDP                  0X2C
1028 #define IXGBE_PACKET_TYPE_IPV6_EXT_SCTP                 0X4C
1029 #define IXGBE_PACKET_TYPE_IPV4_IPV6                     0X05
1030 #define IXGBE_PACKET_TYPE_IPV4_IPV6_TCP                 0X15
1031 #define IXGBE_PACKET_TYPE_IPV4_IPV6_UDP                 0X25
1032 #define IXGBE_PACKET_TYPE_IPV4_IPV6_SCTP                0X45
1033 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6                 0X07
1034 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_TCP             0X17
1035 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_UDP             0X27
1036 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_SCTP            0X47
1037 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT                 0X0D
1038 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_TCP             0X1D
1039 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_UDP             0X2D
1040 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_SCTP            0X4D
1041 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT             0X0F
1042 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_TCP         0X1F
1043 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_UDP         0X2F
1044 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_SCTP        0X4F
1045
1046 #define IXGBE_PACKET_TYPE_NVGRE                   0X00
1047 #define IXGBE_PACKET_TYPE_NVGRE_IPV4              0X01
1048 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_TCP          0X11
1049 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_UDP          0X21
1050 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_SCTP         0X41
1051 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT          0X03
1052 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_TCP      0X13
1053 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_UDP      0X23
1054 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_SCTP     0X43
1055 #define IXGBE_PACKET_TYPE_NVGRE_IPV6              0X04
1056 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_TCP          0X14
1057 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_UDP          0X24
1058 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_SCTP         0X44
1059 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT          0X0C
1060 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_TCP      0X1C
1061 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_UDP      0X2C
1062 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_SCTP     0X4C
1063 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6         0X05
1064 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_TCP     0X15
1065 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_UDP     0X25
1066 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT     0X0D
1067 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_TCP 0X1D
1068 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_UDP 0X2D
1069
1070 #define IXGBE_PACKET_TYPE_VXLAN                   0X80
1071 #define IXGBE_PACKET_TYPE_VXLAN_IPV4              0X81
1072 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_TCP          0x91
1073 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_UDP          0xA1
1074 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_SCTP         0xC1
1075 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT          0x83
1076 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_TCP      0X93
1077 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_UDP      0XA3
1078 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_SCTP     0XC3
1079 #define IXGBE_PACKET_TYPE_VXLAN_IPV6              0X84
1080 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_TCP          0X94
1081 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_UDP          0XA4
1082 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_SCTP         0XC4
1083 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT          0X8C
1084 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_TCP      0X9C
1085 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_UDP      0XAC
1086 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_SCTP     0XCC
1087 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6         0X85
1088 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_TCP     0X95
1089 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_UDP     0XA5
1090 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT     0X8D
1091 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_TCP 0X9D
1092 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_UDP 0XAD
1093
1094 /**
1095  * Use 2 different table for normal packet and tunnel packet
1096  * to save the space.
1097  */
1098 const uint32_t
1099         ptype_table[IXGBE_PACKET_TYPE_MAX] __rte_cache_aligned = {
1100         [IXGBE_PACKET_TYPE_ETHER] = RTE_PTYPE_L2_ETHER,
1101         [IXGBE_PACKET_TYPE_IPV4] = RTE_PTYPE_L2_ETHER |
1102                 RTE_PTYPE_L3_IPV4,
1103         [IXGBE_PACKET_TYPE_IPV4_TCP] = RTE_PTYPE_L2_ETHER |
1104                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP,
1105         [IXGBE_PACKET_TYPE_IPV4_UDP] = RTE_PTYPE_L2_ETHER |
1106                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
1107         [IXGBE_PACKET_TYPE_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |
1108                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_SCTP,
1109         [IXGBE_PACKET_TYPE_IPV4_EXT] = RTE_PTYPE_L2_ETHER |
1110                 RTE_PTYPE_L3_IPV4_EXT,
1111         [IXGBE_PACKET_TYPE_IPV4_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1112                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_TCP,
1113         [IXGBE_PACKET_TYPE_IPV4_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1114                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_UDP,
1115         [IXGBE_PACKET_TYPE_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1116                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_SCTP,
1117         [IXGBE_PACKET_TYPE_IPV6] = RTE_PTYPE_L2_ETHER |
1118                 RTE_PTYPE_L3_IPV6,
1119         [IXGBE_PACKET_TYPE_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1120                 RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP,
1121         [IXGBE_PACKET_TYPE_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1122                 RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
1123         [IXGBE_PACKET_TYPE_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
1124                 RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_SCTP,
1125         [IXGBE_PACKET_TYPE_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1126                 RTE_PTYPE_L3_IPV6_EXT,
1127         [IXGBE_PACKET_TYPE_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1128                 RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_TCP,
1129         [IXGBE_PACKET_TYPE_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1130                 RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_UDP,
1131         [IXGBE_PACKET_TYPE_IPV6_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1132                 RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_SCTP,
1133         [IXGBE_PACKET_TYPE_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |
1134                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1135                 RTE_PTYPE_INNER_L3_IPV6,
1136         [IXGBE_PACKET_TYPE_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1137                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1138                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_TCP,
1139         [IXGBE_PACKET_TYPE_IPV4_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1140                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1141         RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_UDP,
1142         [IXGBE_PACKET_TYPE_IPV4_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
1143                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1144                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_SCTP,
1145         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6] = RTE_PTYPE_L2_ETHER |
1146                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1147                 RTE_PTYPE_INNER_L3_IPV6,
1148         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1149                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1150                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_TCP,
1151         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1152                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1153                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_UDP,
1154         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
1155                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1156                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_SCTP,
1157         [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1158                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1159                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1160         [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1161                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1162                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_TCP,
1163         [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1164                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1165                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_UDP,
1166         [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1167                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1168                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_SCTP,
1169         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1170                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1171                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1172         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1173                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1174                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_TCP,
1175         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1176                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1177                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_UDP,
1178         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_SCTP] =
1179                 RTE_PTYPE_L2_ETHER |
1180                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1181                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_SCTP,
1182 };
1183
1184 const uint32_t
1185         ptype_table_tn[IXGBE_PACKET_TYPE_TN_MAX] __rte_cache_aligned = {
1186         [IXGBE_PACKET_TYPE_NVGRE] = RTE_PTYPE_L2_ETHER |
1187                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1188                 RTE_PTYPE_INNER_L2_ETHER,
1189         [IXGBE_PACKET_TYPE_NVGRE_IPV4] = RTE_PTYPE_L2_ETHER |
1190                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1191                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1192         [IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT] = RTE_PTYPE_L2_ETHER |
1193                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1194                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4_EXT,
1195         [IXGBE_PACKET_TYPE_NVGRE_IPV6] = RTE_PTYPE_L2_ETHER |
1196                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1197                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6,
1198         [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |
1199                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1200                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1201         [IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1202                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1203                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6_EXT,
1204         [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1205                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1206                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1207         [IXGBE_PACKET_TYPE_NVGRE_IPV4_TCP] = RTE_PTYPE_L2_ETHER |
1208                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1209                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4 |
1210                 RTE_PTYPE_INNER_L4_TCP,
1211         [IXGBE_PACKET_TYPE_NVGRE_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1212                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1213                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6 |
1214                 RTE_PTYPE_INNER_L4_TCP,
1215         [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1216                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1217                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1218         [IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1219                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1220                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6_EXT |
1221                 RTE_PTYPE_INNER_L4_TCP,
1222         [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_TCP] =
1223                 RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1224                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_INNER_L2_ETHER |
1225                 RTE_PTYPE_INNER_L3_IPV4,
1226         [IXGBE_PACKET_TYPE_NVGRE_IPV4_UDP] = RTE_PTYPE_L2_ETHER |
1227                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1228                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4 |
1229                 RTE_PTYPE_INNER_L4_UDP,
1230         [IXGBE_PACKET_TYPE_NVGRE_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1231                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1232                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6 |
1233                 RTE_PTYPE_INNER_L4_UDP,
1234         [IXGBE_PACKET_TYPE_NVGRE_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
1235                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1236                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6 |
1237                 RTE_PTYPE_INNER_L4_SCTP,
1238         [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1239                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1240                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1241         [IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1242                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1243                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6_EXT |
1244                 RTE_PTYPE_INNER_L4_UDP,
1245         [IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1246                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1247                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6_EXT |
1248                 RTE_PTYPE_INNER_L4_SCTP,
1249         [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_UDP] =
1250                 RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1251                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_INNER_L2_ETHER |
1252                 RTE_PTYPE_INNER_L3_IPV4,
1253         [IXGBE_PACKET_TYPE_NVGRE_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |
1254                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1255                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4 |
1256                 RTE_PTYPE_INNER_L4_SCTP,
1257         [IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1258                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1259                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4_EXT |
1260                 RTE_PTYPE_INNER_L4_SCTP,
1261         [IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1262                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1263                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4_EXT |
1264                 RTE_PTYPE_INNER_L4_TCP,
1265         [IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1266                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1267                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4_EXT |
1268                 RTE_PTYPE_INNER_L4_UDP,
1269
1270         [IXGBE_PACKET_TYPE_VXLAN] = RTE_PTYPE_L2_ETHER |
1271                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1272                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER,
1273         [IXGBE_PACKET_TYPE_VXLAN_IPV4] = RTE_PTYPE_L2_ETHER |
1274                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1275                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1276                 RTE_PTYPE_INNER_L3_IPV4,
1277         [IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT] = RTE_PTYPE_L2_ETHER |
1278                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1279                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1280                 RTE_PTYPE_INNER_L3_IPV4_EXT,
1281         [IXGBE_PACKET_TYPE_VXLAN_IPV6] = RTE_PTYPE_L2_ETHER |
1282                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1283                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1284                 RTE_PTYPE_INNER_L3_IPV6,
1285         [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |
1286                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1287                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1288                 RTE_PTYPE_INNER_L3_IPV4,
1289         [IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1290                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1291                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1292                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1293         [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1294                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1295                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1296                 RTE_PTYPE_INNER_L3_IPV4,
1297         [IXGBE_PACKET_TYPE_VXLAN_IPV4_TCP] = RTE_PTYPE_L2_ETHER |
1298                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1299                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1300                 RTE_PTYPE_INNER_L3_IPV4 | RTE_PTYPE_INNER_L4_TCP,
1301         [IXGBE_PACKET_TYPE_VXLAN_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1302                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1303                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1304                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_TCP,
1305         [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1306                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1307                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1308                 RTE_PTYPE_INNER_L3_IPV4,
1309         [IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1310                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1311                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1312                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_TCP,
1313         [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_TCP] =
1314                 RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1315                 RTE_PTYPE_L4_UDP | RTE_PTYPE_TUNNEL_VXLAN |
1316                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1317         [IXGBE_PACKET_TYPE_VXLAN_IPV4_UDP] = RTE_PTYPE_L2_ETHER |
1318                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1319                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1320                 RTE_PTYPE_INNER_L3_IPV4 | RTE_PTYPE_INNER_L4_UDP,
1321         [IXGBE_PACKET_TYPE_VXLAN_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1322                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1323                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1324                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_UDP,
1325         [IXGBE_PACKET_TYPE_VXLAN_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
1326                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1327                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1328                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_SCTP,
1329         [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1330                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1331                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1332                 RTE_PTYPE_INNER_L3_IPV4,
1333         [IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1334                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1335                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1336                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_UDP,
1337         [IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1338                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1339                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1340                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_SCTP,
1341         [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_UDP] =
1342                 RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1343                 RTE_PTYPE_L4_UDP | RTE_PTYPE_TUNNEL_VXLAN |
1344                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1345         [IXGBE_PACKET_TYPE_VXLAN_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |
1346                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1347                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1348                 RTE_PTYPE_INNER_L3_IPV4 | RTE_PTYPE_INNER_L4_SCTP,
1349         [IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1350                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1351                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1352                 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_SCTP,
1353         [IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1354                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1355                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1356                 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_TCP,
1357         [IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1358                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1359                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1360                 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_UDP,
1361 };
1362
1363 /* @note: fix ixgbe_dev_supported_ptypes_get() if any change here. */
1364 static inline uint32_t
1365 ixgbe_rxd_pkt_info_to_pkt_type(uint32_t pkt_info, uint16_t ptype_mask)
1366 {
1367
1368         if (unlikely(pkt_info & IXGBE_RXDADV_PKTTYPE_ETQF))
1369                 return RTE_PTYPE_UNKNOWN;
1370
1371         pkt_info = (pkt_info >> IXGBE_PACKET_TYPE_SHIFT) & ptype_mask;
1372
1373         /* For tunnel packet */
1374         if (pkt_info & IXGBE_PACKET_TYPE_TUNNEL_BIT) {
1375                 /* Remove the tunnel bit to save the space. */
1376                 pkt_info &= IXGBE_PACKET_TYPE_MASK_TUNNEL;
1377                 return ptype_table_tn[pkt_info];
1378         }
1379
1380         /**
1381          * For x550, if it's not tunnel,
1382          * tunnel type bit should be set to 0.
1383          * Reuse 82599's mask.
1384          */
1385         pkt_info &= IXGBE_PACKET_TYPE_MASK_82599;
1386
1387         return ptype_table[pkt_info];
1388 }
1389
1390 static inline uint64_t
1391 ixgbe_rxd_pkt_info_to_pkt_flags(uint16_t pkt_info)
1392 {
1393         static uint64_t ip_rss_types_map[16] __rte_cache_aligned = {
1394                 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
1395                 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
1396                 PKT_RX_RSS_HASH, 0, 0, 0,
1397                 0, 0, 0,  PKT_RX_FDIR,
1398         };
1399 #ifdef RTE_LIBRTE_IEEE1588
1400         static uint64_t ip_pkt_etqf_map[8] = {
1401                 0, 0, 0, PKT_RX_IEEE1588_PTP,
1402                 0, 0, 0, 0,
1403         };
1404
1405         if (likely(pkt_info & IXGBE_RXDADV_PKTTYPE_ETQF))
1406                 return ip_pkt_etqf_map[(pkt_info >> 4) & 0X07] |
1407                                 ip_rss_types_map[pkt_info & 0XF];
1408         else
1409                 return ip_rss_types_map[pkt_info & 0XF];
1410 #else
1411         return ip_rss_types_map[pkt_info & 0XF];
1412 #endif
1413 }
1414
1415 static inline uint64_t
1416 rx_desc_status_to_pkt_flags(uint32_t rx_status, uint64_t vlan_flags)
1417 {
1418         uint64_t pkt_flags;
1419
1420         /*
1421          * Check if VLAN present only.
1422          * Do not check whether L3/L4 rx checksum done by NIC or not,
1423          * That can be found from rte_eth_rxmode.hw_ip_checksum flag
1424          */
1425         pkt_flags = (rx_status & IXGBE_RXD_STAT_VP) ?  vlan_flags : 0;
1426
1427 #ifdef RTE_LIBRTE_IEEE1588
1428         if (rx_status & IXGBE_RXD_STAT_TMST)
1429                 pkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;
1430 #endif
1431         return pkt_flags;
1432 }
1433
1434 static inline uint64_t
1435 rx_desc_error_to_pkt_flags(uint32_t rx_status)
1436 {
1437         uint64_t pkt_flags;
1438
1439         /*
1440          * Bit 31: IPE, IPv4 checksum error
1441          * Bit 30: L4I, L4I integrity error
1442          */
1443         static uint64_t error_to_pkt_flags_map[4] = {
1444                 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD,
1445                 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD,
1446                 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD,
1447                 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
1448         };
1449         pkt_flags = error_to_pkt_flags_map[(rx_status >>
1450                 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
1451
1452         if ((rx_status & IXGBE_RXD_STAT_OUTERIPCS) &&
1453             (rx_status & IXGBE_RXDADV_ERR_OUTERIPER)) {
1454                 pkt_flags |= PKT_RX_EIP_CKSUM_BAD;
1455         }
1456
1457 #ifdef RTE_LIBRTE_SECURITY
1458         if (rx_status & IXGBE_RXD_STAT_SECP) {
1459                 pkt_flags |= PKT_RX_SEC_OFFLOAD;
1460                 if (rx_status & IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG)
1461                         pkt_flags |= PKT_RX_SEC_OFFLOAD_FAILED;
1462         }
1463 #endif
1464
1465         return pkt_flags;
1466 }
1467
1468 /*
1469  * LOOK_AHEAD defines how many desc statuses to check beyond the
1470  * current descriptor.
1471  * It must be a pound define for optimal performance.
1472  * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
1473  * function only works with LOOK_AHEAD=8.
1474  */
1475 #define LOOK_AHEAD 8
1476 #if (LOOK_AHEAD != 8)
1477 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
1478 #endif
1479 static inline int
1480 ixgbe_rx_scan_hw_ring(struct ixgbe_rx_queue *rxq)
1481 {
1482         volatile union ixgbe_adv_rx_desc *rxdp;
1483         struct ixgbe_rx_entry *rxep;
1484         struct rte_mbuf *mb;
1485         uint16_t pkt_len;
1486         uint64_t pkt_flags;
1487         int nb_dd;
1488         uint32_t s[LOOK_AHEAD];
1489         uint32_t pkt_info[LOOK_AHEAD];
1490         int i, j, nb_rx = 0;
1491         uint32_t status;
1492         uint64_t vlan_flags = rxq->vlan_flags;
1493
1494         /* get references to current descriptor and S/W ring entry */
1495         rxdp = &rxq->rx_ring[rxq->rx_tail];
1496         rxep = &rxq->sw_ring[rxq->rx_tail];
1497
1498         status = rxdp->wb.upper.status_error;
1499         /* check to make sure there is at least 1 packet to receive */
1500         if (!(status & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1501                 return 0;
1502
1503         /*
1504          * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
1505          * reference packets that are ready to be received.
1506          */
1507         for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
1508              i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD) {
1509                 /* Read desc statuses backwards to avoid race condition */
1510                 for (j = 0; j < LOOK_AHEAD; j++)
1511                         s[j] = rte_le_to_cpu_32(rxdp[j].wb.upper.status_error);
1512
1513                 rte_smp_rmb();
1514
1515                 /* Compute how many status bits were set */
1516                 for (nb_dd = 0; nb_dd < LOOK_AHEAD &&
1517                                 (s[nb_dd] & IXGBE_RXDADV_STAT_DD); nb_dd++)
1518                         ;
1519
1520                 for (j = 0; j < nb_dd; j++)
1521                         pkt_info[j] = rte_le_to_cpu_32(rxdp[j].wb.lower.
1522                                                        lo_dword.data);
1523
1524                 nb_rx += nb_dd;
1525
1526                 /* Translate descriptor info to mbuf format */
1527                 for (j = 0; j < nb_dd; ++j) {
1528                         mb = rxep[j].mbuf;
1529                         pkt_len = rte_le_to_cpu_16(rxdp[j].wb.upper.length) -
1530                                   rxq->crc_len;
1531                         mb->data_len = pkt_len;
1532                         mb->pkt_len = pkt_len;
1533                         mb->vlan_tci = rte_le_to_cpu_16(rxdp[j].wb.upper.vlan);
1534
1535                         /* convert descriptor fields to rte mbuf flags */
1536                         pkt_flags = rx_desc_status_to_pkt_flags(s[j],
1537                                 vlan_flags);
1538                         pkt_flags |= rx_desc_error_to_pkt_flags(s[j]);
1539                         pkt_flags |= ixgbe_rxd_pkt_info_to_pkt_flags
1540                                         ((uint16_t)pkt_info[j]);
1541                         mb->ol_flags = pkt_flags;
1542                         mb->packet_type =
1543                                 ixgbe_rxd_pkt_info_to_pkt_type
1544                                         (pkt_info[j], rxq->pkt_type_mask);
1545
1546                         if (likely(pkt_flags & PKT_RX_RSS_HASH))
1547                                 mb->hash.rss = rte_le_to_cpu_32(
1548                                     rxdp[j].wb.lower.hi_dword.rss);
1549                         else if (pkt_flags & PKT_RX_FDIR) {
1550                                 mb->hash.fdir.hash = rte_le_to_cpu_16(
1551                                     rxdp[j].wb.lower.hi_dword.csum_ip.csum) &
1552                                     IXGBE_ATR_HASH_MASK;
1553                                 mb->hash.fdir.id = rte_le_to_cpu_16(
1554                                     rxdp[j].wb.lower.hi_dword.csum_ip.ip_id);
1555                         }
1556                 }
1557
1558                 /* Move mbuf pointers from the S/W ring to the stage */
1559                 for (j = 0; j < LOOK_AHEAD; ++j) {
1560                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1561                 }
1562
1563                 /* stop if all requested packets could not be received */
1564                 if (nb_dd != LOOK_AHEAD)
1565                         break;
1566         }
1567
1568         /* clear software ring entries so we can cleanup correctly */
1569         for (i = 0; i < nb_rx; ++i) {
1570                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1571         }
1572
1573
1574         return nb_rx;
1575 }
1576
1577 static inline int
1578 ixgbe_rx_alloc_bufs(struct ixgbe_rx_queue *rxq, bool reset_mbuf)
1579 {
1580         volatile union ixgbe_adv_rx_desc *rxdp;
1581         struct ixgbe_rx_entry *rxep;
1582         struct rte_mbuf *mb;
1583         uint16_t alloc_idx;
1584         __le64 dma_addr;
1585         int diag, i;
1586
1587         /* allocate buffers in bulk directly into the S/W ring */
1588         alloc_idx = rxq->rx_free_trigger - (rxq->rx_free_thresh - 1);
1589         rxep = &rxq->sw_ring[alloc_idx];
1590         diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
1591                                     rxq->rx_free_thresh);
1592         if (unlikely(diag != 0))
1593                 return -ENOMEM;
1594
1595         rxdp = &rxq->rx_ring[alloc_idx];
1596         for (i = 0; i < rxq->rx_free_thresh; ++i) {
1597                 /* populate the static rte mbuf fields */
1598                 mb = rxep[i].mbuf;
1599                 if (reset_mbuf) {
1600                         mb->port = rxq->port_id;
1601                 }
1602
1603                 rte_mbuf_refcnt_set(mb, 1);
1604                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1605
1606                 /* populate the descriptors */
1607                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1608                 rxdp[i].read.hdr_addr = 0;
1609                 rxdp[i].read.pkt_addr = dma_addr;
1610         }
1611
1612         /* update state of internal queue structure */
1613         rxq->rx_free_trigger = rxq->rx_free_trigger + rxq->rx_free_thresh;
1614         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1615                 rxq->rx_free_trigger = rxq->rx_free_thresh - 1;
1616
1617         /* no errors */
1618         return 0;
1619 }
1620
1621 static inline uint16_t
1622 ixgbe_rx_fill_from_stage(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1623                          uint16_t nb_pkts)
1624 {
1625         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1626         int i;
1627
1628         /* how many packets are ready to return? */
1629         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1630
1631         /* copy mbuf pointers to the application's packet list */
1632         for (i = 0; i < nb_pkts; ++i)
1633                 rx_pkts[i] = stage[i];
1634
1635         /* update internal queue state */
1636         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1637         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1638
1639         return nb_pkts;
1640 }
1641
1642 static inline uint16_t
1643 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1644              uint16_t nb_pkts)
1645 {
1646         struct ixgbe_rx_queue *rxq = (struct ixgbe_rx_queue *)rx_queue;
1647         uint16_t nb_rx = 0;
1648
1649         /* Any previously recv'd pkts will be returned from the Rx stage */
1650         if (rxq->rx_nb_avail)
1651                 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1652
1653         /* Scan the H/W ring for packets to receive */
1654         nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);
1655
1656         /* update internal queue state */
1657         rxq->rx_next_avail = 0;
1658         rxq->rx_nb_avail = nb_rx;
1659         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1660
1661         /* if required, allocate new buffers to replenish descriptors */
1662         if (rxq->rx_tail > rxq->rx_free_trigger) {
1663                 uint16_t cur_free_trigger = rxq->rx_free_trigger;
1664
1665                 if (ixgbe_rx_alloc_bufs(rxq, true) != 0) {
1666                         int i, j;
1667
1668                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1669                                    "queue_id=%u", (unsigned) rxq->port_id,
1670                                    (unsigned) rxq->queue_id);
1671
1672                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1673                                 rxq->rx_free_thresh;
1674
1675                         /*
1676                          * Need to rewind any previous receives if we cannot
1677                          * allocate new buffers to replenish the old ones.
1678                          */
1679                         rxq->rx_nb_avail = 0;
1680                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1681                         for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1682                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1683
1684                         return 0;
1685                 }
1686
1687                 /* update tail pointer */
1688                 rte_wmb();
1689                 IXGBE_PCI_REG_WRITE_RELAXED(rxq->rdt_reg_addr,
1690                                             cur_free_trigger);
1691         }
1692
1693         if (rxq->rx_tail >= rxq->nb_rx_desc)
1694                 rxq->rx_tail = 0;
1695
1696         /* received any packets this loop? */
1697         if (rxq->rx_nb_avail)
1698                 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1699
1700         return 0;
1701 }
1702
1703 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1704 uint16_t
1705 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1706                            uint16_t nb_pkts)
1707 {
1708         uint16_t nb_rx;
1709
1710         if (unlikely(nb_pkts == 0))
1711                 return 0;
1712
1713         if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1714                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1715
1716         /* request is relatively large, chunk it up */
1717         nb_rx = 0;
1718         while (nb_pkts) {
1719                 uint16_t ret, n;
1720
1721                 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1722                 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1723                 nb_rx = (uint16_t)(nb_rx + ret);
1724                 nb_pkts = (uint16_t)(nb_pkts - ret);
1725                 if (ret < n)
1726                         break;
1727         }
1728
1729         return nb_rx;
1730 }
1731
1732 uint16_t
1733 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1734                 uint16_t nb_pkts)
1735 {
1736         struct ixgbe_rx_queue *rxq;
1737         volatile union ixgbe_adv_rx_desc *rx_ring;
1738         volatile union ixgbe_adv_rx_desc *rxdp;
1739         struct ixgbe_rx_entry *sw_ring;
1740         struct ixgbe_rx_entry *rxe;
1741         struct rte_mbuf *rxm;
1742         struct rte_mbuf *nmb;
1743         union ixgbe_adv_rx_desc rxd;
1744         uint64_t dma_addr;
1745         uint32_t staterr;
1746         uint32_t pkt_info;
1747         uint16_t pkt_len;
1748         uint16_t rx_id;
1749         uint16_t nb_rx;
1750         uint16_t nb_hold;
1751         uint64_t pkt_flags;
1752         uint64_t vlan_flags;
1753
1754         nb_rx = 0;
1755         nb_hold = 0;
1756         rxq = rx_queue;
1757         rx_id = rxq->rx_tail;
1758         rx_ring = rxq->rx_ring;
1759         sw_ring = rxq->sw_ring;
1760         vlan_flags = rxq->vlan_flags;
1761         while (nb_rx < nb_pkts) {
1762                 /*
1763                  * The order of operations here is important as the DD status
1764                  * bit must not be read after any other descriptor fields.
1765                  * rx_ring and rxdp are pointing to volatile data so the order
1766                  * of accesses cannot be reordered by the compiler. If they were
1767                  * not volatile, they could be reordered which could lead to
1768                  * using invalid descriptor fields when read from rxd.
1769                  */
1770                 rxdp = &rx_ring[rx_id];
1771                 staterr = rxdp->wb.upper.status_error;
1772                 if (!(staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1773                         break;
1774                 rxd = *rxdp;
1775
1776                 /*
1777                  * End of packet.
1778                  *
1779                  * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1780                  * is likely to be invalid and to be dropped by the various
1781                  * validation checks performed by the network stack.
1782                  *
1783                  * Allocate a new mbuf to replenish the RX ring descriptor.
1784                  * If the allocation fails:
1785                  *    - arrange for that RX descriptor to be the first one
1786                  *      being parsed the next time the receive function is
1787                  *      invoked [on the same queue].
1788                  *
1789                  *    - Stop parsing the RX ring and return immediately.
1790                  *
1791                  * This policy do not drop the packet received in the RX
1792                  * descriptor for which the allocation of a new mbuf failed.
1793                  * Thus, it allows that packet to be later retrieved if
1794                  * mbuf have been freed in the mean time.
1795                  * As a side effect, holding RX descriptors instead of
1796                  * systematically giving them back to the NIC may lead to
1797                  * RX ring exhaustion situations.
1798                  * However, the NIC can gracefully prevent such situations
1799                  * to happen by sending specific "back-pressure" flow control
1800                  * frames to its peer(s).
1801                  */
1802                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1803                            "ext_err_stat=0x%08x pkt_len=%u",
1804                            (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1805                            (unsigned) rx_id, (unsigned) staterr,
1806                            (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1807
1808                 nmb = rte_mbuf_raw_alloc(rxq->mb_pool);
1809                 if (nmb == NULL) {
1810                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1811                                    "queue_id=%u", (unsigned) rxq->port_id,
1812                                    (unsigned) rxq->queue_id);
1813                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1814                         break;
1815                 }
1816
1817                 nb_hold++;
1818                 rxe = &sw_ring[rx_id];
1819                 rx_id++;
1820                 if (rx_id == rxq->nb_rx_desc)
1821                         rx_id = 0;
1822
1823                 /* Prefetch next mbuf while processing current one. */
1824                 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1825
1826                 /*
1827                  * When next RX descriptor is on a cache-line boundary,
1828                  * prefetch the next 4 RX descriptors and the next 8 pointers
1829                  * to mbufs.
1830                  */
1831                 if ((rx_id & 0x3) == 0) {
1832                         rte_ixgbe_prefetch(&rx_ring[rx_id]);
1833                         rte_ixgbe_prefetch(&sw_ring[rx_id]);
1834                 }
1835
1836                 rxm = rxe->mbuf;
1837                 rxe->mbuf = nmb;
1838                 dma_addr =
1839                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1840                 rxdp->read.hdr_addr = 0;
1841                 rxdp->read.pkt_addr = dma_addr;
1842
1843                 /*
1844                  * Initialize the returned mbuf.
1845                  * 1) setup generic mbuf fields:
1846                  *    - number of segments,
1847                  *    - next segment,
1848                  *    - packet length,
1849                  *    - RX port identifier.
1850                  * 2) integrate hardware offload data, if any:
1851                  *    - RSS flag & hash,
1852                  *    - IP checksum flag,
1853                  *    - VLAN TCI, if any,
1854                  *    - error flags.
1855                  */
1856                 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1857                                       rxq->crc_len);
1858                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1859                 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
1860                 rxm->nb_segs = 1;
1861                 rxm->next = NULL;
1862                 rxm->pkt_len = pkt_len;
1863                 rxm->data_len = pkt_len;
1864                 rxm->port = rxq->port_id;
1865
1866                 pkt_info = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1867                 /* Only valid if PKT_RX_VLAN set in pkt_flags */
1868                 rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1869
1870                 pkt_flags = rx_desc_status_to_pkt_flags(staterr, vlan_flags);
1871                 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
1872                 pkt_flags = pkt_flags |
1873                         ixgbe_rxd_pkt_info_to_pkt_flags((uint16_t)pkt_info);
1874                 rxm->ol_flags = pkt_flags;
1875                 rxm->packet_type =
1876                         ixgbe_rxd_pkt_info_to_pkt_type(pkt_info,
1877                                                        rxq->pkt_type_mask);
1878
1879                 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1880                         rxm->hash.rss = rte_le_to_cpu_32(
1881                                                 rxd.wb.lower.hi_dword.rss);
1882                 else if (pkt_flags & PKT_RX_FDIR) {
1883                         rxm->hash.fdir.hash = rte_le_to_cpu_16(
1884                                         rxd.wb.lower.hi_dword.csum_ip.csum) &
1885                                         IXGBE_ATR_HASH_MASK;
1886                         rxm->hash.fdir.id = rte_le_to_cpu_16(
1887                                         rxd.wb.lower.hi_dword.csum_ip.ip_id);
1888                 }
1889                 /*
1890                  * Store the mbuf address into the next entry of the array
1891                  * of returned packets.
1892                  */
1893                 rx_pkts[nb_rx++] = rxm;
1894         }
1895         rxq->rx_tail = rx_id;
1896
1897         /*
1898          * If the number of free RX descriptors is greater than the RX free
1899          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1900          * register.
1901          * Update the RDT with the value of the last processed RX descriptor
1902          * minus 1, to guarantee that the RDT register is never equal to the
1903          * RDH register, which creates a "full" ring situtation from the
1904          * hardware point of view...
1905          */
1906         nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1907         if (nb_hold > rxq->rx_free_thresh) {
1908                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1909                            "nb_hold=%u nb_rx=%u",
1910                            (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1911                            (unsigned) rx_id, (unsigned) nb_hold,
1912                            (unsigned) nb_rx);
1913                 rx_id = (uint16_t) ((rx_id == 0) ?
1914                                      (rxq->nb_rx_desc - 1) : (rx_id - 1));
1915                 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1916                 nb_hold = 0;
1917         }
1918         rxq->nb_rx_hold = nb_hold;
1919         return nb_rx;
1920 }
1921
1922 /**
1923  * Detect an RSC descriptor.
1924  */
1925 static inline uint32_t
1926 ixgbe_rsc_count(union ixgbe_adv_rx_desc *rx)
1927 {
1928         return (rte_le_to_cpu_32(rx->wb.lower.lo_dword.data) &
1929                 IXGBE_RXDADV_RSCCNT_MASK) >> IXGBE_RXDADV_RSCCNT_SHIFT;
1930 }
1931
1932 /**
1933  * ixgbe_fill_cluster_head_buf - fill the first mbuf of the returned packet
1934  *
1935  * Fill the following info in the HEAD buffer of the Rx cluster:
1936  *    - RX port identifier
1937  *    - hardware offload data, if any:
1938  *      - RSS flag & hash
1939  *      - IP checksum flag
1940  *      - VLAN TCI, if any
1941  *      - error flags
1942  * @head HEAD of the packet cluster
1943  * @desc HW descriptor to get data from
1944  * @rxq Pointer to the Rx queue
1945  */
1946 static inline void
1947 ixgbe_fill_cluster_head_buf(
1948         struct rte_mbuf *head,
1949         union ixgbe_adv_rx_desc *desc,
1950         struct ixgbe_rx_queue *rxq,
1951         uint32_t staterr)
1952 {
1953         uint32_t pkt_info;
1954         uint64_t pkt_flags;
1955
1956         head->port = rxq->port_id;
1957
1958         /* The vlan_tci field is only valid when PKT_RX_VLAN is
1959          * set in the pkt_flags field.
1960          */
1961         head->vlan_tci = rte_le_to_cpu_16(desc->wb.upper.vlan);
1962         pkt_info = rte_le_to_cpu_32(desc->wb.lower.lo_dword.data);
1963         pkt_flags = rx_desc_status_to_pkt_flags(staterr, rxq->vlan_flags);
1964         pkt_flags |= rx_desc_error_to_pkt_flags(staterr);
1965         pkt_flags |= ixgbe_rxd_pkt_info_to_pkt_flags((uint16_t)pkt_info);
1966         head->ol_flags = pkt_flags;
1967         head->packet_type =
1968                 ixgbe_rxd_pkt_info_to_pkt_type(pkt_info, rxq->pkt_type_mask);
1969
1970         if (likely(pkt_flags & PKT_RX_RSS_HASH))
1971                 head->hash.rss = rte_le_to_cpu_32(desc->wb.lower.hi_dword.rss);
1972         else if (pkt_flags & PKT_RX_FDIR) {
1973                 head->hash.fdir.hash =
1974                         rte_le_to_cpu_16(desc->wb.lower.hi_dword.csum_ip.csum)
1975                                                           & IXGBE_ATR_HASH_MASK;
1976                 head->hash.fdir.id =
1977                         rte_le_to_cpu_16(desc->wb.lower.hi_dword.csum_ip.ip_id);
1978         }
1979 }
1980
1981 /**
1982  * ixgbe_recv_pkts_lro - receive handler for and LRO case.
1983  *
1984  * @rx_queue Rx queue handle
1985  * @rx_pkts table of received packets
1986  * @nb_pkts size of rx_pkts table
1987  * @bulk_alloc if TRUE bulk allocation is used for a HW ring refilling
1988  *
1989  * Handles the Rx HW ring completions when RSC feature is configured. Uses an
1990  * additional ring of ixgbe_rsc_entry's that will hold the relevant RSC info.
1991  *
1992  * We use the same logic as in Linux and in FreeBSD ixgbe drivers:
1993  * 1) When non-EOP RSC completion arrives:
1994  *    a) Update the HEAD of the current RSC aggregation cluster with the new
1995  *       segment's data length.
1996  *    b) Set the "next" pointer of the current segment to point to the segment
1997  *       at the NEXTP index.
1998  *    c) Pass the HEAD of RSC aggregation cluster on to the next NEXTP entry
1999  *       in the sw_rsc_ring.
2000  * 2) When EOP arrives we just update the cluster's total length and offload
2001  *    flags and deliver the cluster up to the upper layers. In our case - put it
2002  *    in the rx_pkts table.
2003  *
2004  * Returns the number of received packets/clusters (according to the "bulk
2005  * receive" interface).
2006  */
2007 static inline uint16_t
2008 ixgbe_recv_pkts_lro(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts,
2009                     bool bulk_alloc)
2010 {
2011         struct ixgbe_rx_queue *rxq = rx_queue;
2012         volatile union ixgbe_adv_rx_desc *rx_ring = rxq->rx_ring;
2013         struct ixgbe_rx_entry *sw_ring = rxq->sw_ring;
2014         struct ixgbe_scattered_rx_entry *sw_sc_ring = rxq->sw_sc_ring;
2015         uint16_t rx_id = rxq->rx_tail;
2016         uint16_t nb_rx = 0;
2017         uint16_t nb_hold = rxq->nb_rx_hold;
2018         uint16_t prev_id = rxq->rx_tail;
2019
2020         while (nb_rx < nb_pkts) {
2021                 bool eop;
2022                 struct ixgbe_rx_entry *rxe;
2023                 struct ixgbe_scattered_rx_entry *sc_entry;
2024                 struct ixgbe_scattered_rx_entry *next_sc_entry;
2025                 struct ixgbe_rx_entry *next_rxe = NULL;
2026                 struct rte_mbuf *first_seg;
2027                 struct rte_mbuf *rxm;
2028                 struct rte_mbuf *nmb;
2029                 union ixgbe_adv_rx_desc rxd;
2030                 uint16_t data_len;
2031                 uint16_t next_id;
2032                 volatile union ixgbe_adv_rx_desc *rxdp;
2033                 uint32_t staterr;
2034
2035 next_desc:
2036                 /*
2037                  * The code in this whole file uses the volatile pointer to
2038                  * ensure the read ordering of the status and the rest of the
2039                  * descriptor fields (on the compiler level only!!!). This is so
2040                  * UGLY - why not to just use the compiler barrier instead? DPDK
2041                  * even has the rte_compiler_barrier() for that.
2042                  *
2043                  * But most importantly this is just wrong because this doesn't
2044                  * ensure memory ordering in a general case at all. For
2045                  * instance, DPDK is supposed to work on Power CPUs where
2046                  * compiler barrier may just not be enough!
2047                  *
2048                  * I tried to write only this function properly to have a
2049                  * starting point (as a part of an LRO/RSC series) but the
2050                  * compiler cursed at me when I tried to cast away the
2051                  * "volatile" from rx_ring (yes, it's volatile too!!!). So, I'm
2052                  * keeping it the way it is for now.
2053                  *
2054                  * The code in this file is broken in so many other places and
2055                  * will just not work on a big endian CPU anyway therefore the
2056                  * lines below will have to be revisited together with the rest
2057                  * of the ixgbe PMD.
2058                  *
2059                  * TODO:
2060                  *    - Get rid of "volatile" crap and let the compiler do its
2061                  *      job.
2062                  *    - Use the proper memory barrier (rte_rmb()) to ensure the
2063                  *      memory ordering below.
2064                  */
2065                 rxdp = &rx_ring[rx_id];
2066                 staterr = rte_le_to_cpu_32(rxdp->wb.upper.status_error);
2067
2068                 if (!(staterr & IXGBE_RXDADV_STAT_DD))
2069                         break;
2070
2071                 rxd = *rxdp;
2072
2073                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
2074                                   "staterr=0x%x data_len=%u",
2075                            rxq->port_id, rxq->queue_id, rx_id, staterr,
2076                            rte_le_to_cpu_16(rxd.wb.upper.length));
2077
2078                 if (!bulk_alloc) {
2079                         nmb = rte_mbuf_raw_alloc(rxq->mb_pool);
2080                         if (nmb == NULL) {
2081                                 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed "
2082                                                   "port_id=%u queue_id=%u",
2083                                            rxq->port_id, rxq->queue_id);
2084
2085                                 rte_eth_devices[rxq->port_id].data->
2086                                                         rx_mbuf_alloc_failed++;
2087                                 break;
2088                         }
2089                 } else if (nb_hold > rxq->rx_free_thresh) {
2090                         uint16_t next_rdt = rxq->rx_free_trigger;
2091
2092                         if (!ixgbe_rx_alloc_bufs(rxq, false)) {
2093                                 rte_wmb();
2094                                 IXGBE_PCI_REG_WRITE_RELAXED(rxq->rdt_reg_addr,
2095                                                             next_rdt);
2096                                 nb_hold -= rxq->rx_free_thresh;
2097                         } else {
2098                                 PMD_RX_LOG(DEBUG, "RX bulk alloc failed "
2099                                                   "port_id=%u queue_id=%u",
2100                                            rxq->port_id, rxq->queue_id);
2101
2102                                 rte_eth_devices[rxq->port_id].data->
2103                                                         rx_mbuf_alloc_failed++;
2104                                 break;
2105                         }
2106                 }
2107
2108                 nb_hold++;
2109                 rxe = &sw_ring[rx_id];
2110                 eop = staterr & IXGBE_RXDADV_STAT_EOP;
2111
2112                 next_id = rx_id + 1;
2113                 if (next_id == rxq->nb_rx_desc)
2114                         next_id = 0;
2115
2116                 /* Prefetch next mbuf while processing current one. */
2117                 rte_ixgbe_prefetch(sw_ring[next_id].mbuf);
2118
2119                 /*
2120                  * When next RX descriptor is on a cache-line boundary,
2121                  * prefetch the next 4 RX descriptors and the next 4 pointers
2122                  * to mbufs.
2123                  */
2124                 if ((next_id & 0x3) == 0) {
2125                         rte_ixgbe_prefetch(&rx_ring[next_id]);
2126                         rte_ixgbe_prefetch(&sw_ring[next_id]);
2127                 }
2128
2129                 rxm = rxe->mbuf;
2130
2131                 if (!bulk_alloc) {
2132                         __le64 dma =
2133                           rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
2134                         /*
2135                          * Update RX descriptor with the physical address of the
2136                          * new data buffer of the new allocated mbuf.
2137                          */
2138                         rxe->mbuf = nmb;
2139
2140                         rxm->data_off = RTE_PKTMBUF_HEADROOM;
2141                         rxdp->read.hdr_addr = 0;
2142                         rxdp->read.pkt_addr = dma;
2143                 } else
2144                         rxe->mbuf = NULL;
2145
2146                 /*
2147                  * Set data length & data buffer address of mbuf.
2148                  */
2149                 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
2150                 rxm->data_len = data_len;
2151
2152                 if (!eop) {
2153                         uint16_t nextp_id;
2154                         /*
2155                          * Get next descriptor index:
2156                          *  - For RSC it's in the NEXTP field.
2157                          *  - For a scattered packet - it's just a following
2158                          *    descriptor.
2159                          */
2160                         if (ixgbe_rsc_count(&rxd))
2161                                 nextp_id =
2162                                         (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
2163                                                        IXGBE_RXDADV_NEXTP_SHIFT;
2164                         else
2165                                 nextp_id = next_id;
2166
2167                         next_sc_entry = &sw_sc_ring[nextp_id];
2168                         next_rxe = &sw_ring[nextp_id];
2169                         rte_ixgbe_prefetch(next_rxe);
2170                 }
2171
2172                 sc_entry = &sw_sc_ring[rx_id];
2173                 first_seg = sc_entry->fbuf;
2174                 sc_entry->fbuf = NULL;
2175
2176                 /*
2177                  * If this is the first buffer of the received packet,
2178                  * set the pointer to the first mbuf of the packet and
2179                  * initialize its context.
2180                  * Otherwise, update the total length and the number of segments
2181                  * of the current scattered packet, and update the pointer to
2182                  * the last mbuf of the current packet.
2183                  */
2184                 if (first_seg == NULL) {
2185                         first_seg = rxm;
2186                         first_seg->pkt_len = data_len;
2187                         first_seg->nb_segs = 1;
2188                 } else {
2189                         first_seg->pkt_len += data_len;
2190                         first_seg->nb_segs++;
2191                 }
2192
2193                 prev_id = rx_id;
2194                 rx_id = next_id;
2195
2196                 /*
2197                  * If this is not the last buffer of the received packet, update
2198                  * the pointer to the first mbuf at the NEXTP entry in the
2199                  * sw_sc_ring and continue to parse the RX ring.
2200                  */
2201                 if (!eop && next_rxe) {
2202                         rxm->next = next_rxe->mbuf;
2203                         next_sc_entry->fbuf = first_seg;
2204                         goto next_desc;
2205                 }
2206
2207                 /* Initialize the first mbuf of the returned packet */
2208                 ixgbe_fill_cluster_head_buf(first_seg, &rxd, rxq, staterr);
2209
2210                 /*
2211                  * Deal with the case, when HW CRC srip is disabled.
2212                  * That can't happen when LRO is enabled, but still could
2213                  * happen for scattered RX mode.
2214                  */
2215                 first_seg->pkt_len -= rxq->crc_len;
2216                 if (unlikely(rxm->data_len <= rxq->crc_len)) {
2217                         struct rte_mbuf *lp;
2218
2219                         for (lp = first_seg; lp->next != rxm; lp = lp->next)
2220                                 ;
2221
2222                         first_seg->nb_segs--;
2223                         lp->data_len -= rxq->crc_len - rxm->data_len;
2224                         lp->next = NULL;
2225                         rte_pktmbuf_free_seg(rxm);
2226                 } else
2227                         rxm->data_len -= rxq->crc_len;
2228
2229                 /* Prefetch data of first segment, if configured to do so. */
2230                 rte_packet_prefetch((char *)first_seg->buf_addr +
2231                         first_seg->data_off);
2232
2233                 /*
2234                  * Store the mbuf address into the next entry of the array
2235                  * of returned packets.
2236                  */
2237                 rx_pkts[nb_rx++] = first_seg;
2238         }
2239
2240         /*
2241          * Record index of the next RX descriptor to probe.
2242          */
2243         rxq->rx_tail = rx_id;
2244
2245         /*
2246          * If the number of free RX descriptors is greater than the RX free
2247          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
2248          * register.
2249          * Update the RDT with the value of the last processed RX descriptor
2250          * minus 1, to guarantee that the RDT register is never equal to the
2251          * RDH register, which creates a "full" ring situtation from the
2252          * hardware point of view...
2253          */
2254         if (!bulk_alloc && nb_hold > rxq->rx_free_thresh) {
2255                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
2256                            "nb_hold=%u nb_rx=%u",
2257                            rxq->port_id, rxq->queue_id, rx_id, nb_hold, nb_rx);
2258
2259                 rte_wmb();
2260                 IXGBE_PCI_REG_WRITE_RELAXED(rxq->rdt_reg_addr, prev_id);
2261                 nb_hold = 0;
2262         }
2263
2264         rxq->nb_rx_hold = nb_hold;
2265         return nb_rx;
2266 }
2267
2268 uint16_t
2269 ixgbe_recv_pkts_lro_single_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
2270                                  uint16_t nb_pkts)
2271 {
2272         return ixgbe_recv_pkts_lro(rx_queue, rx_pkts, nb_pkts, false);
2273 }
2274
2275 uint16_t
2276 ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
2277                                uint16_t nb_pkts)
2278 {
2279         return ixgbe_recv_pkts_lro(rx_queue, rx_pkts, nb_pkts, true);
2280 }
2281
2282 /*********************************************************************
2283  *
2284  *  Queue management functions
2285  *
2286  **********************************************************************/
2287
2288 static void __attribute__((cold))
2289 ixgbe_tx_queue_release_mbufs(struct ixgbe_tx_queue *txq)
2290 {
2291         unsigned i;
2292
2293         if (txq->sw_ring != NULL) {
2294                 for (i = 0; i < txq->nb_tx_desc; i++) {
2295                         if (txq->sw_ring[i].mbuf != NULL) {
2296                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2297                                 txq->sw_ring[i].mbuf = NULL;
2298                         }
2299                 }
2300         }
2301 }
2302
2303 static void __attribute__((cold))
2304 ixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)
2305 {
2306         if (txq != NULL &&
2307             txq->sw_ring != NULL)
2308                 rte_free(txq->sw_ring);
2309 }
2310
2311 static void __attribute__((cold))
2312 ixgbe_tx_queue_release(struct ixgbe_tx_queue *txq)
2313 {
2314         if (txq != NULL && txq->ops != NULL) {
2315                 txq->ops->release_mbufs(txq);
2316                 txq->ops->free_swring(txq);
2317                 rte_free(txq);
2318         }
2319 }
2320
2321 void __attribute__((cold))
2322 ixgbe_dev_tx_queue_release(void *txq)
2323 {
2324         ixgbe_tx_queue_release(txq);
2325 }
2326
2327 /* (Re)set dynamic ixgbe_tx_queue fields to defaults */
2328 static void __attribute__((cold))
2329 ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)
2330 {
2331         static const union ixgbe_adv_tx_desc zeroed_desc = {{0}};
2332         struct ixgbe_tx_entry *txe = txq->sw_ring;
2333         uint16_t prev, i;
2334
2335         /* Zero out HW ring memory */
2336         for (i = 0; i < txq->nb_tx_desc; i++) {
2337                 txq->tx_ring[i] = zeroed_desc;
2338         }
2339
2340         /* Initialize SW ring entries */
2341         prev = (uint16_t) (txq->nb_tx_desc - 1);
2342         for (i = 0; i < txq->nb_tx_desc; i++) {
2343                 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
2344
2345                 txd->wb.status = rte_cpu_to_le_32(IXGBE_TXD_STAT_DD);
2346                 txe[i].mbuf = NULL;
2347                 txe[i].last_id = i;
2348                 txe[prev].next_id = i;
2349                 prev = i;
2350         }
2351
2352         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2353         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2354
2355         txq->tx_tail = 0;
2356         txq->nb_tx_used = 0;
2357         /*
2358          * Always allow 1 descriptor to be un-allocated to avoid
2359          * a H/W race condition
2360          */
2361         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2362         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2363         txq->ctx_curr = 0;
2364         memset((void *)&txq->ctx_cache, 0,
2365                 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
2366 }
2367
2368 static const struct ixgbe_txq_ops def_txq_ops = {
2369         .release_mbufs = ixgbe_tx_queue_release_mbufs,
2370         .free_swring = ixgbe_tx_free_swring,
2371         .reset = ixgbe_reset_tx_queue,
2372 };
2373
2374 /* Takes an ethdev and a queue and sets up the tx function to be used based on
2375  * the queue parameters. Used in tx_queue_setup by primary process and then
2376  * in dev_init by secondary process when attaching to an existing ethdev.
2377  */
2378 void __attribute__((cold))
2379 ixgbe_set_tx_function(struct rte_eth_dev *dev, struct ixgbe_tx_queue *txq)
2380 {
2381         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
2382         if ((txq->offloads == 0) &&
2383 #ifdef RTE_LIBRTE_SECURITY
2384                         !(txq->using_ipsec) &&
2385 #endif
2386                         (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
2387                 PMD_INIT_LOG(DEBUG, "Using simple tx code path");
2388                 dev->tx_pkt_prepare = NULL;
2389 #ifdef RTE_IXGBE_INC_VECTOR
2390                 if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
2391                                 (rte_eal_process_type() != RTE_PROC_PRIMARY ||
2392                                         ixgbe_txq_vec_setup(txq) == 0)) {
2393                         PMD_INIT_LOG(DEBUG, "Vector tx enabled.");
2394                         dev->tx_pkt_burst = ixgbe_xmit_pkts_vec;
2395                 } else
2396 #endif
2397                 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
2398         } else {
2399                 PMD_INIT_LOG(DEBUG, "Using full-featured tx code path");
2400                 PMD_INIT_LOG(DEBUG,
2401                                 " - offloads = 0x%" PRIx64,
2402                                 txq->offloads);
2403                 PMD_INIT_LOG(DEBUG,
2404                                 " - tx_rs_thresh = %lu " "[RTE_PMD_IXGBE_TX_MAX_BURST=%lu]",
2405                                 (unsigned long)txq->tx_rs_thresh,
2406                                 (unsigned long)RTE_PMD_IXGBE_TX_MAX_BURST);
2407                 dev->tx_pkt_burst = ixgbe_xmit_pkts;
2408                 dev->tx_pkt_prepare = ixgbe_prep_pkts;
2409         }
2410 }
2411
2412 uint64_t
2413 ixgbe_get_tx_queue_offloads(struct rte_eth_dev *dev)
2414 {
2415         RTE_SET_USED(dev);
2416
2417         return 0;
2418 }
2419
2420 uint64_t
2421 ixgbe_get_tx_port_offloads(struct rte_eth_dev *dev)
2422 {
2423         uint64_t tx_offload_capa;
2424         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2425
2426         tx_offload_capa =
2427                 DEV_TX_OFFLOAD_VLAN_INSERT |
2428                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2429                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2430                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2431                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2432                 DEV_TX_OFFLOAD_TCP_TSO     |
2433                 DEV_TX_OFFLOAD_MULTI_SEGS;
2434
2435         if (hw->mac.type == ixgbe_mac_82599EB ||
2436             hw->mac.type == ixgbe_mac_X540)
2437                 tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
2438
2439         if (hw->mac.type == ixgbe_mac_X550 ||
2440             hw->mac.type == ixgbe_mac_X550EM_x ||
2441             hw->mac.type == ixgbe_mac_X550EM_a)
2442                 tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
2443
2444 #ifdef RTE_LIBRTE_SECURITY
2445         if (dev->security_ctx)
2446                 tx_offload_capa |= DEV_TX_OFFLOAD_SECURITY;
2447 #endif
2448         return tx_offload_capa;
2449 }
2450
2451 int __attribute__((cold))
2452 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
2453                          uint16_t queue_idx,
2454                          uint16_t nb_desc,
2455                          unsigned int socket_id,
2456                          const struct rte_eth_txconf *tx_conf)
2457 {
2458         const struct rte_memzone *tz;
2459         struct ixgbe_tx_queue *txq;
2460         struct ixgbe_hw     *hw;
2461         uint16_t tx_rs_thresh, tx_free_thresh;
2462         uint64_t offloads;
2463
2464         PMD_INIT_FUNC_TRACE();
2465         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2466
2467         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
2468
2469         /*
2470          * Validate number of transmit descriptors.
2471          * It must not exceed hardware maximum, and must be multiple
2472          * of IXGBE_ALIGN.
2473          */
2474         if (nb_desc % IXGBE_TXD_ALIGN != 0 ||
2475                         (nb_desc > IXGBE_MAX_RING_DESC) ||
2476                         (nb_desc < IXGBE_MIN_RING_DESC)) {
2477                 return -EINVAL;
2478         }
2479
2480         /*
2481          * The following two parameters control the setting of the RS bit on
2482          * transmit descriptors.
2483          * TX descriptors will have their RS bit set after txq->tx_rs_thresh
2484          * descriptors have been used.
2485          * The TX descriptor ring will be cleaned after txq->tx_free_thresh
2486          * descriptors are used or if the number of descriptors required
2487          * to transmit a packet is greater than the number of free TX
2488          * descriptors.
2489          * The following constraints must be satisfied:
2490          *  tx_rs_thresh must be greater than 0.
2491          *  tx_rs_thresh must be less than the size of the ring minus 2.
2492          *  tx_rs_thresh must be less than or equal to tx_free_thresh.
2493          *  tx_rs_thresh must be a divisor of the ring size.
2494          *  tx_free_thresh must be greater than 0.
2495          *  tx_free_thresh must be less than the size of the ring minus 3.
2496          * One descriptor in the TX ring is used as a sentinel to avoid a
2497          * H/W race condition, hence the maximum threshold constraints.
2498          * When set to zero use default values.
2499          */
2500         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2501                         tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2502         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2503                         tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2504         if (tx_rs_thresh >= (nb_desc - 2)) {
2505                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the number "
2506                         "of TX descriptors minus 2. (tx_rs_thresh=%u "
2507                         "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2508                         (int)dev->data->port_id, (int)queue_idx);
2509                 return -(EINVAL);
2510         }
2511         if (tx_rs_thresh > DEFAULT_TX_RS_THRESH) {
2512                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less or equal than %u. "
2513                         "(tx_rs_thresh=%u port=%d queue=%d)",
2514                         DEFAULT_TX_RS_THRESH, (unsigned int)tx_rs_thresh,
2515                         (int)dev->data->port_id, (int)queue_idx);
2516                 return -(EINVAL);
2517         }
2518         if (tx_free_thresh >= (nb_desc - 3)) {
2519                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2520                              "tx_free_thresh must be less than the number of "
2521                              "TX descriptors minus 3. (tx_free_thresh=%u "
2522                              "port=%d queue=%d)",
2523                              (unsigned int)tx_free_thresh,
2524                              (int)dev->data->port_id, (int)queue_idx);
2525                 return -(EINVAL);
2526         }
2527         if (tx_rs_thresh > tx_free_thresh) {
2528                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or equal to "
2529                              "tx_free_thresh. (tx_free_thresh=%u "
2530                              "tx_rs_thresh=%u port=%d queue=%d)",
2531                              (unsigned int)tx_free_thresh,
2532                              (unsigned int)tx_rs_thresh,
2533                              (int)dev->data->port_id,
2534                              (int)queue_idx);
2535                 return -(EINVAL);
2536         }
2537         if ((nb_desc % tx_rs_thresh) != 0) {
2538                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2539                              "number of TX descriptors. (tx_rs_thresh=%u "
2540                              "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2541                              (int)dev->data->port_id, (int)queue_idx);
2542                 return -(EINVAL);
2543         }
2544
2545         /*
2546          * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
2547          * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
2548          * by the NIC and all descriptors are written back after the NIC
2549          * accumulates WTHRESH descriptors.
2550          */
2551         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2552                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2553                              "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
2554                              "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2555                              (int)dev->data->port_id, (int)queue_idx);
2556                 return -(EINVAL);
2557         }
2558
2559         /* Free memory prior to re-allocation if needed... */
2560         if (dev->data->tx_queues[queue_idx] != NULL) {
2561                 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
2562                 dev->data->tx_queues[queue_idx] = NULL;
2563         }
2564
2565         /* First allocate the tx queue data structure */
2566         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct ixgbe_tx_queue),
2567                                  RTE_CACHE_LINE_SIZE, socket_id);
2568         if (txq == NULL)
2569                 return -ENOMEM;
2570
2571         /*
2572          * Allocate TX ring hardware descriptors. A memzone large enough to
2573          * handle the maximum ring size is allocated in order to allow for
2574          * resizing in later calls to the queue setup function.
2575          */
2576         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2577                         sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
2578                         IXGBE_ALIGN, socket_id);
2579         if (tz == NULL) {
2580                 ixgbe_tx_queue_release(txq);
2581                 return -ENOMEM;
2582         }
2583
2584         txq->nb_tx_desc = nb_desc;
2585         txq->tx_rs_thresh = tx_rs_thresh;
2586         txq->tx_free_thresh = tx_free_thresh;
2587         txq->pthresh = tx_conf->tx_thresh.pthresh;
2588         txq->hthresh = tx_conf->tx_thresh.hthresh;
2589         txq->wthresh = tx_conf->tx_thresh.wthresh;
2590         txq->queue_id = queue_idx;
2591         txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2592                 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2593         txq->port_id = dev->data->port_id;
2594         txq->offloads = offloads;
2595         txq->ops = &def_txq_ops;
2596         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2597 #ifdef RTE_LIBRTE_SECURITY
2598         txq->using_ipsec = !!(dev->data->dev_conf.txmode.offloads &
2599                         DEV_TX_OFFLOAD_SECURITY);
2600 #endif
2601
2602         /*
2603          * Modification to set VFTDT for virtual function if vf is detected
2604          */
2605         if (hw->mac.type == ixgbe_mac_82599_vf ||
2606             hw->mac.type == ixgbe_mac_X540_vf ||
2607             hw->mac.type == ixgbe_mac_X550_vf ||
2608             hw->mac.type == ixgbe_mac_X550EM_x_vf ||
2609             hw->mac.type == ixgbe_mac_X550EM_a_vf)
2610                 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
2611         else
2612                 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));
2613
2614         txq->tx_ring_phys_addr = tz->iova;
2615         txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
2616
2617         /* Allocate software ring */
2618         txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
2619                                 sizeof(struct ixgbe_tx_entry) * nb_desc,
2620                                 RTE_CACHE_LINE_SIZE, socket_id);
2621         if (txq->sw_ring == NULL) {
2622                 ixgbe_tx_queue_release(txq);
2623                 return -ENOMEM;
2624         }
2625         PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
2626                      txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
2627
2628         /* set up vector or scalar TX function as appropriate */
2629         ixgbe_set_tx_function(dev, txq);
2630
2631         txq->ops->reset(txq);
2632
2633         dev->data->tx_queues[queue_idx] = txq;
2634
2635
2636         return 0;
2637 }
2638
2639 /**
2640  * ixgbe_free_sc_cluster - free the not-yet-completed scattered cluster
2641  *
2642  * The "next" pointer of the last segment of (not-yet-completed) RSC clusters
2643  * in the sw_rsc_ring is not set to NULL but rather points to the next
2644  * mbuf of this RSC aggregation (that has not been completed yet and still
2645  * resides on the HW ring). So, instead of calling for rte_pktmbuf_free() we
2646  * will just free first "nb_segs" segments of the cluster explicitly by calling
2647  * an rte_pktmbuf_free_seg().
2648  *
2649  * @m scattered cluster head
2650  */
2651 static void __attribute__((cold))
2652 ixgbe_free_sc_cluster(struct rte_mbuf *m)
2653 {
2654         uint16_t i, nb_segs = m->nb_segs;
2655         struct rte_mbuf *next_seg;
2656
2657         for (i = 0; i < nb_segs; i++) {
2658                 next_seg = m->next;
2659                 rte_pktmbuf_free_seg(m);
2660                 m = next_seg;
2661         }
2662 }
2663
2664 static void __attribute__((cold))
2665 ixgbe_rx_queue_release_mbufs(struct ixgbe_rx_queue *rxq)
2666 {
2667         unsigned i;
2668
2669 #ifdef RTE_IXGBE_INC_VECTOR
2670         /* SSE Vector driver has a different way of releasing mbufs. */
2671         if (rxq->rx_using_sse) {
2672                 ixgbe_rx_queue_release_mbufs_vec(rxq);
2673                 return;
2674         }
2675 #endif
2676
2677         if (rxq->sw_ring != NULL) {
2678                 for (i = 0; i < rxq->nb_rx_desc; i++) {
2679                         if (rxq->sw_ring[i].mbuf != NULL) {
2680                                 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2681                                 rxq->sw_ring[i].mbuf = NULL;
2682                         }
2683                 }
2684                 if (rxq->rx_nb_avail) {
2685                         for (i = 0; i < rxq->rx_nb_avail; ++i) {
2686                                 struct rte_mbuf *mb;
2687
2688                                 mb = rxq->rx_stage[rxq->rx_next_avail + i];
2689                                 rte_pktmbuf_free_seg(mb);
2690                         }
2691                         rxq->rx_nb_avail = 0;
2692                 }
2693         }
2694
2695         if (rxq->sw_sc_ring)
2696                 for (i = 0; i < rxq->nb_rx_desc; i++)
2697                         if (rxq->sw_sc_ring[i].fbuf) {
2698                                 ixgbe_free_sc_cluster(rxq->sw_sc_ring[i].fbuf);
2699                                 rxq->sw_sc_ring[i].fbuf = NULL;
2700                         }
2701 }
2702
2703 static void __attribute__((cold))
2704 ixgbe_rx_queue_release(struct ixgbe_rx_queue *rxq)
2705 {
2706         if (rxq != NULL) {
2707                 ixgbe_rx_queue_release_mbufs(rxq);
2708                 rte_free(rxq->sw_ring);
2709                 rte_free(rxq->sw_sc_ring);
2710                 rte_free(rxq);
2711         }
2712 }
2713
2714 void __attribute__((cold))
2715 ixgbe_dev_rx_queue_release(void *rxq)
2716 {
2717         ixgbe_rx_queue_release(rxq);
2718 }
2719
2720 /*
2721  * Check if Rx Burst Bulk Alloc function can be used.
2722  * Return
2723  *        0: the preconditions are satisfied and the bulk allocation function
2724  *           can be used.
2725  *  -EINVAL: the preconditions are NOT satisfied and the default Rx burst
2726  *           function must be used.
2727  */
2728 static inline int __attribute__((cold))
2729 check_rx_burst_bulk_alloc_preconditions(struct ixgbe_rx_queue *rxq)
2730 {
2731         int ret = 0;
2732
2733         /*
2734          * Make sure the following pre-conditions are satisfied:
2735          *   rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
2736          *   rxq->rx_free_thresh < rxq->nb_rx_desc
2737          *   (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
2738          * Scattered packets are not supported.  This should be checked
2739          * outside of this function.
2740          */
2741         if (!(rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST)) {
2742                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2743                              "rxq->rx_free_thresh=%d, "
2744                              "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2745                              rxq->rx_free_thresh, RTE_PMD_IXGBE_RX_MAX_BURST);
2746                 ret = -EINVAL;
2747         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
2748                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2749                              "rxq->rx_free_thresh=%d, "
2750                              "rxq->nb_rx_desc=%d",
2751                              rxq->rx_free_thresh, rxq->nb_rx_desc);
2752                 ret = -EINVAL;
2753         } else if (!((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0)) {
2754                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2755                              "rxq->nb_rx_desc=%d, "
2756                              "rxq->rx_free_thresh=%d",
2757                              rxq->nb_rx_desc, rxq->rx_free_thresh);
2758                 ret = -EINVAL;
2759         }
2760
2761         return ret;
2762 }
2763
2764 /* Reset dynamic ixgbe_rx_queue fields back to defaults */
2765 static void __attribute__((cold))
2766 ixgbe_reset_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_rx_queue *rxq)
2767 {
2768         static const union ixgbe_adv_rx_desc zeroed_desc = {{0}};
2769         unsigned i;
2770         uint16_t len = rxq->nb_rx_desc;
2771
2772         /*
2773          * By default, the Rx queue setup function allocates enough memory for
2774          * IXGBE_MAX_RING_DESC.  The Rx Burst bulk allocation function requires
2775          * extra memory at the end of the descriptor ring to be zero'd out.
2776          */
2777         if (adapter->rx_bulk_alloc_allowed)
2778                 /* zero out extra memory */
2779                 len += RTE_PMD_IXGBE_RX_MAX_BURST;
2780
2781         /*
2782          * Zero out HW ring memory. Zero out extra memory at the end of
2783          * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2784          * reads extra memory as zeros.
2785          */
2786         for (i = 0; i < len; i++) {
2787                 rxq->rx_ring[i] = zeroed_desc;
2788         }
2789
2790         /*
2791          * initialize extra software ring entries. Space for these extra
2792          * entries is always allocated
2793          */
2794         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2795         for (i = rxq->nb_rx_desc; i < len; ++i) {
2796                 rxq->sw_ring[i].mbuf = &rxq->fake_mbuf;
2797         }
2798
2799         rxq->rx_nb_avail = 0;
2800         rxq->rx_next_avail = 0;
2801         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2802         rxq->rx_tail = 0;
2803         rxq->nb_rx_hold = 0;
2804         rxq->pkt_first_seg = NULL;
2805         rxq->pkt_last_seg = NULL;
2806
2807 #ifdef RTE_IXGBE_INC_VECTOR
2808         rxq->rxrearm_start = 0;
2809         rxq->rxrearm_nb = 0;
2810 #endif
2811 }
2812
2813 static int
2814 ixgbe_is_vf(struct rte_eth_dev *dev)
2815 {
2816         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2817
2818         switch (hw->mac.type) {
2819         case ixgbe_mac_82599_vf:
2820         case ixgbe_mac_X540_vf:
2821         case ixgbe_mac_X550_vf:
2822         case ixgbe_mac_X550EM_x_vf:
2823         case ixgbe_mac_X550EM_a_vf:
2824                 return 1;
2825         default:
2826                 return 0;
2827         }
2828 }
2829
2830 uint64_t
2831 ixgbe_get_rx_queue_offloads(struct rte_eth_dev *dev)
2832 {
2833         uint64_t offloads = 0;
2834         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2835
2836         if (hw->mac.type != ixgbe_mac_82598EB)
2837                 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2838
2839         return offloads;
2840 }
2841
2842 uint64_t
2843 ixgbe_get_rx_port_offloads(struct rte_eth_dev *dev)
2844 {
2845         uint64_t offloads;
2846         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2847
2848         offloads = DEV_RX_OFFLOAD_IPV4_CKSUM  |
2849                    DEV_RX_OFFLOAD_UDP_CKSUM   |
2850                    DEV_RX_OFFLOAD_TCP_CKSUM   |
2851                    DEV_RX_OFFLOAD_CRC_STRIP   |
2852                    DEV_RX_OFFLOAD_JUMBO_FRAME |
2853                    DEV_RX_OFFLOAD_SCATTER;
2854
2855         if (hw->mac.type == ixgbe_mac_82598EB)
2856                 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2857
2858         if (ixgbe_is_vf(dev) == 0)
2859                 offloads |= (DEV_RX_OFFLOAD_VLAN_FILTER |
2860                              DEV_RX_OFFLOAD_VLAN_EXTEND);
2861
2862         /*
2863          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2864          * mode.
2865          */
2866         if ((hw->mac.type == ixgbe_mac_82599EB ||
2867              hw->mac.type == ixgbe_mac_X540) &&
2868             !RTE_ETH_DEV_SRIOV(dev).active)
2869                 offloads |= DEV_RX_OFFLOAD_TCP_LRO;
2870
2871         if (hw->mac.type == ixgbe_mac_82599EB ||
2872             hw->mac.type == ixgbe_mac_X540)
2873                 offloads |= DEV_RX_OFFLOAD_MACSEC_STRIP;
2874
2875         if (hw->mac.type == ixgbe_mac_X550 ||
2876             hw->mac.type == ixgbe_mac_X550EM_x ||
2877             hw->mac.type == ixgbe_mac_X550EM_a)
2878                 offloads |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
2879
2880 #ifdef RTE_LIBRTE_SECURITY
2881         if (dev->security_ctx)
2882                 offloads |= DEV_RX_OFFLOAD_SECURITY;
2883 #endif
2884
2885         return offloads;
2886 }
2887
2888 int __attribute__((cold))
2889 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2890                          uint16_t queue_idx,
2891                          uint16_t nb_desc,
2892                          unsigned int socket_id,
2893                          const struct rte_eth_rxconf *rx_conf,
2894                          struct rte_mempool *mp)
2895 {
2896         const struct rte_memzone *rz;
2897         struct ixgbe_rx_queue *rxq;
2898         struct ixgbe_hw     *hw;
2899         uint16_t len;
2900         struct ixgbe_adapter *adapter =
2901                 (struct ixgbe_adapter *)dev->data->dev_private;
2902         uint64_t offloads;
2903
2904         PMD_INIT_FUNC_TRACE();
2905         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2906
2907         offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
2908
2909         /*
2910          * Validate number of receive descriptors.
2911          * It must not exceed hardware maximum, and must be multiple
2912          * of IXGBE_ALIGN.
2913          */
2914         if (nb_desc % IXGBE_RXD_ALIGN != 0 ||
2915                         (nb_desc > IXGBE_MAX_RING_DESC) ||
2916                         (nb_desc < IXGBE_MIN_RING_DESC)) {
2917                 return -EINVAL;
2918         }
2919
2920         /* Free memory prior to re-allocation if needed... */
2921         if (dev->data->rx_queues[queue_idx] != NULL) {
2922                 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2923                 dev->data->rx_queues[queue_idx] = NULL;
2924         }
2925
2926         /* First allocate the rx queue data structure */
2927         rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct ixgbe_rx_queue),
2928                                  RTE_CACHE_LINE_SIZE, socket_id);
2929         if (rxq == NULL)
2930                 return -ENOMEM;
2931         rxq->mb_pool = mp;
2932         rxq->nb_rx_desc = nb_desc;
2933         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2934         rxq->queue_id = queue_idx;
2935         rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2936                 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2937         rxq->port_id = dev->data->port_id;
2938         rxq->crc_len = (uint8_t)((dev->data->dev_conf.rxmode.offloads &
2939                 DEV_RX_OFFLOAD_CRC_STRIP) ? 0 : ETHER_CRC_LEN);
2940         rxq->drop_en = rx_conf->rx_drop_en;
2941         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2942         rxq->offloads = offloads;
2943
2944         /*
2945          * The packet type in RX descriptor is different for different NICs.
2946          * Some bits are used for x550 but reserved for other NICS.
2947          * So set different masks for different NICs.
2948          */
2949         if (hw->mac.type == ixgbe_mac_X550 ||
2950             hw->mac.type == ixgbe_mac_X550EM_x ||
2951             hw->mac.type == ixgbe_mac_X550EM_a ||
2952             hw->mac.type == ixgbe_mac_X550_vf ||
2953             hw->mac.type == ixgbe_mac_X550EM_x_vf ||
2954             hw->mac.type == ixgbe_mac_X550EM_a_vf)
2955                 rxq->pkt_type_mask = IXGBE_PACKET_TYPE_MASK_X550;
2956         else
2957                 rxq->pkt_type_mask = IXGBE_PACKET_TYPE_MASK_82599;
2958
2959         /*
2960          * Allocate RX ring hardware descriptors. A memzone large enough to
2961          * handle the maximum ring size is allocated in order to allow for
2962          * resizing in later calls to the queue setup function.
2963          */
2964         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
2965                                       RX_RING_SZ, IXGBE_ALIGN, socket_id);
2966         if (rz == NULL) {
2967                 ixgbe_rx_queue_release(rxq);
2968                 return -ENOMEM;
2969         }
2970
2971         /*
2972          * Zero init all the descriptors in the ring.
2973          */
2974         memset(rz->addr, 0, RX_RING_SZ);
2975
2976         /*
2977          * Modified to setup VFRDT for Virtual Function
2978          */
2979         if (hw->mac.type == ixgbe_mac_82599_vf ||
2980             hw->mac.type == ixgbe_mac_X540_vf ||
2981             hw->mac.type == ixgbe_mac_X550_vf ||
2982             hw->mac.type == ixgbe_mac_X550EM_x_vf ||
2983             hw->mac.type == ixgbe_mac_X550EM_a_vf) {
2984                 rxq->rdt_reg_addr =
2985                         IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
2986                 rxq->rdh_reg_addr =
2987                         IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));
2988         } else {
2989                 rxq->rdt_reg_addr =
2990                         IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));
2991                 rxq->rdh_reg_addr =
2992                         IXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));
2993         }
2994
2995         rxq->rx_ring_phys_addr = rz->iova;
2996         rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
2997
2998         /*
2999          * Certain constraints must be met in order to use the bulk buffer
3000          * allocation Rx burst function. If any of Rx queues doesn't meet them
3001          * the feature should be disabled for the whole port.
3002          */
3003         if (check_rx_burst_bulk_alloc_preconditions(rxq)) {
3004                 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Rx Bulk Alloc "
3005                                     "preconditions - canceling the feature for "
3006                                     "the whole port[%d]",
3007                              rxq->queue_id, rxq->port_id);
3008                 adapter->rx_bulk_alloc_allowed = false;
3009         }
3010
3011         /*
3012          * Allocate software ring. Allow for space at the end of the
3013          * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
3014          * function does not access an invalid memory region.
3015          */
3016         len = nb_desc;
3017         if (adapter->rx_bulk_alloc_allowed)
3018                 len += RTE_PMD_IXGBE_RX_MAX_BURST;
3019
3020         rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
3021                                           sizeof(struct ixgbe_rx_entry) * len,
3022                                           RTE_CACHE_LINE_SIZE, socket_id);
3023         if (!rxq->sw_ring) {
3024                 ixgbe_rx_queue_release(rxq);
3025                 return -ENOMEM;
3026         }
3027
3028         /*
3029          * Always allocate even if it's not going to be needed in order to
3030          * simplify the code.
3031          *
3032          * This ring is used in LRO and Scattered Rx cases and Scattered Rx may
3033          * be requested in ixgbe_dev_rx_init(), which is called later from
3034          * dev_start() flow.
3035          */
3036         rxq->sw_sc_ring =
3037                 rte_zmalloc_socket("rxq->sw_sc_ring",
3038                                    sizeof(struct ixgbe_scattered_rx_entry) * len,
3039                                    RTE_CACHE_LINE_SIZE, socket_id);
3040         if (!rxq->sw_sc_ring) {
3041                 ixgbe_rx_queue_release(rxq);
3042                 return -ENOMEM;
3043         }
3044
3045         PMD_INIT_LOG(DEBUG, "sw_ring=%p sw_sc_ring=%p hw_ring=%p "
3046                             "dma_addr=0x%"PRIx64,
3047                      rxq->sw_ring, rxq->sw_sc_ring, rxq->rx_ring,
3048                      rxq->rx_ring_phys_addr);
3049
3050         if (!rte_is_power_of_2(nb_desc)) {
3051                 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Vector Rx "
3052                                     "preconditions - canceling the feature for "
3053                                     "the whole port[%d]",
3054                              rxq->queue_id, rxq->port_id);
3055                 adapter->rx_vec_allowed = false;
3056         } else
3057                 ixgbe_rxq_vec_setup(rxq);
3058
3059         dev->data->rx_queues[queue_idx] = rxq;
3060
3061         ixgbe_reset_rx_queue(adapter, rxq);
3062
3063         return 0;
3064 }
3065
3066 uint32_t
3067 ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3068 {
3069 #define IXGBE_RXQ_SCAN_INTERVAL 4
3070         volatile union ixgbe_adv_rx_desc *rxdp;
3071         struct ixgbe_rx_queue *rxq;
3072         uint32_t desc = 0;
3073
3074         rxq = dev->data->rx_queues[rx_queue_id];
3075         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
3076
3077         while ((desc < rxq->nb_rx_desc) &&
3078                 (rxdp->wb.upper.status_error &
3079                         rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD))) {
3080                 desc += IXGBE_RXQ_SCAN_INTERVAL;
3081                 rxdp += IXGBE_RXQ_SCAN_INTERVAL;
3082                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
3083                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
3084                                 desc - rxq->nb_rx_desc]);
3085         }
3086
3087         return desc;
3088 }
3089
3090 int
3091 ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
3092 {
3093         volatile union ixgbe_adv_rx_desc *rxdp;
3094         struct ixgbe_rx_queue *rxq = rx_queue;
3095         uint32_t desc;
3096
3097         if (unlikely(offset >= rxq->nb_rx_desc))
3098                 return 0;
3099         desc = rxq->rx_tail + offset;
3100         if (desc >= rxq->nb_rx_desc)
3101                 desc -= rxq->nb_rx_desc;
3102
3103         rxdp = &rxq->rx_ring[desc];
3104         return !!(rxdp->wb.upper.status_error &
3105                         rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD));
3106 }
3107
3108 int
3109 ixgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
3110 {
3111         struct ixgbe_rx_queue *rxq = rx_queue;
3112         volatile uint32_t *status;
3113         uint32_t nb_hold, desc;
3114
3115         if (unlikely(offset >= rxq->nb_rx_desc))
3116                 return -EINVAL;
3117
3118 #ifdef RTE_IXGBE_INC_VECTOR
3119         if (rxq->rx_using_sse)
3120                 nb_hold = rxq->rxrearm_nb;
3121         else
3122 #endif
3123                 nb_hold = rxq->nb_rx_hold;
3124         if (offset >= rxq->nb_rx_desc - nb_hold)
3125                 return RTE_ETH_RX_DESC_UNAVAIL;
3126
3127         desc = rxq->rx_tail + offset;
3128         if (desc >= rxq->nb_rx_desc)
3129                 desc -= rxq->nb_rx_desc;
3130
3131         status = &rxq->rx_ring[desc].wb.upper.status_error;
3132         if (*status & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD))
3133                 return RTE_ETH_RX_DESC_DONE;
3134
3135         return RTE_ETH_RX_DESC_AVAIL;
3136 }
3137
3138 int
3139 ixgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
3140 {
3141         struct ixgbe_tx_queue *txq = tx_queue;
3142         volatile uint32_t *status;
3143         uint32_t desc;
3144
3145         if (unlikely(offset >= txq->nb_tx_desc))
3146                 return -EINVAL;
3147
3148         desc = txq->tx_tail + offset;
3149         /* go to next desc that has the RS bit */
3150         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
3151                 txq->tx_rs_thresh;
3152         if (desc >= txq->nb_tx_desc) {
3153                 desc -= txq->nb_tx_desc;
3154                 if (desc >= txq->nb_tx_desc)
3155                         desc -= txq->nb_tx_desc;
3156         }
3157
3158         status = &txq->tx_ring[desc].wb.status;
3159         if (*status & rte_cpu_to_le_32(IXGBE_ADVTXD_STAT_DD))
3160                 return RTE_ETH_TX_DESC_DONE;
3161
3162         return RTE_ETH_TX_DESC_FULL;
3163 }
3164
3165 void __attribute__((cold))
3166 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
3167 {
3168         unsigned i;
3169         struct ixgbe_adapter *adapter =
3170                 (struct ixgbe_adapter *)dev->data->dev_private;
3171
3172         PMD_INIT_FUNC_TRACE();
3173
3174         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3175                 struct ixgbe_tx_queue *txq = dev->data->tx_queues[i];
3176
3177                 if (txq != NULL) {
3178                         txq->ops->release_mbufs(txq);
3179                         txq->ops->reset(txq);
3180                 }
3181         }
3182
3183         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3184                 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
3185
3186                 if (rxq != NULL) {
3187                         ixgbe_rx_queue_release_mbufs(rxq);
3188                         ixgbe_reset_rx_queue(adapter, rxq);
3189                 }
3190         }
3191 }
3192
3193 void
3194 ixgbe_dev_free_queues(struct rte_eth_dev *dev)
3195 {
3196         unsigned i;
3197
3198         PMD_INIT_FUNC_TRACE();
3199
3200         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3201                 ixgbe_dev_rx_queue_release(dev->data->rx_queues[i]);
3202                 dev->data->rx_queues[i] = NULL;
3203         }
3204         dev->data->nb_rx_queues = 0;
3205
3206         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3207                 ixgbe_dev_tx_queue_release(dev->data->tx_queues[i]);
3208                 dev->data->tx_queues[i] = NULL;
3209         }
3210         dev->data->nb_tx_queues = 0;
3211 }
3212
3213 /*********************************************************************
3214  *
3215  *  Device RX/TX init functions
3216  *
3217  **********************************************************************/
3218
3219 /**
3220  * Receive Side Scaling (RSS)
3221  * See section 7.1.2.8 in the following document:
3222  *     "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
3223  *
3224  * Principles:
3225  * The source and destination IP addresses of the IP header and the source
3226  * and destination ports of TCP/UDP headers, if any, of received packets are
3227  * hashed against a configurable random key to compute a 32-bit RSS hash result.
3228  * The seven (7) LSBs of the 32-bit hash result are used as an index into a
3229  * 128-entry redirection table (RETA).  Each entry of the RETA provides a 3-bit
3230  * RSS output index which is used as the RX queue index where to store the
3231  * received packets.
3232  * The following output is supplied in the RX write-back descriptor:
3233  *     - 32-bit result of the Microsoft RSS hash function,
3234  *     - 4-bit RSS type field.
3235  */
3236
3237 /*
3238  * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
3239  * Used as the default key.
3240  */
3241 static uint8_t rss_intel_key[40] = {
3242         0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
3243         0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
3244         0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
3245         0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
3246         0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
3247 };
3248
3249 static void
3250 ixgbe_rss_disable(struct rte_eth_dev *dev)
3251 {
3252         struct ixgbe_hw *hw;
3253         uint32_t mrqc;
3254         uint32_t mrqc_reg;
3255
3256         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3257         mrqc_reg = ixgbe_mrqc_reg_get(hw->mac.type);
3258         mrqc = IXGBE_READ_REG(hw, mrqc_reg);
3259         mrqc &= ~IXGBE_MRQC_RSSEN;
3260         IXGBE_WRITE_REG(hw, mrqc_reg, mrqc);
3261 }
3262
3263 static void
3264 ixgbe_hw_rss_hash_set(struct ixgbe_hw *hw, struct rte_eth_rss_conf *rss_conf)
3265 {
3266         uint8_t  *hash_key;
3267         uint32_t mrqc;
3268         uint32_t rss_key;
3269         uint64_t rss_hf;
3270         uint16_t i;
3271         uint32_t mrqc_reg;
3272         uint32_t rssrk_reg;
3273
3274         mrqc_reg = ixgbe_mrqc_reg_get(hw->mac.type);
3275         rssrk_reg = ixgbe_rssrk_reg_get(hw->mac.type, 0);
3276
3277         hash_key = rss_conf->rss_key;
3278         if (hash_key != NULL) {
3279                 /* Fill in RSS hash key */
3280                 for (i = 0; i < 10; i++) {
3281                         rss_key  = hash_key[(i * 4)];
3282                         rss_key |= hash_key[(i * 4) + 1] << 8;
3283                         rss_key |= hash_key[(i * 4) + 2] << 16;
3284                         rss_key |= hash_key[(i * 4) + 3] << 24;
3285                         IXGBE_WRITE_REG_ARRAY(hw, rssrk_reg, i, rss_key);
3286                 }
3287         }
3288
3289         /* Set configured hashing protocols in MRQC register */
3290         rss_hf = rss_conf->rss_hf;
3291         mrqc = IXGBE_MRQC_RSSEN; /* Enable RSS */
3292         if (rss_hf & ETH_RSS_IPV4)
3293                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
3294         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
3295                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
3296         if (rss_hf & ETH_RSS_IPV6)
3297                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
3298         if (rss_hf & ETH_RSS_IPV6_EX)
3299                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
3300         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
3301                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3302         if (rss_hf & ETH_RSS_IPV6_TCP_EX)
3303                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
3304         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
3305                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3306         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
3307                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3308         if (rss_hf & ETH_RSS_IPV6_UDP_EX)
3309                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
3310         IXGBE_WRITE_REG(hw, mrqc_reg, mrqc);
3311 }
3312
3313 int
3314 ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
3315                           struct rte_eth_rss_conf *rss_conf)
3316 {
3317         struct ixgbe_hw *hw;
3318         uint32_t mrqc;
3319         uint64_t rss_hf;
3320         uint32_t mrqc_reg;
3321
3322         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3323
3324         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3325                 PMD_DRV_LOG(ERR, "RSS hash update is not supported on this "
3326                         "NIC.");
3327                 return -ENOTSUP;
3328         }
3329         mrqc_reg = ixgbe_mrqc_reg_get(hw->mac.type);
3330
3331         /*
3332          * Excerpt from section 7.1.2.8 Receive-Side Scaling (RSS):
3333          *     "RSS enabling cannot be done dynamically while it must be
3334          *      preceded by a software reset"
3335          * Before changing anything, first check that the update RSS operation
3336          * does not attempt to disable RSS, if RSS was enabled at
3337          * initialization time, or does not attempt to enable RSS, if RSS was
3338          * disabled at initialization time.
3339          */
3340         rss_hf = rss_conf->rss_hf & IXGBE_RSS_OFFLOAD_ALL;
3341         mrqc = IXGBE_READ_REG(hw, mrqc_reg);
3342         if (!(mrqc & IXGBE_MRQC_RSSEN)) { /* RSS disabled */
3343                 if (rss_hf != 0) /* Enable RSS */
3344                         return -(EINVAL);
3345                 return 0; /* Nothing to do */
3346         }
3347         /* RSS enabled */
3348         if (rss_hf == 0) /* Disable RSS */
3349                 return -(EINVAL);
3350         ixgbe_hw_rss_hash_set(hw, rss_conf);
3351         return 0;
3352 }
3353
3354 int
3355 ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
3356                             struct rte_eth_rss_conf *rss_conf)
3357 {
3358         struct ixgbe_hw *hw;
3359         uint8_t *hash_key;
3360         uint32_t mrqc;
3361         uint32_t rss_key;
3362         uint64_t rss_hf;
3363         uint16_t i;
3364         uint32_t mrqc_reg;
3365         uint32_t rssrk_reg;
3366
3367         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3368         mrqc_reg = ixgbe_mrqc_reg_get(hw->mac.type);
3369         rssrk_reg = ixgbe_rssrk_reg_get(hw->mac.type, 0);
3370         hash_key = rss_conf->rss_key;
3371         if (hash_key != NULL) {
3372                 /* Return RSS hash key */
3373                 for (i = 0; i < 10; i++) {
3374                         rss_key = IXGBE_READ_REG_ARRAY(hw, rssrk_reg, i);
3375                         hash_key[(i * 4)] = rss_key & 0x000000FF;
3376                         hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;
3377                         hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;
3378                         hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;
3379                 }
3380         }
3381
3382         /* Get RSS functions configured in MRQC register */
3383         mrqc = IXGBE_READ_REG(hw, mrqc_reg);
3384         if ((mrqc & IXGBE_MRQC_RSSEN) == 0) { /* RSS is disabled */
3385                 rss_conf->rss_hf = 0;
3386                 return 0;
3387         }
3388         rss_hf = 0;
3389         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4)
3390                 rss_hf |= ETH_RSS_IPV4;
3391         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_TCP)
3392                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
3393         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6)
3394                 rss_hf |= ETH_RSS_IPV6;
3395         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX)
3396                 rss_hf |= ETH_RSS_IPV6_EX;
3397         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_TCP)
3398                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
3399         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP)
3400                 rss_hf |= ETH_RSS_IPV6_TCP_EX;
3401         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_UDP)
3402                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
3403         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_UDP)
3404                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
3405         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP)
3406                 rss_hf |= ETH_RSS_IPV6_UDP_EX;
3407         rss_conf->rss_hf = rss_hf;
3408         return 0;
3409 }
3410
3411 static void
3412 ixgbe_rss_configure(struct rte_eth_dev *dev)
3413 {
3414         struct rte_eth_rss_conf rss_conf;
3415         struct ixgbe_hw *hw;
3416         uint32_t reta;
3417         uint16_t i;
3418         uint16_t j;
3419         uint16_t sp_reta_size;
3420         uint32_t reta_reg;
3421
3422         PMD_INIT_FUNC_TRACE();
3423         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3424
3425         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3426
3427         /*
3428          * Fill in redirection table
3429          * The byte-swap is needed because NIC registers are in
3430          * little-endian order.
3431          */
3432         reta = 0;
3433         for (i = 0, j = 0; i < sp_reta_size; i++, j++) {
3434                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3435
3436                 if (j == dev->data->nb_rx_queues)
3437                         j = 0;
3438                 reta = (reta << 8) | j;
3439                 if ((i & 3) == 3)
3440                         IXGBE_WRITE_REG(hw, reta_reg,
3441                                         rte_bswap32(reta));
3442         }
3443
3444         /*
3445          * Configure the RSS key and the RSS protocols used to compute
3446          * the RSS hash of input packets.
3447          */
3448         rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
3449         if ((rss_conf.rss_hf & IXGBE_RSS_OFFLOAD_ALL) == 0) {
3450                 ixgbe_rss_disable(dev);
3451                 return;
3452         }
3453         if (rss_conf.rss_key == NULL)
3454                 rss_conf.rss_key = rss_intel_key; /* Default hash key */
3455         ixgbe_hw_rss_hash_set(hw, &rss_conf);
3456 }
3457
3458 #define NUM_VFTA_REGISTERS 128
3459 #define NIC_RX_BUFFER_SIZE 0x200
3460 #define X550_RX_BUFFER_SIZE 0x180
3461
3462 static void
3463 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
3464 {
3465         struct rte_eth_vmdq_dcb_conf *cfg;
3466         struct ixgbe_hw *hw;
3467         enum rte_eth_nb_pools num_pools;
3468         uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
3469         uint16_t pbsize;
3470         uint8_t nb_tcs; /* number of traffic classes */
3471         int i;
3472
3473         PMD_INIT_FUNC_TRACE();
3474         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3475         cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
3476         num_pools = cfg->nb_queue_pools;
3477         /* Check we have a valid number of pools */
3478         if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
3479                 ixgbe_rss_disable(dev);
3480                 return;
3481         }
3482         /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
3483         nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
3484
3485         /*
3486          * RXPBSIZE
3487          * split rx buffer up into sections, each for 1 traffic class
3488          */
3489         switch (hw->mac.type) {
3490         case ixgbe_mac_X550:
3491         case ixgbe_mac_X550EM_x:
3492         case ixgbe_mac_X550EM_a:
3493                 pbsize = (uint16_t)(X550_RX_BUFFER_SIZE / nb_tcs);
3494                 break;
3495         default:
3496                 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
3497                 break;
3498         }
3499         for (i = 0; i < nb_tcs; i++) {
3500                 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
3501
3502                 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
3503                 /* clear 10 bits. */
3504                 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
3505                 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
3506         }
3507         /* zero alloc all unused TCs */
3508         for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3509                 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
3510
3511                 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
3512                 /* clear 10 bits. */
3513                 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
3514         }
3515
3516         /* MRQC: enable vmdq and dcb */
3517         mrqc = (num_pools == ETH_16_POOLS) ?
3518                 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN;
3519         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3520
3521         /* PFVTCTL: turn on virtualisation and set the default pool */
3522         vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3523         if (cfg->enable_default_pool) {
3524                 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3525         } else {
3526                 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3527         }
3528
3529         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3530
3531         /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
3532         queue_mapping = 0;
3533         for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
3534                 /*
3535                  * mapping is done with 3 bits per priority,
3536                  * so shift by i*3 each time
3537                  */
3538                 queue_mapping |= ((cfg->dcb_tc[i] & 0x07) << (i * 3));
3539
3540         IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
3541
3542         /* RTRPCS: DCB related */
3543         IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
3544
3545         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3546         vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3547         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
3548         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3549
3550         /* VFTA - enable all vlan filters */
3551         for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
3552                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
3553         }
3554
3555         /* VFRE: pool enabling for receive - 16 or 32 */
3556         IXGBE_WRITE_REG(hw, IXGBE_VFRE(0),
3557                         num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
3558
3559         /*
3560          * MPSAR - allow pools to read specific mac addresses
3561          * In this case, all pools should be able to read from mac addr 0
3562          */
3563         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
3564         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
3565
3566         /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3567         for (i = 0; i < cfg->nb_pool_maps; i++) {
3568                 /* set vlan id in VF register and set the valid bit */
3569                 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN |
3570                                 (cfg->pool_map[i].vlan_id & 0xFFF)));
3571                 /*
3572                  * Put the allowed pools in VFB reg. As we only have 16 or 32
3573                  * pools, we only need to use the first half of the register
3574                  * i.e. bits 0-31
3575                  */
3576                 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
3577         }
3578 }
3579
3580 /**
3581  * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
3582  * @dev: pointer to eth_dev structure
3583  * @dcb_config: pointer to ixgbe_dcb_config structure
3584  */
3585 static void
3586 ixgbe_dcb_tx_hw_config(struct rte_eth_dev *dev,
3587                        struct ixgbe_dcb_config *dcb_config)
3588 {
3589         uint32_t reg;
3590         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3591
3592         PMD_INIT_FUNC_TRACE();
3593         if (hw->mac.type != ixgbe_mac_82598EB) {
3594                 /* Disable the Tx desc arbiter so that MTQC can be changed */
3595                 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3596                 reg |= IXGBE_RTTDCS_ARBDIS;
3597                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3598
3599                 /* Enable DCB for Tx with 8 TCs */
3600                 if (dcb_config->num_tcs.pg_tcs == 8) {
3601                         reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3602                 } else {
3603                         reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3604                 }
3605                 if (dcb_config->vt_mode)
3606                         reg |= IXGBE_MTQC_VT_ENA;
3607                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3608
3609                 /* Enable the Tx desc arbiter */
3610                 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3611                 reg &= ~IXGBE_RTTDCS_ARBDIS;
3612                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3613
3614                 /* Enable Security TX Buffer IFG for DCB */
3615                 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3616                 reg |= IXGBE_SECTX_DCB;
3617                 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
3618         }
3619 }
3620
3621 /**
3622  * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
3623  * @dev: pointer to rte_eth_dev structure
3624  * @dcb_config: pointer to ixgbe_dcb_config structure
3625  */
3626 static void
3627 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
3628                         struct ixgbe_dcb_config *dcb_config)
3629 {
3630         struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
3631                         &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
3632         struct ixgbe_hw *hw =
3633                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3634
3635         PMD_INIT_FUNC_TRACE();
3636         if (hw->mac.type != ixgbe_mac_82598EB)
3637                 /*PF VF Transmit Enable*/
3638                 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
3639                         vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
3640
3641         /*Configure general DCB TX parameters*/
3642         ixgbe_dcb_tx_hw_config(dev, dcb_config);
3643 }
3644
3645 static void
3646 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
3647                         struct ixgbe_dcb_config *dcb_config)
3648 {
3649         struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
3650                         &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
3651         struct ixgbe_dcb_tc_config *tc;
3652         uint8_t i, j;
3653
3654         /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
3655         if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS) {
3656                 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
3657                 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
3658         } else {
3659                 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
3660                 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
3661         }
3662
3663         /* Initialize User Priority to Traffic Class mapping */
3664         for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {
3665                 tc = &dcb_config->tc_config[j];
3666                 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0;
3667         }
3668
3669         /* User Priority to Traffic Class mapping */
3670         for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3671                 j = vmdq_rx_conf->dcb_tc[i];
3672                 tc = &dcb_config->tc_config[j];
3673                 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap |=
3674                                                 (uint8_t)(1 << i);
3675         }
3676 }
3677
3678 static void
3679 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
3680                         struct ixgbe_dcb_config *dcb_config)
3681 {
3682         struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
3683                         &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
3684         struct ixgbe_dcb_tc_config *tc;
3685         uint8_t i, j;
3686
3687         /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
3688         if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS) {
3689                 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
3690                 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
3691         } else {
3692                 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
3693                 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
3694         }
3695
3696         /* Initialize User Priority to Traffic Class mapping */
3697         for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {
3698                 tc = &dcb_config->tc_config[j];
3699                 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0;
3700         }
3701
3702         /* User Priority to Traffic Class mapping */
3703         for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3704                 j = vmdq_tx_conf->dcb_tc[i];
3705                 tc = &dcb_config->tc_config[j];
3706                 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap |=
3707                                                 (uint8_t)(1 << i);
3708         }
3709 }
3710
3711 static void
3712 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,
3713                 struct ixgbe_dcb_config *dcb_config)
3714 {
3715         struct rte_eth_dcb_rx_conf *rx_conf =
3716                         &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
3717         struct ixgbe_dcb_tc_config *tc;
3718         uint8_t i, j;
3719
3720         dcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;
3721         dcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;
3722
3723         /* Initialize User Priority to Traffic Class mapping */
3724         for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {
3725                 tc = &dcb_config->tc_config[j];
3726                 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0;
3727         }
3728
3729         /* User Priority to Traffic Class mapping */
3730         for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3731                 j = rx_conf->dcb_tc[i];
3732                 tc = &dcb_config->tc_config[j];
3733                 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap |=
3734                                                 (uint8_t)(1 << i);
3735         }
3736 }
3737
3738 static void
3739 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,
3740                 struct ixgbe_dcb_config *dcb_config)
3741 {
3742         struct rte_eth_dcb_tx_conf *tx_conf =
3743                         &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
3744         struct ixgbe_dcb_tc_config *tc;
3745         uint8_t i, j;
3746
3747         dcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;
3748         dcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;
3749
3750         /* Initialize User Priority to Traffic Class mapping */
3751         for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {
3752                 tc = &dcb_config->tc_config[j];
3753                 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0;
3754         }
3755
3756         /* User Priority to Traffic Class mapping */
3757         for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3758                 j = tx_conf->dcb_tc[i];
3759                 tc = &dcb_config->tc_config[j];
3760                 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap |=
3761                                                 (uint8_t)(1 << i);
3762         }
3763 }
3764
3765 /**
3766  * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
3767  * @dev: pointer to eth_dev structure
3768  * @dcb_config: pointer to ixgbe_dcb_config structure
3769  */
3770 static void
3771 ixgbe_dcb_rx_hw_config(struct rte_eth_dev *dev,
3772                        struct ixgbe_dcb_config *dcb_config)
3773 {
3774         uint32_t reg;
3775         uint32_t vlanctrl;
3776         uint8_t i;
3777         uint32_t q;
3778         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3779
3780         PMD_INIT_FUNC_TRACE();
3781         /*
3782          * Disable the arbiter before changing parameters
3783          * (always enable recycle mode; WSP)
3784          */
3785         reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
3786         IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
3787
3788         if (hw->mac.type != ixgbe_mac_82598EB) {
3789                 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
3790                 if (dcb_config->num_tcs.pg_tcs == 4) {
3791                         if (dcb_config->vt_mode)
3792                                 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3793                                         IXGBE_MRQC_VMDQRT4TCEN;
3794                         else {
3795                                 /* no matter the mode is DCB or DCB_RSS, just
3796                                  * set the MRQE to RSSXTCEN. RSS is controlled
3797                                  * by RSS_FIELD
3798                                  */
3799                                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
3800                                 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3801                                         IXGBE_MRQC_RTRSS4TCEN;
3802                         }
3803                 }
3804                 if (dcb_config->num_tcs.pg_tcs == 8) {
3805                         if (dcb_config->vt_mode)
3806                                 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3807                                         IXGBE_MRQC_VMDQRT8TCEN;
3808                         else {
3809                                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
3810                                 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3811                                         IXGBE_MRQC_RTRSS8TCEN;
3812                         }
3813                 }
3814
3815                 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
3816
3817                 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3818                         /* Disable drop for all queues in VMDQ mode*/
3819                         for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3820                                 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3821                                                 (IXGBE_QDE_WRITE |
3822                                                  (q << IXGBE_QDE_IDX_SHIFT)));
3823                 } else {
3824                         /* Enable drop for all queues in SRIOV mode */
3825                         for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3826                                 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3827                                                 (IXGBE_QDE_WRITE |
3828                                                  (q << IXGBE_QDE_IDX_SHIFT) |
3829                                                  IXGBE_QDE_ENABLE));
3830                 }
3831         }
3832
3833         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3834         vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3835         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
3836         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3837
3838         /* VFTA - enable all vlan filters */
3839         for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
3840                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
3841         }
3842
3843         /*
3844          * Configure Rx packet plane (recycle mode; WSP) and
3845          * enable arbiter
3846          */
3847         reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
3848         IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
3849 }
3850
3851 static void
3852 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
3853                         uint16_t *max, uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
3854 {
3855         switch (hw->mac.type) {
3856         case ixgbe_mac_82598EB:
3857                 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
3858                 break;
3859         case ixgbe_mac_82599EB:
3860         case ixgbe_mac_X540:
3861         case ixgbe_mac_X550:
3862         case ixgbe_mac_X550EM_x:
3863         case ixgbe_mac_X550EM_a:
3864                 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
3865                                                   tsa, map);
3866                 break;
3867         default:
3868                 break;
3869         }
3870 }
3871
3872 static void
3873 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
3874                             uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
3875 {
3876         switch (hw->mac.type) {
3877         case ixgbe_mac_82598EB:
3878                 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id, tsa);
3879                 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id, tsa);
3880                 break;
3881         case ixgbe_mac_82599EB:
3882         case ixgbe_mac_X540:
3883         case ixgbe_mac_X550:
3884         case ixgbe_mac_X550EM_x:
3885         case ixgbe_mac_X550EM_a:
3886                 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id, tsa);
3887                 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id, tsa, map);
3888                 break;
3889         default:
3890                 break;
3891         }
3892 }
3893
3894 #define DCB_RX_CONFIG  1
3895 #define DCB_TX_CONFIG  1
3896 #define DCB_TX_PB      1024
3897 /**
3898  * ixgbe_dcb_hw_configure - Enable DCB and configure
3899  * general DCB in VT mode and non-VT mode parameters
3900  * @dev: pointer to rte_eth_dev structure
3901  * @dcb_config: pointer to ixgbe_dcb_config structure
3902  */
3903 static int
3904 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
3905                         struct ixgbe_dcb_config *dcb_config)
3906 {
3907         int     ret = 0;
3908         uint8_t i, pfc_en, nb_tcs;
3909         uint16_t pbsize, rx_buffer_size;
3910         uint8_t config_dcb_rx = 0;
3911         uint8_t config_dcb_tx = 0;
3912         uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3913         uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3914         uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3915         uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3916         uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3917         struct ixgbe_dcb_tc_config *tc;
3918         uint32_t max_frame = dev->data->mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3919         struct ixgbe_hw *hw =
3920                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3921         struct ixgbe_bw_conf *bw_conf =
3922                 IXGBE_DEV_PRIVATE_TO_BW_CONF(dev->data->dev_private);
3923
3924         switch (dev->data->dev_conf.rxmode.mq_mode) {
3925         case ETH_MQ_RX_VMDQ_DCB:
3926                 dcb_config->vt_mode = true;
3927                 if (hw->mac.type != ixgbe_mac_82598EB) {
3928                         config_dcb_rx = DCB_RX_CONFIG;
3929                         /*
3930                          *get dcb and VT rx configuration parameters
3931                          *from rte_eth_conf
3932                          */
3933                         ixgbe_vmdq_dcb_rx_config(dev, dcb_config);
3934                         /*Configure general VMDQ and DCB RX parameters*/
3935                         ixgbe_vmdq_dcb_configure(dev);
3936                 }
3937                 break;
3938         case ETH_MQ_RX_DCB:
3939         case ETH_MQ_RX_DCB_RSS:
3940                 dcb_config->vt_mode = false;
3941                 config_dcb_rx = DCB_RX_CONFIG;
3942                 /* Get dcb TX configuration parameters from rte_eth_conf */
3943                 ixgbe_dcb_rx_config(dev, dcb_config);
3944                 /*Configure general DCB RX parameters*/
3945                 ixgbe_dcb_rx_hw_config(dev, dcb_config);
3946                 break;
3947         default:
3948                 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration");
3949                 break;
3950         }
3951         switch (dev->data->dev_conf.txmode.mq_mode) {
3952         case ETH_MQ_TX_VMDQ_DCB:
3953                 dcb_config->vt_mode = true;
3954                 config_dcb_tx = DCB_TX_CONFIG;
3955                 /* get DCB and VT TX configuration parameters
3956                  * from rte_eth_conf
3957                  */
3958                 ixgbe_dcb_vt_tx_config(dev, dcb_config);
3959                 /*Configure general VMDQ and DCB TX parameters*/
3960                 ixgbe_vmdq_dcb_hw_tx_config(dev, dcb_config);
3961                 break;
3962
3963         case ETH_MQ_TX_DCB:
3964                 dcb_config->vt_mode = false;
3965                 config_dcb_tx = DCB_TX_CONFIG;
3966                 /*get DCB TX configuration parameters from rte_eth_conf*/
3967                 ixgbe_dcb_tx_config(dev, dcb_config);
3968                 /*Configure general DCB TX parameters*/
3969                 ixgbe_dcb_tx_hw_config(dev, dcb_config);
3970                 break;
3971         default:
3972                 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration");
3973                 break;
3974         }
3975
3976         nb_tcs = dcb_config->num_tcs.pfc_tcs;
3977         /* Unpack map */
3978         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3979         if (nb_tcs == ETH_4_TCS) {
3980                 /* Avoid un-configured priority mapping to TC0 */
3981                 uint8_t j = 4;
3982                 uint8_t mask = 0xFF;
3983
3984                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
3985                         mask = (uint8_t)(mask & (~(1 << map[i])));
3986                 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
3987                         if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
3988                                 map[j++] = i;
3989                         mask >>= 1;
3990                 }
3991                 /* Re-configure 4 TCs BW */
3992                 for (i = 0; i < nb_tcs; i++) {
3993                         tc = &dcb_config->tc_config[i];
3994                         if (bw_conf->tc_num != nb_tcs)
3995                                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
3996                                         (uint8_t)(100 / nb_tcs);
3997                         tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
3998                                                 (uint8_t)(100 / nb_tcs);
3999                 }
4000                 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4001                         tc = &dcb_config->tc_config[i];
4002                         tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
4003                         tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
4004                 }
4005         } else {
4006                 /* Re-configure 8 TCs BW */
4007                 for (i = 0; i < nb_tcs; i++) {
4008                         tc = &dcb_config->tc_config[i];
4009                         if (bw_conf->tc_num != nb_tcs)
4010                                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
4011                                         (uint8_t)(100 / nb_tcs + (i & 1));
4012                         tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
4013                                 (uint8_t)(100 / nb_tcs + (i & 1));
4014                 }
4015         }
4016
4017         switch (hw->mac.type) {
4018         case ixgbe_mac_X550:
4019         case ixgbe_mac_X550EM_x:
4020         case ixgbe_mac_X550EM_a:
4021                 rx_buffer_size = X550_RX_BUFFER_SIZE;
4022                 break;
4023         default:
4024                 rx_buffer_size = NIC_RX_BUFFER_SIZE;
4025                 break;
4026         }
4027
4028         if (config_dcb_rx) {
4029                 /* Set RX buffer size */
4030                 pbsize = (uint16_t)(rx_buffer_size / nb_tcs);
4031                 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
4032
4033                 for (i = 0; i < nb_tcs; i++) {
4034                         IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
4035                 }
4036                 /* zero alloc all unused TCs */
4037                 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
4038                         IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4039                 }
4040         }
4041         if (config_dcb_tx) {
4042                 /* Only support an equally distributed
4043                  *  Tx packet buffer strategy.
4044                  */
4045                 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
4046                 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
4047
4048                 for (i = 0; i < nb_tcs; i++) {
4049                         IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4050                         IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4051                 }
4052                 /* Clear unused TCs, if any, to zero buffer size*/
4053                 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
4054                         IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4055                         IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4056                 }
4057         }
4058
4059         /*Calculates traffic class credits*/
4060         ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config, max_frame,
4061                                 IXGBE_DCB_TX_CONFIG);
4062         ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config, max_frame,
4063                                 IXGBE_DCB_RX_CONFIG);
4064
4065         if (config_dcb_rx) {
4066                 /* Unpack CEE standard containers */
4067                 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
4068                 ixgbe_dcb_unpack_max_cee(dcb_config, max);
4069                 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
4070                 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
4071                 /* Configure PG(ETS) RX */
4072                 ixgbe_dcb_hw_arbite_rx_config(hw, refill, max, bwgid, tsa, map);
4073         }
4074
4075         if (config_dcb_tx) {
4076                 /* Unpack CEE standard containers */
4077                 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
4078                 ixgbe_dcb_unpack_max_cee(dcb_config, max);
4079                 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
4080                 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
4081                 /* Configure PG(ETS) TX */
4082                 ixgbe_dcb_hw_arbite_tx_config(hw, refill, max, bwgid, tsa, map);
4083         }
4084
4085         /*Configure queue statistics registers*/
4086         ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
4087
4088         /* Check if the PFC is supported */
4089         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
4090                 pbsize = (uint16_t)(rx_buffer_size / nb_tcs);
4091                 for (i = 0; i < nb_tcs; i++) {
4092                         /*
4093                         * If the TC count is 8,and the default high_water is 48,
4094                         * the low_water is 16 as default.
4095                         */
4096                         hw->fc.high_water[i] = (pbsize * 3) / 4;
4097                         hw->fc.low_water[i] = pbsize / 4;
4098                         /* Enable pfc for this TC */
4099                         tc = &dcb_config->tc_config[i];
4100                         tc->pfc = ixgbe_dcb_pfc_enabled;
4101                 }
4102                 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
4103                 if (dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
4104                         pfc_en &= 0x0F;
4105                 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
4106         }
4107
4108         return ret;
4109 }
4110
4111 /**
4112  * ixgbe_configure_dcb - Configure DCB  Hardware
4113  * @dev: pointer to rte_eth_dev
4114  */
4115 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
4116 {
4117         struct ixgbe_dcb_config *dcb_cfg =
4118                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4119         struct rte_eth_conf *dev_conf = &(dev->data->dev_conf);
4120
4121         PMD_INIT_FUNC_TRACE();
4122
4123         /* check support mq_mode for DCB */
4124         if ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) &&
4125             (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB) &&
4126             (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB_RSS))
4127                 return;
4128
4129         if (dev->data->nb_rx_queues > ETH_DCB_NUM_QUEUES)
4130                 return;
4131
4132         /** Configure DCB hardware **/
4133         ixgbe_dcb_hw_configure(dev, dcb_cfg);
4134 }
4135
4136 /*
4137  * VMDq only support for 10 GbE NIC.
4138  */
4139 static void
4140 ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
4141 {
4142         struct rte_eth_vmdq_rx_conf *cfg;
4143         struct ixgbe_hw *hw;
4144         enum rte_eth_nb_pools num_pools;
4145         uint32_t mrqc, vt_ctl, vlanctrl;
4146         uint32_t vmolr = 0;
4147         int i;
4148
4149         PMD_INIT_FUNC_TRACE();
4150         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4151         cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
4152         num_pools = cfg->nb_queue_pools;
4153
4154         ixgbe_rss_disable(dev);
4155
4156         /* MRQC: enable vmdq */
4157         mrqc = IXGBE_MRQC_VMDQEN;
4158         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
4159
4160         /* PFVTCTL: turn on virtualisation and set the default pool */
4161         vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
4162         if (cfg->enable_default_pool)
4163                 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
4164         else
4165                 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
4166
4167         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
4168
4169         for (i = 0; i < (int)num_pools; i++) {
4170                 vmolr = ixgbe_convert_vm_rx_mask_to_val(cfg->rx_mode, vmolr);
4171                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(i), vmolr);
4172         }
4173
4174         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
4175         vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4176         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
4177         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
4178
4179         /* VFTA - enable all vlan filters */
4180         for (i = 0; i < NUM_VFTA_REGISTERS; i++)
4181                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), UINT32_MAX);
4182
4183         /* VFRE: pool enabling for receive - 64 */
4184         IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), UINT32_MAX);
4185         if (num_pools == ETH_64_POOLS)
4186                 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), UINT32_MAX);
4187
4188         /*
4189          * MPSAR - allow pools to read specific mac addresses
4190          * In this case, all pools should be able to read from mac addr 0
4191          */
4192         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), UINT32_MAX);
4193         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), UINT32_MAX);
4194
4195         /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
4196         for (i = 0; i < cfg->nb_pool_maps; i++) {
4197                 /* set vlan id in VF register and set the valid bit */
4198                 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN |
4199                                 (cfg->pool_map[i].vlan_id & IXGBE_RXD_VLAN_ID_MASK)));
4200                 /*
4201                  * Put the allowed pools in VFB reg. As we only have 16 or 64
4202                  * pools, we only need to use the first half of the register
4203                  * i.e. bits 0-31
4204                  */
4205                 if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
4206                         IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i * 2),
4207                                         (cfg->pool_map[i].pools & UINT32_MAX));
4208                 else
4209                         IXGBE_WRITE_REG(hw, IXGBE_VLVFB((i * 2 + 1)),
4210                                         ((cfg->pool_map[i].pools >> 32) & UINT32_MAX));
4211
4212         }
4213
4214         /* PFDMA Tx General Switch Control Enables VMDQ loopback */
4215         if (cfg->enable_loop_back) {
4216                 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
4217                 for (i = 0; i < RTE_IXGBE_VMTXSW_REGISTER_COUNT; i++)
4218                         IXGBE_WRITE_REG(hw, IXGBE_VMTXSW(i), UINT32_MAX);
4219         }
4220
4221         IXGBE_WRITE_FLUSH(hw);
4222 }
4223
4224 /*
4225  * ixgbe_dcb_config_tx_hw_config - Configure general VMDq TX parameters
4226  * @hw: pointer to hardware structure
4227  */
4228 static void
4229 ixgbe_vmdq_tx_hw_configure(struct ixgbe_hw *hw)
4230 {
4231         uint32_t reg;
4232         uint32_t q;
4233
4234         PMD_INIT_FUNC_TRACE();
4235         /*PF VF Transmit Enable*/
4236         IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), UINT32_MAX);
4237         IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), UINT32_MAX);
4238
4239         /* Disable the Tx desc arbiter so that MTQC can be changed */
4240         reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
4241         reg |= IXGBE_RTTDCS_ARBDIS;
4242         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
4243
4244         reg = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
4245         IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
4246
4247         /* Disable drop for all queues */
4248         for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
4249                 IXGBE_WRITE_REG(hw, IXGBE_QDE,
4250                   (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
4251
4252         /* Enable the Tx desc arbiter */
4253         reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
4254         reg &= ~IXGBE_RTTDCS_ARBDIS;
4255         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
4256
4257         IXGBE_WRITE_FLUSH(hw);
4258 }
4259
4260 static int __attribute__((cold))
4261 ixgbe_alloc_rx_queue_mbufs(struct ixgbe_rx_queue *rxq)
4262 {
4263         struct ixgbe_rx_entry *rxe = rxq->sw_ring;
4264         uint64_t dma_addr;
4265         unsigned int i;
4266
4267         /* Initialize software ring entries */
4268         for (i = 0; i < rxq->nb_rx_desc; i++) {
4269                 volatile union ixgbe_adv_rx_desc *rxd;
4270                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
4271
4272                 if (mbuf == NULL) {
4273                         PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
4274                                      (unsigned) rxq->queue_id);
4275                         return -ENOMEM;
4276                 }
4277
4278                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
4279                 mbuf->port = rxq->port_id;
4280
4281                 dma_addr =
4282                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
4283                 rxd = &rxq->rx_ring[i];
4284                 rxd->read.hdr_addr = 0;
4285                 rxd->read.pkt_addr = dma_addr;
4286                 rxe[i].mbuf = mbuf;
4287         }
4288
4289         return 0;
4290 }
4291
4292 static int
4293 ixgbe_config_vf_rss(struct rte_eth_dev *dev)
4294 {
4295         struct ixgbe_hw *hw;
4296         uint32_t mrqc;
4297
4298         ixgbe_rss_configure(dev);
4299
4300         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4301
4302         /* MRQC: enable VF RSS */
4303         mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
4304         mrqc &= ~IXGBE_MRQC_MRQE_MASK;
4305         switch (RTE_ETH_DEV_SRIOV(dev).active) {
4306         case ETH_64_POOLS:
4307                 mrqc |= IXGBE_MRQC_VMDQRSS64EN;
4308                 break;
4309
4310         case ETH_32_POOLS:
4311                 mrqc |= IXGBE_MRQC_VMDQRSS32EN;
4312                 break;
4313
4314         default:
4315                 PMD_INIT_LOG(ERR, "Invalid pool number in IOV mode with VMDQ RSS");
4316                 return -EINVAL;
4317         }
4318
4319         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
4320
4321         return 0;
4322 }
4323
4324 static int
4325 ixgbe_config_vf_default(struct rte_eth_dev *dev)
4326 {
4327         struct ixgbe_hw *hw =
4328                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4329
4330         switch (RTE_ETH_DEV_SRIOV(dev).active) {
4331         case ETH_64_POOLS:
4332                 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
4333                         IXGBE_MRQC_VMDQEN);
4334                 break;
4335
4336         case ETH_32_POOLS:
4337                 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
4338                         IXGBE_MRQC_VMDQRT4TCEN);
4339                 break;
4340
4341         case ETH_16_POOLS:
4342                 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
4343                         IXGBE_MRQC_VMDQRT8TCEN);
4344                 break;
4345         default:
4346                 PMD_INIT_LOG(ERR,
4347                         "invalid pool number in IOV mode");
4348                 break;
4349         }
4350         return 0;
4351 }
4352
4353 static int
4354 ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
4355 {
4356         struct ixgbe_hw *hw =
4357                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4358
4359         if (hw->mac.type == ixgbe_mac_82598EB)
4360                 return 0;
4361
4362         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
4363                 /*
4364                  * SRIOV inactive scheme
4365                  * any DCB/RSS w/o VMDq multi-queue setting
4366                  */
4367                 switch (dev->data->dev_conf.rxmode.mq_mode) {
4368                 case ETH_MQ_RX_RSS:
4369                 case ETH_MQ_RX_DCB_RSS:
4370                 case ETH_MQ_RX_VMDQ_RSS:
4371                         ixgbe_rss_configure(dev);
4372                         break;
4373
4374                 case ETH_MQ_RX_VMDQ_DCB:
4375                         ixgbe_vmdq_dcb_configure(dev);
4376                         break;
4377
4378                 case ETH_MQ_RX_VMDQ_ONLY:
4379                         ixgbe_vmdq_rx_hw_configure(dev);
4380                         break;
4381
4382                 case ETH_MQ_RX_NONE:
4383                 default:
4384                         /* if mq_mode is none, disable rss mode.*/
4385                         ixgbe_rss_disable(dev);
4386                         break;
4387                 }
4388         } else {
4389                 /* SRIOV active scheme
4390                  * Support RSS together with SRIOV.
4391                  */
4392                 switch (dev->data->dev_conf.rxmode.mq_mode) {
4393                 case ETH_MQ_RX_RSS:
4394                 case ETH_MQ_RX_VMDQ_RSS:
4395                         ixgbe_config_vf_rss(dev);
4396                         break;
4397                 case ETH_MQ_RX_VMDQ_DCB:
4398                 case ETH_MQ_RX_DCB:
4399                 /* In SRIOV, the configuration is the same as VMDq case */
4400                         ixgbe_vmdq_dcb_configure(dev);
4401                         break;
4402                 /* DCB/RSS together with SRIOV is not supported */
4403                 case ETH_MQ_RX_VMDQ_DCB_RSS:
4404                 case ETH_MQ_RX_DCB_RSS:
4405                         PMD_INIT_LOG(ERR,
4406                                 "Could not support DCB/RSS with VMDq & SRIOV");
4407                         return -1;
4408                 default:
4409                         ixgbe_config_vf_default(dev);
4410                         break;
4411                 }
4412         }
4413
4414         return 0;
4415 }
4416
4417 static int
4418 ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)
4419 {
4420         struct ixgbe_hw *hw =
4421                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4422         uint32_t mtqc;
4423         uint32_t rttdcs;
4424
4425         if (hw->mac.type == ixgbe_mac_82598EB)
4426                 return 0;
4427
4428         /* disable arbiter before setting MTQC */
4429         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
4430         rttdcs |= IXGBE_RTTDCS_ARBDIS;
4431         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
4432
4433         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
4434                 /*
4435                  * SRIOV inactive scheme
4436                  * any DCB w/o VMDq multi-queue setting
4437                  */
4438                 if (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)
4439                         ixgbe_vmdq_tx_hw_configure(hw);
4440                 else {
4441                         mtqc = IXGBE_MTQC_64Q_1PB;
4442                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
4443                 }
4444         } else {
4445                 switch (RTE_ETH_DEV_SRIOV(dev).active) {
4446
4447                 /*
4448                  * SRIOV active scheme
4449                  * FIXME if support DCB together with VMDq & SRIOV
4450                  */
4451                 case ETH_64_POOLS:
4452                         mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
4453                         break;
4454                 case ETH_32_POOLS:
4455                         mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;
4456                         break;
4457                 case ETH_16_POOLS:
4458                         mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |
4459                                 IXGBE_MTQC_8TC_8TQ;
4460                         break;
4461                 default:
4462                         mtqc = IXGBE_MTQC_64Q_1PB;
4463                         PMD_INIT_LOG(ERR, "invalid pool number in IOV mode");
4464                 }
4465                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
4466         }
4467
4468         /* re-enable arbiter */
4469         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
4470         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
4471
4472         return 0;
4473 }
4474
4475 /**
4476  * ixgbe_get_rscctl_maxdesc - Calculate the RSCCTL[n].MAXDESC for PF
4477  *
4478  * Return the RSCCTL[n].MAXDESC for 82599 and x540 PF devices according to the
4479  * spec rev. 3.0 chapter 8.2.3.8.13.
4480  *
4481  * @pool Memory pool of the Rx queue
4482  */
4483 static inline uint32_t
4484 ixgbe_get_rscctl_maxdesc(struct rte_mempool *pool)
4485 {
4486         struct rte_pktmbuf_pool_private *mp_priv = rte_mempool_get_priv(pool);
4487
4488         /* MAXDESC * SRRCTL.BSIZEPKT must not exceed 64 KB minus one */
4489         uint16_t maxdesc =
4490                 IPV4_MAX_PKT_LEN /
4491                         (mp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM);
4492
4493         if (maxdesc >= 16)
4494                 return IXGBE_RSCCTL_MAXDESC_16;
4495         else if (maxdesc >= 8)
4496                 return IXGBE_RSCCTL_MAXDESC_8;
4497         else if (maxdesc >= 4)
4498                 return IXGBE_RSCCTL_MAXDESC_4;
4499         else
4500                 return IXGBE_RSCCTL_MAXDESC_1;
4501 }
4502
4503 /**
4504  * ixgbe_set_ivar - Setup the correct IVAR register for a particular MSIX
4505  * interrupt
4506  *
4507  * (Taken from FreeBSD tree)
4508  * (yes this is all very magic and confusing :)
4509  *
4510  * @dev port handle
4511  * @entry the register array entry
4512  * @vector the MSIX vector for this queue
4513  * @type RX/TX/MISC
4514  */
4515 static void
4516 ixgbe_set_ivar(struct rte_eth_dev *dev, u8 entry, u8 vector, s8 type)
4517 {
4518         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4519         u32 ivar, index;
4520
4521         vector |= IXGBE_IVAR_ALLOC_VAL;
4522
4523         switch (hw->mac.type) {
4524
4525         case ixgbe_mac_82598EB:
4526                 if (type == -1)
4527                         entry = IXGBE_IVAR_OTHER_CAUSES_INDEX;
4528                 else
4529                         entry += (type * 64);
4530                 index = (entry >> 2) & 0x1F;
4531                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
4532                 ivar &= ~(0xFF << (8 * (entry & 0x3)));
4533                 ivar |= (vector << (8 * (entry & 0x3)));
4534                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
4535                 break;
4536
4537         case ixgbe_mac_82599EB:
4538         case ixgbe_mac_X540:
4539                 if (type == -1) { /* MISC IVAR */
4540                         index = (entry & 1) * 8;
4541                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4542                         ivar &= ~(0xFF << index);
4543                         ivar |= (vector << index);
4544                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, ivar);
4545                 } else {        /* RX/TX IVARS */
4546                         index = (16 * (entry & 1)) + (8 * type);
4547                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(entry >> 1));
4548                         ivar &= ~(0xFF << index);
4549                         ivar |= (vector << index);
4550                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(entry >> 1), ivar);
4551                 }
4552
4553                 break;
4554
4555         default:
4556                 break;
4557         }
4558 }
4559
4560 void __attribute__((cold))
4561 ixgbe_set_rx_function(struct rte_eth_dev *dev)
4562 {
4563         uint16_t i, rx_using_sse;
4564         struct ixgbe_adapter *adapter =
4565                 (struct ixgbe_adapter *)dev->data->dev_private;
4566
4567         /*
4568          * In order to allow Vector Rx there are a few configuration
4569          * conditions to be met and Rx Bulk Allocation should be allowed.
4570          */
4571         if (ixgbe_rx_vec_dev_conf_condition_check(dev) ||
4572             !adapter->rx_bulk_alloc_allowed) {
4573                 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet Vector Rx "
4574                                     "preconditions or RTE_IXGBE_INC_VECTOR is "
4575                                     "not enabled",
4576                              dev->data->port_id);
4577
4578                 adapter->rx_vec_allowed = false;
4579         }
4580
4581         /*
4582          * Initialize the appropriate LRO callback.
4583          *
4584          * If all queues satisfy the bulk allocation preconditions
4585          * (hw->rx_bulk_alloc_allowed is TRUE) then we may use bulk allocation.
4586          * Otherwise use a single allocation version.
4587          */
4588         if (dev->data->lro) {
4589                 if (adapter->rx_bulk_alloc_allowed) {
4590                         PMD_INIT_LOG(DEBUG, "LRO is requested. Using a bulk "
4591                                            "allocation version");
4592                         dev->rx_pkt_burst = ixgbe_recv_pkts_lro_bulk_alloc;
4593                 } else {
4594                         PMD_INIT_LOG(DEBUG, "LRO is requested. Using a single "
4595                                            "allocation version");
4596                         dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
4597                 }
4598         } else if (dev->data->scattered_rx) {
4599                 /*
4600                  * Set the non-LRO scattered callback: there are Vector and
4601                  * single allocation versions.
4602                  */
4603                 if (adapter->rx_vec_allowed) {
4604                         PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
4605                                             "callback (port=%d).",
4606                                      dev->data->port_id);
4607
4608                         dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
4609                 } else if (adapter->rx_bulk_alloc_allowed) {
4610                         PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
4611                                            "allocation callback (port=%d).",
4612                                      dev->data->port_id);
4613                         dev->rx_pkt_burst = ixgbe_recv_pkts_lro_bulk_alloc;
4614                 } else {
4615                         PMD_INIT_LOG(DEBUG, "Using Regualr (non-vector, "
4616                                             "single allocation) "
4617                                             "Scattered Rx callback "
4618                                             "(port=%d).",
4619                                      dev->data->port_id);
4620
4621                         dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
4622                 }
4623         /*
4624          * Below we set "simple" callbacks according to port/queues parameters.
4625          * If parameters allow we are going to choose between the following
4626          * callbacks:
4627          *    - Vector
4628          *    - Bulk Allocation
4629          *    - Single buffer allocation (the simplest one)
4630          */
4631         } else if (adapter->rx_vec_allowed) {
4632                 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
4633                                     "burst size no less than %d (port=%d).",
4634                              RTE_IXGBE_DESCS_PER_LOOP,
4635                              dev->data->port_id);
4636
4637                 dev->rx_pkt_burst = ixgbe_recv_pkts_vec;
4638         } else if (adapter->rx_bulk_alloc_allowed) {
4639                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
4640                                     "satisfied. Rx Burst Bulk Alloc function "
4641                                     "will be used on port=%d.",
4642                              dev->data->port_id);
4643
4644                 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
4645         } else {
4646                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
4647                                     "satisfied, or Scattered Rx is requested "
4648                                     "(port=%d).",
4649                              dev->data->port_id);
4650
4651                 dev->rx_pkt_burst = ixgbe_recv_pkts;
4652         }
4653
4654         /* Propagate information about RX function choice through all queues. */
4655
4656         rx_using_sse =
4657                 (dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec ||
4658                 dev->rx_pkt_burst == ixgbe_recv_pkts_vec);
4659
4660         for (i = 0; i < dev->data->nb_rx_queues; i++) {
4661                 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
4662
4663                 rxq->rx_using_sse = rx_using_sse;
4664 #ifdef RTE_LIBRTE_SECURITY
4665                 rxq->using_ipsec = !!(dev->data->dev_conf.rxmode.offloads &
4666                                 DEV_RX_OFFLOAD_SECURITY);
4667 #endif
4668         }
4669 }
4670
4671 /**
4672  * ixgbe_set_rsc - configure RSC related port HW registers
4673  *
4674  * Configures the port's RSC related registers according to the 4.6.7.2 chapter
4675  * of 82599 Spec (x540 configuration is virtually the same).
4676  *
4677  * @dev port handle
4678  *
4679  * Returns 0 in case of success or a non-zero error code
4680  */
4681 static int
4682 ixgbe_set_rsc(struct rte_eth_dev *dev)
4683 {
4684         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
4685         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4686         struct rte_eth_dev_info dev_info = { 0 };
4687         bool rsc_capable = false;
4688         uint16_t i;
4689         uint32_t rdrxctl;
4690         uint32_t rfctl;
4691
4692         /* Sanity check */
4693         dev->dev_ops->dev_infos_get(dev, &dev_info);
4694         if (dev_info.rx_offload_capa & DEV_RX_OFFLOAD_TCP_LRO)
4695                 rsc_capable = true;
4696
4697         if (!rsc_capable && (rx_conf->offloads & DEV_RX_OFFLOAD_TCP_LRO)) {
4698                 PMD_INIT_LOG(CRIT, "LRO is requested on HW that doesn't "
4699                                    "support it");
4700                 return -EINVAL;
4701         }
4702
4703         /* RSC global configuration (chapter 4.6.7.2.1 of 82599 Spec) */
4704
4705         if (!(rx_conf->offloads & DEV_RX_OFFLOAD_CRC_STRIP) &&
4706              (rx_conf->offloads & DEV_RX_OFFLOAD_TCP_LRO)) {
4707                 /*
4708                  * According to chapter of 4.6.7.2.1 of the Spec Rev.
4709                  * 3.0 RSC configuration requires HW CRC stripping being
4710                  * enabled. If user requested both HW CRC stripping off
4711                  * and RSC on - return an error.
4712                  */
4713                 PMD_INIT_LOG(CRIT, "LRO can't be enabled when HW CRC "
4714                                     "is disabled");
4715                 return -EINVAL;
4716         }
4717
4718         /* RFCTL configuration  */
4719         rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
4720         if ((rsc_capable) && (rx_conf->offloads & DEV_RX_OFFLOAD_TCP_LRO))
4721                 /*
4722                  * Since NFS packets coalescing is not supported - clear
4723                  * RFCTL.NFSW_DIS and RFCTL.NFSR_DIS when RSC is
4724                  * enabled.
4725                  */
4726                 rfctl &= ~(IXGBE_RFCTL_RSC_DIS | IXGBE_RFCTL_NFSW_DIS |
4727                            IXGBE_RFCTL_NFSR_DIS);
4728         else
4729                 rfctl |= IXGBE_RFCTL_RSC_DIS;
4730         IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
4731
4732         /* If LRO hasn't been requested - we are done here. */
4733         if (!(rx_conf->offloads & DEV_RX_OFFLOAD_TCP_LRO))
4734                 return 0;
4735
4736         /* Set RDRXCTL.RSCACKC bit */
4737         rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4738         rdrxctl |= IXGBE_RDRXCTL_RSCACKC;
4739         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4740
4741         /* Per-queue RSC configuration (chapter 4.6.7.2.2 of 82599 Spec) */
4742         for (i = 0; i < dev->data->nb_rx_queues; i++) {
4743                 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
4744                 uint32_t srrctl =
4745                         IXGBE_READ_REG(hw, IXGBE_SRRCTL(rxq->reg_idx));
4746                 uint32_t rscctl =
4747                         IXGBE_READ_REG(hw, IXGBE_RSCCTL(rxq->reg_idx));
4748                 uint32_t psrtype =
4749                         IXGBE_READ_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx));
4750                 uint32_t eitr =
4751                         IXGBE_READ_REG(hw, IXGBE_EITR(rxq->reg_idx));
4752
4753                 /*
4754                  * ixgbe PMD doesn't support header-split at the moment.
4755                  *
4756                  * Following the 4.6.7.2.1 chapter of the 82599/x540
4757                  * Spec if RSC is enabled the SRRCTL[n].BSIZEHEADER
4758                  * should be configured even if header split is not
4759                  * enabled. We will configure it 128 bytes following the
4760                  * recommendation in the spec.
4761                  */
4762                 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
4763                 srrctl |= (128 << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4764                                             IXGBE_SRRCTL_BSIZEHDR_MASK;
4765
4766                 /*
4767                  * TODO: Consider setting the Receive Descriptor Minimum
4768                  * Threshold Size for an RSC case. This is not an obviously
4769                  * beneficiary option but the one worth considering...
4770                  */
4771
4772                 rscctl |= IXGBE_RSCCTL_RSCEN;
4773                 rscctl |= ixgbe_get_rscctl_maxdesc(rxq->mb_pool);
4774                 psrtype |= IXGBE_PSRTYPE_TCPHDR;
4775
4776                 /*
4777                  * RSC: Set ITR interval corresponding to 2K ints/s.
4778                  *
4779                  * Full-sized RSC aggregations for a 10Gb/s link will
4780                  * arrive at about 20K aggregation/s rate.
4781                  *
4782                  * 2K inst/s rate will make only 10% of the
4783                  * aggregations to be closed due to the interrupt timer
4784                  * expiration for a streaming at wire-speed case.
4785                  *
4786                  * For a sparse streaming case this setting will yield
4787                  * at most 500us latency for a single RSC aggregation.
4788                  */
4789                 eitr &= ~IXGBE_EITR_ITR_INT_MASK;
4790                 eitr |= IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT);
4791                 eitr |= IXGBE_EITR_CNT_WDIS;
4792
4793                 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
4794                 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(rxq->reg_idx), rscctl);
4795                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
4796                 IXGBE_WRITE_REG(hw, IXGBE_EITR(rxq->reg_idx), eitr);
4797
4798                 /*
4799                  * RSC requires the mapping of the queue to the
4800                  * interrupt vector.
4801                  */
4802                 ixgbe_set_ivar(dev, rxq->reg_idx, i, 0);
4803         }
4804
4805         dev->data->lro = 1;
4806
4807         PMD_INIT_LOG(DEBUG, "enabling LRO mode");
4808
4809         return 0;
4810 }
4811
4812 /*
4813  * Initializes Receive Unit.
4814  */
4815 int __attribute__((cold))
4816 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
4817 {
4818         struct ixgbe_hw     *hw;
4819         struct ixgbe_rx_queue *rxq;
4820         uint64_t bus_addr;
4821         uint32_t rxctrl;
4822         uint32_t fctrl;
4823         uint32_t hlreg0;
4824         uint32_t maxfrs;
4825         uint32_t srrctl;
4826         uint32_t rdrxctl;
4827         uint32_t rxcsum;
4828         uint16_t buf_size;
4829         uint16_t i;
4830         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
4831         int rc;
4832
4833         PMD_INIT_FUNC_TRACE();
4834         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4835
4836         /*
4837          * Make sure receives are disabled while setting
4838          * up the RX context (registers, descriptor rings, etc.).
4839          */
4840         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4841         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4842
4843         /* Enable receipt of broadcasted frames */
4844         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4845         fctrl |= IXGBE_FCTRL_BAM;
4846         fctrl |= IXGBE_FCTRL_DPF;
4847         fctrl |= IXGBE_FCTRL_PMCF;
4848         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4849
4850         /*
4851          * Configure CRC stripping, if any.
4852          */
4853         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4854         if (rx_conf->offloads & DEV_RX_OFFLOAD_CRC_STRIP)
4855                 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
4856         else
4857                 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
4858
4859         /*
4860          * Configure jumbo frame support, if any.
4861          */
4862         if (rx_conf->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
4863                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4864                 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4865                 maxfrs &= 0x0000FFFF;
4866                 maxfrs |= (rx_conf->max_rx_pkt_len << 16);
4867                 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4868         } else
4869                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4870
4871         /*
4872          * If loopback mode is configured for 82599, set LPBK bit.
4873          */
4874         if (hw->mac.type == ixgbe_mac_82599EB &&
4875                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
4876                 hlreg0 |= IXGBE_HLREG0_LPBK;
4877         else
4878                 hlreg0 &= ~IXGBE_HLREG0_LPBK;
4879
4880         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4881
4882         /*
4883          * Assume no header split and no VLAN strip support
4884          * on any Rx queue first .
4885          */
4886         rx_conf->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
4887         /* Setup RX queues */
4888         for (i = 0; i < dev->data->nb_rx_queues; i++) {
4889                 rxq = dev->data->rx_queues[i];
4890
4891                 /*
4892                  * Reset crc_len in case it was changed after queue setup by a
4893                  * call to configure.
4894                  */
4895                 rxq->crc_len = (rx_conf->offloads & DEV_RX_OFFLOAD_CRC_STRIP) ?
4896                                 0 : ETHER_CRC_LEN;
4897
4898                 /* Setup the Base and Length of the Rx Descriptor Rings */
4899                 bus_addr = rxq->rx_ring_phys_addr;
4900                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),
4901                                 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4902                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),
4903                                 (uint32_t)(bus_addr >> 32));
4904                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),
4905                                 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
4906                 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
4907                 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);
4908
4909                 /* Configure the SRRCTL register */
4910                 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
4911
4912                 /* Set if packets are dropped when no descriptors available */
4913                 if (rxq->drop_en)
4914                         srrctl |= IXGBE_SRRCTL_DROP_EN;
4915
4916                 /*
4917                  * Configure the RX buffer size in the BSIZEPACKET field of
4918                  * the SRRCTL register of the queue.
4919                  * The value is in 1 KB resolution. Valid values can be from
4920                  * 1 KB to 16 KB.
4921                  */
4922                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
4923                         RTE_PKTMBUF_HEADROOM);
4924                 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
4925                            IXGBE_SRRCTL_BSIZEPKT_MASK);
4926
4927                 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
4928
4929                 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
4930                                        IXGBE_SRRCTL_BSIZEPKT_SHIFT);
4931
4932                 /* It adds dual VLAN length for supporting dual VLAN */
4933                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len +
4934                                             2 * IXGBE_VLAN_TAG_SIZE > buf_size)
4935                         dev->data->scattered_rx = 1;
4936                 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4937                         rx_conf->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
4938         }
4939
4940         if (rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER)
4941                 dev->data->scattered_rx = 1;
4942
4943         /*
4944          * Device configured with multiple RX queues.
4945          */
4946         ixgbe_dev_mq_rx_configure(dev);
4947
4948         /*
4949          * Setup the Checksum Register.
4950          * Disable Full-Packet Checksum which is mutually exclusive with RSS.
4951          * Enable IP/L4 checkum computation by hardware if requested to do so.
4952          */
4953         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
4954         rxcsum |= IXGBE_RXCSUM_PCSD;
4955         if (rx_conf->offloads & DEV_RX_OFFLOAD_CHECKSUM)
4956                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
4957         else
4958                 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
4959
4960         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
4961
4962         if (hw->mac.type == ixgbe_mac_82599EB ||
4963             hw->mac.type == ixgbe_mac_X540) {
4964                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4965                 if (rx_conf->offloads & DEV_RX_OFFLOAD_CRC_STRIP)
4966                         rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
4967                 else
4968                         rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
4969                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
4970                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4971         }
4972
4973         rc = ixgbe_set_rsc(dev);
4974         if (rc)
4975                 return rc;
4976
4977         ixgbe_set_rx_function(dev);
4978
4979         return 0;
4980 }
4981
4982 /*
4983  * Initializes Transmit Unit.
4984  */
4985 void __attribute__((cold))
4986 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
4987 {
4988         struct ixgbe_hw     *hw;
4989         struct ixgbe_tx_queue *txq;
4990         uint64_t bus_addr;
4991         uint32_t hlreg0;
4992         uint32_t txctrl;
4993         uint16_t i;
4994
4995         PMD_INIT_FUNC_TRACE();
4996         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4997
4998         /* Enable TX CRC (checksum offload requirement) and hw padding
4999          * (TSO requirement)
5000          */
5001         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5002         hlreg0 |= (IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_TXPADEN);
5003         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5004
5005         /* Setup the Base and Length of the Tx Descriptor Rings */
5006         for (i = 0; i < dev->data->nb_tx_queues; i++) {
5007                 txq = dev->data->tx_queues[i];
5008
5009                 bus_addr = txq->tx_ring_phys_addr;
5010                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),
5011                                 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
5012                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),
5013                                 (uint32_t)(bus_addr >> 32));
5014                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),
5015                                 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
5016                 /* Setup the HW Tx Head and TX Tail descriptor pointers */
5017                 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
5018                 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
5019
5020                 /*
5021                  * Disable Tx Head Writeback RO bit, since this hoses
5022                  * bookkeeping if things aren't delivered in order.
5023                  */
5024                 switch (hw->mac.type) {
5025                 case ixgbe_mac_82598EB:
5026                         txctrl = IXGBE_READ_REG(hw,
5027                                                 IXGBE_DCA_TXCTRL(txq->reg_idx));
5028                         txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
5029                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),
5030                                         txctrl);
5031                         break;
5032
5033                 case ixgbe_mac_82599EB:
5034                 case ixgbe_mac_X540:
5035                 case ixgbe_mac_X550:
5036                 case ixgbe_mac_X550EM_x:
5037                 case ixgbe_mac_X550EM_a:
5038                 default:
5039                         txctrl = IXGBE_READ_REG(hw,
5040                                                 IXGBE_DCA_TXCTRL_82599(txq->reg_idx));
5041                         txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
5042                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),
5043                                         txctrl);
5044                         break;
5045                 }
5046         }
5047
5048         /* Device configured with multiple TX queues. */
5049         ixgbe_dev_mq_tx_configure(dev);
5050 }
5051
5052 /*
5053  * Set up link for 82599 loopback mode Tx->Rx.
5054  */
5055 static inline void __attribute__((cold))
5056 ixgbe_setup_loopback_link_82599(struct ixgbe_hw *hw)
5057 {
5058         PMD_INIT_FUNC_TRACE();
5059
5060         if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
5061                 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM) !=
5062                                 IXGBE_SUCCESS) {
5063                         PMD_INIT_LOG(ERR, "Could not enable loopback mode");
5064                         /* ignore error */
5065                         return;
5066                 }
5067         }
5068
5069         /* Restart link */
5070         IXGBE_WRITE_REG(hw,
5071                         IXGBE_AUTOC,
5072                         IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU);
5073         ixgbe_reset_pipeline_82599(hw);
5074
5075         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
5076         msec_delay(50);
5077 }
5078
5079
5080 /*
5081  * Start Transmit and Receive Units.
5082  */
5083 int __attribute__((cold))
5084 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
5085 {
5086         struct ixgbe_hw     *hw;
5087         struct ixgbe_tx_queue *txq;
5088         struct ixgbe_rx_queue *rxq;
5089         uint32_t txdctl;
5090         uint32_t dmatxctl;
5091         uint32_t rxctrl;
5092         uint16_t i;
5093         int ret = 0;
5094
5095         PMD_INIT_FUNC_TRACE();
5096         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5097
5098         for (i = 0; i < dev->data->nb_tx_queues; i++) {
5099                 txq = dev->data->tx_queues[i];
5100                 /* Setup Transmit Threshold Registers */
5101                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
5102                 txdctl |= txq->pthresh & 0x7F;
5103                 txdctl |= ((txq->hthresh & 0x7F) << 8);
5104                 txdctl |= ((txq->wthresh & 0x7F) << 16);
5105                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
5106         }
5107
5108         if (hw->mac.type != ixgbe_mac_82598EB) {
5109                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
5110                 dmatxctl |= IXGBE_DMATXCTL_TE;
5111                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
5112         }
5113
5114         for (i = 0; i < dev->data->nb_tx_queues; i++) {
5115                 txq = dev->data->tx_queues[i];
5116                 if (!txq->tx_deferred_start) {
5117                         ret = ixgbe_dev_tx_queue_start(dev, i);
5118                         if (ret < 0)
5119                                 return ret;
5120                 }
5121         }
5122
5123         for (i = 0; i < dev->data->nb_rx_queues; i++) {
5124                 rxq = dev->data->rx_queues[i];
5125                 if (!rxq->rx_deferred_start) {
5126                         ret = ixgbe_dev_rx_queue_start(dev, i);
5127                         if (ret < 0)
5128                                 return ret;
5129                 }
5130         }
5131
5132         /* Enable Receive engine */
5133         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5134         if (hw->mac.type == ixgbe_mac_82598EB)
5135                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
5136         rxctrl |= IXGBE_RXCTRL_RXEN;
5137         hw->mac.ops.enable_rx_dma(hw, rxctrl);
5138
5139         /* If loopback mode is enabled for 82599, set up the link accordingly */
5140         if (hw->mac.type == ixgbe_mac_82599EB &&
5141                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
5142                 ixgbe_setup_loopback_link_82599(hw);
5143
5144 #ifdef RTE_LIBRTE_SECURITY
5145         if ((dev->data->dev_conf.rxmode.offloads &
5146                         DEV_RX_OFFLOAD_SECURITY) ||
5147                 (dev->data->dev_conf.txmode.offloads &
5148                         DEV_TX_OFFLOAD_SECURITY)) {
5149                 ret = ixgbe_crypto_enable_ipsec(dev);
5150                 if (ret != 0) {
5151                         PMD_DRV_LOG(ERR,
5152                                     "ixgbe_crypto_enable_ipsec fails with %d.",
5153                                     ret);
5154                         return ret;
5155                 }
5156         }
5157 #endif
5158
5159         return 0;
5160 }
5161
5162 /*
5163  * Start Receive Units for specified queue.
5164  */
5165 int __attribute__((cold))
5166 ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
5167 {
5168         struct ixgbe_hw     *hw;
5169         struct ixgbe_rx_queue *rxq;
5170         uint32_t rxdctl;
5171         int poll_ms;
5172
5173         PMD_INIT_FUNC_TRACE();
5174         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5175
5176         if (rx_queue_id < dev->data->nb_rx_queues) {
5177                 rxq = dev->data->rx_queues[rx_queue_id];
5178
5179                 /* Allocate buffers for descriptor rings */
5180                 if (ixgbe_alloc_rx_queue_mbufs(rxq) != 0) {
5181                         PMD_INIT_LOG(ERR, "Could not alloc mbuf for queue:%d",
5182                                      rx_queue_id);
5183                         return -1;
5184                 }
5185                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
5186                 rxdctl |= IXGBE_RXDCTL_ENABLE;
5187                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
5188
5189                 /* Wait until RX Enable ready */
5190                 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
5191                 do {
5192                         rte_delay_ms(1);
5193                         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
5194                 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
5195                 if (!poll_ms)
5196                         PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d",
5197                                      rx_queue_id);
5198                 rte_wmb();
5199                 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
5200                 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
5201                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
5202         } else
5203                 return -1;
5204
5205         return 0;
5206 }
5207
5208 /*
5209  * Stop Receive Units for specified queue.
5210  */
5211 int __attribute__((cold))
5212 ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
5213 {
5214         struct ixgbe_hw     *hw;
5215         struct ixgbe_adapter *adapter =
5216                 (struct ixgbe_adapter *)dev->data->dev_private;
5217         struct ixgbe_rx_queue *rxq;
5218         uint32_t rxdctl;
5219         int poll_ms;
5220
5221         PMD_INIT_FUNC_TRACE();
5222         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5223
5224         if (rx_queue_id < dev->data->nb_rx_queues) {
5225                 rxq = dev->data->rx_queues[rx_queue_id];
5226
5227                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
5228                 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
5229                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
5230
5231                 /* Wait until RX Enable bit clear */
5232                 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
5233                 do {
5234                         rte_delay_ms(1);
5235                         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
5236                 } while (--poll_ms && (rxdctl & IXGBE_RXDCTL_ENABLE));
5237                 if (!poll_ms)
5238                         PMD_INIT_LOG(ERR, "Could not disable Rx Queue %d",
5239                                      rx_queue_id);
5240
5241                 rte_delay_us(RTE_IXGBE_WAIT_100_US);
5242
5243                 ixgbe_rx_queue_release_mbufs(rxq);
5244                 ixgbe_reset_rx_queue(adapter, rxq);
5245                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
5246         } else
5247                 return -1;
5248
5249         return 0;
5250 }
5251
5252
5253 /*
5254  * Start Transmit Units for specified queue.
5255  */
5256 int __attribute__((cold))
5257 ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
5258 {
5259         struct ixgbe_hw     *hw;
5260         struct ixgbe_tx_queue *txq;
5261         uint32_t txdctl;
5262         int poll_ms;
5263
5264         PMD_INIT_FUNC_TRACE();
5265         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5266
5267         if (tx_queue_id < dev->data->nb_tx_queues) {
5268                 txq = dev->data->tx_queues[tx_queue_id];
5269                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
5270                 txdctl |= IXGBE_TXDCTL_ENABLE;
5271                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
5272
5273                 /* Wait until TX Enable ready */
5274                 if (hw->mac.type == ixgbe_mac_82599EB) {
5275                         poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
5276                         do {
5277                                 rte_delay_ms(1);
5278                                 txdctl = IXGBE_READ_REG(hw,
5279                                         IXGBE_TXDCTL(txq->reg_idx));
5280                         } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
5281                         if (!poll_ms)
5282                                 PMD_INIT_LOG(ERR, "Could not enable "
5283                                              "Tx Queue %d", tx_queue_id);
5284                 }
5285                 rte_wmb();
5286                 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
5287                 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
5288                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
5289         } else
5290                 return -1;
5291
5292         return 0;
5293 }
5294
5295 /*
5296  * Stop Transmit Units for specified queue.
5297  */
5298 int __attribute__((cold))
5299 ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
5300 {
5301         struct ixgbe_hw     *hw;
5302         struct ixgbe_tx_queue *txq;
5303         uint32_t txdctl;
5304         uint32_t txtdh, txtdt;
5305         int poll_ms;
5306
5307         PMD_INIT_FUNC_TRACE();
5308         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5309
5310         if (tx_queue_id >= dev->data->nb_tx_queues)
5311                 return -1;
5312
5313         txq = dev->data->tx_queues[tx_queue_id];
5314
5315         /* Wait until TX queue is empty */
5316         if (hw->mac.type == ixgbe_mac_82599EB) {
5317                 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
5318                 do {
5319                         rte_delay_us(RTE_IXGBE_WAIT_100_US);
5320                         txtdh = IXGBE_READ_REG(hw,
5321                                                IXGBE_TDH(txq->reg_idx));
5322                         txtdt = IXGBE_READ_REG(hw,
5323                                                IXGBE_TDT(txq->reg_idx));
5324                 } while (--poll_ms && (txtdh != txtdt));
5325                 if (!poll_ms)
5326                         PMD_INIT_LOG(ERR, "Tx Queue %d is not empty "
5327                                      "when stopping.", tx_queue_id);
5328         }
5329
5330         txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
5331         txdctl &= ~IXGBE_TXDCTL_ENABLE;
5332         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
5333
5334         /* Wait until TX Enable bit clear */
5335         if (hw->mac.type == ixgbe_mac_82599EB) {
5336                 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
5337                 do {
5338                         rte_delay_ms(1);
5339                         txdctl = IXGBE_READ_REG(hw,
5340                                                 IXGBE_TXDCTL(txq->reg_idx));
5341                 } while (--poll_ms && (txdctl & IXGBE_TXDCTL_ENABLE));
5342                 if (!poll_ms)
5343                         PMD_INIT_LOG(ERR, "Could not disable "
5344                                      "Tx Queue %d", tx_queue_id);
5345         }
5346
5347         if (txq->ops != NULL) {
5348                 txq->ops->release_mbufs(txq);
5349                 txq->ops->reset(txq);
5350         }
5351         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
5352
5353         return 0;
5354 }
5355
5356 void
5357 ixgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
5358         struct rte_eth_rxq_info *qinfo)
5359 {
5360         struct ixgbe_rx_queue *rxq;
5361
5362         rxq = dev->data->rx_queues[queue_id];
5363
5364         qinfo->mp = rxq->mb_pool;
5365         qinfo->scattered_rx = dev->data->scattered_rx;
5366         qinfo->nb_desc = rxq->nb_rx_desc;
5367
5368         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
5369         qinfo->conf.rx_drop_en = rxq->drop_en;
5370         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
5371         qinfo->conf.offloads = rxq->offloads;
5372 }
5373
5374 void
5375 ixgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
5376         struct rte_eth_txq_info *qinfo)
5377 {
5378         struct ixgbe_tx_queue *txq;
5379
5380         txq = dev->data->tx_queues[queue_id];
5381
5382         qinfo->nb_desc = txq->nb_tx_desc;
5383
5384         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
5385         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
5386         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
5387
5388         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
5389         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
5390         qinfo->conf.offloads = txq->offloads;
5391         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
5392 }
5393
5394 /*
5395  * [VF] Initializes Receive Unit.
5396  */
5397 int __attribute__((cold))
5398 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
5399 {
5400         struct ixgbe_hw     *hw;
5401         struct ixgbe_rx_queue *rxq;
5402         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
5403         uint64_t bus_addr;
5404         uint32_t srrctl, psrtype = 0;
5405         uint16_t buf_size;
5406         uint16_t i;
5407         int ret;
5408
5409         PMD_INIT_FUNC_TRACE();
5410         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5411
5412         if (rte_is_power_of_2(dev->data->nb_rx_queues) == 0) {
5413                 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
5414                         "it should be power of 2");
5415                 return -1;
5416         }
5417
5418         if (dev->data->nb_rx_queues > hw->mac.max_rx_queues) {
5419                 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
5420                         "it should be equal to or less than %d",
5421                         hw->mac.max_rx_queues);
5422                 return -1;
5423         }
5424
5425         /*
5426          * When the VF driver issues a IXGBE_VF_RESET request, the PF driver
5427          * disables the VF receipt of packets if the PF MTU is > 1500.
5428          * This is done to deal with 82599 limitations that imposes
5429          * the PF and all VFs to share the same MTU.
5430          * Then, the PF driver enables again the VF receipt of packet when
5431          * the VF driver issues a IXGBE_VF_SET_LPE request.
5432          * In the meantime, the VF device cannot be used, even if the VF driver
5433          * and the Guest VM network stack are ready to accept packets with a
5434          * size up to the PF MTU.
5435          * As a work-around to this PF behaviour, force the call to
5436          * ixgbevf_rlpml_set_vf even if jumbo frames are not used. This way,
5437          * VF packets received can work in all cases.
5438          */
5439         ixgbevf_rlpml_set_vf(hw,
5440                 (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len);
5441
5442         /*
5443          * Assume no header split and no VLAN strip support
5444          * on any Rx queue first .
5445          */
5446         rxmode->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
5447         /* Setup RX queues */
5448         for (i = 0; i < dev->data->nb_rx_queues; i++) {
5449                 rxq = dev->data->rx_queues[i];
5450
5451                 /* Allocate buffers for descriptor rings */
5452                 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
5453                 if (ret)
5454                         return ret;
5455
5456                 /* Setup the Base and Length of the Rx Descriptor Rings */
5457                 bus_addr = rxq->rx_ring_phys_addr;
5458
5459                 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
5460                                 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
5461                 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
5462                                 (uint32_t)(bus_addr >> 32));
5463                 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
5464                                 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
5465                 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
5466                 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
5467
5468
5469                 /* Configure the SRRCTL register */
5470                 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
5471
5472                 /* Set if packets are dropped when no descriptors available */
5473                 if (rxq->drop_en)
5474                         srrctl |= IXGBE_SRRCTL_DROP_EN;
5475
5476                 /*
5477                  * Configure the RX buffer size in the BSIZEPACKET field of
5478                  * the SRRCTL register of the queue.
5479                  * The value is in 1 KB resolution. Valid values can be from
5480                  * 1 KB to 16 KB.
5481                  */
5482                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
5483                         RTE_PKTMBUF_HEADROOM);
5484                 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
5485                            IXGBE_SRRCTL_BSIZEPKT_MASK);
5486
5487                 /*
5488                  * VF modification to write virtual function SRRCTL register
5489                  */
5490                 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
5491
5492                 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
5493                                        IXGBE_SRRCTL_BSIZEPKT_SHIFT);
5494
5495                 if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER ||
5496                     /* It adds dual VLAN length for supporting dual VLAN */
5497                     (rxmode->max_rx_pkt_len +
5498                                 2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {
5499                         if (!dev->data->scattered_rx)
5500                                 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
5501                         dev->data->scattered_rx = 1;
5502                 }
5503
5504                 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
5505                         rxmode->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
5506         }
5507
5508         /* Set RQPL for VF RSS according to max Rx queue */
5509         psrtype |= (dev->data->nb_rx_queues >> 1) <<
5510                 IXGBE_PSRTYPE_RQPL_SHIFT;
5511         IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, psrtype);
5512
5513         ixgbe_set_rx_function(dev);
5514
5515         return 0;
5516 }
5517
5518 /*
5519  * [VF] Initializes Transmit Unit.
5520  */
5521 void __attribute__((cold))
5522 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
5523 {
5524         struct ixgbe_hw     *hw;
5525         struct ixgbe_tx_queue *txq;
5526         uint64_t bus_addr;
5527         uint32_t txctrl;
5528         uint16_t i;
5529
5530         PMD_INIT_FUNC_TRACE();
5531         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5532
5533         /* Setup the Base and Length of the Tx Descriptor Rings */
5534         for (i = 0; i < dev->data->nb_tx_queues; i++) {
5535                 txq = dev->data->tx_queues[i];
5536                 bus_addr = txq->tx_ring_phys_addr;
5537                 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
5538                                 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
5539                 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
5540                                 (uint32_t)(bus_addr >> 32));
5541                 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
5542                                 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
5543                 /* Setup the HW Tx Head and TX Tail descriptor pointers */
5544                 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
5545                 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
5546
5547                 /*
5548                  * Disable Tx Head Writeback RO bit, since this hoses
5549                  * bookkeeping if things aren't delivered in order.
5550                  */
5551                 txctrl = IXGBE_READ_REG(hw,
5552                                 IXGBE_VFDCA_TXCTRL(i));
5553                 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
5554                 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
5555                                 txctrl);
5556         }
5557 }
5558
5559 /*
5560  * [VF] Start Transmit and Receive Units.
5561  */
5562 void __attribute__((cold))
5563 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
5564 {
5565         struct ixgbe_hw     *hw;
5566         struct ixgbe_tx_queue *txq;
5567         struct ixgbe_rx_queue *rxq;
5568         uint32_t txdctl;
5569         uint32_t rxdctl;
5570         uint16_t i;
5571         int poll_ms;
5572
5573         PMD_INIT_FUNC_TRACE();
5574         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5575
5576         for (i = 0; i < dev->data->nb_tx_queues; i++) {
5577                 txq = dev->data->tx_queues[i];
5578                 /* Setup Transmit Threshold Registers */
5579                 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
5580                 txdctl |= txq->pthresh & 0x7F;
5581                 txdctl |= ((txq->hthresh & 0x7F) << 8);
5582                 txdctl |= ((txq->wthresh & 0x7F) << 16);
5583                 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
5584         }
5585
5586         for (i = 0; i < dev->data->nb_tx_queues; i++) {
5587
5588                 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
5589                 txdctl |= IXGBE_TXDCTL_ENABLE;
5590                 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
5591
5592                 poll_ms = 10;
5593                 /* Wait until TX Enable ready */
5594                 do {
5595                         rte_delay_ms(1);
5596                         txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
5597                 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
5598                 if (!poll_ms)
5599                         PMD_INIT_LOG(ERR, "Could not enable Tx Queue %d", i);
5600         }
5601         for (i = 0; i < dev->data->nb_rx_queues; i++) {
5602
5603                 rxq = dev->data->rx_queues[i];
5604
5605                 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
5606                 rxdctl |= IXGBE_RXDCTL_ENABLE;
5607                 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
5608
5609                 /* Wait until RX Enable ready */
5610                 poll_ms = 10;
5611                 do {
5612                         rte_delay_ms(1);
5613                         rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
5614                 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
5615                 if (!poll_ms)
5616                         PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d", i);
5617                 rte_wmb();
5618                 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);
5619
5620         }
5621 }
5622
5623 int
5624 ixgbe_rss_conf_init(struct ixgbe_rte_flow_rss_conf *out,
5625                     const struct rte_flow_action_rss *in)
5626 {
5627         if (in->key_len > RTE_DIM(out->key) ||
5628             in->queue_num > RTE_DIM(out->queue))
5629                 return -EINVAL;
5630         out->conf = (struct rte_flow_action_rss){
5631                 .func = in->func,
5632                 .level = in->level,
5633                 .types = in->types,
5634                 .key_len = in->key_len,
5635                 .queue_num = in->queue_num,
5636                 .key = memcpy(out->key, in->key, in->key_len),
5637                 .queue = memcpy(out->queue, in->queue,
5638                                 sizeof(*in->queue) * in->queue_num),
5639         };
5640         return 0;
5641 }
5642
5643 int
5644 ixgbe_action_rss_same(const struct rte_flow_action_rss *comp,
5645                       const struct rte_flow_action_rss *with)
5646 {
5647         return (comp->func == with->func &&
5648                 comp->level == with->level &&
5649                 comp->types == with->types &&
5650                 comp->key_len == with->key_len &&
5651                 comp->queue_num == with->queue_num &&
5652                 !memcmp(comp->key, with->key, with->key_len) &&
5653                 !memcmp(comp->queue, with->queue,
5654                         sizeof(*with->queue) * with->queue_num));
5655 }
5656
5657 int
5658 ixgbe_config_rss_filter(struct rte_eth_dev *dev,
5659                 struct ixgbe_rte_flow_rss_conf *conf, bool add)
5660 {
5661         struct ixgbe_hw *hw;
5662         uint32_t reta;
5663         uint16_t i;
5664         uint16_t j;
5665         uint16_t sp_reta_size;
5666         uint32_t reta_reg;
5667         struct rte_eth_rss_conf rss_conf = {
5668                 .rss_key = conf->conf.key_len ?
5669                         (void *)(uintptr_t)conf->conf.key : NULL,
5670                 .rss_key_len = conf->conf.key_len,
5671                 .rss_hf = conf->conf.types,
5672         };
5673         struct ixgbe_filter_info *filter_info =
5674                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5675
5676         PMD_INIT_FUNC_TRACE();
5677         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5678
5679         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5680
5681         if (!add) {
5682                 if (ixgbe_action_rss_same(&filter_info->rss_info.conf,
5683                                           &conf->conf)) {
5684                         ixgbe_rss_disable(dev);
5685                         memset(&filter_info->rss_info, 0,
5686                                 sizeof(struct ixgbe_rte_flow_rss_conf));
5687                         return 0;
5688                 }
5689                 return -EINVAL;
5690         }
5691
5692         if (filter_info->rss_info.conf.queue_num)
5693                 return -EINVAL;
5694         /* Fill in redirection table
5695          * The byte-swap is needed because NIC registers are in
5696          * little-endian order.
5697          */
5698         reta = 0;
5699         for (i = 0, j = 0; i < sp_reta_size; i++, j++) {
5700                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5701
5702                 if (j == conf->conf.queue_num)
5703                         j = 0;
5704                 reta = (reta << 8) | conf->conf.queue[j];
5705                 if ((i & 3) == 3)
5706                         IXGBE_WRITE_REG(hw, reta_reg,
5707                                         rte_bswap32(reta));
5708         }
5709
5710         /* Configure the RSS key and the RSS protocols used to compute
5711          * the RSS hash of input packets.
5712          */
5713         if ((rss_conf.rss_hf & IXGBE_RSS_OFFLOAD_ALL) == 0) {
5714                 ixgbe_rss_disable(dev);
5715                 return -EINVAL;
5716         }
5717         if (rss_conf.rss_key == NULL)
5718                 rss_conf.rss_key = rss_intel_key; /* Default hash key */
5719         ixgbe_hw_rss_hash_set(hw, &rss_conf);
5720
5721         if (ixgbe_rss_conf_init(&filter_info->rss_info, &conf->conf))
5722                 return -EINVAL;
5723
5724         return 0;
5725 }
5726
5727 /* Stubs needed for linkage when CONFIG_RTE_IXGBE_INC_VECTOR is set to 'n' */
5728 int __attribute__((weak))
5729 ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
5730 {
5731         return -1;
5732 }
5733
5734 uint16_t __attribute__((weak))
5735 ixgbe_recv_pkts_vec(
5736         void __rte_unused *rx_queue,
5737         struct rte_mbuf __rte_unused **rx_pkts,
5738         uint16_t __rte_unused nb_pkts)
5739 {
5740         return 0;
5741 }
5742
5743 uint16_t __attribute__((weak))
5744 ixgbe_recv_scattered_pkts_vec(
5745         void __rte_unused *rx_queue,
5746         struct rte_mbuf __rte_unused **rx_pkts,
5747         uint16_t __rte_unused nb_pkts)
5748 {
5749         return 0;
5750 }
5751
5752 int __attribute__((weak))
5753 ixgbe_rxq_vec_setup(struct ixgbe_rx_queue __rte_unused *rxq)
5754 {
5755         return -1;
5756 }