drivers/net/ixgbe/ixgbe_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation.
   3  * Copyright 2014 6WIND S.A.
   4  */
   5
   6 #include <sys/queue.h>
   7
   8 #include <stdio.h>
   9 #include <stdlib.h>
  10 #include <string.h>
  11 #include <errno.h>
  12 #include <stdint.h>
  13 #include <stdarg.h>
  14 #include <unistd.h>
  15 #include <inttypes.h>
  16
  17 #include <rte_byteorder.h>
  18 #include <rte_common.h>
  19 #include <rte_cycles.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_interrupts.h>
  23 #include <rte_pci.h>
  24 #include <rte_memory.h>
  25 #include <rte_memzone.h>
  26 #include <rte_launch.h>
  27 #include <rte_eal.h>
  28 #include <rte_per_lcore.h>
  29 #include <rte_lcore.h>
  30 #include <rte_atomic.h>
  31 #include <rte_branch_prediction.h>
  32 #include <rte_mempool.h>
  33 #include <rte_malloc.h>
  34 #include <rte_mbuf.h>
  35 #include <rte_ether.h>
  36 #include <rte_ethdev_driver.h>
  37 #include <rte_prefetch.h>
  38 #include <rte_udp.h>
  39 #include <rte_tcp.h>
  40 #include <rte_sctp.h>
  41 #include <rte_string_fns.h>
  42 #include <rte_errno.h>
  43 #include <rte_ip.h>
  44 #include <rte_net.h>
  45
  46 #include "ixgbe_logs.h"
  47 #include "base/ixgbe_api.h"
  48 #include "base/ixgbe_vf.h"
  49 #include "ixgbe_ethdev.h"
  50 #include "base/ixgbe_dcb.h"
  51 #include "base/ixgbe_common.h"
  52 #include "ixgbe_rxtx.h"
  53
  54 #ifdef RTE_LIBRTE_IEEE1588
  55 #define IXGBE_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST
  56 #else
  57 #define IXGBE_TX_IEEE1588_TMST 0
  58 #endif
  59 /* Bit Mask to indicate what bits required for building TX context */
  60 #define IXGBE_TX_OFFLOAD_MASK (                  \
  61                 PKT_TX_OUTER_IPV6 |              \
  62                 PKT_TX_OUTER_IPV4 |              \
  63                 PKT_TX_IPV6 |                    \
  64                 PKT_TX_IPV4 |                    \
  65                 PKT_TX_VLAN_PKT |                \
  66                 PKT_TX_IP_CKSUM |                \
  67                 PKT_TX_L4_MASK |                 \
  68                 PKT_TX_TCP_SEG |                 \
  69                 PKT_TX_MACSEC |                  \
  70                 PKT_TX_OUTER_IP_CKSUM |          \
  71                 PKT_TX_SEC_OFFLOAD |     \
  72                 IXGBE_TX_IEEE1588_TMST)
  73
  74 #define IXGBE_TX_OFFLOAD_NOTSUP_MASK \
  75                 (PKT_TX_OFFLOAD_MASK ^ IXGBE_TX_OFFLOAD_MASK)
  76
  77 #if 1
  78 #define RTE_PMD_USE_PREFETCH
  79 #endif
  80
  81 #ifdef RTE_PMD_USE_PREFETCH
  82 /*
  83  * Prefetch a cache line into all cache levels.
  84  */
  85 #define rte_ixgbe_prefetch(p)   rte_prefetch0(p)
  86 #else
  87 #define rte_ixgbe_prefetch(p)   do {} while (0)
  88 #endif
  89
  90 #ifdef RTE_IXGBE_INC_VECTOR
  91 uint16_t ixgbe_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
  92                                     uint16_t nb_pkts);
  93 #endif
  94
  95 /*********************************************************************
  96  *
  97  *  TX functions
  98  *
  99  **********************************************************************/
 100
 101 /*
 102  * Check for descriptors with their DD bit set and free mbufs.
 103  * Return the total number of buffers freed.
 104  */
 105 static __rte_always_inline int
 106 ixgbe_tx_free_bufs(struct ixgbe_tx_queue *txq)
 107 {
 108         struct ixgbe_tx_entry *txep;
 109         uint32_t status;
 110         int i, nb_free = 0;
 111         struct rte_mbuf *m, *free[RTE_IXGBE_TX_MAX_FREE_BUF_SZ];
 112
 113         /* check DD bit on threshold descriptor */
 114         status = txq->tx_ring[txq->tx_next_dd].wb.status;
 115         if (!(status & rte_cpu_to_le_32(IXGBE_ADVTXD_STAT_DD)))
 116                 return 0;
 117
 118         /*
 119          * first buffer to free from S/W ring is at index
 120          * tx_next_dd - (tx_rs_thresh-1)
 121          */
 122         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
 123
 124         for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
 125                 /* free buffers one at a time */
 126                 m = rte_pktmbuf_prefree_seg(txep->mbuf);
 127                 txep->mbuf = NULL;
 128
 129                 if (unlikely(m == NULL))
 130                         continue;
 131
 132                 if (nb_free >= RTE_IXGBE_TX_MAX_FREE_BUF_SZ ||
 133                     (nb_free > 0 && m->pool != free[0]->pool)) {
 134                         rte_mempool_put_bulk(free[0]->pool,
 135                                              (void **)free, nb_free);
 136                         nb_free = 0;
 137                 }
 138
 139                 free[nb_free++] = m;
 140         }
 141
 142         if (nb_free > 0)
 143                 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
 144
 145         /* buffers were freed, update counters */
 146         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
 147         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
 148         if (txq->tx_next_dd >= txq->nb_tx_desc)
 149                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
 150
 151         return txq->tx_rs_thresh;
 152 }
 153
 154 /* Populate 4 descriptors with data from 4 mbufs */
 155 static inline void
 156 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
 157 {
 158         uint64_t buf_dma_addr;
 159         uint32_t pkt_len;
 160         int i;
 161
 162         for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
 163                 buf_dma_addr = rte_mbuf_data_iova(*pkts);
 164                 pkt_len = (*pkts)->data_len;
 165
 166                 /* write data to descriptor */
 167                 txdp->read.buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
 168
 169                 txdp->read.cmd_type_len =
 170                         rte_cpu_to_le_32((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
 171
 172                 txdp->read.olinfo_status =
 173                         rte_cpu_to_le_32(pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
 174
 175                 rte_prefetch0(&(*pkts)->pool);
 176         }
 177 }
 178
 179 /* Populate 1 descriptor with data from 1 mbuf */
 180 static inline void
 181 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
 182 {
 183         uint64_t buf_dma_addr;
 184         uint32_t pkt_len;
 185
 186         buf_dma_addr = rte_mbuf_data_iova(*pkts);
 187         pkt_len = (*pkts)->data_len;
 188
 189         /* write data to descriptor */
 190         txdp->read.buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
 191         txdp->read.cmd_type_len =
 192                         rte_cpu_to_le_32((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
 193         txdp->read.olinfo_status =
 194                         rte_cpu_to_le_32(pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
 195         rte_prefetch0(&(*pkts)->pool);
 196 }
 197
 198 /*
 199  * Fill H/W descriptor ring with mbuf data.
 200  * Copy mbuf pointers to the S/W ring.
 201  */
 202 static inline void
 203 ixgbe_tx_fill_hw_ring(struct ixgbe_tx_queue *txq, struct rte_mbuf **pkts,
 204                       uint16_t nb_pkts)
 205 {
 206         volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
 207         struct ixgbe_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
 208         const int N_PER_LOOP = 4;
 209         const int N_PER_LOOP_MASK = N_PER_LOOP-1;
 210         int mainpart, leftover;
 211         int i, j;
 212
 213         /*
 214          * Process most of the packets in chunks of N pkts.  Any
 215          * leftover packets will get processed one at a time.
 216          */
 217         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
 218         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
 219         for (i = 0; i < mainpart; i += N_PER_LOOP) {
 220                 /* Copy N mbuf pointers to the S/W ring */
 221                 for (j = 0; j < N_PER_LOOP; ++j) {
 222                         (txep + i + j)->mbuf = *(pkts + i + j);
 223                 }
 224                 tx4(txdp + i, pkts + i);
 225         }
 226
 227         if (unlikely(leftover > 0)) {
 228                 for (i = 0; i < leftover; ++i) {
 229                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
 230                         tx1(txdp + mainpart + i, pkts + mainpart + i);
 231                 }
 232         }
 233 }
 234
 235 static inline uint16_t
 236 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 237              uint16_t nb_pkts)
 238 {
 239         struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
 240         volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
 241         uint16_t n = 0;
 242
 243         /*
 244          * Begin scanning the H/W ring for done descriptors when the
 245          * number of available descriptors drops below tx_free_thresh.  For
 246          * each done descriptor, free the associated buffer.
 247          */
 248         if (txq->nb_tx_free < txq->tx_free_thresh)
 249                 ixgbe_tx_free_bufs(txq);
 250
 251         /* Only use descriptors that are available */
 252         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
 253         if (unlikely(nb_pkts == 0))
 254                 return 0;
 255
 256         /* Use exactly nb_pkts descriptors */
 257         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
 258
 259         /*
 260          * At this point, we know there are enough descriptors in the
 261          * ring to transmit all the packets.  This assumes that each
 262          * mbuf contains a single segment, and that no new offloads
 263          * are expected, which would require a new context descriptor.
 264          */
 265
 266         /*
 267          * See if we're going to wrap-around. If so, handle the top
 268          * of the descriptor ring first, then do the bottom.  If not,
 269          * the processing looks just like the "bottom" part anyway...
 270          */
 271         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
 272                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
 273                 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
 274
 275                 /*
 276                  * We know that the last descriptor in the ring will need to
 277                  * have its RS bit set because tx_rs_thresh has to be
 278                  * a divisor of the ring size
 279                  */
 280                 tx_r[txq->tx_next_rs].read.cmd_type_len |=
 281                         rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
 282                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 283
 284                 txq->tx_tail = 0;
 285         }
 286
 287         /* Fill H/W descriptor ring with mbuf data */
 288         ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
 289         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
 290
 291         /*
 292          * Determine if RS bit should be set
 293          * This is what we actually want:
 294          *   if ((txq->tx_tail - 1) >= txq->tx_next_rs)
 295          * but instead of subtracting 1 and doing >=, we can just do
 296          * greater than without subtracting.
 297          */
 298         if (txq->tx_tail > txq->tx_next_rs) {
 299                 tx_r[txq->tx_next_rs].read.cmd_type_len |=
 300                         rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
 301                 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
 302                                                 txq->tx_rs_thresh);
 303                 if (txq->tx_next_rs >= txq->nb_tx_desc)
 304                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 305         }
 306
 307         /*
 308          * Check for wrap-around. This would only happen if we used
 309          * up to the last descriptor in the ring, no more, no less.
 310          */
 311         if (txq->tx_tail >= txq->nb_tx_desc)
 312                 txq->tx_tail = 0;
 313
 314         /* update tail pointer */
 315         rte_wmb();
 316         IXGBE_PCI_REG_WRITE_RELAXED(txq->tdt_reg_addr, txq->tx_tail);
 317
 318         return nb_pkts;
 319 }
 320
 321 uint16_t
 322 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
 323                        uint16_t nb_pkts)
 324 {
 325         uint16_t nb_tx;
 326
 327         /* Try to transmit at least chunks of TX_MAX_BURST pkts */
 328         if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
 329                 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
 330
 331         /* transmit more than the max burst, in chunks of TX_MAX_BURST */
 332         nb_tx = 0;
 333         while (nb_pkts) {
 334                 uint16_t ret, n;
 335
 336                 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
 337                 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
 338                 nb_tx = (uint16_t)(nb_tx + ret);
 339                 nb_pkts = (uint16_t)(nb_pkts - ret);
 340                 if (ret < n)
 341                         break;
 342         }
 343
 344         return nb_tx;
 345 }
 346
 347 #ifdef RTE_IXGBE_INC_VECTOR
 348 static uint16_t
 349 ixgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 350                     uint16_t nb_pkts)
 351 {
 352         uint16_t nb_tx = 0;
 353         struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
 354
 355         while (nb_pkts) {
 356                 uint16_t ret, num;
 357
 358                 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
 359                 ret = ixgbe_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
 360                                                  num);
 361                 nb_tx += ret;
 362                 nb_pkts -= ret;
 363                 if (ret < num)
 364                         break;
 365         }
 366
 367         return nb_tx;
 368 }
 369 #endif
 370
 371 static inline void
 372 ixgbe_set_xmit_ctx(struct ixgbe_tx_queue *txq,
 373                 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
 374                 uint64_t ol_flags, union ixgbe_tx_offload tx_offload,
 375                 __rte_unused uint64_t *mdata)
 376 {
 377         uint32_t type_tucmd_mlhl;
 378         uint32_t mss_l4len_idx = 0;
 379         uint32_t ctx_idx;
 380         uint32_t vlan_macip_lens;
 381         union ixgbe_tx_offload tx_offload_mask;
 382         uint32_t seqnum_seed = 0;
 383
 384         ctx_idx = txq->ctx_curr;
 385         tx_offload_mask.data[0] = 0;
 386         tx_offload_mask.data[1] = 0;
 387         type_tucmd_mlhl = 0;
 388
 389         /* Specify which HW CTX to upload. */
 390         mss_l4len_idx |= (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
 391
 392         if (ol_flags & PKT_TX_VLAN_PKT) {
 393                 tx_offload_mask.vlan_tci |= ~0;
 394         }
 395
 396         /* check if TCP segmentation required for this packet */
 397         if (ol_flags & PKT_TX_TCP_SEG) {
 398                 /* implies IP cksum in IPv4 */
 399                 if (ol_flags & PKT_TX_IP_CKSUM)
 400                         type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4 |
 401                                 IXGBE_ADVTXD_TUCMD_L4T_TCP |
 402                                 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
 403                 else
 404                         type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV6 |
 405                                 IXGBE_ADVTXD_TUCMD_L4T_TCP |
 406                                 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
 407
 408                 tx_offload_mask.l2_len |= ~0;
 409                 tx_offload_mask.l3_len |= ~0;
 410                 tx_offload_mask.l4_len |= ~0;
 411                 tx_offload_mask.tso_segsz |= ~0;
 412                 mss_l4len_idx |= tx_offload.tso_segsz << IXGBE_ADVTXD_MSS_SHIFT;
 413                 mss_l4len_idx |= tx_offload.l4_len << IXGBE_ADVTXD_L4LEN_SHIFT;
 414         } else { /* no TSO, check if hardware checksum is needed */
 415                 if (ol_flags & PKT_TX_IP_CKSUM) {
 416                         type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
 417                         tx_offload_mask.l2_len |= ~0;
 418                         tx_offload_mask.l3_len |= ~0;
 419                 }
 420
 421                 switch (ol_flags & PKT_TX_L4_MASK) {
 422                 case PKT_TX_UDP_CKSUM:
 423                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
 424                                 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
 425                         mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
 426                         tx_offload_mask.l2_len |= ~0;
 427                         tx_offload_mask.l3_len |= ~0;
 428                         break;
 429                 case PKT_TX_TCP_CKSUM:
 430                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
 431                                 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
 432                         mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
 433                         tx_offload_mask.l2_len |= ~0;
 434                         tx_offload_mask.l3_len |= ~0;
 435                         break;
 436                 case PKT_TX_SCTP_CKSUM:
 437                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
 438                                 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
 439                         mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
 440                         tx_offload_mask.l2_len |= ~0;
 441                         tx_offload_mask.l3_len |= ~0;
 442                         break;
 443                 default:
 444                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
 445                                 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
 446                         break;
 447                 }
 448         }
 449
 450         if (ol_flags & PKT_TX_OUTER_IP_CKSUM) {
 451                 tx_offload_mask.outer_l2_len |= ~0;
 452                 tx_offload_mask.outer_l3_len |= ~0;
 453                 tx_offload_mask.l2_len |= ~0;
 454                 seqnum_seed |= tx_offload.outer_l3_len
 455                                << IXGBE_ADVTXD_OUTER_IPLEN;
 456                 seqnum_seed |= tx_offload.l2_len
 457                                << IXGBE_ADVTXD_TUNNEL_LEN;
 458         }
 459 #ifdef RTE_LIBRTE_SECURITY
 460         if (ol_flags & PKT_TX_SEC_OFFLOAD) {
 461                 union ixgbe_crypto_tx_desc_md *md =
 462                                 (union ixgbe_crypto_tx_desc_md *)mdata;
 463                 seqnum_seed |=
 464                         (IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK & md->sa_idx);
 465                 type_tucmd_mlhl |= md->enc ?
 466                                 (IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP |
 467                                 IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN) : 0;
 468                 type_tucmd_mlhl |=
 469                         (md->pad_len & IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK);
 470                 tx_offload_mask.sa_idx |= ~0;
 471                 tx_offload_mask.sec_pad_len |= ~0;
 472         }
 473 #endif
 474
 475         txq->ctx_cache[ctx_idx].flags = ol_flags;
 476         txq->ctx_cache[ctx_idx].tx_offload.data[0]  =
 477                 tx_offload_mask.data[0] & tx_offload.data[0];
 478         txq->ctx_cache[ctx_idx].tx_offload.data[1]  =
 479                 tx_offload_mask.data[1] & tx_offload.data[1];
 480         txq->ctx_cache[ctx_idx].tx_offload_mask    = tx_offload_mask;
 481
 482         ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
 483         vlan_macip_lens = tx_offload.l3_len;
 484         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 485                 vlan_macip_lens |= (tx_offload.outer_l2_len <<
 486                                     IXGBE_ADVTXD_MACLEN_SHIFT);
 487         else
 488                 vlan_macip_lens |= (tx_offload.l2_len <<
 489                                     IXGBE_ADVTXD_MACLEN_SHIFT);
 490         vlan_macip_lens |= ((uint32_t)tx_offload.vlan_tci << IXGBE_ADVTXD_VLAN_SHIFT);
 491         ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
 492         ctx_txd->mss_l4len_idx   = rte_cpu_to_le_32(mss_l4len_idx);
 493         ctx_txd->seqnum_seed     = seqnum_seed;
 494 }
 495
 496 /*
 497  * Check which hardware context can be used. Use the existing match
 498  * or create a new context descriptor.
 499  */
 500 static inline uint32_t
 501 what_advctx_update(struct ixgbe_tx_queue *txq, uint64_t flags,
 502                    union ixgbe_tx_offload tx_offload)
 503 {
 504         /* If match with the current used context */
 505         if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
 506                    (txq->ctx_cache[txq->ctx_curr].tx_offload.data[0] ==
 507                     (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[0]
 508                      & tx_offload.data[0])) &&
 509                    (txq->ctx_cache[txq->ctx_curr].tx_offload.data[1] ==
 510                     (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[1]
 511                      & tx_offload.data[1]))))
 512                 return txq->ctx_curr;
 513
 514         /* What if match with the next context  */
 515         txq->ctx_curr ^= 1;
 516         if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
 517                    (txq->ctx_cache[txq->ctx_curr].tx_offload.data[0] ==
 518                     (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[0]
 519                      & tx_offload.data[0])) &&
 520                    (txq->ctx_cache[txq->ctx_curr].tx_offload.data[1] ==
 521                     (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[1]
 522                      & tx_offload.data[1]))))
 523                 return txq->ctx_curr;
 524
 525         /* Mismatch, use the previous context */
 526         return IXGBE_CTX_NUM;
 527 }
 528
 529 static inline uint32_t
 530 tx_desc_cksum_flags_to_olinfo(uint64_t ol_flags)
 531 {
 532         uint32_t tmp = 0;
 533
 534         if ((ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM)
 535                 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
 536         if (ol_flags & PKT_TX_IP_CKSUM)
 537                 tmp |= IXGBE_ADVTXD_POPTS_IXSM;
 538         if (ol_flags & PKT_TX_TCP_SEG)
 539                 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
 540         return tmp;
 541 }
 542
 543 static inline uint32_t
 544 tx_desc_ol_flags_to_cmdtype(uint64_t ol_flags)
 545 {
 546         uint32_t cmdtype = 0;
 547
 548         if (ol_flags & PKT_TX_VLAN_PKT)
 549                 cmdtype |= IXGBE_ADVTXD_DCMD_VLE;
 550         if (ol_flags & PKT_TX_TCP_SEG)
 551                 cmdtype |= IXGBE_ADVTXD_DCMD_TSE;
 552         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 553                 cmdtype |= (1 << IXGBE_ADVTXD_OUTERIPCS_SHIFT);
 554         if (ol_flags & PKT_TX_MACSEC)
 555                 cmdtype |= IXGBE_ADVTXD_MAC_LINKSEC;
 556         return cmdtype;
 557 }
 558
 559 /* Default RS bit threshold values */
 560 #ifndef DEFAULT_TX_RS_THRESH
 561 #define DEFAULT_TX_RS_THRESH   32
 562 #endif
 563 #ifndef DEFAULT_TX_FREE_THRESH
 564 #define DEFAULT_TX_FREE_THRESH 32
 565 #endif
 566
 567 /* Reset transmit descriptors after they have been used */
 568 static inline int
 569 ixgbe_xmit_cleanup(struct ixgbe_tx_queue *txq)
 570 {
 571         struct ixgbe_tx_entry *sw_ring = txq->sw_ring;
 572         volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
 573         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 574         uint16_t nb_tx_desc = txq->nb_tx_desc;
 575         uint16_t desc_to_clean_to;
 576         uint16_t nb_tx_to_clean;
 577         uint32_t status;
 578
 579         /* Determine the last descriptor needing to be cleaned */
 580         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 581         if (desc_to_clean_to >= nb_tx_desc)
 582                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 583
 584         /* Check to make sure the last descriptor to clean is done */
 585         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 586         status = txr[desc_to_clean_to].wb.status;
 587         if (!(status & rte_cpu_to_le_32(IXGBE_TXD_STAT_DD))) {
 588                 PMD_TX_FREE_LOG(DEBUG,
 589                                 "TX descriptor %4u is not done"
 590                                 "(port=%d queue=%d)",
 591                                 desc_to_clean_to,
 592                                 txq->port_id, txq->queue_id);
 593                 /* Failed to clean any descriptors, better luck next time */
 594                 return -(1);
 595         }
 596
 597         /* Figure out how many descriptors will be cleaned */
 598         if (last_desc_cleaned > desc_to_clean_to)
 599                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 600                                                         desc_to_clean_to);
 601         else
 602                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 603                                                 last_desc_cleaned);
 604
 605         PMD_TX_FREE_LOG(DEBUG,
 606                         "Cleaning %4u TX descriptors: %4u to %4u "
 607                         "(port=%d queue=%d)",
 608                         nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
 609                         txq->port_id, txq->queue_id);
 610
 611         /*
 612          * The last descriptor to clean is done, so that means all the
 613          * descriptors from the last descriptor that was cleaned
 614          * up to the last descriptor with the RS bit set
 615          * are done. Only reset the threshold descriptor.
 616          */
 617         txr[desc_to_clean_to].wb.status = 0;
 618
 619         /* Update the txq to reflect the last descriptor that was cleaned */
 620         txq->last_desc_cleaned = desc_to_clean_to;
 621         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 622
 623         /* No Error */
 624         return 0;
 625 }
 626
 627 uint16_t
 628 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 629                 uint16_t nb_pkts)
 630 {
 631         struct ixgbe_tx_queue *txq;
 632         struct ixgbe_tx_entry *sw_ring;
 633         struct ixgbe_tx_entry *txe, *txn;
 634         volatile union ixgbe_adv_tx_desc *txr;
 635         volatile union ixgbe_adv_tx_desc *txd, *txp;
 636         struct rte_mbuf     *tx_pkt;
 637         struct rte_mbuf     *m_seg;
 638         uint64_t buf_dma_addr;
 639         uint32_t olinfo_status;
 640         uint32_t cmd_type_len;
 641         uint32_t pkt_len;
 642         uint16_t slen;
 643         uint64_t ol_flags;
 644         uint16_t tx_id;
 645         uint16_t tx_last;
 646         uint16_t nb_tx;
 647         uint16_t nb_used;
 648         uint64_t tx_ol_req;
 649         uint32_t ctx = 0;
 650         uint32_t new_ctx;
 651         union ixgbe_tx_offload tx_offload;
 652 #ifdef RTE_LIBRTE_SECURITY
 653         uint8_t use_ipsec;
 654 #endif
 655
 656         tx_offload.data[0] = 0;
 657         tx_offload.data[1] = 0;
 658         txq = tx_queue;
 659         sw_ring = txq->sw_ring;
 660         txr     = txq->tx_ring;
 661         tx_id   = txq->tx_tail;
 662         txe = &sw_ring[tx_id];
 663         txp = NULL;
 664
 665         /* Determine if the descriptor ring needs to be cleaned. */
 666         if (txq->nb_tx_free < txq->tx_free_thresh)
 667                 ixgbe_xmit_cleanup(txq);
 668
 669         rte_prefetch0(&txe->mbuf->pool);
 670
 671         /* TX loop */
 672         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
 673                 new_ctx = 0;
 674                 tx_pkt = *tx_pkts++;
 675                 pkt_len = tx_pkt->pkt_len;
 676
 677                 /*
 678                  * Determine how many (if any) context descriptors
 679                  * are needed for offload functionality.
 680                  */
 681                 ol_flags = tx_pkt->ol_flags;
 682 #ifdef RTE_LIBRTE_SECURITY
 683                 use_ipsec = txq->using_ipsec && (ol_flags & PKT_TX_SEC_OFFLOAD);
 684 #endif
 685
 686                 /* If hardware offload required */
 687                 tx_ol_req = ol_flags & IXGBE_TX_OFFLOAD_MASK;
 688                 if (tx_ol_req) {
 689                         tx_offload.l2_len = tx_pkt->l2_len;
 690                         tx_offload.l3_len = tx_pkt->l3_len;
 691                         tx_offload.l4_len = tx_pkt->l4_len;
 692                         tx_offload.vlan_tci = tx_pkt->vlan_tci;
 693                         tx_offload.tso_segsz = tx_pkt->tso_segsz;
 694                         tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
 695                         tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
 696 #ifdef RTE_LIBRTE_SECURITY
 697                         if (use_ipsec) {
 698                                 union ixgbe_crypto_tx_desc_md *ipsec_mdata =
 699                                         (union ixgbe_crypto_tx_desc_md *)
 700                                                         &tx_pkt->udata64;
 701                                 tx_offload.sa_idx = ipsec_mdata->sa_idx;
 702                                 tx_offload.sec_pad_len = ipsec_mdata->pad_len;
 703                         }
 704 #endif
 705
 706                         /* If new context need be built or reuse the exist ctx. */
 707                         ctx = what_advctx_update(txq, tx_ol_req,
 708                                 tx_offload);
 709                         /* Only allocate context descriptor if required*/
 710                         new_ctx = (ctx == IXGBE_CTX_NUM);
 711                         ctx = txq->ctx_curr;
 712                 }
 713
 714                 /*
 715                  * Keep track of how many descriptors are used this loop
 716                  * This will always be the number of segments + the number of
 717                  * Context descriptors required to transmit the packet
 718                  */
 719                 nb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);
 720
 721                 if (txp != NULL &&
 722                                 nb_used + txq->nb_tx_used >= txq->tx_rs_thresh)
 723                         /* set RS on the previous packet in the burst */
 724                         txp->read.cmd_type_len |=
 725                                 rte_cpu_to_le_32(IXGBE_TXD_CMD_RS);
 726
 727                 /*
 728                  * The number of descriptors that must be allocated for a
 729                  * packet is the number of segments of that packet, plus 1
 730                  * Context Descriptor for the hardware offload, if any.
 731                  * Determine the last TX descriptor to allocate in the TX ring
 732                  * for the packet, starting from the current position (tx_id)
 733                  * in the ring.
 734                  */
 735                 tx_last = (uint16_t) (tx_id + nb_used - 1);
 736
 737                 /* Circular ring */
 738                 if (tx_last >= txq->nb_tx_desc)
 739                         tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
 740
 741                 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
 742                            " tx_first=%u tx_last=%u",
 743                            (unsigned) txq->port_id,
 744                            (unsigned) txq->queue_id,
 745                            (unsigned) pkt_len,
 746                            (unsigned) tx_id,
 747                            (unsigned) tx_last);
 748
 749                 /*
 750                  * Make sure there are enough TX descriptors available to
 751                  * transmit the entire packet.
 752                  * nb_used better be less than or equal to txq->tx_rs_thresh
 753                  */
 754                 if (nb_used > txq->nb_tx_free) {
 755                         PMD_TX_FREE_LOG(DEBUG,
 756                                         "Not enough free TX descriptors "
 757                                         "nb_used=%4u nb_free=%4u "
 758                                         "(port=%d queue=%d)",
 759                                         nb_used, txq->nb_tx_free,
 760                                         txq->port_id, txq->queue_id);
 761
 762                         if (ixgbe_xmit_cleanup(txq) != 0) {
 763                                 /* Could not clean any descriptors */
 764                                 if (nb_tx == 0)
 765                                         return 0;
 766                                 goto end_of_tx;
 767                         }
 768
 769                         /* nb_used better be <= txq->tx_rs_thresh */
 770                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
 771                                 PMD_TX_FREE_LOG(DEBUG,
 772                                         "The number of descriptors needed to "
 773                                         "transmit the packet exceeds the "
 774                                         "RS bit threshold. This will impact "
 775                                         "performance."
 776                                         "nb_used=%4u nb_free=%4u "
 777                                         "tx_rs_thresh=%4u. "
 778                                         "(port=%d queue=%d)",
 779                                         nb_used, txq->nb_tx_free,
 780                                         txq->tx_rs_thresh,
 781                                         txq->port_id, txq->queue_id);
 782                                 /*
 783                                  * Loop here until there are enough TX
 784                                  * descriptors or until the ring cannot be
 785                                  * cleaned.
 786                                  */
 787                                 while (nb_used > txq->nb_tx_free) {
 788                                         if (ixgbe_xmit_cleanup(txq) != 0) {
 789                                                 /*
 790                                                  * Could not clean any
 791                                                  * descriptors
 792                                                  */
 793                                                 if (nb_tx == 0)
 794                                                         return 0;
 795                                                 goto end_of_tx;
 796                                         }
 797                                 }
 798                         }
 799                 }
 800
 801                 /*
 802                  * By now there are enough free TX descriptors to transmit
 803                  * the packet.
 804                  */
 805
 806                 /*
 807                  * Set common flags of all TX Data Descriptors.
 808                  *
 809                  * The following bits must be set in all Data Descriptors:
 810                  *   - IXGBE_ADVTXD_DTYP_DATA
 811                  *   - IXGBE_ADVTXD_DCMD_DEXT
 812                  *
 813                  * The following bits must be set in the first Data Descriptor
 814                  * and are ignored in the other ones:
 815                  *   - IXGBE_ADVTXD_DCMD_IFCS
 816                  *   - IXGBE_ADVTXD_MAC_1588
 817                  *   - IXGBE_ADVTXD_DCMD_VLE
 818                  *
 819                  * The following bits must only be set in the last Data
 820                  * Descriptor:
 821                  *   - IXGBE_TXD_CMD_EOP
 822                  *
 823                  * The following bits can be set in any Data Descriptor, but
 824                  * are only set in the last Data Descriptor:
 825                  *   - IXGBE_TXD_CMD_RS
 826                  */
 827                 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
 828                         IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
 829
 830 #ifdef RTE_LIBRTE_IEEE1588
 831                 if (ol_flags & PKT_TX_IEEE1588_TMST)
 832                         cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
 833 #endif
 834
 835                 olinfo_status = 0;
 836                 if (tx_ol_req) {
 837
 838                         if (ol_flags & PKT_TX_TCP_SEG) {
 839                                 /* when TSO is on, paylen in descriptor is the
 840                                  * not the packet len but the tcp payload len */
 841                                 pkt_len -= (tx_offload.l2_len +
 842                                         tx_offload.l3_len + tx_offload.l4_len);
 843                         }
 844
 845                         /*
 846                          * Setup the TX Advanced Context Descriptor if required
 847                          */
 848                         if (new_ctx) {
 849                                 volatile struct ixgbe_adv_tx_context_desc *
 850                                     ctx_txd;
 851
 852                                 ctx_txd = (volatile struct
 853                                     ixgbe_adv_tx_context_desc *)
 854                                     &txr[tx_id];
 855
 856                                 txn = &sw_ring[txe->next_id];
 857                                 rte_prefetch0(&txn->mbuf->pool);
 858
 859                                 if (txe->mbuf != NULL) {
 860                                         rte_pktmbuf_free_seg(txe->mbuf);
 861                                         txe->mbuf = NULL;
 862                                 }
 863
 864                                 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
 865                                         tx_offload, &tx_pkt->udata64);
 866
 867                                 txe->last_id = tx_last;
 868                                 tx_id = txe->next_id;
 869                                 txe = txn;
 870                         }
 871
 872                         /*
 873                          * Setup the TX Advanced Data Descriptor,
 874                          * This path will go through
 875                          * whatever new/reuse the context descriptor
 876                          */
 877                         cmd_type_len  |= tx_desc_ol_flags_to_cmdtype(ol_flags);
 878                         olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
 879                         olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
 880                 }
 881
 882                 olinfo_status |= (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
 883 #ifdef RTE_LIBRTE_SECURITY
 884                 if (use_ipsec)
 885                         olinfo_status |= IXGBE_ADVTXD_POPTS_IPSEC;
 886 #endif
 887
 888                 m_seg = tx_pkt;
 889                 do {
 890                         txd = &txr[tx_id];
 891                         txn = &sw_ring[txe->next_id];
 892                         rte_prefetch0(&txn->mbuf->pool);
 893
 894                         if (txe->mbuf != NULL)
 895                                 rte_pktmbuf_free_seg(txe->mbuf);
 896                         txe->mbuf = m_seg;
 897
 898                         /*
 899                          * Set up Transmit Data Descriptor.
 900                          */
 901                         slen = m_seg->data_len;
 902                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
 903                         txd->read.buffer_addr =
 904                                 rte_cpu_to_le_64(buf_dma_addr);
 905                         txd->read.cmd_type_len =
 906                                 rte_cpu_to_le_32(cmd_type_len | slen);
 907                         txd->read.olinfo_status =
 908                                 rte_cpu_to_le_32(olinfo_status);
 909                         txe->last_id = tx_last;
 910                         tx_id = txe->next_id;
 911                         txe = txn;
 912                         m_seg = m_seg->next;
 913                 } while (m_seg != NULL);
 914
 915                 /*
 916                  * The last packet data descriptor needs End Of Packet (EOP)
 917                  */
 918                 cmd_type_len |= IXGBE_TXD_CMD_EOP;
 919                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
 920                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
 921
 922                 /* Set RS bit only on threshold packets' last descriptor */
 923                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
 924                         PMD_TX_FREE_LOG(DEBUG,
 925                                         "Setting RS bit on TXD id="
 926                                         "%4u (port=%d queue=%d)",
 927                                         tx_last, txq->port_id, txq->queue_id);
 928
 929                         cmd_type_len |= IXGBE_TXD_CMD_RS;
 930
 931                         /* Update txq RS bit counters */
 932                         txq->nb_tx_used = 0;
 933                         txp = NULL;
 934                 } else
 935                         txp = txd;
 936
 937                 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
 938         }
 939
 940 end_of_tx:
 941         /* set RS on last packet in the burst */
 942         if (txp != NULL)
 943                 txp->read.cmd_type_len |= rte_cpu_to_le_32(IXGBE_TXD_CMD_RS);
 944
 945         rte_wmb();
 946
 947         /*
 948          * Set the Transmit Descriptor Tail (TDT)
 949          */
 950         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
 951                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
 952                    (unsigned) tx_id, (unsigned) nb_tx);
 953         IXGBE_PCI_REG_WRITE_RELAXED(txq->tdt_reg_addr, tx_id);
 954         txq->tx_tail = tx_id;
 955
 956         return nb_tx;
 957 }
 958
 959 /*********************************************************************
 960  *
 961  *  TX prep functions
 962  *
 963  **********************************************************************/
 964 uint16_t
 965 ixgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
 966 {
 967         int i, ret;
 968         uint64_t ol_flags;
 969         struct rte_mbuf *m;
 970         struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
 971
 972         for (i = 0; i < nb_pkts; i++) {
 973                 m = tx_pkts[i];
 974                 ol_flags = m->ol_flags;
 975
 976                 /**
 977                  * Check if packet meets requirements for number of segments
 978                  *
 979                  * NOTE: for ixgbe it's always (40 - WTHRESH) for both TSO and
 980                  *       non-TSO
 981                  */
 982
 983                 if (m->nb_segs > IXGBE_TX_MAX_SEG - txq->wthresh) {
 984                         rte_errno = -EINVAL;
 985                         return i;
 986                 }
 987
 988                 if (ol_flags & IXGBE_TX_OFFLOAD_NOTSUP_MASK) {
 989                         rte_errno = -ENOTSUP;
 990                         return i;
 991                 }
 992
 993 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
 994                 ret = rte_validate_tx_offload(m);
 995                 if (ret != 0) {
 996                         rte_errno = ret;
 997                         return i;
 998                 }
 999 #endif
1000                 ret = rte_net_intel_cksum_prepare(m);
1001                 if (ret != 0) {
1002                         rte_errno = ret;
1003                         return i;
1004                 }
1005         }
1006
1007         return i;
1008 }
1009
1010 /*********************************************************************
1011  *
1012  *  RX functions
1013  *
1014  **********************************************************************/
1015
1016 #define IXGBE_PACKET_TYPE_ETHER                         0X00
1017 #define IXGBE_PACKET_TYPE_IPV4                          0X01
1018 #define IXGBE_PACKET_TYPE_IPV4_TCP                      0X11
1019 #define IXGBE_PACKET_TYPE_IPV4_UDP                      0X21
1020 #define IXGBE_PACKET_TYPE_IPV4_SCTP                     0X41
1021 #define IXGBE_PACKET_TYPE_IPV4_EXT                      0X03
1022 #define IXGBE_PACKET_TYPE_IPV4_EXT_TCP                  0X13
1023 #define IXGBE_PACKET_TYPE_IPV4_EXT_UDP                  0X23
1024 #define IXGBE_PACKET_TYPE_IPV4_EXT_SCTP                 0X43
1025 #define IXGBE_PACKET_TYPE_IPV6                          0X04
1026 #define IXGBE_PACKET_TYPE_IPV6_TCP                      0X14
1027 #define IXGBE_PACKET_TYPE_IPV6_UDP                      0X24
1028 #define IXGBE_PACKET_TYPE_IPV6_SCTP                     0X44
1029 #define IXGBE_PACKET_TYPE_IPV6_EXT                      0X0C
1030 #define IXGBE_PACKET_TYPE_IPV6_EXT_TCP                  0X1C
1031 #define IXGBE_PACKET_TYPE_IPV6_EXT_UDP                  0X2C
1032 #define IXGBE_PACKET_TYPE_IPV6_EXT_SCTP                 0X4C
1033 #define IXGBE_PACKET_TYPE_IPV4_IPV6                     0X05
1034 #define IXGBE_PACKET_TYPE_IPV4_IPV6_TCP                 0X15
1035 #define IXGBE_PACKET_TYPE_IPV4_IPV6_UDP                 0X25
1036 #define IXGBE_PACKET_TYPE_IPV4_IPV6_SCTP                0X45
1037 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6                 0X07
1038 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_TCP             0X17
1039 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_UDP             0X27
1040 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_SCTP            0X47
1041 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT                 0X0D
1042 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_TCP             0X1D
1043 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_UDP             0X2D
1044 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_SCTP            0X4D
1045 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT             0X0F
1046 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_TCP         0X1F
1047 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_UDP         0X2F
1048 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_SCTP        0X4F
1049
1050 #define IXGBE_PACKET_TYPE_NVGRE                   0X00
1051 #define IXGBE_PACKET_TYPE_NVGRE_IPV4              0X01
1052 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_TCP          0X11
1053 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_UDP          0X21
1054 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_SCTP         0X41
1055 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT          0X03
1056 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_TCP      0X13
1057 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_UDP      0X23
1058 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_SCTP     0X43
1059 #define IXGBE_PACKET_TYPE_NVGRE_IPV6              0X04
1060 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_TCP          0X14
1061 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_UDP          0X24
1062 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_SCTP         0X44
1063 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT          0X0C
1064 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_TCP      0X1C
1065 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_UDP      0X2C
1066 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_SCTP     0X4C
1067 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6         0X05
1068 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_TCP     0X15
1069 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_UDP     0X25
1070 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT     0X0D
1071 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_TCP 0X1D
1072 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_UDP 0X2D
1073
1074 #define IXGBE_PACKET_TYPE_VXLAN                   0X80
1075 #define IXGBE_PACKET_TYPE_VXLAN_IPV4              0X81
1076 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_TCP          0x91
1077 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_UDP          0xA1
1078 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_SCTP         0xC1
1079 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT          0x83
1080 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_TCP      0X93
1081 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_UDP      0XA3
1082 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_SCTP     0XC3
1083 #define IXGBE_PACKET_TYPE_VXLAN_IPV6              0X84
1084 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_TCP          0X94
1085 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_UDP          0XA4
1086 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_SCTP         0XC4
1087 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT          0X8C
1088 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_TCP      0X9C
1089 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_UDP      0XAC
1090 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_SCTP     0XCC
1091 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6         0X85
1092 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_TCP     0X95
1093 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_UDP     0XA5
1094 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT     0X8D
1095 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_TCP 0X9D
1096 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_UDP 0XAD
1097
1098 /**
1099  * Use 2 different table for normal packet and tunnel packet
1100  * to save the space.
1101  */
1102 const uint32_t
1103         ptype_table[IXGBE_PACKET_TYPE_MAX] __rte_cache_aligned = {
1104         [IXGBE_PACKET_TYPE_ETHER] = RTE_PTYPE_L2_ETHER,
1105         [IXGBE_PACKET_TYPE_IPV4] = RTE_PTYPE_L2_ETHER |
1106                 RTE_PTYPE_L3_IPV4,
1107         [IXGBE_PACKET_TYPE_IPV4_TCP] = RTE_PTYPE_L2_ETHER |
1108                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP,
1109         [IXGBE_PACKET_TYPE_IPV4_UDP] = RTE_PTYPE_L2_ETHER |
1110                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
1111         [IXGBE_PACKET_TYPE_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |
1112                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_SCTP,
1113         [IXGBE_PACKET_TYPE_IPV4_EXT] = RTE_PTYPE_L2_ETHER |
1114                 RTE_PTYPE_L3_IPV4_EXT,
1115         [IXGBE_PACKET_TYPE_IPV4_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1116                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_TCP,
1117         [IXGBE_PACKET_TYPE_IPV4_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1118                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_UDP,
1119         [IXGBE_PACKET_TYPE_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1120                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_SCTP,
1121         [IXGBE_PACKET_TYPE_IPV6] = RTE_PTYPE_L2_ETHER |
1122                 RTE_PTYPE_L3_IPV6,
1123         [IXGBE_PACKET_TYPE_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1124                 RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP,
1125         [IXGBE_PACKET_TYPE_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1126                 RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
1127         [IXGBE_PACKET_TYPE_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
1128                 RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_SCTP,
1129         [IXGBE_PACKET_TYPE_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1130                 RTE_PTYPE_L3_IPV6_EXT,
1131         [IXGBE_PACKET_TYPE_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1132                 RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_TCP,
1133         [IXGBE_PACKET_TYPE_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1134                 RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_UDP,
1135         [IXGBE_PACKET_TYPE_IPV6_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1136                 RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_SCTP,
1137         [IXGBE_PACKET_TYPE_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |
1138                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1139                 RTE_PTYPE_INNER_L3_IPV6,
1140         [IXGBE_PACKET_TYPE_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1141                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1142                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_TCP,
1143         [IXGBE_PACKET_TYPE_IPV4_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1144                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1145         RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_UDP,
1146         [IXGBE_PACKET_TYPE_IPV4_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
1147                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1148                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_SCTP,
1149         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6] = RTE_PTYPE_L2_ETHER |
1150                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1151                 RTE_PTYPE_INNER_L3_IPV6,
1152         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1153                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1154                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_TCP,
1155         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1156                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1157                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_UDP,
1158         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
1159                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1160                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_SCTP,
1161         [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1162                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1163                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1164         [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1165                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1166                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_TCP,
1167         [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1168                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1169                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_UDP,
1170         [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1171                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1172                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_SCTP,
1173         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1174                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1175                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1176         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1177                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1178                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_TCP,
1179         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1180                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1181                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_UDP,
1182         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_SCTP] =
1183                 RTE_PTYPE_L2_ETHER |
1184                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1185                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_SCTP,
1186 };
1187
1188 const uint32_t
1189         ptype_table_tn[IXGBE_PACKET_TYPE_TN_MAX] __rte_cache_aligned = {
1190         [IXGBE_PACKET_TYPE_NVGRE] = RTE_PTYPE_L2_ETHER |
1191                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1192                 RTE_PTYPE_INNER_L2_ETHER,
1193         [IXGBE_PACKET_TYPE_NVGRE_IPV4] = RTE_PTYPE_L2_ETHER |
1194                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1195                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1196         [IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT] = RTE_PTYPE_L2_ETHER |
1197                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1198                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4_EXT,
1199         [IXGBE_PACKET_TYPE_NVGRE_IPV6] = RTE_PTYPE_L2_ETHER |
1200                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1201                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6,
1202         [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |
1203                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1204                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1205         [IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1206                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1207                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6_EXT,
1208         [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1209                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1210                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1211         [IXGBE_PACKET_TYPE_NVGRE_IPV4_TCP] = RTE_PTYPE_L2_ETHER |
1212                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1213                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4 |
1214                 RTE_PTYPE_INNER_L4_TCP,
1215         [IXGBE_PACKET_TYPE_NVGRE_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1216                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1217                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6 |
1218                 RTE_PTYPE_INNER_L4_TCP,
1219         [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1220                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1221                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1222         [IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1223                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1224                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6_EXT |
1225                 RTE_PTYPE_INNER_L4_TCP,
1226         [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_TCP] =
1227                 RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1228                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_INNER_L2_ETHER |
1229                 RTE_PTYPE_INNER_L3_IPV4,
1230         [IXGBE_PACKET_TYPE_NVGRE_IPV4_UDP] = RTE_PTYPE_L2_ETHER |
1231                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1232                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4 |
1233                 RTE_PTYPE_INNER_L4_UDP,
1234         [IXGBE_PACKET_TYPE_NVGRE_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1235                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1236                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6 |
1237                 RTE_PTYPE_INNER_L4_UDP,
1238         [IXGBE_PACKET_TYPE_NVGRE_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
1239                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1240                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6 |
1241                 RTE_PTYPE_INNER_L4_SCTP,
1242         [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1243                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1244                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1245         [IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1246                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1247                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6_EXT |
1248                 RTE_PTYPE_INNER_L4_UDP,
1249         [IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1250                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1251                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6_EXT |
1252                 RTE_PTYPE_INNER_L4_SCTP,
1253         [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_UDP] =
1254                 RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1255                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_INNER_L2_ETHER |
1256                 RTE_PTYPE_INNER_L3_IPV4,
1257         [IXGBE_PACKET_TYPE_NVGRE_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |
1258                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1259                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4 |
1260                 RTE_PTYPE_INNER_L4_SCTP,
1261         [IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1262                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1263                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4_EXT |
1264                 RTE_PTYPE_INNER_L4_SCTP,
1265         [IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1266                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1267                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4_EXT |
1268                 RTE_PTYPE_INNER_L4_TCP,
1269         [IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1270                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1271                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4_EXT |
1272                 RTE_PTYPE_INNER_L4_UDP,
1273
1274         [IXGBE_PACKET_TYPE_VXLAN] = RTE_PTYPE_L2_ETHER |
1275                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1276                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER,
1277         [IXGBE_PACKET_TYPE_VXLAN_IPV4] = RTE_PTYPE_L2_ETHER |
1278                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1279                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1280                 RTE_PTYPE_INNER_L3_IPV4,
1281         [IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT] = RTE_PTYPE_L2_ETHER |
1282                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1283                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1284                 RTE_PTYPE_INNER_L3_IPV4_EXT,
1285         [IXGBE_PACKET_TYPE_VXLAN_IPV6] = RTE_PTYPE_L2_ETHER |
1286                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1287                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1288                 RTE_PTYPE_INNER_L3_IPV6,
1289         [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |
1290                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1291                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1292                 RTE_PTYPE_INNER_L3_IPV4,
1293         [IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1294                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1295                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1296                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1297         [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1298                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1299                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1300                 RTE_PTYPE_INNER_L3_IPV4,
1301         [IXGBE_PACKET_TYPE_VXLAN_IPV4_TCP] = RTE_PTYPE_L2_ETHER |
1302                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1303                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1304                 RTE_PTYPE_INNER_L3_IPV4 | RTE_PTYPE_INNER_L4_TCP,
1305         [IXGBE_PACKET_TYPE_VXLAN_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1306                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1307                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1308                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_TCP,
1309         [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1310                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1311                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1312                 RTE_PTYPE_INNER_L3_IPV4,
1313         [IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1314                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1315                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1316                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_TCP,
1317         [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_TCP] =
1318                 RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1319                 RTE_PTYPE_L4_UDP | RTE_PTYPE_TUNNEL_VXLAN |
1320                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1321         [IXGBE_PACKET_TYPE_VXLAN_IPV4_UDP] = RTE_PTYPE_L2_ETHER |
1322                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1323                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1324                 RTE_PTYPE_INNER_L3_IPV4 | RTE_PTYPE_INNER_L4_UDP,
1325         [IXGBE_PACKET_TYPE_VXLAN_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1326                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1327                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1328                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_UDP,
1329         [IXGBE_PACKET_TYPE_VXLAN_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
1330                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1331                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1332                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_SCTP,
1333         [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1334                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1335                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1336                 RTE_PTYPE_INNER_L3_IPV4,
1337         [IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1338                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1339                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1340                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_UDP,
1341         [IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1342                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1343                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1344                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_SCTP,
1345         [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_UDP] =
1346                 RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1347                 RTE_PTYPE_L4_UDP | RTE_PTYPE_TUNNEL_VXLAN |
1348                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1349         [IXGBE_PACKET_TYPE_VXLAN_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |
1350                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1351                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1352                 RTE_PTYPE_INNER_L3_IPV4 | RTE_PTYPE_INNER_L4_SCTP,
1353         [IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1354                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1355                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1356                 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_SCTP,
1357         [IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1358                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1359                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1360                 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_TCP,
1361         [IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1362                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1363                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1364                 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_UDP,
1365 };
1366
1367 /* @note: fix ixgbe_dev_supported_ptypes_get() if any change here. */
1368 static inline uint32_t
1369 ixgbe_rxd_pkt_info_to_pkt_type(uint32_t pkt_info, uint16_t ptype_mask)
1370 {
1371
1372         if (unlikely(pkt_info & IXGBE_RXDADV_PKTTYPE_ETQF))
1373                 return RTE_PTYPE_UNKNOWN;
1374
1375         pkt_info = (pkt_info >> IXGBE_PACKET_TYPE_SHIFT) & ptype_mask;
1376
1377         /* For tunnel packet */
1378         if (pkt_info & IXGBE_PACKET_TYPE_TUNNEL_BIT) {
1379                 /* Remove the tunnel bit to save the space. */
1380                 pkt_info &= IXGBE_PACKET_TYPE_MASK_TUNNEL;
1381                 return ptype_table_tn[pkt_info];
1382         }
1383
1384         /**
1385          * For x550, if it's not tunnel,
1386          * tunnel type bit should be set to 0.
1387          * Reuse 82599's mask.
1388          */
1389         pkt_info &= IXGBE_PACKET_TYPE_MASK_82599;
1390
1391         return ptype_table[pkt_info];
1392 }
1393
1394 static inline uint64_t
1395 ixgbe_rxd_pkt_info_to_pkt_flags(uint16_t pkt_info)
1396 {
1397         static uint64_t ip_rss_types_map[16] __rte_cache_aligned = {
1398                 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
1399                 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
1400                 PKT_RX_RSS_HASH, 0, 0, 0,
1401                 0, 0, 0,  PKT_RX_FDIR,
1402         };
1403 #ifdef RTE_LIBRTE_IEEE1588
1404         static uint64_t ip_pkt_etqf_map[8] = {
1405                 0, 0, 0, PKT_RX_IEEE1588_PTP,
1406                 0, 0, 0, 0,
1407         };
1408
1409         if (likely(pkt_info & IXGBE_RXDADV_PKTTYPE_ETQF))
1410                 return ip_pkt_etqf_map[(pkt_info >> 4) & 0X07] |
1411                                 ip_rss_types_map[pkt_info & 0XF];
1412         else
1413                 return ip_rss_types_map[pkt_info & 0XF];
1414 #else
1415         return ip_rss_types_map[pkt_info & 0XF];
1416 #endif
1417 }
1418
1419 static inline uint64_t
1420 rx_desc_status_to_pkt_flags(uint32_t rx_status, uint64_t vlan_flags)
1421 {
1422         uint64_t pkt_flags;
1423
1424         /*
1425          * Check if VLAN present only.
1426          * Do not check whether L3/L4 rx checksum done by NIC or not,
1427          * That can be found from rte_eth_rxmode.offloads flag
1428          */
1429         pkt_flags = (rx_status & IXGBE_RXD_STAT_VP) ?  vlan_flags : 0;
1430
1431 #ifdef RTE_LIBRTE_IEEE1588
1432         if (rx_status & IXGBE_RXD_STAT_TMST)
1433                 pkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;
1434 #endif
1435         return pkt_flags;
1436 }
1437
1438 static inline uint64_t
1439 rx_desc_error_to_pkt_flags(uint32_t rx_status)
1440 {
1441         uint64_t pkt_flags;
1442
1443         /*
1444          * Bit 31: IPE, IPv4 checksum error
1445          * Bit 30: L4I, L4I integrity error
1446          */
1447         static uint64_t error_to_pkt_flags_map[4] = {
1448                 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD,
1449                 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD,
1450                 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD,
1451                 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
1452         };
1453         pkt_flags = error_to_pkt_flags_map[(rx_status >>
1454                 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
1455
1456         if ((rx_status & IXGBE_RXD_STAT_OUTERIPCS) &&
1457             (rx_status & IXGBE_RXDADV_ERR_OUTERIPER)) {
1458                 pkt_flags |= PKT_RX_EIP_CKSUM_BAD;
1459         }
1460
1461 #ifdef RTE_LIBRTE_SECURITY
1462         if (rx_status & IXGBE_RXD_STAT_SECP) {
1463                 pkt_flags |= PKT_RX_SEC_OFFLOAD;
1464                 if (rx_status & IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG)
1465                         pkt_flags |= PKT_RX_SEC_OFFLOAD_FAILED;
1466         }
1467 #endif
1468
1469         return pkt_flags;
1470 }
1471
1472 /*
1473  * LOOK_AHEAD defines how many desc statuses to check beyond the
1474  * current descriptor.
1475  * It must be a pound define for optimal performance.
1476  * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
1477  * function only works with LOOK_AHEAD=8.
1478  */
1479 #define LOOK_AHEAD 8
1480 #if (LOOK_AHEAD != 8)
1481 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
1482 #endif
1483 static inline int
1484 ixgbe_rx_scan_hw_ring(struct ixgbe_rx_queue *rxq)
1485 {
1486         volatile union ixgbe_adv_rx_desc *rxdp;
1487         struct ixgbe_rx_entry *rxep;
1488         struct rte_mbuf *mb;
1489         uint16_t pkt_len;
1490         uint64_t pkt_flags;
1491         int nb_dd;
1492         uint32_t s[LOOK_AHEAD];
1493         uint32_t pkt_info[LOOK_AHEAD];
1494         int i, j, nb_rx = 0;
1495         uint32_t status;
1496         uint64_t vlan_flags = rxq->vlan_flags;
1497
1498         /* get references to current descriptor and S/W ring entry */
1499         rxdp = &rxq->rx_ring[rxq->rx_tail];
1500         rxep = &rxq->sw_ring[rxq->rx_tail];
1501
1502         status = rxdp->wb.upper.status_error;
1503         /* check to make sure there is at least 1 packet to receive */
1504         if (!(status & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1505                 return 0;
1506
1507         /*
1508          * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
1509          * reference packets that are ready to be received.
1510          */
1511         for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
1512              i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD) {
1513                 /* Read desc statuses backwards to avoid race condition */
1514                 for (j = 0; j < LOOK_AHEAD; j++)
1515                         s[j] = rte_le_to_cpu_32(rxdp[j].wb.upper.status_error);
1516
1517                 rte_smp_rmb();
1518
1519                 /* Compute how many status bits were set */
1520                 for (nb_dd = 0; nb_dd < LOOK_AHEAD &&
1521                                 (s[nb_dd] & IXGBE_RXDADV_STAT_DD); nb_dd++)
1522                         ;
1523
1524                 for (j = 0; j < nb_dd; j++)
1525                         pkt_info[j] = rte_le_to_cpu_32(rxdp[j].wb.lower.
1526                                                        lo_dword.data);
1527
1528                 nb_rx += nb_dd;
1529
1530                 /* Translate descriptor info to mbuf format */
1531                 for (j = 0; j < nb_dd; ++j) {
1532                         mb = rxep[j].mbuf;
1533                         pkt_len = rte_le_to_cpu_16(rxdp[j].wb.upper.length) -
1534                                   rxq->crc_len;
1535                         mb->data_len = pkt_len;
1536                         mb->pkt_len = pkt_len;
1537                         mb->vlan_tci = rte_le_to_cpu_16(rxdp[j].wb.upper.vlan);
1538
1539                         /* convert descriptor fields to rte mbuf flags */
1540                         pkt_flags = rx_desc_status_to_pkt_flags(s[j],
1541                                 vlan_flags);
1542                         pkt_flags |= rx_desc_error_to_pkt_flags(s[j]);
1543                         pkt_flags |= ixgbe_rxd_pkt_info_to_pkt_flags
1544                                         ((uint16_t)pkt_info[j]);
1545                         mb->ol_flags = pkt_flags;
1546                         mb->packet_type =
1547                                 ixgbe_rxd_pkt_info_to_pkt_type
1548                                         (pkt_info[j], rxq->pkt_type_mask);
1549
1550                         if (likely(pkt_flags & PKT_RX_RSS_HASH))
1551                                 mb->hash.rss = rte_le_to_cpu_32(
1552                                     rxdp[j].wb.lower.hi_dword.rss);
1553                         else if (pkt_flags & PKT_RX_FDIR) {
1554                                 mb->hash.fdir.hash = rte_le_to_cpu_16(
1555                                     rxdp[j].wb.lower.hi_dword.csum_ip.csum) &
1556                                     IXGBE_ATR_HASH_MASK;
1557                                 mb->hash.fdir.id = rte_le_to_cpu_16(
1558                                     rxdp[j].wb.lower.hi_dword.csum_ip.ip_id);
1559                         }
1560                 }
1561
1562                 /* Move mbuf pointers from the S/W ring to the stage */
1563                 for (j = 0; j < LOOK_AHEAD; ++j) {
1564                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1565                 }
1566
1567                 /* stop if all requested packets could not be received */
1568                 if (nb_dd != LOOK_AHEAD)
1569                         break;
1570         }
1571
1572         /* clear software ring entries so we can cleanup correctly */
1573         for (i = 0; i < nb_rx; ++i) {
1574                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1575         }
1576
1577
1578         return nb_rx;
1579 }
1580
1581 static inline int
1582 ixgbe_rx_alloc_bufs(struct ixgbe_rx_queue *rxq, bool reset_mbuf)
1583 {
1584         volatile union ixgbe_adv_rx_desc *rxdp;
1585         struct ixgbe_rx_entry *rxep;
1586         struct rte_mbuf *mb;
1587         uint16_t alloc_idx;
1588         __le64 dma_addr;
1589         int diag, i;
1590
1591         /* allocate buffers in bulk directly into the S/W ring */
1592         alloc_idx = rxq->rx_free_trigger - (rxq->rx_free_thresh - 1);
1593         rxep = &rxq->sw_ring[alloc_idx];
1594         diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
1595                                     rxq->rx_free_thresh);
1596         if (unlikely(diag != 0))
1597                 return -ENOMEM;
1598
1599         rxdp = &rxq->rx_ring[alloc_idx];
1600         for (i = 0; i < rxq->rx_free_thresh; ++i) {
1601                 /* populate the static rte mbuf fields */
1602                 mb = rxep[i].mbuf;
1603                 if (reset_mbuf) {
1604                         mb->port = rxq->port_id;
1605                 }
1606
1607                 rte_mbuf_refcnt_set(mb, 1);
1608                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1609
1610                 /* populate the descriptors */
1611                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1612                 rxdp[i].read.hdr_addr = 0;
1613                 rxdp[i].read.pkt_addr = dma_addr;
1614         }
1615
1616         /* update state of internal queue structure */
1617         rxq->rx_free_trigger = rxq->rx_free_trigger + rxq->rx_free_thresh;
1618         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1619                 rxq->rx_free_trigger = rxq->rx_free_thresh - 1;
1620
1621         /* no errors */
1622         return 0;
1623 }
1624
1625 static inline uint16_t
1626 ixgbe_rx_fill_from_stage(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1627                          uint16_t nb_pkts)
1628 {
1629         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1630         int i;
1631
1632         /* how many packets are ready to return? */
1633         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1634
1635         /* copy mbuf pointers to the application's packet list */
1636         for (i = 0; i < nb_pkts; ++i)
1637                 rx_pkts[i] = stage[i];
1638
1639         /* update internal queue state */
1640         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1641         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1642
1643         return nb_pkts;
1644 }
1645
1646 static inline uint16_t
1647 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1648              uint16_t nb_pkts)
1649 {
1650         struct ixgbe_rx_queue *rxq = (struct ixgbe_rx_queue *)rx_queue;
1651         uint16_t nb_rx = 0;
1652
1653         /* Any previously recv'd pkts will be returned from the Rx stage */
1654         if (rxq->rx_nb_avail)
1655                 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1656
1657         /* Scan the H/W ring for packets to receive */
1658         nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);
1659
1660         /* update internal queue state */
1661         rxq->rx_next_avail = 0;
1662         rxq->rx_nb_avail = nb_rx;
1663         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1664
1665         /* if required, allocate new buffers to replenish descriptors */
1666         if (rxq->rx_tail > rxq->rx_free_trigger) {
1667                 uint16_t cur_free_trigger = rxq->rx_free_trigger;
1668
1669                 if (ixgbe_rx_alloc_bufs(rxq, true) != 0) {
1670                         int i, j;
1671
1672                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1673                                    "queue_id=%u", (unsigned) rxq->port_id,
1674                                    (unsigned) rxq->queue_id);
1675
1676                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1677                                 rxq->rx_free_thresh;
1678
1679                         /*
1680                          * Need to rewind any previous receives if we cannot
1681                          * allocate new buffers to replenish the old ones.
1682                          */
1683                         rxq->rx_nb_avail = 0;
1684                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1685                         for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1686                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1687
1688                         return 0;
1689                 }
1690
1691                 /* update tail pointer */
1692                 rte_wmb();
1693                 IXGBE_PCI_REG_WRITE_RELAXED(rxq->rdt_reg_addr,
1694                                             cur_free_trigger);
1695         }
1696
1697         if (rxq->rx_tail >= rxq->nb_rx_desc)
1698                 rxq->rx_tail = 0;
1699
1700         /* received any packets this loop? */
1701         if (rxq->rx_nb_avail)
1702                 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1703
1704         return 0;
1705 }
1706
1707 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1708 uint16_t
1709 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1710                            uint16_t nb_pkts)
1711 {
1712         uint16_t nb_rx;
1713
1714         if (unlikely(nb_pkts == 0))
1715                 return 0;
1716
1717         if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1718                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1719
1720         /* request is relatively large, chunk it up */
1721         nb_rx = 0;
1722         while (nb_pkts) {
1723                 uint16_t ret, n;
1724
1725                 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1726                 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1727                 nb_rx = (uint16_t)(nb_rx + ret);
1728                 nb_pkts = (uint16_t)(nb_pkts - ret);
1729                 if (ret < n)
1730                         break;
1731         }
1732
1733         return nb_rx;
1734 }
1735
1736 uint16_t
1737 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1738                 uint16_t nb_pkts)
1739 {
1740         struct ixgbe_rx_queue *rxq;
1741         volatile union ixgbe_adv_rx_desc *rx_ring;
1742         volatile union ixgbe_adv_rx_desc *rxdp;
1743         struct ixgbe_rx_entry *sw_ring;
1744         struct ixgbe_rx_entry *rxe;
1745         struct rte_mbuf *rxm;
1746         struct rte_mbuf *nmb;
1747         union ixgbe_adv_rx_desc rxd;
1748         uint64_t dma_addr;
1749         uint32_t staterr;
1750         uint32_t pkt_info;
1751         uint16_t pkt_len;
1752         uint16_t rx_id;
1753         uint16_t nb_rx;
1754         uint16_t nb_hold;
1755         uint64_t pkt_flags;
1756         uint64_t vlan_flags;
1757
1758         nb_rx = 0;
1759         nb_hold = 0;
1760         rxq = rx_queue;
1761         rx_id = rxq->rx_tail;
1762         rx_ring = rxq->rx_ring;
1763         sw_ring = rxq->sw_ring;
1764         vlan_flags = rxq->vlan_flags;
1765         while (nb_rx < nb_pkts) {
1766                 /*
1767                  * The order of operations here is important as the DD status
1768                  * bit must not be read after any other descriptor fields.
1769                  * rx_ring and rxdp are pointing to volatile data so the order
1770                  * of accesses cannot be reordered by the compiler. If they were
1771                  * not volatile, they could be reordered which could lead to
1772                  * using invalid descriptor fields when read from rxd.
1773                  */
1774                 rxdp = &rx_ring[rx_id];
1775                 staterr = rxdp->wb.upper.status_error;
1776                 if (!(staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1777                         break;
1778                 rxd = *rxdp;
1779
1780                 /*
1781                  * End of packet.
1782                  *
1783                  * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1784                  * is likely to be invalid and to be dropped by the various
1785                  * validation checks performed by the network stack.
1786                  *
1787                  * Allocate a new mbuf to replenish the RX ring descriptor.
1788                  * If the allocation fails:
1789                  *    - arrange for that RX descriptor to be the first one
1790                  *      being parsed the next time the receive function is
1791                  *      invoked [on the same queue].
1792                  *
1793                  *    - Stop parsing the RX ring and return immediately.
1794                  *
1795                  * This policy do not drop the packet received in the RX
1796                  * descriptor for which the allocation of a new mbuf failed.
1797                  * Thus, it allows that packet to be later retrieved if
1798                  * mbuf have been freed in the mean time.
1799                  * As a side effect, holding RX descriptors instead of
1800                  * systematically giving them back to the NIC may lead to
1801                  * RX ring exhaustion situations.
1802                  * However, the NIC can gracefully prevent such situations
1803                  * to happen by sending specific "back-pressure" flow control
1804                  * frames to its peer(s).
1805                  */
1806                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1807                            "ext_err_stat=0x%08x pkt_len=%u",
1808                            (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1809                            (unsigned) rx_id, (unsigned) staterr,
1810                            (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1811
1812                 nmb = rte_mbuf_raw_alloc(rxq->mb_pool);
1813                 if (nmb == NULL) {
1814                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1815                                    "queue_id=%u", (unsigned) rxq->port_id,
1816                                    (unsigned) rxq->queue_id);
1817                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1818                         break;
1819                 }
1820
1821                 nb_hold++;
1822                 rxe = &sw_ring[rx_id];
1823                 rx_id++;
1824                 if (rx_id == rxq->nb_rx_desc)
1825                         rx_id = 0;
1826
1827                 /* Prefetch next mbuf while processing current one. */
1828                 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1829
1830                 /*
1831                  * When next RX descriptor is on a cache-line boundary,
1832                  * prefetch the next 4 RX descriptors and the next 8 pointers
1833                  * to mbufs.
1834                  */
1835                 if ((rx_id & 0x3) == 0) {
1836                         rte_ixgbe_prefetch(&rx_ring[rx_id]);
1837                         rte_ixgbe_prefetch(&sw_ring[rx_id]);
1838                 }
1839
1840                 rxm = rxe->mbuf;
1841                 rxe->mbuf = nmb;
1842                 dma_addr =
1843                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1844                 rxdp->read.hdr_addr = 0;
1845                 rxdp->read.pkt_addr = dma_addr;
1846
1847                 /*
1848                  * Initialize the returned mbuf.
1849                  * 1) setup generic mbuf fields:
1850                  *    - number of segments,
1851                  *    - next segment,
1852                  *    - packet length,
1853                  *    - RX port identifier.
1854                  * 2) integrate hardware offload data, if any:
1855                  *    - RSS flag & hash,
1856                  *    - IP checksum flag,
1857                  *    - VLAN TCI, if any,
1858                  *    - error flags.
1859                  */
1860                 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1861                                       rxq->crc_len);
1862                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1863                 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
1864                 rxm->nb_segs = 1;
1865                 rxm->next = NULL;
1866                 rxm->pkt_len = pkt_len;
1867                 rxm->data_len = pkt_len;
1868                 rxm->port = rxq->port_id;
1869
1870                 pkt_info = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1871                 /* Only valid if PKT_RX_VLAN set in pkt_flags */
1872                 rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1873
1874                 pkt_flags = rx_desc_status_to_pkt_flags(staterr, vlan_flags);
1875                 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
1876                 pkt_flags = pkt_flags |
1877                         ixgbe_rxd_pkt_info_to_pkt_flags((uint16_t)pkt_info);
1878                 rxm->ol_flags = pkt_flags;
1879                 rxm->packet_type =
1880                         ixgbe_rxd_pkt_info_to_pkt_type(pkt_info,
1881                                                        rxq->pkt_type_mask);
1882
1883                 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1884                         rxm->hash.rss = rte_le_to_cpu_32(
1885                                                 rxd.wb.lower.hi_dword.rss);
1886                 else if (pkt_flags & PKT_RX_FDIR) {
1887                         rxm->hash.fdir.hash = rte_le_to_cpu_16(
1888                                         rxd.wb.lower.hi_dword.csum_ip.csum) &
1889                                         IXGBE_ATR_HASH_MASK;
1890                         rxm->hash.fdir.id = rte_le_to_cpu_16(
1891                                         rxd.wb.lower.hi_dword.csum_ip.ip_id);
1892                 }
1893                 /*
1894                  * Store the mbuf address into the next entry of the array
1895                  * of returned packets.
1896                  */
1897                 rx_pkts[nb_rx++] = rxm;
1898         }
1899         rxq->rx_tail = rx_id;
1900
1901         /*
1902          * If the number of free RX descriptors is greater than the RX free
1903          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1904          * register.
1905          * Update the RDT with the value of the last processed RX descriptor
1906          * minus 1, to guarantee that the RDT register is never equal to the
1907          * RDH register, which creates a "full" ring situtation from the
1908          * hardware point of view...
1909          */
1910         nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1911         if (nb_hold > rxq->rx_free_thresh) {
1912                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1913                            "nb_hold=%u nb_rx=%u",
1914                            (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1915                            (unsigned) rx_id, (unsigned) nb_hold,
1916                            (unsigned) nb_rx);
1917                 rx_id = (uint16_t) ((rx_id == 0) ?
1918                                      (rxq->nb_rx_desc - 1) : (rx_id - 1));
1919                 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1920                 nb_hold = 0;
1921         }
1922         rxq->nb_rx_hold = nb_hold;
1923         return nb_rx;
1924 }
1925
1926 /**
1927  * Detect an RSC descriptor.
1928  */
1929 static inline uint32_t
1930 ixgbe_rsc_count(union ixgbe_adv_rx_desc *rx)
1931 {
1932         return (rte_le_to_cpu_32(rx->wb.lower.lo_dword.data) &
1933                 IXGBE_RXDADV_RSCCNT_MASK) >> IXGBE_RXDADV_RSCCNT_SHIFT;
1934 }
1935
1936 /**
1937  * ixgbe_fill_cluster_head_buf - fill the first mbuf of the returned packet
1938  *
1939  * Fill the following info in the HEAD buffer of the Rx cluster:
1940  *    - RX port identifier
1941  *    - hardware offload data, if any:
1942  *      - RSS flag & hash
1943  *      - IP checksum flag
1944  *      - VLAN TCI, if any
1945  *      - error flags
1946  * @head HEAD of the packet cluster
1947  * @desc HW descriptor to get data from
1948  * @rxq Pointer to the Rx queue
1949  */
1950 static inline void
1951 ixgbe_fill_cluster_head_buf(
1952         struct rte_mbuf *head,
1953         union ixgbe_adv_rx_desc *desc,
1954         struct ixgbe_rx_queue *rxq,
1955         uint32_t staterr)
1956 {
1957         uint32_t pkt_info;
1958         uint64_t pkt_flags;
1959
1960         head->port = rxq->port_id;
1961
1962         /* The vlan_tci field is only valid when PKT_RX_VLAN is
1963          * set in the pkt_flags field.
1964          */
1965         head->vlan_tci = rte_le_to_cpu_16(desc->wb.upper.vlan);
1966         pkt_info = rte_le_to_cpu_32(desc->wb.lower.lo_dword.data);
1967         pkt_flags = rx_desc_status_to_pkt_flags(staterr, rxq->vlan_flags);
1968         pkt_flags |= rx_desc_error_to_pkt_flags(staterr);
1969         pkt_flags |= ixgbe_rxd_pkt_info_to_pkt_flags((uint16_t)pkt_info);
1970         head->ol_flags = pkt_flags;
1971         head->packet_type =
1972                 ixgbe_rxd_pkt_info_to_pkt_type(pkt_info, rxq->pkt_type_mask);
1973
1974         if (likely(pkt_flags & PKT_RX_RSS_HASH))
1975                 head->hash.rss = rte_le_to_cpu_32(desc->wb.lower.hi_dword.rss);
1976         else if (pkt_flags & PKT_RX_FDIR) {
1977                 head->hash.fdir.hash =
1978                         rte_le_to_cpu_16(desc->wb.lower.hi_dword.csum_ip.csum)
1979                                                           & IXGBE_ATR_HASH_MASK;
1980                 head->hash.fdir.id =
1981                         rte_le_to_cpu_16(desc->wb.lower.hi_dword.csum_ip.ip_id);
1982         }
1983 }
1984
1985 /**
1986  * ixgbe_recv_pkts_lro - receive handler for and LRO case.
1987  *
1988  * @rx_queue Rx queue handle
1989  * @rx_pkts table of received packets
1990  * @nb_pkts size of rx_pkts table
1991  * @bulk_alloc if TRUE bulk allocation is used for a HW ring refilling
1992  *
1993  * Handles the Rx HW ring completions when RSC feature is configured. Uses an
1994  * additional ring of ixgbe_rsc_entry's that will hold the relevant RSC info.
1995  *
1996  * We use the same logic as in Linux and in FreeBSD ixgbe drivers:
1997  * 1) When non-EOP RSC completion arrives:
1998  *    a) Update the HEAD of the current RSC aggregation cluster with the new
1999  *       segment's data length.
2000  *    b) Set the "next" pointer of the current segment to point to the segment
2001  *       at the NEXTP index.
2002  *    c) Pass the HEAD of RSC aggregation cluster on to the next NEXTP entry
2003  *       in the sw_rsc_ring.
2004  * 2) When EOP arrives we just update the cluster's total length and offload
2005  *    flags and deliver the cluster up to the upper layers. In our case - put it
2006  *    in the rx_pkts table.
2007  *
2008  * Returns the number of received packets/clusters (according to the "bulk
2009  * receive" interface).
2010  */
2011 static inline uint16_t
2012 ixgbe_recv_pkts_lro(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts,
2013                     bool bulk_alloc)
2014 {
2015         struct ixgbe_rx_queue *rxq = rx_queue;
2016         volatile union ixgbe_adv_rx_desc *rx_ring = rxq->rx_ring;
2017         struct ixgbe_rx_entry *sw_ring = rxq->sw_ring;
2018         struct ixgbe_scattered_rx_entry *sw_sc_ring = rxq->sw_sc_ring;
2019         uint16_t rx_id = rxq->rx_tail;
2020         uint16_t nb_rx = 0;
2021         uint16_t nb_hold = rxq->nb_rx_hold;
2022         uint16_t prev_id = rxq->rx_tail;
2023
2024         while (nb_rx < nb_pkts) {
2025                 bool eop;
2026                 struct ixgbe_rx_entry *rxe;
2027                 struct ixgbe_scattered_rx_entry *sc_entry;
2028                 struct ixgbe_scattered_rx_entry *next_sc_entry;
2029                 struct ixgbe_rx_entry *next_rxe = NULL;
2030                 struct rte_mbuf *first_seg;
2031                 struct rte_mbuf *rxm;
2032                 struct rte_mbuf *nmb;
2033                 union ixgbe_adv_rx_desc rxd;
2034                 uint16_t data_len;
2035                 uint16_t next_id;
2036                 volatile union ixgbe_adv_rx_desc *rxdp;
2037                 uint32_t staterr;
2038
2039 next_desc:
2040                 /*
2041                  * The code in this whole file uses the volatile pointer to
2042                  * ensure the read ordering of the status and the rest of the
2043                  * descriptor fields (on the compiler level only!!!). This is so
2044                  * UGLY - why not to just use the compiler barrier instead? DPDK
2045                  * even has the rte_compiler_barrier() for that.
2046                  *
2047                  * But most importantly this is just wrong because this doesn't
2048                  * ensure memory ordering in a general case at all. For
2049                  * instance, DPDK is supposed to work on Power CPUs where
2050                  * compiler barrier may just not be enough!
2051                  *
2052                  * I tried to write only this function properly to have a
2053                  * starting point (as a part of an LRO/RSC series) but the
2054                  * compiler cursed at me when I tried to cast away the
2055                  * "volatile" from rx_ring (yes, it's volatile too!!!). So, I'm
2056                  * keeping it the way it is for now.
2057                  *
2058                  * The code in this file is broken in so many other places and
2059                  * will just not work on a big endian CPU anyway therefore the
2060                  * lines below will have to be revisited together with the rest
2061                  * of the ixgbe PMD.
2062                  *
2063                  * TODO:
2064                  *    - Get rid of "volatile" and let the compiler do its job.
2065                  *    - Use the proper memory barrier (rte_rmb()) to ensure the
2066                  *      memory ordering below.
2067                  */
2068                 rxdp = &rx_ring[rx_id];
2069                 staterr = rte_le_to_cpu_32(rxdp->wb.upper.status_error);
2070
2071                 if (!(staterr & IXGBE_RXDADV_STAT_DD))
2072                         break;
2073
2074                 rxd = *rxdp;
2075
2076                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
2077                                   "staterr=0x%x data_len=%u",
2078                            rxq->port_id, rxq->queue_id, rx_id, staterr,
2079                            rte_le_to_cpu_16(rxd.wb.upper.length));
2080
2081                 if (!bulk_alloc) {
2082                         nmb = rte_mbuf_raw_alloc(rxq->mb_pool);
2083                         if (nmb == NULL) {
2084                                 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed "
2085                                                   "port_id=%u queue_id=%u",
2086                                            rxq->port_id, rxq->queue_id);
2087
2088                                 rte_eth_devices[rxq->port_id].data->
2089                                                         rx_mbuf_alloc_failed++;
2090                                 break;
2091                         }
2092                 } else if (nb_hold > rxq->rx_free_thresh) {
2093                         uint16_t next_rdt = rxq->rx_free_trigger;
2094
2095                         if (!ixgbe_rx_alloc_bufs(rxq, false)) {
2096                                 rte_wmb();
2097                                 IXGBE_PCI_REG_WRITE_RELAXED(rxq->rdt_reg_addr,
2098                                                             next_rdt);
2099                                 nb_hold -= rxq->rx_free_thresh;
2100                         } else {
2101                                 PMD_RX_LOG(DEBUG, "RX bulk alloc failed "
2102                                                   "port_id=%u queue_id=%u",
2103                                            rxq->port_id, rxq->queue_id);
2104
2105                                 rte_eth_devices[rxq->port_id].data->
2106                                                         rx_mbuf_alloc_failed++;
2107                                 break;
2108                         }
2109                 }
2110
2111                 nb_hold++;
2112                 rxe = &sw_ring[rx_id];
2113                 eop = staterr & IXGBE_RXDADV_STAT_EOP;
2114
2115                 next_id = rx_id + 1;
2116                 if (next_id == rxq->nb_rx_desc)
2117                         next_id = 0;
2118
2119                 /* Prefetch next mbuf while processing current one. */
2120                 rte_ixgbe_prefetch(sw_ring[next_id].mbuf);
2121
2122                 /*
2123                  * When next RX descriptor is on a cache-line boundary,
2124                  * prefetch the next 4 RX descriptors and the next 4 pointers
2125                  * to mbufs.
2126                  */
2127                 if ((next_id & 0x3) == 0) {
2128                         rte_ixgbe_prefetch(&rx_ring[next_id]);
2129                         rte_ixgbe_prefetch(&sw_ring[next_id]);
2130                 }
2131
2132                 rxm = rxe->mbuf;
2133
2134                 if (!bulk_alloc) {
2135                         __le64 dma =
2136                           rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
2137                         /*
2138                          * Update RX descriptor with the physical address of the
2139                          * new data buffer of the new allocated mbuf.
2140                          */
2141                         rxe->mbuf = nmb;
2142
2143                         rxm->data_off = RTE_PKTMBUF_HEADROOM;
2144                         rxdp->read.hdr_addr = 0;
2145                         rxdp->read.pkt_addr = dma;
2146                 } else
2147                         rxe->mbuf = NULL;
2148
2149                 /*
2150                  * Set data length & data buffer address of mbuf.
2151                  */
2152                 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
2153                 rxm->data_len = data_len;
2154
2155                 if (!eop) {
2156                         uint16_t nextp_id;
2157                         /*
2158                          * Get next descriptor index:
2159                          *  - For RSC it's in the NEXTP field.
2160                          *  - For a scattered packet - it's just a following
2161                          *    descriptor.
2162                          */
2163                         if (ixgbe_rsc_count(&rxd))
2164                                 nextp_id =
2165                                         (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
2166                                                        IXGBE_RXDADV_NEXTP_SHIFT;
2167                         else
2168                                 nextp_id = next_id;
2169
2170                         next_sc_entry = &sw_sc_ring[nextp_id];
2171                         next_rxe = &sw_ring[nextp_id];
2172                         rte_ixgbe_prefetch(next_rxe);
2173                 }
2174
2175                 sc_entry = &sw_sc_ring[rx_id];
2176                 first_seg = sc_entry->fbuf;
2177                 sc_entry->fbuf = NULL;
2178
2179                 /*
2180                  * If this is the first buffer of the received packet,
2181                  * set the pointer to the first mbuf of the packet and
2182                  * initialize its context.
2183                  * Otherwise, update the total length and the number of segments
2184                  * of the current scattered packet, and update the pointer to
2185                  * the last mbuf of the current packet.
2186                  */
2187                 if (first_seg == NULL) {
2188                         first_seg = rxm;
2189                         first_seg->pkt_len = data_len;
2190                         first_seg->nb_segs = 1;
2191                 } else {
2192                         first_seg->pkt_len += data_len;
2193                         first_seg->nb_segs++;
2194                 }
2195
2196                 prev_id = rx_id;
2197                 rx_id = next_id;
2198
2199                 /*
2200                  * If this is not the last buffer of the received packet, update
2201                  * the pointer to the first mbuf at the NEXTP entry in the
2202                  * sw_sc_ring and continue to parse the RX ring.
2203                  */
2204                 if (!eop && next_rxe) {
2205                         rxm->next = next_rxe->mbuf;
2206                         next_sc_entry->fbuf = first_seg;
2207                         goto next_desc;
2208                 }
2209
2210                 /* Initialize the first mbuf of the returned packet */
2211                 ixgbe_fill_cluster_head_buf(first_seg, &rxd, rxq, staterr);
2212
2213                 /*
2214                  * Deal with the case, when HW CRC srip is disabled.
2215                  * That can't happen when LRO is enabled, but still could
2216                  * happen for scattered RX mode.
2217                  */
2218                 first_seg->pkt_len -= rxq->crc_len;
2219                 if (unlikely(rxm->data_len <= rxq->crc_len)) {
2220                         struct rte_mbuf *lp;
2221
2222                         for (lp = first_seg; lp->next != rxm; lp = lp->next)
2223                                 ;
2224
2225                         first_seg->nb_segs--;
2226                         lp->data_len -= rxq->crc_len - rxm->data_len;
2227                         lp->next = NULL;
2228                         rte_pktmbuf_free_seg(rxm);
2229                 } else
2230                         rxm->data_len -= rxq->crc_len;
2231
2232                 /* Prefetch data of first segment, if configured to do so. */
2233                 rte_packet_prefetch((char *)first_seg->buf_addr +
2234                         first_seg->data_off);
2235
2236                 /*
2237                  * Store the mbuf address into the next entry of the array
2238                  * of returned packets.
2239                  */
2240                 rx_pkts[nb_rx++] = first_seg;
2241         }
2242
2243         /*
2244          * Record index of the next RX descriptor to probe.
2245          */
2246         rxq->rx_tail = rx_id;
2247
2248         /*
2249          * If the number of free RX descriptors is greater than the RX free
2250          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
2251          * register.
2252          * Update the RDT with the value of the last processed RX descriptor
2253          * minus 1, to guarantee that the RDT register is never equal to the
2254          * RDH register, which creates a "full" ring situtation from the
2255          * hardware point of view...
2256          */
2257         if (!bulk_alloc && nb_hold > rxq->rx_free_thresh) {
2258                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
2259                            "nb_hold=%u nb_rx=%u",
2260                            rxq->port_id, rxq->queue_id, rx_id, nb_hold, nb_rx);
2261
2262                 rte_wmb();
2263                 IXGBE_PCI_REG_WRITE_RELAXED(rxq->rdt_reg_addr, prev_id);
2264                 nb_hold = 0;
2265         }
2266
2267         rxq->nb_rx_hold = nb_hold;
2268         return nb_rx;
2269 }
2270
2271 uint16_t
2272 ixgbe_recv_pkts_lro_single_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
2273                                  uint16_t nb_pkts)
2274 {
2275         return ixgbe_recv_pkts_lro(rx_queue, rx_pkts, nb_pkts, false);
2276 }
2277
2278 uint16_t
2279 ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
2280                                uint16_t nb_pkts)
2281 {
2282         return ixgbe_recv_pkts_lro(rx_queue, rx_pkts, nb_pkts, true);
2283 }
2284
2285 /*********************************************************************
2286  *
2287  *  Queue management functions
2288  *
2289  **********************************************************************/
2290
2291 static void __attribute__((cold))
2292 ixgbe_tx_queue_release_mbufs(struct ixgbe_tx_queue *txq)
2293 {
2294         unsigned i;
2295
2296         if (txq->sw_ring != NULL) {
2297                 for (i = 0; i < txq->nb_tx_desc; i++) {
2298                         if (txq->sw_ring[i].mbuf != NULL) {
2299                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2300                                 txq->sw_ring[i].mbuf = NULL;
2301                         }
2302                 }
2303         }
2304 }
2305
2306 static void __attribute__((cold))
2307 ixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)
2308 {
2309         if (txq != NULL &&
2310             txq->sw_ring != NULL)
2311                 rte_free(txq->sw_ring);
2312 }
2313
2314 static void __attribute__((cold))
2315 ixgbe_tx_queue_release(struct ixgbe_tx_queue *txq)
2316 {
2317         if (txq != NULL && txq->ops != NULL) {
2318                 txq->ops->release_mbufs(txq);
2319                 txq->ops->free_swring(txq);
2320                 rte_free(txq);
2321         }
2322 }
2323
2324 void __attribute__((cold))
2325 ixgbe_dev_tx_queue_release(void *txq)
2326 {
2327         ixgbe_tx_queue_release(txq);
2328 }
2329
2330 /* (Re)set dynamic ixgbe_tx_queue fields to defaults */
2331 static void __attribute__((cold))
2332 ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)
2333 {
2334         static const union ixgbe_adv_tx_desc zeroed_desc = {{0}};
2335         struct ixgbe_tx_entry *txe = txq->sw_ring;
2336         uint16_t prev, i;
2337
2338         /* Zero out HW ring memory */
2339         for (i = 0; i < txq->nb_tx_desc; i++) {
2340                 txq->tx_ring[i] = zeroed_desc;
2341         }
2342
2343         /* Initialize SW ring entries */
2344         prev = (uint16_t) (txq->nb_tx_desc - 1);
2345         for (i = 0; i < txq->nb_tx_desc; i++) {
2346                 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
2347
2348                 txd->wb.status = rte_cpu_to_le_32(IXGBE_TXD_STAT_DD);
2349                 txe[i].mbuf = NULL;
2350                 txe[i].last_id = i;
2351                 txe[prev].next_id = i;
2352                 prev = i;
2353         }
2354
2355         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2356         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2357
2358         txq->tx_tail = 0;
2359         txq->nb_tx_used = 0;
2360         /*
2361          * Always allow 1 descriptor to be un-allocated to avoid
2362          * a H/W race condition
2363          */
2364         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2365         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2366         txq->ctx_curr = 0;
2367         memset((void *)&txq->ctx_cache, 0,
2368                 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
2369 }
2370
2371 static const struct ixgbe_txq_ops def_txq_ops = {
2372         .release_mbufs = ixgbe_tx_queue_release_mbufs,
2373         .free_swring = ixgbe_tx_free_swring,
2374         .reset = ixgbe_reset_tx_queue,
2375 };
2376
2377 /* Takes an ethdev and a queue and sets up the tx function to be used based on
2378  * the queue parameters. Used in tx_queue_setup by primary process and then
2379  * in dev_init by secondary process when attaching to an existing ethdev.
2380  */
2381 void __attribute__((cold))
2382 ixgbe_set_tx_function(struct rte_eth_dev *dev, struct ixgbe_tx_queue *txq)
2383 {
2384         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
2385         if ((txq->offloads == 0) &&
2386 #ifdef RTE_LIBRTE_SECURITY
2387                         !(txq->using_ipsec) &&
2388 #endif
2389                         (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
2390                 PMD_INIT_LOG(DEBUG, "Using simple tx code path");
2391                 dev->tx_pkt_prepare = NULL;
2392 #ifdef RTE_IXGBE_INC_VECTOR
2393                 if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
2394                                 (rte_eal_process_type() != RTE_PROC_PRIMARY ||
2395                                         ixgbe_txq_vec_setup(txq) == 0)) {
2396                         PMD_INIT_LOG(DEBUG, "Vector tx enabled.");
2397                         dev->tx_pkt_burst = ixgbe_xmit_pkts_vec;
2398                 } else
2399 #endif
2400                 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
2401         } else {
2402                 PMD_INIT_LOG(DEBUG, "Using full-featured tx code path");
2403                 PMD_INIT_LOG(DEBUG,
2404                                 " - offloads = 0x%" PRIx64,
2405                                 txq->offloads);
2406                 PMD_INIT_LOG(DEBUG,
2407                                 " - tx_rs_thresh = %lu " "[RTE_PMD_IXGBE_TX_MAX_BURST=%lu]",
2408                                 (unsigned long)txq->tx_rs_thresh,
2409                                 (unsigned long)RTE_PMD_IXGBE_TX_MAX_BURST);
2410                 dev->tx_pkt_burst = ixgbe_xmit_pkts;
2411                 dev->tx_pkt_prepare = ixgbe_prep_pkts;
2412         }
2413 }
2414
2415 uint64_t
2416 ixgbe_get_tx_queue_offloads(struct rte_eth_dev *dev)
2417 {
2418         RTE_SET_USED(dev);
2419
2420         return 0;
2421 }
2422
2423 uint64_t
2424 ixgbe_get_tx_port_offloads(struct rte_eth_dev *dev)
2425 {
2426         uint64_t tx_offload_capa;
2427         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2428
2429         tx_offload_capa =
2430                 DEV_TX_OFFLOAD_VLAN_INSERT |
2431                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2432                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2433                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2434                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2435                 DEV_TX_OFFLOAD_TCP_TSO     |
2436                 DEV_TX_OFFLOAD_MULTI_SEGS;
2437
2438         if (hw->mac.type == ixgbe_mac_82599EB ||
2439             hw->mac.type == ixgbe_mac_X540)
2440                 tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
2441
2442         if (hw->mac.type == ixgbe_mac_X550 ||
2443             hw->mac.type == ixgbe_mac_X550EM_x ||
2444             hw->mac.type == ixgbe_mac_X550EM_a)
2445                 tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
2446
2447 #ifdef RTE_LIBRTE_SECURITY
2448         if (dev->security_ctx)
2449                 tx_offload_capa |= DEV_TX_OFFLOAD_SECURITY;
2450 #endif
2451         return tx_offload_capa;
2452 }
2453
2454 int __attribute__((cold))
2455 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
2456                          uint16_t queue_idx,
2457                          uint16_t nb_desc,
2458                          unsigned int socket_id,
2459                          const struct rte_eth_txconf *tx_conf)
2460 {
2461         const struct rte_memzone *tz;
2462         struct ixgbe_tx_queue *txq;
2463         struct ixgbe_hw     *hw;
2464         uint16_t tx_rs_thresh, tx_free_thresh;
2465         uint64_t offloads;
2466
2467         PMD_INIT_FUNC_TRACE();
2468         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2469
2470         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
2471
2472         /*
2473          * Validate number of transmit descriptors.
2474          * It must not exceed hardware maximum, and must be multiple
2475          * of IXGBE_ALIGN.
2476          */
2477         if (nb_desc % IXGBE_TXD_ALIGN != 0 ||
2478                         (nb_desc > IXGBE_MAX_RING_DESC) ||
2479                         (nb_desc < IXGBE_MIN_RING_DESC)) {
2480                 return -EINVAL;
2481         }
2482
2483         /*
2484          * The following two parameters control the setting of the RS bit on
2485          * transmit descriptors.
2486          * TX descriptors will have their RS bit set after txq->tx_rs_thresh
2487          * descriptors have been used.
2488          * The TX descriptor ring will be cleaned after txq->tx_free_thresh
2489          * descriptors are used or if the number of descriptors required
2490          * to transmit a packet is greater than the number of free TX
2491          * descriptors.
2492          * The following constraints must be satisfied:
2493          *  tx_rs_thresh must be greater than 0.
2494          *  tx_rs_thresh must be less than the size of the ring minus 2.
2495          *  tx_rs_thresh must be less than or equal to tx_free_thresh.
2496          *  tx_rs_thresh must be a divisor of the ring size.
2497          *  tx_free_thresh must be greater than 0.
2498          *  tx_free_thresh must be less than the size of the ring minus 3.
2499          * One descriptor in the TX ring is used as a sentinel to avoid a
2500          * H/W race condition, hence the maximum threshold constraints.
2501          * When set to zero use default values.
2502          */
2503         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2504                         tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2505         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2506                         tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2507         if (tx_rs_thresh >= (nb_desc - 2)) {
2508                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the number "
2509                         "of TX descriptors minus 2. (tx_rs_thresh=%u "
2510                         "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2511                         (int)dev->data->port_id, (int)queue_idx);
2512                 return -(EINVAL);
2513         }
2514         if (tx_rs_thresh > DEFAULT_TX_RS_THRESH) {
2515                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less or equal than %u. "
2516                         "(tx_rs_thresh=%u port=%d queue=%d)",
2517                         DEFAULT_TX_RS_THRESH, (unsigned int)tx_rs_thresh,
2518                         (int)dev->data->port_id, (int)queue_idx);
2519                 return -(EINVAL);
2520         }
2521         if (tx_free_thresh >= (nb_desc - 3)) {
2522                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2523                              "tx_free_thresh must be less than the number of "
2524                              "TX descriptors minus 3. (tx_free_thresh=%u "
2525                              "port=%d queue=%d)",
2526                              (unsigned int)tx_free_thresh,
2527                              (int)dev->data->port_id, (int)queue_idx);
2528                 return -(EINVAL);
2529         }
2530         if (tx_rs_thresh > tx_free_thresh) {
2531                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or equal to "
2532                              "tx_free_thresh. (tx_free_thresh=%u "
2533                              "tx_rs_thresh=%u port=%d queue=%d)",
2534                              (unsigned int)tx_free_thresh,
2535                              (unsigned int)tx_rs_thresh,
2536                              (int)dev->data->port_id,
2537                              (int)queue_idx);
2538                 return -(EINVAL);
2539         }
2540         if ((nb_desc % tx_rs_thresh) != 0) {
2541                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2542                              "number of TX descriptors. (tx_rs_thresh=%u "
2543                              "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2544                              (int)dev->data->port_id, (int)queue_idx);
2545                 return -(EINVAL);
2546         }
2547
2548         /*
2549          * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
2550          * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
2551          * by the NIC and all descriptors are written back after the NIC
2552          * accumulates WTHRESH descriptors.
2553          */
2554         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2555                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2556                              "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
2557                              "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2558                              (int)dev->data->port_id, (int)queue_idx);
2559                 return -(EINVAL);
2560         }
2561
2562         /* Free memory prior to re-allocation if needed... */
2563         if (dev->data->tx_queues[queue_idx] != NULL) {
2564                 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
2565                 dev->data->tx_queues[queue_idx] = NULL;
2566         }
2567
2568         /* First allocate the tx queue data structure */
2569         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct ixgbe_tx_queue),
2570                                  RTE_CACHE_LINE_SIZE, socket_id);
2571         if (txq == NULL)
2572                 return -ENOMEM;
2573
2574         /*
2575          * Allocate TX ring hardware descriptors. A memzone large enough to
2576          * handle the maximum ring size is allocated in order to allow for
2577          * resizing in later calls to the queue setup function.
2578          */
2579         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2580                         sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
2581                         IXGBE_ALIGN, socket_id);
2582         if (tz == NULL) {
2583                 ixgbe_tx_queue_release(txq);
2584                 return -ENOMEM;
2585         }
2586
2587         txq->nb_tx_desc = nb_desc;
2588         txq->tx_rs_thresh = tx_rs_thresh;
2589         txq->tx_free_thresh = tx_free_thresh;
2590         txq->pthresh = tx_conf->tx_thresh.pthresh;
2591         txq->hthresh = tx_conf->tx_thresh.hthresh;
2592         txq->wthresh = tx_conf->tx_thresh.wthresh;
2593         txq->queue_id = queue_idx;
2594         txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2595                 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2596         txq->port_id = dev->data->port_id;
2597         txq->offloads = offloads;
2598         txq->ops = &def_txq_ops;
2599         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2600 #ifdef RTE_LIBRTE_SECURITY
2601         txq->using_ipsec = !!(dev->data->dev_conf.txmode.offloads &
2602                         DEV_TX_OFFLOAD_SECURITY);
2603 #endif
2604
2605         /*
2606          * Modification to set VFTDT for virtual function if vf is detected
2607          */
2608         if (hw->mac.type == ixgbe_mac_82599_vf ||
2609             hw->mac.type == ixgbe_mac_X540_vf ||
2610             hw->mac.type == ixgbe_mac_X550_vf ||
2611             hw->mac.type == ixgbe_mac_X550EM_x_vf ||
2612             hw->mac.type == ixgbe_mac_X550EM_a_vf)
2613                 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
2614         else
2615                 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));
2616
2617         txq->tx_ring_phys_addr = tz->iova;
2618         txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
2619
2620         /* Allocate software ring */
2621         txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
2622                                 sizeof(struct ixgbe_tx_entry) * nb_desc,
2623                                 RTE_CACHE_LINE_SIZE, socket_id);
2624         if (txq->sw_ring == NULL) {
2625                 ixgbe_tx_queue_release(txq);
2626                 return -ENOMEM;
2627         }
2628         PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
2629                      txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
2630
2631         /* set up vector or scalar TX function as appropriate */
2632         ixgbe_set_tx_function(dev, txq);
2633
2634         txq->ops->reset(txq);
2635
2636         dev->data->tx_queues[queue_idx] = txq;
2637
2638
2639         return 0;
2640 }
2641
2642 /**
2643  * ixgbe_free_sc_cluster - free the not-yet-completed scattered cluster
2644  *
2645  * The "next" pointer of the last segment of (not-yet-completed) RSC clusters
2646  * in the sw_rsc_ring is not set to NULL but rather points to the next
2647  * mbuf of this RSC aggregation (that has not been completed yet and still
2648  * resides on the HW ring). So, instead of calling for rte_pktmbuf_free() we
2649  * will just free first "nb_segs" segments of the cluster explicitly by calling
2650  * an rte_pktmbuf_free_seg().
2651  *
2652  * @m scattered cluster head
2653  */
2654 static void __attribute__((cold))
2655 ixgbe_free_sc_cluster(struct rte_mbuf *m)
2656 {
2657         uint16_t i, nb_segs = m->nb_segs;
2658         struct rte_mbuf *next_seg;
2659
2660         for (i = 0; i < nb_segs; i++) {
2661                 next_seg = m->next;
2662                 rte_pktmbuf_free_seg(m);
2663                 m = next_seg;
2664         }
2665 }
2666
2667 static void __attribute__((cold))
2668 ixgbe_rx_queue_release_mbufs(struct ixgbe_rx_queue *rxq)
2669 {
2670         unsigned i;
2671
2672 #ifdef RTE_IXGBE_INC_VECTOR
2673         /* SSE Vector driver has a different way of releasing mbufs. */
2674         if (rxq->rx_using_sse) {
2675                 ixgbe_rx_queue_release_mbufs_vec(rxq);
2676                 return;
2677         }
2678 #endif
2679
2680         if (rxq->sw_ring != NULL) {
2681                 for (i = 0; i < rxq->nb_rx_desc; i++) {
2682                         if (rxq->sw_ring[i].mbuf != NULL) {
2683                                 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2684                                 rxq->sw_ring[i].mbuf = NULL;
2685                         }
2686                 }
2687                 if (rxq->rx_nb_avail) {
2688                         for (i = 0; i < rxq->rx_nb_avail; ++i) {
2689                                 struct rte_mbuf *mb;
2690
2691                                 mb = rxq->rx_stage[rxq->rx_next_avail + i];
2692                                 rte_pktmbuf_free_seg(mb);
2693                         }
2694                         rxq->rx_nb_avail = 0;
2695                 }
2696         }
2697
2698         if (rxq->sw_sc_ring)
2699                 for (i = 0; i < rxq->nb_rx_desc; i++)
2700                         if (rxq->sw_sc_ring[i].fbuf) {
2701                                 ixgbe_free_sc_cluster(rxq->sw_sc_ring[i].fbuf);
2702                                 rxq->sw_sc_ring[i].fbuf = NULL;
2703                         }
2704 }
2705
2706 static void __attribute__((cold))
2707 ixgbe_rx_queue_release(struct ixgbe_rx_queue *rxq)
2708 {
2709         if (rxq != NULL) {
2710                 ixgbe_rx_queue_release_mbufs(rxq);
2711                 rte_free(rxq->sw_ring);
2712                 rte_free(rxq->sw_sc_ring);
2713                 rte_free(rxq);
2714         }
2715 }
2716
2717 void __attribute__((cold))
2718 ixgbe_dev_rx_queue_release(void *rxq)
2719 {
2720         ixgbe_rx_queue_release(rxq);
2721 }
2722
2723 /*
2724  * Check if Rx Burst Bulk Alloc function can be used.
2725  * Return
2726  *        0: the preconditions are satisfied and the bulk allocation function
2727  *           can be used.
2728  *  -EINVAL: the preconditions are NOT satisfied and the default Rx burst
2729  *           function must be used.
2730  */
2731 static inline int __attribute__((cold))
2732 check_rx_burst_bulk_alloc_preconditions(struct ixgbe_rx_queue *rxq)
2733 {
2734         int ret = 0;
2735
2736         /*
2737          * Make sure the following pre-conditions are satisfied:
2738          *   rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
2739          *   rxq->rx_free_thresh < rxq->nb_rx_desc
2740          *   (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
2741          * Scattered packets are not supported.  This should be checked
2742          * outside of this function.
2743          */
2744         if (!(rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST)) {
2745                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2746                              "rxq->rx_free_thresh=%d, "
2747                              "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2748                              rxq->rx_free_thresh, RTE_PMD_IXGBE_RX_MAX_BURST);
2749                 ret = -EINVAL;
2750         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
2751                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2752                              "rxq->rx_free_thresh=%d, "
2753                              "rxq->nb_rx_desc=%d",
2754                              rxq->rx_free_thresh, rxq->nb_rx_desc);
2755                 ret = -EINVAL;
2756         } else if (!((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0)) {
2757                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2758                              "rxq->nb_rx_desc=%d, "
2759                              "rxq->rx_free_thresh=%d",
2760                              rxq->nb_rx_desc, rxq->rx_free_thresh);
2761                 ret = -EINVAL;
2762         }
2763
2764         return ret;
2765 }
2766
2767 /* Reset dynamic ixgbe_rx_queue fields back to defaults */
2768 static void __attribute__((cold))
2769 ixgbe_reset_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_rx_queue *rxq)
2770 {
2771         static const union ixgbe_adv_rx_desc zeroed_desc = {{0}};
2772         unsigned i;
2773         uint16_t len = rxq->nb_rx_desc;
2774
2775         /*
2776          * By default, the Rx queue setup function allocates enough memory for
2777          * IXGBE_MAX_RING_DESC.  The Rx Burst bulk allocation function requires
2778          * extra memory at the end of the descriptor ring to be zero'd out.
2779          */
2780         if (adapter->rx_bulk_alloc_allowed)
2781                 /* zero out extra memory */
2782                 len += RTE_PMD_IXGBE_RX_MAX_BURST;
2783
2784         /*
2785          * Zero out HW ring memory. Zero out extra memory at the end of
2786          * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2787          * reads extra memory as zeros.
2788          */
2789         for (i = 0; i < len; i++) {
2790                 rxq->rx_ring[i] = zeroed_desc;
2791         }
2792
2793         /*
2794          * initialize extra software ring entries. Space for these extra
2795          * entries is always allocated
2796          */
2797         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2798         for (i = rxq->nb_rx_desc; i < len; ++i) {
2799                 rxq->sw_ring[i].mbuf = &rxq->fake_mbuf;
2800         }
2801
2802         rxq->rx_nb_avail = 0;
2803         rxq->rx_next_avail = 0;
2804         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2805         rxq->rx_tail = 0;
2806         rxq->nb_rx_hold = 0;
2807         rxq->pkt_first_seg = NULL;
2808         rxq->pkt_last_seg = NULL;
2809
2810 #ifdef RTE_IXGBE_INC_VECTOR
2811         rxq->rxrearm_start = 0;
2812         rxq->rxrearm_nb = 0;
2813 #endif
2814 }
2815
2816 static int
2817 ixgbe_is_vf(struct rte_eth_dev *dev)
2818 {
2819         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2820
2821         switch (hw->mac.type) {
2822         case ixgbe_mac_82599_vf:
2823         case ixgbe_mac_X540_vf:
2824         case ixgbe_mac_X550_vf:
2825         case ixgbe_mac_X550EM_x_vf:
2826         case ixgbe_mac_X550EM_a_vf:
2827                 return 1;
2828         default:
2829                 return 0;
2830         }
2831 }
2832
2833 uint64_t
2834 ixgbe_get_rx_queue_offloads(struct rte_eth_dev *dev)
2835 {
2836         uint64_t offloads = 0;
2837         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2838
2839         if (hw->mac.type != ixgbe_mac_82598EB)
2840                 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2841
2842         return offloads;
2843 }
2844
2845 uint64_t
2846 ixgbe_get_rx_port_offloads(struct rte_eth_dev *dev)
2847 {
2848         uint64_t offloads;
2849         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2850
2851         offloads = DEV_RX_OFFLOAD_IPV4_CKSUM  |
2852                    DEV_RX_OFFLOAD_UDP_CKSUM   |
2853                    DEV_RX_OFFLOAD_TCP_CKSUM   |
2854                    DEV_RX_OFFLOAD_KEEP_CRC    |
2855                    DEV_RX_OFFLOAD_JUMBO_FRAME |
2856                    DEV_RX_OFFLOAD_SCATTER;
2857
2858         if (hw->mac.type == ixgbe_mac_82598EB)
2859                 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2860
2861         if (ixgbe_is_vf(dev) == 0)
2862                 offloads |= (DEV_RX_OFFLOAD_VLAN_FILTER |
2863                              DEV_RX_OFFLOAD_VLAN_EXTEND);
2864
2865         /*
2866          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2867          * mode.
2868          */
2869         if ((hw->mac.type == ixgbe_mac_82599EB ||
2870              hw->mac.type == ixgbe_mac_X540 ||
2871              hw->mac.type == ixgbe_mac_X550) &&
2872             !RTE_ETH_DEV_SRIOV(dev).active)
2873                 offloads |= DEV_RX_OFFLOAD_TCP_LRO;
2874
2875         if (hw->mac.type == ixgbe_mac_82599EB ||
2876             hw->mac.type == ixgbe_mac_X540)
2877                 offloads |= DEV_RX_OFFLOAD_MACSEC_STRIP;
2878
2879         if (hw->mac.type == ixgbe_mac_X550 ||
2880             hw->mac.type == ixgbe_mac_X550EM_x ||
2881             hw->mac.type == ixgbe_mac_X550EM_a)
2882                 offloads |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
2883
2884 #ifdef RTE_LIBRTE_SECURITY
2885         if (dev->security_ctx)
2886                 offloads |= DEV_RX_OFFLOAD_SECURITY;
2887 #endif
2888
2889         return offloads;
2890 }
2891
2892 int __attribute__((cold))
2893 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2894                          uint16_t queue_idx,
2895                          uint16_t nb_desc,
2896                          unsigned int socket_id,
2897                          const struct rte_eth_rxconf *rx_conf,
2898                          struct rte_mempool *mp)
2899 {
2900         const struct rte_memzone *rz;
2901         struct ixgbe_rx_queue *rxq;
2902         struct ixgbe_hw     *hw;
2903         uint16_t len;
2904         struct ixgbe_adapter *adapter =
2905                 (struct ixgbe_adapter *)dev->data->dev_private;
2906         uint64_t offloads;
2907
2908         PMD_INIT_FUNC_TRACE();
2909         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2910
2911         offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
2912
2913         /*
2914          * Validate number of receive descriptors.
2915          * It must not exceed hardware maximum, and must be multiple
2916          * of IXGBE_ALIGN.
2917          */
2918         if (nb_desc % IXGBE_RXD_ALIGN != 0 ||
2919                         (nb_desc > IXGBE_MAX_RING_DESC) ||
2920                         (nb_desc < IXGBE_MIN_RING_DESC)) {
2921                 return -EINVAL;
2922         }
2923
2924         /* Free memory prior to re-allocation if needed... */
2925         if (dev->data->rx_queues[queue_idx] != NULL) {
2926                 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2927                 dev->data->rx_queues[queue_idx] = NULL;
2928         }
2929
2930         /* First allocate the rx queue data structure */
2931         rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct ixgbe_rx_queue),
2932                                  RTE_CACHE_LINE_SIZE, socket_id);
2933         if (rxq == NULL)
2934                 return -ENOMEM;
2935         rxq->mb_pool = mp;
2936         rxq->nb_rx_desc = nb_desc;
2937         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2938         rxq->queue_id = queue_idx;
2939         rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2940                 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2941         rxq->port_id = dev->data->port_id;
2942         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
2943                 rxq->crc_len = ETHER_CRC_LEN;
2944         else
2945                 rxq->crc_len = 0;
2946         rxq->drop_en = rx_conf->rx_drop_en;
2947         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2948         rxq->offloads = offloads;
2949
2950         /*
2951          * The packet type in RX descriptor is different for different NICs.
2952          * Some bits are used for x550 but reserved for other NICS.
2953          * So set different masks for different NICs.
2954          */
2955         if (hw->mac.type == ixgbe_mac_X550 ||
2956             hw->mac.type == ixgbe_mac_X550EM_x ||
2957             hw->mac.type == ixgbe_mac_X550EM_a ||
2958             hw->mac.type == ixgbe_mac_X550_vf ||
2959             hw->mac.type == ixgbe_mac_X550EM_x_vf ||
2960             hw->mac.type == ixgbe_mac_X550EM_a_vf)
2961                 rxq->pkt_type_mask = IXGBE_PACKET_TYPE_MASK_X550;
2962         else
2963                 rxq->pkt_type_mask = IXGBE_PACKET_TYPE_MASK_82599;
2964
2965         /*
2966          * Allocate RX ring hardware descriptors. A memzone large enough to
2967          * handle the maximum ring size is allocated in order to allow for
2968          * resizing in later calls to the queue setup function.
2969          */
2970         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
2971                                       RX_RING_SZ, IXGBE_ALIGN, socket_id);
2972         if (rz == NULL) {
2973                 ixgbe_rx_queue_release(rxq);
2974                 return -ENOMEM;
2975         }
2976
2977         /*
2978          * Zero init all the descriptors in the ring.
2979          */
2980         memset(rz->addr, 0, RX_RING_SZ);
2981
2982         /*
2983          * Modified to setup VFRDT for Virtual Function
2984          */
2985         if (hw->mac.type == ixgbe_mac_82599_vf ||
2986             hw->mac.type == ixgbe_mac_X540_vf ||
2987             hw->mac.type == ixgbe_mac_X550_vf ||
2988             hw->mac.type == ixgbe_mac_X550EM_x_vf ||
2989             hw->mac.type == ixgbe_mac_X550EM_a_vf) {
2990                 rxq->rdt_reg_addr =
2991                         IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
2992                 rxq->rdh_reg_addr =
2993                         IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));
2994         } else {
2995                 rxq->rdt_reg_addr =
2996                         IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));
2997                 rxq->rdh_reg_addr =
2998                         IXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));
2999         }
3000
3001         rxq->rx_ring_phys_addr = rz->iova;
3002         rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
3003
3004         /*
3005          * Certain constraints must be met in order to use the bulk buffer
3006          * allocation Rx burst function. If any of Rx queues doesn't meet them
3007          * the feature should be disabled for the whole port.
3008          */
3009         if (check_rx_burst_bulk_alloc_preconditions(rxq)) {
3010                 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Rx Bulk Alloc "
3011                                     "preconditions - canceling the feature for "
3012                                     "the whole port[%d]",
3013                              rxq->queue_id, rxq->port_id);
3014                 adapter->rx_bulk_alloc_allowed = false;
3015         }
3016
3017         /*
3018          * Allocate software ring. Allow for space at the end of the
3019          * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
3020          * function does not access an invalid memory region.
3021          */
3022         len = nb_desc;
3023         if (adapter->rx_bulk_alloc_allowed)
3024                 len += RTE_PMD_IXGBE_RX_MAX_BURST;
3025
3026         rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
3027                                           sizeof(struct ixgbe_rx_entry) * len,
3028                                           RTE_CACHE_LINE_SIZE, socket_id);
3029         if (!rxq->sw_ring) {
3030                 ixgbe_rx_queue_release(rxq);
3031                 return -ENOMEM;
3032         }
3033
3034         /*
3035          * Always allocate even if it's not going to be needed in order to
3036          * simplify the code.
3037          *
3038          * This ring is used in LRO and Scattered Rx cases and Scattered Rx may
3039          * be requested in ixgbe_dev_rx_init(), which is called later from
3040          * dev_start() flow.
3041          */
3042         rxq->sw_sc_ring =
3043                 rte_zmalloc_socket("rxq->sw_sc_ring",
3044                                    sizeof(struct ixgbe_scattered_rx_entry) * len,
3045                                    RTE_CACHE_LINE_SIZE, socket_id);
3046         if (!rxq->sw_sc_ring) {
3047                 ixgbe_rx_queue_release(rxq);
3048                 return -ENOMEM;
3049         }
3050
3051         PMD_INIT_LOG(DEBUG, "sw_ring=%p sw_sc_ring=%p hw_ring=%p "
3052                             "dma_addr=0x%"PRIx64,
3053                      rxq->sw_ring, rxq->sw_sc_ring, rxq->rx_ring,
3054                      rxq->rx_ring_phys_addr);
3055
3056         if (!rte_is_power_of_2(nb_desc)) {
3057                 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Vector Rx "
3058                                     "preconditions - canceling the feature for "
3059                                     "the whole port[%d]",
3060                              rxq->queue_id, rxq->port_id);
3061                 adapter->rx_vec_allowed = false;
3062         } else
3063                 ixgbe_rxq_vec_setup(rxq);
3064
3065         dev->data->rx_queues[queue_idx] = rxq;
3066
3067         ixgbe_reset_rx_queue(adapter, rxq);
3068
3069         return 0;
3070 }
3071
3072 uint32_t
3073 ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3074 {
3075 #define IXGBE_RXQ_SCAN_INTERVAL 4
3076         volatile union ixgbe_adv_rx_desc *rxdp;
3077         struct ixgbe_rx_queue *rxq;
3078         uint32_t desc = 0;
3079
3080         rxq = dev->data->rx_queues[rx_queue_id];
3081         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
3082
3083         while ((desc < rxq->nb_rx_desc) &&
3084                 (rxdp->wb.upper.status_error &
3085                         rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD))) {
3086                 desc += IXGBE_RXQ_SCAN_INTERVAL;
3087                 rxdp += IXGBE_RXQ_SCAN_INTERVAL;
3088                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
3089                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
3090                                 desc - rxq->nb_rx_desc]);
3091         }
3092
3093         return desc;
3094 }
3095
3096 int
3097 ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
3098 {
3099         volatile union ixgbe_adv_rx_desc *rxdp;
3100         struct ixgbe_rx_queue *rxq = rx_queue;
3101         uint32_t desc;
3102
3103         if (unlikely(offset >= rxq->nb_rx_desc))
3104                 return 0;
3105         desc = rxq->rx_tail + offset;
3106         if (desc >= rxq->nb_rx_desc)
3107                 desc -= rxq->nb_rx_desc;
3108
3109         rxdp = &rxq->rx_ring[desc];
3110         return !!(rxdp->wb.upper.status_error &
3111                         rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD));
3112 }
3113
3114 int
3115 ixgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
3116 {
3117         struct ixgbe_rx_queue *rxq = rx_queue;
3118         volatile uint32_t *status;
3119         uint32_t nb_hold, desc;
3120
3121         if (unlikely(offset >= rxq->nb_rx_desc))
3122                 return -EINVAL;
3123
3124 #ifdef RTE_IXGBE_INC_VECTOR
3125         if (rxq->rx_using_sse)
3126                 nb_hold = rxq->rxrearm_nb;
3127         else
3128 #endif
3129                 nb_hold = rxq->nb_rx_hold;
3130         if (offset >= rxq->nb_rx_desc - nb_hold)
3131                 return RTE_ETH_RX_DESC_UNAVAIL;
3132
3133         desc = rxq->rx_tail + offset;
3134         if (desc >= rxq->nb_rx_desc)
3135                 desc -= rxq->nb_rx_desc;
3136
3137         status = &rxq->rx_ring[desc].wb.upper.status_error;
3138         if (*status & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD))
3139                 return RTE_ETH_RX_DESC_DONE;
3140
3141         return RTE_ETH_RX_DESC_AVAIL;
3142 }
3143
3144 int
3145 ixgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
3146 {
3147         struct ixgbe_tx_queue *txq = tx_queue;
3148         volatile uint32_t *status;
3149         uint32_t desc;
3150
3151         if (unlikely(offset >= txq->nb_tx_desc))
3152                 return -EINVAL;
3153
3154         desc = txq->tx_tail + offset;
3155         /* go to next desc that has the RS bit */
3156         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
3157                 txq->tx_rs_thresh;
3158         if (desc >= txq->nb_tx_desc) {
3159                 desc -= txq->nb_tx_desc;
3160                 if (desc >= txq->nb_tx_desc)
3161                         desc -= txq->nb_tx_desc;
3162         }
3163
3164         status = &txq->tx_ring[desc].wb.status;
3165         if (*status & rte_cpu_to_le_32(IXGBE_ADVTXD_STAT_DD))
3166                 return RTE_ETH_TX_DESC_DONE;
3167
3168         return RTE_ETH_TX_DESC_FULL;
3169 }
3170
3171 void __attribute__((cold))
3172 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
3173 {
3174         unsigned i;
3175         struct ixgbe_adapter *adapter =
3176                 (struct ixgbe_adapter *)dev->data->dev_private;
3177
3178         PMD_INIT_FUNC_TRACE();
3179
3180         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3181                 struct ixgbe_tx_queue *txq = dev->data->tx_queues[i];
3182
3183                 if (txq != NULL) {
3184                         txq->ops->release_mbufs(txq);
3185                         txq->ops->reset(txq);
3186                 }
3187         }
3188
3189         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3190                 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
3191
3192                 if (rxq != NULL) {
3193                         ixgbe_rx_queue_release_mbufs(rxq);
3194                         ixgbe_reset_rx_queue(adapter, rxq);
3195                 }
3196         }
3197 }
3198
3199 void
3200 ixgbe_dev_free_queues(struct rte_eth_dev *dev)
3201 {
3202         unsigned i;
3203
3204         PMD_INIT_FUNC_TRACE();
3205
3206         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3207                 ixgbe_dev_rx_queue_release(dev->data->rx_queues[i]);
3208                 dev->data->rx_queues[i] = NULL;
3209         }
3210         dev->data->nb_rx_queues = 0;
3211
3212         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3213                 ixgbe_dev_tx_queue_release(dev->data->tx_queues[i]);
3214                 dev->data->tx_queues[i] = NULL;
3215         }
3216         dev->data->nb_tx_queues = 0;
3217 }
3218
3219 /*********************************************************************
3220  *
3221  *  Device RX/TX init functions
3222  *
3223  **********************************************************************/
3224
3225 /**
3226  * Receive Side Scaling (RSS)
3227  * See section 7.1.2.8 in the following document:
3228  *     "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
3229  *
3230  * Principles:
3231  * The source and destination IP addresses of the IP header and the source
3232  * and destination ports of TCP/UDP headers, if any, of received packets are
3233  * hashed against a configurable random key to compute a 32-bit RSS hash result.
3234  * The seven (7) LSBs of the 32-bit hash result are used as an index into a
3235  * 128-entry redirection table (RETA).  Each entry of the RETA provides a 3-bit
3236  * RSS output index which is used as the RX queue index where to store the
3237  * received packets.
3238  * The following output is supplied in the RX write-back descriptor:
3239  *     - 32-bit result of the Microsoft RSS hash function,
3240  *     - 4-bit RSS type field.
3241  */
3242
3243 /*
3244  * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
3245  * Used as the default key.
3246  */
3247 static uint8_t rss_intel_key[40] = {
3248         0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
3249         0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
3250         0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
3251         0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
3252         0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
3253 };
3254
3255 static void
3256 ixgbe_rss_disable(struct rte_eth_dev *dev)
3257 {
3258         struct ixgbe_hw *hw;
3259         uint32_t mrqc;
3260         uint32_t mrqc_reg;
3261
3262         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3263         mrqc_reg = ixgbe_mrqc_reg_get(hw->mac.type);
3264         mrqc = IXGBE_READ_REG(hw, mrqc_reg);
3265         mrqc &= ~IXGBE_MRQC_RSSEN;
3266         IXGBE_WRITE_REG(hw, mrqc_reg, mrqc);
3267 }
3268
3269 static void
3270 ixgbe_hw_rss_hash_set(struct ixgbe_hw *hw, struct rte_eth_rss_conf *rss_conf)
3271 {
3272         uint8_t  *hash_key;
3273         uint32_t mrqc;
3274         uint32_t rss_key;
3275         uint64_t rss_hf;
3276         uint16_t i;
3277         uint32_t mrqc_reg;
3278         uint32_t rssrk_reg;
3279
3280         mrqc_reg = ixgbe_mrqc_reg_get(hw->mac.type);
3281         rssrk_reg = ixgbe_rssrk_reg_get(hw->mac.type, 0);
3282
3283         hash_key = rss_conf->rss_key;
3284         if (hash_key != NULL) {
3285                 /* Fill in RSS hash key */
3286                 for (i = 0; i < 10; i++) {
3287                         rss_key  = hash_key[(i * 4)];
3288                         rss_key |= hash_key[(i * 4) + 1] << 8;
3289                         rss_key |= hash_key[(i * 4) + 2] << 16;
3290                         rss_key |= hash_key[(i * 4) + 3] << 24;
3291                         IXGBE_WRITE_REG_ARRAY(hw, rssrk_reg, i, rss_key);
3292                 }
3293         }
3294
3295         /* Set configured hashing protocols in MRQC register */
3296         rss_hf = rss_conf->rss_hf;
3297         mrqc = IXGBE_MRQC_RSSEN; /* Enable RSS */
3298         if (rss_hf & ETH_RSS_IPV4)
3299                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
3300         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
3301                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
3302         if (rss_hf & ETH_RSS_IPV6)
3303                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
3304         if (rss_hf & ETH_RSS_IPV6_EX)
3305                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
3306         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
3307                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3308         if (rss_hf & ETH_RSS_IPV6_TCP_EX)
3309                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
3310         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
3311                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3312         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
3313                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3314         if (rss_hf & ETH_RSS_IPV6_UDP_EX)
3315                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
3316         IXGBE_WRITE_REG(hw, mrqc_reg, mrqc);
3317 }
3318
3319 int
3320 ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
3321                           struct rte_eth_rss_conf *rss_conf)
3322 {
3323         struct ixgbe_hw *hw;
3324         uint32_t mrqc;
3325         uint64_t rss_hf;
3326         uint32_t mrqc_reg;
3327
3328         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3329
3330         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3331                 PMD_DRV_LOG(ERR, "RSS hash update is not supported on this "
3332                         "NIC.");
3333                 return -ENOTSUP;
3334         }
3335         mrqc_reg = ixgbe_mrqc_reg_get(hw->mac.type);
3336
3337         /*
3338          * Excerpt from section 7.1.2.8 Receive-Side Scaling (RSS):
3339          *     "RSS enabling cannot be done dynamically while it must be
3340          *      preceded by a software reset"
3341          * Before changing anything, first check that the update RSS operation
3342          * does not attempt to disable RSS, if RSS was enabled at
3343          * initialization time, or does not attempt to enable RSS, if RSS was
3344          * disabled at initialization time.
3345          */
3346         rss_hf = rss_conf->rss_hf & IXGBE_RSS_OFFLOAD_ALL;
3347         mrqc = IXGBE_READ_REG(hw, mrqc_reg);
3348         if (!(mrqc & IXGBE_MRQC_RSSEN)) { /* RSS disabled */
3349                 if (rss_hf != 0) /* Enable RSS */
3350                         return -(EINVAL);
3351                 return 0; /* Nothing to do */
3352         }
3353         /* RSS enabled */
3354         if (rss_hf == 0) /* Disable RSS */
3355                 return -(EINVAL);
3356         ixgbe_hw_rss_hash_set(hw, rss_conf);
3357         return 0;
3358 }
3359
3360 int
3361 ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
3362                             struct rte_eth_rss_conf *rss_conf)
3363 {
3364         struct ixgbe_hw *hw;
3365         uint8_t *hash_key;
3366         uint32_t mrqc;
3367         uint32_t rss_key;
3368         uint64_t rss_hf;
3369         uint16_t i;
3370         uint32_t mrqc_reg;
3371         uint32_t rssrk_reg;
3372
3373         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3374         mrqc_reg = ixgbe_mrqc_reg_get(hw->mac.type);
3375         rssrk_reg = ixgbe_rssrk_reg_get(hw->mac.type, 0);
3376         hash_key = rss_conf->rss_key;
3377         if (hash_key != NULL) {
3378                 /* Return RSS hash key */
3379                 for (i = 0; i < 10; i++) {
3380                         rss_key = IXGBE_READ_REG_ARRAY(hw, rssrk_reg, i);
3381                         hash_key[(i * 4)] = rss_key & 0x000000FF;
3382                         hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;
3383                         hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;
3384                         hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;
3385                 }
3386         }
3387
3388         /* Get RSS functions configured in MRQC register */
3389         mrqc = IXGBE_READ_REG(hw, mrqc_reg);
3390         if ((mrqc & IXGBE_MRQC_RSSEN) == 0) { /* RSS is disabled */
3391                 rss_conf->rss_hf = 0;
3392                 return 0;
3393         }
3394         rss_hf = 0;
3395         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4)
3396                 rss_hf |= ETH_RSS_IPV4;
3397         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_TCP)
3398                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
3399         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6)
3400                 rss_hf |= ETH_RSS_IPV6;
3401         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX)
3402                 rss_hf |= ETH_RSS_IPV6_EX;
3403         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_TCP)
3404                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
3405         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP)
3406                 rss_hf |= ETH_RSS_IPV6_TCP_EX;
3407         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_UDP)
3408                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
3409         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_UDP)
3410                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
3411         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP)
3412                 rss_hf |= ETH_RSS_IPV6_UDP_EX;
3413         rss_conf->rss_hf = rss_hf;
3414         return 0;
3415 }
3416
3417 static void
3418 ixgbe_rss_configure(struct rte_eth_dev *dev)
3419 {
3420         struct rte_eth_rss_conf rss_conf;
3421         struct ixgbe_adapter *adapter;
3422         struct ixgbe_hw *hw;
3423         uint32_t reta;
3424         uint16_t i;
3425         uint16_t j;
3426         uint16_t sp_reta_size;
3427         uint32_t reta_reg;
3428
3429         PMD_INIT_FUNC_TRACE();
3430         adapter = (struct ixgbe_adapter *)dev->data->dev_private;
3431         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3432
3433         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3434
3435         /*
3436          * Fill in redirection table
3437          * The byte-swap is needed because NIC registers are in
3438          * little-endian order.
3439          */
3440         if (adapter->rss_reta_updated == 0) {
3441                 reta = 0;
3442                 for (i = 0, j = 0; i < sp_reta_size; i++, j++) {
3443                         reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3444
3445                         if (j == dev->data->nb_rx_queues)
3446                                 j = 0;
3447                         reta = (reta << 8) | j;
3448                         if ((i & 3) == 3)
3449                                 IXGBE_WRITE_REG(hw, reta_reg,
3450                                                 rte_bswap32(reta));
3451                 }
3452         }
3453
3454         /*
3455          * Configure the RSS key and the RSS protocols used to compute
3456          * the RSS hash of input packets.
3457          */
3458         rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
3459         if ((rss_conf.rss_hf & IXGBE_RSS_OFFLOAD_ALL) == 0) {
3460                 ixgbe_rss_disable(dev);
3461                 return;
3462         }
3463         if (rss_conf.rss_key == NULL)
3464                 rss_conf.rss_key = rss_intel_key; /* Default hash key */
3465         ixgbe_hw_rss_hash_set(hw, &rss_conf);
3466 }
3467
3468 #define NUM_VFTA_REGISTERS 128
3469 #define NIC_RX_BUFFER_SIZE 0x200
3470 #define X550_RX_BUFFER_SIZE 0x180
3471
3472 static void
3473 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
3474 {
3475         struct rte_eth_vmdq_dcb_conf *cfg;
3476         struct ixgbe_hw *hw;
3477         enum rte_eth_nb_pools num_pools;
3478         uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
3479         uint16_t pbsize;
3480         uint8_t nb_tcs; /* number of traffic classes */
3481         int i;
3482
3483         PMD_INIT_FUNC_TRACE();
3484         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3485         cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
3486         num_pools = cfg->nb_queue_pools;
3487         /* Check we have a valid number of pools */
3488         if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
3489                 ixgbe_rss_disable(dev);
3490                 return;
3491         }
3492         /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
3493         nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
3494
3495         /*
3496          * RXPBSIZE
3497          * split rx buffer up into sections, each for 1 traffic class
3498          */
3499         switch (hw->mac.type) {
3500         case ixgbe_mac_X550:
3501         case ixgbe_mac_X550EM_x:
3502         case ixgbe_mac_X550EM_a:
3503                 pbsize = (uint16_t)(X550_RX_BUFFER_SIZE / nb_tcs);
3504                 break;
3505         default:
3506                 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
3507                 break;
3508         }
3509         for (i = 0; i < nb_tcs; i++) {
3510                 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
3511
3512                 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
3513                 /* clear 10 bits. */
3514                 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
3515                 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
3516         }
3517         /* zero alloc all unused TCs */
3518         for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3519                 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
3520
3521                 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
3522                 /* clear 10 bits. */
3523                 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
3524         }
3525
3526         /* MRQC: enable vmdq and dcb */
3527         mrqc = (num_pools == ETH_16_POOLS) ?
3528                 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN;
3529         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3530
3531         /* PFVTCTL: turn on virtualisation and set the default pool */
3532         vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3533         if (cfg->enable_default_pool) {
3534                 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3535         } else {
3536                 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3537         }
3538
3539         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3540
3541         /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
3542         queue_mapping = 0;
3543         for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
3544                 /*
3545                  * mapping is done with 3 bits per priority,
3546                  * so shift by i*3 each time
3547                  */
3548                 queue_mapping |= ((cfg->dcb_tc[i] & 0x07) << (i * 3));
3549
3550         IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
3551
3552         /* RTRPCS: DCB related */
3553         IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
3554
3555         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3556         vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3557         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
3558         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3559
3560         /* VFTA - enable all vlan filters */
3561         for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
3562                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
3563         }
3564
3565         /* VFRE: pool enabling for receive - 16 or 32 */
3566         IXGBE_WRITE_REG(hw, IXGBE_VFRE(0),
3567                         num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
3568
3569         /*
3570          * MPSAR - allow pools to read specific mac addresses
3571          * In this case, all pools should be able to read from mac addr 0
3572          */
3573         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
3574         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
3575
3576         /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3577         for (i = 0; i < cfg->nb_pool_maps; i++) {
3578                 /* set vlan id in VF register and set the valid bit */
3579                 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN |
3580                                 (cfg->pool_map[i].vlan_id & 0xFFF)));
3581                 /*
3582                  * Put the allowed pools in VFB reg. As we only have 16 or 32
3583                  * pools, we only need to use the first half of the register
3584                  * i.e. bits 0-31
3585                  */
3586                 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
3587         }
3588 }
3589
3590 /**
3591  * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
3592  * @dev: pointer to eth_dev structure
3593  * @dcb_config: pointer to ixgbe_dcb_config structure
3594  */
3595 static void
3596 ixgbe_dcb_tx_hw_config(struct rte_eth_dev *dev,
3597                        struct ixgbe_dcb_config *dcb_config)
3598 {
3599         uint32_t reg;
3600         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3601
3602         PMD_INIT_FUNC_TRACE();
3603         if (hw->mac.type != ixgbe_mac_82598EB) {
3604                 /* Disable the Tx desc arbiter so that MTQC can be changed */
3605                 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3606                 reg |= IXGBE_RTTDCS_ARBDIS;
3607                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3608
3609                 /* Enable DCB for Tx with 8 TCs */
3610                 if (dcb_config->num_tcs.pg_tcs == 8) {
3611                         reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3612                 } else {
3613                         reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3614                 }
3615                 if (dcb_config->vt_mode)
3616                         reg |= IXGBE_MTQC_VT_ENA;
3617                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3618
3619                 /* Enable the Tx desc arbiter */
3620                 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3621                 reg &= ~IXGBE_RTTDCS_ARBDIS;
3622                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3623
3624                 /* Enable Security TX Buffer IFG for DCB */
3625                 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3626                 reg |= IXGBE_SECTX_DCB;
3627                 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
3628         }
3629 }
3630
3631 /**
3632  * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
3633  * @dev: pointer to rte_eth_dev structure
3634  * @dcb_config: pointer to ixgbe_dcb_config structure
3635  */
3636 static void
3637 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
3638                         struct ixgbe_dcb_config *dcb_config)
3639 {
3640         struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
3641                         &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
3642         struct ixgbe_hw *hw =
3643                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3644
3645         PMD_INIT_FUNC_TRACE();
3646         if (hw->mac.type != ixgbe_mac_82598EB)
3647                 /*PF VF Transmit Enable*/
3648                 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
3649                         vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
3650
3651         /*Configure general DCB TX parameters*/
3652         ixgbe_dcb_tx_hw_config(dev, dcb_config);
3653 }
3654
3655 static void
3656 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
3657                         struct ixgbe_dcb_config *dcb_config)
3658 {
3659         struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
3660                         &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
3661         struct ixgbe_dcb_tc_config *tc;
3662         uint8_t i, j;
3663
3664         /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
3665         if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS) {
3666                 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
3667                 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
3668         } else {
3669                 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
3670                 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
3671         }
3672
3673         /* Initialize User Priority to Traffic Class mapping */
3674         for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {
3675                 tc = &dcb_config->tc_config[j];
3676                 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0;
3677         }
3678
3679         /* User Priority to Traffic Class mapping */
3680         for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3681                 j = vmdq_rx_conf->dcb_tc[i];
3682                 tc = &dcb_config->tc_config[j];
3683                 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap |=
3684                                                 (uint8_t)(1 << i);
3685         }
3686 }
3687
3688 static void
3689 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
3690                         struct ixgbe_dcb_config *dcb_config)
3691 {
3692         struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
3693                         &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
3694         struct ixgbe_dcb_tc_config *tc;
3695         uint8_t i, j;
3696
3697         /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
3698         if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS) {
3699                 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
3700                 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
3701         } else {
3702                 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
3703                 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
3704         }
3705
3706         /* Initialize User Priority to Traffic Class mapping */
3707         for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {
3708                 tc = &dcb_config->tc_config[j];
3709                 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0;
3710         }
3711
3712         /* User Priority to Traffic Class mapping */
3713         for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3714                 j = vmdq_tx_conf->dcb_tc[i];
3715                 tc = &dcb_config->tc_config[j];
3716                 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap |=
3717                                                 (uint8_t)(1 << i);
3718         }
3719 }
3720
3721 static void
3722 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,
3723                 struct ixgbe_dcb_config *dcb_config)
3724 {
3725         struct rte_eth_dcb_rx_conf *rx_conf =
3726                         &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
3727         struct ixgbe_dcb_tc_config *tc;
3728         uint8_t i, j;
3729
3730         dcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;
3731         dcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;
3732
3733         /* Initialize User Priority to Traffic Class mapping */
3734         for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {
3735                 tc = &dcb_config->tc_config[j];
3736                 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0;
3737         }
3738
3739         /* User Priority to Traffic Class mapping */
3740         for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3741                 j = rx_conf->dcb_tc[i];
3742                 tc = &dcb_config->tc_config[j];
3743                 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap |=
3744                                                 (uint8_t)(1 << i);
3745         }
3746 }
3747
3748 static void
3749 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,
3750                 struct ixgbe_dcb_config *dcb_config)
3751 {
3752         struct rte_eth_dcb_tx_conf *tx_conf =
3753                         &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
3754         struct ixgbe_dcb_tc_config *tc;
3755         uint8_t i, j;
3756
3757         dcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;
3758         dcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;
3759
3760         /* Initialize User Priority to Traffic Class mapping */
3761         for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {
3762                 tc = &dcb_config->tc_config[j];
3763                 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0;
3764         }
3765
3766         /* User Priority to Traffic Class mapping */
3767         for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3768                 j = tx_conf->dcb_tc[i];
3769                 tc = &dcb_config->tc_config[j];
3770                 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap |=
3771                                                 (uint8_t)(1 << i);
3772         }
3773 }
3774
3775 /**
3776  * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
3777  * @dev: pointer to eth_dev structure
3778  * @dcb_config: pointer to ixgbe_dcb_config structure
3779  */
3780 static void
3781 ixgbe_dcb_rx_hw_config(struct rte_eth_dev *dev,
3782                        struct ixgbe_dcb_config *dcb_config)
3783 {
3784         uint32_t reg;
3785         uint32_t vlanctrl;
3786         uint8_t i;
3787         uint32_t q;
3788         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3789
3790         PMD_INIT_FUNC_TRACE();
3791         /*
3792          * Disable the arbiter before changing parameters
3793          * (always enable recycle mode; WSP)
3794          */
3795         reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
3796         IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
3797
3798         if (hw->mac.type != ixgbe_mac_82598EB) {
3799                 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
3800                 if (dcb_config->num_tcs.pg_tcs == 4) {
3801                         if (dcb_config->vt_mode)
3802                                 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3803                                         IXGBE_MRQC_VMDQRT4TCEN;
3804                         else {
3805                                 /* no matter the mode is DCB or DCB_RSS, just
3806                                  * set the MRQE to RSSXTCEN. RSS is controlled
3807                                  * by RSS_FIELD
3808                                  */
3809                                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
3810                                 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3811                                         IXGBE_MRQC_RTRSS4TCEN;
3812                         }
3813                 }
3814                 if (dcb_config->num_tcs.pg_tcs == 8) {
3815                         if (dcb_config->vt_mode)
3816                                 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3817                                         IXGBE_MRQC_VMDQRT8TCEN;
3818                         else {
3819                                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
3820                                 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3821                                         IXGBE_MRQC_RTRSS8TCEN;
3822                         }
3823                 }
3824
3825                 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
3826
3827                 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3828                         /* Disable drop for all queues in VMDQ mode*/
3829                         for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3830                                 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3831                                                 (IXGBE_QDE_WRITE |
3832                                                  (q << IXGBE_QDE_IDX_SHIFT)));
3833                 } else {
3834                         /* Enable drop for all queues in SRIOV mode */
3835                         for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3836                                 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3837                                                 (IXGBE_QDE_WRITE |
3838                                                  (q << IXGBE_QDE_IDX_SHIFT) |
3839                                                  IXGBE_QDE_ENABLE));
3840                 }
3841         }
3842
3843         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3844         vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3845         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
3846         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3847
3848         /* VFTA - enable all vlan filters */
3849         for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
3850                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
3851         }
3852
3853         /*
3854          * Configure Rx packet plane (recycle mode; WSP) and
3855          * enable arbiter
3856          */
3857         reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
3858         IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
3859 }
3860
3861 static void
3862 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
3863                         uint16_t *max, uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
3864 {
3865         switch (hw->mac.type) {
3866         case ixgbe_mac_82598EB:
3867                 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
3868                 break;
3869         case ixgbe_mac_82599EB:
3870         case ixgbe_mac_X540:
3871         case ixgbe_mac_X550:
3872         case ixgbe_mac_X550EM_x:
3873         case ixgbe_mac_X550EM_a:
3874                 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
3875                                                   tsa, map);
3876                 break;
3877         default:
3878                 break;
3879         }
3880 }
3881
3882 static void
3883 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
3884                             uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
3885 {
3886         switch (hw->mac.type) {
3887         case ixgbe_mac_82598EB:
3888                 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id, tsa);
3889                 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id, tsa);
3890                 break;
3891         case ixgbe_mac_82599EB:
3892         case ixgbe_mac_X540:
3893         case ixgbe_mac_X550:
3894         case ixgbe_mac_X550EM_x:
3895         case ixgbe_mac_X550EM_a:
3896                 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id, tsa);
3897                 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id, tsa, map);
3898                 break;
3899         default:
3900                 break;
3901         }
3902 }
3903
3904 #define DCB_RX_CONFIG  1
3905 #define DCB_TX_CONFIG  1
3906 #define DCB_TX_PB      1024
3907 /**
3908  * ixgbe_dcb_hw_configure - Enable DCB and configure
3909  * general DCB in VT mode and non-VT mode parameters
3910  * @dev: pointer to rte_eth_dev structure
3911  * @dcb_config: pointer to ixgbe_dcb_config structure
3912  */
3913 static int
3914 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
3915                         struct ixgbe_dcb_config *dcb_config)
3916 {
3917         int     ret = 0;
3918         uint8_t i, pfc_en, nb_tcs;
3919         uint16_t pbsize, rx_buffer_size;
3920         uint8_t config_dcb_rx = 0;
3921         uint8_t config_dcb_tx = 0;
3922         uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3923         uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3924         uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3925         uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3926         uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3927         struct ixgbe_dcb_tc_config *tc;
3928         uint32_t max_frame = dev->data->mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3929         struct ixgbe_hw *hw =
3930                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3931         struct ixgbe_bw_conf *bw_conf =
3932                 IXGBE_DEV_PRIVATE_TO_BW_CONF(dev->data->dev_private);
3933
3934         switch (dev->data->dev_conf.rxmode.mq_mode) {
3935         case ETH_MQ_RX_VMDQ_DCB:
3936                 dcb_config->vt_mode = true;
3937                 if (hw->mac.type != ixgbe_mac_82598EB) {
3938                         config_dcb_rx = DCB_RX_CONFIG;
3939                         /*
3940                          *get dcb and VT rx configuration parameters
3941                          *from rte_eth_conf
3942                          */
3943                         ixgbe_vmdq_dcb_rx_config(dev, dcb_config);
3944                         /*Configure general VMDQ and DCB RX parameters*/
3945                         ixgbe_vmdq_dcb_configure(dev);
3946                 }
3947                 break;
3948         case ETH_MQ_RX_DCB:
3949         case ETH_MQ_RX_DCB_RSS:
3950                 dcb_config->vt_mode = false;
3951                 config_dcb_rx = DCB_RX_CONFIG;
3952                 /* Get dcb TX configuration parameters from rte_eth_conf */
3953                 ixgbe_dcb_rx_config(dev, dcb_config);
3954                 /*Configure general DCB RX parameters*/
3955                 ixgbe_dcb_rx_hw_config(dev, dcb_config);
3956                 break;
3957         default:
3958                 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration");
3959                 break;
3960         }
3961         switch (dev->data->dev_conf.txmode.mq_mode) {
3962         case ETH_MQ_TX_VMDQ_DCB:
3963                 dcb_config->vt_mode = true;
3964                 config_dcb_tx = DCB_TX_CONFIG;
3965                 /* get DCB and VT TX configuration parameters
3966                  * from rte_eth_conf
3967                  */
3968                 ixgbe_dcb_vt_tx_config(dev, dcb_config);
3969                 /*Configure general VMDQ and DCB TX parameters*/
3970                 ixgbe_vmdq_dcb_hw_tx_config(dev, dcb_config);
3971                 break;
3972
3973         case ETH_MQ_TX_DCB:
3974                 dcb_config->vt_mode = false;
3975                 config_dcb_tx = DCB_TX_CONFIG;
3976                 /*get DCB TX configuration parameters from rte_eth_conf*/
3977                 ixgbe_dcb_tx_config(dev, dcb_config);
3978                 /*Configure general DCB TX parameters*/
3979                 ixgbe_dcb_tx_hw_config(dev, dcb_config);
3980                 break;
3981         default:
3982                 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration");
3983                 break;
3984         }
3985
3986         nb_tcs = dcb_config->num_tcs.pfc_tcs;
3987         /* Unpack map */
3988         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3989         if (nb_tcs == ETH_4_TCS) {
3990                 /* Avoid un-configured priority mapping to TC0 */
3991                 uint8_t j = 4;
3992                 uint8_t mask = 0xFF;
3993
3994                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
3995                         mask = (uint8_t)(mask & (~(1 << map[i])));
3996                 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
3997                         if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
3998                                 map[j++] = i;
3999                         mask >>= 1;
4000                 }
4001                 /* Re-configure 4 TCs BW */
4002                 for (i = 0; i < nb_tcs; i++) {
4003                         tc = &dcb_config->tc_config[i];
4004                         if (bw_conf->tc_num != nb_tcs)
4005                                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
4006                                         (uint8_t)(100 / nb_tcs);
4007                         tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
4008                                                 (uint8_t)(100 / nb_tcs);
4009                 }
4010                 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4011                         tc = &dcb_config->tc_config[i];
4012                         tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
4013                         tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
4014                 }
4015         } else {
4016                 /* Re-configure 8 TCs BW */
4017                 for (i = 0; i < nb_tcs; i++) {
4018                         tc = &dcb_config->tc_config[i];
4019                         if (bw_conf->tc_num != nb_tcs)
4020                                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
4021                                         (uint8_t)(100 / nb_tcs + (i & 1));
4022                         tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
4023                                 (uint8_t)(100 / nb_tcs + (i & 1));
4024                 }
4025         }
4026
4027         switch (hw->mac.type) {
4028         case ixgbe_mac_X550:
4029         case ixgbe_mac_X550EM_x:
4030         case ixgbe_mac_X550EM_a:
4031                 rx_buffer_size = X550_RX_BUFFER_SIZE;
4032                 break;
4033         default:
4034                 rx_buffer_size = NIC_RX_BUFFER_SIZE;
4035                 break;
4036         }
4037
4038         if (config_dcb_rx) {
4039                 /* Set RX buffer size */
4040                 pbsize = (uint16_t)(rx_buffer_size / nb_tcs);
4041                 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
4042
4043                 for (i = 0; i < nb_tcs; i++) {
4044                         IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
4045                 }
4046                 /* zero alloc all unused TCs */
4047                 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
4048                         IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4049                 }
4050         }
4051         if (config_dcb_tx) {
4052                 /* Only support an equally distributed
4053                  *  Tx packet buffer strategy.
4054                  */
4055                 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
4056                 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
4057
4058                 for (i = 0; i < nb_tcs; i++) {
4059                         IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4060                         IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4061                 }
4062                 /* Clear unused TCs, if any, to zero buffer size*/
4063                 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
4064                         IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4065                         IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4066                 }
4067         }
4068
4069         /*Calculates traffic class credits*/
4070         ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config, max_frame,
4071                                 IXGBE_DCB_TX_CONFIG);
4072         ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config, max_frame,
4073                                 IXGBE_DCB_RX_CONFIG);
4074
4075         if (config_dcb_rx) {
4076                 /* Unpack CEE standard containers */
4077                 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
4078                 ixgbe_dcb_unpack_max_cee(dcb_config, max);
4079                 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
4080                 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
4081                 /* Configure PG(ETS) RX */
4082                 ixgbe_dcb_hw_arbite_rx_config(hw, refill, max, bwgid, tsa, map);
4083         }
4084
4085         if (config_dcb_tx) {
4086                 /* Unpack CEE standard containers */
4087                 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
4088                 ixgbe_dcb_unpack_max_cee(dcb_config, max);
4089                 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
4090                 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
4091                 /* Configure PG(ETS) TX */
4092                 ixgbe_dcb_hw_arbite_tx_config(hw, refill, max, bwgid, tsa, map);
4093         }
4094
4095         /*Configure queue statistics registers*/
4096         ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
4097
4098         /* Check if the PFC is supported */
4099         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
4100                 pbsize = (uint16_t)(rx_buffer_size / nb_tcs);
4101                 for (i = 0; i < nb_tcs; i++) {
4102                         /*
4103                         * If the TC count is 8,and the default high_water is 48,
4104                         * the low_water is 16 as default.
4105                         */
4106                         hw->fc.high_water[i] = (pbsize * 3) / 4;
4107                         hw->fc.low_water[i] = pbsize / 4;
4108                         /* Enable pfc for this TC */
4109                         tc = &dcb_config->tc_config[i];
4110                         tc->pfc = ixgbe_dcb_pfc_enabled;
4111                 }
4112                 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
4113                 if (dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
4114                         pfc_en &= 0x0F;
4115                 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
4116         }
4117
4118         return ret;
4119 }
4120
4121 /**
4122  * ixgbe_configure_dcb - Configure DCB  Hardware
4123  * @dev: pointer to rte_eth_dev
4124  */
4125 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
4126 {
4127         struct ixgbe_dcb_config *dcb_cfg =
4128                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4129         struct rte_eth_conf *dev_conf = &(dev->data->dev_conf);
4130
4131         PMD_INIT_FUNC_TRACE();
4132
4133         /* check support mq_mode for DCB */
4134         if ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) &&
4135             (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB) &&
4136             (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB_RSS))
4137                 return;
4138
4139         if (dev->data->nb_rx_queues > ETH_DCB_NUM_QUEUES)
4140                 return;
4141
4142         /** Configure DCB hardware **/
4143         ixgbe_dcb_hw_configure(dev, dcb_cfg);
4144 }
4145
4146 /*
4147  * VMDq only support for 10 GbE NIC.
4148  */
4149 static void
4150 ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
4151 {
4152         struct rte_eth_vmdq_rx_conf *cfg;
4153         struct ixgbe_hw *hw;
4154         enum rte_eth_nb_pools num_pools;
4155         uint32_t mrqc, vt_ctl, vlanctrl;
4156         uint32_t vmolr = 0;
4157         int i;
4158
4159         PMD_INIT_FUNC_TRACE();
4160         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4161         cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
4162         num_pools = cfg->nb_queue_pools;
4163
4164         ixgbe_rss_disable(dev);
4165
4166         /* MRQC: enable vmdq */
4167         mrqc = IXGBE_MRQC_VMDQEN;
4168         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
4169
4170         /* PFVTCTL: turn on virtualisation and set the default pool */
4171         vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
4172         if (cfg->enable_default_pool)
4173                 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
4174         else
4175                 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
4176
4177         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
4178
4179         for (i = 0; i < (int)num_pools; i++) {
4180                 vmolr = ixgbe_convert_vm_rx_mask_to_val(cfg->rx_mode, vmolr);
4181                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(i), vmolr);
4182         }
4183
4184         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
4185         vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4186         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
4187         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
4188
4189         /* VFTA - enable all vlan filters */
4190         for (i = 0; i < NUM_VFTA_REGISTERS; i++)
4191                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), UINT32_MAX);
4192
4193         /* VFRE: pool enabling for receive - 64 */
4194         IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), UINT32_MAX);
4195         if (num_pools == ETH_64_POOLS)
4196                 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), UINT32_MAX);
4197
4198         /*
4199          * MPSAR - allow pools to read specific mac addresses
4200          * In this case, all pools should be able to read from mac addr 0
4201          */
4202         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), UINT32_MAX);
4203         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), UINT32_MAX);
4204
4205         /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
4206         for (i = 0; i < cfg->nb_pool_maps; i++) {
4207                 /* set vlan id in VF register and set the valid bit */
4208                 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN |
4209                                 (cfg->pool_map[i].vlan_id & IXGBE_RXD_VLAN_ID_MASK)));
4210                 /*
4211                  * Put the allowed pools in VFB reg. As we only have 16 or 64
4212                  * pools, we only need to use the first half of the register
4213                  * i.e. bits 0-31
4214                  */
4215                 if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
4216                         IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i * 2),
4217                                         (cfg->pool_map[i].pools & UINT32_MAX));
4218                 else
4219                         IXGBE_WRITE_REG(hw, IXGBE_VLVFB((i * 2 + 1)),
4220                                         ((cfg->pool_map[i].pools >> 32) & UINT32_MAX));
4221
4222         }
4223
4224         /* PFDMA Tx General Switch Control Enables VMDQ loopback */
4225         if (cfg->enable_loop_back) {
4226                 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
4227                 for (i = 0; i < RTE_IXGBE_VMTXSW_REGISTER_COUNT; i++)
4228                         IXGBE_WRITE_REG(hw, IXGBE_VMTXSW(i), UINT32_MAX);
4229         }
4230
4231         IXGBE_WRITE_FLUSH(hw);
4232 }
4233
4234 /*
4235  * ixgbe_dcb_config_tx_hw_config - Configure general VMDq TX parameters
4236  * @hw: pointer to hardware structure
4237  */
4238 static void
4239 ixgbe_vmdq_tx_hw_configure(struct ixgbe_hw *hw)
4240 {
4241         uint32_t reg;
4242         uint32_t q;
4243
4244         PMD_INIT_FUNC_TRACE();
4245         /*PF VF Transmit Enable*/
4246         IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), UINT32_MAX);
4247         IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), UINT32_MAX);
4248
4249         /* Disable the Tx desc arbiter so that MTQC can be changed */
4250         reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
4251         reg |= IXGBE_RTTDCS_ARBDIS;
4252         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
4253
4254         reg = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
4255         IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
4256
4257         /* Disable drop for all queues */
4258         for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
4259                 IXGBE_WRITE_REG(hw, IXGBE_QDE,
4260                   (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
4261
4262         /* Enable the Tx desc arbiter */
4263         reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
4264         reg &= ~IXGBE_RTTDCS_ARBDIS;
4265         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
4266
4267         IXGBE_WRITE_FLUSH(hw);
4268 }
4269
4270 static int __attribute__((cold))
4271 ixgbe_alloc_rx_queue_mbufs(struct ixgbe_rx_queue *rxq)
4272 {
4273         struct ixgbe_rx_entry *rxe = rxq->sw_ring;
4274         uint64_t dma_addr;
4275         unsigned int i;
4276
4277         /* Initialize software ring entries */
4278         for (i = 0; i < rxq->nb_rx_desc; i++) {
4279                 volatile union ixgbe_adv_rx_desc *rxd;
4280                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
4281
4282                 if (mbuf == NULL) {
4283                         PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
4284                                      (unsigned) rxq->queue_id);
4285                         return -ENOMEM;
4286                 }
4287
4288                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
4289                 mbuf->port = rxq->port_id;
4290
4291                 dma_addr =
4292                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
4293                 rxd = &rxq->rx_ring[i];
4294                 rxd->read.hdr_addr = 0;
4295                 rxd->read.pkt_addr = dma_addr;
4296                 rxe[i].mbuf = mbuf;
4297         }
4298
4299         return 0;
4300 }
4301
4302 static int
4303 ixgbe_config_vf_rss(struct rte_eth_dev *dev)
4304 {
4305         struct ixgbe_hw *hw;
4306         uint32_t mrqc;
4307
4308         ixgbe_rss_configure(dev);
4309
4310         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4311
4312         /* MRQC: enable VF RSS */
4313         mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
4314         mrqc &= ~IXGBE_MRQC_MRQE_MASK;
4315         switch (RTE_ETH_DEV_SRIOV(dev).active) {
4316         case ETH_64_POOLS:
4317                 mrqc |= IXGBE_MRQC_VMDQRSS64EN;
4318                 break;
4319
4320         case ETH_32_POOLS:
4321                 mrqc |= IXGBE_MRQC_VMDQRSS32EN;
4322                 break;
4323
4324         default:
4325                 PMD_INIT_LOG(ERR, "Invalid pool number in IOV mode with VMDQ RSS");
4326                 return -EINVAL;
4327         }
4328
4329         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
4330
4331         return 0;
4332 }
4333
4334 static int
4335 ixgbe_config_vf_default(struct rte_eth_dev *dev)
4336 {
4337         struct ixgbe_hw *hw =
4338                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4339
4340         switch (RTE_ETH_DEV_SRIOV(dev).active) {
4341         case ETH_64_POOLS:
4342                 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
4343                         IXGBE_MRQC_VMDQEN);
4344                 break;
4345
4346         case ETH_32_POOLS:
4347                 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
4348                         IXGBE_MRQC_VMDQRT4TCEN);
4349                 break;
4350
4351         case ETH_16_POOLS:
4352                 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
4353                         IXGBE_MRQC_VMDQRT8TCEN);
4354                 break;
4355         default:
4356                 PMD_INIT_LOG(ERR,
4357                         "invalid pool number in IOV mode");
4358                 break;
4359         }
4360         return 0;
4361 }
4362
4363 static int
4364 ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
4365 {
4366         struct ixgbe_hw *hw =
4367                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4368
4369         if (hw->mac.type == ixgbe_mac_82598EB)
4370                 return 0;
4371
4372         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
4373                 /*
4374                  * SRIOV inactive scheme
4375                  * any DCB/RSS w/o VMDq multi-queue setting
4376                  */
4377                 switch (dev->data->dev_conf.rxmode.mq_mode) {
4378                 case ETH_MQ_RX_RSS:
4379                 case ETH_MQ_RX_DCB_RSS:
4380                 case ETH_MQ_RX_VMDQ_RSS:
4381                         ixgbe_rss_configure(dev);
4382                         break;
4383
4384                 case ETH_MQ_RX_VMDQ_DCB:
4385                         ixgbe_vmdq_dcb_configure(dev);
4386                         break;
4387
4388                 case ETH_MQ_RX_VMDQ_ONLY:
4389                         ixgbe_vmdq_rx_hw_configure(dev);
4390                         break;
4391
4392                 case ETH_MQ_RX_NONE:
4393                 default:
4394                         /* if mq_mode is none, disable rss mode.*/
4395                         ixgbe_rss_disable(dev);
4396                         break;
4397                 }
4398         } else {
4399                 /* SRIOV active scheme
4400                  * Support RSS together with SRIOV.
4401                  */
4402                 switch (dev->data->dev_conf.rxmode.mq_mode) {
4403                 case ETH_MQ_RX_RSS:
4404                 case ETH_MQ_RX_VMDQ_RSS:
4405                         ixgbe_config_vf_rss(dev);
4406                         break;
4407                 case ETH_MQ_RX_VMDQ_DCB:
4408                 case ETH_MQ_RX_DCB:
4409                 /* In SRIOV, the configuration is the same as VMDq case */
4410                         ixgbe_vmdq_dcb_configure(dev);
4411                         break;
4412                 /* DCB/RSS together with SRIOV is not supported */
4413                 case ETH_MQ_RX_VMDQ_DCB_RSS:
4414                 case ETH_MQ_RX_DCB_RSS:
4415                         PMD_INIT_LOG(ERR,
4416                                 "Could not support DCB/RSS with VMDq & SRIOV");
4417                         return -1;
4418                 default:
4419                         ixgbe_config_vf_default(dev);
4420                         break;
4421                 }
4422         }
4423
4424         return 0;
4425 }
4426
4427 static int
4428 ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)
4429 {
4430         struct ixgbe_hw *hw =
4431                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4432         uint32_t mtqc;
4433         uint32_t rttdcs;
4434
4435         if (hw->mac.type == ixgbe_mac_82598EB)
4436                 return 0;
4437
4438         /* disable arbiter before setting MTQC */
4439         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
4440         rttdcs |= IXGBE_RTTDCS_ARBDIS;
4441         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
4442
4443         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
4444                 /*
4445                  * SRIOV inactive scheme
4446                  * any DCB w/o VMDq multi-queue setting
4447                  */
4448                 if (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)
4449                         ixgbe_vmdq_tx_hw_configure(hw);
4450                 else {
4451                         mtqc = IXGBE_MTQC_64Q_1PB;
4452                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
4453                 }
4454         } else {
4455                 switch (RTE_ETH_DEV_SRIOV(dev).active) {
4456
4457                 /*
4458                  * SRIOV active scheme
4459                  * FIXME if support DCB together with VMDq & SRIOV
4460                  */
4461                 case ETH_64_POOLS:
4462                         mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
4463                         break;
4464                 case ETH_32_POOLS:
4465                         mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;
4466                         break;
4467                 case ETH_16_POOLS:
4468                         mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |
4469                                 IXGBE_MTQC_8TC_8TQ;
4470                         break;
4471                 default:
4472                         mtqc = IXGBE_MTQC_64Q_1PB;
4473                         PMD_INIT_LOG(ERR, "invalid pool number in IOV mode");
4474                 }
4475                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
4476         }
4477
4478         /* re-enable arbiter */
4479         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
4480         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
4481
4482         return 0;
4483 }
4484
4485 /**
4486  * ixgbe_get_rscctl_maxdesc - Calculate the RSCCTL[n].MAXDESC for PF
4487  *
4488  * Return the RSCCTL[n].MAXDESC for 82599 and x540 PF devices according to the
4489  * spec rev. 3.0 chapter 8.2.3.8.13.
4490  *
4491  * @pool Memory pool of the Rx queue
4492  */
4493 static inline uint32_t
4494 ixgbe_get_rscctl_maxdesc(struct rte_mempool *pool)
4495 {
4496         struct rte_pktmbuf_pool_private *mp_priv = rte_mempool_get_priv(pool);
4497
4498         /* MAXDESC * SRRCTL.BSIZEPKT must not exceed 64 KB minus one */
4499         uint16_t maxdesc =
4500                 IPV4_MAX_PKT_LEN /
4501                         (mp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM);
4502
4503         if (maxdesc >= 16)
4504                 return IXGBE_RSCCTL_MAXDESC_16;
4505         else if (maxdesc >= 8)
4506                 return IXGBE_RSCCTL_MAXDESC_8;
4507         else if (maxdesc >= 4)
4508                 return IXGBE_RSCCTL_MAXDESC_4;
4509         else
4510                 return IXGBE_RSCCTL_MAXDESC_1;
4511 }
4512
4513 /**
4514  * ixgbe_set_ivar - Setup the correct IVAR register for a particular MSIX
4515  * interrupt
4516  *
4517  * (Taken from FreeBSD tree)
4518  * (yes this is all very magic and confusing :)
4519  *
4520  * @dev port handle
4521  * @entry the register array entry
4522  * @vector the MSIX vector for this queue
4523  * @type RX/TX/MISC
4524  */
4525 static void
4526 ixgbe_set_ivar(struct rte_eth_dev *dev, u8 entry, u8 vector, s8 type)
4527 {
4528         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4529         u32 ivar, index;
4530
4531         vector |= IXGBE_IVAR_ALLOC_VAL;
4532
4533         switch (hw->mac.type) {
4534
4535         case ixgbe_mac_82598EB:
4536                 if (type == -1)
4537                         entry = IXGBE_IVAR_OTHER_CAUSES_INDEX;
4538                 else
4539                         entry += (type * 64);
4540                 index = (entry >> 2) & 0x1F;
4541                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
4542                 ivar &= ~(0xFF << (8 * (entry & 0x3)));
4543                 ivar |= (vector << (8 * (entry & 0x3)));
4544                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
4545                 break;
4546
4547         case ixgbe_mac_82599EB:
4548         case ixgbe_mac_X540:
4549                 if (type == -1) { /* MISC IVAR */
4550                         index = (entry & 1) * 8;
4551                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4552                         ivar &= ~(0xFF << index);
4553                         ivar |= (vector << index);
4554                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, ivar);
4555                 } else {        /* RX/TX IVARS */
4556                         index = (16 * (entry & 1)) + (8 * type);
4557                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(entry >> 1));
4558                         ivar &= ~(0xFF << index);
4559                         ivar |= (vector << index);
4560                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(entry >> 1), ivar);
4561                 }
4562
4563                 break;
4564
4565         default:
4566                 break;
4567         }
4568 }
4569
4570 void __attribute__((cold))
4571 ixgbe_set_rx_function(struct rte_eth_dev *dev)
4572 {
4573         uint16_t i, rx_using_sse;
4574         struct ixgbe_adapter *adapter =
4575                 (struct ixgbe_adapter *)dev->data->dev_private;
4576
4577         /*
4578          * In order to allow Vector Rx there are a few configuration
4579          * conditions to be met and Rx Bulk Allocation should be allowed.
4580          */
4581         if (ixgbe_rx_vec_dev_conf_condition_check(dev) ||
4582             !adapter->rx_bulk_alloc_allowed) {
4583                 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet Vector Rx "
4584                                     "preconditions or RTE_IXGBE_INC_VECTOR is "
4585                                     "not enabled",
4586                              dev->data->port_id);
4587
4588                 adapter->rx_vec_allowed = false;
4589         }
4590
4591         /*
4592          * Initialize the appropriate LRO callback.
4593          *
4594          * If all queues satisfy the bulk allocation preconditions
4595          * (hw->rx_bulk_alloc_allowed is TRUE) then we may use bulk allocation.
4596          * Otherwise use a single allocation version.
4597          */
4598         if (dev->data->lro) {
4599                 if (adapter->rx_bulk_alloc_allowed) {
4600                         PMD_INIT_LOG(DEBUG, "LRO is requested. Using a bulk "
4601                                            "allocation version");
4602                         dev->rx_pkt_burst = ixgbe_recv_pkts_lro_bulk_alloc;
4603                 } else {
4604                         PMD_INIT_LOG(DEBUG, "LRO is requested. Using a single "
4605                                            "allocation version");
4606                         dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
4607                 }
4608         } else if (dev->data->scattered_rx) {
4609                 /*
4610                  * Set the non-LRO scattered callback: there are Vector and
4611                  * single allocation versions.
4612                  */
4613                 if (adapter->rx_vec_allowed) {
4614                         PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
4615                                             "callback (port=%d).",
4616                                      dev->data->port_id);
4617
4618                         dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
4619                 } else if (adapter->rx_bulk_alloc_allowed) {
4620                         PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
4621                                            "allocation callback (port=%d).",
4622                                      dev->data->port_id);
4623                         dev->rx_pkt_burst = ixgbe_recv_pkts_lro_bulk_alloc;
4624                 } else {
4625                         PMD_INIT_LOG(DEBUG, "Using Regualr (non-vector, "
4626                                             "single allocation) "
4627                                             "Scattered Rx callback "
4628                                             "(port=%d).",
4629                                      dev->data->port_id);
4630
4631                         dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
4632                 }
4633         /*
4634          * Below we set "simple" callbacks according to port/queues parameters.
4635          * If parameters allow we are going to choose between the following
4636          * callbacks:
4637          *    - Vector
4638          *    - Bulk Allocation
4639          *    - Single buffer allocation (the simplest one)
4640          */
4641         } else if (adapter->rx_vec_allowed) {
4642                 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
4643                                     "burst size no less than %d (port=%d).",
4644                              RTE_IXGBE_DESCS_PER_LOOP,
4645                              dev->data->port_id);
4646
4647                 dev->rx_pkt_burst = ixgbe_recv_pkts_vec;
4648         } else if (adapter->rx_bulk_alloc_allowed) {
4649                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
4650                                     "satisfied. Rx Burst Bulk Alloc function "
4651                                     "will be used on port=%d.",
4652                              dev->data->port_id);
4653
4654                 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
4655         } else {
4656                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
4657                                     "satisfied, or Scattered Rx is requested "
4658                                     "(port=%d).",
4659                              dev->data->port_id);
4660
4661                 dev->rx_pkt_burst = ixgbe_recv_pkts;
4662         }
4663
4664         /* Propagate information about RX function choice through all queues. */
4665
4666         rx_using_sse =
4667                 (dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec ||
4668                 dev->rx_pkt_burst == ixgbe_recv_pkts_vec);
4669
4670         for (i = 0; i < dev->data->nb_rx_queues; i++) {
4671                 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
4672
4673                 rxq->rx_using_sse = rx_using_sse;
4674 #ifdef RTE_LIBRTE_SECURITY
4675                 rxq->using_ipsec = !!(dev->data->dev_conf.rxmode.offloads &
4676                                 DEV_RX_OFFLOAD_SECURITY);
4677 #endif
4678         }
4679 }
4680
4681 /**
4682  * ixgbe_set_rsc - configure RSC related port HW registers
4683  *
4684  * Configures the port's RSC related registers according to the 4.6.7.2 chapter
4685  * of 82599 Spec (x540 configuration is virtually the same).
4686  *
4687  * @dev port handle
4688  *
4689  * Returns 0 in case of success or a non-zero error code
4690  */
4691 static int
4692 ixgbe_set_rsc(struct rte_eth_dev *dev)
4693 {
4694         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
4695         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4696         struct rte_eth_dev_info dev_info = { 0 };
4697         bool rsc_capable = false;
4698         uint16_t i;
4699         uint32_t rdrxctl;
4700         uint32_t rfctl;
4701
4702         /* Sanity check */
4703         dev->dev_ops->dev_infos_get(dev, &dev_info);
4704         if (dev_info.rx_offload_capa & DEV_RX_OFFLOAD_TCP_LRO)
4705                 rsc_capable = true;
4706
4707         if (!rsc_capable && (rx_conf->offloads & DEV_RX_OFFLOAD_TCP_LRO)) {
4708                 PMD_INIT_LOG(CRIT, "LRO is requested on HW that doesn't "
4709                                    "support it");
4710                 return -EINVAL;
4711         }
4712
4713         /* RSC global configuration (chapter 4.6.7.2.1 of 82599 Spec) */
4714
4715         if ((rx_conf->offloads & DEV_RX_OFFLOAD_KEEP_CRC) &&
4716              (rx_conf->offloads & DEV_RX_OFFLOAD_TCP_LRO)) {
4717                 /*
4718                  * According to chapter of 4.6.7.2.1 of the Spec Rev.
4719                  * 3.0 RSC configuration requires HW CRC stripping being
4720                  * enabled. If user requested both HW CRC stripping off
4721                  * and RSC on - return an error.
4722                  */
4723                 PMD_INIT_LOG(CRIT, "LRO can't be enabled when HW CRC "
4724                                     "is disabled");
4725                 return -EINVAL;
4726         }
4727
4728         /* RFCTL configuration  */
4729         rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
4730         if ((rsc_capable) && (rx_conf->offloads & DEV_RX_OFFLOAD_TCP_LRO))
4731                 /*
4732                  * Since NFS packets coalescing is not supported - clear
4733                  * RFCTL.NFSW_DIS and RFCTL.NFSR_DIS when RSC is
4734                  * enabled.
4735                  */
4736                 rfctl &= ~(IXGBE_RFCTL_RSC_DIS | IXGBE_RFCTL_NFSW_DIS |
4737                            IXGBE_RFCTL_NFSR_DIS);
4738         else
4739                 rfctl |= IXGBE_RFCTL_RSC_DIS;
4740         IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
4741
4742         /* If LRO hasn't been requested - we are done here. */
4743         if (!(rx_conf->offloads & DEV_RX_OFFLOAD_TCP_LRO))
4744                 return 0;
4745
4746         /* Set RDRXCTL.RSCACKC bit */
4747         rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4748         rdrxctl |= IXGBE_RDRXCTL_RSCACKC;
4749         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4750
4751         /* Per-queue RSC configuration (chapter 4.6.7.2.2 of 82599 Spec) */
4752         for (i = 0; i < dev->data->nb_rx_queues; i++) {
4753                 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
4754                 uint32_t srrctl =
4755                         IXGBE_READ_REG(hw, IXGBE_SRRCTL(rxq->reg_idx));
4756                 uint32_t rscctl =
4757                         IXGBE_READ_REG(hw, IXGBE_RSCCTL(rxq->reg_idx));
4758                 uint32_t psrtype =
4759                         IXGBE_READ_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx));
4760                 uint32_t eitr =
4761                         IXGBE_READ_REG(hw, IXGBE_EITR(rxq->reg_idx));
4762
4763                 /*
4764                  * ixgbe PMD doesn't support header-split at the moment.
4765                  *
4766                  * Following the 4.6.7.2.1 chapter of the 82599/x540
4767                  * Spec if RSC is enabled the SRRCTL[n].BSIZEHEADER
4768                  * should be configured even if header split is not
4769                  * enabled. We will configure it 128 bytes following the
4770                  * recommendation in the spec.
4771                  */
4772                 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
4773                 srrctl |= (128 << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4774                                             IXGBE_SRRCTL_BSIZEHDR_MASK;
4775
4776                 /*
4777                  * TODO: Consider setting the Receive Descriptor Minimum
4778                  * Threshold Size for an RSC case. This is not an obviously
4779                  * beneficiary option but the one worth considering...
4780                  */
4781
4782                 rscctl |= IXGBE_RSCCTL_RSCEN;
4783                 rscctl |= ixgbe_get_rscctl_maxdesc(rxq->mb_pool);
4784                 psrtype |= IXGBE_PSRTYPE_TCPHDR;
4785
4786                 /*
4787                  * RSC: Set ITR interval corresponding to 2K ints/s.
4788                  *
4789                  * Full-sized RSC aggregations for a 10Gb/s link will
4790                  * arrive at about 20K aggregation/s rate.
4791                  *
4792                  * 2K inst/s rate will make only 10% of the
4793                  * aggregations to be closed due to the interrupt timer
4794                  * expiration for a streaming at wire-speed case.
4795                  *
4796                  * For a sparse streaming case this setting will yield
4797                  * at most 500us latency for a single RSC aggregation.
4798                  */
4799                 eitr &= ~IXGBE_EITR_ITR_INT_MASK;
4800                 eitr |= IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT);
4801                 eitr |= IXGBE_EITR_CNT_WDIS;
4802
4803                 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
4804                 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(rxq->reg_idx), rscctl);
4805                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
4806                 IXGBE_WRITE_REG(hw, IXGBE_EITR(rxq->reg_idx), eitr);
4807
4808                 /*
4809                  * RSC requires the mapping of the queue to the
4810                  * interrupt vector.
4811                  */
4812                 ixgbe_set_ivar(dev, rxq->reg_idx, i, 0);
4813         }
4814
4815         dev->data->lro = 1;
4816
4817         PMD_INIT_LOG(DEBUG, "enabling LRO mode");
4818
4819         return 0;
4820 }
4821
4822 /*
4823  * Initializes Receive Unit.
4824  */
4825 int __attribute__((cold))
4826 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
4827 {
4828         struct ixgbe_hw     *hw;
4829         struct ixgbe_rx_queue *rxq;
4830         uint64_t bus_addr;
4831         uint32_t rxctrl;
4832         uint32_t fctrl;
4833         uint32_t hlreg0;
4834         uint32_t maxfrs;
4835         uint32_t srrctl;
4836         uint32_t rdrxctl;
4837         uint32_t rxcsum;
4838         uint16_t buf_size;
4839         uint16_t i;
4840         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
4841         int rc;
4842
4843         PMD_INIT_FUNC_TRACE();
4844         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4845
4846         /*
4847          * Make sure receives are disabled while setting
4848          * up the RX context (registers, descriptor rings, etc.).
4849          */
4850         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4851         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4852
4853         /* Enable receipt of broadcasted frames */
4854         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4855         fctrl |= IXGBE_FCTRL_BAM;
4856         fctrl |= IXGBE_FCTRL_DPF;
4857         fctrl |= IXGBE_FCTRL_PMCF;
4858         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4859
4860         /*
4861          * Configure CRC stripping, if any.
4862          */
4863         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4864         if (rx_conf->offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4865                 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
4866         else
4867                 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
4868
4869         /*
4870          * Configure jumbo frame support, if any.
4871          */
4872         if (rx_conf->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
4873                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4874                 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4875                 maxfrs &= 0x0000FFFF;
4876                 maxfrs |= (rx_conf->max_rx_pkt_len << 16);
4877                 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4878         } else
4879                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4880
4881         /*
4882          * If loopback mode is configured, set LPBK bit.
4883          */
4884         if (dev->data->dev_conf.lpbk_mode != 0) {
4885                 rc = ixgbe_check_supported_loopback_mode(dev);
4886                 if (rc < 0) {
4887                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
4888                         return rc;
4889                 }
4890                 hlreg0 |= IXGBE_HLREG0_LPBK;
4891         } else {
4892                 hlreg0 &= ~IXGBE_HLREG0_LPBK;
4893         }
4894
4895         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4896
4897         /*
4898          * Assume no header split and no VLAN strip support
4899          * on any Rx queue first .
4900          */
4901         rx_conf->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
4902         /* Setup RX queues */
4903         for (i = 0; i < dev->data->nb_rx_queues; i++) {
4904                 rxq = dev->data->rx_queues[i];
4905
4906                 /*
4907                  * Reset crc_len in case it was changed after queue setup by a
4908                  * call to configure.
4909                  */
4910                 if (rx_conf->offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4911                         rxq->crc_len = ETHER_CRC_LEN;
4912                 else
4913                         rxq->crc_len = 0;
4914
4915                 /* Setup the Base and Length of the Rx Descriptor Rings */
4916                 bus_addr = rxq->rx_ring_phys_addr;
4917                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),
4918                                 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4919                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),
4920                                 (uint32_t)(bus_addr >> 32));
4921                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),
4922                                 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
4923                 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
4924                 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);
4925
4926                 /* Configure the SRRCTL register */
4927                 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
4928
4929                 /* Set if packets are dropped when no descriptors available */
4930                 if (rxq->drop_en)
4931                         srrctl |= IXGBE_SRRCTL_DROP_EN;
4932
4933                 /*
4934                  * Configure the RX buffer size in the BSIZEPACKET field of
4935                  * the SRRCTL register of the queue.
4936                  * The value is in 1 KB resolution. Valid values can be from
4937                  * 1 KB to 16 KB.
4938                  */
4939                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
4940                         RTE_PKTMBUF_HEADROOM);
4941                 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
4942                            IXGBE_SRRCTL_BSIZEPKT_MASK);
4943
4944                 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
4945
4946                 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
4947                                        IXGBE_SRRCTL_BSIZEPKT_SHIFT);
4948
4949                 /* It adds dual VLAN length for supporting dual VLAN */
4950                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len +
4951                                             2 * IXGBE_VLAN_TAG_SIZE > buf_size)
4952                         dev->data->scattered_rx = 1;
4953                 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4954                         rx_conf->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
4955         }
4956
4957         if (rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER)
4958                 dev->data->scattered_rx = 1;
4959
4960         /*
4961          * Device configured with multiple RX queues.
4962          */
4963         ixgbe_dev_mq_rx_configure(dev);
4964
4965         /*
4966          * Setup the Checksum Register.
4967          * Disable Full-Packet Checksum which is mutually exclusive with RSS.
4968          * Enable IP/L4 checkum computation by hardware if requested to do so.
4969          */
4970         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
4971         rxcsum |= IXGBE_RXCSUM_PCSD;
4972         if (rx_conf->offloads & DEV_RX_OFFLOAD_CHECKSUM)
4973                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
4974         else
4975                 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
4976
4977         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
4978
4979         if (hw->mac.type == ixgbe_mac_82599EB ||
4980             hw->mac.type == ixgbe_mac_X540) {
4981                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4982                 if (rx_conf->offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4983                         rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
4984                 else
4985                         rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
4986                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
4987                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4988         }
4989
4990         rc = ixgbe_set_rsc(dev);
4991         if (rc)
4992                 return rc;
4993
4994         ixgbe_set_rx_function(dev);
4995
4996         return 0;
4997 }
4998
4999 /*
5000  * Initializes Transmit Unit.
5001  */
5002 void __attribute__((cold))
5003 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
5004 {
5005         struct ixgbe_hw     *hw;
5006         struct ixgbe_tx_queue *txq;
5007         uint64_t bus_addr;
5008         uint32_t hlreg0;
5009         uint32_t txctrl;
5010         uint16_t i;
5011
5012         PMD_INIT_FUNC_TRACE();
5013         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5014
5015         /* Enable TX CRC (checksum offload requirement) and hw padding
5016          * (TSO requirement)
5017          */
5018         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5019         hlreg0 |= (IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_TXPADEN);
5020         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5021
5022         /* Setup the Base and Length of the Tx Descriptor Rings */
5023         for (i = 0; i < dev->data->nb_tx_queues; i++) {
5024                 txq = dev->data->tx_queues[i];
5025
5026                 bus_addr = txq->tx_ring_phys_addr;
5027                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),
5028                                 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
5029                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),
5030                                 (uint32_t)(bus_addr >> 32));
5031                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),
5032                                 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
5033                 /* Setup the HW Tx Head and TX Tail descriptor pointers */
5034                 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
5035                 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
5036
5037                 /*
5038                  * Disable Tx Head Writeback RO bit, since this hoses
5039                  * bookkeeping if things aren't delivered in order.
5040                  */
5041                 switch (hw->mac.type) {
5042                 case ixgbe_mac_82598EB:
5043                         txctrl = IXGBE_READ_REG(hw,
5044                                                 IXGBE_DCA_TXCTRL(txq->reg_idx));
5045                         txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
5046                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),
5047                                         txctrl);
5048                         break;
5049
5050                 case ixgbe_mac_82599EB:
5051                 case ixgbe_mac_X540:
5052                 case ixgbe_mac_X550:
5053                 case ixgbe_mac_X550EM_x:
5054                 case ixgbe_mac_X550EM_a:
5055                 default:
5056                         txctrl = IXGBE_READ_REG(hw,
5057                                                 IXGBE_DCA_TXCTRL_82599(txq->reg_idx));
5058                         txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
5059                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),
5060                                         txctrl);
5061                         break;
5062                 }
5063         }
5064
5065         /* Device configured with multiple TX queues. */
5066         ixgbe_dev_mq_tx_configure(dev);
5067 }
5068
5069 /*
5070  * Check if requested loopback mode is supported
5071  */
5072 int
5073 ixgbe_check_supported_loopback_mode(struct rte_eth_dev *dev)
5074 {
5075         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5076
5077         if (dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
5078                 if (hw->mac.type == ixgbe_mac_82599EB)
5079                         return 0;
5080
5081         return -ENOTSUP;
5082 }
5083
5084 /*
5085  * Set up link for 82599 loopback mode Tx->Rx.
5086  */
5087 static inline void __attribute__((cold))
5088 ixgbe_setup_loopback_link_82599(struct ixgbe_hw *hw)
5089 {
5090         PMD_INIT_FUNC_TRACE();
5091
5092         if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
5093                 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM) !=
5094                                 IXGBE_SUCCESS) {
5095                         PMD_INIT_LOG(ERR, "Could not enable loopback mode");
5096                         /* ignore error */
5097                         return;
5098                 }
5099         }
5100
5101         /* Restart link */
5102         IXGBE_WRITE_REG(hw,
5103                         IXGBE_AUTOC,
5104                         IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU);
5105         ixgbe_reset_pipeline_82599(hw);
5106
5107         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
5108         msec_delay(50);
5109 }
5110
5111
5112 /*
5113  * Start Transmit and Receive Units.
5114  */
5115 int __attribute__((cold))
5116 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
5117 {
5118         struct ixgbe_hw     *hw;
5119         struct ixgbe_tx_queue *txq;
5120         struct ixgbe_rx_queue *rxq;
5121         uint32_t txdctl;
5122         uint32_t dmatxctl;
5123         uint32_t rxctrl;
5124         uint16_t i;
5125         int ret = 0;
5126
5127         PMD_INIT_FUNC_TRACE();
5128         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5129
5130         for (i = 0; i < dev->data->nb_tx_queues; i++) {
5131                 txq = dev->data->tx_queues[i];
5132                 /* Setup Transmit Threshold Registers */
5133                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
5134                 txdctl |= txq->pthresh & 0x7F;
5135                 txdctl |= ((txq->hthresh & 0x7F) << 8);
5136                 txdctl |= ((txq->wthresh & 0x7F) << 16);
5137                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
5138         }
5139
5140         if (hw->mac.type != ixgbe_mac_82598EB) {
5141                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
5142                 dmatxctl |= IXGBE_DMATXCTL_TE;
5143                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
5144         }
5145
5146         for (i = 0; i < dev->data->nb_tx_queues; i++) {
5147                 txq = dev->data->tx_queues[i];
5148                 if (!txq->tx_deferred_start) {
5149                         ret = ixgbe_dev_tx_queue_start(dev, i);
5150                         if (ret < 0)
5151                                 return ret;
5152                 }
5153         }
5154
5155         for (i = 0; i < dev->data->nb_rx_queues; i++) {
5156                 rxq = dev->data->rx_queues[i];
5157                 if (!rxq->rx_deferred_start) {
5158                         ret = ixgbe_dev_rx_queue_start(dev, i);
5159                         if (ret < 0)
5160                                 return ret;
5161                 }
5162         }
5163
5164         /* Enable Receive engine */
5165         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5166         if (hw->mac.type == ixgbe_mac_82598EB)
5167                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
5168         rxctrl |= IXGBE_RXCTRL_RXEN;
5169         hw->mac.ops.enable_rx_dma(hw, rxctrl);
5170
5171         /* If loopback mode is enabled, set up the link accordingly */
5172         if (dev->data->dev_conf.lpbk_mode != 0) {
5173                 if (hw->mac.type == ixgbe_mac_82599EB)
5174                         ixgbe_setup_loopback_link_82599(hw);
5175         }
5176
5177 #ifdef RTE_LIBRTE_SECURITY
5178         if ((dev->data->dev_conf.rxmode.offloads &
5179                         DEV_RX_OFFLOAD_SECURITY) ||
5180                 (dev->data->dev_conf.txmode.offloads &
5181                         DEV_TX_OFFLOAD_SECURITY)) {
5182                 ret = ixgbe_crypto_enable_ipsec(dev);
5183                 if (ret != 0) {
5184                         PMD_DRV_LOG(ERR,
5185                                     "ixgbe_crypto_enable_ipsec fails with %d.",
5186                                     ret);
5187                         return ret;
5188                 }
5189         }
5190 #endif
5191
5192         return 0;
5193 }
5194
5195 /*
5196  * Start Receive Units for specified queue.
5197  */
5198 int __attribute__((cold))
5199 ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
5200 {
5201         struct ixgbe_hw     *hw;
5202         struct ixgbe_rx_queue *rxq;
5203         uint32_t rxdctl;
5204         int poll_ms;
5205
5206         PMD_INIT_FUNC_TRACE();
5207         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5208
5209         rxq = dev->data->rx_queues[rx_queue_id];
5210
5211         /* Allocate buffers for descriptor rings */
5212         if (ixgbe_alloc_rx_queue_mbufs(rxq) != 0) {
5213                 PMD_INIT_LOG(ERR, "Could not alloc mbuf for queue:%d",
5214                              rx_queue_id);
5215                 return -1;
5216         }
5217         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
5218         rxdctl |= IXGBE_RXDCTL_ENABLE;
5219         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
5220
5221         /* Wait until RX Enable ready */
5222         poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
5223         do {
5224                 rte_delay_ms(1);
5225                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
5226         } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
5227         if (!poll_ms)
5228                 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d", rx_queue_id);
5229         rte_wmb();
5230         IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
5231         IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
5232         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
5233
5234         return 0;
5235 }
5236
5237 /*
5238  * Stop Receive Units for specified queue.
5239  */
5240 int __attribute__((cold))
5241 ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
5242 {
5243         struct ixgbe_hw     *hw;
5244         struct ixgbe_adapter *adapter =
5245                 (struct ixgbe_adapter *)dev->data->dev_private;
5246         struct ixgbe_rx_queue *rxq;
5247         uint32_t rxdctl;
5248         int poll_ms;
5249
5250         PMD_INIT_FUNC_TRACE();
5251         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5252
5253         rxq = dev->data->rx_queues[rx_queue_id];
5254
5255         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
5256         rxdctl &= ~IXGBE_RXDCTL_ENABLE;
5257         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
5258
5259         /* Wait until RX Enable bit clear */
5260         poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
5261         do {
5262                 rte_delay_ms(1);
5263                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
5264         } while (--poll_ms && (rxdctl & IXGBE_RXDCTL_ENABLE));
5265         if (!poll_ms)
5266                 PMD_INIT_LOG(ERR, "Could not disable Rx Queue %d", rx_queue_id);
5267
5268         rte_delay_us(RTE_IXGBE_WAIT_100_US);
5269
5270         ixgbe_rx_queue_release_mbufs(rxq);
5271         ixgbe_reset_rx_queue(adapter, rxq);
5272         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
5273
5274         return 0;
5275 }
5276
5277
5278 /*
5279  * Start Transmit Units for specified queue.
5280  */
5281 int __attribute__((cold))
5282 ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
5283 {
5284         struct ixgbe_hw     *hw;
5285         struct ixgbe_tx_queue *txq;
5286         uint32_t txdctl;
5287         int poll_ms;
5288
5289         PMD_INIT_FUNC_TRACE();
5290         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5291
5292         txq = dev->data->tx_queues[tx_queue_id];
5293         IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
5294         txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
5295         txdctl |= IXGBE_TXDCTL_ENABLE;
5296         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
5297
5298         /* Wait until TX Enable ready */
5299         if (hw->mac.type == ixgbe_mac_82599EB) {
5300                 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
5301                 do {
5302                         rte_delay_ms(1);
5303                         txdctl = IXGBE_READ_REG(hw,
5304                                 IXGBE_TXDCTL(txq->reg_idx));
5305                 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
5306                 if (!poll_ms)
5307                         PMD_INIT_LOG(ERR, "Could not enable Tx Queue %d",
5308                                 tx_queue_id);
5309         }
5310         rte_wmb();
5311         IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
5312         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
5313
5314         return 0;
5315 }
5316
5317 /*
5318  * Stop Transmit Units for specified queue.
5319  */
5320 int __attribute__((cold))
5321 ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
5322 {
5323         struct ixgbe_hw     *hw;
5324         struct ixgbe_tx_queue *txq;
5325         uint32_t txdctl;
5326         uint32_t txtdh, txtdt;
5327         int poll_ms;
5328
5329         PMD_INIT_FUNC_TRACE();
5330         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5331
5332         txq = dev->data->tx_queues[tx_queue_id];
5333
5334         /* Wait until TX queue is empty */
5335         if (hw->mac.type == ixgbe_mac_82599EB) {
5336                 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
5337                 do {
5338                         rte_delay_us(RTE_IXGBE_WAIT_100_US);
5339                         txtdh = IXGBE_READ_REG(hw,
5340                                                IXGBE_TDH(txq->reg_idx));
5341                         txtdt = IXGBE_READ_REG(hw,
5342                                                IXGBE_TDT(txq->reg_idx));
5343                 } while (--poll_ms && (txtdh != txtdt));
5344                 if (!poll_ms)
5345                         PMD_INIT_LOG(ERR,
5346                                 "Tx Queue %d is not empty when stopping.",
5347                                 tx_queue_id);
5348         }
5349
5350         txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
5351         txdctl &= ~IXGBE_TXDCTL_ENABLE;
5352         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
5353
5354         /* Wait until TX Enable bit clear */
5355         if (hw->mac.type == ixgbe_mac_82599EB) {
5356                 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
5357                 do {
5358                         rte_delay_ms(1);
5359                         txdctl = IXGBE_READ_REG(hw,
5360                                                 IXGBE_TXDCTL(txq->reg_idx));
5361                 } while (--poll_ms && (txdctl & IXGBE_TXDCTL_ENABLE));
5362                 if (!poll_ms)
5363                         PMD_INIT_LOG(ERR, "Could not disable Tx Queue %d",
5364                                 tx_queue_id);
5365         }
5366
5367         if (txq->ops != NULL) {
5368                 txq->ops->release_mbufs(txq);
5369                 txq->ops->reset(txq);
5370         }
5371         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
5372
5373         return 0;
5374 }
5375
5376 void
5377 ixgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
5378         struct rte_eth_rxq_info *qinfo)
5379 {
5380         struct ixgbe_rx_queue *rxq;
5381
5382         rxq = dev->data->rx_queues[queue_id];
5383
5384         qinfo->mp = rxq->mb_pool;
5385         qinfo->scattered_rx = dev->data->scattered_rx;
5386         qinfo->nb_desc = rxq->nb_rx_desc;
5387
5388         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
5389         qinfo->conf.rx_drop_en = rxq->drop_en;
5390         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
5391         qinfo->conf.offloads = rxq->offloads;
5392 }
5393
5394 void
5395 ixgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
5396         struct rte_eth_txq_info *qinfo)
5397 {
5398         struct ixgbe_tx_queue *txq;
5399
5400         txq = dev->data->tx_queues[queue_id];
5401
5402         qinfo->nb_desc = txq->nb_tx_desc;
5403
5404         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
5405         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
5406         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
5407
5408         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
5409         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
5410         qinfo->conf.offloads = txq->offloads;
5411         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
5412 }
5413
5414 /*
5415  * [VF] Initializes Receive Unit.
5416  */
5417 int __attribute__((cold))
5418 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
5419 {
5420         struct ixgbe_hw     *hw;
5421         struct ixgbe_rx_queue *rxq;
5422         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
5423         uint64_t bus_addr;
5424         uint32_t srrctl, psrtype = 0;
5425         uint16_t buf_size;
5426         uint16_t i;
5427         int ret;
5428
5429         PMD_INIT_FUNC_TRACE();
5430         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5431
5432         if (rte_is_power_of_2(dev->data->nb_rx_queues) == 0) {
5433                 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
5434                         "it should be power of 2");
5435                 return -1;
5436         }
5437
5438         if (dev->data->nb_rx_queues > hw->mac.max_rx_queues) {
5439                 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
5440                         "it should be equal to or less than %d",
5441                         hw->mac.max_rx_queues);
5442                 return -1;
5443         }
5444
5445         /*
5446          * When the VF driver issues a IXGBE_VF_RESET request, the PF driver
5447          * disables the VF receipt of packets if the PF MTU is > 1500.
5448          * This is done to deal with 82599 limitations that imposes
5449          * the PF and all VFs to share the same MTU.
5450          * Then, the PF driver enables again the VF receipt of packet when
5451          * the VF driver issues a IXGBE_VF_SET_LPE request.
5452          * In the meantime, the VF device cannot be used, even if the VF driver
5453          * and the Guest VM network stack are ready to accept packets with a
5454          * size up to the PF MTU.
5455          * As a work-around to this PF behaviour, force the call to
5456          * ixgbevf_rlpml_set_vf even if jumbo frames are not used. This way,
5457          * VF packets received can work in all cases.
5458          */
5459         ixgbevf_rlpml_set_vf(hw,
5460                 (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len);
5461
5462         /*
5463          * Assume no header split and no VLAN strip support
5464          * on any Rx queue first .
5465          */
5466         rxmode->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
5467         /* Setup RX queues */
5468         for (i = 0; i < dev->data->nb_rx_queues; i++) {
5469                 rxq = dev->data->rx_queues[i];
5470
5471                 /* Allocate buffers for descriptor rings */
5472                 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
5473                 if (ret)
5474                         return ret;
5475
5476                 /* Setup the Base and Length of the Rx Descriptor Rings */
5477                 bus_addr = rxq->rx_ring_phys_addr;
5478
5479                 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
5480                                 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
5481                 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
5482                                 (uint32_t)(bus_addr >> 32));
5483                 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
5484                                 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
5485                 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
5486                 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
5487
5488
5489                 /* Configure the SRRCTL register */
5490                 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
5491
5492                 /* Set if packets are dropped when no descriptors available */
5493                 if (rxq->drop_en)
5494                         srrctl |= IXGBE_SRRCTL_DROP_EN;
5495
5496                 /*
5497                  * Configure the RX buffer size in the BSIZEPACKET field of
5498                  * the SRRCTL register of the queue.
5499                  * The value is in 1 KB resolution. Valid values can be from
5500                  * 1 KB to 16 KB.
5501                  */
5502                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
5503                         RTE_PKTMBUF_HEADROOM);
5504                 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
5505                            IXGBE_SRRCTL_BSIZEPKT_MASK);
5506
5507                 /*
5508                  * VF modification to write virtual function SRRCTL register
5509                  */
5510                 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
5511
5512                 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
5513                                        IXGBE_SRRCTL_BSIZEPKT_SHIFT);
5514
5515                 if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER ||
5516                     /* It adds dual VLAN length for supporting dual VLAN */
5517                     (rxmode->max_rx_pkt_len +
5518                                 2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {
5519                         if (!dev->data->scattered_rx)
5520                                 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
5521                         dev->data->scattered_rx = 1;
5522                 }
5523
5524                 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
5525                         rxmode->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
5526         }
5527
5528         /* Set RQPL for VF RSS according to max Rx queue */
5529         psrtype |= (dev->data->nb_rx_queues >> 1) <<
5530                 IXGBE_PSRTYPE_RQPL_SHIFT;
5531         IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, psrtype);
5532
5533         ixgbe_set_rx_function(dev);
5534
5535         return 0;
5536 }
5537
5538 /*
5539  * [VF] Initializes Transmit Unit.
5540  */
5541 void __attribute__((cold))
5542 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
5543 {
5544         struct ixgbe_hw     *hw;
5545         struct ixgbe_tx_queue *txq;
5546         uint64_t bus_addr;
5547         uint32_t txctrl;
5548         uint16_t i;
5549
5550         PMD_INIT_FUNC_TRACE();
5551         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5552
5553         /* Setup the Base and Length of the Tx Descriptor Rings */
5554         for (i = 0; i < dev->data->nb_tx_queues; i++) {
5555                 txq = dev->data->tx_queues[i];
5556                 bus_addr = txq->tx_ring_phys_addr;
5557                 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
5558                                 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
5559                 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
5560                                 (uint32_t)(bus_addr >> 32));
5561                 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
5562                                 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
5563                 /* Setup the HW Tx Head and TX Tail descriptor pointers */
5564                 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
5565                 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
5566
5567                 /*
5568                  * Disable Tx Head Writeback RO bit, since this hoses
5569                  * bookkeeping if things aren't delivered in order.
5570                  */
5571                 txctrl = IXGBE_READ_REG(hw,
5572                                 IXGBE_VFDCA_TXCTRL(i));
5573                 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
5574                 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
5575                                 txctrl);
5576         }
5577 }
5578
5579 /*
5580  * [VF] Start Transmit and Receive Units.
5581  */
5582 void __attribute__((cold))
5583 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
5584 {
5585         struct ixgbe_hw     *hw;
5586         struct ixgbe_tx_queue *txq;
5587         struct ixgbe_rx_queue *rxq;
5588         uint32_t txdctl;
5589         uint32_t rxdctl;
5590         uint16_t i;
5591         int poll_ms;
5592
5593         PMD_INIT_FUNC_TRACE();
5594         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5595
5596         for (i = 0; i < dev->data->nb_tx_queues; i++) {
5597                 txq = dev->data->tx_queues[i];
5598                 /* Setup Transmit Threshold Registers */
5599                 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
5600                 txdctl |= txq->pthresh & 0x7F;
5601                 txdctl |= ((txq->hthresh & 0x7F) << 8);
5602                 txdctl |= ((txq->wthresh & 0x7F) << 16);
5603                 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
5604         }
5605
5606         for (i = 0; i < dev->data->nb_tx_queues; i++) {
5607
5608                 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
5609                 txdctl |= IXGBE_TXDCTL_ENABLE;
5610                 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
5611
5612                 poll_ms = 10;
5613                 /* Wait until TX Enable ready */
5614                 do {
5615                         rte_delay_ms(1);
5616                         txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
5617                 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
5618                 if (!poll_ms)
5619                         PMD_INIT_LOG(ERR, "Could not enable Tx Queue %d", i);
5620         }
5621         for (i = 0; i < dev->data->nb_rx_queues; i++) {
5622
5623                 rxq = dev->data->rx_queues[i];
5624
5625                 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
5626                 rxdctl |= IXGBE_RXDCTL_ENABLE;
5627                 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
5628
5629                 /* Wait until RX Enable ready */
5630                 poll_ms = 10;
5631                 do {
5632                         rte_delay_ms(1);
5633                         rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
5634                 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
5635                 if (!poll_ms)
5636                         PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d", i);
5637                 rte_wmb();
5638                 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);
5639
5640         }
5641 }
5642
5643 int
5644 ixgbe_rss_conf_init(struct ixgbe_rte_flow_rss_conf *out,
5645                     const struct rte_flow_action_rss *in)
5646 {
5647         if (in->key_len > RTE_DIM(out->key) ||
5648             in->queue_num > RTE_DIM(out->queue))
5649                 return -EINVAL;
5650         out->conf = (struct rte_flow_action_rss){
5651                 .func = in->func,
5652                 .level = in->level,
5653                 .types = in->types,
5654                 .key_len = in->key_len,
5655                 .queue_num = in->queue_num,
5656                 .key = memcpy(out->key, in->key, in->key_len),
5657                 .queue = memcpy(out->queue, in->queue,
5658                                 sizeof(*in->queue) * in->queue_num),
5659         };
5660         return 0;
5661 }
5662
5663 int
5664 ixgbe_action_rss_same(const struct rte_flow_action_rss *comp,
5665                       const struct rte_flow_action_rss *with)
5666 {
5667         return (comp->func == with->func &&
5668                 comp->level == with->level &&
5669                 comp->types == with->types &&
5670                 comp->key_len == with->key_len &&
5671                 comp->queue_num == with->queue_num &&
5672                 !memcmp(comp->key, with->key, with->key_len) &&
5673                 !memcmp(comp->queue, with->queue,
5674                         sizeof(*with->queue) * with->queue_num));
5675 }
5676
5677 int
5678 ixgbe_config_rss_filter(struct rte_eth_dev *dev,
5679                 struct ixgbe_rte_flow_rss_conf *conf, bool add)
5680 {
5681         struct ixgbe_hw *hw;
5682         uint32_t reta;
5683         uint16_t i;
5684         uint16_t j;
5685         uint16_t sp_reta_size;
5686         uint32_t reta_reg;
5687         struct rte_eth_rss_conf rss_conf = {
5688                 .rss_key = conf->conf.key_len ?
5689                         (void *)(uintptr_t)conf->conf.key : NULL,
5690                 .rss_key_len = conf->conf.key_len,
5691                 .rss_hf = conf->conf.types,
5692         };
5693         struct ixgbe_filter_info *filter_info =
5694                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5695
5696         PMD_INIT_FUNC_TRACE();
5697         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5698
5699         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5700
5701         if (!add) {
5702                 if (ixgbe_action_rss_same(&filter_info->rss_info.conf,
5703                                           &conf->conf)) {
5704                         ixgbe_rss_disable(dev);
5705                         memset(&filter_info->rss_info, 0,
5706                                 sizeof(struct ixgbe_rte_flow_rss_conf));
5707                         return 0;
5708                 }
5709                 return -EINVAL;
5710         }
5711
5712         if (filter_info->rss_info.conf.queue_num)
5713                 return -EINVAL;
5714         /* Fill in redirection table
5715          * The byte-swap is needed because NIC registers are in
5716          * little-endian order.
5717          */
5718         reta = 0;
5719         for (i = 0, j = 0; i < sp_reta_size; i++, j++) {
5720                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5721
5722                 if (j == conf->conf.queue_num)
5723                         j = 0;
5724                 reta = (reta << 8) | conf->conf.queue[j];
5725                 if ((i & 3) == 3)
5726                         IXGBE_WRITE_REG(hw, reta_reg,
5727                                         rte_bswap32(reta));
5728         }
5729
5730         /* Configure the RSS key and the RSS protocols used to compute
5731          * the RSS hash of input packets.
5732          */
5733         if ((rss_conf.rss_hf & IXGBE_RSS_OFFLOAD_ALL) == 0) {
5734                 ixgbe_rss_disable(dev);
5735                 return 0;
5736         }
5737         if (rss_conf.rss_key == NULL)
5738                 rss_conf.rss_key = rss_intel_key; /* Default hash key */
5739         ixgbe_hw_rss_hash_set(hw, &rss_conf);
5740
5741         if (ixgbe_rss_conf_init(&filter_info->rss_info, &conf->conf))
5742                 return -EINVAL;
5743
5744         return 0;
5745 }
5746
5747 /* Stubs needed for linkage when CONFIG_RTE_IXGBE_INC_VECTOR is set to 'n' */
5748 __rte_weak int
5749 ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
5750 {
5751         return -1;
5752 }
5753
5754 __rte_weak uint16_t
5755 ixgbe_recv_pkts_vec(
5756         void __rte_unused *rx_queue,
5757         struct rte_mbuf __rte_unused **rx_pkts,
5758         uint16_t __rte_unused nb_pkts)
5759 {
5760         return 0;
5761 }
5762
5763 __rte_weak uint16_t
5764 ixgbe_recv_scattered_pkts_vec(
5765         void __rte_unused *rx_queue,
5766         struct rte_mbuf __rte_unused **rx_pkts,
5767         uint16_t __rte_unused nb_pkts)
5768 {
5769         return 0;
5770 }
5771
5772 __rte_weak int
5773 ixgbe_rxq_vec_setup(struct ixgbe_rx_queue __rte_unused *rxq)
5774 {
5775         return -1;
5776 }