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35 #include <rte_ethdev.h>
36 #include <rte_malloc.h>
38 #include "ixgbe_ethdev.h"
39 #include "ixgbe_rxtx.h"
41 #include <tmmintrin.h>
43 #ifndef __INTEL_COMPILER
44 #pragma GCC diagnostic ignored "-Wcast-qual"
48 ixgbe_rxq_rearm(struct ixgbe_rx_queue *rxq)
52 volatile union ixgbe_adv_rx_desc *rxdp;
53 struct ixgbe_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
54 struct rte_mbuf *mb0, *mb1;
55 __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
56 RTE_PKTMBUF_HEADROOM);
57 __m128i dma_addr0, dma_addr1;
59 rxdp = rxq->rx_ring + rxq->rxrearm_start;
61 /* Pull 'n' more MBUFs into the software ring */
62 if (rte_mempool_get_bulk(rxq->mb_pool,
64 RTE_IXGBE_RXQ_REARM_THRESH) < 0) {
65 if (rxq->rxrearm_nb + RTE_IXGBE_RXQ_REARM_THRESH >=
67 dma_addr0 = _mm_setzero_si128();
68 for (i = 0; i < RTE_IXGBE_DESCS_PER_LOOP; i++) {
69 rxep[i].mbuf = &rxq->fake_mbuf;
70 _mm_store_si128((__m128i *)&rxdp[i].read,
74 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
75 RTE_IXGBE_RXQ_REARM_THRESH;
79 /* Initialize the mbufs in vector, process 2 mbufs in one loop */
80 for (i = 0; i < RTE_IXGBE_RXQ_REARM_THRESH; i += 2, rxep += 2) {
81 __m128i vaddr0, vaddr1;
88 * Flush mbuf with pkt template.
89 * Data to be rearmed is 6 bytes long.
90 * Though, RX will overwrite ol_flags that are coming next
91 * anyway. So overwrite whole 8 bytes with one load:
92 * 6 bytes of rearm_data plus first 2 bytes of ol_flags.
94 p0 = (uintptr_t)&mb0->rearm_data;
95 *(uint64_t *)p0 = rxq->mbuf_initializer;
96 p1 = (uintptr_t)&mb1->rearm_data;
97 *(uint64_t *)p1 = rxq->mbuf_initializer;
99 /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */
100 vaddr0 = _mm_loadu_si128((__m128i *)&(mb0->buf_addr));
101 vaddr1 = _mm_loadu_si128((__m128i *)&(mb1->buf_addr));
103 /* convert pa to dma_addr hdr/data */
104 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
105 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
107 /* add headroom to pa values */
108 dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
109 dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
111 /* flush desc with pa dma_addr */
112 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
113 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
116 rxq->rxrearm_start += RTE_IXGBE_RXQ_REARM_THRESH;
117 if (rxq->rxrearm_start >= rxq->nb_rx_desc)
118 rxq->rxrearm_start = 0;
120 rxq->rxrearm_nb -= RTE_IXGBE_RXQ_REARM_THRESH;
122 rx_id = (uint16_t) ((rxq->rxrearm_start == 0) ?
123 (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
125 /* Update the tail pointer on the NIC */
126 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
129 /* Handling the offload flags (olflags) field takes computation
130 * time when receiving packets. Therefore we provide a flag to disable
131 * the processing of the olflags field when they are not needed. This
132 * gives improved performance, at the cost of losing the offload info
133 * in the received packet
135 #ifdef RTE_IXGBE_RX_OLFLAGS_ENABLE
138 #define OLFLAGS_MASK ((uint16_t)(PKT_RX_VLAN_PKT | PKT_RX_IPV4_HDR |\
139 PKT_RX_IPV4_HDR_EXT | PKT_RX_IPV6_HDR |\
140 PKT_RX_IPV6_HDR_EXT))
141 #define PTYPE_SHIFT (1)
142 #endif /* RTE_NEXT_ABI */
144 #define VTAG_SHIFT (3)
147 desc_to_olflags_v(__m128i descs[4], struct rte_mbuf **rx_pkts)
150 __m128i ptype0, ptype1, vtag0, vtag1;
156 /* pkt type + vlan olflags mask */
157 const __m128i pkttype_msk = _mm_set_epi16(
158 0x0000, 0x0000, 0x0000, 0x0000,
159 PKT_RX_VLAN_PKT, PKT_RX_VLAN_PKT, PKT_RX_VLAN_PKT, PKT_RX_VLAN_PKT);
161 /* mask everything except rss type */
162 const __m128i rsstype_msk = _mm_set_epi16(
163 0x0000, 0x0000, 0x0000, 0x0000,
164 0x000F, 0x000F, 0x000F, 0x000F);
166 /* map rss type to rss hash flag */
167 const __m128i rss_flags = _mm_set_epi8(PKT_RX_FDIR, 0, 0, 0,
168 0, 0, 0, PKT_RX_RSS_HASH,
169 PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH, 0,
170 PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, 0);
172 ptype0 = _mm_unpacklo_epi16(descs[0], descs[1]);
173 ptype1 = _mm_unpacklo_epi16(descs[2], descs[3]);
174 vtag0 = _mm_unpackhi_epi16(descs[0], descs[1]);
175 vtag1 = _mm_unpackhi_epi16(descs[2], descs[3]);
177 ptype0 = _mm_unpacklo_epi32(ptype0, ptype1);
178 ptype0 = _mm_and_si128(ptype0, rsstype_msk);
179 ptype0 = _mm_shuffle_epi8(rss_flags, ptype0);
181 vtag1 = _mm_unpacklo_epi32(vtag0, vtag1);
182 vtag1 = _mm_srli_epi16(vtag1, VTAG_SHIFT);
183 vtag1 = _mm_and_si128(vtag1, pkttype_msk);
185 vtag1 = _mm_or_si128(ptype0, vtag1);
186 vol.dword = _mm_cvtsi128_si64(vtag1);
188 __m128i ptype0, ptype1, vtag0, vtag1;
194 /* pkt type + vlan olflags mask */
195 const __m128i pkttype_msk = _mm_set_epi16(
196 0x0000, 0x0000, 0x0000, 0x0000,
197 OLFLAGS_MASK, OLFLAGS_MASK, OLFLAGS_MASK, OLFLAGS_MASK);
199 /* mask everything except rss type */
200 const __m128i rsstype_msk = _mm_set_epi16(
201 0x0000, 0x0000, 0x0000, 0x0000,
202 0x000F, 0x000F, 0x000F, 0x000F);
204 /* rss type to PKT_RX_RSS_HASH translation */
205 const __m128i rss_flags = _mm_set_epi8(PKT_RX_FDIR, 0, 0, 0,
206 0, 0, 0, PKT_RX_RSS_HASH,
207 PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH, 0,
208 PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, 0);
210 ptype0 = _mm_unpacklo_epi16(descs[0], descs[1]);
211 ptype1 = _mm_unpacklo_epi16(descs[2], descs[3]);
212 vtag0 = _mm_unpackhi_epi16(descs[0], descs[1]);
213 vtag1 = _mm_unpackhi_epi16(descs[2], descs[3]);
215 ptype1 = _mm_unpacklo_epi32(ptype0, ptype1);
216 vtag1 = _mm_unpacklo_epi32(vtag0, vtag1);
218 ptype0 = _mm_and_si128(ptype1, rsstype_msk);
219 ptype0 = _mm_shuffle_epi8(rss_flags, ptype0);
221 ptype1 = _mm_slli_epi16(ptype1, PTYPE_SHIFT);
222 vtag1 = _mm_srli_epi16(vtag1, VTAG_SHIFT);
224 ptype1 = _mm_or_si128(ptype1, vtag1);
225 ptype1 = _mm_and_si128(ptype1, pkttype_msk);
227 ptype0 = _mm_or_si128(ptype0, ptype1);
229 vol.dword = _mm_cvtsi128_si64(ptype0);
230 #endif /* RTE_NEXT_ABI */
232 rx_pkts[0]->ol_flags = vol.e[0];
233 rx_pkts[1]->ol_flags = vol.e[1];
234 rx_pkts[2]->ol_flags = vol.e[2];
235 rx_pkts[3]->ol_flags = vol.e[3];
238 #define desc_to_olflags_v(desc, rx_pkts) do {} while (0)
242 * vPMD receive routine, now only accept (nb_pkts == RTE_IXGBE_VPMD_RX_BURST)
246 * - nb_pkts < RTE_IXGBE_VPMD_RX_BURST, just return no packet
247 * - nb_pkts > RTE_IXGBE_VPMD_RX_BURST, only scan RTE_IXGBE_VPMD_RX_BURST
249 * - don't support ol_flags for rss and csum err
251 static inline uint16_t
252 _recv_raw_pkts_vec(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
253 uint16_t nb_pkts, uint8_t *split_packet)
255 volatile union ixgbe_adv_rx_desc *rxdp;
256 struct ixgbe_rx_entry *sw_ring;
257 uint16_t nb_pkts_recd;
262 __m128i crc_adjust = _mm_set_epi16(
263 0, 0, 0, /* ignore non-length fields */
264 -rxq->crc_len, /* sub crc on data_len */
265 0, /* ignore high-16bits of pkt_len */
266 -rxq->crc_len, /* sub crc on pkt_len */
267 0, 0 /* ignore pkt_type field */
269 __m128i dd_check, eop_check;
270 __m128i desc_mask = _mm_set_epi32(0xFFFFFFFF, 0xFFFFFFFF,
271 0xFFFFFFFF, 0xFFFF07F0);
273 __m128i crc_adjust = _mm_set_epi16(
274 0, 0, 0, 0, /* ignore non-length fields */
275 0, /* ignore high-16bits of pkt_len */
276 -rxq->crc_len, /* sub crc on pkt_len */
277 -rxq->crc_len, /* sub crc on data_len */
278 0 /* ignore pkt_type field */
280 __m128i dd_check, eop_check;
281 #endif /* RTE_NEXT_ABI */
283 if (unlikely(nb_pkts < RTE_IXGBE_VPMD_RX_BURST))
286 /* Just the act of getting into the function from the application is
287 * going to cost about 7 cycles */
288 rxdp = rxq->rx_ring + rxq->rx_tail;
290 _mm_prefetch((const void *)rxdp, _MM_HINT_T0);
292 /* See if we need to rearm the RX queue - gives the prefetch a bit
294 if (rxq->rxrearm_nb > RTE_IXGBE_RXQ_REARM_THRESH)
295 ixgbe_rxq_rearm(rxq);
297 /* Before we start moving massive data around, check to see if
298 * there is actually a packet available */
299 if (!(rxdp->wb.upper.status_error &
300 rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
303 /* 4 packets DD mask */
304 dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
306 /* 4 packets EOP mask */
307 eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
309 /* mask to shuffle from desc. to mbuf */
311 shuf_msk = _mm_set_epi8(
312 7, 6, 5, 4, /* octet 4~7, 32bits rss */
313 15, 14, /* octet 14~15, low 16 bits vlan_macip */
314 13, 12, /* octet 12~13, 16 bits data_len */
315 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
316 13, 12, /* octet 12~13, low 16 bits pkt_len */
317 0xFF, 0xFF, /* skip high 16 bits pkt_type */
318 1, /* octet 1, 8 bits pkt_type field */
319 0 /* octet 0, 4 bits offset 4 pkt_type field */
322 shuf_msk = _mm_set_epi8(
323 7, 6, 5, 4, /* octet 4~7, 32bits rss */
324 0xFF, 0xFF, /* skip high 16 bits vlan_macip, zero out */
325 15, 14, /* octet 14~15, low 16 bits vlan_macip */
326 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
327 13, 12, /* octet 12~13, low 16 bits pkt_len */
328 13, 12, /* octet 12~13, 16 bits data_len */
329 0xFF, 0xFF /* skip pkt_type field */
331 #endif /* RTE_NEXT_ABI */
333 /* Cache is empty -> need to scan the buffer rings, but first move
334 * the next 'n' mbufs into the cache */
335 sw_ring = &rxq->sw_ring[rxq->rx_tail];
338 /* A. load 4 packet in one loop
339 * [A*. mask out 4 unused dirty field in desc]
340 * B. copy 4 mbuf point from swring to rx_pkts
341 * C. calc the number of DD bits among the 4 packets
342 * [C*. extract the end-of-packet bit, if requested]
343 * D. fill info. from desc to mbuf
346 /* A. load 4 packet in one loop
347 * B. copy 4 mbuf point from swring to rx_pkts
348 * C. calc the number of DD bits among the 4 packets
349 * [C*. extract the end-of-packet bit, if requested]
350 * D. fill info. from desc to mbuf
352 #endif /* RTE_NEXT_ABI */
353 for (pos = 0, nb_pkts_recd = 0; pos < RTE_IXGBE_VPMD_RX_BURST;
354 pos += RTE_IXGBE_DESCS_PER_LOOP,
355 rxdp += RTE_IXGBE_DESCS_PER_LOOP) {
357 __m128i descs0[RTE_IXGBE_DESCS_PER_LOOP];
358 #endif /* RTE_NEXT_ABI */
359 __m128i descs[RTE_IXGBE_DESCS_PER_LOOP];
360 __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
361 __m128i zero, staterr, sterr_tmp1, sterr_tmp2;
362 __m128i mbp1, mbp2; /* two mbuf pointer in one XMM reg. */
365 rte_prefetch0(&rx_pkts[pos]->cacheline1);
366 rte_prefetch0(&rx_pkts[pos + 1]->cacheline1);
367 rte_prefetch0(&rx_pkts[pos + 2]->cacheline1);
368 rte_prefetch0(&rx_pkts[pos + 3]->cacheline1);
371 /* B.1 load 1 mbuf point */
372 mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);
375 /* Read desc statuses backwards to avoid race condition */
376 /* A.1 load 4 pkts desc */
377 descs0[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
379 /* B.2 copy 2 mbuf point into rx_pkts */
380 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
382 /* B.1 load 1 mbuf point */
383 mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos+2]);
385 descs0[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
386 /* B.1 load 2 mbuf point */
387 descs0[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
388 descs0[0] = _mm_loadu_si128((__m128i *)(rxdp));
390 /* B.2 copy 2 mbuf point into rx_pkts */
391 _mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2);
393 /* A* mask out 0~3 bits RSS type */
394 descs[3] = _mm_and_si128(descs0[3], desc_mask);
395 descs[2] = _mm_and_si128(descs0[2], desc_mask);
397 /* A* mask out 0~3 bits RSS type */
398 descs[1] = _mm_and_si128(descs0[1], desc_mask);
399 descs[0] = _mm_and_si128(descs0[0], desc_mask);
401 /* Read desc statuses backwards to avoid race condition */
402 /* A.1 load 4 pkts desc */
403 descs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
405 /* B.2 copy 2 mbuf point into rx_pkts */
406 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
408 /* B.1 load 1 mbuf point */
409 mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos + 2]);
411 descs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
412 /* B.1 load 2 mbuf point */
413 descs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
414 descs[0] = _mm_loadu_si128((__m128i *)(rxdp));
416 /* B.2 copy 2 mbuf point into rx_pkts */
417 _mm_storeu_si128((__m128i *)&rx_pkts[pos + 2], mbp2);
418 #endif /* RTE_NEXT_ABI */
420 /* avoid compiler reorder optimization */
421 rte_compiler_barrier();
423 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
424 pkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk);
425 pkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk);
427 /* C.1 4=>2 filter staterr info only */
428 sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]);
429 /* C.1 4=>2 filter staterr info only */
430 sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]);
433 /* set ol_flags with vlan packet type */
434 desc_to_olflags_v(descs0, &rx_pkts[pos]);
436 /* set ol_flags with packet type and vlan tag */
437 desc_to_olflags_v(descs, &rx_pkts[pos]);
438 #endif /* RTE_NEXT_ABI */
440 /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
441 pkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);
442 pkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);
444 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
445 pkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk);
446 pkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk);
448 /* C.2 get 4 pkts staterr value */
449 zero = _mm_xor_si128(dd_check, dd_check);
450 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
452 /* D.3 copy final 3,4 data to rx_pkts */
453 _mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1,
455 _mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1,
458 /* D.2 pkt 1,2 set in_port/nb_seg and remove crc */
459 pkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);
460 pkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);
462 /* C* extract and record EOP bit */
464 __m128i eop_shuf_mask = _mm_set_epi8(
465 0xFF, 0xFF, 0xFF, 0xFF,
466 0xFF, 0xFF, 0xFF, 0xFF,
467 0xFF, 0xFF, 0xFF, 0xFF,
468 0x04, 0x0C, 0x00, 0x08
471 /* and with mask to extract bits, flipping 1-0 */
472 __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
473 /* the staterr values are not in order, as the count
474 * count of dd bits doesn't care. However, for end of
475 * packet tracking, we do care, so shuffle. This also
476 * compresses the 32-bit values to 8-bit */
477 eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
478 /* store the resulting 32-bit value */
479 *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
480 split_packet += RTE_IXGBE_DESCS_PER_LOOP;
482 /* zero-out next pointers */
483 rx_pkts[pos]->next = NULL;
484 rx_pkts[pos + 1]->next = NULL;
485 rx_pkts[pos + 2]->next = NULL;
486 rx_pkts[pos + 3]->next = NULL;
489 /* C.3 calc available number of desc */
490 staterr = _mm_and_si128(staterr, dd_check);
491 staterr = _mm_packs_epi32(staterr, zero);
493 /* D.3 copy final 1,2 data to rx_pkts */
494 _mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1,
496 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
499 /* C.4 calc avaialbe number of desc */
500 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
502 if (likely(var != RTE_IXGBE_DESCS_PER_LOOP))
506 /* Update our internal tail pointer */
507 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
508 rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
509 rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
515 * vPMD receive routine, now only accept (nb_pkts == RTE_IXGBE_VPMD_RX_BURST)
519 * - nb_pkts < RTE_IXGBE_VPMD_RX_BURST, just return no packet
520 * - nb_pkts > RTE_IXGBE_VPMD_RX_BURST, only scan RTE_IXGBE_VPMD_RX_BURST
522 * - don't support ol_flags for rss and csum err
525 ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
528 return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
531 static inline uint16_t
532 reassemble_packets(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_bufs,
533 uint16_t nb_bufs, uint8_t *split_flags)
535 struct rte_mbuf *pkts[RTE_IXGBE_VPMD_RX_BURST]; /*finished pkts*/
536 struct rte_mbuf *start = rxq->pkt_first_seg;
537 struct rte_mbuf *end = rxq->pkt_last_seg;
538 unsigned pkt_idx, buf_idx;
541 for (buf_idx = 0, pkt_idx = 0; buf_idx < nb_bufs; buf_idx++) {
543 /* processing a split packet */
544 end->next = rx_bufs[buf_idx];
545 rx_bufs[buf_idx]->data_len += rxq->crc_len;
548 start->pkt_len += rx_bufs[buf_idx]->data_len;
551 if (!split_flags[buf_idx]) {
552 /* it's the last packet of the set */
553 start->hash = end->hash;
554 start->ol_flags = end->ol_flags;
555 /* we need to strip crc for the whole packet */
556 start->pkt_len -= rxq->crc_len;
557 if (end->data_len > rxq->crc_len)
558 end->data_len -= rxq->crc_len;
560 /* free up last mbuf */
561 struct rte_mbuf *secondlast = start;
564 while (secondlast->next != end)
565 secondlast = secondlast->next;
566 secondlast->data_len -= (rxq->crc_len -
568 secondlast->next = NULL;
569 rte_pktmbuf_free_seg(end);
572 pkts[pkt_idx++] = start;
576 /* not processing a split packet */
577 if (!split_flags[buf_idx]) {
578 /* not a split packet, save and skip */
579 pkts[pkt_idx++] = rx_bufs[buf_idx];
582 end = start = rx_bufs[buf_idx];
583 rx_bufs[buf_idx]->data_len += rxq->crc_len;
584 rx_bufs[buf_idx]->pkt_len += rxq->crc_len;
588 /* save the partial packet for next time */
589 rxq->pkt_first_seg = start;
590 rxq->pkt_last_seg = end;
591 memcpy(rx_bufs, pkts, pkt_idx * (sizeof(*pkts)));
596 * vPMD receive routine that reassembles scattered packets
599 * - don't support ol_flags for rss and csum err
600 * - now only accept (nb_pkts == RTE_IXGBE_VPMD_RX_BURST)
603 ixgbe_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
606 struct ixgbe_rx_queue *rxq = rx_queue;
607 uint8_t split_flags[RTE_IXGBE_VPMD_RX_BURST] = {0};
609 /* get some new buffers */
610 uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
615 /* happy day case, full burst + no packets to be joined */
616 const uint64_t *split_fl64 = (uint64_t *)split_flags;
617 if (rxq->pkt_first_seg == NULL &&
618 split_fl64[0] == 0 && split_fl64[1] == 0 &&
619 split_fl64[2] == 0 && split_fl64[3] == 0)
622 /* reassemble any packets that need reassembly*/
624 if (rxq->pkt_first_seg == NULL) {
625 /* find the first split flag, and only reassemble then*/
626 while (i < nb_bufs && !split_flags[i])
631 return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
636 vtx1(volatile union ixgbe_adv_tx_desc *txdp,
637 struct rte_mbuf *pkt, uint64_t flags)
639 __m128i descriptor = _mm_set_epi64x((uint64_t)pkt->pkt_len << 46 |
640 flags | pkt->data_len,
641 pkt->buf_physaddr + pkt->data_off);
642 _mm_store_si128((__m128i *)&txdp->read, descriptor);
646 vtx(volatile union ixgbe_adv_tx_desc *txdp,
647 struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags)
650 for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
651 vtx1(txdp, *pkt, flags);
654 static inline int __attribute__((always_inline))
655 ixgbe_tx_free_bufs(struct ixgbe_tx_queue *txq)
657 struct ixgbe_tx_entry_v *txep;
662 struct rte_mbuf *m, *free[RTE_IXGBE_TX_MAX_FREE_BUF_SZ];
664 /* check DD bit on threshold descriptor */
665 status = txq->tx_ring[txq->tx_next_dd].wb.status;
666 if (!(status & IXGBE_ADVTXD_STAT_DD))
669 n = txq->tx_rs_thresh;
672 * first buffer to free from S/W ring is at index
673 * tx_next_dd - (tx_rs_thresh-1)
675 txep = &txq->sw_ring_v[txq->tx_next_dd - (n - 1)];
676 m = __rte_pktmbuf_prefree_seg(txep[0].mbuf);
677 if (likely(m != NULL)) {
680 for (i = 1; i < n; i++) {
681 m = __rte_pktmbuf_prefree_seg(txep[i].mbuf);
682 if (likely(m != NULL)) {
683 if (likely(m->pool == free[0]->pool))
686 rte_mempool_put_bulk(free[0]->pool,
687 (void *)free, nb_free);
693 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
695 for (i = 1; i < n; i++) {
696 m = __rte_pktmbuf_prefree_seg(txep[i].mbuf);
698 rte_mempool_put(m->pool, m);
702 /* buffers were freed, update counters */
703 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
704 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
705 if (txq->tx_next_dd >= txq->nb_tx_desc)
706 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
708 return txq->tx_rs_thresh;
711 static inline void __attribute__((always_inline))
712 tx_backlog_entry(struct ixgbe_tx_entry_v *txep,
713 struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
716 for (i = 0; i < (int)nb_pkts; ++i)
717 txep[i].mbuf = tx_pkts[i];
721 ixgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
724 struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
725 volatile union ixgbe_adv_tx_desc *txdp;
726 struct ixgbe_tx_entry_v *txep;
727 uint16_t n, nb_commit, tx_id;
728 uint64_t flags = DCMD_DTYP_FLAGS;
729 uint64_t rs = IXGBE_ADVTXD_DCMD_RS|DCMD_DTYP_FLAGS;
732 if (unlikely(nb_pkts > RTE_IXGBE_VPMD_TX_BURST))
733 nb_pkts = RTE_IXGBE_VPMD_TX_BURST;
735 if (txq->nb_tx_free < txq->tx_free_thresh)
736 ixgbe_tx_free_bufs(txq);
738 nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
739 if (unlikely(nb_pkts == 0))
742 tx_id = txq->tx_tail;
743 txdp = &txq->tx_ring[tx_id];
744 txep = &txq->sw_ring_v[tx_id];
746 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
748 n = (uint16_t)(txq->nb_tx_desc - tx_id);
749 if (nb_commit >= n) {
751 tx_backlog_entry(txep, tx_pkts, n);
753 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
754 vtx1(txdp, *tx_pkts, flags);
756 vtx1(txdp, *tx_pkts++, rs);
758 nb_commit = (uint16_t)(nb_commit - n);
761 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
763 /* avoid reach the end of ring */
764 txdp = &(txq->tx_ring[tx_id]);
765 txep = &txq->sw_ring_v[tx_id];
768 tx_backlog_entry(txep, tx_pkts, nb_commit);
770 vtx(txdp, tx_pkts, nb_commit, flags);
772 tx_id = (uint16_t)(tx_id + nb_commit);
773 if (tx_id > txq->tx_next_rs) {
774 txq->tx_ring[txq->tx_next_rs].read.cmd_type_len |=
775 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
776 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
780 txq->tx_tail = tx_id;
782 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
787 static void __attribute__((cold))
788 ixgbe_tx_queue_release_mbufs_vec(struct ixgbe_tx_queue *txq)
791 struct ixgbe_tx_entry_v *txe;
792 const uint16_t max_desc = (uint16_t)(txq->nb_tx_desc - 1);
794 if (txq->sw_ring == NULL || txq->nb_tx_free == max_desc)
797 /* release the used mbufs in sw_ring */
798 for (i = txq->tx_next_dd - (txq->tx_rs_thresh - 1);
800 i = (i + 1) & max_desc) {
801 txe = &txq->sw_ring_v[i];
802 rte_pktmbuf_free_seg(txe->mbuf);
804 txq->nb_tx_free = max_desc;
807 for (i = 0; i < txq->nb_tx_desc; i++) {
808 txe = &txq->sw_ring_v[i];
813 void __attribute__((cold))
814 ixgbe_rx_queue_release_mbufs_vec(struct ixgbe_rx_queue *rxq)
816 const unsigned mask = rxq->nb_rx_desc - 1;
819 if (rxq->sw_ring == NULL || rxq->rxrearm_nb >= rxq->nb_rx_desc)
822 /* free all mbufs that are valid in the ring */
823 for (i = rxq->rx_tail; i != rxq->rxrearm_start; i = (i + 1) & mask)
824 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
825 rxq->rxrearm_nb = rxq->nb_rx_desc;
827 /* set all entries to NULL */
828 memset(rxq->sw_ring, 0, sizeof(rxq->sw_ring[0]) * rxq->nb_rx_desc);
831 static void __attribute__((cold))
832 ixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)
837 if (txq->sw_ring != NULL) {
838 rte_free(txq->sw_ring_v - 1);
839 txq->sw_ring_v = NULL;
843 static void __attribute__((cold))
844 ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)
846 static const union ixgbe_adv_tx_desc zeroed_desc = {{0}};
847 struct ixgbe_tx_entry_v *txe = txq->sw_ring_v;
850 /* Zero out HW ring memory */
851 for (i = 0; i < txq->nb_tx_desc; i++)
852 txq->tx_ring[i] = zeroed_desc;
854 /* Initialize SW ring entries */
855 for (i = 0; i < txq->nb_tx_desc; i++) {
856 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
857 txd->wb.status = IXGBE_TXD_STAT_DD;
861 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
862 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
867 * Always allow 1 descriptor to be un-allocated to avoid
868 * a H/W race condition
870 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
871 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
873 memset((void *)&txq->ctx_cache, 0,
874 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
877 static const struct ixgbe_txq_ops vec_txq_ops = {
878 .release_mbufs = ixgbe_tx_queue_release_mbufs_vec,
879 .free_swring = ixgbe_tx_free_swring,
880 .reset = ixgbe_reset_tx_queue,
883 int __attribute__((cold))
884 ixgbe_rxq_vec_setup(struct ixgbe_rx_queue *rxq)
887 struct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */
890 mb_def.data_off = RTE_PKTMBUF_HEADROOM;
891 mb_def.port = rxq->port_id;
892 rte_mbuf_refcnt_set(&mb_def, 1);
894 /* prevent compiler reordering: rearm_data covers previous fields */
895 rte_compiler_barrier();
896 p = (uintptr_t)&mb_def.rearm_data;
897 rxq->mbuf_initializer = *(uint64_t *)p;
901 int __attribute__((cold))
902 ixgbe_txq_vec_setup(struct ixgbe_tx_queue *txq)
904 if (txq->sw_ring_v == NULL)
907 /* leave the first one for overflow */
908 txq->sw_ring_v = txq->sw_ring_v + 1;
909 txq->ops = &vec_txq_ops;
914 int __attribute__((cold))
915 ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev)
917 #ifndef RTE_LIBRTE_IEEE1588
918 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
919 struct rte_fdir_conf *fconf = &dev->data->dev_conf.fdir_conf;
921 #ifndef RTE_IXGBE_RX_OLFLAGS_ENABLE
922 /* whithout rx ol_flags, no VP flag report */
923 if (rxmode->hw_vlan_strip != 0 ||
924 rxmode->hw_vlan_extend != 0)
928 /* no fdir support */
929 if (fconf->mode != RTE_FDIR_MODE_NONE)
933 * - no csum error report support
934 * - no header split support
936 if (rxmode->hw_ip_checksum == 1 ||
937 rxmode->header_split == 1)