4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <rte_ethdev.h>
36 #include <rte_malloc.h>
38 #include "ixgbe_ethdev.h"
39 #include "ixgbe_rxtx.h"
40 #include "ixgbe_rxtx_vec_common.h"
42 #include <tmmintrin.h>
44 #ifndef __INTEL_COMPILER
45 #pragma GCC diagnostic ignored "-Wcast-qual"
49 ixgbe_rxq_rearm(struct ixgbe_rx_queue *rxq)
53 volatile union ixgbe_adv_rx_desc *rxdp;
54 struct ixgbe_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
55 struct rte_mbuf *mb0, *mb1;
56 __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
57 RTE_PKTMBUF_HEADROOM);
58 __m128i dma_addr0, dma_addr1;
60 const __m128i hba_msk = _mm_set_epi64x(0, UINT64_MAX);
62 rxdp = rxq->rx_ring + rxq->rxrearm_start;
64 /* Pull 'n' more MBUFs into the software ring */
65 if (rte_mempool_get_bulk(rxq->mb_pool,
67 RTE_IXGBE_RXQ_REARM_THRESH) < 0) {
68 if (rxq->rxrearm_nb + RTE_IXGBE_RXQ_REARM_THRESH >=
70 dma_addr0 = _mm_setzero_si128();
71 for (i = 0; i < RTE_IXGBE_DESCS_PER_LOOP; i++) {
72 rxep[i].mbuf = &rxq->fake_mbuf;
73 _mm_store_si128((__m128i *)&rxdp[i].read,
77 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
78 RTE_IXGBE_RXQ_REARM_THRESH;
82 /* Initialize the mbufs in vector, process 2 mbufs in one loop */
83 for (i = 0; i < RTE_IXGBE_RXQ_REARM_THRESH; i += 2, rxep += 2) {
84 __m128i vaddr0, vaddr1;
91 * Flush mbuf with pkt template.
92 * Data to be rearmed is 6 bytes long.
93 * Though, RX will overwrite ol_flags that are coming next
94 * anyway. So overwrite whole 8 bytes with one load:
95 * 6 bytes of rearm_data plus first 2 bytes of ol_flags.
97 p0 = (uintptr_t)&mb0->rearm_data;
98 *(uint64_t *)p0 = rxq->mbuf_initializer;
99 p1 = (uintptr_t)&mb1->rearm_data;
100 *(uint64_t *)p1 = rxq->mbuf_initializer;
102 /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */
103 vaddr0 = _mm_loadu_si128((__m128i *)&(mb0->buf_addr));
104 vaddr1 = _mm_loadu_si128((__m128i *)&(mb1->buf_addr));
106 /* convert pa to dma_addr hdr/data */
107 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
108 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
110 /* add headroom to pa values */
111 dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
112 dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
114 /* set Header Buffer Address to zero */
115 dma_addr0 = _mm_and_si128(dma_addr0, hba_msk);
116 dma_addr1 = _mm_and_si128(dma_addr1, hba_msk);
118 /* flush desc with pa dma_addr */
119 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
120 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
123 rxq->rxrearm_start += RTE_IXGBE_RXQ_REARM_THRESH;
124 if (rxq->rxrearm_start >= rxq->nb_rx_desc)
125 rxq->rxrearm_start = 0;
127 rxq->rxrearm_nb -= RTE_IXGBE_RXQ_REARM_THRESH;
129 rx_id = (uint16_t) ((rxq->rxrearm_start == 0) ?
130 (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
132 /* Update the tail pointer on the NIC */
133 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
136 /* Handling the offload flags (olflags) field takes computation
137 * time when receiving packets. Therefore we provide a flag to disable
138 * the processing of the olflags field when they are not needed. This
139 * gives improved performance, at the cost of losing the offload info
140 * in the received packet
142 #ifdef RTE_IXGBE_RX_OLFLAGS_ENABLE
145 desc_to_olflags_v(__m128i descs[4], uint8_t vlan_flags,
146 struct rte_mbuf **rx_pkts)
148 __m128i ptype0, ptype1, vtag0, vtag1, csum;
154 /* mask everything except rss type */
155 const __m128i rsstype_msk = _mm_set_epi16(
156 0x0000, 0x0000, 0x0000, 0x0000,
157 0x000F, 0x000F, 0x000F, 0x000F);
159 /* map rss type to rss hash flag */
160 const __m128i rss_flags = _mm_set_epi8(PKT_RX_FDIR, 0, 0, 0,
161 0, 0, 0, PKT_RX_RSS_HASH,
162 PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH, 0,
163 PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, 0);
165 /* mask everything except vlan present and l4/ip csum error */
166 const __m128i vlan_csum_msk = _mm_set_epi16(
167 (IXGBE_RXDADV_ERR_TCPE | IXGBE_RXDADV_ERR_IPE) >> 16,
168 (IXGBE_RXDADV_ERR_TCPE | IXGBE_RXDADV_ERR_IPE) >> 16,
169 (IXGBE_RXDADV_ERR_TCPE | IXGBE_RXDADV_ERR_IPE) >> 16,
170 (IXGBE_RXDADV_ERR_TCPE | IXGBE_RXDADV_ERR_IPE) >> 16,
171 IXGBE_RXD_STAT_VP, IXGBE_RXD_STAT_VP,
172 IXGBE_RXD_STAT_VP, IXGBE_RXD_STAT_VP);
173 /* map vlan present (0x8), IPE (0x2), L4E (0x1) to ol_flags */
174 const __m128i vlan_csum_map = _mm_set_epi8(
176 vlan_flags | PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD,
177 vlan_flags | PKT_RX_IP_CKSUM_BAD,
178 vlan_flags | PKT_RX_L4_CKSUM_BAD,
181 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD,
186 ptype0 = _mm_unpacklo_epi16(descs[0], descs[1]);
187 ptype1 = _mm_unpacklo_epi16(descs[2], descs[3]);
188 vtag0 = _mm_unpackhi_epi16(descs[0], descs[1]);
189 vtag1 = _mm_unpackhi_epi16(descs[2], descs[3]);
191 ptype0 = _mm_unpacklo_epi32(ptype0, ptype1);
192 ptype0 = _mm_and_si128(ptype0, rsstype_msk);
193 ptype0 = _mm_shuffle_epi8(rss_flags, ptype0);
195 vtag1 = _mm_unpacklo_epi32(vtag0, vtag1);
196 vtag1 = _mm_and_si128(vtag1, vlan_csum_msk);
198 /* csum bits are in the most significant, to use shuffle we need to
199 * shift them. Change mask to 0xc000 to 0x0003.
201 csum = _mm_srli_epi16(vtag1, 14);
203 /* now or the most significant 64 bits containing the checksum
204 * flags with the vlan present flags.
206 csum = _mm_srli_si128(csum, 8);
207 vtag1 = _mm_or_si128(csum, vtag1);
209 /* convert VP, IPE, L4E to ol_flags */
210 vtag1 = _mm_shuffle_epi8(vlan_csum_map, vtag1);
212 vtag1 = _mm_or_si128(ptype0, vtag1);
213 vol.dword = _mm_cvtsi128_si64(vtag1);
215 rx_pkts[0]->ol_flags = vol.e[0];
216 rx_pkts[1]->ol_flags = vol.e[1];
217 rx_pkts[2]->ol_flags = vol.e[2];
218 rx_pkts[3]->ol_flags = vol.e[3];
221 #define desc_to_olflags_v(desc, vlan_flags, rx_pkts) do { \
222 RTE_SET_USED(vlan_flags); \
227 * vPMD raw receive routine, only accept(nb_pkts >= RTE_IXGBE_DESCS_PER_LOOP)
230 * - nb_pkts < RTE_IXGBE_DESCS_PER_LOOP, just return no packet
231 * - nb_pkts > RTE_IXGBE_MAX_RX_BURST, only scan RTE_IXGBE_MAX_RX_BURST
233 * - floor align nb_pkts to a RTE_IXGBE_DESC_PER_LOOP power-of-two
235 static inline uint16_t
236 _recv_raw_pkts_vec(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
237 uint16_t nb_pkts, uint8_t *split_packet)
239 volatile union ixgbe_adv_rx_desc *rxdp;
240 struct ixgbe_rx_entry *sw_ring;
241 uint16_t nb_pkts_recd;
245 __m128i crc_adjust = _mm_set_epi16(
246 0, 0, 0, /* ignore non-length fields */
247 -rxq->crc_len, /* sub crc on data_len */
248 0, /* ignore high-16bits of pkt_len */
249 -rxq->crc_len, /* sub crc on pkt_len */
250 0, 0 /* ignore pkt_type field */
252 __m128i dd_check, eop_check;
255 /* nb_pkts shall be less equal than RTE_IXGBE_MAX_RX_BURST */
256 nb_pkts = RTE_MIN(nb_pkts, RTE_IXGBE_MAX_RX_BURST);
258 /* nb_pkts has to be floor-aligned to RTE_IXGBE_DESCS_PER_LOOP */
259 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_IXGBE_DESCS_PER_LOOP);
261 /* Just the act of getting into the function from the application is
262 * going to cost about 7 cycles
264 rxdp = rxq->rx_ring + rxq->rx_tail;
268 /* See if we need to rearm the RX queue - gives the prefetch a bit
271 if (rxq->rxrearm_nb > RTE_IXGBE_RXQ_REARM_THRESH)
272 ixgbe_rxq_rearm(rxq);
274 /* Before we start moving massive data around, check to see if
275 * there is actually a packet available
277 if (!(rxdp->wb.upper.status_error &
278 rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
281 /* 4 packets DD mask */
282 dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
284 /* 4 packets EOP mask */
285 eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
287 /* mask to shuffle from desc. to mbuf */
288 shuf_msk = _mm_set_epi8(
289 7, 6, 5, 4, /* octet 4~7, 32bits rss */
290 15, 14, /* octet 14~15, low 16 bits vlan_macip */
291 13, 12, /* octet 12~13, 16 bits data_len */
292 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
293 13, 12, /* octet 12~13, low 16 bits pkt_len */
294 0xFF, 0xFF, /* skip 32 bit pkt_type */
298 /* Cache is empty -> need to scan the buffer rings, but first move
299 * the next 'n' mbufs into the cache
301 sw_ring = &rxq->sw_ring[rxq->rx_tail];
303 /* ensure these 2 flags are in the lower 8 bits */
304 RTE_BUILD_BUG_ON((PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED) > UINT8_MAX);
305 vlan_flags = rxq->vlan_flags & UINT8_MAX;
307 /* A. load 4 packet in one loop
308 * [A*. mask out 4 unused dirty field in desc]
309 * B. copy 4 mbuf point from swring to rx_pkts
310 * C. calc the number of DD bits among the 4 packets
311 * [C*. extract the end-of-packet bit, if requested]
312 * D. fill info. from desc to mbuf
314 for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
315 pos += RTE_IXGBE_DESCS_PER_LOOP,
316 rxdp += RTE_IXGBE_DESCS_PER_LOOP) {
317 __m128i descs[RTE_IXGBE_DESCS_PER_LOOP];
318 __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
319 __m128i zero, staterr, sterr_tmp1, sterr_tmp2;
320 __m128i mbp1, mbp2; /* two mbuf pointer in one XMM reg. */
322 /* B.1 load 1 mbuf point */
323 mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);
325 /* Read desc statuses backwards to avoid race condition */
326 /* A.1 load 4 pkts desc */
327 descs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
329 /* B.2 copy 2 mbuf point into rx_pkts */
330 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
332 /* B.1 load 1 mbuf point */
333 mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos+2]);
335 descs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
336 /* B.1 load 2 mbuf point */
337 descs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
338 descs[0] = _mm_loadu_si128((__m128i *)(rxdp));
340 /* B.2 copy 2 mbuf point into rx_pkts */
341 _mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2);
344 rte_mbuf_prefetch_part2(rx_pkts[pos]);
345 rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
346 rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
347 rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
350 /* avoid compiler reorder optimization */
351 rte_compiler_barrier();
353 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
354 pkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk);
355 pkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk);
357 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
358 pkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk);
359 pkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk);
361 /* C.1 4=>2 filter staterr info only */
362 sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]);
363 /* C.1 4=>2 filter staterr info only */
364 sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]);
366 /* set ol_flags with vlan packet type */
367 desc_to_olflags_v(descs, vlan_flags, &rx_pkts[pos]);
369 /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
370 pkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);
371 pkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);
373 /* C.2 get 4 pkts staterr value */
374 zero = _mm_xor_si128(dd_check, dd_check);
375 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
377 /* D.3 copy final 3,4 data to rx_pkts */
378 _mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1,
380 _mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1,
383 /* D.2 pkt 1,2 set in_port/nb_seg and remove crc */
384 pkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);
385 pkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);
387 /* C* extract and record EOP bit */
389 __m128i eop_shuf_mask = _mm_set_epi8(
390 0xFF, 0xFF, 0xFF, 0xFF,
391 0xFF, 0xFF, 0xFF, 0xFF,
392 0xFF, 0xFF, 0xFF, 0xFF,
393 0x04, 0x0C, 0x00, 0x08
396 /* and with mask to extract bits, flipping 1-0 */
397 __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
398 /* the staterr values are not in order, as the count
399 * count of dd bits doesn't care. However, for end of
400 * packet tracking, we do care, so shuffle. This also
401 * compresses the 32-bit values to 8-bit
403 eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
404 /* store the resulting 32-bit value */
405 *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
406 split_packet += RTE_IXGBE_DESCS_PER_LOOP;
408 /* zero-out next pointers */
409 rx_pkts[pos]->next = NULL;
410 rx_pkts[pos + 1]->next = NULL;
411 rx_pkts[pos + 2]->next = NULL;
412 rx_pkts[pos + 3]->next = NULL;
415 /* C.3 calc available number of desc */
416 staterr = _mm_and_si128(staterr, dd_check);
417 staterr = _mm_packs_epi32(staterr, zero);
419 /* D.3 copy final 1,2 data to rx_pkts */
420 _mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1,
422 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
425 /* C.4 calc avaialbe number of desc */
426 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
428 if (likely(var != RTE_IXGBE_DESCS_PER_LOOP))
432 /* Update our internal tail pointer */
433 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
434 rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
435 rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
441 * vPMD receive routine, only accept(nb_pkts >= RTE_IXGBE_DESCS_PER_LOOP)
444 * - nb_pkts < RTE_IXGBE_DESCS_PER_LOOP, just return no packet
445 * - nb_pkts > RTE_IXGBE_MAX_RX_BURST, only scan RTE_IXGBE_MAX_RX_BURST
447 * - floor align nb_pkts to a RTE_IXGBE_DESC_PER_LOOP power-of-two
450 ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
453 return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
457 * vPMD receive routine that reassembles scattered packets
460 * - nb_pkts < RTE_IXGBE_DESCS_PER_LOOP, just return no packet
461 * - nb_pkts > RTE_IXGBE_MAX_RX_BURST, only scan RTE_IXGBE_MAX_RX_BURST
463 * - floor align nb_pkts to a RTE_IXGBE_DESC_PER_LOOP power-of-two
466 ixgbe_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
469 struct ixgbe_rx_queue *rxq = rx_queue;
470 uint8_t split_flags[RTE_IXGBE_MAX_RX_BURST] = {0};
472 /* get some new buffers */
473 uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
478 /* happy day case, full burst + no packets to be joined */
479 const uint64_t *split_fl64 = (uint64_t *)split_flags;
480 if (rxq->pkt_first_seg == NULL &&
481 split_fl64[0] == 0 && split_fl64[1] == 0 &&
482 split_fl64[2] == 0 && split_fl64[3] == 0)
485 /* reassemble any packets that need reassembly*/
487 if (rxq->pkt_first_seg == NULL) {
488 /* find the first split flag, and only reassemble then*/
489 while (i < nb_bufs && !split_flags[i])
494 return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
499 vtx1(volatile union ixgbe_adv_tx_desc *txdp,
500 struct rte_mbuf *pkt, uint64_t flags)
502 __m128i descriptor = _mm_set_epi64x((uint64_t)pkt->pkt_len << 46 |
503 flags | pkt->data_len,
504 pkt->buf_physaddr + pkt->data_off);
505 _mm_store_si128((__m128i *)&txdp->read, descriptor);
509 vtx(volatile union ixgbe_adv_tx_desc *txdp,
510 struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags)
514 for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
515 vtx1(txdp, *pkt, flags);
519 ixgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
522 struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
523 volatile union ixgbe_adv_tx_desc *txdp;
524 struct ixgbe_tx_entry_v *txep;
525 uint16_t n, nb_commit, tx_id;
526 uint64_t flags = DCMD_DTYP_FLAGS;
527 uint64_t rs = IXGBE_ADVTXD_DCMD_RS|DCMD_DTYP_FLAGS;
530 /* cross rx_thresh boundary is not allowed */
531 nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
533 if (txq->nb_tx_free < txq->tx_free_thresh)
534 ixgbe_tx_free_bufs(txq);
536 nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
537 if (unlikely(nb_pkts == 0))
540 tx_id = txq->tx_tail;
541 txdp = &txq->tx_ring[tx_id];
542 txep = &txq->sw_ring_v[tx_id];
544 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
546 n = (uint16_t)(txq->nb_tx_desc - tx_id);
547 if (nb_commit >= n) {
549 tx_backlog_entry(txep, tx_pkts, n);
551 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
552 vtx1(txdp, *tx_pkts, flags);
554 vtx1(txdp, *tx_pkts++, rs);
556 nb_commit = (uint16_t)(nb_commit - n);
559 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
561 /* avoid reach the end of ring */
562 txdp = &(txq->tx_ring[tx_id]);
563 txep = &txq->sw_ring_v[tx_id];
566 tx_backlog_entry(txep, tx_pkts, nb_commit);
568 vtx(txdp, tx_pkts, nb_commit, flags);
570 tx_id = (uint16_t)(tx_id + nb_commit);
571 if (tx_id > txq->tx_next_rs) {
572 txq->tx_ring[txq->tx_next_rs].read.cmd_type_len |=
573 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
574 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
578 txq->tx_tail = tx_id;
580 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
585 static void __attribute__((cold))
586 ixgbe_tx_queue_release_mbufs_vec(struct ixgbe_tx_queue *txq)
588 _ixgbe_tx_queue_release_mbufs_vec(txq);
591 void __attribute__((cold))
592 ixgbe_rx_queue_release_mbufs_vec(struct ixgbe_rx_queue *rxq)
594 _ixgbe_rx_queue_release_mbufs_vec(rxq);
597 static void __attribute__((cold))
598 ixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)
600 _ixgbe_tx_free_swring_vec(txq);
603 static void __attribute__((cold))
604 ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)
606 _ixgbe_reset_tx_queue_vec(txq);
609 static const struct ixgbe_txq_ops vec_txq_ops = {
610 .release_mbufs = ixgbe_tx_queue_release_mbufs_vec,
611 .free_swring = ixgbe_tx_free_swring,
612 .reset = ixgbe_reset_tx_queue,
615 int __attribute__((cold))
616 ixgbe_rxq_vec_setup(struct ixgbe_rx_queue *rxq)
618 return ixgbe_rxq_vec_setup_default(rxq);
621 int __attribute__((cold))
622 ixgbe_txq_vec_setup(struct ixgbe_tx_queue *txq)
624 return ixgbe_txq_vec_setup_default(txq, &vec_txq_ops);
627 int __attribute__((cold))
628 ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev)
630 return ixgbe_rx_vec_dev_conf_condition_check_default(dev);