4 * Copyright(c) 2017 Cavium, Inc.. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Cavium, Inc. nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER(S) OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <rte_ethdev.h>
35 #include <rte_cycles.h>
36 #include <rte_malloc.h>
39 #include "lio_23xx_vf.h"
40 #include "lio_23xx_reg.h"
43 cn23xx_vf_reset_io_queues(struct lio_device *lio_dev, uint32_t num_queues)
45 uint32_t loop = CN23XX_VF_BUSY_READING_REG_LOOP_COUNT;
49 PMD_INIT_FUNC_TRACE();
51 for (q_no = 0; q_no < num_queues; q_no++) {
52 /* set RST bit to 1. This bit applies to both IQ and OQ */
53 d64 = lio_read_csr64(lio_dev,
54 CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
55 d64 = d64 | CN23XX_PKT_INPUT_CTL_RST;
56 lio_write_csr64(lio_dev, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
60 /* wait until the RST bit is clear or the RST and QUIET bits are set */
61 for (q_no = 0; q_no < num_queues; q_no++) {
62 volatile uint64_t reg_val;
64 reg_val = lio_read_csr64(lio_dev,
65 CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
66 while ((reg_val & CN23XX_PKT_INPUT_CTL_RST) &&
67 !(reg_val & CN23XX_PKT_INPUT_CTL_QUIET) &&
69 reg_val = lio_read_csr64(
71 CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
77 "clearing the reset reg failed or setting the quiet reg failed for qno: %lu\n",
82 reg_val = reg_val & ~CN23XX_PKT_INPUT_CTL_RST;
83 lio_write_csr64(lio_dev, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
86 reg_val = lio_read_csr64(
87 lio_dev, CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
88 if (reg_val & CN23XX_PKT_INPUT_CTL_RST) {
90 "clearing the reset failed for qno: %lu\n",
100 cn23xx_vf_setup_global_input_regs(struct lio_device *lio_dev)
105 PMD_INIT_FUNC_TRACE();
107 if (cn23xx_vf_reset_io_queues(lio_dev,
108 lio_dev->sriov_info.rings_per_vf))
111 for (q_no = 0; q_no < (lio_dev->sriov_info.rings_per_vf); q_no++) {
112 lio_write_csr64(lio_dev, CN23XX_SLI_IQ_DOORBELL(q_no),
115 d64 = lio_read_csr64(lio_dev,
116 CN23XX_SLI_IQ_INSTR_COUNT64(q_no));
118 d64 &= 0xEFFFFFFFFFFFFFFFL;
120 lio_write_csr64(lio_dev, CN23XX_SLI_IQ_INSTR_COUNT64(q_no),
123 /* Select ES, RO, NS, RDSIZE,DPTR Fomat#0 for
126 lio_write_csr64(lio_dev, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
127 CN23XX_PKT_INPUT_CTL_MASK);
134 cn23xx_vf_setup_global_output_regs(struct lio_device *lio_dev)
139 PMD_INIT_FUNC_TRACE();
141 for (q_no = 0; q_no < lio_dev->sriov_info.rings_per_vf; q_no++) {
142 lio_write_csr(lio_dev, CN23XX_SLI_OQ_PKTS_CREDIT(q_no),
146 lio_read_csr(lio_dev, CN23XX_SLI_OQ_PKTS_SENT(q_no));
148 reg_val &= 0xEFFFFFFFFFFFFFFFL;
151 lio_read_csr(lio_dev, CN23XX_SLI_OQ_PKT_CONTROL(q_no));
153 /* set IPTR & DPTR */
155 (CN23XX_PKT_OUTPUT_CTL_IPTR | CN23XX_PKT_OUTPUT_CTL_DPTR);
158 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_BMODE);
160 /* No Relaxed Ordering, No Snoop, 64-bit Byte swap
161 * for Output Queue Scatter List
164 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR_P);
165 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR_P);
167 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
168 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ES_P);
169 #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN
170 reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES_P);
172 /* No Relaxed Ordering, No Snoop, 64-bit Byte swap
173 * for Output Queue Data
176 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR);
177 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR);
179 reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES);
181 /* write all the selected settings */
182 lio_write_csr(lio_dev, CN23XX_SLI_OQ_PKT_CONTROL(q_no),
188 cn23xx_vf_setup_device_regs(struct lio_device *lio_dev)
190 PMD_INIT_FUNC_TRACE();
192 if (cn23xx_vf_setup_global_input_regs(lio_dev))
195 cn23xx_vf_setup_global_output_regs(lio_dev);
201 cn23xx_vf_setup_device(struct lio_device *lio_dev)
205 PMD_INIT_FUNC_TRACE();
207 /* INPUT_CONTROL[RPVF] gives the VF IOq count */
208 reg_val = lio_read_csr64(lio_dev, CN23XX_SLI_IQ_PKT_CONTROL64(0));
210 lio_dev->pf_num = (reg_val >> CN23XX_PKT_INPUT_CTL_PF_NUM_POS) &
211 CN23XX_PKT_INPUT_CTL_PF_NUM_MASK;
212 lio_dev->vf_num = (reg_val >> CN23XX_PKT_INPUT_CTL_VF_NUM_POS) &
213 CN23XX_PKT_INPUT_CTL_VF_NUM_MASK;
215 reg_val = reg_val >> CN23XX_PKT_INPUT_CTL_RPVF_POS;
217 lio_dev->sriov_info.rings_per_vf =
218 reg_val & CN23XX_PKT_INPUT_CTL_RPVF_MASK;
220 lio_dev->default_config = lio_get_conf(lio_dev);
221 if (lio_dev->default_config == NULL)
224 lio_dev->fn_list.setup_device_regs = cn23xx_vf_setup_device_regs;
230 cn23xx_vf_set_io_queues_off(struct lio_device *lio_dev)
232 uint32_t loop = CN23XX_VF_BUSY_READING_REG_LOOP_COUNT;
235 /* Disable the i/p and o/p queues for this Octeon.
236 * IOQs will already be in reset.
237 * If RST bit is set, wait for Quiet bit to be set
238 * Once Quiet bit is set, clear the RST bit
240 PMD_INIT_FUNC_TRACE();
242 for (q_no = 0; q_no < lio_dev->sriov_info.rings_per_vf; q_no++) {
243 volatile uint64_t reg_val;
245 reg_val = lio_read_csr64(lio_dev,
246 CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
247 while ((reg_val & CN23XX_PKT_INPUT_CTL_RST) && !(reg_val &
248 CN23XX_PKT_INPUT_CTL_QUIET) && loop) {
249 reg_val = lio_read_csr64(
251 CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
257 "clearing the reset reg failed or setting the quiet reg failed for qno %lu\n",
258 (unsigned long)q_no);
262 reg_val = reg_val & ~CN23XX_PKT_INPUT_CTL_RST;
263 lio_write_csr64(lio_dev, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
266 reg_val = lio_read_csr64(lio_dev,
267 CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
268 if (reg_val & CN23XX_PKT_INPUT_CTL_RST) {
269 lio_dev_err(lio_dev, "unable to reset qno %lu\n",
270 (unsigned long)q_no);