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34 #ifndef _LIO_HW_DEFS_H_
35 #define _LIO_HW_DEFS_H_
39 #ifndef PCI_VENDOR_ID_CAVIUM
40 #define PCI_VENDOR_ID_CAVIUM 0x177D
43 #define LIO_CN23XX_VF_VID 0x9712
45 /* --------------------------CONFIG VALUES------------------------ */
47 /* CN23xx IQ configuration macros */
48 #define CN23XX_MAX_RINGS_PER_PF 64
49 #define CN23XX_MAX_RINGS_PER_VF 8
51 #define CN23XX_MAX_INPUT_QUEUES CN23XX_MAX_RINGS_PER_PF
52 #define CN23XX_MAX_IQ_DESCRIPTORS 512
53 #define CN23XX_MIN_IQ_DESCRIPTORS 128
55 #define CN23XX_MAX_OUTPUT_QUEUES CN23XX_MAX_RINGS_PER_PF
56 #define CN23XX_MAX_OQ_DESCRIPTORS 512
57 #define CN23XX_MIN_OQ_DESCRIPTORS 128
58 #define CN23XX_OQ_BUF_SIZE 1536
60 #define CN23XX_OQ_REFIL_THRESHOLD 16
62 #define CN23XX_DEFAULT_NUM_PORTS 1
64 #define CN23XX_CFG_IO_QUEUES CN23XX_MAX_RINGS_PER_PF
66 /* common OCTEON configuration macros */
67 #define OCTEON_64BYTE_INSTR 64
68 #define OCTEON_OQ_INFOPTR_MODE 1
70 /* Max IOQs per LIO Link */
71 #define LIO_MAX_IOQS_PER_IF 64
77 #define LIO_23XX_NAME "23xx"
79 #define LIO_DEV_RUNNING 0xc
81 #define LIO_OQ_REFILL_THRESHOLD_CFG(cfg) \
82 ((cfg)->default_config->oq.refill_threshold)
83 #define LIO_NUM_DEF_TX_DESCS_CFG(cfg) \
84 ((cfg)->default_config->num_def_tx_descs)
86 #define LIO_IQ_INSTR_TYPE(cfg) ((cfg)->default_config->iq.instr_type)
88 /* The following config values are fixed and should not be modified. */
90 /* Maximum number of Instruction queues */
91 #define LIO_MAX_INSTR_QUEUES(lio_dev) CN23XX_MAX_RINGS_PER_VF
93 #define LIO_MAX_POSSIBLE_INSTR_QUEUES CN23XX_MAX_INPUT_QUEUES
94 #define LIO_MAX_POSSIBLE_OUTPUT_QUEUES CN23XX_MAX_OUTPUT_QUEUES
96 #define LIO_DEVICE_NAME_LEN 32
97 #define LIO_BASE_MAJOR_VERSION 1
98 #define LIO_BASE_MINOR_VERSION 5
99 #define LIO_BASE_MICRO_VERSION 1
101 #define LIO_FW_VERSION_LENGTH 32
103 /** Tag types used by Octeon cores in its work. */
104 enum octeon_tag_type {
105 OCTEON_ORDERED_TAG = 0,
106 OCTEON_ATOMIC_TAG = 1,
109 /* pre-defined host->NIC tag values */
110 #define LIO_CONTROL (0x11111110)
111 #define LIO_DATA(i) (0x11111111 + (i))
113 /* used for NIC operations */
116 /* Subcodes are used by host driver/apps to identify the sub-operation
117 * for the core. They only need to by unique for a given subsystem.
119 #define LIO_OPCODE_SUBCODE(op, sub) \
120 ((((op) & 0x0f) << 8) | ((sub) & 0x7f))
122 /** LIO_OPCODE subcodes */
123 /* This subcode is sent by core PCI driver to indicate cores are ready. */
124 #define LIO_OPCODE_NW_DATA 0x02 /* network packet data */
125 #define LIO_OPCODE_CMD 0x03
126 #define LIO_OPCODE_INFO 0x04
127 #define LIO_OPCODE_IF_CFG 0x09
129 #define LIO_MAX_RX_PKTLEN (64 * 1024)
131 /* RX(packets coming from wire) Checksum verification flags */
133 #define LIO_L4_CSUM_VERIFIED 0x1
134 #define LIO_IP_CSUM_VERIFIED 0x2
136 /* Interface flags communicated between host driver and core app. */
138 LIO_IFFLAG_UNICAST = 0x10
141 /* Routines for reading and writing CSRs */
142 #ifdef RTE_LIBRTE_LIO_DEBUG_REGS
143 #define lio_write_csr(lio_dev, reg_off, value) \
145 typeof(lio_dev) _dev = lio_dev; \
146 typeof(reg_off) _reg_off = reg_off; \
147 typeof(value) _value = value; \
149 "Write32: Reg: 0x%08lx Val: 0x%08lx\n", \
150 (unsigned long)_reg_off, \
151 (unsigned long)_value); \
152 rte_write32(_value, _dev->hw_addr + _reg_off); \
155 #define lio_write_csr64(lio_dev, reg_off, val64) \
157 typeof(lio_dev) _dev = lio_dev; \
158 typeof(reg_off) _reg_off = reg_off; \
159 typeof(val64) _val64 = val64; \
162 "Write64: Reg: 0x%08lx Val: 0x%016llx\n", \
163 (unsigned long)_reg_off, \
164 (unsigned long long)_val64); \
165 rte_write64(_val64, _dev->hw_addr + _reg_off); \
168 #define lio_read_csr(lio_dev, reg_off) \
170 typeof(lio_dev) _dev = lio_dev; \
171 typeof(reg_off) _reg_off = reg_off; \
172 uint32_t val = rte_read32(_dev->hw_addr + _reg_off); \
174 "Read32: Reg: 0x%08lx Val: 0x%08lx\n", \
175 (unsigned long)_reg_off, \
176 (unsigned long)val); \
180 #define lio_read_csr64(lio_dev, reg_off) \
182 typeof(lio_dev) _dev = lio_dev; \
183 typeof(reg_off) _reg_off = reg_off; \
184 uint64_t val64 = rte_read64(_dev->hw_addr + _reg_off); \
187 "Read64: Reg: 0x%08lx Val: 0x%016llx\n", \
188 (unsigned long)_reg_off, \
189 (unsigned long long)val64); \
193 #define lio_write_csr(lio_dev, reg_off, value) \
194 rte_write32(value, (lio_dev)->hw_addr + (reg_off))
196 #define lio_write_csr64(lio_dev, reg_off, val64) \
197 rte_write64(val64, (lio_dev)->hw_addr + (reg_off))
199 #define lio_read_csr(lio_dev, reg_off) \
200 rte_read32((lio_dev)->hw_addr + (reg_off))
202 #define lio_read_csr64(lio_dev, reg_off) \
203 rte_read64((lio_dev)->hw_addr + (reg_off))
205 #endif /* _LIO_HW_DEFS_H_ */