drivers/net/mlx4/mlx4_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright 2017 6WIND S.A.
   5  *   Copyright 2017 Mellanox
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of 6WIND S.A. nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 /**
  35  * @file
  36  * Data plane functions for mlx4 driver.
  37  */
  38
  39 #include <assert.h>
  40 #include <stdint.h>
  41 #include <string.h>
  42
  43 /* Verbs headers do not support -pedantic. */
  44 #ifdef PEDANTIC
  45 #pragma GCC diagnostic ignored "-Wpedantic"
  46 #endif
  47 #include <infiniband/verbs.h>
  48 #ifdef PEDANTIC
  49 #pragma GCC diagnostic error "-Wpedantic"
  50 #endif
  51
  52 #include <rte_branch_prediction.h>
  53 #include <rte_common.h>
  54 #include <rte_io.h>
  55 #include <rte_mbuf.h>
  56 #include <rte_mempool.h>
  57 #include <rte_prefetch.h>
  58
  59 #include "mlx4.h"
  60 #include "mlx4_prm.h"
  61 #include "mlx4_rxtx.h"
  62 #include "mlx4_utils.h"
  63
  64 #define WQE_ONE_DATA_SEG_SIZE \
  65         (sizeof(struct mlx4_wqe_ctrl_seg) + sizeof(struct mlx4_wqe_data_seg))
  66
  67 /**
  68  * Pointer-value pair structure used in tx_post_send for saving the first
  69  * DWORD (32 byte) of a TXBB.
  70  */
  71 struct pv {
  72         volatile struct mlx4_wqe_data_seg *dseg;
  73         uint32_t val;
  74 };
  75
  76 /** A table to translate Rx completion flags to packet type. */
  77 uint32_t mlx4_ptype_table[0x100] __rte_cache_aligned = {
  78         /*
  79          * The index to the array should have:
  80          *  bit[7] - MLX4_CQE_L2_TUNNEL
  81          *  bit[6] - MLX4_CQE_L2_TUNNEL_IPV4
  82          *  bit[5] - MLX4_CQE_STATUS_UDP
  83          *  bit[4] - MLX4_CQE_STATUS_TCP
  84          *  bit[3] - MLX4_CQE_STATUS_IPV4OPT
  85          *  bit[2] - MLX4_CQE_STATUS_IPV6
  86          *  bit[1] - MLX4_CQE_STATUS_IPV4F
  87          *  bit[0] - MLX4_CQE_STATUS_IPV4
  88          * giving a total of up to 256 entries.
  89          */
  90         [0x00] = RTE_PTYPE_L2_ETHER,
  91         [0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
  92         [0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  93                      RTE_PTYPE_L4_FRAG,
  94         [0x03] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  95                      RTE_PTYPE_L4_FRAG,
  96         [0x04] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
  97         [0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT,
  98         [0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
  99                      RTE_PTYPE_L4_FRAG,
 100         [0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 101                      RTE_PTYPE_L4_TCP,
 102         [0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 103                      RTE_PTYPE_L4_TCP,
 104         [0x14] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 105                      RTE_PTYPE_L4_TCP,
 106         [0x18] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
 107                      RTE_PTYPE_L4_TCP,
 108         [0x19] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
 109                      RTE_PTYPE_L4_TCP,
 110         [0x1a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
 111                      RTE_PTYPE_L4_TCP,
 112         [0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 113                      RTE_PTYPE_L4_UDP,
 114         [0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 115                      RTE_PTYPE_L4_UDP,
 116         [0x24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 117                      RTE_PTYPE_L4_UDP,
 118         [0x28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
 119                      RTE_PTYPE_L4_UDP,
 120         [0x29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
 121                      RTE_PTYPE_L4_UDP,
 122         [0x2a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
 123                      RTE_PTYPE_L4_UDP,
 124         /* Tunneled - L3 IPV6 */
 125         [0x80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 126         [0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 127                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
 128         [0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 129                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 130                      RTE_PTYPE_INNER_L4_FRAG,
 131         [0x83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 132                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 133                      RTE_PTYPE_INNER_L4_FRAG,
 134         [0x84] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 135                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
 136         [0x88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 137                      RTE_PTYPE_INNER_L3_IPV4_EXT,
 138         [0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 139                      RTE_PTYPE_INNER_L3_IPV4_EXT,
 140         [0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 141                      RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_FRAG,
 142         /* Tunneled - L3 IPV6, TCP */
 143         [0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 144                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 145                      RTE_PTYPE_INNER_L4_TCP,
 146         [0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 147                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 148                      RTE_PTYPE_INNER_L4_FRAG |
 149                      RTE_PTYPE_INNER_L4_TCP,
 150         [0x93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 151                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 152                      RTE_PTYPE_INNER_L4_FRAG |
 153                      RTE_PTYPE_INNER_L4_TCP,
 154         [0x94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 155                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 156                      RTE_PTYPE_INNER_L4_TCP,
 157         [0x98] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 158                      RTE_PTYPE_INNER_L3_IPV4_EXT |
 159                      RTE_PTYPE_INNER_L4_TCP,
 160         [0x99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 161                      RTE_PTYPE_INNER_L3_IPV4_EXT |
 162                      RTE_PTYPE_INNER_L4_TCP,
 163         [0x9a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 164                      RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_FRAG |
 165                      RTE_PTYPE_INNER_L4_TCP,
 166         /* Tunneled - L3 IPV6, UDP */
 167         [0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 168                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 169                      RTE_PTYPE_INNER_L4_UDP,
 170         [0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 171                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 172                      RTE_PTYPE_INNER_L4_FRAG |
 173                      RTE_PTYPE_INNER_L4_UDP,
 174         [0xa3] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 175                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 176                      RTE_PTYPE_INNER_L4_FRAG |
 177                      RTE_PTYPE_INNER_L4_UDP,
 178         [0xa4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 179                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 180                      RTE_PTYPE_INNER_L4_UDP,
 181         [0xa8] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 182                      RTE_PTYPE_INNER_L3_IPV4_EXT |
 183                      RTE_PTYPE_INNER_L4_UDP,
 184         [0xa9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 185                      RTE_PTYPE_INNER_L3_IPV4_EXT |
 186                      RTE_PTYPE_INNER_L4_UDP,
 187         [0xaa] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 188                      RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_FRAG |
 189                      RTE_PTYPE_INNER_L4_UDP,
 190         /* Tunneled - L3 IPV4 */
 191         [0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 192         [0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 193                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
 194         [0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 195                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 196                      RTE_PTYPE_INNER_L4_FRAG,
 197         [0xc3] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 198                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 199                      RTE_PTYPE_INNER_L4_FRAG,
 200         [0xc4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 201                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
 202         [0xc8] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 203                      RTE_PTYPE_INNER_L3_IPV4_EXT,
 204         [0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 205                      RTE_PTYPE_INNER_L3_IPV4_EXT,
 206         [0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 207                      RTE_PTYPE_INNER_L3_IPV4_EXT |
 208                      RTE_PTYPE_INNER_L4_FRAG,
 209         /* Tunneled - L3 IPV4, TCP */
 210         [0xd0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 211                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 212                      RTE_PTYPE_INNER_L4_TCP,
 213         [0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 214                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 215                      RTE_PTYPE_INNER_L4_TCP,
 216         [0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 217                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 218                      RTE_PTYPE_INNER_L4_FRAG |
 219                      RTE_PTYPE_INNER_L4_TCP,
 220         [0xd3] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 221                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 222                      RTE_PTYPE_INNER_L4_FRAG |
 223                      RTE_PTYPE_INNER_L4_TCP,
 224         [0xd4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 225                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 226                      RTE_PTYPE_INNER_L4_TCP,
 227         [0xd8] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 228                      RTE_PTYPE_INNER_L3_IPV4_EXT |
 229                      RTE_PTYPE_INNER_L4_TCP,
 230         [0xd9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 231                      RTE_PTYPE_INNER_L3_IPV4_EXT |
 232                      RTE_PTYPE_INNER_L4_TCP,
 233         [0xda] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 234                      RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_FRAG |
 235                      RTE_PTYPE_INNER_L4_TCP,
 236         /* Tunneled - L3 IPV4, UDP */
 237         [0xe0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 238                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 239                      RTE_PTYPE_INNER_L4_UDP,
 240         [0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 241                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 242                      RTE_PTYPE_INNER_L4_UDP,
 243         [0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 244                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 245                      RTE_PTYPE_INNER_L4_FRAG |
 246                      RTE_PTYPE_INNER_L4_UDP,
 247         [0xe3] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 248                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 249                      RTE_PTYPE_INNER_L4_FRAG |
 250                      RTE_PTYPE_INNER_L4_UDP,
 251         [0xe4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 252                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 253                      RTE_PTYPE_INNER_L4_UDP,
 254         [0xe8] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 255                      RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_UDP,
 256         [0xe9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 257                      RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_UDP,
 258         [0xea] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 259                      RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_FRAG |
 260                      RTE_PTYPE_INNER_L4_UDP,
 261 };
 262
 263 /**
 264  * Stamp a WQE so it won't be reused by the HW.
 265  *
 266  * Routine is used when freeing WQE used by the chip or when failing
 267  * building an WQ entry has failed leaving partial information on the queue.
 268  *
 269  * @param sq
 270  *   Pointer to the SQ structure.
 271  * @param index
 272  *   Index of the freed WQE.
 273  * @param num_txbbs
 274  *   Number of blocks to stamp.
 275  *   If < 0 the routine will use the size written in the WQ entry.
 276  * @param owner
 277  *   The value of the WQE owner bit to use in the stamp.
 278  *
 279  * @return
 280  *   The number of Tx basic blocs (TXBB) the WQE contained.
 281  */
 282 static int
 283 mlx4_txq_stamp_freed_wqe(struct mlx4_sq *sq, uint16_t index, uint8_t owner)
 284 {
 285         uint32_t stamp = rte_cpu_to_be_32(MLX4_SQ_STAMP_VAL |
 286                                           (!!owner << MLX4_SQ_STAMP_SHIFT));
 287         volatile uint8_t *wqe = mlx4_get_send_wqe(sq,
 288                                                 (index & sq->txbb_cnt_mask));
 289         volatile uint32_t *ptr = (volatile uint32_t *)wqe;
 290         int i;
 291         int txbbs_size;
 292         int num_txbbs;
 293
 294         /* Extract the size from the control segment of the WQE. */
 295         num_txbbs = MLX4_SIZE_TO_TXBBS((((volatile struct mlx4_wqe_ctrl_seg *)
 296                                          wqe)->fence_size & 0x3f) << 4);
 297         txbbs_size = num_txbbs * MLX4_TXBB_SIZE;
 298         /* Optimize the common case when there is no wrap-around. */
 299         if (wqe + txbbs_size <= sq->eob) {
 300                 /* Stamp the freed descriptor. */
 301                 for (i = 0; i < txbbs_size; i += MLX4_SQ_STAMP_STRIDE) {
 302                         *ptr = stamp;
 303                         ptr += MLX4_SQ_STAMP_DWORDS;
 304                 }
 305         } else {
 306                 /* Stamp the freed descriptor. */
 307                 for (i = 0; i < txbbs_size; i += MLX4_SQ_STAMP_STRIDE) {
 308                         *ptr = stamp;
 309                         ptr += MLX4_SQ_STAMP_DWORDS;
 310                         if ((volatile uint8_t *)ptr >= sq->eob) {
 311                                 ptr = (volatile uint32_t *)sq->buf;
 312                                 stamp ^= RTE_BE32(0x80000000);
 313                         }
 314                 }
 315         }
 316         return num_txbbs;
 317 }
 318
 319 /**
 320  * Manage Tx completions.
 321  *
 322  * When sending a burst, mlx4_tx_burst() posts several WRs.
 323  * To improve performance, a completion event is only required once every
 324  * MLX4_PMD_TX_PER_COMP_REQ sends. Doing so discards completion information
 325  * for other WRs, but this information would not be used anyway.
 326  *
 327  * @param txq
 328  *   Pointer to Tx queue structure.
 329  *
 330  * @return
 331  *   0 on success, -1 on failure.
 332  */
 333 static int
 334 mlx4_txq_complete(struct txq *txq, const unsigned int elts_n,
 335                                   struct mlx4_sq *sq)
 336 {
 337         unsigned int elts_comp = txq->elts_comp;
 338         unsigned int elts_tail = txq->elts_tail;
 339         struct mlx4_cq *cq = &txq->mcq;
 340         volatile struct mlx4_cqe *cqe;
 341         uint32_t cons_index = cq->cons_index;
 342         uint16_t new_index;
 343         uint16_t nr_txbbs = 0;
 344         int pkts = 0;
 345
 346         /*
 347          * Traverse over all CQ entries reported and handle each WQ entry
 348          * reported by them.
 349          */
 350         do {
 351                 cqe = (volatile struct mlx4_cqe *)mlx4_get_cqe(cq, cons_index);
 352                 if (unlikely(!!(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
 353                     !!(cons_index & cq->cqe_cnt)))
 354                         break;
 355                 /*
 356                  * Make sure we read the CQE after we read the ownership bit.
 357                  */
 358                 rte_io_rmb();
 359 #ifndef NDEBUG
 360                 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
 361                              MLX4_CQE_OPCODE_ERROR)) {
 362                         volatile struct mlx4_err_cqe *cqe_err =
 363                                 (volatile struct mlx4_err_cqe *)cqe;
 364                         ERROR("%p CQE error - vendor syndrome: 0x%x"
 365                               " syndrome: 0x%x\n",
 366                               (void *)txq, cqe_err->vendor_err,
 367                               cqe_err->syndrome);
 368                 }
 369 #endif /* NDEBUG */
 370                 /* Get WQE index reported in the CQE. */
 371                 new_index =
 372                         rte_be_to_cpu_16(cqe->wqe_index) & sq->txbb_cnt_mask;
 373                 do {
 374                         /* Free next descriptor. */
 375                         nr_txbbs +=
 376                                 mlx4_txq_stamp_freed_wqe(sq,
 377                                      (sq->tail + nr_txbbs) & sq->txbb_cnt_mask,
 378                                      !!((sq->tail + nr_txbbs) & sq->txbb_cnt));
 379                         pkts++;
 380                 } while (((sq->tail + nr_txbbs) & sq->txbb_cnt_mask) !=
 381                          new_index);
 382                 cons_index++;
 383         } while (1);
 384         if (unlikely(pkts == 0))
 385                 return 0;
 386         /* Update CQ. */
 387         cq->cons_index = cons_index;
 388         *cq->set_ci_db = rte_cpu_to_be_32(cq->cons_index & MLX4_CQ_DB_CI_MASK);
 389         sq->tail = sq->tail + nr_txbbs;
 390         /* Update the list of packets posted for transmission. */
 391         elts_comp -= pkts;
 392         assert(elts_comp <= txq->elts_comp);
 393         /*
 394          * Assume completion status is successful as nothing can be done about
 395          * it anyway.
 396          */
 397         elts_tail += pkts;
 398         if (elts_tail >= elts_n)
 399                 elts_tail -= elts_n;
 400         txq->elts_tail = elts_tail;
 401         txq->elts_comp = elts_comp;
 402         return 0;
 403 }
 404
 405 /**
 406  * Get memory pool (MP) from mbuf. If mbuf is indirect, the pool from which
 407  * the cloned mbuf is allocated is returned instead.
 408  *
 409  * @param buf
 410  *   Pointer to mbuf.
 411  *
 412  * @return
 413  *   Memory pool where data is located for given mbuf.
 414  */
 415 static struct rte_mempool *
 416 mlx4_txq_mb2mp(struct rte_mbuf *buf)
 417 {
 418         if (unlikely(RTE_MBUF_INDIRECT(buf)))
 419                 return rte_mbuf_from_indirect(buf)->pool;
 420         return buf->pool;
 421 }
 422
 423 static int
 424 mlx4_tx_burst_segs(struct rte_mbuf *buf, struct txq *txq,
 425                    volatile struct mlx4_wqe_ctrl_seg **pctrl)
 426 {
 427         int wqe_real_size;
 428         int nr_txbbs;
 429         struct pv *pv = (struct pv *)txq->bounce_buf;
 430         struct mlx4_sq *sq = &txq->msq;
 431         uint32_t head_idx = sq->head & sq->txbb_cnt_mask;
 432         volatile struct mlx4_wqe_ctrl_seg *ctrl;
 433         volatile struct mlx4_wqe_data_seg *dseg;
 434         struct rte_mbuf *sbuf;
 435         uint32_t lkey;
 436         uintptr_t addr;
 437         uint32_t byte_count;
 438         int pv_counter = 0;
 439
 440         /* Calculate the needed work queue entry size for this packet. */
 441         wqe_real_size = sizeof(volatile struct mlx4_wqe_ctrl_seg) +
 442                 buf->nb_segs * sizeof(volatile struct mlx4_wqe_data_seg);
 443         nr_txbbs = MLX4_SIZE_TO_TXBBS(wqe_real_size);
 444         /*
 445          * Check that there is room for this WQE in the send queue and that
 446          * the WQE size is legal.
 447          */
 448         if (((sq->head - sq->tail) + nr_txbbs +
 449                                 sq->headroom_txbbs) >= sq->txbb_cnt ||
 450                         nr_txbbs > MLX4_MAX_WQE_TXBBS) {
 451                 return -1;
 452         }
 453         /* Get the control and data entries of the WQE. */
 454         ctrl = (volatile struct mlx4_wqe_ctrl_seg *)
 455                         mlx4_get_send_wqe(sq, head_idx);
 456         dseg = (volatile struct mlx4_wqe_data_seg *)
 457                         ((uintptr_t)ctrl + sizeof(struct mlx4_wqe_ctrl_seg));
 458         *pctrl = ctrl;
 459         /* Fill the data segments with buffer information. */
 460         for (sbuf = buf; sbuf != NULL; sbuf = sbuf->next, dseg++) {
 461                 addr = rte_pktmbuf_mtod(sbuf, uintptr_t);
 462                 rte_prefetch0((volatile void *)addr);
 463                 /* Handle WQE wraparound. */
 464                 if (dseg >= (volatile struct mlx4_wqe_data_seg *)sq->eob)
 465                         dseg = (volatile struct mlx4_wqe_data_seg *)sq->buf;
 466                 dseg->addr = rte_cpu_to_be_64(addr);
 467                 /* Memory region key (big endian) for this memory pool. */
 468                 lkey = mlx4_txq_mp2mr(txq, mlx4_txq_mb2mp(sbuf));
 469                 dseg->lkey = rte_cpu_to_be_32(lkey);
 470 #ifndef NDEBUG
 471                 /* Calculate the needed work queue entry size for this packet */
 472                 if (unlikely(dseg->lkey == rte_cpu_to_be_32((uint32_t)-1))) {
 473                         /* MR does not exist. */
 474                         DEBUG("%p: unable to get MP <-> MR association",
 475                                         (void *)txq);
 476                         /*
 477                          * Restamp entry in case of failure.
 478                          * Make sure that size is written correctly
 479                          * Note that we give ownership to the SW, not the HW.
 480                          */
 481                         wqe_real_size = sizeof(struct mlx4_wqe_ctrl_seg) +
 482                                 buf->nb_segs * sizeof(struct mlx4_wqe_data_seg);
 483                         ctrl->fence_size = (wqe_real_size >> 4) & 0x3f;
 484                         mlx4_txq_stamp_freed_wqe(sq, head_idx,
 485                                         (sq->head & sq->txbb_cnt) ? 0 : 1);
 486                         return -1;
 487                 }
 488 #endif /* NDEBUG */
 489                 if (likely(sbuf->data_len)) {
 490                         byte_count = rte_cpu_to_be_32(sbuf->data_len);
 491                 } else {
 492                         /*
 493                          * Zero length segment is treated as inline segment
 494                          * with zero data.
 495                          */
 496                         byte_count = RTE_BE32(0x80000000);
 497                 }
 498                 /*
 499                  * If the data segment is not at the beginning of a
 500                  * Tx basic block (TXBB) then write the byte count,
 501                  * else postpone the writing to just before updating the
 502                  * control segment.
 503                  */
 504                 if ((uintptr_t)dseg & (uintptr_t)(MLX4_TXBB_SIZE - 1)) {
 505 #if RTE_CACHE_LINE_SIZE < 64
 506                         /*
 507                          * Need a barrier here before writing the byte_count
 508                          * fields to make sure that all the data is visible
 509                          * before the byte_count field is set.
 510                          * Otherwise, if the segment begins a new cacheline,
 511                          * the HCA prefetcher could grab the 64-byte chunk and
 512                          * get a valid (!= 0xffffffff) byte count but stale
 513                          * data, and end up sending the wrong data.
 514                          */
 515                         rte_io_wmb();
 516 #endif /* RTE_CACHE_LINE_SIZE */
 517                         dseg->byte_count = byte_count;
 518                 } else {
 519                         /*
 520                          * This data segment starts at the beginning of a new
 521                          * TXBB, so we need to postpone its byte_count writing
 522                          * for later.
 523                          */
 524                         pv[pv_counter].dseg = dseg;
 525                         pv[pv_counter++].val = byte_count;
 526                 }
 527         }
 528         /* Write the first DWORD of each TXBB save earlier. */
 529         if (pv_counter) {
 530                 /* Need a barrier here before writing the byte_count. */
 531                 rte_io_wmb();
 532                 for (--pv_counter; pv_counter  >= 0; pv_counter--)
 533                         pv[pv_counter].dseg->byte_count = pv[pv_counter].val;
 534         }
 535         /* Fill the control parameters for this packet. */
 536         ctrl->fence_size = (wqe_real_size >> 4) & 0x3f;
 537         return nr_txbbs;
 538 }
 539
 540 /**
 541  * DPDK callback for Tx.
 542  *
 543  * @param dpdk_txq
 544  *   Generic pointer to Tx queue structure.
 545  * @param[in] pkts
 546  *   Packets to transmit.
 547  * @param pkts_n
 548  *   Number of packets in array.
 549  *
 550  * @return
 551  *   Number of packets successfully transmitted (<= pkts_n).
 552  */
 553 uint16_t
 554 mlx4_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 555 {
 556         struct txq *txq = (struct txq *)dpdk_txq;
 557         unsigned int elts_head = txq->elts_head;
 558         const unsigned int elts_n = txq->elts_n;
 559         unsigned int bytes_sent = 0;
 560         unsigned int i;
 561         unsigned int max;
 562         struct mlx4_sq *sq = &txq->msq;
 563         int nr_txbbs;
 564
 565         assert(txq->elts_comp_cd != 0);
 566         if (likely(txq->elts_comp != 0))
 567                 mlx4_txq_complete(txq, elts_n, sq);
 568         max = (elts_n - (elts_head - txq->elts_tail));
 569         if (max > elts_n)
 570                 max -= elts_n;
 571         assert(max >= 1);
 572         assert(max <= elts_n);
 573         /* Always leave one free entry in the ring. */
 574         --max;
 575         if (max > pkts_n)
 576                 max = pkts_n;
 577         for (i = 0; (i != max); ++i) {
 578                 struct rte_mbuf *buf = pkts[i];
 579                 unsigned int elts_head_next =
 580                         (((elts_head + 1) == elts_n) ? 0 : elts_head + 1);
 581                 struct txq_elt *elt_next = &(*txq->elts)[elts_head_next];
 582                 struct txq_elt *elt = &(*txq->elts)[elts_head];
 583                 uint32_t owner_opcode = MLX4_OPCODE_SEND;
 584                 volatile struct mlx4_wqe_ctrl_seg *ctrl;
 585                 volatile struct mlx4_wqe_data_seg *dseg;
 586                 union {
 587                         uint32_t flags;
 588                         uint16_t flags16[2];
 589                 } srcrb;
 590                 uint32_t head_idx = sq->head & sq->txbb_cnt_mask;
 591                 uint32_t lkey;
 592                 uintptr_t addr;
 593
 594                 /* Clean up old buffer. */
 595                 if (likely(elt->buf != NULL)) {
 596                         struct rte_mbuf *tmp = elt->buf;
 597
 598 #ifndef NDEBUG
 599                         /* Poisoning. */
 600                         memset(elt, 0x66, sizeof(*elt));
 601 #endif
 602                         /* Faster than rte_pktmbuf_free(). */
 603                         do {
 604                                 struct rte_mbuf *next = tmp->next;
 605
 606                                 rte_pktmbuf_free_seg(tmp);
 607                                 tmp = next;
 608                         } while (tmp != NULL);
 609                 }
 610                 RTE_MBUF_PREFETCH_TO_FREE(elt_next->buf);
 611                 if (buf->nb_segs == 1) {
 612                         /*
 613                          * Check that there is room for this WQE in the send
 614                          * queue and that the WQE size is legal
 615                          */
 616                         if (((sq->head - sq->tail) + 1 + sq->headroom_txbbs) >=
 617                              sq->txbb_cnt || 1 > MLX4_MAX_WQE_TXBBS) {
 618                                 elt->buf = NULL;
 619                                 break;
 620                         }
 621                         /* Get the control and data entries of the WQE. */
 622                         ctrl = (volatile struct mlx4_wqe_ctrl_seg *)
 623                                         mlx4_get_send_wqe(sq, head_idx);
 624                         dseg = (volatile struct mlx4_wqe_data_seg *)
 625                                         ((uintptr_t)ctrl +
 626                                         sizeof(struct mlx4_wqe_ctrl_seg));
 627                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
 628                         rte_prefetch0((volatile void *)addr);
 629                         /* Handle WQE wraparound. */
 630                         if (dseg >=
 631                                 (volatile struct mlx4_wqe_data_seg *)sq->eob)
 632                                 dseg = (volatile struct mlx4_wqe_data_seg *)
 633                                                 sq->buf;
 634                         dseg->addr = rte_cpu_to_be_64(addr);
 635                         /* Memory region key (big endian). */
 636                         lkey = mlx4_txq_mp2mr(txq, mlx4_txq_mb2mp(buf));
 637                         dseg->lkey = rte_cpu_to_be_32(lkey);
 638 #ifndef NDEBUG
 639                         if (unlikely(dseg->lkey ==
 640                                 rte_cpu_to_be_32((uint32_t)-1))) {
 641                                 /* MR does not exist. */
 642                                 DEBUG("%p: unable to get MP <-> MR association",
 643                                       (void *)txq);
 644                                 /*
 645                                  * Restamp entry in case of failure.
 646                                  * Make sure that size is written correctly
 647                                  * Note that we give ownership to the SW,
 648                                  * not the HW.
 649                                  */
 650                                 ctrl->fence_size =
 651                                         (WQE_ONE_DATA_SEG_SIZE >> 4) & 0x3f;
 652                                 mlx4_txq_stamp_freed_wqe(sq, head_idx,
 653                                              (sq->head & sq->txbb_cnt) ? 0 : 1);
 654                                 elt->buf = NULL;
 655                                 break;
 656                         }
 657 #endif /* NDEBUG */
 658                         /* Never be TXBB aligned, no need compiler barrier. */
 659                         dseg->byte_count = rte_cpu_to_be_32(buf->data_len);
 660                         /* Fill the control parameters for this packet. */
 661                         ctrl->fence_size = (WQE_ONE_DATA_SEG_SIZE >> 4) & 0x3f;
 662                         nr_txbbs = 1;
 663                 } else {
 664                         nr_txbbs = mlx4_tx_burst_segs(buf, txq, &ctrl);
 665                         if (nr_txbbs < 0) {
 666                                 elt->buf = NULL;
 667                                 break;
 668                         }
 669                 }
 670                 /*
 671                  * For raw Ethernet, the SOLICIT flag is used to indicate
 672                  * that no ICRC should be calculated.
 673                  */
 674                 txq->elts_comp_cd -= nr_txbbs;
 675                 if (unlikely(txq->elts_comp_cd <= 0)) {
 676                         txq->elts_comp_cd = txq->elts_comp_cd_init;
 677                         srcrb.flags = RTE_BE32(MLX4_WQE_CTRL_SOLICIT |
 678                                                MLX4_WQE_CTRL_CQ_UPDATE);
 679                 } else {
 680                         srcrb.flags = RTE_BE32(MLX4_WQE_CTRL_SOLICIT);
 681                 }
 682                 /* Enable HW checksum offload if requested */
 683                 if (txq->csum &&
 684                     (buf->ol_flags &
 685                      (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))) {
 686                         const uint64_t is_tunneled = (buf->ol_flags &
 687                                                       (PKT_TX_TUNNEL_GRE |
 688                                                        PKT_TX_TUNNEL_VXLAN));
 689
 690                         if (is_tunneled && txq->csum_l2tun) {
 691                                 owner_opcode |= MLX4_WQE_CTRL_IIP_HDR_CSUM |
 692                                                 MLX4_WQE_CTRL_IL4_HDR_CSUM;
 693                                 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
 694                                         srcrb.flags |=
 695                                             RTE_BE32(MLX4_WQE_CTRL_IP_HDR_CSUM);
 696                         } else {
 697                                 srcrb.flags |=
 698                                         RTE_BE32(MLX4_WQE_CTRL_IP_HDR_CSUM |
 699                                                 MLX4_WQE_CTRL_TCP_UDP_CSUM);
 700                         }
 701                 }
 702                 if (txq->lb) {
 703                         /*
 704                          * Copy destination MAC address to the WQE, this allows
 705                          * loopback in eSwitch, so that VFs and PF can
 706                          * communicate with each other.
 707                          */
 708                         srcrb.flags16[0] = *(rte_pktmbuf_mtod(buf, uint16_t *));
 709                         ctrl->imm = *(rte_pktmbuf_mtod_offset(buf, uint32_t *,
 710                                               sizeof(uint16_t)));
 711                 } else {
 712                         ctrl->imm = 0;
 713                 }
 714                 ctrl->srcrb_flags = srcrb.flags;
 715                 /*
 716                  * Make sure descriptor is fully written before
 717                  * setting ownership bit (because HW can start
 718                  * executing as soon as we do).
 719                  */
 720                 rte_io_wmb();
 721                 ctrl->owner_opcode = rte_cpu_to_be_32(owner_opcode |
 722                                               ((sq->head & sq->txbb_cnt) ?
 723                                                        MLX4_BIT_WQE_OWN : 0));
 724                 sq->head += nr_txbbs;
 725                 elt->buf = buf;
 726                 bytes_sent += buf->pkt_len;
 727                 elts_head = elts_head_next;
 728         }
 729         /* Take a shortcut if nothing must be sent. */
 730         if (unlikely(i == 0))
 731                 return 0;
 732         /* Increment send statistics counters. */
 733         txq->stats.opackets += i;
 734         txq->stats.obytes += bytes_sent;
 735         /* Make sure that descriptors are written before doorbell record. */
 736         rte_wmb();
 737         /* Ring QP doorbell. */
 738         rte_write32(txq->msq.doorbell_qpn, txq->msq.db);
 739         txq->elts_head = elts_head;
 740         txq->elts_comp += i;
 741         return i;
 742 }
 743
 744 /**
 745  * Translate Rx completion flags to packet type.
 746  *
 747  * @param[in] cqe
 748  *   Pointer to CQE.
 749  *
 750  * @return
 751  *   Packet type for struct rte_mbuf.
 752  */
 753 static inline uint32_t
 754 rxq_cq_to_pkt_type(volatile struct mlx4_cqe *cqe)
 755 {
 756         uint8_t idx = 0;
 757         uint32_t pinfo = rte_be_to_cpu_32(cqe->vlan_my_qpn);
 758         uint32_t status = rte_be_to_cpu_32(cqe->status);
 759
 760         /*
 761          * The index to the array should have:
 762          *  bit[7] - MLX4_CQE_L2_TUNNEL
 763          *  bit[6] - MLX4_CQE_L2_TUNNEL_IPV4
 764          */
 765         if (!(pinfo & MLX4_CQE_L2_VLAN_MASK) && (pinfo & MLX4_CQE_L2_TUNNEL))
 766                 idx |= ((pinfo & MLX4_CQE_L2_TUNNEL) >> 20) |
 767                        ((pinfo & MLX4_CQE_L2_TUNNEL_IPV4) >> 19);
 768         /*
 769          * The index to the array should have:
 770          *  bit[5] - MLX4_CQE_STATUS_UDP
 771          *  bit[4] - MLX4_CQE_STATUS_TCP
 772          *  bit[3] - MLX4_CQE_STATUS_IPV4OPT
 773          *  bit[2] - MLX4_CQE_STATUS_IPV6
 774          *  bit[1] - MLX4_CQE_STATUS_IPV4F
 775          *  bit[0] - MLX4_CQE_STATUS_IPV4
 776          * giving a total of up to 256 entries.
 777          */
 778         idx |= ((status & MLX4_CQE_STATUS_PTYPE_MASK) >> 22);
 779         return mlx4_ptype_table[idx];
 780 }
 781
 782 /**
 783  * Translate Rx completion flags to offload flags.
 784  *
 785  * @param flags
 786  *   Rx completion flags returned by mlx4_cqe_flags().
 787  * @param csum
 788  *   Whether Rx checksums are enabled.
 789  * @param csum_l2tun
 790  *   Whether Rx L2 tunnel checksums are enabled.
 791  *
 792  * @return
 793  *   Offload flags (ol_flags) in mbuf format.
 794  */
 795 static inline uint32_t
 796 rxq_cq_to_ol_flags(uint32_t flags, int csum, int csum_l2tun)
 797 {
 798         uint32_t ol_flags = 0;
 799
 800         if (csum)
 801                 ol_flags |=
 802                         mlx4_transpose(flags,
 803                                        MLX4_CQE_STATUS_IP_HDR_CSUM_OK,
 804                                        PKT_RX_IP_CKSUM_GOOD) |
 805                         mlx4_transpose(flags,
 806                                        MLX4_CQE_STATUS_TCP_UDP_CSUM_OK,
 807                                        PKT_RX_L4_CKSUM_GOOD);
 808         if ((flags & MLX4_CQE_L2_TUNNEL) && csum_l2tun)
 809                 ol_flags |=
 810                         mlx4_transpose(flags,
 811                                        MLX4_CQE_L2_TUNNEL_IPOK,
 812                                        PKT_RX_IP_CKSUM_GOOD) |
 813                         mlx4_transpose(flags,
 814                                        MLX4_CQE_L2_TUNNEL_L4_CSUM,
 815                                        PKT_RX_L4_CKSUM_GOOD);
 816         return ol_flags;
 817 }
 818
 819 /**
 820  * Extract checksum information from CQE flags.
 821  *
 822  * @param cqe
 823  *   Pointer to CQE structure.
 824  * @param csum
 825  *   Whether Rx checksums are enabled.
 826  * @param csum_l2tun
 827  *   Whether Rx L2 tunnel checksums are enabled.
 828  *
 829  * @return
 830  *   CQE checksum information.
 831  */
 832 static inline uint32_t
 833 mlx4_cqe_flags(volatile struct mlx4_cqe *cqe, int csum, int csum_l2tun)
 834 {
 835         uint32_t flags = 0;
 836
 837         /*
 838          * The relevant bits are in different locations on their
 839          * CQE fields therefore we can join them in one 32bit
 840          * variable.
 841          */
 842         if (csum)
 843                 flags = (rte_be_to_cpu_32(cqe->status) &
 844                          MLX4_CQE_STATUS_IPV4_CSUM_OK);
 845         if (csum_l2tun)
 846                 flags |= (rte_be_to_cpu_32(cqe->vlan_my_qpn) &
 847                           (MLX4_CQE_L2_TUNNEL |
 848                            MLX4_CQE_L2_TUNNEL_IPOK |
 849                            MLX4_CQE_L2_TUNNEL_L4_CSUM |
 850                            MLX4_CQE_L2_TUNNEL_IPV4));
 851         return flags;
 852 }
 853
 854 /**
 855  * Poll one CQE from CQ.
 856  *
 857  * @param rxq
 858  *   Pointer to the receive queue structure.
 859  * @param[out] out
 860  *   Just polled CQE.
 861  *
 862  * @return
 863  *   Number of bytes of the CQE, 0 in case there is no completion.
 864  */
 865 static unsigned int
 866 mlx4_cq_poll_one(struct rxq *rxq, volatile struct mlx4_cqe **out)
 867 {
 868         int ret = 0;
 869         volatile struct mlx4_cqe *cqe = NULL;
 870         struct mlx4_cq *cq = &rxq->mcq;
 871
 872         cqe = (volatile struct mlx4_cqe *)mlx4_get_cqe(cq, cq->cons_index);
 873         if (!!(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
 874             !!(cq->cons_index & cq->cqe_cnt))
 875                 goto out;
 876         /*
 877          * Make sure we read CQ entry contents after we've checked the
 878          * ownership bit.
 879          */
 880         rte_rmb();
 881         assert(!(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK));
 882         assert((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) !=
 883                MLX4_CQE_OPCODE_ERROR);
 884         ret = rte_be_to_cpu_32(cqe->byte_cnt);
 885         ++cq->cons_index;
 886 out:
 887         *out = cqe;
 888         return ret;
 889 }
 890
 891 /**
 892  * DPDK callback for Rx with scattered packets support.
 893  *
 894  * @param dpdk_rxq
 895  *   Generic pointer to Rx queue structure.
 896  * @param[out] pkts
 897  *   Array to store received packets.
 898  * @param pkts_n
 899  *   Maximum number of packets in array.
 900  *
 901  * @return
 902  *   Number of packets successfully received (<= pkts_n).
 903  */
 904 uint16_t
 905 mlx4_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
 906 {
 907         struct rxq *rxq = dpdk_rxq;
 908         const uint32_t wr_cnt = (1 << rxq->elts_n) - 1;
 909         const uint16_t sges_n = rxq->sges_n;
 910         struct rte_mbuf *pkt = NULL;
 911         struct rte_mbuf *seg = NULL;
 912         unsigned int i = 0;
 913         uint32_t rq_ci = rxq->rq_ci << sges_n;
 914         int len = 0;
 915
 916         while (pkts_n) {
 917                 volatile struct mlx4_cqe *cqe;
 918                 uint32_t idx = rq_ci & wr_cnt;
 919                 struct rte_mbuf *rep = (*rxq->elts)[idx];
 920                 volatile struct mlx4_wqe_data_seg *scat = &(*rxq->wqes)[idx];
 921
 922                 /* Update the 'next' pointer of the previous segment. */
 923                 if (pkt)
 924                         seg->next = rep;
 925                 seg = rep;
 926                 rte_prefetch0(seg);
 927                 rte_prefetch0(scat);
 928                 rep = rte_mbuf_raw_alloc(rxq->mp);
 929                 if (unlikely(rep == NULL)) {
 930                         ++rxq->stats.rx_nombuf;
 931                         if (!pkt) {
 932                                 /*
 933                                  * No buffers before we even started,
 934                                  * bail out silently.
 935                                  */
 936                                 break;
 937                         }
 938                         while (pkt != seg) {
 939                                 assert(pkt != (*rxq->elts)[idx]);
 940                                 rep = pkt->next;
 941                                 pkt->next = NULL;
 942                                 pkt->nb_segs = 1;
 943                                 rte_mbuf_raw_free(pkt);
 944                                 pkt = rep;
 945                         }
 946                         break;
 947                 }
 948                 if (!pkt) {
 949                         /* Looking for the new packet. */
 950                         len = mlx4_cq_poll_one(rxq, &cqe);
 951                         if (!len) {
 952                                 rte_mbuf_raw_free(rep);
 953                                 break;
 954                         }
 955                         if (unlikely(len < 0)) {
 956                                 /* Rx error, packet is likely too large. */
 957                                 rte_mbuf_raw_free(rep);
 958                                 ++rxq->stats.idropped;
 959                                 goto skip;
 960                         }
 961                         pkt = seg;
 962                         /* Update packet information. */
 963                         pkt->packet_type = rxq_cq_to_pkt_type(cqe);
 964                         pkt->ol_flags = 0;
 965                         pkt->pkt_len = len;
 966                         if (rxq->csum | rxq->csum_l2tun) {
 967                                 uint32_t flags =
 968                                         mlx4_cqe_flags(cqe,
 969                                                        rxq->csum,
 970                                                        rxq->csum_l2tun);
 971
 972                                 pkt->ol_flags =
 973                                         rxq_cq_to_ol_flags(flags,
 974                                                            rxq->csum,
 975                                                            rxq->csum_l2tun);
 976                         }
 977                 }
 978                 rep->nb_segs = 1;
 979                 rep->port = rxq->port_id;
 980                 rep->data_len = seg->data_len;
 981                 rep->data_off = seg->data_off;
 982                 (*rxq->elts)[idx] = rep;
 983                 /*
 984                  * Fill NIC descriptor with the new buffer. The lkey and size
 985                  * of the buffers are already known, only the buffer address
 986                  * changes.
 987                  */
 988                 scat->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
 989                 if (len > seg->data_len) {
 990                         len -= seg->data_len;
 991                         ++pkt->nb_segs;
 992                         ++rq_ci;
 993                         continue;
 994                 }
 995                 /* The last segment. */
 996                 seg->data_len = len;
 997                 /* Increment bytes counter. */
 998                 rxq->stats.ibytes += pkt->pkt_len;
 999                 /* Return packet. */
1000                 *(pkts++) = pkt;
1001                 pkt = NULL;
1002                 --pkts_n;
1003                 ++i;
1004 skip:
1005                 /* Align consumer index to the next stride. */
1006                 rq_ci >>= sges_n;
1007                 ++rq_ci;
1008                 rq_ci <<= sges_n;
1009         }
1010         if (unlikely(i == 0 && (rq_ci >> sges_n) == rxq->rq_ci))
1011                 return 0;
1012         /* Update the consumer index. */
1013         rxq->rq_ci = rq_ci >> sges_n;
1014         rte_wmb();
1015         *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1016         *rxq->mcq.set_ci_db =
1017                 rte_cpu_to_be_32(rxq->mcq.cons_index & MLX4_CQ_DB_CI_MASK);
1018         /* Increment packets counter. */
1019         rxq->stats.ipackets += i;
1020         return i;
1021 }
1022
1023 /**
1024  * Dummy DPDK callback for Tx.
1025  *
1026  * This function is used to temporarily replace the real callback during
1027  * unsafe control operations on the queue, or in case of error.
1028  *
1029  * @param dpdk_txq
1030  *   Generic pointer to Tx queue structure.
1031  * @param[in] pkts
1032  *   Packets to transmit.
1033  * @param pkts_n
1034  *   Number of packets in array.
1035  *
1036  * @return
1037  *   Number of packets successfully transmitted (<= pkts_n).
1038  */
1039 uint16_t
1040 mlx4_tx_burst_removed(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1041 {
1042         (void)dpdk_txq;
1043         (void)pkts;
1044         (void)pkts_n;
1045         return 0;
1046 }
1047
1048 /**
1049  * Dummy DPDK callback for Rx.
1050  *
1051  * This function is used to temporarily replace the real callback during
1052  * unsafe control operations on the queue, or in case of error.
1053  *
1054  * @param dpdk_rxq
1055  *   Generic pointer to Rx queue structure.
1056  * @param[out] pkts
1057  *   Array to store received packets.
1058  * @param pkts_n
1059  *   Maximum number of packets in array.
1060  *
1061  * @return
1062  *   Number of packets successfully received (<= pkts_n).
1063  */
1064 uint16_t
1065 mlx4_rx_burst_removed(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1066 {
1067         (void)dpdk_rxq;
1068         (void)pkts;
1069         (void)pkts_n;
1070         return 0;
1071 }