drivers/net/mlx4/mlx4_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright 2017 6WIND S.A.
   5  *   Copyright 2017 Mellanox
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of 6WIND S.A. nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 /**
  35  * @file
  36  * Data plane functions for mlx4 driver.
  37  */
  38
  39 #include <assert.h>
  40 #include <stdint.h>
  41 #include <string.h>
  42
  43 /* Verbs headers do not support -pedantic. */
  44 #ifdef PEDANTIC
  45 #pragma GCC diagnostic ignored "-Wpedantic"
  46 #endif
  47 #include <infiniband/verbs.h>
  48 #ifdef PEDANTIC
  49 #pragma GCC diagnostic error "-Wpedantic"
  50 #endif
  51
  52 #include <rte_branch_prediction.h>
  53 #include <rte_common.h>
  54 #include <rte_io.h>
  55 #include <rte_mbuf.h>
  56 #include <rte_mempool.h>
  57 #include <rte_prefetch.h>
  58
  59 #include "mlx4.h"
  60 #include "mlx4_prm.h"
  61 #include "mlx4_rxtx.h"
  62 #include "mlx4_utils.h"
  63
  64 /**
  65  * Pointer-value pair structure used in tx_post_send for saving the first
  66  * DWORD (32 byte) of a TXBB.
  67  */
  68 struct pv {
  69         volatile struct mlx4_wqe_data_seg *dseg;
  70         uint32_t val;
  71 };
  72
  73 /** A table to translate Rx completion flags to packet type. */
  74 uint32_t mlx4_ptype_table[0x100] __rte_cache_aligned = {
  75         /*
  76          * The index to the array should have:
  77          *  bit[7] - MLX4_CQE_L2_TUNNEL
  78          *  bit[6] - MLX4_CQE_L2_TUNNEL_IPV4
  79          *  bit[5] - MLX4_CQE_STATUS_UDP
  80          *  bit[4] - MLX4_CQE_STATUS_TCP
  81          *  bit[3] - MLX4_CQE_STATUS_IPV4OPT
  82          *  bit[2] - MLX4_CQE_STATUS_IPV6
  83          *  bit[1] - MLX4_CQE_STATUS_IPV4F
  84          *  bit[0] - MLX4_CQE_STATUS_IPV4
  85          * giving a total of up to 256 entries.
  86          */
  87         [0x00] = RTE_PTYPE_L2_ETHER,
  88         [0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
  89         [0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  90                      RTE_PTYPE_L4_FRAG,
  91         [0x03] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  92                      RTE_PTYPE_L4_FRAG,
  93         [0x04] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
  94         [0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT,
  95         [0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
  96                      RTE_PTYPE_L4_FRAG,
  97         [0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  98                      RTE_PTYPE_L4_TCP,
  99         [0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 100                      RTE_PTYPE_L4_TCP,
 101         [0x14] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 102                      RTE_PTYPE_L4_TCP,
 103         [0x18] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
 104                      RTE_PTYPE_L4_TCP,
 105         [0x19] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
 106                      RTE_PTYPE_L4_TCP,
 107         [0x1a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
 108                      RTE_PTYPE_L4_TCP,
 109         [0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 110                      RTE_PTYPE_L4_UDP,
 111         [0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 112                      RTE_PTYPE_L4_UDP,
 113         [0x24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 114                      RTE_PTYPE_L4_UDP,
 115         [0x28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
 116                      RTE_PTYPE_L4_UDP,
 117         [0x29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
 118                      RTE_PTYPE_L4_UDP,
 119         [0x2a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
 120                      RTE_PTYPE_L4_UDP,
 121         /* Tunneled - L3 IPV6 */
 122         [0x80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 123         [0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 124                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
 125         [0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 126                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 127                      RTE_PTYPE_INNER_L4_FRAG,
 128         [0x83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 129                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 130                      RTE_PTYPE_INNER_L4_FRAG,
 131         [0x84] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 132                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
 133         [0x88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 134                      RTE_PTYPE_INNER_L3_IPV4_EXT,
 135         [0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 136                      RTE_PTYPE_INNER_L3_IPV4_EXT,
 137         [0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 138                      RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_FRAG,
 139         /* Tunneled - L3 IPV6, TCP */
 140         [0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 141                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 142                      RTE_PTYPE_INNER_L4_TCP,
 143         [0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 144                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 145                      RTE_PTYPE_INNER_L4_FRAG |
 146                      RTE_PTYPE_INNER_L4_TCP,
 147         [0x93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 148                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 149                      RTE_PTYPE_INNER_L4_FRAG |
 150                      RTE_PTYPE_INNER_L4_TCP,
 151         [0x94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 152                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 153                      RTE_PTYPE_INNER_L4_TCP,
 154         [0x98] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 155                      RTE_PTYPE_INNER_L3_IPV4_EXT |
 156                      RTE_PTYPE_INNER_L4_TCP,
 157         [0x99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 158                      RTE_PTYPE_INNER_L3_IPV4_EXT |
 159                      RTE_PTYPE_INNER_L4_TCP,
 160         [0x9a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 161                      RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_FRAG |
 162                      RTE_PTYPE_INNER_L4_TCP,
 163         /* Tunneled - L3 IPV6, UDP */
 164         [0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 165                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 166                      RTE_PTYPE_INNER_L4_UDP,
 167         [0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 168                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 169                      RTE_PTYPE_INNER_L4_FRAG |
 170                      RTE_PTYPE_INNER_L4_UDP,
 171         [0xa3] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 172                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 173                      RTE_PTYPE_INNER_L4_FRAG |
 174                      RTE_PTYPE_INNER_L4_UDP,
 175         [0xa4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 176                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 177                      RTE_PTYPE_INNER_L4_UDP,
 178         [0xa8] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 179                      RTE_PTYPE_INNER_L3_IPV4_EXT |
 180                      RTE_PTYPE_INNER_L4_UDP,
 181         [0xa9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 182                      RTE_PTYPE_INNER_L3_IPV4_EXT |
 183                      RTE_PTYPE_INNER_L4_UDP,
 184         [0xaa] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 185                      RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_FRAG |
 186                      RTE_PTYPE_INNER_L4_UDP,
 187         /* Tunneled - L3 IPV4 */
 188         [0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 189         [0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 190                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
 191         [0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 192                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 193                      RTE_PTYPE_INNER_L4_FRAG,
 194         [0xc3] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 195                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 196                      RTE_PTYPE_INNER_L4_FRAG,
 197         [0xc4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 198                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
 199         [0xc8] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 200                      RTE_PTYPE_INNER_L3_IPV4_EXT,
 201         [0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 202                      RTE_PTYPE_INNER_L3_IPV4_EXT,
 203         [0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 204                      RTE_PTYPE_INNER_L3_IPV4_EXT |
 205                      RTE_PTYPE_INNER_L4_FRAG,
 206         /* Tunneled - L3 IPV4, TCP */
 207         [0xd0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 208                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 209                      RTE_PTYPE_INNER_L4_TCP,
 210         [0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 211                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 212                      RTE_PTYPE_INNER_L4_TCP,
 213         [0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 214                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 215                      RTE_PTYPE_INNER_L4_FRAG |
 216                      RTE_PTYPE_INNER_L4_TCP,
 217         [0xd3] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 218                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 219                      RTE_PTYPE_INNER_L4_FRAG |
 220                      RTE_PTYPE_INNER_L4_TCP,
 221         [0xd4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 222                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 223                      RTE_PTYPE_INNER_L4_TCP,
 224         [0xd8] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 225                      RTE_PTYPE_INNER_L3_IPV4_EXT |
 226                      RTE_PTYPE_INNER_L4_TCP,
 227         [0xd9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 228                      RTE_PTYPE_INNER_L3_IPV4_EXT |
 229                      RTE_PTYPE_INNER_L4_TCP,
 230         [0xda] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 231                      RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_FRAG |
 232                      RTE_PTYPE_INNER_L4_TCP,
 233         /* Tunneled - L3 IPV4, UDP */
 234         [0xe0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 235                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 236                      RTE_PTYPE_INNER_L4_UDP,
 237         [0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 238                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 239                      RTE_PTYPE_INNER_L4_UDP,
 240         [0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 241                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 242                      RTE_PTYPE_INNER_L4_FRAG |
 243                      RTE_PTYPE_INNER_L4_UDP,
 244         [0xe3] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 245                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 246                      RTE_PTYPE_INNER_L4_FRAG |
 247                      RTE_PTYPE_INNER_L4_UDP,
 248         [0xe4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 249                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 250                      RTE_PTYPE_INNER_L4_UDP,
 251         [0xe8] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 252                      RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_UDP,
 253         [0xe9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 254                      RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_UDP,
 255         [0xea] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 256                      RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_FRAG |
 257                      RTE_PTYPE_INNER_L4_UDP,
 258 };
 259
 260 /**
 261  * Stamp TXBB burst so it won't be reused by the HW.
 262  *
 263  * Routine is used when freeing WQE used by the chip or when failing
 264  * building an WQ entry has failed leaving partial information on the queue.
 265  *
 266  * @param sq
 267  *   Pointer to the SQ structure.
 268  * @param start
 269  *   Pointer to the first TXBB to stamp.
 270  * @param end
 271  *   Pointer to the followed end TXBB to stamp.
 272  *
 273  * @return
 274  *   Stamping burst size in byte units.
 275  */
 276 static uint32_t
 277 mlx4_txq_stamp_freed_wqe(struct mlx4_sq *sq, volatile uint32_t *start,
 278                          volatile uint32_t *end)
 279 {
 280         uint32_t stamp = sq->stamp;
 281         int32_t size = (intptr_t)end - (intptr_t)start;
 282
 283         assert(start != end);
 284         /* Hold SQ ring wrap around. */
 285         if (size < 0) {
 286                 size = (int32_t)sq->size + size;
 287                 do {
 288                         *start = stamp;
 289                         start += MLX4_SQ_STAMP_DWORDS;
 290                 } while (start != (volatile uint32_t *)sq->eob);
 291                 start = (volatile uint32_t *)sq->buf;
 292                 /* Flip invalid stamping ownership. */
 293                 stamp ^= RTE_BE32(0x1 << MLX4_SQ_OWNER_BIT);
 294                 sq->stamp = stamp;
 295                 if (start == end)
 296                         return size;
 297         }
 298         do {
 299                 *start = stamp;
 300                 start += MLX4_SQ_STAMP_DWORDS;
 301         } while (start != end);
 302         return (uint32_t)size;
 303 }
 304
 305 /**
 306  * Manage Tx completions.
 307  *
 308  * When sending a burst, mlx4_tx_burst() posts several WRs.
 309  * To improve performance, a completion event is only required once every
 310  * MLX4_PMD_TX_PER_COMP_REQ sends. Doing so discards completion information
 311  * for other WRs, but this information would not be used anyway.
 312  *
 313  * @param txq
 314  *   Pointer to Tx queue structure.
 315  */
 316 static void
 317 mlx4_txq_complete(struct txq *txq, const unsigned int elts_n,
 318                                   struct mlx4_sq *sq)
 319 {
 320         unsigned int elts_tail = txq->elts_tail;
 321         struct mlx4_cq *cq = &txq->mcq;
 322         volatile struct mlx4_cqe *cqe;
 323         uint32_t completed;
 324         uint32_t cons_index = cq->cons_index;
 325         volatile uint32_t *first_txbb;
 326
 327         /*
 328          * Traverse over all CQ entries reported and handle each WQ entry
 329          * reported by them.
 330          */
 331         do {
 332                 cqe = (volatile struct mlx4_cqe *)mlx4_get_cqe(cq, cons_index);
 333                 if (unlikely(!!(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
 334                     !!(cons_index & cq->cqe_cnt)))
 335                         break;
 336 #ifndef NDEBUG
 337                 /*
 338                  * Make sure we read the CQE after we read the ownership bit.
 339                  */
 340                 rte_io_rmb();
 341                 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
 342                              MLX4_CQE_OPCODE_ERROR)) {
 343                         volatile struct mlx4_err_cqe *cqe_err =
 344                                 (volatile struct mlx4_err_cqe *)cqe;
 345                         ERROR("%p CQE error - vendor syndrome: 0x%x"
 346                               " syndrome: 0x%x\n",
 347                               (void *)txq, cqe_err->vendor_err,
 348                               cqe_err->syndrome);
 349                         break;
 350                 }
 351 #endif /* NDEBUG */
 352                 cons_index++;
 353         } while (1);
 354         completed = (cons_index - cq->cons_index) * txq->elts_comp_cd_init;
 355         if (unlikely(!completed))
 356                 return;
 357         /* First stamping address is the end of the last one. */
 358         first_txbb = (&(*txq->elts)[elts_tail])->eocb;
 359         elts_tail += completed;
 360         if (elts_tail >= elts_n)
 361                 elts_tail -= elts_n;
 362         /* The new tail element holds the end address. */
 363         sq->remain_size += mlx4_txq_stamp_freed_wqe(sq, first_txbb,
 364                 (&(*txq->elts)[elts_tail])->eocb);
 365         /* Update CQ consumer index. */
 366         cq->cons_index = cons_index;
 367         *cq->set_ci_db = rte_cpu_to_be_32(cons_index & MLX4_CQ_DB_CI_MASK);
 368         txq->elts_comp -= completed;
 369         txq->elts_tail = elts_tail;
 370 }
 371
 372 /**
 373  * Get memory pool (MP) from mbuf. If mbuf is indirect, the pool from which
 374  * the cloned mbuf is allocated is returned instead.
 375  *
 376  * @param buf
 377  *   Pointer to mbuf.
 378  *
 379  * @return
 380  *   Memory pool where data is located for given mbuf.
 381  */
 382 static struct rte_mempool *
 383 mlx4_txq_mb2mp(struct rte_mbuf *buf)
 384 {
 385         if (unlikely(RTE_MBUF_INDIRECT(buf)))
 386                 return rte_mbuf_from_indirect(buf)->pool;
 387         return buf->pool;
 388 }
 389
 390 /**
 391  * Write Tx data segment to the SQ.
 392  *
 393  * @param dseg
 394  *   Pointer to data segment in SQ.
 395  * @param lkey
 396  *   Memory region lkey.
 397  * @param addr
 398  *   Data address.
 399  * @param byte_count
 400  *   Big endian bytes count of the data to send.
 401  */
 402 static inline void
 403 mlx4_fill_tx_data_seg(volatile struct mlx4_wqe_data_seg *dseg,
 404                        uint32_t lkey, uintptr_t addr, rte_be32_t  byte_count)
 405 {
 406         dseg->addr = rte_cpu_to_be_64(addr);
 407         dseg->lkey = rte_cpu_to_be_32(lkey);
 408 #if RTE_CACHE_LINE_SIZE < 64
 409         /*
 410          * Need a barrier here before writing the byte_count
 411          * fields to make sure that all the data is visible
 412          * before the byte_count field is set.
 413          * Otherwise, if the segment begins a new cacheline,
 414          * the HCA prefetcher could grab the 64-byte chunk and
 415          * get a valid (!= 0xffffffff) byte count but stale
 416          * data, and end up sending the wrong data.
 417          */
 418         rte_io_wmb();
 419 #endif /* RTE_CACHE_LINE_SIZE */
 420         dseg->byte_count = byte_count;
 421 }
 422
 423 /**
 424  * Write data segments of multi-segment packet.
 425  *
 426  * @param buf
 427  *   Pointer to the first packet mbuf.
 428  * @param txq
 429  *   Pointer to Tx queue structure.
 430  * @param ctrl
 431  *   Pointer to the WQE control segment.
 432  *
 433  * @return
 434  *   Pointer to the next WQE control segment on success, NULL otherwise.
 435  */
 436 static volatile struct mlx4_wqe_ctrl_seg *
 437 mlx4_tx_burst_segs(struct rte_mbuf *buf, struct txq *txq,
 438                    volatile struct mlx4_wqe_ctrl_seg *ctrl)
 439 {
 440         struct pv *pv = (struct pv *)txq->bounce_buf;
 441         struct mlx4_sq *sq = &txq->msq;
 442         struct rte_mbuf *sbuf = buf;
 443         uint32_t lkey;
 444         int pv_counter = 0;
 445         int nb_segs = buf->nb_segs;
 446         uint32_t wqe_size;
 447         volatile struct mlx4_wqe_data_seg *dseg =
 448                 (volatile struct mlx4_wqe_data_seg *)(ctrl + 1);
 449
 450         ctrl->fence_size = 1 + nb_segs;
 451         wqe_size = RTE_ALIGN((uint32_t)(ctrl->fence_size << MLX4_SEG_SHIFT),
 452                              MLX4_TXBB_SIZE);
 453         /* Validate WQE size and WQE space in the send queue. */
 454         if (sq->remain_size < wqe_size ||
 455             wqe_size > MLX4_MAX_WQE_SIZE)
 456                 return NULL;
 457         /*
 458          * Fill the data segments with buffer information.
 459          * First WQE TXBB head segment is always control segment,
 460          * so jump to tail TXBB data segments code for the first
 461          * WQE data segments filling.
 462          */
 463         goto txbb_tail_segs;
 464 txbb_head_seg:
 465         /* Memory region key (big endian) for this memory pool. */
 466         lkey = mlx4_txq_mp2mr(txq, mlx4_txq_mb2mp(sbuf));
 467         if (unlikely(lkey == (uint32_t)-1)) {
 468                 DEBUG("%p: unable to get MP <-> MR association",
 469                       (void *)txq);
 470                 return NULL;
 471         }
 472         /* Handle WQE wraparound. */
 473         if (dseg >=
 474                 (volatile struct mlx4_wqe_data_seg *)sq->eob)
 475                 dseg = (volatile struct mlx4_wqe_data_seg *)
 476                         sq->buf;
 477         dseg->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(sbuf, uintptr_t));
 478         dseg->lkey = rte_cpu_to_be_32(lkey);
 479         /*
 480          * This data segment starts at the beginning of a new
 481          * TXBB, so we need to postpone its byte_count writing
 482          * for later.
 483          */
 484         pv[pv_counter].dseg = dseg;
 485         /*
 486          * Zero length segment is treated as inline segment
 487          * with zero data.
 488          */
 489         pv[pv_counter++].val = rte_cpu_to_be_32(sbuf->data_len ?
 490                                                 sbuf->data_len : 0x80000000);
 491         sbuf = sbuf->next;
 492         dseg++;
 493         nb_segs--;
 494 txbb_tail_segs:
 495         /* Jump to default if there are more than two segments remaining. */
 496         switch (nb_segs) {
 497         default:
 498                 lkey = mlx4_txq_mp2mr(txq, mlx4_txq_mb2mp(sbuf));
 499                 if (unlikely(lkey == (uint32_t)-1)) {
 500                         DEBUG("%p: unable to get MP <-> MR association",
 501                               (void *)txq);
 502                         return NULL;
 503                 }
 504                 mlx4_fill_tx_data_seg(dseg, lkey,
 505                                       rte_pktmbuf_mtod(sbuf, uintptr_t),
 506                                       rte_cpu_to_be_32(sbuf->data_len ?
 507                                                        sbuf->data_len :
 508                                                        0x80000000));
 509                 sbuf = sbuf->next;
 510                 dseg++;
 511                 nb_segs--;
 512                 /* fallthrough */
 513         case 2:
 514                 lkey = mlx4_txq_mp2mr(txq, mlx4_txq_mb2mp(sbuf));
 515                 if (unlikely(lkey == (uint32_t)-1)) {
 516                         DEBUG("%p: unable to get MP <-> MR association",
 517                               (void *)txq);
 518                         return NULL;
 519                 }
 520                 mlx4_fill_tx_data_seg(dseg, lkey,
 521                                       rte_pktmbuf_mtod(sbuf, uintptr_t),
 522                                       rte_cpu_to_be_32(sbuf->data_len ?
 523                                                        sbuf->data_len :
 524                                                        0x80000000));
 525                 sbuf = sbuf->next;
 526                 dseg++;
 527                 nb_segs--;
 528                 /* fallthrough */
 529         case 1:
 530                 lkey = mlx4_txq_mp2mr(txq, mlx4_txq_mb2mp(sbuf));
 531                 if (unlikely(lkey == (uint32_t)-1)) {
 532                         DEBUG("%p: unable to get MP <-> MR association",
 533                               (void *)txq);
 534                         return NULL;
 535                 }
 536                 mlx4_fill_tx_data_seg(dseg, lkey,
 537                                       rte_pktmbuf_mtod(sbuf, uintptr_t),
 538                                       rte_cpu_to_be_32(sbuf->data_len ?
 539                                                        sbuf->data_len :
 540                                                        0x80000000));
 541                 nb_segs--;
 542                 if (nb_segs) {
 543                         sbuf = sbuf->next;
 544                         dseg++;
 545                         goto txbb_head_seg;
 546                 }
 547                 /* fallthrough */
 548         case 0:
 549                 break;
 550         }
 551         /* Write the first DWORD of each TXBB save earlier. */
 552         if (pv_counter) {
 553                 /* Need a barrier here before writing the byte_count. */
 554                 rte_io_wmb();
 555                 for (--pv_counter; pv_counter  >= 0; pv_counter--)
 556                         pv[pv_counter].dseg->byte_count = pv[pv_counter].val;
 557         }
 558         sq->remain_size -= wqe_size;
 559         /* Align next WQE address to the next TXBB. */
 560         return (volatile struct mlx4_wqe_ctrl_seg *)
 561                 ((volatile uint8_t *)ctrl + wqe_size);
 562 }
 563
 564 /**
 565  * DPDK callback for Tx.
 566  *
 567  * @param dpdk_txq
 568  *   Generic pointer to Tx queue structure.
 569  * @param[in] pkts
 570  *   Packets to transmit.
 571  * @param pkts_n
 572  *   Number of packets in array.
 573  *
 574  * @return
 575  *   Number of packets successfully transmitted (<= pkts_n).
 576  */
 577 uint16_t
 578 mlx4_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 579 {
 580         struct txq *txq = (struct txq *)dpdk_txq;
 581         unsigned int elts_head = txq->elts_head;
 582         const unsigned int elts_n = txq->elts_n;
 583         unsigned int bytes_sent = 0;
 584         unsigned int i;
 585         unsigned int max;
 586         struct mlx4_sq *sq = &txq->msq;
 587         volatile struct mlx4_wqe_ctrl_seg *ctrl;
 588         struct txq_elt *elt;
 589
 590         assert(txq->elts_comp_cd != 0);
 591         if (likely(txq->elts_comp != 0))
 592                 mlx4_txq_complete(txq, elts_n, sq);
 593         max = (elts_n - (elts_head - txq->elts_tail));
 594         if (max > elts_n)
 595                 max -= elts_n;
 596         assert(max >= 1);
 597         assert(max <= elts_n);
 598         /* Always leave one free entry in the ring. */
 599         --max;
 600         if (max > pkts_n)
 601                 max = pkts_n;
 602         elt = &(*txq->elts)[elts_head];
 603         /* First Tx burst element saves the next WQE control segment. */
 604         ctrl = elt->wqe;
 605         for (i = 0; (i != max); ++i) {
 606                 struct rte_mbuf *buf = pkts[i];
 607                 unsigned int elts_head_next =
 608                         (((elts_head + 1) == elts_n) ? 0 : elts_head + 1);
 609                 struct txq_elt *elt_next = &(*txq->elts)[elts_head_next];
 610                 uint32_t owner_opcode = sq->owner_opcode;
 611                 volatile struct mlx4_wqe_data_seg *dseg =
 612                                 (volatile struct mlx4_wqe_data_seg *)(ctrl + 1);
 613                 volatile struct mlx4_wqe_ctrl_seg *ctrl_next;
 614                 union {
 615                         uint32_t flags;
 616                         uint16_t flags16[2];
 617                 } srcrb;
 618                 uint32_t lkey;
 619
 620                 /* Clean up old buffer. */
 621                 if (likely(elt->buf != NULL)) {
 622                         struct rte_mbuf *tmp = elt->buf;
 623
 624 #ifndef NDEBUG
 625                         /* Poisoning. */
 626                         memset(&elt->buf, 0x66, sizeof(struct rte_mbuf *));
 627 #endif
 628                         /* Faster than rte_pktmbuf_free(). */
 629                         do {
 630                                 struct rte_mbuf *next = tmp->next;
 631
 632                                 rte_pktmbuf_free_seg(tmp);
 633                                 tmp = next;
 634                         } while (tmp != NULL);
 635                 }
 636                 RTE_MBUF_PREFETCH_TO_FREE(elt_next->buf);
 637                 if (buf->nb_segs == 1) {
 638                         /* Validate WQE space in the send queue. */
 639                         if (sq->remain_size < MLX4_TXBB_SIZE) {
 640                                 elt->buf = NULL;
 641                                 break;
 642                         }
 643                         lkey = mlx4_txq_mp2mr(txq, mlx4_txq_mb2mp(buf));
 644                         if (unlikely(lkey == (uint32_t)-1)) {
 645                                 /* MR does not exist. */
 646                                 DEBUG("%p: unable to get MP <-> MR association",
 647                                       (void *)txq);
 648                                 elt->buf = NULL;
 649                                 break;
 650                         }
 651                         mlx4_fill_tx_data_seg(dseg++, lkey,
 652                                               rte_pktmbuf_mtod(buf, uintptr_t),
 653                                               rte_cpu_to_be_32(buf->data_len));
 654                         /* Set WQE size in 16-byte units. */
 655                         ctrl->fence_size = 0x2;
 656                         sq->remain_size -= MLX4_TXBB_SIZE;
 657                         /* Align next WQE address to the next TXBB. */
 658                         ctrl_next = ctrl + 0x4;
 659                 } else {
 660                         ctrl_next = mlx4_tx_burst_segs(buf, txq, ctrl);
 661                         if (!ctrl_next) {
 662                                 elt->buf = NULL;
 663                                 break;
 664                         }
 665                 }
 666                 /* Hold SQ ring wrap around. */
 667                 if ((volatile uint8_t *)ctrl_next >= sq->eob) {
 668                         ctrl_next = (volatile struct mlx4_wqe_ctrl_seg *)
 669                                 ((volatile uint8_t *)ctrl_next - sq->size);
 670                         /* Flip HW valid ownership. */
 671                         sq->owner_opcode ^= 0x1 << MLX4_SQ_OWNER_BIT;
 672                 }
 673                 /*
 674                  * For raw Ethernet, the SOLICIT flag is used to indicate
 675                  * that no ICRC should be calculated.
 676                  */
 677                 if (--txq->elts_comp_cd == 0) {
 678                         /* Save the completion burst end address. */
 679                         elt_next->eocb = (volatile uint32_t *)ctrl_next;
 680                         txq->elts_comp_cd = txq->elts_comp_cd_init;
 681                         srcrb.flags = RTE_BE32(MLX4_WQE_CTRL_SOLICIT |
 682                                                MLX4_WQE_CTRL_CQ_UPDATE);
 683                 } else {
 684                         srcrb.flags = RTE_BE32(MLX4_WQE_CTRL_SOLICIT);
 685                 }
 686                 /* Enable HW checksum offload if requested */
 687                 if (txq->csum &&
 688                     (buf->ol_flags &
 689                      (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))) {
 690                         const uint64_t is_tunneled = (buf->ol_flags &
 691                                                       (PKT_TX_TUNNEL_GRE |
 692                                                        PKT_TX_TUNNEL_VXLAN));
 693
 694                         if (is_tunneled && txq->csum_l2tun) {
 695                                 owner_opcode |= MLX4_WQE_CTRL_IIP_HDR_CSUM |
 696                                                 MLX4_WQE_CTRL_IL4_HDR_CSUM;
 697                                 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
 698                                         srcrb.flags |=
 699                                             RTE_BE32(MLX4_WQE_CTRL_IP_HDR_CSUM);
 700                         } else {
 701                                 srcrb.flags |=
 702                                         RTE_BE32(MLX4_WQE_CTRL_IP_HDR_CSUM |
 703                                                 MLX4_WQE_CTRL_TCP_UDP_CSUM);
 704                         }
 705                 }
 706                 if (txq->lb) {
 707                         /*
 708                          * Copy destination MAC address to the WQE, this allows
 709                          * loopback in eSwitch, so that VFs and PF can
 710                          * communicate with each other.
 711                          */
 712                         srcrb.flags16[0] = *(rte_pktmbuf_mtod(buf, uint16_t *));
 713                         ctrl->imm = *(rte_pktmbuf_mtod_offset(buf, uint32_t *,
 714                                               sizeof(uint16_t)));
 715                 } else {
 716                         ctrl->imm = 0;
 717                 }
 718                 ctrl->srcrb_flags = srcrb.flags;
 719                 /*
 720                  * Make sure descriptor is fully written before
 721                  * setting ownership bit (because HW can start
 722                  * executing as soon as we do).
 723                  */
 724                 rte_io_wmb();
 725                 ctrl->owner_opcode = rte_cpu_to_be_32(owner_opcode);
 726                 elt->buf = buf;
 727                 bytes_sent += buf->pkt_len;
 728                 elts_head = elts_head_next;
 729                 ctrl = ctrl_next;
 730                 elt = elt_next;
 731         }
 732         /* Take a shortcut if nothing must be sent. */
 733         if (unlikely(i == 0))
 734                 return 0;
 735         /* Save WQE address of the next Tx burst element. */
 736         elt->wqe = ctrl;
 737         /* Increment send statistics counters. */
 738         txq->stats.opackets += i;
 739         txq->stats.obytes += bytes_sent;
 740         /* Make sure that descriptors are written before doorbell record. */
 741         rte_wmb();
 742         /* Ring QP doorbell. */
 743         rte_write32(txq->msq.doorbell_qpn, txq->msq.db);
 744         txq->elts_head = elts_head;
 745         txq->elts_comp += i;
 746         return i;
 747 }
 748
 749 /**
 750  * Translate Rx completion flags to packet type.
 751  *
 752  * @param[in] cqe
 753  *   Pointer to CQE.
 754  *
 755  * @return
 756  *   Packet type for struct rte_mbuf.
 757  */
 758 static inline uint32_t
 759 rxq_cq_to_pkt_type(volatile struct mlx4_cqe *cqe,
 760                    uint32_t l2tun_offload)
 761 {
 762         uint8_t idx = 0;
 763         uint32_t pinfo = rte_be_to_cpu_32(cqe->vlan_my_qpn);
 764         uint32_t status = rte_be_to_cpu_32(cqe->status);
 765
 766         /*
 767          * The index to the array should have:
 768          *  bit[7] - MLX4_CQE_L2_TUNNEL
 769          *  bit[6] - MLX4_CQE_L2_TUNNEL_IPV4
 770          */
 771         if (l2tun_offload && (pinfo & MLX4_CQE_L2_TUNNEL))
 772                 idx |= ((pinfo & MLX4_CQE_L2_TUNNEL) >> 20) |
 773                        ((pinfo & MLX4_CQE_L2_TUNNEL_IPV4) >> 19);
 774         /*
 775          * The index to the array should have:
 776          *  bit[5] - MLX4_CQE_STATUS_UDP
 777          *  bit[4] - MLX4_CQE_STATUS_TCP
 778          *  bit[3] - MLX4_CQE_STATUS_IPV4OPT
 779          *  bit[2] - MLX4_CQE_STATUS_IPV6
 780          *  bit[1] - MLX4_CQE_STATUS_IPV4F
 781          *  bit[0] - MLX4_CQE_STATUS_IPV4
 782          * giving a total of up to 256 entries.
 783          */
 784         idx |= ((status & MLX4_CQE_STATUS_PTYPE_MASK) >> 22);
 785         return mlx4_ptype_table[idx];
 786 }
 787
 788 /**
 789  * Translate Rx completion flags to offload flags.
 790  *
 791  * @param flags
 792  *   Rx completion flags returned by mlx4_cqe_flags().
 793  * @param csum
 794  *   Whether Rx checksums are enabled.
 795  * @param csum_l2tun
 796  *   Whether Rx L2 tunnel checksums are enabled.
 797  *
 798  * @return
 799  *   Offload flags (ol_flags) in mbuf format.
 800  */
 801 static inline uint32_t
 802 rxq_cq_to_ol_flags(uint32_t flags, int csum, int csum_l2tun)
 803 {
 804         uint32_t ol_flags = 0;
 805
 806         if (csum)
 807                 ol_flags |=
 808                         mlx4_transpose(flags,
 809                                        MLX4_CQE_STATUS_IP_HDR_CSUM_OK,
 810                                        PKT_RX_IP_CKSUM_GOOD) |
 811                         mlx4_transpose(flags,
 812                                        MLX4_CQE_STATUS_TCP_UDP_CSUM_OK,
 813                                        PKT_RX_L4_CKSUM_GOOD);
 814         if ((flags & MLX4_CQE_L2_TUNNEL) && csum_l2tun)
 815                 ol_flags |=
 816                         mlx4_transpose(flags,
 817                                        MLX4_CQE_L2_TUNNEL_IPOK,
 818                                        PKT_RX_IP_CKSUM_GOOD) |
 819                         mlx4_transpose(flags,
 820                                        MLX4_CQE_L2_TUNNEL_L4_CSUM,
 821                                        PKT_RX_L4_CKSUM_GOOD);
 822         return ol_flags;
 823 }
 824
 825 /**
 826  * Extract checksum information from CQE flags.
 827  *
 828  * @param cqe
 829  *   Pointer to CQE structure.
 830  * @param csum
 831  *   Whether Rx checksums are enabled.
 832  * @param csum_l2tun
 833  *   Whether Rx L2 tunnel checksums are enabled.
 834  *
 835  * @return
 836  *   CQE checksum information.
 837  */
 838 static inline uint32_t
 839 mlx4_cqe_flags(volatile struct mlx4_cqe *cqe, int csum, int csum_l2tun)
 840 {
 841         uint32_t flags = 0;
 842
 843         /*
 844          * The relevant bits are in different locations on their
 845          * CQE fields therefore we can join them in one 32bit
 846          * variable.
 847          */
 848         if (csum)
 849                 flags = (rte_be_to_cpu_32(cqe->status) &
 850                          MLX4_CQE_STATUS_IPV4_CSUM_OK);
 851         if (csum_l2tun)
 852                 flags |= (rte_be_to_cpu_32(cqe->vlan_my_qpn) &
 853                           (MLX4_CQE_L2_TUNNEL |
 854                            MLX4_CQE_L2_TUNNEL_IPOK |
 855                            MLX4_CQE_L2_TUNNEL_L4_CSUM |
 856                            MLX4_CQE_L2_TUNNEL_IPV4));
 857         return flags;
 858 }
 859
 860 /**
 861  * Poll one CQE from CQ.
 862  *
 863  * @param rxq
 864  *   Pointer to the receive queue structure.
 865  * @param[out] out
 866  *   Just polled CQE.
 867  *
 868  * @return
 869  *   Number of bytes of the CQE, 0 in case there is no completion.
 870  */
 871 static unsigned int
 872 mlx4_cq_poll_one(struct rxq *rxq, volatile struct mlx4_cqe **out)
 873 {
 874         int ret = 0;
 875         volatile struct mlx4_cqe *cqe = NULL;
 876         struct mlx4_cq *cq = &rxq->mcq;
 877
 878         cqe = (volatile struct mlx4_cqe *)mlx4_get_cqe(cq, cq->cons_index);
 879         if (!!(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
 880             !!(cq->cons_index & cq->cqe_cnt))
 881                 goto out;
 882         /*
 883          * Make sure we read CQ entry contents after we've checked the
 884          * ownership bit.
 885          */
 886         rte_rmb();
 887         assert(!(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK));
 888         assert((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) !=
 889                MLX4_CQE_OPCODE_ERROR);
 890         ret = rte_be_to_cpu_32(cqe->byte_cnt);
 891         ++cq->cons_index;
 892 out:
 893         *out = cqe;
 894         return ret;
 895 }
 896
 897 /**
 898  * DPDK callback for Rx with scattered packets support.
 899  *
 900  * @param dpdk_rxq
 901  *   Generic pointer to Rx queue structure.
 902  * @param[out] pkts
 903  *   Array to store received packets.
 904  * @param pkts_n
 905  *   Maximum number of packets in array.
 906  *
 907  * @return
 908  *   Number of packets successfully received (<= pkts_n).
 909  */
 910 uint16_t
 911 mlx4_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
 912 {
 913         struct rxq *rxq = dpdk_rxq;
 914         const uint32_t wr_cnt = (1 << rxq->elts_n) - 1;
 915         const uint16_t sges_n = rxq->sges_n;
 916         struct rte_mbuf *pkt = NULL;
 917         struct rte_mbuf *seg = NULL;
 918         unsigned int i = 0;
 919         uint32_t rq_ci = rxq->rq_ci << sges_n;
 920         int len = 0;
 921
 922         while (pkts_n) {
 923                 volatile struct mlx4_cqe *cqe;
 924                 uint32_t idx = rq_ci & wr_cnt;
 925                 struct rte_mbuf *rep = (*rxq->elts)[idx];
 926                 volatile struct mlx4_wqe_data_seg *scat = &(*rxq->wqes)[idx];
 927
 928                 /* Update the 'next' pointer of the previous segment. */
 929                 if (pkt)
 930                         seg->next = rep;
 931                 seg = rep;
 932                 rte_prefetch0(seg);
 933                 rte_prefetch0(scat);
 934                 rep = rte_mbuf_raw_alloc(rxq->mp);
 935                 if (unlikely(rep == NULL)) {
 936                         ++rxq->stats.rx_nombuf;
 937                         if (!pkt) {
 938                                 /*
 939                                  * No buffers before we even started,
 940                                  * bail out silently.
 941                                  */
 942                                 break;
 943                         }
 944                         while (pkt != seg) {
 945                                 assert(pkt != (*rxq->elts)[idx]);
 946                                 rep = pkt->next;
 947                                 pkt->next = NULL;
 948                                 pkt->nb_segs = 1;
 949                                 rte_mbuf_raw_free(pkt);
 950                                 pkt = rep;
 951                         }
 952                         break;
 953                 }
 954                 if (!pkt) {
 955                         /* Looking for the new packet. */
 956                         len = mlx4_cq_poll_one(rxq, &cqe);
 957                         if (!len) {
 958                                 rte_mbuf_raw_free(rep);
 959                                 break;
 960                         }
 961                         if (unlikely(len < 0)) {
 962                                 /* Rx error, packet is likely too large. */
 963                                 rte_mbuf_raw_free(rep);
 964                                 ++rxq->stats.idropped;
 965                                 goto skip;
 966                         }
 967                         pkt = seg;
 968                         /* Update packet information. */
 969                         pkt->packet_type =
 970                                 rxq_cq_to_pkt_type(cqe, rxq->l2tun_offload);
 971                         pkt->ol_flags = PKT_RX_RSS_HASH;
 972                         pkt->hash.rss = cqe->immed_rss_invalid;
 973                         pkt->pkt_len = len;
 974                         if (rxq->csum | rxq->csum_l2tun) {
 975                                 uint32_t flags =
 976                                         mlx4_cqe_flags(cqe,
 977                                                        rxq->csum,
 978                                                        rxq->csum_l2tun);
 979
 980                                 pkt->ol_flags =
 981                                         rxq_cq_to_ol_flags(flags,
 982                                                            rxq->csum,
 983                                                            rxq->csum_l2tun);
 984                         }
 985                 }
 986                 rep->nb_segs = 1;
 987                 rep->port = rxq->port_id;
 988                 rep->data_len = seg->data_len;
 989                 rep->data_off = seg->data_off;
 990                 (*rxq->elts)[idx] = rep;
 991                 /*
 992                  * Fill NIC descriptor with the new buffer. The lkey and size
 993                  * of the buffers are already known, only the buffer address
 994                  * changes.
 995                  */
 996                 scat->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
 997                 if (len > seg->data_len) {
 998                         len -= seg->data_len;
 999                         ++pkt->nb_segs;
1000                         ++rq_ci;
1001                         continue;
1002                 }
1003                 /* The last segment. */
1004                 seg->data_len = len;
1005                 /* Increment bytes counter. */
1006                 rxq->stats.ibytes += pkt->pkt_len;
1007                 /* Return packet. */
1008                 *(pkts++) = pkt;
1009                 pkt = NULL;
1010                 --pkts_n;
1011                 ++i;
1012 skip:
1013                 /* Align consumer index to the next stride. */
1014                 rq_ci >>= sges_n;
1015                 ++rq_ci;
1016                 rq_ci <<= sges_n;
1017         }
1018         if (unlikely(i == 0 && (rq_ci >> sges_n) == rxq->rq_ci))
1019                 return 0;
1020         /* Update the consumer index. */
1021         rxq->rq_ci = rq_ci >> sges_n;
1022         rte_wmb();
1023         *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1024         *rxq->mcq.set_ci_db =
1025                 rte_cpu_to_be_32(rxq->mcq.cons_index & MLX4_CQ_DB_CI_MASK);
1026         /* Increment packets counter. */
1027         rxq->stats.ipackets += i;
1028         return i;
1029 }
1030
1031 /**
1032  * Dummy DPDK callback for Tx.
1033  *
1034  * This function is used to temporarily replace the real callback during
1035  * unsafe control operations on the queue, or in case of error.
1036  *
1037  * @param dpdk_txq
1038  *   Generic pointer to Tx queue structure.
1039  * @param[in] pkts
1040  *   Packets to transmit.
1041  * @param pkts_n
1042  *   Number of packets in array.
1043  *
1044  * @return
1045  *   Number of packets successfully transmitted (<= pkts_n).
1046  */
1047 uint16_t
1048 mlx4_tx_burst_removed(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1049 {
1050         (void)dpdk_txq;
1051         (void)pkts;
1052         (void)pkts_n;
1053         return 0;
1054 }
1055
1056 /**
1057  * Dummy DPDK callback for Rx.
1058  *
1059  * This function is used to temporarily replace the real callback during
1060  * unsafe control operations on the queue, or in case of error.
1061  *
1062  * @param dpdk_rxq
1063  *   Generic pointer to Rx queue structure.
1064  * @param[out] pkts
1065  *   Array to store received packets.
1066  * @param pkts_n
1067  *   Maximum number of packets in array.
1068  *
1069  * @return
1070  *   Number of packets successfully received (<= pkts_n).
1071  */
1072 uint16_t
1073 mlx4_rx_burst_removed(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1074 {
1075         (void)dpdk_rxq;
1076         (void)pkts;
1077         (void)pkts_n;
1078         return 0;
1079 }