drivers/net/mlx4/mlx4_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright 2017 6WIND S.A.
   5  *   Copyright 2017 Mellanox
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of 6WIND S.A. nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 /**
  35  * @file
  36  * Data plane functions for mlx4 driver.
  37  */
  38
  39 #include <assert.h>
  40 #include <stdint.h>
  41 #include <string.h>
  42
  43 /* Verbs headers do not support -pedantic. */
  44 #ifdef PEDANTIC
  45 #pragma GCC diagnostic ignored "-Wpedantic"
  46 #endif
  47 #include <infiniband/verbs.h>
  48 #ifdef PEDANTIC
  49 #pragma GCC diagnostic error "-Wpedantic"
  50 #endif
  51
  52 #include <rte_branch_prediction.h>
  53 #include <rte_common.h>
  54 #include <rte_io.h>
  55 #include <rte_mbuf.h>
  56 #include <rte_mempool.h>
  57 #include <rte_prefetch.h>
  58
  59 #include "mlx4.h"
  60 #include "mlx4_prm.h"
  61 #include "mlx4_rxtx.h"
  62 #include "mlx4_utils.h"
  63
  64 #define WQE_ONE_DATA_SEG_SIZE \
  65         (sizeof(struct mlx4_wqe_ctrl_seg) + sizeof(struct mlx4_wqe_data_seg))
  66
  67 /**
  68  * Pointer-value pair structure used in tx_post_send for saving the first
  69  * DWORD (32 byte) of a TXBB.
  70  */
  71 struct pv {
  72         volatile struct mlx4_wqe_data_seg *dseg;
  73         uint32_t val;
  74 };
  75
  76 /** A table to translate Rx completion flags to packet type. */
  77 uint32_t mlx4_ptype_table[0x100] __rte_cache_aligned = {
  78         /*
  79          * The index to the array should have:
  80          *  bit[7] - MLX4_CQE_L2_TUNNEL
  81          *  bit[6] - MLX4_CQE_L2_TUNNEL_IPV4
  82          *  bit[5] - MLX4_CQE_STATUS_UDP
  83          *  bit[4] - MLX4_CQE_STATUS_TCP
  84          *  bit[3] - MLX4_CQE_STATUS_IPV4OPT
  85          *  bit[2] - MLX4_CQE_STATUS_IPV6
  86          *  bit[1] - MLX4_CQE_STATUS_IPV4F
  87          *  bit[0] - MLX4_CQE_STATUS_IPV4
  88          * giving a total of up to 256 entries.
  89          */
  90         [0x00] = RTE_PTYPE_L2_ETHER,
  91         [0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
  92         [0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  93                      RTE_PTYPE_L4_FRAG,
  94         [0x03] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  95                      RTE_PTYPE_L4_FRAG,
  96         [0x04] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
  97         [0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT,
  98         [0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
  99                      RTE_PTYPE_L4_FRAG,
 100         [0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 101                      RTE_PTYPE_L4_TCP,
 102         [0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 103                      RTE_PTYPE_L4_TCP,
 104         [0x14] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 105                      RTE_PTYPE_L4_TCP,
 106         [0x18] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
 107                      RTE_PTYPE_L4_TCP,
 108         [0x19] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
 109                      RTE_PTYPE_L4_TCP,
 110         [0x1a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
 111                      RTE_PTYPE_L4_TCP,
 112         [0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 113                      RTE_PTYPE_L4_UDP,
 114         [0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 115                      RTE_PTYPE_L4_UDP,
 116         [0x24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 117                      RTE_PTYPE_L4_UDP,
 118         [0x28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
 119                      RTE_PTYPE_L4_UDP,
 120         [0x29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
 121                      RTE_PTYPE_L4_UDP,
 122         [0x2a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
 123                      RTE_PTYPE_L4_UDP,
 124         /* Tunneled - L3 IPV6 */
 125         [0x80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 126         [0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 127                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
 128         [0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 129                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 130                      RTE_PTYPE_INNER_L4_FRAG,
 131         [0x83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 132                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 133                      RTE_PTYPE_INNER_L4_FRAG,
 134         [0x84] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 135                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
 136         [0x88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 137                      RTE_PTYPE_INNER_L3_IPV4_EXT,
 138         [0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 139                      RTE_PTYPE_INNER_L3_IPV4_EXT,
 140         [0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 141                      RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_FRAG,
 142         /* Tunneled - L3 IPV6, TCP */
 143         [0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 144                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 145                      RTE_PTYPE_INNER_L4_TCP,
 146         [0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 147                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 148                      RTE_PTYPE_INNER_L4_FRAG |
 149                      RTE_PTYPE_INNER_L4_TCP,
 150         [0x93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 151                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 152                      RTE_PTYPE_INNER_L4_FRAG |
 153                      RTE_PTYPE_INNER_L4_TCP,
 154         [0x94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 155                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 156                      RTE_PTYPE_INNER_L4_TCP,
 157         [0x98] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 158                      RTE_PTYPE_INNER_L3_IPV4_EXT |
 159                      RTE_PTYPE_INNER_L4_TCP,
 160         [0x99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 161                      RTE_PTYPE_INNER_L3_IPV4_EXT |
 162                      RTE_PTYPE_INNER_L4_TCP,
 163         [0x9a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 164                      RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_FRAG |
 165                      RTE_PTYPE_INNER_L4_TCP,
 166         /* Tunneled - L3 IPV6, UDP */
 167         [0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 168                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 169                      RTE_PTYPE_INNER_L4_UDP,
 170         [0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 171                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 172                      RTE_PTYPE_INNER_L4_FRAG |
 173                      RTE_PTYPE_INNER_L4_UDP,
 174         [0xa3] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 175                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 176                      RTE_PTYPE_INNER_L4_FRAG |
 177                      RTE_PTYPE_INNER_L4_UDP,
 178         [0xa4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 179                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 180                      RTE_PTYPE_INNER_L4_UDP,
 181         [0xa8] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 182                      RTE_PTYPE_INNER_L3_IPV4_EXT |
 183                      RTE_PTYPE_INNER_L4_UDP,
 184         [0xa9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 185                      RTE_PTYPE_INNER_L3_IPV4_EXT |
 186                      RTE_PTYPE_INNER_L4_UDP,
 187         [0xaa] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 188                      RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_FRAG |
 189                      RTE_PTYPE_INNER_L4_UDP,
 190         /* Tunneled - L3 IPV4 */
 191         [0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 192         [0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 193                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
 194         [0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 195                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 196                      RTE_PTYPE_INNER_L4_FRAG,
 197         [0xc3] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 198                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 199                      RTE_PTYPE_INNER_L4_FRAG,
 200         [0xc4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 201                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
 202         [0xc8] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 203                      RTE_PTYPE_INNER_L3_IPV4_EXT,
 204         [0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 205                      RTE_PTYPE_INNER_L3_IPV4_EXT,
 206         [0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 207                      RTE_PTYPE_INNER_L3_IPV4_EXT |
 208                      RTE_PTYPE_INNER_L4_FRAG,
 209         /* Tunneled - L3 IPV4, TCP */
 210         [0xd0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 211                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 212                      RTE_PTYPE_INNER_L4_TCP,
 213         [0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 214                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 215                      RTE_PTYPE_INNER_L4_TCP,
 216         [0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 217                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 218                      RTE_PTYPE_INNER_L4_FRAG |
 219                      RTE_PTYPE_INNER_L4_TCP,
 220         [0xd3] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 221                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 222                      RTE_PTYPE_INNER_L4_FRAG |
 223                      RTE_PTYPE_INNER_L4_TCP,
 224         [0xd4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 225                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 226                      RTE_PTYPE_INNER_L4_TCP,
 227         [0xd8] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 228                      RTE_PTYPE_INNER_L3_IPV4_EXT |
 229                      RTE_PTYPE_INNER_L4_TCP,
 230         [0xd9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 231                      RTE_PTYPE_INNER_L3_IPV4_EXT |
 232                      RTE_PTYPE_INNER_L4_TCP,
 233         [0xda] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 234                      RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_FRAG |
 235                      RTE_PTYPE_INNER_L4_TCP,
 236         /* Tunneled - L3 IPV4, UDP */
 237         [0xe0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 238                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 239                      RTE_PTYPE_INNER_L4_UDP,
 240         [0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 241                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 242                      RTE_PTYPE_INNER_L4_UDP,
 243         [0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 244                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 245                      RTE_PTYPE_INNER_L4_FRAG |
 246                      RTE_PTYPE_INNER_L4_UDP,
 247         [0xe3] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 248                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 249                      RTE_PTYPE_INNER_L4_FRAG |
 250                      RTE_PTYPE_INNER_L4_UDP,
 251         [0xe4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 252                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 253                      RTE_PTYPE_INNER_L4_UDP,
 254         [0xe8] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 255                      RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_UDP,
 256         [0xe9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 257                      RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_UDP,
 258         [0xea] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 259                      RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_FRAG |
 260                      RTE_PTYPE_INNER_L4_UDP,
 261 };
 262
 263 /**
 264  * Stamp a WQE so it won't be reused by the HW.
 265  *
 266  * Routine is used when freeing WQE used by the chip or when failing
 267  * building an WQ entry has failed leaving partial information on the queue.
 268  *
 269  * @param sq
 270  *   Pointer to the SQ structure.
 271  * @param index
 272  *   Index of the freed WQE.
 273  * @param num_txbbs
 274  *   Number of blocks to stamp.
 275  *   If < 0 the routine will use the size written in the WQ entry.
 276  * @param owner
 277  *   The value of the WQE owner bit to use in the stamp.
 278  *
 279  * @return
 280  *   The number of Tx basic blocs (TXBB) the WQE contained.
 281  */
 282 static int
 283 mlx4_txq_stamp_freed_wqe(struct mlx4_sq *sq, uint16_t index, uint8_t owner)
 284 {
 285         uint32_t stamp = rte_cpu_to_be_32(MLX4_SQ_STAMP_VAL |
 286                                           (!!owner << MLX4_SQ_STAMP_SHIFT));
 287         volatile uint8_t *wqe = mlx4_get_send_wqe(sq,
 288                                                 (index & sq->txbb_cnt_mask));
 289         volatile uint32_t *ptr = (volatile uint32_t *)wqe;
 290         int i;
 291         int txbbs_size;
 292         int num_txbbs;
 293
 294         /* Extract the size from the control segment of the WQE. */
 295         num_txbbs = MLX4_SIZE_TO_TXBBS((((volatile struct mlx4_wqe_ctrl_seg *)
 296                                          wqe)->fence_size & 0x3f) << 4);
 297         txbbs_size = num_txbbs * MLX4_TXBB_SIZE;
 298         /* Optimize the common case when there is no wrap-around. */
 299         if (wqe + txbbs_size <= sq->eob) {
 300                 /* Stamp the freed descriptor. */
 301                 for (i = 0; i < txbbs_size; i += MLX4_SQ_STAMP_STRIDE) {
 302                         *ptr = stamp;
 303                         ptr += MLX4_SQ_STAMP_DWORDS;
 304                 }
 305         } else {
 306                 /* Stamp the freed descriptor. */
 307                 for (i = 0; i < txbbs_size; i += MLX4_SQ_STAMP_STRIDE) {
 308                         *ptr = stamp;
 309                         ptr += MLX4_SQ_STAMP_DWORDS;
 310                         if ((volatile uint8_t *)ptr >= sq->eob) {
 311                                 ptr = (volatile uint32_t *)sq->buf;
 312                                 stamp ^= RTE_BE32(0x80000000);
 313                         }
 314                 }
 315         }
 316         return num_txbbs;
 317 }
 318
 319 /**
 320  * Manage Tx completions.
 321  *
 322  * When sending a burst, mlx4_tx_burst() posts several WRs.
 323  * To improve performance, a completion event is only required once every
 324  * MLX4_PMD_TX_PER_COMP_REQ sends. Doing so discards completion information
 325  * for other WRs, but this information would not be used anyway.
 326  *
 327  * @param txq
 328  *   Pointer to Tx queue structure.
 329  *
 330  * @return
 331  *   0 on success, -1 on failure.
 332  */
 333 static int
 334 mlx4_txq_complete(struct txq *txq, const unsigned int elts_n,
 335                                   struct mlx4_sq *sq)
 336 {
 337         unsigned int elts_comp = txq->elts_comp;
 338         unsigned int elts_tail = txq->elts_tail;
 339         unsigned int sq_tail = sq->tail;
 340         struct mlx4_cq *cq = &txq->mcq;
 341         volatile struct mlx4_cqe *cqe;
 342         uint32_t cons_index = cq->cons_index;
 343         uint16_t new_index;
 344         uint16_t nr_txbbs = 0;
 345         int pkts = 0;
 346
 347         /*
 348          * Traverse over all CQ entries reported and handle each WQ entry
 349          * reported by them.
 350          */
 351         do {
 352                 cqe = (volatile struct mlx4_cqe *)mlx4_get_cqe(cq, cons_index);
 353                 if (unlikely(!!(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
 354                     !!(cons_index & cq->cqe_cnt)))
 355                         break;
 356                 /*
 357                  * Make sure we read the CQE after we read the ownership bit.
 358                  */
 359                 rte_io_rmb();
 360 #ifndef NDEBUG
 361                 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
 362                              MLX4_CQE_OPCODE_ERROR)) {
 363                         volatile struct mlx4_err_cqe *cqe_err =
 364                                 (volatile struct mlx4_err_cqe *)cqe;
 365                         ERROR("%p CQE error - vendor syndrome: 0x%x"
 366                               " syndrome: 0x%x\n",
 367                               (void *)txq, cqe_err->vendor_err,
 368                               cqe_err->syndrome);
 369                 }
 370 #endif /* NDEBUG */
 371                 /* Get WQE index reported in the CQE. */
 372                 new_index =
 373                         rte_be_to_cpu_16(cqe->wqe_index) & sq->txbb_cnt_mask;
 374                 do {
 375                         /* Free next descriptor. */
 376                         sq_tail += nr_txbbs;
 377                         nr_txbbs =
 378                                 mlx4_txq_stamp_freed_wqe(sq,
 379                                      sq_tail & sq->txbb_cnt_mask,
 380                                      !!(sq_tail & sq->txbb_cnt));
 381                         pkts++;
 382                 } while ((sq_tail & sq->txbb_cnt_mask) != new_index);
 383                 cons_index++;
 384         } while (1);
 385         if (unlikely(pkts == 0))
 386                 return 0;
 387         /* Update CQ. */
 388         cq->cons_index = cons_index;
 389         *cq->set_ci_db = rte_cpu_to_be_32(cq->cons_index & MLX4_CQ_DB_CI_MASK);
 390         sq->tail = sq_tail + nr_txbbs;
 391         /* Update the list of packets posted for transmission. */
 392         elts_comp -= pkts;
 393         assert(elts_comp <= txq->elts_comp);
 394         /*
 395          * Assume completion status is successful as nothing can be done about
 396          * it anyway.
 397          */
 398         elts_tail += pkts;
 399         if (elts_tail >= elts_n)
 400                 elts_tail -= elts_n;
 401         txq->elts_tail = elts_tail;
 402         txq->elts_comp = elts_comp;
 403         return 0;
 404 }
 405
 406 /**
 407  * Get memory pool (MP) from mbuf. If mbuf is indirect, the pool from which
 408  * the cloned mbuf is allocated is returned instead.
 409  *
 410  * @param buf
 411  *   Pointer to mbuf.
 412  *
 413  * @return
 414  *   Memory pool where data is located for given mbuf.
 415  */
 416 static struct rte_mempool *
 417 mlx4_txq_mb2mp(struct rte_mbuf *buf)
 418 {
 419         if (unlikely(RTE_MBUF_INDIRECT(buf)))
 420                 return rte_mbuf_from_indirect(buf)->pool;
 421         return buf->pool;
 422 }
 423
 424 /**
 425  * Write Tx data segment to the SQ.
 426  *
 427  * @param dseg
 428  *   Pointer to data segment in SQ.
 429  * @param lkey
 430  *   Memory region lkey.
 431  * @param addr
 432  *   Data address.
 433  * @param byte_count
 434  *   Big endian bytes count of the data to send.
 435  */
 436 static inline void
 437 mlx4_fill_tx_data_seg(volatile struct mlx4_wqe_data_seg *dseg,
 438                        uint32_t lkey, uintptr_t addr, rte_be32_t  byte_count)
 439 {
 440         dseg->addr = rte_cpu_to_be_64(addr);
 441         dseg->lkey = rte_cpu_to_be_32(lkey);
 442 #if RTE_CACHE_LINE_SIZE < 64
 443         /*
 444          * Need a barrier here before writing the byte_count
 445          * fields to make sure that all the data is visible
 446          * before the byte_count field is set.
 447          * Otherwise, if the segment begins a new cacheline,
 448          * the HCA prefetcher could grab the 64-byte chunk and
 449          * get a valid (!= 0xffffffff) byte count but stale
 450          * data, and end up sending the wrong data.
 451          */
 452         rte_io_wmb();
 453 #endif /* RTE_CACHE_LINE_SIZE */
 454         dseg->byte_count = byte_count;
 455 }
 456
 457 static int
 458 mlx4_tx_burst_segs(struct rte_mbuf *buf, struct txq *txq,
 459                    volatile struct mlx4_wqe_ctrl_seg **pctrl)
 460 {
 461         int wqe_real_size;
 462         int nr_txbbs;
 463         struct pv *pv = (struct pv *)txq->bounce_buf;
 464         struct mlx4_sq *sq = &txq->msq;
 465         uint32_t head_idx = sq->head & sq->txbb_cnt_mask;
 466         volatile struct mlx4_wqe_ctrl_seg *ctrl;
 467         volatile struct mlx4_wqe_data_seg *dseg;
 468         struct rte_mbuf *sbuf = buf;
 469         uint32_t lkey;
 470         int pv_counter = 0;
 471         int nb_segs = buf->nb_segs;
 472
 473         /* Calculate the needed work queue entry size for this packet. */
 474         wqe_real_size = sizeof(volatile struct mlx4_wqe_ctrl_seg) +
 475                 nb_segs * sizeof(volatile struct mlx4_wqe_data_seg);
 476         nr_txbbs = MLX4_SIZE_TO_TXBBS(wqe_real_size);
 477         /*
 478          * Check that there is room for this WQE in the send queue and that
 479          * the WQE size is legal.
 480          */
 481         if (((sq->head - sq->tail) + nr_txbbs +
 482                                 sq->headroom_txbbs) >= sq->txbb_cnt ||
 483                         nr_txbbs > MLX4_MAX_WQE_TXBBS) {
 484                 return -1;
 485         }
 486         /* Get the control and data entries of the WQE. */
 487         ctrl = (volatile struct mlx4_wqe_ctrl_seg *)
 488                         mlx4_get_send_wqe(sq, head_idx);
 489         dseg = (volatile struct mlx4_wqe_data_seg *)
 490                         ((uintptr_t)ctrl + sizeof(struct mlx4_wqe_ctrl_seg));
 491         *pctrl = ctrl;
 492         /*
 493          * Fill the data segments with buffer information.
 494          * First WQE TXBB head segment is always control segment,
 495          * so jump to tail TXBB data segments code for the first
 496          * WQE data segments filling.
 497          */
 498         goto txbb_tail_segs;
 499 txbb_head_seg:
 500         /* Memory region key (big endian) for this memory pool. */
 501         lkey = mlx4_txq_mp2mr(txq, mlx4_txq_mb2mp(sbuf));
 502         if (unlikely(lkey == (uint32_t)-1)) {
 503                 DEBUG("%p: unable to get MP <-> MR association",
 504                       (void *)txq);
 505                 return -1;
 506         }
 507         /* Handle WQE wraparound. */
 508         if (dseg >=
 509                 (volatile struct mlx4_wqe_data_seg *)sq->eob)
 510                 dseg = (volatile struct mlx4_wqe_data_seg *)
 511                         sq->buf;
 512         dseg->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(sbuf, uintptr_t));
 513         dseg->lkey = rte_cpu_to_be_32(lkey);
 514         /*
 515          * This data segment starts at the beginning of a new
 516          * TXBB, so we need to postpone its byte_count writing
 517          * for later.
 518          */
 519         pv[pv_counter].dseg = dseg;
 520         /*
 521          * Zero length segment is treated as inline segment
 522          * with zero data.
 523          */
 524         pv[pv_counter++].val = rte_cpu_to_be_32(sbuf->data_len ?
 525                                                 sbuf->data_len : 0x80000000);
 526         sbuf = sbuf->next;
 527         dseg++;
 528         nb_segs--;
 529 txbb_tail_segs:
 530         /* Jump to default if there are more than two segments remaining. */
 531         switch (nb_segs) {
 532         default:
 533                 lkey = mlx4_txq_mp2mr(txq, mlx4_txq_mb2mp(sbuf));
 534                 if (unlikely(lkey == (uint32_t)-1)) {
 535                         DEBUG("%p: unable to get MP <-> MR association",
 536                               (void *)txq);
 537                         return -1;
 538                 }
 539                 mlx4_fill_tx_data_seg(dseg, lkey,
 540                                       rte_pktmbuf_mtod(sbuf, uintptr_t),
 541                                       rte_cpu_to_be_32(sbuf->data_len ?
 542                                                        sbuf->data_len :
 543                                                        0x80000000));
 544                 sbuf = sbuf->next;
 545                 dseg++;
 546                 nb_segs--;
 547                 /* fallthrough */
 548         case 2:
 549                 lkey = mlx4_txq_mp2mr(txq, mlx4_txq_mb2mp(sbuf));
 550                 if (unlikely(lkey == (uint32_t)-1)) {
 551                         DEBUG("%p: unable to get MP <-> MR association",
 552                               (void *)txq);
 553                         return -1;
 554                 }
 555                 mlx4_fill_tx_data_seg(dseg, lkey,
 556                                       rte_pktmbuf_mtod(sbuf, uintptr_t),
 557                                       rte_cpu_to_be_32(sbuf->data_len ?
 558                                                        sbuf->data_len :
 559                                                        0x80000000));
 560                 sbuf = sbuf->next;
 561                 dseg++;
 562                 nb_segs--;
 563                 /* fallthrough */
 564         case 1:
 565                 lkey = mlx4_txq_mp2mr(txq, mlx4_txq_mb2mp(sbuf));
 566                 if (unlikely(lkey == (uint32_t)-1)) {
 567                         DEBUG("%p: unable to get MP <-> MR association",
 568                               (void *)txq);
 569                         return -1;
 570                 }
 571                 mlx4_fill_tx_data_seg(dseg, lkey,
 572                                       rte_pktmbuf_mtod(sbuf, uintptr_t),
 573                                       rte_cpu_to_be_32(sbuf->data_len ?
 574                                                        sbuf->data_len :
 575                                                        0x80000000));
 576                 nb_segs--;
 577                 if (nb_segs) {
 578                         sbuf = sbuf->next;
 579                         dseg++;
 580                         goto txbb_head_seg;
 581                 }
 582                 /* fallthrough */
 583         case 0:
 584                 break;
 585         }
 586         /* Write the first DWORD of each TXBB save earlier. */
 587         if (pv_counter) {
 588                 /* Need a barrier here before writing the byte_count. */
 589                 rte_io_wmb();
 590                 for (--pv_counter; pv_counter  >= 0; pv_counter--)
 591                         pv[pv_counter].dseg->byte_count = pv[pv_counter].val;
 592         }
 593         /* Fill the control parameters for this packet. */
 594         ctrl->fence_size = (wqe_real_size >> 4) & 0x3f;
 595         return nr_txbbs;
 596 }
 597
 598 /**
 599  * DPDK callback for Tx.
 600  *
 601  * @param dpdk_txq
 602  *   Generic pointer to Tx queue structure.
 603  * @param[in] pkts
 604  *   Packets to transmit.
 605  * @param pkts_n
 606  *   Number of packets in array.
 607  *
 608  * @return
 609  *   Number of packets successfully transmitted (<= pkts_n).
 610  */
 611 uint16_t
 612 mlx4_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 613 {
 614         struct txq *txq = (struct txq *)dpdk_txq;
 615         unsigned int elts_head = txq->elts_head;
 616         const unsigned int elts_n = txq->elts_n;
 617         unsigned int bytes_sent = 0;
 618         unsigned int i;
 619         unsigned int max;
 620         struct mlx4_sq *sq = &txq->msq;
 621         int nr_txbbs;
 622
 623         assert(txq->elts_comp_cd != 0);
 624         if (likely(txq->elts_comp != 0))
 625                 mlx4_txq_complete(txq, elts_n, sq);
 626         max = (elts_n - (elts_head - txq->elts_tail));
 627         if (max > elts_n)
 628                 max -= elts_n;
 629         assert(max >= 1);
 630         assert(max <= elts_n);
 631         /* Always leave one free entry in the ring. */
 632         --max;
 633         if (max > pkts_n)
 634                 max = pkts_n;
 635         for (i = 0; (i != max); ++i) {
 636                 struct rte_mbuf *buf = pkts[i];
 637                 unsigned int elts_head_next =
 638                         (((elts_head + 1) == elts_n) ? 0 : elts_head + 1);
 639                 struct txq_elt *elt_next = &(*txq->elts)[elts_head_next];
 640                 struct txq_elt *elt = &(*txq->elts)[elts_head];
 641                 uint32_t owner_opcode = MLX4_OPCODE_SEND;
 642                 volatile struct mlx4_wqe_ctrl_seg *ctrl;
 643                 volatile struct mlx4_wqe_data_seg *dseg;
 644                 union {
 645                         uint32_t flags;
 646                         uint16_t flags16[2];
 647                 } srcrb;
 648                 uint32_t head_idx = sq->head & sq->txbb_cnt_mask;
 649                 uint32_t lkey;
 650
 651                 /* Clean up old buffer. */
 652                 if (likely(elt->buf != NULL)) {
 653                         struct rte_mbuf *tmp = elt->buf;
 654
 655 #ifndef NDEBUG
 656                         /* Poisoning. */
 657                         memset(elt, 0x66, sizeof(*elt));
 658 #endif
 659                         /* Faster than rte_pktmbuf_free(). */
 660                         do {
 661                                 struct rte_mbuf *next = tmp->next;
 662
 663                                 rte_pktmbuf_free_seg(tmp);
 664                                 tmp = next;
 665                         } while (tmp != NULL);
 666                 }
 667                 RTE_MBUF_PREFETCH_TO_FREE(elt_next->buf);
 668                 if (buf->nb_segs == 1) {
 669                         /*
 670                          * Check that there is room for this WQE in the send
 671                          * queue and that the WQE size is legal
 672                          */
 673                         if (((sq->head - sq->tail) + 1 + sq->headroom_txbbs) >=
 674                              sq->txbb_cnt || 1 > MLX4_MAX_WQE_TXBBS) {
 675                                 elt->buf = NULL;
 676                                 break;
 677                         }
 678                         /* Get the control and data entries of the WQE. */
 679                         ctrl = (volatile struct mlx4_wqe_ctrl_seg *)
 680                                         mlx4_get_send_wqe(sq, head_idx);
 681                         dseg = (volatile struct mlx4_wqe_data_seg *)
 682                                         ((uintptr_t)ctrl +
 683                                         sizeof(struct mlx4_wqe_ctrl_seg));
 684
 685                         ctrl->fence_size = (WQE_ONE_DATA_SEG_SIZE >> 4) & 0x3f;
 686                         lkey = mlx4_txq_mp2mr(txq, mlx4_txq_mb2mp(buf));
 687                         if (unlikely(lkey == (uint32_t)-1)) {
 688                                 /* MR does not exist. */
 689                                 DEBUG("%p: unable to get MP <-> MR association",
 690                                       (void *)txq);
 691                                 elt->buf = NULL;
 692                                 break;
 693                         }
 694                         mlx4_fill_tx_data_seg(dseg, lkey,
 695                                               rte_pktmbuf_mtod(buf, uintptr_t),
 696                                               rte_cpu_to_be_32(buf->data_len));
 697                         nr_txbbs = 1;
 698                 } else {
 699                         nr_txbbs = mlx4_tx_burst_segs(buf, txq, &ctrl);
 700                         if (nr_txbbs < 0) {
 701                                 elt->buf = NULL;
 702                                 break;
 703                         }
 704                 }
 705                 /*
 706                  * For raw Ethernet, the SOLICIT flag is used to indicate
 707                  * that no ICRC should be calculated.
 708                  */
 709                 txq->elts_comp_cd -= nr_txbbs;
 710                 if (unlikely(txq->elts_comp_cd <= 0)) {
 711                         txq->elts_comp_cd = txq->elts_comp_cd_init;
 712                         srcrb.flags = RTE_BE32(MLX4_WQE_CTRL_SOLICIT |
 713                                                MLX4_WQE_CTRL_CQ_UPDATE);
 714                 } else {
 715                         srcrb.flags = RTE_BE32(MLX4_WQE_CTRL_SOLICIT);
 716                 }
 717                 /* Enable HW checksum offload if requested */
 718                 if (txq->csum &&
 719                     (buf->ol_flags &
 720                      (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))) {
 721                         const uint64_t is_tunneled = (buf->ol_flags &
 722                                                       (PKT_TX_TUNNEL_GRE |
 723                                                        PKT_TX_TUNNEL_VXLAN));
 724
 725                         if (is_tunneled && txq->csum_l2tun) {
 726                                 owner_opcode |= MLX4_WQE_CTRL_IIP_HDR_CSUM |
 727                                                 MLX4_WQE_CTRL_IL4_HDR_CSUM;
 728                                 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
 729                                         srcrb.flags |=
 730                                             RTE_BE32(MLX4_WQE_CTRL_IP_HDR_CSUM);
 731                         } else {
 732                                 srcrb.flags |=
 733                                         RTE_BE32(MLX4_WQE_CTRL_IP_HDR_CSUM |
 734                                                 MLX4_WQE_CTRL_TCP_UDP_CSUM);
 735                         }
 736                 }
 737                 if (txq->lb) {
 738                         /*
 739                          * Copy destination MAC address to the WQE, this allows
 740                          * loopback in eSwitch, so that VFs and PF can
 741                          * communicate with each other.
 742                          */
 743                         srcrb.flags16[0] = *(rte_pktmbuf_mtod(buf, uint16_t *));
 744                         ctrl->imm = *(rte_pktmbuf_mtod_offset(buf, uint32_t *,
 745                                               sizeof(uint16_t)));
 746                 } else {
 747                         ctrl->imm = 0;
 748                 }
 749                 ctrl->srcrb_flags = srcrb.flags;
 750                 /*
 751                  * Make sure descriptor is fully written before
 752                  * setting ownership bit (because HW can start
 753                  * executing as soon as we do).
 754                  */
 755                 rte_io_wmb();
 756                 ctrl->owner_opcode = rte_cpu_to_be_32(owner_opcode |
 757                                               ((sq->head & sq->txbb_cnt) ?
 758                                                        MLX4_BIT_WQE_OWN : 0));
 759                 sq->head += nr_txbbs;
 760                 elt->buf = buf;
 761                 bytes_sent += buf->pkt_len;
 762                 elts_head = elts_head_next;
 763         }
 764         /* Take a shortcut if nothing must be sent. */
 765         if (unlikely(i == 0))
 766                 return 0;
 767         /* Increment send statistics counters. */
 768         txq->stats.opackets += i;
 769         txq->stats.obytes += bytes_sent;
 770         /* Make sure that descriptors are written before doorbell record. */
 771         rte_wmb();
 772         /* Ring QP doorbell. */
 773         rte_write32(txq->msq.doorbell_qpn, txq->msq.db);
 774         txq->elts_head = elts_head;
 775         txq->elts_comp += i;
 776         return i;
 777 }
 778
 779 /**
 780  * Translate Rx completion flags to packet type.
 781  *
 782  * @param[in] cqe
 783  *   Pointer to CQE.
 784  *
 785  * @return
 786  *   Packet type for struct rte_mbuf.
 787  */
 788 static inline uint32_t
 789 rxq_cq_to_pkt_type(volatile struct mlx4_cqe *cqe,
 790                    uint32_t l2tun_offload)
 791 {
 792         uint8_t idx = 0;
 793         uint32_t pinfo = rte_be_to_cpu_32(cqe->vlan_my_qpn);
 794         uint32_t status = rte_be_to_cpu_32(cqe->status);
 795
 796         /*
 797          * The index to the array should have:
 798          *  bit[7] - MLX4_CQE_L2_TUNNEL
 799          *  bit[6] - MLX4_CQE_L2_TUNNEL_IPV4
 800          */
 801         if (l2tun_offload && (pinfo & MLX4_CQE_L2_TUNNEL))
 802                 idx |= ((pinfo & MLX4_CQE_L2_TUNNEL) >> 20) |
 803                        ((pinfo & MLX4_CQE_L2_TUNNEL_IPV4) >> 19);
 804         /*
 805          * The index to the array should have:
 806          *  bit[5] - MLX4_CQE_STATUS_UDP
 807          *  bit[4] - MLX4_CQE_STATUS_TCP
 808          *  bit[3] - MLX4_CQE_STATUS_IPV4OPT
 809          *  bit[2] - MLX4_CQE_STATUS_IPV6
 810          *  bit[1] - MLX4_CQE_STATUS_IPV4F
 811          *  bit[0] - MLX4_CQE_STATUS_IPV4
 812          * giving a total of up to 256 entries.
 813          */
 814         idx |= ((status & MLX4_CQE_STATUS_PTYPE_MASK) >> 22);
 815         return mlx4_ptype_table[idx];
 816 }
 817
 818 /**
 819  * Translate Rx completion flags to offload flags.
 820  *
 821  * @param flags
 822  *   Rx completion flags returned by mlx4_cqe_flags().
 823  * @param csum
 824  *   Whether Rx checksums are enabled.
 825  * @param csum_l2tun
 826  *   Whether Rx L2 tunnel checksums are enabled.
 827  *
 828  * @return
 829  *   Offload flags (ol_flags) in mbuf format.
 830  */
 831 static inline uint32_t
 832 rxq_cq_to_ol_flags(uint32_t flags, int csum, int csum_l2tun)
 833 {
 834         uint32_t ol_flags = 0;
 835
 836         if (csum)
 837                 ol_flags |=
 838                         mlx4_transpose(flags,
 839                                        MLX4_CQE_STATUS_IP_HDR_CSUM_OK,
 840                                        PKT_RX_IP_CKSUM_GOOD) |
 841                         mlx4_transpose(flags,
 842                                        MLX4_CQE_STATUS_TCP_UDP_CSUM_OK,
 843                                        PKT_RX_L4_CKSUM_GOOD);
 844         if ((flags & MLX4_CQE_L2_TUNNEL) && csum_l2tun)
 845                 ol_flags |=
 846                         mlx4_transpose(flags,
 847                                        MLX4_CQE_L2_TUNNEL_IPOK,
 848                                        PKT_RX_IP_CKSUM_GOOD) |
 849                         mlx4_transpose(flags,
 850                                        MLX4_CQE_L2_TUNNEL_L4_CSUM,
 851                                        PKT_RX_L4_CKSUM_GOOD);
 852         return ol_flags;
 853 }
 854
 855 /**
 856  * Extract checksum information from CQE flags.
 857  *
 858  * @param cqe
 859  *   Pointer to CQE structure.
 860  * @param csum
 861  *   Whether Rx checksums are enabled.
 862  * @param csum_l2tun
 863  *   Whether Rx L2 tunnel checksums are enabled.
 864  *
 865  * @return
 866  *   CQE checksum information.
 867  */
 868 static inline uint32_t
 869 mlx4_cqe_flags(volatile struct mlx4_cqe *cqe, int csum, int csum_l2tun)
 870 {
 871         uint32_t flags = 0;
 872
 873         /*
 874          * The relevant bits are in different locations on their
 875          * CQE fields therefore we can join them in one 32bit
 876          * variable.
 877          */
 878         if (csum)
 879                 flags = (rte_be_to_cpu_32(cqe->status) &
 880                          MLX4_CQE_STATUS_IPV4_CSUM_OK);
 881         if (csum_l2tun)
 882                 flags |= (rte_be_to_cpu_32(cqe->vlan_my_qpn) &
 883                           (MLX4_CQE_L2_TUNNEL |
 884                            MLX4_CQE_L2_TUNNEL_IPOK |
 885                            MLX4_CQE_L2_TUNNEL_L4_CSUM |
 886                            MLX4_CQE_L2_TUNNEL_IPV4));
 887         return flags;
 888 }
 889
 890 /**
 891  * Poll one CQE from CQ.
 892  *
 893  * @param rxq
 894  *   Pointer to the receive queue structure.
 895  * @param[out] out
 896  *   Just polled CQE.
 897  *
 898  * @return
 899  *   Number of bytes of the CQE, 0 in case there is no completion.
 900  */
 901 static unsigned int
 902 mlx4_cq_poll_one(struct rxq *rxq, volatile struct mlx4_cqe **out)
 903 {
 904         int ret = 0;
 905         volatile struct mlx4_cqe *cqe = NULL;
 906         struct mlx4_cq *cq = &rxq->mcq;
 907
 908         cqe = (volatile struct mlx4_cqe *)mlx4_get_cqe(cq, cq->cons_index);
 909         if (!!(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
 910             !!(cq->cons_index & cq->cqe_cnt))
 911                 goto out;
 912         /*
 913          * Make sure we read CQ entry contents after we've checked the
 914          * ownership bit.
 915          */
 916         rte_rmb();
 917         assert(!(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK));
 918         assert((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) !=
 919                MLX4_CQE_OPCODE_ERROR);
 920         ret = rte_be_to_cpu_32(cqe->byte_cnt);
 921         ++cq->cons_index;
 922 out:
 923         *out = cqe;
 924         return ret;
 925 }
 926
 927 /**
 928  * DPDK callback for Rx with scattered packets support.
 929  *
 930  * @param dpdk_rxq
 931  *   Generic pointer to Rx queue structure.
 932  * @param[out] pkts
 933  *   Array to store received packets.
 934  * @param pkts_n
 935  *   Maximum number of packets in array.
 936  *
 937  * @return
 938  *   Number of packets successfully received (<= pkts_n).
 939  */
 940 uint16_t
 941 mlx4_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
 942 {
 943         struct rxq *rxq = dpdk_rxq;
 944         const uint32_t wr_cnt = (1 << rxq->elts_n) - 1;
 945         const uint16_t sges_n = rxq->sges_n;
 946         struct rte_mbuf *pkt = NULL;
 947         struct rte_mbuf *seg = NULL;
 948         unsigned int i = 0;
 949         uint32_t rq_ci = rxq->rq_ci << sges_n;
 950         int len = 0;
 951
 952         while (pkts_n) {
 953                 volatile struct mlx4_cqe *cqe;
 954                 uint32_t idx = rq_ci & wr_cnt;
 955                 struct rte_mbuf *rep = (*rxq->elts)[idx];
 956                 volatile struct mlx4_wqe_data_seg *scat = &(*rxq->wqes)[idx];
 957
 958                 /* Update the 'next' pointer of the previous segment. */
 959                 if (pkt)
 960                         seg->next = rep;
 961                 seg = rep;
 962                 rte_prefetch0(seg);
 963                 rte_prefetch0(scat);
 964                 rep = rte_mbuf_raw_alloc(rxq->mp);
 965                 if (unlikely(rep == NULL)) {
 966                         ++rxq->stats.rx_nombuf;
 967                         if (!pkt) {
 968                                 /*
 969                                  * No buffers before we even started,
 970                                  * bail out silently.
 971                                  */
 972                                 break;
 973                         }
 974                         while (pkt != seg) {
 975                                 assert(pkt != (*rxq->elts)[idx]);
 976                                 rep = pkt->next;
 977                                 pkt->next = NULL;
 978                                 pkt->nb_segs = 1;
 979                                 rte_mbuf_raw_free(pkt);
 980                                 pkt = rep;
 981                         }
 982                         break;
 983                 }
 984                 if (!pkt) {
 985                         /* Looking for the new packet. */
 986                         len = mlx4_cq_poll_one(rxq, &cqe);
 987                         if (!len) {
 988                                 rte_mbuf_raw_free(rep);
 989                                 break;
 990                         }
 991                         if (unlikely(len < 0)) {
 992                                 /* Rx error, packet is likely too large. */
 993                                 rte_mbuf_raw_free(rep);
 994                                 ++rxq->stats.idropped;
 995                                 goto skip;
 996                         }
 997                         pkt = seg;
 998                         /* Update packet information. */
 999                         pkt->packet_type =
1000                                 rxq_cq_to_pkt_type(cqe, rxq->l2tun_offload);
1001                         pkt->ol_flags = PKT_RX_RSS_HASH;
1002                         pkt->hash.rss = cqe->immed_rss_invalid;
1003                         pkt->pkt_len = len;
1004                         if (rxq->csum | rxq->csum_l2tun) {
1005                                 uint32_t flags =
1006                                         mlx4_cqe_flags(cqe,
1007                                                        rxq->csum,
1008                                                        rxq->csum_l2tun);
1009
1010                                 pkt->ol_flags =
1011                                         rxq_cq_to_ol_flags(flags,
1012                                                            rxq->csum,
1013                                                            rxq->csum_l2tun);
1014                         }
1015                 }
1016                 rep->nb_segs = 1;
1017                 rep->port = rxq->port_id;
1018                 rep->data_len = seg->data_len;
1019                 rep->data_off = seg->data_off;
1020                 (*rxq->elts)[idx] = rep;
1021                 /*
1022                  * Fill NIC descriptor with the new buffer. The lkey and size
1023                  * of the buffers are already known, only the buffer address
1024                  * changes.
1025                  */
1026                 scat->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1027                 if (len > seg->data_len) {
1028                         len -= seg->data_len;
1029                         ++pkt->nb_segs;
1030                         ++rq_ci;
1031                         continue;
1032                 }
1033                 /* The last segment. */
1034                 seg->data_len = len;
1035                 /* Increment bytes counter. */
1036                 rxq->stats.ibytes += pkt->pkt_len;
1037                 /* Return packet. */
1038                 *(pkts++) = pkt;
1039                 pkt = NULL;
1040                 --pkts_n;
1041                 ++i;
1042 skip:
1043                 /* Align consumer index to the next stride. */
1044                 rq_ci >>= sges_n;
1045                 ++rq_ci;
1046                 rq_ci <<= sges_n;
1047         }
1048         if (unlikely(i == 0 && (rq_ci >> sges_n) == rxq->rq_ci))
1049                 return 0;
1050         /* Update the consumer index. */
1051         rxq->rq_ci = rq_ci >> sges_n;
1052         rte_wmb();
1053         *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1054         *rxq->mcq.set_ci_db =
1055                 rte_cpu_to_be_32(rxq->mcq.cons_index & MLX4_CQ_DB_CI_MASK);
1056         /* Increment packets counter. */
1057         rxq->stats.ipackets += i;
1058         return i;
1059 }
1060
1061 /**
1062  * Dummy DPDK callback for Tx.
1063  *
1064  * This function is used to temporarily replace the real callback during
1065  * unsafe control operations on the queue, or in case of error.
1066  *
1067  * @param dpdk_txq
1068  *   Generic pointer to Tx queue structure.
1069  * @param[in] pkts
1070  *   Packets to transmit.
1071  * @param pkts_n
1072  *   Number of packets in array.
1073  *
1074  * @return
1075  *   Number of packets successfully transmitted (<= pkts_n).
1076  */
1077 uint16_t
1078 mlx4_tx_burst_removed(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1079 {
1080         (void)dpdk_txq;
1081         (void)pkts;
1082         (void)pkts_n;
1083         return 0;
1084 }
1085
1086 /**
1087  * Dummy DPDK callback for Rx.
1088  *
1089  * This function is used to temporarily replace the real callback during
1090  * unsafe control operations on the queue, or in case of error.
1091  *
1092  * @param dpdk_rxq
1093  *   Generic pointer to Rx queue structure.
1094  * @param[out] pkts
1095  *   Array to store received packets.
1096  * @param pkts_n
1097  *   Maximum number of packets in array.
1098  *
1099  * @return
1100  *   Number of packets successfully received (<= pkts_n).
1101  */
1102 uint16_t
1103 mlx4_rx_burst_removed(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1104 {
1105         (void)dpdk_rxq;
1106         (void)pkts;
1107         (void)pkts_n;
1108         return 0;
1109 }