drivers/net/mlx4/mlx4_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright 2017 6WIND S.A.
   5  *   Copyright 2017 Mellanox
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of 6WIND S.A. nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 /**
  35  * @file
  36  * Data plane functions for mlx4 driver.
  37  */
  38
  39 #include <assert.h>
  40 #include <stdint.h>
  41 #include <string.h>
  42
  43 /* Verbs headers do not support -pedantic. */
  44 #ifdef PEDANTIC
  45 #pragma GCC diagnostic ignored "-Wpedantic"
  46 #endif
  47 #include <infiniband/verbs.h>
  48 #ifdef PEDANTIC
  49 #pragma GCC diagnostic error "-Wpedantic"
  50 #endif
  51
  52 #include <rte_branch_prediction.h>
  53 #include <rte_common.h>
  54 #include <rte_io.h>
  55 #include <rte_mbuf.h>
  56 #include <rte_mempool.h>
  57 #include <rte_prefetch.h>
  58
  59 #include "mlx4.h"
  60 #include "mlx4_prm.h"
  61 #include "mlx4_rxtx.h"
  62 #include "mlx4_utils.h"
  63
  64 /**
  65  * Pointer-value pair structure used in tx_post_send for saving the first
  66  * DWORD (32 byte) of a TXBB.
  67  */
  68 struct pv {
  69         volatile struct mlx4_wqe_data_seg *dseg;
  70         uint32_t val;
  71 };
  72
  73 /** A table to translate Rx completion flags to packet type. */
  74 uint32_t mlx4_ptype_table[0x100] __rte_cache_aligned = {
  75         /*
  76          * The index to the array should have:
  77          *  bit[7] - MLX4_CQE_L2_TUNNEL
  78          *  bit[6] - MLX4_CQE_L2_TUNNEL_IPV4
  79          *  bit[5] - MLX4_CQE_STATUS_UDP
  80          *  bit[4] - MLX4_CQE_STATUS_TCP
  81          *  bit[3] - MLX4_CQE_STATUS_IPV4OPT
  82          *  bit[2] - MLX4_CQE_STATUS_IPV6
  83          *  bit[1] - MLX4_CQE_STATUS_IPV4F
  84          *  bit[0] - MLX4_CQE_STATUS_IPV4
  85          * giving a total of up to 256 entries.
  86          */
  87         [0x00] = RTE_PTYPE_L2_ETHER,
  88         [0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
  89         [0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  90                      RTE_PTYPE_L4_FRAG,
  91         [0x03] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  92                      RTE_PTYPE_L4_FRAG,
  93         [0x04] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
  94         [0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT,
  95         [0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
  96                      RTE_PTYPE_L4_FRAG,
  97         [0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  98                      RTE_PTYPE_L4_TCP,
  99         [0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 100                      RTE_PTYPE_L4_TCP,
 101         [0x14] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 102                      RTE_PTYPE_L4_TCP,
 103         [0x18] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
 104                      RTE_PTYPE_L4_TCP,
 105         [0x19] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
 106                      RTE_PTYPE_L4_TCP,
 107         [0x1a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
 108                      RTE_PTYPE_L4_TCP,
 109         [0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 110                      RTE_PTYPE_L4_UDP,
 111         [0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 112                      RTE_PTYPE_L4_UDP,
 113         [0x24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 114                      RTE_PTYPE_L4_UDP,
 115         [0x28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
 116                      RTE_PTYPE_L4_UDP,
 117         [0x29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
 118                      RTE_PTYPE_L4_UDP,
 119         [0x2a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
 120                      RTE_PTYPE_L4_UDP,
 121         /* Tunneled - L3 IPV6 */
 122         [0x80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 123         [0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 124                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
 125         [0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 126                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 127                      RTE_PTYPE_INNER_L4_FRAG,
 128         [0x83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 129                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 130                      RTE_PTYPE_INNER_L4_FRAG,
 131         [0x84] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 132                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
 133         [0x88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 134                      RTE_PTYPE_INNER_L3_IPV4_EXT,
 135         [0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 136                      RTE_PTYPE_INNER_L3_IPV4_EXT,
 137         [0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 138                      RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_FRAG,
 139         /* Tunneled - L3 IPV6, TCP */
 140         [0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 141                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 142                      RTE_PTYPE_INNER_L4_TCP,
 143         [0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 144                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 145                      RTE_PTYPE_INNER_L4_FRAG |
 146                      RTE_PTYPE_INNER_L4_TCP,
 147         [0x93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 148                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 149                      RTE_PTYPE_INNER_L4_FRAG |
 150                      RTE_PTYPE_INNER_L4_TCP,
 151         [0x94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 152                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 153                      RTE_PTYPE_INNER_L4_TCP,
 154         [0x98] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 155                      RTE_PTYPE_INNER_L3_IPV4_EXT |
 156                      RTE_PTYPE_INNER_L4_TCP,
 157         [0x99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 158                      RTE_PTYPE_INNER_L3_IPV4_EXT |
 159                      RTE_PTYPE_INNER_L4_TCP,
 160         [0x9a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 161                      RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_FRAG |
 162                      RTE_PTYPE_INNER_L4_TCP,
 163         /* Tunneled - L3 IPV6, UDP */
 164         [0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 165                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 166                      RTE_PTYPE_INNER_L4_UDP,
 167         [0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 168                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 169                      RTE_PTYPE_INNER_L4_FRAG |
 170                      RTE_PTYPE_INNER_L4_UDP,
 171         [0xa3] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 172                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 173                      RTE_PTYPE_INNER_L4_FRAG |
 174                      RTE_PTYPE_INNER_L4_UDP,
 175         [0xa4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 176                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 177                      RTE_PTYPE_INNER_L4_UDP,
 178         [0xa8] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 179                      RTE_PTYPE_INNER_L3_IPV4_EXT |
 180                      RTE_PTYPE_INNER_L4_UDP,
 181         [0xa9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 182                      RTE_PTYPE_INNER_L3_IPV4_EXT |
 183                      RTE_PTYPE_INNER_L4_UDP,
 184         [0xaa] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 185                      RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_FRAG |
 186                      RTE_PTYPE_INNER_L4_UDP,
 187         /* Tunneled - L3 IPV4 */
 188         [0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 189         [0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 190                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
 191         [0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 192                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 193                      RTE_PTYPE_INNER_L4_FRAG,
 194         [0xc3] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 195                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 196                      RTE_PTYPE_INNER_L4_FRAG,
 197         [0xc4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 198                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
 199         [0xc8] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 200                      RTE_PTYPE_INNER_L3_IPV4_EXT,
 201         [0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 202                      RTE_PTYPE_INNER_L3_IPV4_EXT,
 203         [0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 204                      RTE_PTYPE_INNER_L3_IPV4_EXT |
 205                      RTE_PTYPE_INNER_L4_FRAG,
 206         /* Tunneled - L3 IPV4, TCP */
 207         [0xd0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 208                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 209                      RTE_PTYPE_INNER_L4_TCP,
 210         [0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 211                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 212                      RTE_PTYPE_INNER_L4_TCP,
 213         [0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 214                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 215                      RTE_PTYPE_INNER_L4_FRAG |
 216                      RTE_PTYPE_INNER_L4_TCP,
 217         [0xd3] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 218                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 219                      RTE_PTYPE_INNER_L4_FRAG |
 220                      RTE_PTYPE_INNER_L4_TCP,
 221         [0xd4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 222                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 223                      RTE_PTYPE_INNER_L4_TCP,
 224         [0xd8] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 225                      RTE_PTYPE_INNER_L3_IPV4_EXT |
 226                      RTE_PTYPE_INNER_L4_TCP,
 227         [0xd9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 228                      RTE_PTYPE_INNER_L3_IPV4_EXT |
 229                      RTE_PTYPE_INNER_L4_TCP,
 230         [0xda] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 231                      RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_FRAG |
 232                      RTE_PTYPE_INNER_L4_TCP,
 233         /* Tunneled - L3 IPV4, UDP */
 234         [0xe0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 235                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 236                      RTE_PTYPE_INNER_L4_UDP,
 237         [0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 238                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 239                      RTE_PTYPE_INNER_L4_UDP,
 240         [0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 241                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 242                      RTE_PTYPE_INNER_L4_FRAG |
 243                      RTE_PTYPE_INNER_L4_UDP,
 244         [0xe3] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 245                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 246                      RTE_PTYPE_INNER_L4_FRAG |
 247                      RTE_PTYPE_INNER_L4_UDP,
 248         [0xe4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 249                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 250                      RTE_PTYPE_INNER_L4_UDP,
 251         [0xe8] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 252                      RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_UDP,
 253         [0xe9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 254                      RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_UDP,
 255         [0xea] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 256                      RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_FRAG |
 257                      RTE_PTYPE_INNER_L4_UDP,
 258 };
 259
 260 /**
 261  * Stamp a WQE so it won't be reused by the HW.
 262  *
 263  * Routine is used when freeing WQE used by the chip or when failing
 264  * building an WQ entry has failed leaving partial information on the queue.
 265  *
 266  * @param sq
 267  *   Pointer to the SQ structure.
 268  * @param[in, out] wqe
 269  *   Pointer of WQE address to stamp. This value is modified on return to
 270  *   store the address of the next WQE.
 271  *
 272  * @return
 273  *   WQE size.
 274  */
 275 static uint32_t
 276 mlx4_txq_stamp_freed_wqe(struct mlx4_sq *sq, volatile uint32_t **wqe)
 277 {
 278         uint32_t stamp = sq->stamp;
 279         volatile uint32_t *next_txbb = *wqe;
 280         /* Extract the size from the control segment of the WQE. */
 281         uint32_t size = RTE_ALIGN((uint32_t)
 282                                   ((((volatile struct mlx4_wqe_ctrl_seg *)
 283                                      next_txbb)->fence_size & 0x3f) << 4),
 284                                   MLX4_TXBB_SIZE);
 285         uint32_t size_cd = size;
 286
 287         /* Optimize the common case when there is no wrap-around. */
 288         if ((uintptr_t)next_txbb + size < (uintptr_t)sq->eob) {
 289                 /* Stamp the freed descriptor. */
 290                 do {
 291                         *next_txbb = stamp;
 292                         next_txbb += MLX4_SQ_STAMP_DWORDS;
 293                         size_cd -= MLX4_TXBB_SIZE;
 294                 } while (size_cd);
 295         } else {
 296                 /* Stamp the freed descriptor. */
 297                 do {
 298                         *next_txbb = stamp;
 299                         next_txbb += MLX4_SQ_STAMP_DWORDS;
 300                         if ((volatile uint8_t *)next_txbb >= sq->eob) {
 301                                 next_txbb = (volatile uint32_t *)sq->buf;
 302                                 /* Flip invalid stamping ownership. */
 303                                 stamp ^= RTE_BE32(0x1 << MLX4_SQ_OWNER_BIT);
 304                                 sq->stamp = stamp;
 305                         }
 306                         size_cd -= MLX4_TXBB_SIZE;
 307                 } while (size_cd);
 308         }
 309         *wqe = next_txbb;
 310         return size;
 311 }
 312
 313 /**
 314  * Manage Tx completions.
 315  *
 316  * When sending a burst, mlx4_tx_burst() posts several WRs.
 317  * To improve performance, a completion event is only required once every
 318  * MLX4_PMD_TX_PER_COMP_REQ sends. Doing so discards completion information
 319  * for other WRs, but this information would not be used anyway.
 320  *
 321  * @param txq
 322  *   Pointer to Tx queue structure.
 323  */
 324 static void
 325 mlx4_txq_complete(struct txq *txq, const unsigned int elts_n,
 326                                   struct mlx4_sq *sq)
 327 {
 328         unsigned int elts_tail = txq->elts_tail;
 329         struct mlx4_cq *cq = &txq->mcq;
 330         volatile struct mlx4_cqe *cqe;
 331         uint32_t cons_index = cq->cons_index;
 332         volatile uint32_t *first_wqe;
 333         volatile uint32_t *next_wqe = (volatile uint32_t *)
 334                         ((&(*txq->elts)[elts_tail])->wqe);
 335         volatile uint32_t *last_wqe;
 336         uint16_t mask = (((uintptr_t)sq->eob - (uintptr_t)sq->buf) >>
 337                          MLX4_TXBB_SHIFT) - 1;
 338         uint32_t pkts = 0;
 339         /*
 340          * Traverse over all CQ entries reported and handle each WQ entry
 341          * reported by them.
 342          */
 343         do {
 344                 cqe = (volatile struct mlx4_cqe *)mlx4_get_cqe(cq, cons_index);
 345                 if (unlikely(!!(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
 346                     !!(cons_index & cq->cqe_cnt)))
 347                         break;
 348 #ifndef NDEBUG
 349                 /*
 350                  * Make sure we read the CQE after we read the ownership bit.
 351                  */
 352                 rte_io_rmb();
 353                 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
 354                              MLX4_CQE_OPCODE_ERROR)) {
 355                         volatile struct mlx4_err_cqe *cqe_err =
 356                                 (volatile struct mlx4_err_cqe *)cqe;
 357                         ERROR("%p CQE error - vendor syndrome: 0x%x"
 358                               " syndrome: 0x%x\n",
 359                               (void *)txq, cqe_err->vendor_err,
 360                               cqe_err->syndrome);
 361                         break;
 362                 }
 363 #endif /* NDEBUG */
 364                 /* Get WQE address buy index from the CQE. */
 365                 last_wqe = (volatile uint32_t *)((uintptr_t)sq->buf +
 366                         ((rte_be_to_cpu_16(cqe->wqe_index) & mask) <<
 367                          MLX4_TXBB_SHIFT));
 368                 do {
 369                         /* Free next descriptor. */
 370                         first_wqe = next_wqe;
 371                         sq->remain_size +=
 372                                 mlx4_txq_stamp_freed_wqe(sq, &next_wqe);
 373                         pkts++;
 374                 } while (first_wqe != last_wqe);
 375                 cons_index++;
 376         } while (1);
 377         if (unlikely(pkts == 0))
 378                 return;
 379         /* Update CQ consumer index. */
 380         cq->cons_index = cons_index;
 381         *cq->set_ci_db = rte_cpu_to_be_32(cons_index & MLX4_CQ_DB_CI_MASK);
 382         txq->elts_comp -= pkts;
 383         elts_tail += pkts;
 384         if (elts_tail >= elts_n)
 385                 elts_tail -= elts_n;
 386         txq->elts_tail = elts_tail;
 387 }
 388
 389 /**
 390  * Get memory pool (MP) from mbuf. If mbuf is indirect, the pool from which
 391  * the cloned mbuf is allocated is returned instead.
 392  *
 393  * @param buf
 394  *   Pointer to mbuf.
 395  *
 396  * @return
 397  *   Memory pool where data is located for given mbuf.
 398  */
 399 static struct rte_mempool *
 400 mlx4_txq_mb2mp(struct rte_mbuf *buf)
 401 {
 402         if (unlikely(RTE_MBUF_INDIRECT(buf)))
 403                 return rte_mbuf_from_indirect(buf)->pool;
 404         return buf->pool;
 405 }
 406
 407 /**
 408  * Write Tx data segment to the SQ.
 409  *
 410  * @param dseg
 411  *   Pointer to data segment in SQ.
 412  * @param lkey
 413  *   Memory region lkey.
 414  * @param addr
 415  *   Data address.
 416  * @param byte_count
 417  *   Big endian bytes count of the data to send.
 418  */
 419 static inline void
 420 mlx4_fill_tx_data_seg(volatile struct mlx4_wqe_data_seg *dseg,
 421                        uint32_t lkey, uintptr_t addr, rte_be32_t  byte_count)
 422 {
 423         dseg->addr = rte_cpu_to_be_64(addr);
 424         dseg->lkey = rte_cpu_to_be_32(lkey);
 425 #if RTE_CACHE_LINE_SIZE < 64
 426         /*
 427          * Need a barrier here before writing the byte_count
 428          * fields to make sure that all the data is visible
 429          * before the byte_count field is set.
 430          * Otherwise, if the segment begins a new cacheline,
 431          * the HCA prefetcher could grab the 64-byte chunk and
 432          * get a valid (!= 0xffffffff) byte count but stale
 433          * data, and end up sending the wrong data.
 434          */
 435         rte_io_wmb();
 436 #endif /* RTE_CACHE_LINE_SIZE */
 437         dseg->byte_count = byte_count;
 438 }
 439
 440 /**
 441  * Write data segments of multi-segment packet.
 442  *
 443  * @param buf
 444  *   Pointer to the first packet mbuf.
 445  * @param txq
 446  *   Pointer to Tx queue structure.
 447  * @param ctrl
 448  *   Pointer to the WQE control segment.
 449  *
 450  * @return
 451  *   Pointer to the next WQE control segment on success, NULL otherwise.
 452  */
 453 static volatile struct mlx4_wqe_ctrl_seg *
 454 mlx4_tx_burst_segs(struct rte_mbuf *buf, struct txq *txq,
 455                    volatile struct mlx4_wqe_ctrl_seg *ctrl)
 456 {
 457         struct pv *pv = (struct pv *)txq->bounce_buf;
 458         struct mlx4_sq *sq = &txq->msq;
 459         struct rte_mbuf *sbuf = buf;
 460         uint32_t lkey;
 461         int pv_counter = 0;
 462         int nb_segs = buf->nb_segs;
 463         uint32_t wqe_size;
 464         volatile struct mlx4_wqe_data_seg *dseg =
 465                 (volatile struct mlx4_wqe_data_seg *)(ctrl + 1);
 466
 467         ctrl->fence_size = 1 + nb_segs;
 468         wqe_size = RTE_ALIGN((uint32_t)(ctrl->fence_size << MLX4_SEG_SHIFT),
 469                              MLX4_TXBB_SIZE);
 470         /* Validate WQE size and WQE space in the send queue. */
 471         if (sq->remain_size < wqe_size ||
 472             wqe_size > MLX4_MAX_WQE_SIZE)
 473                 return NULL;
 474         /*
 475          * Fill the data segments with buffer information.
 476          * First WQE TXBB head segment is always control segment,
 477          * so jump to tail TXBB data segments code for the first
 478          * WQE data segments filling.
 479          */
 480         goto txbb_tail_segs;
 481 txbb_head_seg:
 482         /* Memory region key (big endian) for this memory pool. */
 483         lkey = mlx4_txq_mp2mr(txq, mlx4_txq_mb2mp(sbuf));
 484         if (unlikely(lkey == (uint32_t)-1)) {
 485                 DEBUG("%p: unable to get MP <-> MR association",
 486                       (void *)txq);
 487                 return NULL;
 488         }
 489         /* Handle WQE wraparound. */
 490         if (dseg >=
 491                 (volatile struct mlx4_wqe_data_seg *)sq->eob)
 492                 dseg = (volatile struct mlx4_wqe_data_seg *)
 493                         sq->buf;
 494         dseg->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(sbuf, uintptr_t));
 495         dseg->lkey = rte_cpu_to_be_32(lkey);
 496         /*
 497          * This data segment starts at the beginning of a new
 498          * TXBB, so we need to postpone its byte_count writing
 499          * for later.
 500          */
 501         pv[pv_counter].dseg = dseg;
 502         /*
 503          * Zero length segment is treated as inline segment
 504          * with zero data.
 505          */
 506         pv[pv_counter++].val = rte_cpu_to_be_32(sbuf->data_len ?
 507                                                 sbuf->data_len : 0x80000000);
 508         sbuf = sbuf->next;
 509         dseg++;
 510         nb_segs--;
 511 txbb_tail_segs:
 512         /* Jump to default if there are more than two segments remaining. */
 513         switch (nb_segs) {
 514         default:
 515                 lkey = mlx4_txq_mp2mr(txq, mlx4_txq_mb2mp(sbuf));
 516                 if (unlikely(lkey == (uint32_t)-1)) {
 517                         DEBUG("%p: unable to get MP <-> MR association",
 518                               (void *)txq);
 519                         return NULL;
 520                 }
 521                 mlx4_fill_tx_data_seg(dseg, lkey,
 522                                       rte_pktmbuf_mtod(sbuf, uintptr_t),
 523                                       rte_cpu_to_be_32(sbuf->data_len ?
 524                                                        sbuf->data_len :
 525                                                        0x80000000));
 526                 sbuf = sbuf->next;
 527                 dseg++;
 528                 nb_segs--;
 529                 /* fallthrough */
 530         case 2:
 531                 lkey = mlx4_txq_mp2mr(txq, mlx4_txq_mb2mp(sbuf));
 532                 if (unlikely(lkey == (uint32_t)-1)) {
 533                         DEBUG("%p: unable to get MP <-> MR association",
 534                               (void *)txq);
 535                         return NULL;
 536                 }
 537                 mlx4_fill_tx_data_seg(dseg, lkey,
 538                                       rte_pktmbuf_mtod(sbuf, uintptr_t),
 539                                       rte_cpu_to_be_32(sbuf->data_len ?
 540                                                        sbuf->data_len :
 541                                                        0x80000000));
 542                 sbuf = sbuf->next;
 543                 dseg++;
 544                 nb_segs--;
 545                 /* fallthrough */
 546         case 1:
 547                 lkey = mlx4_txq_mp2mr(txq, mlx4_txq_mb2mp(sbuf));
 548                 if (unlikely(lkey == (uint32_t)-1)) {
 549                         DEBUG("%p: unable to get MP <-> MR association",
 550                               (void *)txq);
 551                         return NULL;
 552                 }
 553                 mlx4_fill_tx_data_seg(dseg, lkey,
 554                                       rte_pktmbuf_mtod(sbuf, uintptr_t),
 555                                       rte_cpu_to_be_32(sbuf->data_len ?
 556                                                        sbuf->data_len :
 557                                                        0x80000000));
 558                 nb_segs--;
 559                 if (nb_segs) {
 560                         sbuf = sbuf->next;
 561                         dseg++;
 562                         goto txbb_head_seg;
 563                 }
 564                 /* fallthrough */
 565         case 0:
 566                 break;
 567         }
 568         /* Write the first DWORD of each TXBB save earlier. */
 569         if (pv_counter) {
 570                 /* Need a barrier here before writing the byte_count. */
 571                 rte_io_wmb();
 572                 for (--pv_counter; pv_counter  >= 0; pv_counter--)
 573                         pv[pv_counter].dseg->byte_count = pv[pv_counter].val;
 574         }
 575         sq->remain_size -= wqe_size;
 576         /* Align next WQE address to the next TXBB. */
 577         return (volatile struct mlx4_wqe_ctrl_seg *)
 578                 ((volatile uint8_t *)ctrl + wqe_size);
 579 }
 580
 581 /**
 582  * DPDK callback for Tx.
 583  *
 584  * @param dpdk_txq
 585  *   Generic pointer to Tx queue structure.
 586  * @param[in] pkts
 587  *   Packets to transmit.
 588  * @param pkts_n
 589  *   Number of packets in array.
 590  *
 591  * @return
 592  *   Number of packets successfully transmitted (<= pkts_n).
 593  */
 594 uint16_t
 595 mlx4_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 596 {
 597         struct txq *txq = (struct txq *)dpdk_txq;
 598         unsigned int elts_head = txq->elts_head;
 599         const unsigned int elts_n = txq->elts_n;
 600         unsigned int bytes_sent = 0;
 601         unsigned int i;
 602         unsigned int max;
 603         struct mlx4_sq *sq = &txq->msq;
 604         volatile struct mlx4_wqe_ctrl_seg *ctrl;
 605         struct txq_elt *elt;
 606
 607         assert(txq->elts_comp_cd != 0);
 608         if (likely(txq->elts_comp != 0))
 609                 mlx4_txq_complete(txq, elts_n, sq);
 610         max = (elts_n - (elts_head - txq->elts_tail));
 611         if (max > elts_n)
 612                 max -= elts_n;
 613         assert(max >= 1);
 614         assert(max <= elts_n);
 615         /* Always leave one free entry in the ring. */
 616         --max;
 617         if (max > pkts_n)
 618                 max = pkts_n;
 619         elt = &(*txq->elts)[elts_head];
 620         /* Each element saves its appropriate work queue. */
 621         ctrl = elt->wqe;
 622         for (i = 0; (i != max); ++i) {
 623                 struct rte_mbuf *buf = pkts[i];
 624                 unsigned int elts_head_next =
 625                         (((elts_head + 1) == elts_n) ? 0 : elts_head + 1);
 626                 struct txq_elt *elt_next = &(*txq->elts)[elts_head_next];
 627                 uint32_t owner_opcode = sq->owner_opcode;
 628                 volatile struct mlx4_wqe_data_seg *dseg =
 629                                 (volatile struct mlx4_wqe_data_seg *)(ctrl + 1);
 630                 volatile struct mlx4_wqe_ctrl_seg *ctrl_next;
 631                 union {
 632                         uint32_t flags;
 633                         uint16_t flags16[2];
 634                 } srcrb;
 635                 uint32_t lkey;
 636
 637                 /* Clean up old buffer. */
 638                 if (likely(elt->buf != NULL)) {
 639                         struct rte_mbuf *tmp = elt->buf;
 640
 641 #ifndef NDEBUG
 642                         /* Poisoning. */
 643                         memset(&elt->buf, 0x66, sizeof(struct rte_mbuf *));
 644 #endif
 645                         /* Faster than rte_pktmbuf_free(). */
 646                         do {
 647                                 struct rte_mbuf *next = tmp->next;
 648
 649                                 rte_pktmbuf_free_seg(tmp);
 650                                 tmp = next;
 651                         } while (tmp != NULL);
 652                 }
 653                 RTE_MBUF_PREFETCH_TO_FREE(elt_next->buf);
 654                 if (buf->nb_segs == 1) {
 655                         /* Validate WQE space in the send queue. */
 656                         if (sq->remain_size < MLX4_TXBB_SIZE) {
 657                                 elt->buf = NULL;
 658                                 break;
 659                         }
 660                         lkey = mlx4_txq_mp2mr(txq, mlx4_txq_mb2mp(buf));
 661                         if (unlikely(lkey == (uint32_t)-1)) {
 662                                 /* MR does not exist. */
 663                                 DEBUG("%p: unable to get MP <-> MR association",
 664                                       (void *)txq);
 665                                 elt->buf = NULL;
 666                                 break;
 667                         }
 668                         mlx4_fill_tx_data_seg(dseg++, lkey,
 669                                               rte_pktmbuf_mtod(buf, uintptr_t),
 670                                               rte_cpu_to_be_32(buf->data_len));
 671                         /* Set WQE size in 16-byte units. */
 672                         ctrl->fence_size = 0x2;
 673                         sq->remain_size -= MLX4_TXBB_SIZE;
 674                         /* Align next WQE address to the next TXBB. */
 675                         ctrl_next = ctrl + 0x4;
 676                 } else {
 677                         ctrl_next = mlx4_tx_burst_segs(buf, txq, ctrl);
 678                         if (!ctrl_next) {
 679                                 elt->buf = NULL;
 680                                 break;
 681                         }
 682                 }
 683                 /* Hold SQ ring wrap around. */
 684                 if ((volatile uint8_t *)ctrl_next >= sq->eob) {
 685                         ctrl_next = (volatile struct mlx4_wqe_ctrl_seg *)
 686                                 ((volatile uint8_t *)ctrl_next - sq->size);
 687                         /* Flip HW valid ownership. */
 688                         sq->owner_opcode ^= 0x1 << MLX4_SQ_OWNER_BIT;
 689                 }
 690                 /*
 691                  * For raw Ethernet, the SOLICIT flag is used to indicate
 692                  * that no ICRC should be calculated.
 693                  */
 694                 if (--txq->elts_comp_cd == 0) {
 695                         txq->elts_comp_cd = txq->elts_comp_cd_init;
 696                         srcrb.flags = RTE_BE32(MLX4_WQE_CTRL_SOLICIT |
 697                                                MLX4_WQE_CTRL_CQ_UPDATE);
 698                 } else {
 699                         srcrb.flags = RTE_BE32(MLX4_WQE_CTRL_SOLICIT);
 700                 }
 701                 /* Enable HW checksum offload if requested */
 702                 if (txq->csum &&
 703                     (buf->ol_flags &
 704                      (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))) {
 705                         const uint64_t is_tunneled = (buf->ol_flags &
 706                                                       (PKT_TX_TUNNEL_GRE |
 707                                                        PKT_TX_TUNNEL_VXLAN));
 708
 709                         if (is_tunneled && txq->csum_l2tun) {
 710                                 owner_opcode |= MLX4_WQE_CTRL_IIP_HDR_CSUM |
 711                                                 MLX4_WQE_CTRL_IL4_HDR_CSUM;
 712                                 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
 713                                         srcrb.flags |=
 714                                             RTE_BE32(MLX4_WQE_CTRL_IP_HDR_CSUM);
 715                         } else {
 716                                 srcrb.flags |=
 717                                         RTE_BE32(MLX4_WQE_CTRL_IP_HDR_CSUM |
 718                                                 MLX4_WQE_CTRL_TCP_UDP_CSUM);
 719                         }
 720                 }
 721                 if (txq->lb) {
 722                         /*
 723                          * Copy destination MAC address to the WQE, this allows
 724                          * loopback in eSwitch, so that VFs and PF can
 725                          * communicate with each other.
 726                          */
 727                         srcrb.flags16[0] = *(rte_pktmbuf_mtod(buf, uint16_t *));
 728                         ctrl->imm = *(rte_pktmbuf_mtod_offset(buf, uint32_t *,
 729                                               sizeof(uint16_t)));
 730                 } else {
 731                         ctrl->imm = 0;
 732                 }
 733                 ctrl->srcrb_flags = srcrb.flags;
 734                 /*
 735                  * Make sure descriptor is fully written before
 736                  * setting ownership bit (because HW can start
 737                  * executing as soon as we do).
 738                  */
 739                 rte_io_wmb();
 740                 ctrl->owner_opcode = rte_cpu_to_be_32(owner_opcode);
 741                 elt->buf = buf;
 742                 bytes_sent += buf->pkt_len;
 743                 elts_head = elts_head_next;
 744                 elt_next->wqe = ctrl_next;
 745                 ctrl = ctrl_next;
 746                 elt = elt_next;
 747         }
 748         /* Take a shortcut if nothing must be sent. */
 749         if (unlikely(i == 0))
 750                 return 0;
 751         /* Increment send statistics counters. */
 752         txq->stats.opackets += i;
 753         txq->stats.obytes += bytes_sent;
 754         /* Make sure that descriptors are written before doorbell record. */
 755         rte_wmb();
 756         /* Ring QP doorbell. */
 757         rte_write32(txq->msq.doorbell_qpn, txq->msq.db);
 758         txq->elts_head = elts_head;
 759         txq->elts_comp += i;
 760         return i;
 761 }
 762
 763 /**
 764  * Translate Rx completion flags to packet type.
 765  *
 766  * @param[in] cqe
 767  *   Pointer to CQE.
 768  *
 769  * @return
 770  *   Packet type for struct rte_mbuf.
 771  */
 772 static inline uint32_t
 773 rxq_cq_to_pkt_type(volatile struct mlx4_cqe *cqe,
 774                    uint32_t l2tun_offload)
 775 {
 776         uint8_t idx = 0;
 777         uint32_t pinfo = rte_be_to_cpu_32(cqe->vlan_my_qpn);
 778         uint32_t status = rte_be_to_cpu_32(cqe->status);
 779
 780         /*
 781          * The index to the array should have:
 782          *  bit[7] - MLX4_CQE_L2_TUNNEL
 783          *  bit[6] - MLX4_CQE_L2_TUNNEL_IPV4
 784          */
 785         if (l2tun_offload && (pinfo & MLX4_CQE_L2_TUNNEL))
 786                 idx |= ((pinfo & MLX4_CQE_L2_TUNNEL) >> 20) |
 787                        ((pinfo & MLX4_CQE_L2_TUNNEL_IPV4) >> 19);
 788         /*
 789          * The index to the array should have:
 790          *  bit[5] - MLX4_CQE_STATUS_UDP
 791          *  bit[4] - MLX4_CQE_STATUS_TCP
 792          *  bit[3] - MLX4_CQE_STATUS_IPV4OPT
 793          *  bit[2] - MLX4_CQE_STATUS_IPV6
 794          *  bit[1] - MLX4_CQE_STATUS_IPV4F
 795          *  bit[0] - MLX4_CQE_STATUS_IPV4
 796          * giving a total of up to 256 entries.
 797          */
 798         idx |= ((status & MLX4_CQE_STATUS_PTYPE_MASK) >> 22);
 799         return mlx4_ptype_table[idx];
 800 }
 801
 802 /**
 803  * Translate Rx completion flags to offload flags.
 804  *
 805  * @param flags
 806  *   Rx completion flags returned by mlx4_cqe_flags().
 807  * @param csum
 808  *   Whether Rx checksums are enabled.
 809  * @param csum_l2tun
 810  *   Whether Rx L2 tunnel checksums are enabled.
 811  *
 812  * @return
 813  *   Offload flags (ol_flags) in mbuf format.
 814  */
 815 static inline uint32_t
 816 rxq_cq_to_ol_flags(uint32_t flags, int csum, int csum_l2tun)
 817 {
 818         uint32_t ol_flags = 0;
 819
 820         if (csum)
 821                 ol_flags |=
 822                         mlx4_transpose(flags,
 823                                        MLX4_CQE_STATUS_IP_HDR_CSUM_OK,
 824                                        PKT_RX_IP_CKSUM_GOOD) |
 825                         mlx4_transpose(flags,
 826                                        MLX4_CQE_STATUS_TCP_UDP_CSUM_OK,
 827                                        PKT_RX_L4_CKSUM_GOOD);
 828         if ((flags & MLX4_CQE_L2_TUNNEL) && csum_l2tun)
 829                 ol_flags |=
 830                         mlx4_transpose(flags,
 831                                        MLX4_CQE_L2_TUNNEL_IPOK,
 832                                        PKT_RX_IP_CKSUM_GOOD) |
 833                         mlx4_transpose(flags,
 834                                        MLX4_CQE_L2_TUNNEL_L4_CSUM,
 835                                        PKT_RX_L4_CKSUM_GOOD);
 836         return ol_flags;
 837 }
 838
 839 /**
 840  * Extract checksum information from CQE flags.
 841  *
 842  * @param cqe
 843  *   Pointer to CQE structure.
 844  * @param csum
 845  *   Whether Rx checksums are enabled.
 846  * @param csum_l2tun
 847  *   Whether Rx L2 tunnel checksums are enabled.
 848  *
 849  * @return
 850  *   CQE checksum information.
 851  */
 852 static inline uint32_t
 853 mlx4_cqe_flags(volatile struct mlx4_cqe *cqe, int csum, int csum_l2tun)
 854 {
 855         uint32_t flags = 0;
 856
 857         /*
 858          * The relevant bits are in different locations on their
 859          * CQE fields therefore we can join them in one 32bit
 860          * variable.
 861          */
 862         if (csum)
 863                 flags = (rte_be_to_cpu_32(cqe->status) &
 864                          MLX4_CQE_STATUS_IPV4_CSUM_OK);
 865         if (csum_l2tun)
 866                 flags |= (rte_be_to_cpu_32(cqe->vlan_my_qpn) &
 867                           (MLX4_CQE_L2_TUNNEL |
 868                            MLX4_CQE_L2_TUNNEL_IPOK |
 869                            MLX4_CQE_L2_TUNNEL_L4_CSUM |
 870                            MLX4_CQE_L2_TUNNEL_IPV4));
 871         return flags;
 872 }
 873
 874 /**
 875  * Poll one CQE from CQ.
 876  *
 877  * @param rxq
 878  *   Pointer to the receive queue structure.
 879  * @param[out] out
 880  *   Just polled CQE.
 881  *
 882  * @return
 883  *   Number of bytes of the CQE, 0 in case there is no completion.
 884  */
 885 static unsigned int
 886 mlx4_cq_poll_one(struct rxq *rxq, volatile struct mlx4_cqe **out)
 887 {
 888         int ret = 0;
 889         volatile struct mlx4_cqe *cqe = NULL;
 890         struct mlx4_cq *cq = &rxq->mcq;
 891
 892         cqe = (volatile struct mlx4_cqe *)mlx4_get_cqe(cq, cq->cons_index);
 893         if (!!(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
 894             !!(cq->cons_index & cq->cqe_cnt))
 895                 goto out;
 896         /*
 897          * Make sure we read CQ entry contents after we've checked the
 898          * ownership bit.
 899          */
 900         rte_rmb();
 901         assert(!(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK));
 902         assert((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) !=
 903                MLX4_CQE_OPCODE_ERROR);
 904         ret = rte_be_to_cpu_32(cqe->byte_cnt);
 905         ++cq->cons_index;
 906 out:
 907         *out = cqe;
 908         return ret;
 909 }
 910
 911 /**
 912  * DPDK callback for Rx with scattered packets support.
 913  *
 914  * @param dpdk_rxq
 915  *   Generic pointer to Rx queue structure.
 916  * @param[out] pkts
 917  *   Array to store received packets.
 918  * @param pkts_n
 919  *   Maximum number of packets in array.
 920  *
 921  * @return
 922  *   Number of packets successfully received (<= pkts_n).
 923  */
 924 uint16_t
 925 mlx4_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
 926 {
 927         struct rxq *rxq = dpdk_rxq;
 928         const uint32_t wr_cnt = (1 << rxq->elts_n) - 1;
 929         const uint16_t sges_n = rxq->sges_n;
 930         struct rte_mbuf *pkt = NULL;
 931         struct rte_mbuf *seg = NULL;
 932         unsigned int i = 0;
 933         uint32_t rq_ci = rxq->rq_ci << sges_n;
 934         int len = 0;
 935
 936         while (pkts_n) {
 937                 volatile struct mlx4_cqe *cqe;
 938                 uint32_t idx = rq_ci & wr_cnt;
 939                 struct rte_mbuf *rep = (*rxq->elts)[idx];
 940                 volatile struct mlx4_wqe_data_seg *scat = &(*rxq->wqes)[idx];
 941
 942                 /* Update the 'next' pointer of the previous segment. */
 943                 if (pkt)
 944                         seg->next = rep;
 945                 seg = rep;
 946                 rte_prefetch0(seg);
 947                 rte_prefetch0(scat);
 948                 rep = rte_mbuf_raw_alloc(rxq->mp);
 949                 if (unlikely(rep == NULL)) {
 950                         ++rxq->stats.rx_nombuf;
 951                         if (!pkt) {
 952                                 /*
 953                                  * No buffers before we even started,
 954                                  * bail out silently.
 955                                  */
 956                                 break;
 957                         }
 958                         while (pkt != seg) {
 959                                 assert(pkt != (*rxq->elts)[idx]);
 960                                 rep = pkt->next;
 961                                 pkt->next = NULL;
 962                                 pkt->nb_segs = 1;
 963                                 rte_mbuf_raw_free(pkt);
 964                                 pkt = rep;
 965                         }
 966                         break;
 967                 }
 968                 if (!pkt) {
 969                         /* Looking for the new packet. */
 970                         len = mlx4_cq_poll_one(rxq, &cqe);
 971                         if (!len) {
 972                                 rte_mbuf_raw_free(rep);
 973                                 break;
 974                         }
 975                         if (unlikely(len < 0)) {
 976                                 /* Rx error, packet is likely too large. */
 977                                 rte_mbuf_raw_free(rep);
 978                                 ++rxq->stats.idropped;
 979                                 goto skip;
 980                         }
 981                         pkt = seg;
 982                         /* Update packet information. */
 983                         pkt->packet_type =
 984                                 rxq_cq_to_pkt_type(cqe, rxq->l2tun_offload);
 985                         pkt->ol_flags = PKT_RX_RSS_HASH;
 986                         pkt->hash.rss = cqe->immed_rss_invalid;
 987                         pkt->pkt_len = len;
 988                         if (rxq->csum | rxq->csum_l2tun) {
 989                                 uint32_t flags =
 990                                         mlx4_cqe_flags(cqe,
 991                                                        rxq->csum,
 992                                                        rxq->csum_l2tun);
 993
 994                                 pkt->ol_flags =
 995                                         rxq_cq_to_ol_flags(flags,
 996                                                            rxq->csum,
 997                                                            rxq->csum_l2tun);
 998                         }
 999                 }
1000                 rep->nb_segs = 1;
1001                 rep->port = rxq->port_id;
1002                 rep->data_len = seg->data_len;
1003                 rep->data_off = seg->data_off;
1004                 (*rxq->elts)[idx] = rep;
1005                 /*
1006                  * Fill NIC descriptor with the new buffer. The lkey and size
1007                  * of the buffers are already known, only the buffer address
1008                  * changes.
1009                  */
1010                 scat->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1011                 if (len > seg->data_len) {
1012                         len -= seg->data_len;
1013                         ++pkt->nb_segs;
1014                         ++rq_ci;
1015                         continue;
1016                 }
1017                 /* The last segment. */
1018                 seg->data_len = len;
1019                 /* Increment bytes counter. */
1020                 rxq->stats.ibytes += pkt->pkt_len;
1021                 /* Return packet. */
1022                 *(pkts++) = pkt;
1023                 pkt = NULL;
1024                 --pkts_n;
1025                 ++i;
1026 skip:
1027                 /* Align consumer index to the next stride. */
1028                 rq_ci >>= sges_n;
1029                 ++rq_ci;
1030                 rq_ci <<= sges_n;
1031         }
1032         if (unlikely(i == 0 && (rq_ci >> sges_n) == rxq->rq_ci))
1033                 return 0;
1034         /* Update the consumer index. */
1035         rxq->rq_ci = rq_ci >> sges_n;
1036         rte_wmb();
1037         *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1038         *rxq->mcq.set_ci_db =
1039                 rte_cpu_to_be_32(rxq->mcq.cons_index & MLX4_CQ_DB_CI_MASK);
1040         /* Increment packets counter. */
1041         rxq->stats.ipackets += i;
1042         return i;
1043 }
1044
1045 /**
1046  * Dummy DPDK callback for Tx.
1047  *
1048  * This function is used to temporarily replace the real callback during
1049  * unsafe control operations on the queue, or in case of error.
1050  *
1051  * @param dpdk_txq
1052  *   Generic pointer to Tx queue structure.
1053  * @param[in] pkts
1054  *   Packets to transmit.
1055  * @param pkts_n
1056  *   Number of packets in array.
1057  *
1058  * @return
1059  *   Number of packets successfully transmitted (<= pkts_n).
1060  */
1061 uint16_t
1062 mlx4_tx_burst_removed(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1063 {
1064         (void)dpdk_txq;
1065         (void)pkts;
1066         (void)pkts_n;
1067         return 0;
1068 }
1069
1070 /**
1071  * Dummy DPDK callback for Rx.
1072  *
1073  * This function is used to temporarily replace the real callback during
1074  * unsafe control operations on the queue, or in case of error.
1075  *
1076  * @param dpdk_rxq
1077  *   Generic pointer to Rx queue structure.
1078  * @param[out] pkts
1079  *   Array to store received packets.
1080  * @param pkts_n
1081  *   Maximum number of packets in array.
1082  *
1083  * @return
1084  *   Number of packets successfully received (<= pkts_n).
1085  */
1086 uint16_t
1087 mlx4_rx_burst_removed(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1088 {
1089         (void)dpdk_rxq;
1090         (void)pkts;
1091         (void)pkts_n;
1092         return 0;
1093 }