drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12 #include <net/if.h>
  13 #include <sys/mman.h>
  14 #include <linux/rtnetlink.h>
  15
  16 /* Verbs header. */
  17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  18 #ifdef PEDANTIC
  19 #pragma GCC diagnostic ignored "-Wpedantic"
  20 #endif
  21 #include <infiniband/verbs.h>
  22 #ifdef PEDANTIC
  23 #pragma GCC diagnostic error "-Wpedantic"
  24 #endif
  25
  26 #include <rte_malloc.h>
  27 #include <rte_ethdev_driver.h>
  28 #include <rte_ethdev_pci.h>
  29 #include <rte_pci.h>
  30 #include <rte_bus_pci.h>
  31 #include <rte_common.h>
  32 #include <rte_kvargs.h>
  33 #include <rte_rwlock.h>
  34 #include <rte_spinlock.h>
  35 #include <rte_string_fns.h>
  36 #include <rte_alarm.h>
  37
  38 #include <mlx5_glue.h>
  39 #include <mlx5_devx_cmds.h>
  40 #include <mlx5_common.h>
  41 #include <mlx5_common_os.h>
  42 #include <mlx5_common_mp.h>
  43 #include <mlx5_malloc.h>
  44
  45 #include "mlx5_defs.h"
  46 #include "mlx5.h"
  47 #include "mlx5_utils.h"
  48 #include "mlx5_rxtx.h"
  49 #include "mlx5_autoconf.h"
  50 #include "mlx5_mr.h"
  51 #include "mlx5_flow.h"
  52 #include "rte_pmd_mlx5.h"
  53
  54 /* Device parameter to enable RX completion queue compression. */
  55 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  56
  57 /* Device parameter to enable RX completion entry padding to 128B. */
  58 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
  59
  60 /* Device parameter to enable padding Rx packet to cacheline size. */
  61 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  62
  63 /* Device parameter to enable Multi-Packet Rx queue. */
  64 #define MLX5_RX_MPRQ_EN "mprq_en"
  65
  66 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  67 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  68
  69 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  70 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  71
  72 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  73 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  74
  75 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  76 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  77
  78 /* Device parameter to configure inline send. Deprecated, ignored.*/
  79 #define MLX5_TXQ_INLINE "txq_inline"
  80
  81 /* Device parameter to limit packet size to inline with ordinary SEND. */
  82 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  83
  84 /* Device parameter to configure minimal data size to inline. */
  85 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  86
  87 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  88 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  89
  90 /*
  91  * Device parameter to configure the number of TX queues threshold for
  92  * enabling inline send.
  93  */
  94 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  95
  96 /*
  97  * Device parameter to configure the number of TX queues threshold for
  98  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  99  */
 100 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
 101
 102 /* Device parameter to enable multi-packet send WQEs. */
 103 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
 104
 105 /*
 106  * Device parameter to force doorbell register mapping
 107  * to non-cahed region eliminating the extra write memory barrier.
 108  */
 109 #define MLX5_TX_DB_NC "tx_db_nc"
 110
 111 /*
 112  * Device parameter to include 2 dsegs in the title WQEBB.
 113  * Deprecated, ignored.
 114  */
 115 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 116
 117 /*
 118  * Device parameter to limit the size of inlining packet.
 119  * Deprecated, ignored.
 120  */
 121 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 122
 123 /*
 124  * Device parameter to enable Tx scheduling on timestamps
 125  * and specify the packet pacing granularity in nanoseconds.
 126  */
 127 #define MLX5_TX_PP "tx_pp"
 128
 129 /*
 130  * Device parameter to specify skew in nanoseconds on Tx datapath,
 131  * it represents the time between SQ start WQE processing and
 132  * appearing actual packet data on the wire.
 133  */
 134 #define MLX5_TX_SKEW "tx_skew"
 135
 136 /*
 137  * Device parameter to enable hardware Tx vector.
 138  * Deprecated, ignored (no vectorized Tx routines anymore).
 139  */
 140 #define MLX5_TX_VEC_EN "tx_vec_en"
 141
 142 /* Device parameter to enable hardware Rx vector. */
 143 #define MLX5_RX_VEC_EN "rx_vec_en"
 144
 145 /* Allow L3 VXLAN flow creation. */
 146 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 147
 148 /* Activate DV E-Switch flow steering. */
 149 #define MLX5_DV_ESW_EN "dv_esw_en"
 150
 151 /* Activate DV flow steering. */
 152 #define MLX5_DV_FLOW_EN "dv_flow_en"
 153
 154 /* Enable extensive flow metadata support. */
 155 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 156
 157 /* Device parameter to let the user manage the lacp traffic of bonded device */
 158 #define MLX5_LACP_BY_USER "lacp_by_user"
 159
 160 /* Activate Netlink support in VF mode. */
 161 #define MLX5_VF_NL_EN "vf_nl_en"
 162
 163 /* Enable extending memsegs when creating a MR. */
 164 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 165
 166 /* Select port representors to instantiate. */
 167 #define MLX5_REPRESENTOR "representor"
 168
 169 /* Device parameter to configure the maximum number of dump files per queue. */
 170 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 171
 172 /* Configure timeout of LRO session (in microseconds). */
 173 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 174
 175 /*
 176  * Device parameter to configure the total data buffer size for a single
 177  * hairpin queue (logarithm value).
 178  */
 179 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 180
 181 /* Flow memory reclaim mode. */
 182 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 183
 184 /* The default memory allocator used in PMD. */
 185 #define MLX5_SYS_MEM_EN "sys_mem_en"
 186 /* Decap will be used or not. */
 187 #define MLX5_DECAP_EN "decap_en"
 188
 189 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
 190
 191 /* Shared memory between primary and secondary processes. */
 192 struct mlx5_shared_data *mlx5_shared_data;
 193
 194 /* Spinlock for mlx5_shared_data allocation. */
 195 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
 196
 197 /* Process local data for secondary processes. */
 198 static struct mlx5_local_data mlx5_local_data;
 199
 200 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 201                                                 LIST_HEAD_INITIALIZER();
 202 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
 203
 204 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 205 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 206         {
 207                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 208                 .trunk_size = 64,
 209                 .grow_trunk = 3,
 210                 .grow_shift = 2,
 211                 .need_lock = 0,
 212                 .release_mem_en = 1,
 213                 .malloc = mlx5_malloc,
 214                 .free = mlx5_free,
 215                 .type = "mlx5_encap_decap_ipool",
 216         },
 217         {
 218                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 219                 .trunk_size = 64,
 220                 .grow_trunk = 3,
 221                 .grow_shift = 2,
 222                 .need_lock = 0,
 223                 .release_mem_en = 1,
 224                 .malloc = mlx5_malloc,
 225                 .free = mlx5_free,
 226                 .type = "mlx5_push_vlan_ipool",
 227         },
 228         {
 229                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 230                 .trunk_size = 64,
 231                 .grow_trunk = 3,
 232                 .grow_shift = 2,
 233                 .need_lock = 0,
 234                 .release_mem_en = 1,
 235                 .malloc = mlx5_malloc,
 236                 .free = mlx5_free,
 237                 .type = "mlx5_tag_ipool",
 238         },
 239         {
 240                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 241                 .trunk_size = 64,
 242                 .grow_trunk = 3,
 243                 .grow_shift = 2,
 244                 .need_lock = 0,
 245                 .release_mem_en = 1,
 246                 .malloc = mlx5_malloc,
 247                 .free = mlx5_free,
 248                 .type = "mlx5_port_id_ipool",
 249         },
 250         {
 251                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 252                 .trunk_size = 64,
 253                 .grow_trunk = 3,
 254                 .grow_shift = 2,
 255                 .need_lock = 0,
 256                 .release_mem_en = 1,
 257                 .malloc = mlx5_malloc,
 258                 .free = mlx5_free,
 259                 .type = "mlx5_jump_ipool",
 260         },
 261 #endif
 262         {
 263                 .size = sizeof(struct mlx5_flow_meter),
 264                 .trunk_size = 64,
 265                 .grow_trunk = 3,
 266                 .grow_shift = 2,
 267                 .need_lock = 0,
 268                 .release_mem_en = 1,
 269                 .malloc = mlx5_malloc,
 270                 .free = mlx5_free,
 271                 .type = "mlx5_meter_ipool",
 272         },
 273         {
 274                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 275                 .trunk_size = 64,
 276                 .grow_trunk = 3,
 277                 .grow_shift = 2,
 278                 .need_lock = 0,
 279                 .release_mem_en = 1,
 280                 .malloc = mlx5_malloc,
 281                 .free = mlx5_free,
 282                 .type = "mlx5_mcp_ipool",
 283         },
 284         {
 285                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 286                 .trunk_size = 64,
 287                 .grow_trunk = 3,
 288                 .grow_shift = 2,
 289                 .need_lock = 0,
 290                 .release_mem_en = 1,
 291                 .malloc = mlx5_malloc,
 292                 .free = mlx5_free,
 293                 .type = "mlx5_hrxq_ipool",
 294         },
 295         {
 296                 /*
 297                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 298                  * It set in run time according to PCI function configuration.
 299                  */
 300                 .size = 0,
 301                 .trunk_size = 64,
 302                 .grow_trunk = 3,
 303                 .grow_shift = 2,
 304                 .need_lock = 0,
 305                 .release_mem_en = 1,
 306                 .malloc = mlx5_malloc,
 307                 .free = mlx5_free,
 308                 .type = "mlx5_flow_handle_ipool",
 309         },
 310         {
 311                 .size = sizeof(struct rte_flow),
 312                 .trunk_size = 4096,
 313                 .need_lock = 1,
 314                 .release_mem_en = 1,
 315                 .malloc = mlx5_malloc,
 316                 .free = mlx5_free,
 317                 .type = "rte_flow_ipool",
 318         },
 319 };
 320
 321
 322 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 323 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 324
 325 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 326
 327 /**
 328  * Allocate ID pool structure.
 329  *
 330  * @param[in] max_id
 331  *   The maximum id can be allocated from the pool.
 332  *
 333  * @return
 334  *   Pointer to pool object, NULL value otherwise.
 335  */
 336 struct mlx5_flow_id_pool *
 337 mlx5_flow_id_pool_alloc(uint32_t max_id)
 338 {
 339         struct mlx5_flow_id_pool *pool;
 340         void *mem;
 341
 342         pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool),
 343                            RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 344         if (!pool) {
 345                 DRV_LOG(ERR, "can't allocate id pool");
 346                 rte_errno  = ENOMEM;
 347                 return NULL;
 348         }
 349         mem = mlx5_malloc(MLX5_MEM_ZERO,
 350                           MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
 351                           RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 352         if (!mem) {
 353                 DRV_LOG(ERR, "can't allocate mem for id pool");
 354                 rte_errno  = ENOMEM;
 355                 goto error;
 356         }
 357         pool->free_arr = mem;
 358         pool->curr = pool->free_arr;
 359         pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
 360         pool->base_index = 0;
 361         pool->max_id = max_id;
 362         return pool;
 363 error:
 364         mlx5_free(pool);
 365         return NULL;
 366 }
 367
 368 /**
 369  * Release ID pool structure.
 370  *
 371  * @param[in] pool
 372  *   Pointer to flow id pool object to free.
 373  */
 374 void
 375 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
 376 {
 377         mlx5_free(pool->free_arr);
 378         mlx5_free(pool);
 379 }
 380
 381 /**
 382  * Generate ID.
 383  *
 384  * @param[in] pool
 385  *   Pointer to flow id pool.
 386  * @param[out] id
 387  *   The generated ID.
 388  *
 389  * @return
 390  *   0 on success, error value otherwise.
 391  */
 392 uint32_t
 393 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
 394 {
 395         if (pool->curr == pool->free_arr) {
 396                 if (pool->base_index == pool->max_id) {
 397                         rte_errno  = ENOMEM;
 398                         DRV_LOG(ERR, "no free id");
 399                         return -rte_errno;
 400                 }
 401                 *id = ++pool->base_index;
 402                 return 0;
 403         }
 404         *id = *(--pool->curr);
 405         return 0;
 406 }
 407
 408 /**
 409  * Release ID.
 410  *
 411  * @param[in] pool
 412  *   Pointer to flow id pool.
 413  * @param[out] id
 414  *   The generated ID.
 415  *
 416  * @return
 417  *   0 on success, error value otherwise.
 418  */
 419 uint32_t
 420 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
 421 {
 422         uint32_t size;
 423         uint32_t size2;
 424         void *mem;
 425
 426         if (pool->curr == pool->last) {
 427                 size = pool->curr - pool->free_arr;
 428                 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
 429                 MLX5_ASSERT(size2 > size);
 430                 mem = mlx5_malloc(0, size2 * sizeof(uint32_t), 0,
 431                                   SOCKET_ID_ANY);
 432                 if (!mem) {
 433                         DRV_LOG(ERR, "can't allocate mem for id pool");
 434                         rte_errno  = ENOMEM;
 435                         return -rte_errno;
 436                 }
 437                 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
 438                 mlx5_free(pool->free_arr);
 439                 pool->free_arr = mem;
 440                 pool->curr = pool->free_arr + size;
 441                 pool->last = pool->free_arr + size2;
 442         }
 443         *pool->curr = id;
 444         pool->curr++;
 445         return 0;
 446 }
 447
 448 /**
 449  * Initialize the shared aging list information per port.
 450  *
 451  * @param[in] sh
 452  *   Pointer to mlx5_dev_ctx_shared object.
 453  */
 454 static void
 455 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 456 {
 457         uint32_t i;
 458         struct mlx5_age_info *age_info;
 459
 460         for (i = 0; i < sh->max_port; i++) {
 461                 age_info = &sh->port[i].age_info;
 462                 age_info->flags = 0;
 463                 TAILQ_INIT(&age_info->aged_counters);
 464                 rte_spinlock_init(&age_info->aged_sl);
 465                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 466         }
 467 }
 468
 469 /**
 470  * Initialize the counters management structure.
 471  *
 472  * @param[in] sh
 473  *   Pointer to mlx5_dev_ctx_shared object to free
 474  */
 475 static void
 476 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 477 {
 478         int i;
 479
 480         memset(&sh->cmng, 0, sizeof(sh->cmng));
 481         TAILQ_INIT(&sh->cmng.flow_counters);
 482         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 483                 sh->cmng.ccont[i].min_id = MLX5_CNT_BATCH_OFFSET;
 484                 sh->cmng.ccont[i].max_id = -1;
 485                 sh->cmng.ccont[i].last_pool_idx = POOL_IDX_INVALID;
 486                 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
 487                 rte_spinlock_init(&sh->cmng.ccont[i].resize_sl);
 488                 TAILQ_INIT(&sh->cmng.ccont[i].counters);
 489                 rte_spinlock_init(&sh->cmng.ccont[i].csl);
 490         }
 491 }
 492
 493 /**
 494  * Destroy all the resources allocated for a counter memory management.
 495  *
 496  * @param[in] mng
 497  *   Pointer to the memory management structure.
 498  */
 499 static void
 500 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 501 {
 502         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 503
 504         LIST_REMOVE(mng, next);
 505         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 506         claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
 507         mlx5_free(mem);
 508 }
 509
 510 /**
 511  * Close and release all the resources of the counters management.
 512  *
 513  * @param[in] sh
 514  *   Pointer to mlx5_dev_ctx_shared object to free.
 515  */
 516 static void
 517 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 518 {
 519         struct mlx5_counter_stats_mem_mng *mng;
 520         int i;
 521         int j;
 522         int retries = 1024;
 523
 524         rte_errno = 0;
 525         while (--retries) {
 526                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 527                 if (rte_errno != EINPROGRESS)
 528                         break;
 529                 rte_pause();
 530         }
 531         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 532                 struct mlx5_flow_counter_pool *pool;
 533                 uint32_t batch = !!(i > 1);
 534
 535                 if (!sh->cmng.ccont[i].pools)
 536                         continue;
 537                 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 538                 while (pool) {
 539                         if (batch && pool->min_dcs)
 540                                 claim_zero(mlx5_devx_cmd_destroy
 541                                                                (pool->min_dcs));
 542                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 543                                 if (MLX5_POOL_GET_CNT(pool, j)->action)
 544                                         claim_zero
 545                                          (mlx5_glue->destroy_flow_action
 546                                           (MLX5_POOL_GET_CNT
 547                                           (pool, j)->action));
 548                                 if (!batch && MLX5_GET_POOL_CNT_EXT
 549                                     (pool, j)->dcs)
 550                                         claim_zero(mlx5_devx_cmd_destroy
 551                                                    (MLX5_GET_POOL_CNT_EXT
 552                                                     (pool, j)->dcs));
 553                         }
 554                         TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, next);
 555                         mlx5_free(pool);
 556                         pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 557                 }
 558                 mlx5_free(sh->cmng.ccont[i].pools);
 559         }
 560         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 561         while (mng) {
 562                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 563                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 564         }
 565         memset(&sh->cmng, 0, sizeof(sh->cmng));
 566 }
 567
 568 /**
 569  * Initialize the flow resources' indexed mempool.
 570  *
 571  * @param[in] sh
 572  *   Pointer to mlx5_dev_ctx_shared object.
 573  * @param[in] sh
 574  *   Pointer to user dev config.
 575  */
 576 static void
 577 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 578                        const struct mlx5_dev_config *config)
 579 {
 580         uint8_t i;
 581         struct mlx5_indexed_pool_config cfg;
 582
 583         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 584                 cfg = mlx5_ipool_cfg[i];
 585                 switch (i) {
 586                 default:
 587                         break;
 588                 /*
 589                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 590                  * according to PCI function flow configuration.
 591                  */
 592                 case MLX5_IPOOL_MLX5_FLOW:
 593                         cfg.size = config->dv_flow_en ?
 594                                 sizeof(struct mlx5_flow_handle) :
 595                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 596                         break;
 597                 }
 598                 if (config->reclaim_mode)
 599                         cfg.release_mem_en = 1;
 600                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 601         }
 602 }
 603
 604 /**
 605  * Release the flow resources' indexed mempool.
 606  *
 607  * @param[in] sh
 608  *   Pointer to mlx5_dev_ctx_shared object.
 609  */
 610 static void
 611 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 612 {
 613         uint8_t i;
 614
 615         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 616                 mlx5_ipool_destroy(sh->ipool[i]);
 617 }
 618
 619 /*
 620  * Check if dynamic flex parser for eCPRI already exists.
 621  *
 622  * @param dev
 623  *   Pointer to Ethernet device structure.
 624  *
 625  * @return
 626  *   true on exists, false on not.
 627  */
 628 bool
 629 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
 630 {
 631         struct mlx5_priv *priv = dev->data->dev_private;
 632         struct mlx5_flex_parser_profiles *prf =
 633                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 634
 635         return !!prf->obj;
 636 }
 637
 638 /*
 639  * Allocation of a flex parser for eCPRI. Once created, this parser related
 640  * resources will be held until the device is closed.
 641  *
 642  * @param dev
 643  *   Pointer to Ethernet device structure.
 644  *
 645  * @return
 646  *   0 on success, a negative errno value otherwise and rte_errno is set.
 647  */
 648 int
 649 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
 650 {
 651         struct mlx5_priv *priv = dev->data->dev_private;
 652         struct mlx5_flex_parser_profiles *prf =
 653                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 654         struct mlx5_devx_graph_node_attr node = {
 655                 .modify_field_select = 0,
 656         };
 657         uint32_t ids[8];
 658         int ret;
 659
 660         if (!priv->config.hca_attr.parse_graph_flex_node) {
 661                 DRV_LOG(ERR, "Dynamic flex parser is not supported "
 662                         "for device %s.", priv->dev_data->name);
 663                 return -ENOTSUP;
 664         }
 665         node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
 666         /* 8 bytes now: 4B common header + 4B message body header. */
 667         node.header_length_base_value = 0x8;
 668         /* After MAC layer: Ether / VLAN. */
 669         node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
 670         /* Type of compared condition should be 0xAEFE in the L2 layer. */
 671         node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
 672         /* Sample #0: type in common header. */
 673         node.sample[0].flow_match_sample_en = 1;
 674         /* Fixed offset. */
 675         node.sample[0].flow_match_sample_offset_mode = 0x0;
 676         /* Only the 2nd byte will be used. */
 677         node.sample[0].flow_match_sample_field_base_offset = 0x0;
 678         /* Sample #1: message payload. */
 679         node.sample[1].flow_match_sample_en = 1;
 680         /* Fixed offset. */
 681         node.sample[1].flow_match_sample_offset_mode = 0x0;
 682         /*
 683          * Only the first two bytes will be used right now, and its offset will
 684          * start after the common header that with the length of a DW(u32).
 685          */
 686         node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
 687         prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
 688         if (!prf->obj) {
 689                 DRV_LOG(ERR, "Failed to create flex parser node object.");
 690                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 691         }
 692         prf->num = 2;
 693         ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
 694         if (ret) {
 695                 DRV_LOG(ERR, "Failed to query sample IDs.");
 696                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 697         }
 698         prf->offset[0] = 0x0;
 699         prf->offset[1] = sizeof(uint32_t);
 700         prf->ids[0] = ids[0];
 701         prf->ids[1] = ids[1];
 702         return 0;
 703 }
 704
 705 /*
 706  * Destroy the flex parser node, including the parser itself, input / output
 707  * arcs and DW samples. Resources could be reused then.
 708  *
 709  * @param dev
 710  *   Pointer to Ethernet device structure.
 711  */
 712 static void
 713 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
 714 {
 715         struct mlx5_priv *priv = dev->data->dev_private;
 716         struct mlx5_flex_parser_profiles *prf =
 717                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 718
 719         if (prf->obj)
 720                 mlx5_devx_cmd_destroy(prf->obj);
 721         prf->obj = NULL;
 722 }
 723
 724 /**
 725  * Allocate shared device context. If there is multiport device the
 726  * master and representors will share this context, if there is single
 727  * port dedicated device, the context will be used by only given
 728  * port due to unification.
 729  *
 730  * Routine first searches the context for the specified device name,
 731  * if found the shared context assumed and reference counter is incremented.
 732  * If no context found the new one is created and initialized with specified
 733  * device context and parameters.
 734  *
 735  * @param[in] spawn
 736  *   Pointer to the device attributes (name, port, etc).
 737  * @param[in] config
 738  *   Pointer to device configuration structure.
 739  *
 740  * @return
 741  *   Pointer to mlx5_dev_ctx_shared object on success,
 742  *   otherwise NULL and rte_errno is set.
 743  */
 744 struct mlx5_dev_ctx_shared *
 745 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
 746                            const struct mlx5_dev_config *config)
 747 {
 748         struct mlx5_dev_ctx_shared *sh;
 749         int err = 0;
 750         uint32_t i;
 751         struct mlx5_devx_tis_attr tis_attr = { 0 };
 752
 753         MLX5_ASSERT(spawn);
 754         /* Secondary process should not create the shared context. */
 755         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 756         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 757         /* Search for IB context by device name. */
 758         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
 759                 if (!strcmp(sh->ibdev_name,
 760                         mlx5_os_get_dev_device_name(spawn->phys_dev))) {
 761                         sh->refcnt++;
 762                         goto exit;
 763                 }
 764         }
 765         /* No device found, we have to create new shared context. */
 766         MLX5_ASSERT(spawn->max_port);
 767         sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
 768                          sizeof(struct mlx5_dev_ctx_shared) +
 769                          spawn->max_port *
 770                          sizeof(struct mlx5_dev_shared_port),
 771                          RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 772         if (!sh) {
 773                 DRV_LOG(ERR, "shared context allocation failure");
 774                 rte_errno  = ENOMEM;
 775                 goto exit;
 776         }
 777         err = mlx5_os_open_device(spawn, config, sh);
 778         if (!sh->ctx)
 779                 goto error;
 780         err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
 781         if (err) {
 782                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
 783                 goto error;
 784         }
 785         sh->refcnt = 1;
 786         sh->max_port = spawn->max_port;
 787         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
 788                 sizeof(sh->ibdev_name) - 1);
 789         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
 790                 sizeof(sh->ibdev_path) - 1);
 791         /*
 792          * Setting port_id to max unallowed value means
 793          * there is no interrupt subhandler installed for
 794          * the given port index i.
 795          */
 796         for (i = 0; i < sh->max_port; i++) {
 797                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 798                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
 799         }
 800         sh->pd = mlx5_glue->alloc_pd(sh->ctx);
 801         if (sh->pd == NULL) {
 802                 DRV_LOG(ERR, "PD allocation failure");
 803                 err = ENOMEM;
 804                 goto error;
 805         }
 806         if (sh->devx) {
 807                 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
 808                 if (err) {
 809                         DRV_LOG(ERR, "Fail to extract pdn from PD");
 810                         goto error;
 811                 }
 812                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
 813                 if (!sh->td) {
 814                         DRV_LOG(ERR, "TD allocation failure");
 815                         err = ENOMEM;
 816                         goto error;
 817                 }
 818                 tis_attr.transport_domain = sh->td->id;
 819                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
 820                 if (!sh->tis) {
 821                         DRV_LOG(ERR, "TIS allocation failure");
 822                         err = ENOMEM;
 823                         goto error;
 824                 }
 825                 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, 0);
 826                 if (!sh->tx_uar) {
 827                         DRV_LOG(ERR, "Failed to allocate DevX UAR.");
 828                         err = ENOMEM;
 829                         goto error;
 830                 }
 831         }
 832         sh->flow_id_pool = mlx5_flow_id_pool_alloc
 833                                         ((1 << HAIRPIN_FLOW_ID_BITS) - 1);
 834         if (!sh->flow_id_pool) {
 835                 DRV_LOG(ERR, "can't create flow id pool");
 836                 err = ENOMEM;
 837                 goto error;
 838         }
 839 #ifndef RTE_ARCH_64
 840         /* Initialize UAR access locks for 32bit implementations. */
 841         rte_spinlock_init(&sh->uar_lock_cq);
 842         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
 843                 rte_spinlock_init(&sh->uar_lock[i]);
 844 #endif
 845         /*
 846          * Once the device is added to the list of memory event
 847          * callback, its global MR cache table cannot be expanded
 848          * on the fly because of deadlock. If it overflows, lookup
 849          * should be done by searching MR list linearly, which is slow.
 850          *
 851          * At this point the device is not added to the memory
 852          * event list yet, context is just being created.
 853          */
 854         err = mlx5_mr_btree_init(&sh->share_cache.cache,
 855                                  MLX5_MR_BTREE_CACHE_N * 2,
 856                                  spawn->pci_dev->device.numa_node);
 857         if (err) {
 858                 err = rte_errno;
 859                 goto error;
 860         }
 861         mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
 862                               &sh->share_cache.dereg_mr_cb);
 863         mlx5_os_dev_shared_handler_install(sh);
 864         sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
 865         if (!sh->cnt_id_tbl) {
 866                 err = rte_errno;
 867                 goto error;
 868         }
 869         mlx5_flow_aging_init(sh);
 870         mlx5_flow_counters_mng_init(sh);
 871         mlx5_flow_ipool_create(sh, config);
 872         /* Add device to memory callback list. */
 873         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 874         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
 875                          sh, mem_event_cb);
 876         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 877         /* Add context to the global device list. */
 878         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
 879 exit:
 880         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 881         return sh;
 882 error:
 883         pthread_mutex_destroy(&sh->txpp.mutex);
 884         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 885         MLX5_ASSERT(sh);
 886         if (sh->cnt_id_tbl) {
 887                 mlx5_l3t_destroy(sh->cnt_id_tbl);
 888                 sh->cnt_id_tbl = NULL;
 889         }
 890         if (sh->tx_uar) {
 891                 mlx5_glue->devx_free_uar(sh->tx_uar);
 892                 sh->tx_uar = NULL;
 893         }
 894         if (sh->tis)
 895                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 896         if (sh->td)
 897                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 898         if (sh->pd)
 899                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 900         if (sh->ctx)
 901                 claim_zero(mlx5_glue->close_device(sh->ctx));
 902         if (sh->flow_id_pool)
 903                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 904         mlx5_free(sh);
 905         MLX5_ASSERT(err > 0);
 906         rte_errno = err;
 907         return NULL;
 908 }
 909
 910 /**
 911  * Free shared IB device context. Decrement counter and if zero free
 912  * all allocated resources and close handles.
 913  *
 914  * @param[in] sh
 915  *   Pointer to mlx5_dev_ctx_shared object to free
 916  */
 917 void
 918 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
 919 {
 920         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 921 #ifdef RTE_LIBRTE_MLX5_DEBUG
 922         /* Check the object presence in the list. */
 923         struct mlx5_dev_ctx_shared *lctx;
 924
 925         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
 926                 if (lctx == sh)
 927                         break;
 928         MLX5_ASSERT(lctx);
 929         if (lctx != sh) {
 930                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
 931                 goto exit;
 932         }
 933 #endif
 934         MLX5_ASSERT(sh);
 935         MLX5_ASSERT(sh->refcnt);
 936         /* Secondary process should not free the shared context. */
 937         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 938         if (--sh->refcnt)
 939                 goto exit;
 940         /* Remove from memory callback device list. */
 941         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 942         LIST_REMOVE(sh, mem_event_cb);
 943         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 944         /* Release created Memory Regions. */
 945         mlx5_mr_release_cache(&sh->share_cache);
 946         /* Remove context from the global device list. */
 947         LIST_REMOVE(sh, next);
 948         /*
 949          *  Ensure there is no async event handler installed.
 950          *  Only primary process handles async device events.
 951          **/
 952         mlx5_flow_counters_mng_close(sh);
 953         mlx5_flow_ipool_destroy(sh);
 954         mlx5_os_dev_shared_handler_uninstall(sh);
 955         if (sh->cnt_id_tbl) {
 956                 mlx5_l3t_destroy(sh->cnt_id_tbl);
 957                 sh->cnt_id_tbl = NULL;
 958         }
 959         if (sh->tx_uar) {
 960                 mlx5_glue->devx_free_uar(sh->tx_uar);
 961                 sh->tx_uar = NULL;
 962         }
 963         if (sh->pd)
 964                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 965         if (sh->tis)
 966                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 967         if (sh->td)
 968                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 969         if (sh->ctx)
 970                 claim_zero(mlx5_glue->close_device(sh->ctx));
 971         if (sh->flow_id_pool)
 972                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 973         pthread_mutex_destroy(&sh->txpp.mutex);
 974         mlx5_free(sh);
 975 exit:
 976         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 977 }
 978
 979 /**
 980  * Destroy table hash list and all the root entries per domain.
 981  *
 982  * @param[in] priv
 983  *   Pointer to the private device data structure.
 984  */
 985 void
 986 mlx5_free_table_hash_list(struct mlx5_priv *priv)
 987 {
 988         struct mlx5_dev_ctx_shared *sh = priv->sh;
 989         struct mlx5_flow_tbl_data_entry *tbl_data;
 990         union mlx5_flow_tbl_key table_key = {
 991                 {
 992                         .table_id = 0,
 993                         .reserved = 0,
 994                         .domain = 0,
 995                         .direction = 0,
 996                 }
 997         };
 998         struct mlx5_hlist_entry *pos;
 999
1000         if (!sh->flow_tbls)
1001                 return;
1002         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1003         if (pos) {
1004                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1005                                         entry);
1006                 MLX5_ASSERT(tbl_data);
1007                 mlx5_hlist_remove(sh->flow_tbls, pos);
1008                 mlx5_free(tbl_data);
1009         }
1010         table_key.direction = 1;
1011         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1012         if (pos) {
1013                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1014                                         entry);
1015                 MLX5_ASSERT(tbl_data);
1016                 mlx5_hlist_remove(sh->flow_tbls, pos);
1017                 mlx5_free(tbl_data);
1018         }
1019         table_key.direction = 0;
1020         table_key.domain = 1;
1021         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1022         if (pos) {
1023                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1024                                         entry);
1025                 MLX5_ASSERT(tbl_data);
1026                 mlx5_hlist_remove(sh->flow_tbls, pos);
1027                 mlx5_free(tbl_data);
1028         }
1029         mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
1030 }
1031
1032 /**
1033  * Initialize flow table hash list and create the root tables entry
1034  * for each domain.
1035  *
1036  * @param[in] priv
1037  *   Pointer to the private device data structure.
1038  *
1039  * @return
1040  *   Zero on success, positive error code otherwise.
1041  */
1042 int
1043 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
1044 {
1045         struct mlx5_dev_ctx_shared *sh = priv->sh;
1046         char s[MLX5_HLIST_NAMESIZE];
1047         int err = 0;
1048
1049         MLX5_ASSERT(sh);
1050         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1051         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
1052         if (!sh->flow_tbls) {
1053                 DRV_LOG(ERR, "flow tables with hash creation failed.");
1054                 err = ENOMEM;
1055                 return err;
1056         }
1057 #ifndef HAVE_MLX5DV_DR
1058         /*
1059          * In case we have not DR support, the zero tables should be created
1060          * because DV expect to see them even if they cannot be created by
1061          * RDMA-CORE.
1062          */
1063         union mlx5_flow_tbl_key table_key = {
1064                 {
1065                         .table_id = 0,
1066                         .reserved = 0,
1067                         .domain = 0,
1068                         .direction = 0,
1069                 }
1070         };
1071         struct mlx5_flow_tbl_data_entry *tbl_data = mlx5_malloc(MLX5_MEM_ZERO,
1072                                                           sizeof(*tbl_data), 0,
1073                                                           SOCKET_ID_ANY);
1074
1075         if (!tbl_data) {
1076                 err = ENOMEM;
1077                 goto error;
1078         }
1079         tbl_data->entry.key = table_key.v64;
1080         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1081         if (err)
1082                 goto error;
1083         rte_atomic32_init(&tbl_data->tbl.refcnt);
1084         rte_atomic32_inc(&tbl_data->tbl.refcnt);
1085         table_key.direction = 1;
1086         tbl_data = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tbl_data), 0,
1087                                SOCKET_ID_ANY);
1088         if (!tbl_data) {
1089                 err = ENOMEM;
1090                 goto error;
1091         }
1092         tbl_data->entry.key = table_key.v64;
1093         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1094         if (err)
1095                 goto error;
1096         rte_atomic32_init(&tbl_data->tbl.refcnt);
1097         rte_atomic32_inc(&tbl_data->tbl.refcnt);
1098         table_key.direction = 0;
1099         table_key.domain = 1;
1100         tbl_data = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tbl_data), 0,
1101                                SOCKET_ID_ANY);
1102         if (!tbl_data) {
1103                 err = ENOMEM;
1104                 goto error;
1105         }
1106         tbl_data->entry.key = table_key.v64;
1107         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1108         if (err)
1109                 goto error;
1110         rte_atomic32_init(&tbl_data->tbl.refcnt);
1111         rte_atomic32_inc(&tbl_data->tbl.refcnt);
1112         return err;
1113 error:
1114         mlx5_free_table_hash_list(priv);
1115 #endif /* HAVE_MLX5DV_DR */
1116         return err;
1117 }
1118
1119 /**
1120  * Initialize shared data between primary and secondary process.
1121  *
1122  * A memzone is reserved by primary process and secondary processes attach to
1123  * the memzone.
1124  *
1125  * @return
1126  *   0 on success, a negative errno value otherwise and rte_errno is set.
1127  */
1128 static int
1129 mlx5_init_shared_data(void)
1130 {
1131         const struct rte_memzone *mz;
1132         int ret = 0;
1133
1134         rte_spinlock_lock(&mlx5_shared_data_lock);
1135         if (mlx5_shared_data == NULL) {
1136                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
1137                         /* Allocate shared memory. */
1138                         mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
1139                                                  sizeof(*mlx5_shared_data),
1140                                                  SOCKET_ID_ANY, 0);
1141                         if (mz == NULL) {
1142                                 DRV_LOG(ERR,
1143                                         "Cannot allocate mlx5 shared data");
1144                                 ret = -rte_errno;
1145                                 goto error;
1146                         }
1147                         mlx5_shared_data = mz->addr;
1148                         memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
1149                         rte_spinlock_init(&mlx5_shared_data->lock);
1150                 } else {
1151                         /* Lookup allocated shared memory. */
1152                         mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
1153                         if (mz == NULL) {
1154                                 DRV_LOG(ERR,
1155                                         "Cannot attach mlx5 shared data");
1156                                 ret = -rte_errno;
1157                                 goto error;
1158                         }
1159                         mlx5_shared_data = mz->addr;
1160                         memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
1161                 }
1162         }
1163 error:
1164         rte_spinlock_unlock(&mlx5_shared_data_lock);
1165         return ret;
1166 }
1167
1168 /**
1169  * Retrieve integer value from environment variable.
1170  *
1171  * @param[in] name
1172  *   Environment variable name.
1173  *
1174  * @return
1175  *   Integer value, 0 if the variable is not set.
1176  */
1177 int
1178 mlx5_getenv_int(const char *name)
1179 {
1180         const char *val = getenv(name);
1181
1182         if (val == NULL)
1183                 return 0;
1184         return atoi(val);
1185 }
1186
1187 /**
1188  * DPDK callback to add udp tunnel port
1189  *
1190  * @param[in] dev
1191  *   A pointer to eth_dev
1192  * @param[in] udp_tunnel
1193  *   A pointer to udp tunnel
1194  *
1195  * @return
1196  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1197  */
1198 int
1199 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1200                          struct rte_eth_udp_tunnel *udp_tunnel)
1201 {
1202         MLX5_ASSERT(udp_tunnel != NULL);
1203         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1204             udp_tunnel->udp_port == 4789)
1205                 return 0;
1206         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1207             udp_tunnel->udp_port == 4790)
1208                 return 0;
1209         return -ENOTSUP;
1210 }
1211
1212 /**
1213  * Initialize process private data structure.
1214  *
1215  * @param dev
1216  *   Pointer to Ethernet device structure.
1217  *
1218  * @return
1219  *   0 on success, a negative errno value otherwise and rte_errno is set.
1220  */
1221 int
1222 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1223 {
1224         struct mlx5_priv *priv = dev->data->dev_private;
1225         struct mlx5_proc_priv *ppriv;
1226         size_t ppriv_size;
1227
1228         /*
1229          * UAR register table follows the process private structure. BlueFlame
1230          * registers for Tx queues are stored in the table.
1231          */
1232         ppriv_size =
1233                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1234         ppriv = mlx5_malloc(MLX5_MEM_RTE, ppriv_size, RTE_CACHE_LINE_SIZE,
1235                             dev->device->numa_node);
1236         if (!ppriv) {
1237                 rte_errno = ENOMEM;
1238                 return -rte_errno;
1239         }
1240         ppriv->uar_table_sz = ppriv_size;
1241         dev->process_private = ppriv;
1242         return 0;
1243 }
1244
1245 /**
1246  * Un-initialize process private data structure.
1247  *
1248  * @param dev
1249  *   Pointer to Ethernet device structure.
1250  */
1251 static void
1252 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1253 {
1254         if (!dev->process_private)
1255                 return;
1256         mlx5_free(dev->process_private);
1257         dev->process_private = NULL;
1258 }
1259
1260 /**
1261  * DPDK callback to close the device.
1262  *
1263  * Destroy all queues and objects, free memory.
1264  *
1265  * @param dev
1266  *   Pointer to Ethernet device structure.
1267  */
1268 void
1269 mlx5_dev_close(struct rte_eth_dev *dev)
1270 {
1271         struct mlx5_priv *priv = dev->data->dev_private;
1272         unsigned int i;
1273         int ret;
1274
1275         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1276                 /* Check if process_private released. */
1277                 if (!dev->process_private)
1278                         return;
1279                 mlx5_tx_uar_uninit_secondary(dev);
1280                 mlx5_proc_priv_uninit(dev);
1281                 rte_eth_dev_release_port(dev);
1282                 return;
1283         }
1284         if (!priv->sh)
1285                 return;
1286         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1287                 dev->data->port_id,
1288                 ((priv->sh->ctx != NULL) ?
1289                 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1290         /*
1291          * If default mreg copy action is removed at the stop stage,
1292          * the search will return none and nothing will be done anymore.
1293          */
1294         mlx5_flow_stop_default(dev);
1295         mlx5_traffic_disable(dev);
1296         /*
1297          * If all the flows are already flushed in the device stop stage,
1298          * then this will return directly without any action.
1299          */
1300         mlx5_flow_list_flush(dev, &priv->flows, true);
1301         mlx5_flow_meter_flush(dev, NULL);
1302         /* Free the intermediate buffers for flow creation. */
1303         mlx5_flow_free_intermediate(dev);
1304         /* Prevent crashes when queues are still in use. */
1305         dev->rx_pkt_burst = removed_rx_burst;
1306         dev->tx_pkt_burst = removed_tx_burst;
1307         rte_wmb();
1308         /* Disable datapath on secondary process. */
1309         mlx5_mp_req_stop_rxtx(dev);
1310         /* Free the eCPRI flex parser resource. */
1311         mlx5_flex_parser_ecpri_release(dev);
1312         if (priv->rxqs != NULL) {
1313                 /* XXX race condition if mlx5_rx_burst() is still running. */
1314                 usleep(1000);
1315                 for (i = 0; (i != priv->rxqs_n); ++i)
1316                         mlx5_rxq_release(dev, i);
1317                 priv->rxqs_n = 0;
1318                 priv->rxqs = NULL;
1319         }
1320         if (priv->txqs != NULL) {
1321                 /* XXX race condition if mlx5_tx_burst() is still running. */
1322                 usleep(1000);
1323                 for (i = 0; (i != priv->txqs_n); ++i)
1324                         mlx5_txq_release(dev, i);
1325                 priv->txqs_n = 0;
1326                 priv->txqs = NULL;
1327         }
1328         mlx5_proc_priv_uninit(dev);
1329         if (priv->mreg_cp_tbl)
1330                 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1331         mlx5_mprq_free_mp(dev);
1332         mlx5_os_free_shared_dr(priv);
1333         if (priv->rss_conf.rss_key != NULL)
1334                 mlx5_free(priv->rss_conf.rss_key);
1335         if (priv->reta_idx != NULL)
1336                 mlx5_free(priv->reta_idx);
1337         if (priv->config.vf)
1338                 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1339                                        dev->data->mac_addrs,
1340                                        MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1341         if (priv->nl_socket_route >= 0)
1342                 close(priv->nl_socket_route);
1343         if (priv->nl_socket_rdma >= 0)
1344                 close(priv->nl_socket_rdma);
1345         if (priv->vmwa_context)
1346                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1347         ret = mlx5_hrxq_verify(dev);
1348         if (ret)
1349                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1350                         dev->data->port_id);
1351         ret = mlx5_ind_table_obj_verify(dev);
1352         if (ret)
1353                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1354                         dev->data->port_id);
1355         ret = mlx5_rxq_obj_verify(dev);
1356         if (ret)
1357                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1358                         dev->data->port_id);
1359         ret = mlx5_rxq_verify(dev);
1360         if (ret)
1361                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1362                         dev->data->port_id);
1363         ret = mlx5_txq_obj_verify(dev);
1364         if (ret)
1365                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1366                         dev->data->port_id);
1367         ret = mlx5_txq_verify(dev);
1368         if (ret)
1369                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1370                         dev->data->port_id);
1371         ret = mlx5_flow_verify(dev);
1372         if (ret)
1373                 DRV_LOG(WARNING, "port %u some flows still remain",
1374                         dev->data->port_id);
1375         /*
1376          * Free the shared context in last turn, because the cleanup
1377          * routines above may use some shared fields, like
1378          * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1379          * ifindex if Netlink fails.
1380          */
1381         mlx5_free_shared_dev_ctx(priv->sh);
1382         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1383                 unsigned int c = 0;
1384                 uint16_t port_id;
1385
1386                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1387                         struct mlx5_priv *opriv =
1388                                 rte_eth_devices[port_id].data->dev_private;
1389
1390                         if (!opriv ||
1391                             opriv->domain_id != priv->domain_id ||
1392                             &rte_eth_devices[port_id] == dev)
1393                                 continue;
1394                         ++c;
1395                         break;
1396                 }
1397                 if (!c)
1398                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1399         }
1400         memset(priv, 0, sizeof(*priv));
1401         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1402         /*
1403          * Reset mac_addrs to NULL such that it is not freed as part of
1404          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1405          * it is freed when dev_private is freed.
1406          */
1407         dev->data->mac_addrs = NULL;
1408 }
1409
1410 /**
1411  * Verify and store value for device argument.
1412  *
1413  * @param[in] key
1414  *   Key argument to verify.
1415  * @param[in] val
1416  *   Value associated with key.
1417  * @param opaque
1418  *   User data.
1419  *
1420  * @return
1421  *   0 on success, a negative errno value otherwise and rte_errno is set.
1422  */
1423 static int
1424 mlx5_args_check(const char *key, const char *val, void *opaque)
1425 {
1426         struct mlx5_dev_config *config = opaque;
1427         unsigned long mod;
1428         signed long tmp;
1429
1430         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1431         if (!strcmp(MLX5_REPRESENTOR, key))
1432                 return 0;
1433         errno = 0;
1434         tmp = strtol(val, NULL, 0);
1435         if (errno) {
1436                 rte_errno = errno;
1437                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1438                 return -rte_errno;
1439         }
1440         if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1441                 /* Negative values are acceptable for some keys only. */
1442                 rte_errno = EINVAL;
1443                 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1444                 return -rte_errno;
1445         }
1446         mod = tmp >= 0 ? tmp : -tmp;
1447         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1448                 config->cqe_comp = !!tmp;
1449         } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1450                 config->cqe_pad = !!tmp;
1451         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1452                 config->hw_padding = !!tmp;
1453         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1454                 config->mprq.enabled = !!tmp;
1455         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1456                 config->mprq.stride_num_n = tmp;
1457         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1458                 config->mprq.stride_size_n = tmp;
1459         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1460                 config->mprq.max_memcpy_len = tmp;
1461         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1462                 config->mprq.min_rxqs_num = tmp;
1463         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1464                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1465                                  " converted to txq_inline_max", key);
1466                 config->txq_inline_max = tmp;
1467         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1468                 config->txq_inline_max = tmp;
1469         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1470                 config->txq_inline_min = tmp;
1471         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1472                 config->txq_inline_mpw = tmp;
1473         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1474                 config->txqs_inline = tmp;
1475         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1476                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1477         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1478                 config->mps = !!tmp;
1479         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1480                 if (tmp != MLX5_TXDB_CACHED &&
1481                     tmp != MLX5_TXDB_NCACHED &&
1482                     tmp != MLX5_TXDB_HEURISTIC) {
1483                         DRV_LOG(ERR, "invalid Tx doorbell "
1484                                      "mapping parameter");
1485                         rte_errno = EINVAL;
1486                         return -rte_errno;
1487                 }
1488                 config->dbnc = tmp;
1489         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1490                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1491         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1492                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1493                                  " converted to txq_inline_mpw", key);
1494                 config->txq_inline_mpw = tmp;
1495         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1496                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1497         } else if (strcmp(MLX5_TX_PP, key) == 0) {
1498                 if (!mod) {
1499                         DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1500                         rte_errno = EINVAL;
1501                         return -rte_errno;
1502                 }
1503                 config->tx_pp = tmp;
1504         } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1505                 config->tx_skew = tmp;
1506         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1507                 config->rx_vec_en = !!tmp;
1508         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1509                 config->l3_vxlan_en = !!tmp;
1510         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1511                 config->vf_nl_en = !!tmp;
1512         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1513                 config->dv_esw_en = !!tmp;
1514         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1515                 config->dv_flow_en = !!tmp;
1516         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1517                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1518                     tmp != MLX5_XMETA_MODE_META16 &&
1519                     tmp != MLX5_XMETA_MODE_META32) {
1520                         DRV_LOG(ERR, "invalid extensive "
1521                                      "metadata parameter");
1522                         rte_errno = EINVAL;
1523                         return -rte_errno;
1524                 }
1525                 config->dv_xmeta_en = tmp;
1526         } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1527                 config->lacp_by_user = !!tmp;
1528         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1529                 config->mr_ext_memseg_en = !!tmp;
1530         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1531                 config->max_dump_files_num = tmp;
1532         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1533                 config->lro.timeout = tmp;
1534         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1535                 DRV_LOG(DEBUG, "class argument is %s.", val);
1536         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1537                 config->log_hp_size = tmp;
1538         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1539                 if (tmp != MLX5_RCM_NONE &&
1540                     tmp != MLX5_RCM_LIGHT &&
1541                     tmp != MLX5_RCM_AGGR) {
1542                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1543                         rte_errno = EINVAL;
1544                         return -rte_errno;
1545                 }
1546                 config->reclaim_mode = tmp;
1547         } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1548                 config->sys_mem_en = !!tmp;
1549         } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1550                 config->decap_en = !!tmp;
1551         } else {
1552                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1553                 rte_errno = EINVAL;
1554                 return -rte_errno;
1555         }
1556         return 0;
1557 }
1558
1559 /**
1560  * Parse device parameters.
1561  *
1562  * @param config
1563  *   Pointer to device configuration structure.
1564  * @param devargs
1565  *   Device arguments structure.
1566  *
1567  * @return
1568  *   0 on success, a negative errno value otherwise and rte_errno is set.
1569  */
1570 int
1571 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1572 {
1573         const char **params = (const char *[]){
1574                 MLX5_RXQ_CQE_COMP_EN,
1575                 MLX5_RXQ_CQE_PAD_EN,
1576                 MLX5_RXQ_PKT_PAD_EN,
1577                 MLX5_RX_MPRQ_EN,
1578                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1579                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1580                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1581                 MLX5_RXQS_MIN_MPRQ,
1582                 MLX5_TXQ_INLINE,
1583                 MLX5_TXQ_INLINE_MIN,
1584                 MLX5_TXQ_INLINE_MAX,
1585                 MLX5_TXQ_INLINE_MPW,
1586                 MLX5_TXQS_MIN_INLINE,
1587                 MLX5_TXQS_MAX_VEC,
1588                 MLX5_TXQ_MPW_EN,
1589                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1590                 MLX5_TXQ_MAX_INLINE_LEN,
1591                 MLX5_TX_DB_NC,
1592                 MLX5_TX_PP,
1593                 MLX5_TX_SKEW,
1594                 MLX5_TX_VEC_EN,
1595                 MLX5_RX_VEC_EN,
1596                 MLX5_L3_VXLAN_EN,
1597                 MLX5_VF_NL_EN,
1598                 MLX5_DV_ESW_EN,
1599                 MLX5_DV_FLOW_EN,
1600                 MLX5_DV_XMETA_EN,
1601                 MLX5_LACP_BY_USER,
1602                 MLX5_MR_EXT_MEMSEG_EN,
1603                 MLX5_REPRESENTOR,
1604                 MLX5_MAX_DUMP_FILES_NUM,
1605                 MLX5_LRO_TIMEOUT_USEC,
1606                 MLX5_CLASS_ARG_NAME,
1607                 MLX5_HP_BUF_SIZE,
1608                 MLX5_RECLAIM_MEM,
1609                 MLX5_SYS_MEM_EN,
1610                 MLX5_DECAP_EN,
1611                 NULL,
1612         };
1613         struct rte_kvargs *kvlist;
1614         int ret = 0;
1615         int i;
1616
1617         if (devargs == NULL)
1618                 return 0;
1619         /* Following UGLY cast is done to pass checkpatch. */
1620         kvlist = rte_kvargs_parse(devargs->args, params);
1621         if (kvlist == NULL) {
1622                 rte_errno = EINVAL;
1623                 return -rte_errno;
1624         }
1625         /* Process parameters. */
1626         for (i = 0; (params[i] != NULL); ++i) {
1627                 if (rte_kvargs_count(kvlist, params[i])) {
1628                         ret = rte_kvargs_process(kvlist, params[i],
1629                                                  mlx5_args_check, config);
1630                         if (ret) {
1631                                 rte_errno = EINVAL;
1632                                 rte_kvargs_free(kvlist);
1633                                 return -rte_errno;
1634                         }
1635                 }
1636         }
1637         rte_kvargs_free(kvlist);
1638         return 0;
1639 }
1640
1641 /**
1642  * PMD global initialization.
1643  *
1644  * Independent from individual device, this function initializes global
1645  * per-PMD data structures distinguishing primary and secondary processes.
1646  * Hence, each initialization is called once per a process.
1647  *
1648  * @return
1649  *   0 on success, a negative errno value otherwise and rte_errno is set.
1650  */
1651 int
1652 mlx5_init_once(void)
1653 {
1654         struct mlx5_shared_data *sd;
1655         struct mlx5_local_data *ld = &mlx5_local_data;
1656         int ret = 0;
1657
1658         if (mlx5_init_shared_data())
1659                 return -rte_errno;
1660         sd = mlx5_shared_data;
1661         MLX5_ASSERT(sd);
1662         rte_spinlock_lock(&sd->lock);
1663         switch (rte_eal_process_type()) {
1664         case RTE_PROC_PRIMARY:
1665                 if (sd->init_done)
1666                         break;
1667                 LIST_INIT(&sd->mem_event_cb_list);
1668                 rte_rwlock_init(&sd->mem_event_rwlock);
1669                 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1670                                                 mlx5_mr_mem_event_cb, NULL);
1671                 ret = mlx5_mp_init_primary(MLX5_MP_NAME,
1672                                            mlx5_mp_primary_handle);
1673                 if (ret)
1674                         goto out;
1675                 sd->init_done = true;
1676                 break;
1677         case RTE_PROC_SECONDARY:
1678                 if (ld->init_done)
1679                         break;
1680                 ret = mlx5_mp_init_secondary(MLX5_MP_NAME,
1681                                              mlx5_mp_secondary_handle);
1682                 if (ret)
1683                         goto out;
1684                 ++sd->secondary_cnt;
1685                 ld->init_done = true;
1686                 break;
1687         default:
1688                 break;
1689         }
1690 out:
1691         rte_spinlock_unlock(&sd->lock);
1692         return ret;
1693 }
1694
1695 /**
1696  * Configures the minimal amount of data to inline into WQE
1697  * while sending packets.
1698  *
1699  * - the txq_inline_min has the maximal priority, if this
1700  *   key is specified in devargs
1701  * - if DevX is enabled the inline mode is queried from the
1702  *   device (HCA attributes and NIC vport context if needed).
1703  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1704  *   and none (0 bytes) for other NICs
1705  *
1706  * @param spawn
1707  *   Verbs device parameters (name, port, switch_info) to spawn.
1708  * @param config
1709  *   Device configuration parameters.
1710  */
1711 void
1712 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1713                     struct mlx5_dev_config *config)
1714 {
1715         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1716                 /* Application defines size of inlined data explicitly. */
1717                 switch (spawn->pci_dev->id.device_id) {
1718                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1719                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1720                         if (config->txq_inline_min <
1721                                        (int)MLX5_INLINE_HSIZE_L2) {
1722                                 DRV_LOG(DEBUG,
1723                                         "txq_inline_mix aligned to minimal"
1724                                         " ConnectX-4 required value %d",
1725                                         (int)MLX5_INLINE_HSIZE_L2);
1726                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1727                         }
1728                         break;
1729                 }
1730                 goto exit;
1731         }
1732         if (config->hca_attr.eth_net_offloads) {
1733                 /* We have DevX enabled, inline mode queried successfully. */
1734                 switch (config->hca_attr.wqe_inline_mode) {
1735                 case MLX5_CAP_INLINE_MODE_L2:
1736                         /* outer L2 header must be inlined. */
1737                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1738                         goto exit;
1739                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1740                         /* No inline data are required by NIC. */
1741                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1742                         config->hw_vlan_insert =
1743                                 config->hca_attr.wqe_vlan_insert;
1744                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1745                         goto exit;
1746                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1747                         /* inline mode is defined by NIC vport context. */
1748                         if (!config->hca_attr.eth_virt)
1749                                 break;
1750                         switch (config->hca_attr.vport_inline_mode) {
1751                         case MLX5_INLINE_MODE_NONE:
1752                                 config->txq_inline_min =
1753                                         MLX5_INLINE_HSIZE_NONE;
1754                                 goto exit;
1755                         case MLX5_INLINE_MODE_L2:
1756                                 config->txq_inline_min =
1757                                         MLX5_INLINE_HSIZE_L2;
1758                                 goto exit;
1759                         case MLX5_INLINE_MODE_IP:
1760                                 config->txq_inline_min =
1761                                         MLX5_INLINE_HSIZE_L3;
1762                                 goto exit;
1763                         case MLX5_INLINE_MODE_TCP_UDP:
1764                                 config->txq_inline_min =
1765                                         MLX5_INLINE_HSIZE_L4;
1766                                 goto exit;
1767                         case MLX5_INLINE_MODE_INNER_L2:
1768                                 config->txq_inline_min =
1769                                         MLX5_INLINE_HSIZE_INNER_L2;
1770                                 goto exit;
1771                         case MLX5_INLINE_MODE_INNER_IP:
1772                                 config->txq_inline_min =
1773                                         MLX5_INLINE_HSIZE_INNER_L3;
1774                                 goto exit;
1775                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
1776                                 config->txq_inline_min =
1777                                         MLX5_INLINE_HSIZE_INNER_L4;
1778                                 goto exit;
1779                         }
1780                 }
1781         }
1782         /*
1783          * We get here if we are unable to deduce
1784          * inline data size with DevX. Try PCI ID
1785          * to determine old NICs.
1786          */
1787         switch (spawn->pci_dev->id.device_id) {
1788         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1789         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1790         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1791         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1792                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1793                 config->hw_vlan_insert = 0;
1794                 break;
1795         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1796         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1797         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1798         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1799                 /*
1800                  * These NICs support VLAN insertion from WQE and
1801                  * report the wqe_vlan_insert flag. But there is the bug
1802                  * and PFC control may be broken, so disable feature.
1803                  */
1804                 config->hw_vlan_insert = 0;
1805                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1806                 break;
1807         default:
1808                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1809                 break;
1810         }
1811 exit:
1812         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1813 }
1814
1815 /**
1816  * Configures the metadata mask fields in the shared context.
1817  *
1818  * @param [in] dev
1819  *   Pointer to Ethernet device.
1820  */
1821 void
1822 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1823 {
1824         struct mlx5_priv *priv = dev->data->dev_private;
1825         struct mlx5_dev_ctx_shared *sh = priv->sh;
1826         uint32_t meta, mark, reg_c0;
1827
1828         reg_c0 = ~priv->vport_meta_mask;
1829         switch (priv->config.dv_xmeta_en) {
1830         case MLX5_XMETA_MODE_LEGACY:
1831                 meta = UINT32_MAX;
1832                 mark = MLX5_FLOW_MARK_MASK;
1833                 break;
1834         case MLX5_XMETA_MODE_META16:
1835                 meta = reg_c0 >> rte_bsf32(reg_c0);
1836                 mark = MLX5_FLOW_MARK_MASK;
1837                 break;
1838         case MLX5_XMETA_MODE_META32:
1839                 meta = UINT32_MAX;
1840                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1841                 break;
1842         default:
1843                 meta = 0;
1844                 mark = 0;
1845                 MLX5_ASSERT(false);
1846                 break;
1847         }
1848         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1849                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1850                                  sh->dv_mark_mask, mark);
1851         else
1852                 sh->dv_mark_mask = mark;
1853         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1854                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1855                                  sh->dv_meta_mask, meta);
1856         else
1857                 sh->dv_meta_mask = meta;
1858         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1859                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1860                                  sh->dv_meta_mask, reg_c0);
1861         else
1862                 sh->dv_regc0_mask = reg_c0;
1863         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1864         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1865         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1866         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1867 }
1868
1869 int
1870 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1871 {
1872         static const char *const dynf_names[] = {
1873                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1874                 RTE_MBUF_DYNFLAG_METADATA_NAME,
1875                 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
1876         };
1877         unsigned int i;
1878
1879         if (n < RTE_DIM(dynf_names))
1880                 return -ENOMEM;
1881         for (i = 0; i < RTE_DIM(dynf_names); i++) {
1882                 if (names[i] == NULL)
1883                         return -EINVAL;
1884                 strcpy(names[i], dynf_names[i]);
1885         }
1886         return RTE_DIM(dynf_names);
1887 }
1888
1889 /**
1890  * Comparison callback to sort device data.
1891  *
1892  * This is meant to be used with qsort().
1893  *
1894  * @param a[in]
1895  *   Pointer to pointer to first data object.
1896  * @param b[in]
1897  *   Pointer to pointer to second data object.
1898  *
1899  * @return
1900  *   0 if both objects are equal, less than 0 if the first argument is less
1901  *   than the second, greater than 0 otherwise.
1902  */
1903 int
1904 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1905                               struct mlx5_dev_config *config)
1906 {
1907         struct mlx5_dev_ctx_shared *sh = priv->sh;
1908         struct mlx5_dev_config *sh_conf = NULL;
1909         uint16_t port_id;
1910
1911         MLX5_ASSERT(sh);
1912         /* Nothing to compare for the single/first device. */
1913         if (sh->refcnt == 1)
1914                 return 0;
1915         /* Find the device with shared context. */
1916         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1917                 struct mlx5_priv *opriv =
1918                         rte_eth_devices[port_id].data->dev_private;
1919
1920                 if (opriv && opriv != priv && opriv->sh == sh) {
1921                         sh_conf = &opriv->config;
1922                         break;
1923                 }
1924         }
1925         if (!sh_conf)
1926                 return 0;
1927         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1928                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1929                              " for shared %s context", sh->ibdev_name);
1930                 rte_errno = EINVAL;
1931                 return rte_errno;
1932         }
1933         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1934                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1935                              " for shared %s context", sh->ibdev_name);
1936                 rte_errno = EINVAL;
1937                 return rte_errno;
1938         }
1939         return 0;
1940 }
1941
1942 /**
1943  * Look for the ethernet device belonging to mlx5 driver.
1944  *
1945  * @param[in] port_id
1946  *   port_id to start looking for device.
1947  * @param[in] pci_dev
1948  *   Pointer to the hint PCI device. When device is being probed
1949  *   the its siblings (master and preceding representors might
1950  *   not have assigned driver yet (because the mlx5_os_pci_probe()
1951  *   is not completed yet, for this case match on hint PCI
1952  *   device may be used to detect sibling device.
1953  *
1954  * @return
1955  *   port_id of found device, RTE_MAX_ETHPORT if not found.
1956  */
1957 uint16_t
1958 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
1959 {
1960         while (port_id < RTE_MAX_ETHPORTS) {
1961                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
1962
1963                 if (dev->state != RTE_ETH_DEV_UNUSED &&
1964                     dev->device &&
1965                     (dev->device == &pci_dev->device ||
1966                      (dev->device->driver &&
1967                      dev->device->driver->name &&
1968                      !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
1969                         break;
1970                 port_id++;
1971         }
1972         if (port_id >= RTE_MAX_ETHPORTS)
1973                 return RTE_MAX_ETHPORTS;
1974         return port_id;
1975 }
1976
1977 /**
1978  * DPDK callback to remove a PCI device.
1979  *
1980  * This function removes all Ethernet devices belong to a given PCI device.
1981  *
1982  * @param[in] pci_dev
1983  *   Pointer to the PCI device.
1984  *
1985  * @return
1986  *   0 on success, the function cannot fail.
1987  */
1988 static int
1989 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1990 {
1991         uint16_t port_id;
1992
1993         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
1994                 /*
1995                  * mlx5_dev_close() is not registered to secondary process,
1996                  * call the close function explicitly for secondary process.
1997                  */
1998                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
1999                         mlx5_dev_close(&rte_eth_devices[port_id]);
2000                 else
2001                         rte_eth_dev_close(port_id);
2002         }
2003         return 0;
2004 }
2005
2006 static const struct rte_pci_id mlx5_pci_id_map[] = {
2007         {
2008                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2009                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2010         },
2011         {
2012                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2013                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2014         },
2015         {
2016                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2017                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2018         },
2019         {
2020                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2021                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2022         },
2023         {
2024                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2025                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2026         },
2027         {
2028                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2029                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2030         },
2031         {
2032                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2033                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2034         },
2035         {
2036                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2037                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2038         },
2039         {
2040                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2041                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2042         },
2043         {
2044                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2045                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2046         },
2047         {
2048                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2049                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2050         },
2051         {
2052                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2053                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2054         },
2055         {
2056                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2057                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2058         },
2059         {
2060                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2061                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
2062         },
2063         {
2064                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2065                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2066         },
2067         {
2068                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2069                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2070         },
2071         {
2072                 .vendor_id = 0
2073         }
2074 };
2075
2076 struct rte_pci_driver mlx5_driver = {
2077         .driver = {
2078                 .name = MLX5_DRIVER_NAME
2079         },
2080         .id_table = mlx5_pci_id_map,
2081         .probe = mlx5_os_pci_probe,
2082         .remove = mlx5_pci_remove,
2083         .dma_map = mlx5_dma_map,
2084         .dma_unmap = mlx5_dma_unmap,
2085         .drv_flags = PCI_DRV_FLAGS,
2086 };
2087
2088 /* Initialize driver log type. */
2089 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
2090
2091 /**
2092  * Driver initialization routine.
2093  */
2094 RTE_INIT(rte_mlx5_pmd_init)
2095 {
2096         /* Build the static tables for Verbs conversion. */
2097         mlx5_set_ptype_table();
2098         mlx5_set_cksum_table();
2099         mlx5_set_swp_types_table();
2100         if (mlx5_glue)
2101                 rte_pci_register(&mlx5_driver);
2102 }
2103
2104 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2105 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2106 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");