1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
13 #include <rte_malloc.h>
14 #include <rte_ethdev_driver.h>
15 #include <rte_ethdev_pci.h>
17 #include <rte_bus_pci.h>
18 #include <rte_common.h>
19 #include <rte_kvargs.h>
20 #include <rte_rwlock.h>
21 #include <rte_spinlock.h>
22 #include <rte_string_fns.h>
23 #include <rte_alarm.h>
25 #include <mlx5_glue.h>
26 #include <mlx5_devx_cmds.h>
27 #include <mlx5_common.h>
28 #include <mlx5_common_os.h>
29 #include <mlx5_common_mp.h>
30 #include <mlx5_common_pci.h>
31 #include <mlx5_malloc.h>
33 #include "mlx5_defs.h"
35 #include "mlx5_utils.h"
36 #include "mlx5_rxtx.h"
37 #include "mlx5_autoconf.h"
39 #include "mlx5_flow.h"
40 #include "rte_pmd_mlx5.h"
42 /* Device parameter to enable RX completion queue compression. */
43 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
45 /* Device parameter to enable RX completion entry padding to 128B. */
46 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
48 /* Device parameter to enable padding Rx packet to cacheline size. */
49 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
51 /* Device parameter to enable Multi-Packet Rx queue. */
52 #define MLX5_RX_MPRQ_EN "mprq_en"
54 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
55 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
57 /* Device parameter to configure log 2 of the stride size for MPRQ. */
58 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
60 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
61 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
63 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
64 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
66 /* Device parameter to configure inline send. Deprecated, ignored.*/
67 #define MLX5_TXQ_INLINE "txq_inline"
69 /* Device parameter to limit packet size to inline with ordinary SEND. */
70 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
72 /* Device parameter to configure minimal data size to inline. */
73 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
75 /* Device parameter to limit packet size to inline with Enhanced MPW. */
76 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
79 * Device parameter to configure the number of TX queues threshold for
80 * enabling inline send.
82 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
85 * Device parameter to configure the number of TX queues threshold for
86 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
88 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
90 /* Device parameter to enable multi-packet send WQEs. */
91 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
94 * Device parameter to force doorbell register mapping
95 * to non-cahed region eliminating the extra write memory barrier.
97 #define MLX5_TX_DB_NC "tx_db_nc"
100 * Device parameter to include 2 dsegs in the title WQEBB.
101 * Deprecated, ignored.
103 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
106 * Device parameter to limit the size of inlining packet.
107 * Deprecated, ignored.
109 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
112 * Device parameter to enable Tx scheduling on timestamps
113 * and specify the packet pacing granularity in nanoseconds.
115 #define MLX5_TX_PP "tx_pp"
118 * Device parameter to specify skew in nanoseconds on Tx datapath,
119 * it represents the time between SQ start WQE processing and
120 * appearing actual packet data on the wire.
122 #define MLX5_TX_SKEW "tx_skew"
125 * Device parameter to enable hardware Tx vector.
126 * Deprecated, ignored (no vectorized Tx routines anymore).
128 #define MLX5_TX_VEC_EN "tx_vec_en"
130 /* Device parameter to enable hardware Rx vector. */
131 #define MLX5_RX_VEC_EN "rx_vec_en"
133 /* Allow L3 VXLAN flow creation. */
134 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
136 /* Activate DV E-Switch flow steering. */
137 #define MLX5_DV_ESW_EN "dv_esw_en"
139 /* Activate DV flow steering. */
140 #define MLX5_DV_FLOW_EN "dv_flow_en"
142 /* Enable extensive flow metadata support. */
143 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
145 /* Device parameter to let the user manage the lacp traffic of bonded device */
146 #define MLX5_LACP_BY_USER "lacp_by_user"
148 /* Activate Netlink support in VF mode. */
149 #define MLX5_VF_NL_EN "vf_nl_en"
151 /* Enable extending memsegs when creating a MR. */
152 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
154 /* Select port representors to instantiate. */
155 #define MLX5_REPRESENTOR "representor"
157 /* Device parameter to configure the maximum number of dump files per queue. */
158 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
160 /* Configure timeout of LRO session (in microseconds). */
161 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
164 * Device parameter to configure the total data buffer size for a single
165 * hairpin queue (logarithm value).
167 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
169 /* Flow memory reclaim mode. */
170 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
172 /* The default memory allocator used in PMD. */
173 #define MLX5_SYS_MEM_EN "sys_mem_en"
174 /* Decap will be used or not. */
175 #define MLX5_DECAP_EN "decap_en"
177 /* Shared memory between primary and secondary processes. */
178 struct mlx5_shared_data *mlx5_shared_data;
180 /** Driver-specific log messages type. */
183 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
184 LIST_HEAD_INITIALIZER();
185 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
187 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
188 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
190 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
196 .malloc = mlx5_malloc,
198 .type = "mlx5_encap_decap_ipool",
201 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
207 .malloc = mlx5_malloc,
209 .type = "mlx5_push_vlan_ipool",
212 .size = sizeof(struct mlx5_flow_dv_tag_resource),
218 .malloc = mlx5_malloc,
220 .type = "mlx5_tag_ipool",
223 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
229 .malloc = mlx5_malloc,
231 .type = "mlx5_port_id_ipool",
234 .size = sizeof(struct mlx5_flow_tbl_data_entry),
240 .malloc = mlx5_malloc,
242 .type = "mlx5_jump_ipool",
245 .size = sizeof(struct mlx5_flow_dv_sample_resource),
251 .malloc = mlx5_malloc,
253 .type = "mlx5_sample_ipool",
256 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
262 .malloc = mlx5_malloc,
264 .type = "mlx5_dest_array_ipool",
268 .size = sizeof(struct mlx5_flow_meter),
274 .malloc = mlx5_malloc,
276 .type = "mlx5_meter_ipool",
279 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
285 .malloc = mlx5_malloc,
287 .type = "mlx5_mcp_ipool",
290 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
296 .malloc = mlx5_malloc,
298 .type = "mlx5_hrxq_ipool",
302 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
303 * It set in run time according to PCI function configuration.
311 .malloc = mlx5_malloc,
313 .type = "mlx5_flow_handle_ipool",
316 .size = sizeof(struct rte_flow),
320 .malloc = mlx5_malloc,
322 .type = "rte_flow_ipool",
327 .type = "mlx5_flow_rss_id_ipool",
332 .type = "mlx5_flow_tnl_flow_ipool",
337 .type = "mlx5_flow_tnl_tbl_ipool",
340 .size = sizeof(struct mlx5_shared_action_rss),
346 .malloc = mlx5_malloc,
348 .type = "mlx5_shared_action_rss",
354 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
355 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
357 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
360 * Initialize the ASO aging management structure.
363 * Pointer to mlx5_dev_ctx_shared object to free
366 * 0 on success, a negative errno value otherwise and rte_errno is set.
369 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
375 sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
376 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
377 if (!sh->aso_age_mng) {
378 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
382 err = mlx5_aso_queue_init(sh);
384 mlx5_free(sh->aso_age_mng);
387 rte_spinlock_init(&sh->aso_age_mng->resize_sl);
388 rte_spinlock_init(&sh->aso_age_mng->free_sl);
389 LIST_INIT(&sh->aso_age_mng->free);
394 * Close and release all the resources of the ASO aging management structure.
397 * Pointer to mlx5_dev_ctx_shared object to free.
400 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
404 mlx5_aso_queue_stop(sh);
405 mlx5_aso_queue_uninit(sh);
406 if (sh->aso_age_mng->pools) {
407 struct mlx5_aso_age_pool *pool;
409 for (i = 0; i < sh->aso_age_mng->next; ++i) {
410 pool = sh->aso_age_mng->pools[i];
411 claim_zero(mlx5_devx_cmd_destroy
412 (pool->flow_hit_aso_obj));
413 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
414 if (pool->actions[j].dr_action)
416 (mlx5_glue->destroy_flow_action
417 (pool->actions[j].dr_action));
420 mlx5_free(sh->aso_age_mng->pools);
422 memset(&sh->aso_age_mng, 0, sizeof(sh->aso_age_mng));
426 * Initialize the shared aging list information per port.
429 * Pointer to mlx5_dev_ctx_shared object.
432 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
435 struct mlx5_age_info *age_info;
437 for (i = 0; i < sh->max_port; i++) {
438 age_info = &sh->port[i].age_info;
440 TAILQ_INIT(&age_info->aged_counters);
441 LIST_INIT(&age_info->aged_aso);
442 rte_spinlock_init(&age_info->aged_sl);
443 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
448 * Initialize the counters management structure.
451 * Pointer to mlx5_dev_ctx_shared object to free
454 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
458 memset(&sh->cmng, 0, sizeof(sh->cmng));
459 TAILQ_INIT(&sh->cmng.flow_counters);
460 sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
461 sh->cmng.max_id = -1;
462 sh->cmng.last_pool_idx = POOL_IDX_INVALID;
463 rte_spinlock_init(&sh->cmng.pool_update_sl);
464 for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
465 TAILQ_INIT(&sh->cmng.counters[i]);
466 rte_spinlock_init(&sh->cmng.csl[i]);
471 * Destroy all the resources allocated for a counter memory management.
474 * Pointer to the memory management structure.
477 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
479 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
481 LIST_REMOVE(mng, next);
482 claim_zero(mlx5_devx_cmd_destroy(mng->dm));
483 claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
488 * Close and release all the resources of the counters management.
491 * Pointer to mlx5_dev_ctx_shared object to free.
494 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
496 struct mlx5_counter_stats_mem_mng *mng;
502 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
503 if (rte_errno != EINPROGRESS)
508 if (sh->cmng.pools) {
509 struct mlx5_flow_counter_pool *pool;
510 uint16_t n_valid = sh->cmng.n_valid;
511 bool fallback = sh->cmng.counter_fallback;
513 for (i = 0; i < n_valid; ++i) {
514 pool = sh->cmng.pools[i];
515 if (!fallback && pool->min_dcs)
516 claim_zero(mlx5_devx_cmd_destroy
518 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
519 struct mlx5_flow_counter *cnt =
520 MLX5_POOL_GET_CNT(pool, j);
524 (mlx5_glue->destroy_flow_action
526 if (fallback && MLX5_POOL_GET_CNT
527 (pool, j)->dcs_when_free)
528 claim_zero(mlx5_devx_cmd_destroy
529 (cnt->dcs_when_free));
533 mlx5_free(sh->cmng.pools);
535 mng = LIST_FIRST(&sh->cmng.mem_mngs);
537 mlx5_flow_destroy_counter_stat_mem_mng(mng);
538 mng = LIST_FIRST(&sh->cmng.mem_mngs);
540 memset(&sh->cmng, 0, sizeof(sh->cmng));
543 /* Send FLOW_AGED event if needed. */
545 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
547 struct mlx5_age_info *age_info;
550 for (i = 0; i < sh->max_port; i++) {
551 age_info = &sh->port[i].age_info;
552 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
554 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER))
555 rte_eth_dev_callback_process
556 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
557 RTE_ETH_EVENT_FLOW_AGED, NULL);
563 * Initialize the flow resources' indexed mempool.
566 * Pointer to mlx5_dev_ctx_shared object.
568 * Pointer to user dev config.
571 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
572 const struct mlx5_dev_config *config)
575 struct mlx5_indexed_pool_config cfg;
577 for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
578 cfg = mlx5_ipool_cfg[i];
583 * Set MLX5_IPOOL_MLX5_FLOW ipool size
584 * according to PCI function flow configuration.
586 case MLX5_IPOOL_MLX5_FLOW:
587 cfg.size = config->dv_flow_en ?
588 sizeof(struct mlx5_flow_handle) :
589 MLX5_FLOW_HANDLE_VERBS_SIZE;
592 if (config->reclaim_mode)
593 cfg.release_mem_en = 1;
594 sh->ipool[i] = mlx5_ipool_create(&cfg);
599 * Release the flow resources' indexed mempool.
602 * Pointer to mlx5_dev_ctx_shared object.
605 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
609 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
610 mlx5_ipool_destroy(sh->ipool[i]);
614 * Check if dynamic flex parser for eCPRI already exists.
617 * Pointer to Ethernet device structure.
620 * true on exists, false on not.
623 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
625 struct mlx5_priv *priv = dev->data->dev_private;
626 struct mlx5_flex_parser_profiles *prf =
627 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
633 * Allocation of a flex parser for eCPRI. Once created, this parser related
634 * resources will be held until the device is closed.
637 * Pointer to Ethernet device structure.
640 * 0 on success, a negative errno value otherwise and rte_errno is set.
643 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
645 struct mlx5_priv *priv = dev->data->dev_private;
646 struct mlx5_flex_parser_profiles *prf =
647 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
648 struct mlx5_devx_graph_node_attr node = {
649 .modify_field_select = 0,
654 if (!priv->config.hca_attr.parse_graph_flex_node) {
655 DRV_LOG(ERR, "Dynamic flex parser is not supported "
656 "for device %s.", priv->dev_data->name);
659 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
660 /* 8 bytes now: 4B common header + 4B message body header. */
661 node.header_length_base_value = 0x8;
662 /* After MAC layer: Ether / VLAN. */
663 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
664 /* Type of compared condition should be 0xAEFE in the L2 layer. */
665 node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
666 /* Sample #0: type in common header. */
667 node.sample[0].flow_match_sample_en = 1;
669 node.sample[0].flow_match_sample_offset_mode = 0x0;
670 /* Only the 2nd byte will be used. */
671 node.sample[0].flow_match_sample_field_base_offset = 0x0;
672 /* Sample #1: message payload. */
673 node.sample[1].flow_match_sample_en = 1;
675 node.sample[1].flow_match_sample_offset_mode = 0x0;
677 * Only the first two bytes will be used right now, and its offset will
678 * start after the common header that with the length of a DW(u32).
680 node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
681 prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
683 DRV_LOG(ERR, "Failed to create flex parser node object.");
684 return (rte_errno == 0) ? -ENODEV : -rte_errno;
687 ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
689 DRV_LOG(ERR, "Failed to query sample IDs.");
690 return (rte_errno == 0) ? -ENODEV : -rte_errno;
692 prf->offset[0] = 0x0;
693 prf->offset[1] = sizeof(uint32_t);
694 prf->ids[0] = ids[0];
695 prf->ids[1] = ids[1];
700 * Destroy the flex parser node, including the parser itself, input / output
701 * arcs and DW samples. Resources could be reused then.
704 * Pointer to Ethernet device structure.
707 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
709 struct mlx5_priv *priv = dev->data->dev_private;
710 struct mlx5_flex_parser_profiles *prf =
711 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
714 mlx5_devx_cmd_destroy(prf->obj);
719 * Allocate Rx and Tx UARs in robust fashion.
720 * This routine handles the following UAR allocation issues:
722 * - tries to allocate the UAR with the most appropriate memory
723 * mapping type from the ones supported by the host
725 * - tries to allocate the UAR with non-NULL base address
726 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
727 * UAR base address if UAR was not the first object in the UAR page.
728 * It caused the PMD failure and we should try to get another UAR
729 * till we get the first one with non-NULL base address returned.
732 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
733 const struct mlx5_dev_config *config)
735 uint32_t uar_mapping, retry;
739 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
740 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
741 /* Control the mapping type according to the settings. */
742 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
743 MLX5DV_UAR_ALLOC_TYPE_NC :
744 MLX5DV_UAR_ALLOC_TYPE_BF;
746 RTE_SET_USED(config);
748 * It seems we have no way to control the memory mapping type
749 * for the UAR, the default "Write-Combining" type is supposed.
750 * The UAR initialization on queue creation queries the
751 * actual mapping type done by Verbs/kernel and setups the
752 * PMD datapath accordingly.
756 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
757 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
759 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
760 if (config->dbnc == MLX5_TXDB_CACHED ||
761 config->dbnc == MLX5_TXDB_HEURISTIC)
762 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
763 "is not supported by DevX");
765 * In some environments like virtual machine
766 * the Write Combining mapped might be not supported
767 * and UAR allocation fails. We try "Non-Cached"
768 * mapping for the case. The tx_burst routines take
769 * the UAR mapping type into account on UAR setup
772 DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (BF)");
773 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
774 sh->tx_uar = mlx5_glue->devx_alloc_uar
775 (sh->ctx, uar_mapping);
776 } else if (!sh->tx_uar &&
777 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
778 if (config->dbnc == MLX5_TXDB_NCACHED)
779 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
780 "is not supported by DevX");
782 * If Verbs/kernel does not support "Non-Cached"
783 * try the "Write-Combining".
785 DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (NC)");
786 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
787 sh->tx_uar = mlx5_glue->devx_alloc_uar
788 (sh->ctx, uar_mapping);
792 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
796 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
800 * The UARs are allocated by rdma_core within the
801 * IB device context, on context closure all UARs
802 * will be freed, should be no memory/object leakage.
804 DRV_LOG(WARNING, "Retrying to allocate Tx DevX UAR");
807 /* Check whether we finally succeeded with valid UAR allocation. */
809 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
813 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
815 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
816 (sh->ctx, uar_mapping);
817 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
818 if (!sh->devx_rx_uar &&
819 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
821 * Rx UAR is used to control interrupts only,
822 * should be no datapath noticeable impact,
823 * can try "Non-Cached" mapping safely.
825 DRV_LOG(WARNING, "Failed to allocate Rx DevX UAR (BF)");
826 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
827 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
828 (sh->ctx, uar_mapping);
831 if (!sh->devx_rx_uar) {
832 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
836 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
840 * The UARs are allocated by rdma_core within the
841 * IB device context, on context closure all UARs
842 * will be freed, should be no memory/object leakage.
844 DRV_LOG(WARNING, "Retrying to allocate Rx DevX UAR");
845 sh->devx_rx_uar = NULL;
847 /* Check whether we finally succeeded with valid UAR allocation. */
848 if (!sh->devx_rx_uar) {
849 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
857 * Allocate shared device context. If there is multiport device the
858 * master and representors will share this context, if there is single
859 * port dedicated device, the context will be used by only given
860 * port due to unification.
862 * Routine first searches the context for the specified device name,
863 * if found the shared context assumed and reference counter is incremented.
864 * If no context found the new one is created and initialized with specified
865 * device context and parameters.
868 * Pointer to the device attributes (name, port, etc).
870 * Pointer to device configuration structure.
873 * Pointer to mlx5_dev_ctx_shared object on success,
874 * otherwise NULL and rte_errno is set.
876 struct mlx5_dev_ctx_shared *
877 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
878 const struct mlx5_dev_config *config)
880 struct mlx5_dev_ctx_shared *sh;
883 struct mlx5_devx_tis_attr tis_attr = { 0 };
886 /* Secondary process should not create the shared context. */
887 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
888 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
889 /* Search for IB context by device name. */
890 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
891 if (!strcmp(sh->ibdev_name,
892 mlx5_os_get_dev_device_name(spawn->phys_dev))) {
897 /* No device found, we have to create new shared context. */
898 MLX5_ASSERT(spawn->max_port);
899 sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
900 sizeof(struct mlx5_dev_ctx_shared) +
902 sizeof(struct mlx5_dev_shared_port),
903 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
905 DRV_LOG(ERR, "shared context allocation failure");
909 err = mlx5_os_open_device(spawn, config, sh);
912 err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
914 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
918 sh->max_port = spawn->max_port;
919 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
920 sizeof(sh->ibdev_name) - 1);
921 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
922 sizeof(sh->ibdev_path) - 1);
924 * Setting port_id to max unallowed value means
925 * there is no interrupt subhandler installed for
926 * the given port index i.
928 for (i = 0; i < sh->max_port; i++) {
929 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
930 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
932 sh->pd = mlx5_glue->alloc_pd(sh->ctx);
933 if (sh->pd == NULL) {
934 DRV_LOG(ERR, "PD allocation failure");
939 /* Query the EQN for this core. */
940 err = mlx5_glue->devx_query_eqn(sh->ctx, 0, &sh->eqn);
943 DRV_LOG(ERR, "Failed to query event queue number %d.",
947 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
949 DRV_LOG(ERR, "Fail to extract pdn from PD");
952 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
954 DRV_LOG(ERR, "TD allocation failure");
958 tis_attr.transport_domain = sh->td->id;
959 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
961 DRV_LOG(ERR, "TIS allocation failure");
965 err = mlx5_alloc_rxtx_uars(sh, config);
968 MLX5_ASSERT(sh->tx_uar);
969 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
971 MLX5_ASSERT(sh->devx_rx_uar);
972 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
975 /* Initialize UAR access locks for 32bit implementations. */
976 rte_spinlock_init(&sh->uar_lock_cq);
977 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
978 rte_spinlock_init(&sh->uar_lock[i]);
981 * Once the device is added to the list of memory event
982 * callback, its global MR cache table cannot be expanded
983 * on the fly because of deadlock. If it overflows, lookup
984 * should be done by searching MR list linearly, which is slow.
986 * At this point the device is not added to the memory
987 * event list yet, context is just being created.
989 err = mlx5_mr_btree_init(&sh->share_cache.cache,
990 MLX5_MR_BTREE_CACHE_N * 2,
991 spawn->pci_dev->device.numa_node);
996 mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
997 &sh->share_cache.dereg_mr_cb);
998 mlx5_os_dev_shared_handler_install(sh);
999 sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
1000 if (!sh->cnt_id_tbl) {
1004 mlx5_flow_aging_init(sh);
1005 mlx5_flow_counters_mng_init(sh);
1006 mlx5_flow_ipool_create(sh, config);
1007 /* Add device to memory callback list. */
1008 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1009 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1011 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1012 /* Add context to the global device list. */
1013 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1015 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1018 pthread_mutex_destroy(&sh->txpp.mutex);
1019 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1022 mlx5_l3t_destroy(sh->cnt_id_tbl);
1024 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1026 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1027 if (sh->devx_rx_uar)
1028 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1030 mlx5_glue->devx_free_uar(sh->tx_uar);
1032 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
1034 claim_zero(mlx5_glue->close_device(sh->ctx));
1036 MLX5_ASSERT(err > 0);
1042 * Free shared IB device context. Decrement counter and if zero free
1043 * all allocated resources and close handles.
1046 * Pointer to mlx5_dev_ctx_shared object to free
1049 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1051 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1052 #ifdef RTE_LIBRTE_MLX5_DEBUG
1053 /* Check the object presence in the list. */
1054 struct mlx5_dev_ctx_shared *lctx;
1056 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1061 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1066 MLX5_ASSERT(sh->refcnt);
1067 /* Secondary process should not free the shared context. */
1068 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1071 /* Remove from memory callback device list. */
1072 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1073 LIST_REMOVE(sh, mem_event_cb);
1074 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1075 /* Release created Memory Regions. */
1076 mlx5_mr_release_cache(&sh->share_cache);
1077 /* Remove context from the global device list. */
1078 LIST_REMOVE(sh, next);
1079 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1081 * Ensure there is no async event handler installed.
1082 * Only primary process handles async device events.
1084 mlx5_flow_counters_mng_close(sh);
1085 if (sh->aso_age_mng) {
1086 mlx5_flow_aso_age_mng_close(sh);
1087 sh->aso_age_mng = NULL;
1089 mlx5_flow_ipool_destroy(sh);
1090 mlx5_os_dev_shared_handler_uninstall(sh);
1091 if (sh->cnt_id_tbl) {
1092 mlx5_l3t_destroy(sh->cnt_id_tbl);
1093 sh->cnt_id_tbl = NULL;
1096 mlx5_glue->devx_free_uar(sh->tx_uar);
1100 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
1102 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1104 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1105 if (sh->devx_rx_uar)
1106 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1108 claim_zero(mlx5_glue->close_device(sh->ctx));
1109 pthread_mutex_destroy(&sh->txpp.mutex);
1113 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1117 * Destroy table hash list.
1120 * Pointer to the private device data structure.
1123 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1125 struct mlx5_dev_ctx_shared *sh = priv->sh;
1129 mlx5_hlist_destroy(sh->flow_tbls);
1133 * Initialize flow table hash list and create the root tables entry
1137 * Pointer to the private device data structure.
1140 * Zero on success, positive error code otherwise.
1143 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1146 /* Tables are only used in DV and DR modes. */
1147 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1148 struct mlx5_dev_ctx_shared *sh = priv->sh;
1149 char s[MLX5_HLIST_NAMESIZE];
1152 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1153 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1154 0, 0, flow_dv_tbl_create_cb, NULL,
1155 flow_dv_tbl_remove_cb);
1156 if (!sh->flow_tbls) {
1157 DRV_LOG(ERR, "flow tables with hash creation failed.");
1161 sh->flow_tbls->ctx = sh;
1162 #ifndef HAVE_MLX5DV_DR
1163 struct rte_flow_error error;
1164 struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1167 * In case we have not DR support, the zero tables should be created
1168 * because DV expect to see them even if they cannot be created by
1171 if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0, NULL, 0, 1, &error) ||
1172 !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0, NULL, 0, 1, &error) ||
1173 !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0, NULL, 0, 1, &error)) {
1179 mlx5_free_table_hash_list(priv);
1180 #endif /* HAVE_MLX5DV_DR */
1186 * Retrieve integer value from environment variable.
1189 * Environment variable name.
1192 * Integer value, 0 if the variable is not set.
1195 mlx5_getenv_int(const char *name)
1197 const char *val = getenv(name);
1205 * DPDK callback to add udp tunnel port
1208 * A pointer to eth_dev
1209 * @param[in] udp_tunnel
1210 * A pointer to udp tunnel
1213 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1216 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1217 struct rte_eth_udp_tunnel *udp_tunnel)
1219 MLX5_ASSERT(udp_tunnel != NULL);
1220 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1221 udp_tunnel->udp_port == 4789)
1223 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1224 udp_tunnel->udp_port == 4790)
1230 * Initialize process private data structure.
1233 * Pointer to Ethernet device structure.
1236 * 0 on success, a negative errno value otherwise and rte_errno is set.
1239 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1241 struct mlx5_priv *priv = dev->data->dev_private;
1242 struct mlx5_proc_priv *ppriv;
1246 * UAR register table follows the process private structure. BlueFlame
1247 * registers for Tx queues are stored in the table.
1250 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1251 ppriv = mlx5_malloc(MLX5_MEM_RTE, ppriv_size, RTE_CACHE_LINE_SIZE,
1252 dev->device->numa_node);
1257 ppriv->uar_table_sz = ppriv_size;
1258 dev->process_private = ppriv;
1263 * Un-initialize process private data structure.
1266 * Pointer to Ethernet device structure.
1269 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1271 if (!dev->process_private)
1273 mlx5_free(dev->process_private);
1274 dev->process_private = NULL;
1278 * DPDK callback to close the device.
1280 * Destroy all queues and objects, free memory.
1283 * Pointer to Ethernet device structure.
1286 mlx5_dev_close(struct rte_eth_dev *dev)
1288 struct mlx5_priv *priv = dev->data->dev_private;
1292 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1293 /* Check if process_private released. */
1294 if (!dev->process_private)
1296 mlx5_tx_uar_uninit_secondary(dev);
1297 mlx5_proc_priv_uninit(dev);
1298 rte_eth_dev_release_port(dev);
1303 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1305 ((priv->sh->ctx != NULL) ?
1306 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1308 * If default mreg copy action is removed at the stop stage,
1309 * the search will return none and nothing will be done anymore.
1311 mlx5_flow_stop_default(dev);
1312 mlx5_traffic_disable(dev);
1314 * If all the flows are already flushed in the device stop stage,
1315 * then this will return directly without any action.
1317 mlx5_flow_list_flush(dev, &priv->flows, true);
1318 mlx5_shared_action_flush(dev);
1319 mlx5_flow_meter_flush(dev, NULL);
1320 /* Prevent crashes when queues are still in use. */
1321 dev->rx_pkt_burst = removed_rx_burst;
1322 dev->tx_pkt_burst = removed_tx_burst;
1324 /* Disable datapath on secondary process. */
1325 mlx5_mp_os_req_stop_rxtx(dev);
1326 /* Free the eCPRI flex parser resource. */
1327 mlx5_flex_parser_ecpri_release(dev);
1328 if (priv->rxqs != NULL) {
1329 /* XXX race condition if mlx5_rx_burst() is still running. */
1331 for (i = 0; (i != priv->rxqs_n); ++i)
1332 mlx5_rxq_release(dev, i);
1336 if (priv->txqs != NULL) {
1337 /* XXX race condition if mlx5_tx_burst() is still running. */
1339 for (i = 0; (i != priv->txqs_n); ++i)
1340 mlx5_txq_release(dev, i);
1344 mlx5_proc_priv_uninit(dev);
1345 if (priv->drop_queue.hrxq)
1346 mlx5_drop_action_destroy(dev);
1347 if (priv->mreg_cp_tbl)
1348 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1349 mlx5_mprq_free_mp(dev);
1350 mlx5_os_free_shared_dr(priv);
1351 if (priv->rss_conf.rss_key != NULL)
1352 mlx5_free(priv->rss_conf.rss_key);
1353 if (priv->reta_idx != NULL)
1354 mlx5_free(priv->reta_idx);
1355 if (priv->config.vf)
1356 mlx5_os_mac_addr_flush(dev);
1357 if (priv->nl_socket_route >= 0)
1358 close(priv->nl_socket_route);
1359 if (priv->nl_socket_rdma >= 0)
1360 close(priv->nl_socket_rdma);
1361 if (priv->vmwa_context)
1362 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1363 ret = mlx5_hrxq_verify(dev);
1365 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1366 dev->data->port_id);
1367 ret = mlx5_ind_table_obj_verify(dev);
1369 DRV_LOG(WARNING, "port %u some indirection table still remain",
1370 dev->data->port_id);
1371 ret = mlx5_rxq_obj_verify(dev);
1373 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1374 dev->data->port_id);
1375 ret = mlx5_rxq_verify(dev);
1377 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1378 dev->data->port_id);
1379 ret = mlx5_txq_obj_verify(dev);
1381 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1382 dev->data->port_id);
1383 ret = mlx5_txq_verify(dev);
1385 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1386 dev->data->port_id);
1387 ret = mlx5_flow_verify(dev);
1389 DRV_LOG(WARNING, "port %u some flows still remain",
1390 dev->data->port_id);
1391 mlx5_cache_list_destroy(&priv->hrxqs);
1393 * Free the shared context in last turn, because the cleanup
1394 * routines above may use some shared fields, like
1395 * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1396 * ifindex if Netlink fails.
1398 mlx5_free_shared_dev_ctx(priv->sh);
1399 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1403 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1404 struct mlx5_priv *opriv =
1405 rte_eth_devices[port_id].data->dev_private;
1408 opriv->domain_id != priv->domain_id ||
1409 &rte_eth_devices[port_id] == dev)
1415 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1417 memset(priv, 0, sizeof(*priv));
1418 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1420 * Reset mac_addrs to NULL such that it is not freed as part of
1421 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1422 * it is freed when dev_private is freed.
1424 dev->data->mac_addrs = NULL;
1429 * Verify and store value for device argument.
1432 * Key argument to verify.
1434 * Value associated with key.
1439 * 0 on success, a negative errno value otherwise and rte_errno is set.
1442 mlx5_args_check(const char *key, const char *val, void *opaque)
1444 struct mlx5_dev_config *config = opaque;
1448 /* No-op, port representors are processed in mlx5_dev_spawn(). */
1449 if (!strcmp(MLX5_REPRESENTOR, key))
1452 tmp = strtol(val, NULL, 0);
1455 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1458 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1459 /* Negative values are acceptable for some keys only. */
1461 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1464 mod = tmp >= 0 ? tmp : -tmp;
1465 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1466 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1467 DRV_LOG(ERR, "invalid CQE compression "
1468 "format parameter");
1472 config->cqe_comp = !!tmp;
1473 config->cqe_comp_fmt = tmp;
1474 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1475 config->cqe_pad = !!tmp;
1476 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1477 config->hw_padding = !!tmp;
1478 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1479 config->mprq.enabled = !!tmp;
1480 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1481 config->mprq.stride_num_n = tmp;
1482 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1483 config->mprq.stride_size_n = tmp;
1484 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1485 config->mprq.max_memcpy_len = tmp;
1486 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1487 config->mprq.min_rxqs_num = tmp;
1488 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1489 DRV_LOG(WARNING, "%s: deprecated parameter,"
1490 " converted to txq_inline_max", key);
1491 config->txq_inline_max = tmp;
1492 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1493 config->txq_inline_max = tmp;
1494 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1495 config->txq_inline_min = tmp;
1496 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1497 config->txq_inline_mpw = tmp;
1498 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1499 config->txqs_inline = tmp;
1500 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1501 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1502 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1503 config->mps = !!tmp;
1504 } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1505 if (tmp != MLX5_TXDB_CACHED &&
1506 tmp != MLX5_TXDB_NCACHED &&
1507 tmp != MLX5_TXDB_HEURISTIC) {
1508 DRV_LOG(ERR, "invalid Tx doorbell "
1509 "mapping parameter");
1514 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1515 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1516 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1517 DRV_LOG(WARNING, "%s: deprecated parameter,"
1518 " converted to txq_inline_mpw", key);
1519 config->txq_inline_mpw = tmp;
1520 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1521 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1522 } else if (strcmp(MLX5_TX_PP, key) == 0) {
1524 DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1528 config->tx_pp = tmp;
1529 } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1530 config->tx_skew = tmp;
1531 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1532 config->rx_vec_en = !!tmp;
1533 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1534 config->l3_vxlan_en = !!tmp;
1535 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1536 config->vf_nl_en = !!tmp;
1537 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1538 config->dv_esw_en = !!tmp;
1539 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1540 config->dv_flow_en = !!tmp;
1541 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1542 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1543 tmp != MLX5_XMETA_MODE_META16 &&
1544 tmp != MLX5_XMETA_MODE_META32 &&
1545 tmp != MLX5_XMETA_MODE_MISS_INFO) {
1546 DRV_LOG(ERR, "invalid extensive "
1547 "metadata parameter");
1551 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
1552 config->dv_xmeta_en = tmp;
1554 config->dv_miss_info = 1;
1555 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1556 config->lacp_by_user = !!tmp;
1557 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1558 config->mr_ext_memseg_en = !!tmp;
1559 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1560 config->max_dump_files_num = tmp;
1561 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1562 config->lro.timeout = tmp;
1563 } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1564 DRV_LOG(DEBUG, "class argument is %s.", val);
1565 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1566 config->log_hp_size = tmp;
1567 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1568 if (tmp != MLX5_RCM_NONE &&
1569 tmp != MLX5_RCM_LIGHT &&
1570 tmp != MLX5_RCM_AGGR) {
1571 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1575 config->reclaim_mode = tmp;
1576 } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1577 config->sys_mem_en = !!tmp;
1578 } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1579 config->decap_en = !!tmp;
1581 DRV_LOG(WARNING, "%s: unknown parameter", key);
1589 * Parse device parameters.
1592 * Pointer to device configuration structure.
1594 * Device arguments structure.
1597 * 0 on success, a negative errno value otherwise and rte_errno is set.
1600 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1602 const char **params = (const char *[]){
1603 MLX5_RXQ_CQE_COMP_EN,
1604 MLX5_RXQ_CQE_PAD_EN,
1605 MLX5_RXQ_PKT_PAD_EN,
1607 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1608 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1609 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1612 MLX5_TXQ_INLINE_MIN,
1613 MLX5_TXQ_INLINE_MAX,
1614 MLX5_TXQ_INLINE_MPW,
1615 MLX5_TXQS_MIN_INLINE,
1618 MLX5_TXQ_MPW_HDR_DSEG_EN,
1619 MLX5_TXQ_MAX_INLINE_LEN,
1631 MLX5_MR_EXT_MEMSEG_EN,
1633 MLX5_MAX_DUMP_FILES_NUM,
1634 MLX5_LRO_TIMEOUT_USEC,
1635 MLX5_CLASS_ARG_NAME,
1642 struct rte_kvargs *kvlist;
1646 if (devargs == NULL)
1648 /* Following UGLY cast is done to pass checkpatch. */
1649 kvlist = rte_kvargs_parse(devargs->args, params);
1650 if (kvlist == NULL) {
1654 /* Process parameters. */
1655 for (i = 0; (params[i] != NULL); ++i) {
1656 if (rte_kvargs_count(kvlist, params[i])) {
1657 ret = rte_kvargs_process(kvlist, params[i],
1658 mlx5_args_check, config);
1661 rte_kvargs_free(kvlist);
1666 rte_kvargs_free(kvlist);
1671 * Configures the minimal amount of data to inline into WQE
1672 * while sending packets.
1674 * - the txq_inline_min has the maximal priority, if this
1675 * key is specified in devargs
1676 * - if DevX is enabled the inline mode is queried from the
1677 * device (HCA attributes and NIC vport context if needed).
1678 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1679 * and none (0 bytes) for other NICs
1682 * Verbs device parameters (name, port, switch_info) to spawn.
1684 * Device configuration parameters.
1687 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1688 struct mlx5_dev_config *config)
1690 if (config->txq_inline_min != MLX5_ARG_UNSET) {
1691 /* Application defines size of inlined data explicitly. */
1692 switch (spawn->pci_dev->id.device_id) {
1693 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1694 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1695 if (config->txq_inline_min <
1696 (int)MLX5_INLINE_HSIZE_L2) {
1698 "txq_inline_mix aligned to minimal"
1699 " ConnectX-4 required value %d",
1700 (int)MLX5_INLINE_HSIZE_L2);
1701 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1707 if (config->hca_attr.eth_net_offloads) {
1708 /* We have DevX enabled, inline mode queried successfully. */
1709 switch (config->hca_attr.wqe_inline_mode) {
1710 case MLX5_CAP_INLINE_MODE_L2:
1711 /* outer L2 header must be inlined. */
1712 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1714 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1715 /* No inline data are required by NIC. */
1716 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1717 config->hw_vlan_insert =
1718 config->hca_attr.wqe_vlan_insert;
1719 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1721 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1722 /* inline mode is defined by NIC vport context. */
1723 if (!config->hca_attr.eth_virt)
1725 switch (config->hca_attr.vport_inline_mode) {
1726 case MLX5_INLINE_MODE_NONE:
1727 config->txq_inline_min =
1728 MLX5_INLINE_HSIZE_NONE;
1730 case MLX5_INLINE_MODE_L2:
1731 config->txq_inline_min =
1732 MLX5_INLINE_HSIZE_L2;
1734 case MLX5_INLINE_MODE_IP:
1735 config->txq_inline_min =
1736 MLX5_INLINE_HSIZE_L3;
1738 case MLX5_INLINE_MODE_TCP_UDP:
1739 config->txq_inline_min =
1740 MLX5_INLINE_HSIZE_L4;
1742 case MLX5_INLINE_MODE_INNER_L2:
1743 config->txq_inline_min =
1744 MLX5_INLINE_HSIZE_INNER_L2;
1746 case MLX5_INLINE_MODE_INNER_IP:
1747 config->txq_inline_min =
1748 MLX5_INLINE_HSIZE_INNER_L3;
1750 case MLX5_INLINE_MODE_INNER_TCP_UDP:
1751 config->txq_inline_min =
1752 MLX5_INLINE_HSIZE_INNER_L4;
1758 * We get here if we are unable to deduce
1759 * inline data size with DevX. Try PCI ID
1760 * to determine old NICs.
1762 switch (spawn->pci_dev->id.device_id) {
1763 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1764 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1765 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1766 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1767 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1768 config->hw_vlan_insert = 0;
1770 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1771 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1772 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1773 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1775 * These NICs support VLAN insertion from WQE and
1776 * report the wqe_vlan_insert flag. But there is the bug
1777 * and PFC control may be broken, so disable feature.
1779 config->hw_vlan_insert = 0;
1780 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1783 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1787 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1791 * Configures the metadata mask fields in the shared context.
1794 * Pointer to Ethernet device.
1797 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1799 struct mlx5_priv *priv = dev->data->dev_private;
1800 struct mlx5_dev_ctx_shared *sh = priv->sh;
1801 uint32_t meta, mark, reg_c0;
1803 reg_c0 = ~priv->vport_meta_mask;
1804 switch (priv->config.dv_xmeta_en) {
1805 case MLX5_XMETA_MODE_LEGACY:
1807 mark = MLX5_FLOW_MARK_MASK;
1809 case MLX5_XMETA_MODE_META16:
1810 meta = reg_c0 >> rte_bsf32(reg_c0);
1811 mark = MLX5_FLOW_MARK_MASK;
1813 case MLX5_XMETA_MODE_META32:
1815 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1823 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1824 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1825 sh->dv_mark_mask, mark);
1827 sh->dv_mark_mask = mark;
1828 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1829 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1830 sh->dv_meta_mask, meta);
1832 sh->dv_meta_mask = meta;
1833 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1834 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1835 sh->dv_meta_mask, reg_c0);
1837 sh->dv_regc0_mask = reg_c0;
1838 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1839 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1840 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1841 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1845 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1847 static const char *const dynf_names[] = {
1848 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1849 RTE_MBUF_DYNFLAG_METADATA_NAME,
1850 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
1854 if (n < RTE_DIM(dynf_names))
1856 for (i = 0; i < RTE_DIM(dynf_names); i++) {
1857 if (names[i] == NULL)
1859 strcpy(names[i], dynf_names[i]);
1861 return RTE_DIM(dynf_names);
1865 * Comparison callback to sort device data.
1867 * This is meant to be used with qsort().
1870 * Pointer to pointer to first data object.
1872 * Pointer to pointer to second data object.
1875 * 0 if both objects are equal, less than 0 if the first argument is less
1876 * than the second, greater than 0 otherwise.
1879 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1880 struct mlx5_dev_config *config)
1882 struct mlx5_dev_ctx_shared *sh = priv->sh;
1883 struct mlx5_dev_config *sh_conf = NULL;
1887 /* Nothing to compare for the single/first device. */
1888 if (sh->refcnt == 1)
1890 /* Find the device with shared context. */
1891 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1892 struct mlx5_priv *opriv =
1893 rte_eth_devices[port_id].data->dev_private;
1895 if (opriv && opriv != priv && opriv->sh == sh) {
1896 sh_conf = &opriv->config;
1902 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1903 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1904 " for shared %s context", sh->ibdev_name);
1908 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1909 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1910 " for shared %s context", sh->ibdev_name);
1918 * Look for the ethernet device belonging to mlx5 driver.
1920 * @param[in] port_id
1921 * port_id to start looking for device.
1922 * @param[in] pci_dev
1923 * Pointer to the hint PCI device. When device is being probed
1924 * the its siblings (master and preceding representors might
1925 * not have assigned driver yet (because the mlx5_os_pci_probe()
1926 * is not completed yet, for this case match on hint PCI
1927 * device may be used to detect sibling device.
1930 * port_id of found device, RTE_MAX_ETHPORT if not found.
1933 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
1935 while (port_id < RTE_MAX_ETHPORTS) {
1936 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
1938 if (dev->state != RTE_ETH_DEV_UNUSED &&
1940 (dev->device == &pci_dev->device ||
1941 (dev->device->driver &&
1942 dev->device->driver->name &&
1943 !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
1947 if (port_id >= RTE_MAX_ETHPORTS)
1948 return RTE_MAX_ETHPORTS;
1953 * DPDK callback to remove a PCI device.
1955 * This function removes all Ethernet devices belong to a given PCI device.
1957 * @param[in] pci_dev
1958 * Pointer to the PCI device.
1961 * 0 on success, the function cannot fail.
1964 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1969 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
1971 * mlx5_dev_close() is not registered to secondary process,
1972 * call the close function explicitly for secondary process.
1974 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
1975 ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
1977 ret |= rte_eth_dev_close(port_id);
1979 return ret == 0 ? 0 : -EIO;
1982 static const struct rte_pci_id mlx5_pci_id_map[] = {
1984 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1985 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1988 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1989 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1992 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1993 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1996 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1997 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2000 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2001 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2004 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2005 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2008 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2009 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2012 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2013 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2016 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2017 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2020 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2021 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2024 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2025 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2028 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2029 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2032 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2033 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2036 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2037 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
2040 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2041 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2044 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2045 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2048 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2049 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2052 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2053 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2060 static struct mlx5_pci_driver mlx5_driver = {
2061 .driver_class = MLX5_CLASS_NET,
2064 .name = MLX5_DRIVER_NAME,
2066 .id_table = mlx5_pci_id_map,
2067 .probe = mlx5_os_pci_probe,
2068 .remove = mlx5_pci_remove,
2069 .dma_map = mlx5_dma_map,
2070 .dma_unmap = mlx5_dma_unmap,
2071 .drv_flags = PCI_DRV_FLAGS,
2075 /* Initialize driver log type. */
2076 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
2079 * Driver initialization routine.
2081 RTE_INIT(rte_mlx5_pmd_init)
2084 /* Build the static tables for Verbs conversion. */
2085 mlx5_set_ptype_table();
2086 mlx5_set_cksum_table();
2087 mlx5_set_swp_types_table();
2089 mlx5_pci_driver_register(&mlx5_driver);
2092 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2093 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2094 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");