drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12 #include <net/if.h>
  13 #include <sys/mman.h>
  14 #include <linux/rtnetlink.h>
  15
  16 /* Verbs header. */
  17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  18 #ifdef PEDANTIC
  19 #pragma GCC diagnostic ignored "-Wpedantic"
  20 #endif
  21 #include <infiniband/verbs.h>
  22 #ifdef PEDANTIC
  23 #pragma GCC diagnostic error "-Wpedantic"
  24 #endif
  25
  26 #include <rte_malloc.h>
  27 #include <rte_ethdev_driver.h>
  28 #include <rte_ethdev_pci.h>
  29 #include <rte_pci.h>
  30 #include <rte_bus_pci.h>
  31 #include <rte_common.h>
  32 #include <rte_kvargs.h>
  33 #include <rte_rwlock.h>
  34 #include <rte_spinlock.h>
  35 #include <rte_string_fns.h>
  36 #include <rte_alarm.h>
  37
  38 #include <mlx5_glue.h>
  39 #include <mlx5_devx_cmds.h>
  40 #include <mlx5_common.h>
  41 #include <mlx5_common_mp.h>
  42
  43 #include "mlx5_defs.h"
  44 #include "mlx5.h"
  45 #include "mlx5_utils.h"
  46 #include "mlx5_rxtx.h"
  47 #include "mlx5_autoconf.h"
  48 #include "mlx5_mr.h"
  49 #include "mlx5_flow.h"
  50 #include "rte_pmd_mlx5.h"
  51
  52 /* Device parameter to enable RX completion queue compression. */
  53 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  54
  55 /* Device parameter to enable RX completion entry padding to 128B. */
  56 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
  57
  58 /* Device parameter to enable padding Rx packet to cacheline size. */
  59 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  60
  61 /* Device parameter to enable Multi-Packet Rx queue. */
  62 #define MLX5_RX_MPRQ_EN "mprq_en"
  63
  64 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  65 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  66
  67 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  68 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  69
  70 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  71 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  72
  73 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  74 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  75
  76 /* Device parameter to configure inline send. Deprecated, ignored.*/
  77 #define MLX5_TXQ_INLINE "txq_inline"
  78
  79 /* Device parameter to limit packet size to inline with ordinary SEND. */
  80 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  81
  82 /* Device parameter to configure minimal data size to inline. */
  83 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  84
  85 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  86 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  87
  88 /*
  89  * Device parameter to configure the number of TX queues threshold for
  90  * enabling inline send.
  91  */
  92 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  93
  94 /*
  95  * Device parameter to configure the number of TX queues threshold for
  96  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  97  */
  98 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  99
 100 /* Device parameter to enable multi-packet send WQEs. */
 101 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
 102
 103 /*
 104  * Device parameter to force doorbell register mapping
 105  * to non-cahed region eliminating the extra write memory barrier.
 106  */
 107 #define MLX5_TX_DB_NC "tx_db_nc"
 108
 109 /*
 110  * Device parameter to include 2 dsegs in the title WQEBB.
 111  * Deprecated, ignored.
 112  */
 113 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 114
 115 /*
 116  * Device parameter to limit the size of inlining packet.
 117  * Deprecated, ignored.
 118  */
 119 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 120
 121 /*
 122  * Device parameter to enable hardware Tx vector.
 123  * Deprecated, ignored (no vectorized Tx routines anymore).
 124  */
 125 #define MLX5_TX_VEC_EN "tx_vec_en"
 126
 127 /* Device parameter to enable hardware Rx vector. */
 128 #define MLX5_RX_VEC_EN "rx_vec_en"
 129
 130 /* Allow L3 VXLAN flow creation. */
 131 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 132
 133 /* Activate DV E-Switch flow steering. */
 134 #define MLX5_DV_ESW_EN "dv_esw_en"
 135
 136 /* Activate DV flow steering. */
 137 #define MLX5_DV_FLOW_EN "dv_flow_en"
 138
 139 /* Enable extensive flow metadata support. */
 140 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 141
 142 /* Activate Netlink support in VF mode. */
 143 #define MLX5_VF_NL_EN "vf_nl_en"
 144
 145 /* Enable extending memsegs when creating a MR. */
 146 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 147
 148 /* Select port representors to instantiate. */
 149 #define MLX5_REPRESENTOR "representor"
 150
 151 /* Device parameter to configure the maximum number of dump files per queue. */
 152 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 153
 154 /* Configure timeout of LRO session (in microseconds). */
 155 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 156
 157 /*
 158  * Device parameter to configure the total data buffer size for a single
 159  * hairpin queue (logarithm value).
 160  */
 161 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 162
 163 /* Flow memory reclaim mode. */
 164 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 165
 166 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
 167
 168 /* Shared memory between primary and secondary processes. */
 169 struct mlx5_shared_data *mlx5_shared_data;
 170
 171 /* Spinlock for mlx5_shared_data allocation. */
 172 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
 173
 174 /* Process local data for secondary processes. */
 175 static struct mlx5_local_data mlx5_local_data;
 176 /** Driver-specific log messages type. */
 177 int mlx5_logtype;
 178
 179 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 180                                                 LIST_HEAD_INITIALIZER();
 181 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
 182
 183 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 184 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 185         {
 186                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 187                 .trunk_size = 64,
 188                 .grow_trunk = 3,
 189                 .grow_shift = 2,
 190                 .need_lock = 0,
 191                 .release_mem_en = 1,
 192                 .malloc = rte_malloc_socket,
 193                 .free = rte_free,
 194                 .type = "mlx5_encap_decap_ipool",
 195         },
 196         {
 197                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 198                 .trunk_size = 64,
 199                 .grow_trunk = 3,
 200                 .grow_shift = 2,
 201                 .need_lock = 0,
 202                 .release_mem_en = 1,
 203                 .malloc = rte_malloc_socket,
 204                 .free = rte_free,
 205                 .type = "mlx5_push_vlan_ipool",
 206         },
 207         {
 208                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 209                 .trunk_size = 64,
 210                 .grow_trunk = 3,
 211                 .grow_shift = 2,
 212                 .need_lock = 0,
 213                 .release_mem_en = 1,
 214                 .malloc = rte_malloc_socket,
 215                 .free = rte_free,
 216                 .type = "mlx5_tag_ipool",
 217         },
 218         {
 219                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 220                 .trunk_size = 64,
 221                 .grow_trunk = 3,
 222                 .grow_shift = 2,
 223                 .need_lock = 0,
 224                 .release_mem_en = 1,
 225                 .malloc = rte_malloc_socket,
 226                 .free = rte_free,
 227                 .type = "mlx5_port_id_ipool",
 228         },
 229         {
 230                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 231                 .trunk_size = 64,
 232                 .grow_trunk = 3,
 233                 .grow_shift = 2,
 234                 .need_lock = 0,
 235                 .release_mem_en = 1,
 236                 .malloc = rte_malloc_socket,
 237                 .free = rte_free,
 238                 .type = "mlx5_jump_ipool",
 239         },
 240 #endif
 241         {
 242                 .size = sizeof(struct mlx5_flow_meter),
 243                 .trunk_size = 64,
 244                 .grow_trunk = 3,
 245                 .grow_shift = 2,
 246                 .need_lock = 0,
 247                 .release_mem_en = 1,
 248                 .malloc = rte_malloc_socket,
 249                 .free = rte_free,
 250                 .type = "mlx5_meter_ipool",
 251         },
 252         {
 253                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 254                 .trunk_size = 64,
 255                 .grow_trunk = 3,
 256                 .grow_shift = 2,
 257                 .need_lock = 0,
 258                 .release_mem_en = 1,
 259                 .malloc = rte_malloc_socket,
 260                 .free = rte_free,
 261                 .type = "mlx5_mcp_ipool",
 262         },
 263         {
 264                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 265                 .trunk_size = 64,
 266                 .grow_trunk = 3,
 267                 .grow_shift = 2,
 268                 .need_lock = 0,
 269                 .release_mem_en = 1,
 270                 .malloc = rte_malloc_socket,
 271                 .free = rte_free,
 272                 .type = "mlx5_hrxq_ipool",
 273         },
 274         {
 275                 /*
 276                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 277                  * It set in run time according to PCI function configuration.
 278                  */
 279                 .size = 0,
 280                 .trunk_size = 64,
 281                 .grow_trunk = 3,
 282                 .grow_shift = 2,
 283                 .need_lock = 0,
 284                 .release_mem_en = 1,
 285                 .malloc = rte_malloc_socket,
 286                 .free = rte_free,
 287                 .type = "mlx5_flow_handle_ipool",
 288         },
 289         {
 290                 .size = sizeof(struct rte_flow),
 291                 .trunk_size = 4096,
 292                 .need_lock = 1,
 293                 .release_mem_en = 1,
 294                 .malloc = rte_malloc_socket,
 295                 .free = rte_free,
 296                 .type = "rte_flow_ipool",
 297         },
 298 };
 299
 300
 301 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 302 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 303
 304 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 305
 306 /**
 307  * Allocate ID pool structure.
 308  *
 309  * @param[in] max_id
 310  *   The maximum id can be allocated from the pool.
 311  *
 312  * @return
 313  *   Pointer to pool object, NULL value otherwise.
 314  */
 315 struct mlx5_flow_id_pool *
 316 mlx5_flow_id_pool_alloc(uint32_t max_id)
 317 {
 318         struct mlx5_flow_id_pool *pool;
 319         void *mem;
 320
 321         pool = rte_zmalloc("id pool allocation", sizeof(*pool),
 322                            RTE_CACHE_LINE_SIZE);
 323         if (!pool) {
 324                 DRV_LOG(ERR, "can't allocate id pool");
 325                 rte_errno  = ENOMEM;
 326                 return NULL;
 327         }
 328         mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
 329                           RTE_CACHE_LINE_SIZE);
 330         if (!mem) {
 331                 DRV_LOG(ERR, "can't allocate mem for id pool");
 332                 rte_errno  = ENOMEM;
 333                 goto error;
 334         }
 335         pool->free_arr = mem;
 336         pool->curr = pool->free_arr;
 337         pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
 338         pool->base_index = 0;
 339         pool->max_id = max_id;
 340         return pool;
 341 error:
 342         rte_free(pool);
 343         return NULL;
 344 }
 345
 346 /**
 347  * Release ID pool structure.
 348  *
 349  * @param[in] pool
 350  *   Pointer to flow id pool object to free.
 351  */
 352 void
 353 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
 354 {
 355         rte_free(pool->free_arr);
 356         rte_free(pool);
 357 }
 358
 359 /**
 360  * Generate ID.
 361  *
 362  * @param[in] pool
 363  *   Pointer to flow id pool.
 364  * @param[out] id
 365  *   The generated ID.
 366  *
 367  * @return
 368  *   0 on success, error value otherwise.
 369  */
 370 uint32_t
 371 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
 372 {
 373         if (pool->curr == pool->free_arr) {
 374                 if (pool->base_index == pool->max_id) {
 375                         rte_errno  = ENOMEM;
 376                         DRV_LOG(ERR, "no free id");
 377                         return -rte_errno;
 378                 }
 379                 *id = ++pool->base_index;
 380                 return 0;
 381         }
 382         *id = *(--pool->curr);
 383         return 0;
 384 }
 385
 386 /**
 387  * Release ID.
 388  *
 389  * @param[in] pool
 390  *   Pointer to flow id pool.
 391  * @param[out] id
 392  *   The generated ID.
 393  *
 394  * @return
 395  *   0 on success, error value otherwise.
 396  */
 397 uint32_t
 398 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
 399 {
 400         uint32_t size;
 401         uint32_t size2;
 402         void *mem;
 403
 404         if (pool->curr == pool->last) {
 405                 size = pool->curr - pool->free_arr;
 406                 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
 407                 MLX5_ASSERT(size2 > size);
 408                 mem = rte_malloc("", size2 * sizeof(uint32_t), 0);
 409                 if (!mem) {
 410                         DRV_LOG(ERR, "can't allocate mem for id pool");
 411                         rte_errno  = ENOMEM;
 412                         return -rte_errno;
 413                 }
 414                 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
 415                 rte_free(pool->free_arr);
 416                 pool->free_arr = mem;
 417                 pool->curr = pool->free_arr + size;
 418                 pool->last = pool->free_arr + size2;
 419         }
 420         *pool->curr = id;
 421         pool->curr++;
 422         return 0;
 423 }
 424
 425 /**
 426  * Initialize the shared aging list information per port.
 427  *
 428  * @param[in] sh
 429  *   Pointer to mlx5_dev_ctx_shared object.
 430  */
 431 static void
 432 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 433 {
 434         uint32_t i;
 435         struct mlx5_age_info *age_info;
 436
 437         for (i = 0; i < sh->max_port; i++) {
 438                 age_info = &sh->port[i].age_info;
 439                 age_info->flags = 0;
 440                 TAILQ_INIT(&age_info->aged_counters);
 441                 rte_spinlock_init(&age_info->aged_sl);
 442                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 443         }
 444 }
 445
 446 /**
 447  * Initialize the counters management structure.
 448  *
 449  * @param[in] sh
 450  *   Pointer to mlx5_dev_ctx_shared object to free
 451  */
 452 static void
 453 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 454 {
 455         int i;
 456
 457         memset(&sh->cmng, 0, sizeof(sh->cmng));
 458         TAILQ_INIT(&sh->cmng.flow_counters);
 459         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 460                 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
 461                 rte_spinlock_init(&sh->cmng.ccont[i].resize_sl);
 462         }
 463 }
 464
 465 /**
 466  * Destroy all the resources allocated for a counter memory management.
 467  *
 468  * @param[in] mng
 469  *   Pointer to the memory management structure.
 470  */
 471 static void
 472 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 473 {
 474         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 475
 476         LIST_REMOVE(mng, next);
 477         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 478         claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
 479         rte_free(mem);
 480 }
 481
 482 /**
 483  * Close and release all the resources of the counters management.
 484  *
 485  * @param[in] sh
 486  *   Pointer to mlx5_dev_ctx_shared object to free.
 487  */
 488 static void
 489 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 490 {
 491         struct mlx5_counter_stats_mem_mng *mng;
 492         int i;
 493         int j;
 494         int retries = 1024;
 495
 496         rte_errno = 0;
 497         while (--retries) {
 498                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 499                 if (rte_errno != EINPROGRESS)
 500                         break;
 501                 rte_pause();
 502         }
 503         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 504                 struct mlx5_flow_counter_pool *pool;
 505                 uint32_t batch = !!(i > 1);
 506
 507                 if (!sh->cmng.ccont[i].pools)
 508                         continue;
 509                 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 510                 while (pool) {
 511                         if (batch && pool->min_dcs)
 512                                 claim_zero(mlx5_devx_cmd_destroy
 513                                                                (pool->min_dcs));
 514                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 515                                 if (MLX5_POOL_GET_CNT(pool, j)->action)
 516                                         claim_zero
 517                                          (mlx5_glue->destroy_flow_action
 518                                           (MLX5_POOL_GET_CNT
 519                                           (pool, j)->action));
 520                                 if (!batch && MLX5_GET_POOL_CNT_EXT
 521                                     (pool, j)->dcs)
 522                                         claim_zero(mlx5_devx_cmd_destroy
 523                                                    (MLX5_GET_POOL_CNT_EXT
 524                                                     (pool, j)->dcs));
 525                         }
 526                         TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, next);
 527                         rte_free(pool);
 528                         pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 529                 }
 530                 rte_free(sh->cmng.ccont[i].pools);
 531         }
 532         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 533         while (mng) {
 534                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 535                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 536         }
 537         memset(&sh->cmng, 0, sizeof(sh->cmng));
 538 }
 539
 540 /**
 541  * Initialize the flow resources' indexed mempool.
 542  *
 543  * @param[in] sh
 544  *   Pointer to mlx5_dev_ctx_shared object.
 545  * @param[in] sh
 546  *   Pointer to user dev config.
 547  */
 548 static void
 549 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 550                        const struct mlx5_dev_config *config)
 551 {
 552         uint8_t i;
 553         struct mlx5_indexed_pool_config cfg;
 554
 555         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 556                 cfg = mlx5_ipool_cfg[i];
 557                 switch (i) {
 558                 default:
 559                         break;
 560                 /*
 561                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 562                  * according to PCI function flow configuration.
 563                  */
 564                 case MLX5_IPOOL_MLX5_FLOW:
 565                         cfg.size = config->dv_flow_en ?
 566                                 sizeof(struct mlx5_flow_handle) :
 567                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 568                         break;
 569                 }
 570                 if (config->reclaim_mode)
 571                         cfg.release_mem_en = 1;
 572                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 573         }
 574 }
 575
 576 /**
 577  * Release the flow resources' indexed mempool.
 578  *
 579  * @param[in] sh
 580  *   Pointer to mlx5_dev_ctx_shared object.
 581  */
 582 static void
 583 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 584 {
 585         uint8_t i;
 586
 587         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 588                 mlx5_ipool_destroy(sh->ipool[i]);
 589 }
 590
 591 /**
 592  * Allocate shared device context. If there is multiport device the
 593  * master and representors will share this context, if there is single
 594  * port dedicated device, the context will be used by only given
 595  * port due to unification.
 596  *
 597  * Routine first searches the context for the specified device name,
 598  * if found the shared context assumed and reference counter is incremented.
 599  * If no context found the new one is created and initialized with specified
 600  * device context and parameters.
 601  *
 602  * @param[in] spawn
 603  *   Pointer to the device attributes (name, port, etc).
 604  * @param[in] config
 605  *   Pointer to device configuration structure.
 606  *
 607  * @return
 608  *   Pointer to mlx5_dev_ctx_shared object on success,
 609  *   otherwise NULL and rte_errno is set.
 610  */
 611 struct mlx5_dev_ctx_shared *
 612 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
 613                            const struct mlx5_dev_config *config)
 614 {
 615         struct mlx5_dev_ctx_shared *sh;
 616         int err = 0;
 617         uint32_t i;
 618         struct mlx5_devx_tis_attr tis_attr = { 0 };
 619
 620         MLX5_ASSERT(spawn);
 621         /* Secondary process should not create the shared context. */
 622         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 623         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 624         /* Search for IB context by device name. */
 625         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
 626                 if (!strcmp(sh->ibdev_name,
 627                         mlx5_os_get_dev_device_name(spawn->phys_dev))) {
 628                         sh->refcnt++;
 629                         goto exit;
 630                 }
 631         }
 632         /* No device found, we have to create new shared context. */
 633         MLX5_ASSERT(spawn->max_port);
 634         sh = rte_zmalloc("ethdev shared ib context",
 635                          sizeof(struct mlx5_dev_ctx_shared) +
 636                          spawn->max_port *
 637                          sizeof(struct mlx5_dev_shared_port),
 638                          RTE_CACHE_LINE_SIZE);
 639         if (!sh) {
 640                 DRV_LOG(ERR, "shared context allocation failure");
 641                 rte_errno  = ENOMEM;
 642                 goto exit;
 643         }
 644         err = mlx5_os_open_device(spawn, config, sh);
 645         if (!sh->ctx)
 646                 goto error;
 647         err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
 648         if (err) {
 649                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
 650                 goto error;
 651         }
 652         sh->refcnt = 1;
 653         sh->max_port = spawn->max_port;
 654         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
 655                 sizeof(sh->ibdev_name) - 1);
 656         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
 657                 sizeof(sh->ibdev_path) - 1);
 658         /*
 659          * Setting port_id to max unallowed value means
 660          * there is no interrupt subhandler installed for
 661          * the given port index i.
 662          */
 663         for (i = 0; i < sh->max_port; i++) {
 664                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 665                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
 666         }
 667         sh->pd = mlx5_glue->alloc_pd(sh->ctx);
 668         if (sh->pd == NULL) {
 669                 DRV_LOG(ERR, "PD allocation failure");
 670                 err = ENOMEM;
 671                 goto error;
 672         }
 673         if (sh->devx) {
 674                 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
 675                 if (err) {
 676                         DRV_LOG(ERR, "Fail to extract pdn from PD");
 677                         goto error;
 678                 }
 679                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
 680                 if (!sh->td) {
 681                         DRV_LOG(ERR, "TD allocation failure");
 682                         err = ENOMEM;
 683                         goto error;
 684                 }
 685                 tis_attr.transport_domain = sh->td->id;
 686                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
 687                 if (!sh->tis) {
 688                         DRV_LOG(ERR, "TIS allocation failure");
 689                         err = ENOMEM;
 690                         goto error;
 691                 }
 692         }
 693         sh->flow_id_pool = mlx5_flow_id_pool_alloc
 694                                         ((1 << HAIRPIN_FLOW_ID_BITS) - 1);
 695         if (!sh->flow_id_pool) {
 696                 DRV_LOG(ERR, "can't create flow id pool");
 697                 err = ENOMEM;
 698                 goto error;
 699         }
 700         /*
 701          * Once the device is added to the list of memory event
 702          * callback, its global MR cache table cannot be expanded
 703          * on the fly because of deadlock. If it overflows, lookup
 704          * should be done by searching MR list linearly, which is slow.
 705          *
 706          * At this point the device is not added to the memory
 707          * event list yet, context is just being created.
 708          */
 709         err = mlx5_mr_btree_init(&sh->share_cache.cache,
 710                                  MLX5_MR_BTREE_CACHE_N * 2,
 711                                  spawn->pci_dev->device.numa_node);
 712         if (err) {
 713                 err = rte_errno;
 714                 goto error;
 715         }
 716         mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
 717                               &sh->share_cache.dereg_mr_cb);
 718         mlx5_os_dev_shared_handler_install(sh);
 719         mlx5_flow_aging_init(sh);
 720         mlx5_flow_counters_mng_init(sh);
 721         mlx5_flow_ipool_create(sh, config);
 722         /* Add device to memory callback list. */
 723         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 724         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
 725                          sh, mem_event_cb);
 726         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 727         /* Add context to the global device list. */
 728         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
 729 exit:
 730         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 731         return sh;
 732 error:
 733         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 734         MLX5_ASSERT(sh);
 735         if (sh->tis)
 736                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 737         if (sh->td)
 738                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 739         if (sh->pd)
 740                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 741         if (sh->ctx)
 742                 claim_zero(mlx5_glue->close_device(sh->ctx));
 743         if (sh->flow_id_pool)
 744                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 745         rte_free(sh);
 746         MLX5_ASSERT(err > 0);
 747         rte_errno = err;
 748         return NULL;
 749 }
 750
 751 /**
 752  * Free shared IB device context. Decrement counter and if zero free
 753  * all allocated resources and close handles.
 754  *
 755  * @param[in] sh
 756  *   Pointer to mlx5_dev_ctx_shared object to free
 757  */
 758 void
 759 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
 760 {
 761         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 762 #ifdef RTE_LIBRTE_MLX5_DEBUG
 763         /* Check the object presence in the list. */
 764         struct mlx5_dev_ctx_shared *lctx;
 765
 766         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
 767                 if (lctx == sh)
 768                         break;
 769         MLX5_ASSERT(lctx);
 770         if (lctx != sh) {
 771                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
 772                 goto exit;
 773         }
 774 #endif
 775         MLX5_ASSERT(sh);
 776         MLX5_ASSERT(sh->refcnt);
 777         /* Secondary process should not free the shared context. */
 778         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 779         if (--sh->refcnt)
 780                 goto exit;
 781         /* Remove from memory callback device list. */
 782         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 783         LIST_REMOVE(sh, mem_event_cb);
 784         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 785         /* Release created Memory Regions. */
 786         mlx5_mr_release_cache(&sh->share_cache);
 787         /* Remove context from the global device list. */
 788         LIST_REMOVE(sh, next);
 789         /*
 790          *  Ensure there is no async event handler installed.
 791          *  Only primary process handles async device events.
 792          **/
 793         mlx5_flow_counters_mng_close(sh);
 794         mlx5_flow_ipool_destroy(sh);
 795         mlx5_os_dev_shared_handler_uninstall(sh);
 796         if (sh->pd)
 797                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 798         if (sh->tis)
 799                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 800         if (sh->td)
 801                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 802         if (sh->ctx)
 803                 claim_zero(mlx5_glue->close_device(sh->ctx));
 804         if (sh->flow_id_pool)
 805                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 806         rte_free(sh);
 807 exit:
 808         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 809 }
 810
 811 /**
 812  * Destroy table hash list and all the root entries per domain.
 813  *
 814  * @param[in] priv
 815  *   Pointer to the private device data structure.
 816  */
 817 void
 818 mlx5_free_table_hash_list(struct mlx5_priv *priv)
 819 {
 820         struct mlx5_dev_ctx_shared *sh = priv->sh;
 821         struct mlx5_flow_tbl_data_entry *tbl_data;
 822         union mlx5_flow_tbl_key table_key = {
 823                 {
 824                         .table_id = 0,
 825                         .reserved = 0,
 826                         .domain = 0,
 827                         .direction = 0,
 828                 }
 829         };
 830         struct mlx5_hlist_entry *pos;
 831
 832         if (!sh->flow_tbls)
 833                 return;
 834         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 835         if (pos) {
 836                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 837                                         entry);
 838                 MLX5_ASSERT(tbl_data);
 839                 mlx5_hlist_remove(sh->flow_tbls, pos);
 840                 rte_free(tbl_data);
 841         }
 842         table_key.direction = 1;
 843         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 844         if (pos) {
 845                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 846                                         entry);
 847                 MLX5_ASSERT(tbl_data);
 848                 mlx5_hlist_remove(sh->flow_tbls, pos);
 849                 rte_free(tbl_data);
 850         }
 851         table_key.direction = 0;
 852         table_key.domain = 1;
 853         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 854         if (pos) {
 855                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 856                                         entry);
 857                 MLX5_ASSERT(tbl_data);
 858                 mlx5_hlist_remove(sh->flow_tbls, pos);
 859                 rte_free(tbl_data);
 860         }
 861         mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
 862 }
 863
 864 /**
 865  * Initialize flow table hash list and create the root tables entry
 866  * for each domain.
 867  *
 868  * @param[in] priv
 869  *   Pointer to the private device data structure.
 870  *
 871  * @return
 872  *   Zero on success, positive error code otherwise.
 873  */
 874 int
 875 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
 876 {
 877         struct mlx5_dev_ctx_shared *sh = priv->sh;
 878         char s[MLX5_HLIST_NAMESIZE];
 879         int err = 0;
 880
 881         MLX5_ASSERT(sh);
 882         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
 883         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
 884         if (!sh->flow_tbls) {
 885                 DRV_LOG(ERR, "flow tables with hash creation failed.\n");
 886                 err = ENOMEM;
 887                 return err;
 888         }
 889 #ifndef HAVE_MLX5DV_DR
 890         /*
 891          * In case we have not DR support, the zero tables should be created
 892          * because DV expect to see them even if they cannot be created by
 893          * RDMA-CORE.
 894          */
 895         union mlx5_flow_tbl_key table_key = {
 896                 {
 897                         .table_id = 0,
 898                         .reserved = 0,
 899                         .domain = 0,
 900                         .direction = 0,
 901                 }
 902         };
 903         struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL,
 904                                                           sizeof(*tbl_data), 0);
 905
 906         if (!tbl_data) {
 907                 err = ENOMEM;
 908                 goto error;
 909         }
 910         tbl_data->entry.key = table_key.v64;
 911         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 912         if (err)
 913                 goto error;
 914         rte_atomic32_init(&tbl_data->tbl.refcnt);
 915         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 916         table_key.direction = 1;
 917         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 918         if (!tbl_data) {
 919                 err = ENOMEM;
 920                 goto error;
 921         }
 922         tbl_data->entry.key = table_key.v64;
 923         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 924         if (err)
 925                 goto error;
 926         rte_atomic32_init(&tbl_data->tbl.refcnt);
 927         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 928         table_key.direction = 0;
 929         table_key.domain = 1;
 930         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 931         if (!tbl_data) {
 932                 err = ENOMEM;
 933                 goto error;
 934         }
 935         tbl_data->entry.key = table_key.v64;
 936         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 937         if (err)
 938                 goto error;
 939         rte_atomic32_init(&tbl_data->tbl.refcnt);
 940         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 941         return err;
 942 error:
 943         mlx5_free_table_hash_list(priv);
 944 #endif /* HAVE_MLX5DV_DR */
 945         return err;
 946 }
 947
 948 /**
 949  * Initialize shared data between primary and secondary process.
 950  *
 951  * A memzone is reserved by primary process and secondary processes attach to
 952  * the memzone.
 953  *
 954  * @return
 955  *   0 on success, a negative errno value otherwise and rte_errno is set.
 956  */
 957 static int
 958 mlx5_init_shared_data(void)
 959 {
 960         const struct rte_memzone *mz;
 961         int ret = 0;
 962
 963         rte_spinlock_lock(&mlx5_shared_data_lock);
 964         if (mlx5_shared_data == NULL) {
 965                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
 966                         /* Allocate shared memory. */
 967                         mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
 968                                                  sizeof(*mlx5_shared_data),
 969                                                  SOCKET_ID_ANY, 0);
 970                         if (mz == NULL) {
 971                                 DRV_LOG(ERR,
 972                                         "Cannot allocate mlx5 shared data");
 973                                 ret = -rte_errno;
 974                                 goto error;
 975                         }
 976                         mlx5_shared_data = mz->addr;
 977                         memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
 978                         rte_spinlock_init(&mlx5_shared_data->lock);
 979                 } else {
 980                         /* Lookup allocated shared memory. */
 981                         mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
 982                         if (mz == NULL) {
 983                                 DRV_LOG(ERR,
 984                                         "Cannot attach mlx5 shared data");
 985                                 ret = -rte_errno;
 986                                 goto error;
 987                         }
 988                         mlx5_shared_data = mz->addr;
 989                         memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
 990                 }
 991         }
 992 error:
 993         rte_spinlock_unlock(&mlx5_shared_data_lock);
 994         return ret;
 995 }
 996
 997 /**
 998  * Retrieve integer value from environment variable.
 999  *
1000  * @param[in] name
1001  *   Environment variable name.
1002  *
1003  * @return
1004  *   Integer value, 0 if the variable is not set.
1005  */
1006 int
1007 mlx5_getenv_int(const char *name)
1008 {
1009         const char *val = getenv(name);
1010
1011         if (val == NULL)
1012                 return 0;
1013         return atoi(val);
1014 }
1015
1016 /**
1017  * DPDK callback to add udp tunnel port
1018  *
1019  * @param[in] dev
1020  *   A pointer to eth_dev
1021  * @param[in] udp_tunnel
1022  *   A pointer to udp tunnel
1023  *
1024  * @return
1025  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1026  */
1027 int
1028 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1029                          struct rte_eth_udp_tunnel *udp_tunnel)
1030 {
1031         MLX5_ASSERT(udp_tunnel != NULL);
1032         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1033             udp_tunnel->udp_port == 4789)
1034                 return 0;
1035         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1036             udp_tunnel->udp_port == 4790)
1037                 return 0;
1038         return -ENOTSUP;
1039 }
1040
1041 /**
1042  * Initialize process private data structure.
1043  *
1044  * @param dev
1045  *   Pointer to Ethernet device structure.
1046  *
1047  * @return
1048  *   0 on success, a negative errno value otherwise and rte_errno is set.
1049  */
1050 int
1051 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1052 {
1053         struct mlx5_priv *priv = dev->data->dev_private;
1054         struct mlx5_proc_priv *ppriv;
1055         size_t ppriv_size;
1056
1057         /*
1058          * UAR register table follows the process private structure. BlueFlame
1059          * registers for Tx queues are stored in the table.
1060          */
1061         ppriv_size =
1062                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1063         ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
1064                                   RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1065         if (!ppriv) {
1066                 rte_errno = ENOMEM;
1067                 return -rte_errno;
1068         }
1069         ppriv->uar_table_sz = ppriv_size;
1070         dev->process_private = ppriv;
1071         return 0;
1072 }
1073
1074 /**
1075  * Un-initialize process private data structure.
1076  *
1077  * @param dev
1078  *   Pointer to Ethernet device structure.
1079  */
1080 static void
1081 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1082 {
1083         if (!dev->process_private)
1084                 return;
1085         rte_free(dev->process_private);
1086         dev->process_private = NULL;
1087 }
1088
1089 /**
1090  * DPDK callback to close the device.
1091  *
1092  * Destroy all queues and objects, free memory.
1093  *
1094  * @param dev
1095  *   Pointer to Ethernet device structure.
1096  */
1097 void
1098 mlx5_dev_close(struct rte_eth_dev *dev)
1099 {
1100         struct mlx5_priv *priv = dev->data->dev_private;
1101         unsigned int i;
1102         int ret;
1103
1104         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1105                 /* Check if process_private released. */
1106                 if (!dev->process_private)
1107                         return;
1108                 mlx5_tx_uar_uninit_secondary(dev);
1109                 mlx5_proc_priv_uninit(dev);
1110                 rte_eth_dev_release_port(dev);
1111                 return;
1112         }
1113         if (!priv->sh)
1114                 return;
1115         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1116                 dev->data->port_id,
1117                 ((priv->sh->ctx != NULL) ?
1118                 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1119         /*
1120          * If default mreg copy action is removed at the stop stage,
1121          * the search will return none and nothing will be done anymore.
1122          */
1123         mlx5_flow_stop_default(dev);
1124         mlx5_traffic_disable(dev);
1125         /*
1126          * If all the flows are already flushed in the device stop stage,
1127          * then this will return directly without any action.
1128          */
1129         mlx5_flow_list_flush(dev, &priv->flows, true);
1130         mlx5_flow_meter_flush(dev, NULL);
1131         /* Free the intermediate buffers for flow creation. */
1132         mlx5_flow_free_intermediate(dev);
1133         /* Prevent crashes when queues are still in use. */
1134         dev->rx_pkt_burst = removed_rx_burst;
1135         dev->tx_pkt_burst = removed_tx_burst;
1136         rte_wmb();
1137         /* Disable datapath on secondary process. */
1138         mlx5_mp_req_stop_rxtx(dev);
1139         if (priv->rxqs != NULL) {
1140                 /* XXX race condition if mlx5_rx_burst() is still running. */
1141                 usleep(1000);
1142                 for (i = 0; (i != priv->rxqs_n); ++i)
1143                         mlx5_rxq_release(dev, i);
1144                 priv->rxqs_n = 0;
1145                 priv->rxqs = NULL;
1146         }
1147         if (priv->txqs != NULL) {
1148                 /* XXX race condition if mlx5_tx_burst() is still running. */
1149                 usleep(1000);
1150                 for (i = 0; (i != priv->txqs_n); ++i)
1151                         mlx5_txq_release(dev, i);
1152                 priv->txqs_n = 0;
1153                 priv->txqs = NULL;
1154         }
1155         mlx5_proc_priv_uninit(dev);
1156         if (priv->mreg_cp_tbl)
1157                 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1158         mlx5_mprq_free_mp(dev);
1159         mlx5_os_free_shared_dr(priv);
1160         if (priv->rss_conf.rss_key != NULL)
1161                 rte_free(priv->rss_conf.rss_key);
1162         if (priv->reta_idx != NULL)
1163                 rte_free(priv->reta_idx);
1164         if (priv->config.vf)
1165                 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1166                                        dev->data->mac_addrs,
1167                                        MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1168         if (priv->nl_socket_route >= 0)
1169                 close(priv->nl_socket_route);
1170         if (priv->nl_socket_rdma >= 0)
1171                 close(priv->nl_socket_rdma);
1172         if (priv->vmwa_context)
1173                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1174         ret = mlx5_hrxq_verify(dev);
1175         if (ret)
1176                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1177                         dev->data->port_id);
1178         ret = mlx5_ind_table_obj_verify(dev);
1179         if (ret)
1180                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1181                         dev->data->port_id);
1182         ret = mlx5_rxq_obj_verify(dev);
1183         if (ret)
1184                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1185                         dev->data->port_id);
1186         ret = mlx5_rxq_verify(dev);
1187         if (ret)
1188                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1189                         dev->data->port_id);
1190         ret = mlx5_txq_obj_verify(dev);
1191         if (ret)
1192                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1193                         dev->data->port_id);
1194         ret = mlx5_txq_verify(dev);
1195         if (ret)
1196                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1197                         dev->data->port_id);
1198         ret = mlx5_flow_verify(dev);
1199         if (ret)
1200                 DRV_LOG(WARNING, "port %u some flows still remain",
1201                         dev->data->port_id);
1202         /*
1203          * Free the shared context in last turn, because the cleanup
1204          * routines above may use some shared fields, like
1205          * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1206          * ifindex if Netlink fails.
1207          */
1208         mlx5_free_shared_dev_ctx(priv->sh);
1209         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1210                 unsigned int c = 0;
1211                 uint16_t port_id;
1212
1213                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1214                         struct mlx5_priv *opriv =
1215                                 rte_eth_devices[port_id].data->dev_private;
1216
1217                         if (!opriv ||
1218                             opriv->domain_id != priv->domain_id ||
1219                             &rte_eth_devices[port_id] == dev)
1220                                 continue;
1221                         ++c;
1222                         break;
1223                 }
1224                 if (!c)
1225                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1226         }
1227         memset(priv, 0, sizeof(*priv));
1228         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1229         /*
1230          * Reset mac_addrs to NULL such that it is not freed as part of
1231          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1232          * it is freed when dev_private is freed.
1233          */
1234         dev->data->mac_addrs = NULL;
1235 }
1236
1237 /**
1238  * Verify and store value for device argument.
1239  *
1240  * @param[in] key
1241  *   Key argument to verify.
1242  * @param[in] val
1243  *   Value associated with key.
1244  * @param opaque
1245  *   User data.
1246  *
1247  * @return
1248  *   0 on success, a negative errno value otherwise and rte_errno is set.
1249  */
1250 static int
1251 mlx5_args_check(const char *key, const char *val, void *opaque)
1252 {
1253         struct mlx5_dev_config *config = opaque;
1254         unsigned long tmp;
1255
1256         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1257         if (!strcmp(MLX5_REPRESENTOR, key))
1258                 return 0;
1259         errno = 0;
1260         tmp = strtoul(val, NULL, 0);
1261         if (errno) {
1262                 rte_errno = errno;
1263                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1264                 return -rte_errno;
1265         }
1266         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1267                 config->cqe_comp = !!tmp;
1268         } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1269                 config->cqe_pad = !!tmp;
1270         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1271                 config->hw_padding = !!tmp;
1272         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1273                 config->mprq.enabled = !!tmp;
1274         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1275                 config->mprq.stride_num_n = tmp;
1276         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1277                 config->mprq.stride_size_n = tmp;
1278         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1279                 config->mprq.max_memcpy_len = tmp;
1280         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1281                 config->mprq.min_rxqs_num = tmp;
1282         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1283                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1284                                  " converted to txq_inline_max", key);
1285                 config->txq_inline_max = tmp;
1286         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1287                 config->txq_inline_max = tmp;
1288         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1289                 config->txq_inline_min = tmp;
1290         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1291                 config->txq_inline_mpw = tmp;
1292         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1293                 config->txqs_inline = tmp;
1294         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1295                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1296         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1297                 config->mps = !!tmp;
1298         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1299                 if (tmp != MLX5_TXDB_CACHED &&
1300                     tmp != MLX5_TXDB_NCACHED &&
1301                     tmp != MLX5_TXDB_HEURISTIC) {
1302                         DRV_LOG(ERR, "invalid Tx doorbell "
1303                                      "mapping parameter");
1304                         rte_errno = EINVAL;
1305                         return -rte_errno;
1306                 }
1307                 config->dbnc = tmp;
1308         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1309                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1310         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1311                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1312                                  " converted to txq_inline_mpw", key);
1313                 config->txq_inline_mpw = tmp;
1314         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1315                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1316         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1317                 config->rx_vec_en = !!tmp;
1318         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1319                 config->l3_vxlan_en = !!tmp;
1320         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1321                 config->vf_nl_en = !!tmp;
1322         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1323                 config->dv_esw_en = !!tmp;
1324         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1325                 config->dv_flow_en = !!tmp;
1326         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1327                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1328                     tmp != MLX5_XMETA_MODE_META16 &&
1329                     tmp != MLX5_XMETA_MODE_META32) {
1330                         DRV_LOG(ERR, "invalid extensive "
1331                                      "metadata parameter");
1332                         rte_errno = EINVAL;
1333                         return -rte_errno;
1334                 }
1335                 config->dv_xmeta_en = tmp;
1336         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1337                 config->mr_ext_memseg_en = !!tmp;
1338         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1339                 config->max_dump_files_num = tmp;
1340         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1341                 config->lro.timeout = tmp;
1342         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1343                 DRV_LOG(DEBUG, "class argument is %s.", val);
1344         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1345                 config->log_hp_size = tmp;
1346         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1347                 if (tmp != MLX5_RCM_NONE &&
1348                     tmp != MLX5_RCM_LIGHT &&
1349                     tmp != MLX5_RCM_AGGR) {
1350                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1351                         rte_errno = EINVAL;
1352                         return -rte_errno;
1353                 }
1354                 config->reclaim_mode = tmp;
1355         } else {
1356                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1357                 rte_errno = EINVAL;
1358                 return -rte_errno;
1359         }
1360         return 0;
1361 }
1362
1363 /**
1364  * Parse device parameters.
1365  *
1366  * @param config
1367  *   Pointer to device configuration structure.
1368  * @param devargs
1369  *   Device arguments structure.
1370  *
1371  * @return
1372  *   0 on success, a negative errno value otherwise and rte_errno is set.
1373  */
1374 int
1375 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1376 {
1377         const char **params = (const char *[]){
1378                 MLX5_RXQ_CQE_COMP_EN,
1379                 MLX5_RXQ_CQE_PAD_EN,
1380                 MLX5_RXQ_PKT_PAD_EN,
1381                 MLX5_RX_MPRQ_EN,
1382                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1383                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1384                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1385                 MLX5_RXQS_MIN_MPRQ,
1386                 MLX5_TXQ_INLINE,
1387                 MLX5_TXQ_INLINE_MIN,
1388                 MLX5_TXQ_INLINE_MAX,
1389                 MLX5_TXQ_INLINE_MPW,
1390                 MLX5_TXQS_MIN_INLINE,
1391                 MLX5_TXQS_MAX_VEC,
1392                 MLX5_TXQ_MPW_EN,
1393                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1394                 MLX5_TXQ_MAX_INLINE_LEN,
1395                 MLX5_TX_DB_NC,
1396                 MLX5_TX_VEC_EN,
1397                 MLX5_RX_VEC_EN,
1398                 MLX5_L3_VXLAN_EN,
1399                 MLX5_VF_NL_EN,
1400                 MLX5_DV_ESW_EN,
1401                 MLX5_DV_FLOW_EN,
1402                 MLX5_DV_XMETA_EN,
1403                 MLX5_MR_EXT_MEMSEG_EN,
1404                 MLX5_REPRESENTOR,
1405                 MLX5_MAX_DUMP_FILES_NUM,
1406                 MLX5_LRO_TIMEOUT_USEC,
1407                 MLX5_CLASS_ARG_NAME,
1408                 MLX5_HP_BUF_SIZE,
1409                 MLX5_RECLAIM_MEM,
1410                 NULL,
1411         };
1412         struct rte_kvargs *kvlist;
1413         int ret = 0;
1414         int i;
1415
1416         if (devargs == NULL)
1417                 return 0;
1418         /* Following UGLY cast is done to pass checkpatch. */
1419         kvlist = rte_kvargs_parse(devargs->args, params);
1420         if (kvlist == NULL) {
1421                 rte_errno = EINVAL;
1422                 return -rte_errno;
1423         }
1424         /* Process parameters. */
1425         for (i = 0; (params[i] != NULL); ++i) {
1426                 if (rte_kvargs_count(kvlist, params[i])) {
1427                         ret = rte_kvargs_process(kvlist, params[i],
1428                                                  mlx5_args_check, config);
1429                         if (ret) {
1430                                 rte_errno = EINVAL;
1431                                 rte_kvargs_free(kvlist);
1432                                 return -rte_errno;
1433                         }
1434                 }
1435         }
1436         rte_kvargs_free(kvlist);
1437         return 0;
1438 }
1439
1440 /**
1441  * PMD global initialization.
1442  *
1443  * Independent from individual device, this function initializes global
1444  * per-PMD data structures distinguishing primary and secondary processes.
1445  * Hence, each initialization is called once per a process.
1446  *
1447  * @return
1448  *   0 on success, a negative errno value otherwise and rte_errno is set.
1449  */
1450 int
1451 mlx5_init_once(void)
1452 {
1453         struct mlx5_shared_data *sd;
1454         struct mlx5_local_data *ld = &mlx5_local_data;
1455         int ret = 0;
1456
1457         if (mlx5_init_shared_data())
1458                 return -rte_errno;
1459         sd = mlx5_shared_data;
1460         MLX5_ASSERT(sd);
1461         rte_spinlock_lock(&sd->lock);
1462         switch (rte_eal_process_type()) {
1463         case RTE_PROC_PRIMARY:
1464                 if (sd->init_done)
1465                         break;
1466                 LIST_INIT(&sd->mem_event_cb_list);
1467                 rte_rwlock_init(&sd->mem_event_rwlock);
1468                 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1469                                                 mlx5_mr_mem_event_cb, NULL);
1470                 ret = mlx5_mp_init_primary(MLX5_MP_NAME,
1471                                            mlx5_mp_primary_handle);
1472                 if (ret)
1473                         goto out;
1474                 sd->init_done = true;
1475                 break;
1476         case RTE_PROC_SECONDARY:
1477                 if (ld->init_done)
1478                         break;
1479                 ret = mlx5_mp_init_secondary(MLX5_MP_NAME,
1480                                              mlx5_mp_secondary_handle);
1481                 if (ret)
1482                         goto out;
1483                 ++sd->secondary_cnt;
1484                 ld->init_done = true;
1485                 break;
1486         default:
1487                 break;
1488         }
1489 out:
1490         rte_spinlock_unlock(&sd->lock);
1491         return ret;
1492 }
1493
1494 /**
1495  * Configures the minimal amount of data to inline into WQE
1496  * while sending packets.
1497  *
1498  * - the txq_inline_min has the maximal priority, if this
1499  *   key is specified in devargs
1500  * - if DevX is enabled the inline mode is queried from the
1501  *   device (HCA attributes and NIC vport context if needed).
1502  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1503  *   and none (0 bytes) for other NICs
1504  *
1505  * @param spawn
1506  *   Verbs device parameters (name, port, switch_info) to spawn.
1507  * @param config
1508  *   Device configuration parameters.
1509  */
1510 void
1511 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1512                     struct mlx5_dev_config *config)
1513 {
1514         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1515                 /* Application defines size of inlined data explicitly. */
1516                 switch (spawn->pci_dev->id.device_id) {
1517                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1518                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1519                         if (config->txq_inline_min <
1520                                        (int)MLX5_INLINE_HSIZE_L2) {
1521                                 DRV_LOG(DEBUG,
1522                                         "txq_inline_mix aligned to minimal"
1523                                         " ConnectX-4 required value %d",
1524                                         (int)MLX5_INLINE_HSIZE_L2);
1525                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1526                         }
1527                         break;
1528                 }
1529                 goto exit;
1530         }
1531         if (config->hca_attr.eth_net_offloads) {
1532                 /* We have DevX enabled, inline mode queried successfully. */
1533                 switch (config->hca_attr.wqe_inline_mode) {
1534                 case MLX5_CAP_INLINE_MODE_L2:
1535                         /* outer L2 header must be inlined. */
1536                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1537                         goto exit;
1538                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1539                         /* No inline data are required by NIC. */
1540                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1541                         config->hw_vlan_insert =
1542                                 config->hca_attr.wqe_vlan_insert;
1543                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1544                         goto exit;
1545                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1546                         /* inline mode is defined by NIC vport context. */
1547                         if (!config->hca_attr.eth_virt)
1548                                 break;
1549                         switch (config->hca_attr.vport_inline_mode) {
1550                         case MLX5_INLINE_MODE_NONE:
1551                                 config->txq_inline_min =
1552                                         MLX5_INLINE_HSIZE_NONE;
1553                                 goto exit;
1554                         case MLX5_INLINE_MODE_L2:
1555                                 config->txq_inline_min =
1556                                         MLX5_INLINE_HSIZE_L2;
1557                                 goto exit;
1558                         case MLX5_INLINE_MODE_IP:
1559                                 config->txq_inline_min =
1560                                         MLX5_INLINE_HSIZE_L3;
1561                                 goto exit;
1562                         case MLX5_INLINE_MODE_TCP_UDP:
1563                                 config->txq_inline_min =
1564                                         MLX5_INLINE_HSIZE_L4;
1565                                 goto exit;
1566                         case MLX5_INLINE_MODE_INNER_L2:
1567                                 config->txq_inline_min =
1568                                         MLX5_INLINE_HSIZE_INNER_L2;
1569                                 goto exit;
1570                         case MLX5_INLINE_MODE_INNER_IP:
1571                                 config->txq_inline_min =
1572                                         MLX5_INLINE_HSIZE_INNER_L3;
1573                                 goto exit;
1574                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
1575                                 config->txq_inline_min =
1576                                         MLX5_INLINE_HSIZE_INNER_L4;
1577                                 goto exit;
1578                         }
1579                 }
1580         }
1581         /*
1582          * We get here if we are unable to deduce
1583          * inline data size with DevX. Try PCI ID
1584          * to determine old NICs.
1585          */
1586         switch (spawn->pci_dev->id.device_id) {
1587         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1588         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1589         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1590         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1591                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1592                 config->hw_vlan_insert = 0;
1593                 break;
1594         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1595         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1596         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1597         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1598                 /*
1599                  * These NICs support VLAN insertion from WQE and
1600                  * report the wqe_vlan_insert flag. But there is the bug
1601                  * and PFC control may be broken, so disable feature.
1602                  */
1603                 config->hw_vlan_insert = 0;
1604                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1605                 break;
1606         default:
1607                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1608                 break;
1609         }
1610 exit:
1611         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1612 }
1613
1614 /**
1615  * Configures the metadata mask fields in the shared context.
1616  *
1617  * @param [in] dev
1618  *   Pointer to Ethernet device.
1619  */
1620 void
1621 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1622 {
1623         struct mlx5_priv *priv = dev->data->dev_private;
1624         struct mlx5_dev_ctx_shared *sh = priv->sh;
1625         uint32_t meta, mark, reg_c0;
1626
1627         reg_c0 = ~priv->vport_meta_mask;
1628         switch (priv->config.dv_xmeta_en) {
1629         case MLX5_XMETA_MODE_LEGACY:
1630                 meta = UINT32_MAX;
1631                 mark = MLX5_FLOW_MARK_MASK;
1632                 break;
1633         case MLX5_XMETA_MODE_META16:
1634                 meta = reg_c0 >> rte_bsf32(reg_c0);
1635                 mark = MLX5_FLOW_MARK_MASK;
1636                 break;
1637         case MLX5_XMETA_MODE_META32:
1638                 meta = UINT32_MAX;
1639                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1640                 break;
1641         default:
1642                 meta = 0;
1643                 mark = 0;
1644                 MLX5_ASSERT(false);
1645                 break;
1646         }
1647         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1648                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1649                                  sh->dv_mark_mask, mark);
1650         else
1651                 sh->dv_mark_mask = mark;
1652         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1653                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1654                                  sh->dv_meta_mask, meta);
1655         else
1656                 sh->dv_meta_mask = meta;
1657         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1658                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1659                                  sh->dv_meta_mask, reg_c0);
1660         else
1661                 sh->dv_regc0_mask = reg_c0;
1662         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1663         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1664         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1665         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1666 }
1667
1668 /**
1669  * Allocate page of door-bells and register it using DevX API.
1670  *
1671  * @param [in] dev
1672  *   Pointer to Ethernet device.
1673  *
1674  * @return
1675  *   Pointer to new page on success, NULL otherwise.
1676  */
1677 static struct mlx5_devx_dbr_page *
1678 mlx5_alloc_dbr_page(struct rte_eth_dev *dev)
1679 {
1680         struct mlx5_priv *priv = dev->data->dev_private;
1681         struct mlx5_devx_dbr_page *page;
1682
1683         /* Allocate space for door-bell page and management data. */
1684         page = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_devx_dbr_page),
1685                                  RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1686         if (!page) {
1687                 DRV_LOG(ERR, "port %u cannot allocate dbr page",
1688                         dev->data->port_id);
1689                 return NULL;
1690         }
1691         /* Register allocated memory. */
1692         page->umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, page->dbrs,
1693                                               MLX5_DBR_PAGE_SIZE, 0);
1694         if (!page->umem) {
1695                 DRV_LOG(ERR, "port %u cannot umem reg dbr page",
1696                         dev->data->port_id);
1697                 rte_free(page);
1698                 return NULL;
1699         }
1700         return page;
1701 }
1702
1703 /**
1704  * Find the next available door-bell, allocate new page if needed.
1705  *
1706  * @param [in] dev
1707  *   Pointer to Ethernet device.
1708  * @param [out] dbr_page
1709  *   Door-bell page containing the page data.
1710  *
1711  * @return
1712  *   Door-bell address offset on success, a negative error value otherwise.
1713  */
1714 int64_t
1715 mlx5_get_dbr(struct rte_eth_dev *dev, struct mlx5_devx_dbr_page **dbr_page)
1716 {
1717         struct mlx5_priv *priv = dev->data->dev_private;
1718         struct mlx5_devx_dbr_page *page = NULL;
1719         uint32_t i, j;
1720
1721         LIST_FOREACH(page, &priv->dbrpgs, next)
1722                 if (page->dbr_count < MLX5_DBR_PER_PAGE)
1723                         break;
1724         if (!page) { /* No page with free door-bell exists. */
1725                 page = mlx5_alloc_dbr_page(dev);
1726                 if (!page) /* Failed to allocate new page. */
1727                         return (-1);
1728                 LIST_INSERT_HEAD(&priv->dbrpgs, page, next);
1729         }
1730         /* Loop to find bitmap part with clear bit. */
1731         for (i = 0;
1732              i < MLX5_DBR_BITMAP_SIZE && page->dbr_bitmap[i] == UINT64_MAX;
1733              i++)
1734                 ; /* Empty. */
1735         /* Find the first clear bit. */
1736         MLX5_ASSERT(i < MLX5_DBR_BITMAP_SIZE);
1737         j = rte_bsf64(~page->dbr_bitmap[i]);
1738         page->dbr_bitmap[i] |= (UINT64_C(1) << j);
1739         page->dbr_count++;
1740         *dbr_page = page;
1741         return (((i * 64) + j) * sizeof(uint64_t));
1742 }
1743
1744 /**
1745  * Release a door-bell record.
1746  *
1747  * @param [in] dev
1748  *   Pointer to Ethernet device.
1749  * @param [in] umem_id
1750  *   UMEM ID of page containing the door-bell record to release.
1751  * @param [in] offset
1752  *   Offset of door-bell record in page.
1753  *
1754  * @return
1755  *   0 on success, a negative error value otherwise.
1756  */
1757 int32_t
1758 mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id, uint64_t offset)
1759 {
1760         struct mlx5_priv *priv = dev->data->dev_private;
1761         struct mlx5_devx_dbr_page *page = NULL;
1762         int ret = 0;
1763
1764         LIST_FOREACH(page, &priv->dbrpgs, next)
1765                 /* Find the page this address belongs to. */
1766                 if (mlx5_os_get_umem_id(page->umem) == umem_id)
1767                         break;
1768         if (!page)
1769                 return -EINVAL;
1770         page->dbr_count--;
1771         if (!page->dbr_count) {
1772                 /* Page not used, free it and remove from list. */
1773                 LIST_REMOVE(page, next);
1774                 if (page->umem)
1775                         ret = -mlx5_glue->devx_umem_dereg(page->umem);
1776                 rte_free(page);
1777         } else {
1778                 /* Mark in bitmap that this door-bell is not in use. */
1779                 offset /= MLX5_DBR_SIZE;
1780                 int i = offset / 64;
1781                 int j = offset % 64;
1782
1783                 page->dbr_bitmap[i] &= ~(UINT64_C(1) << j);
1784         }
1785         return ret;
1786 }
1787
1788 int
1789 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1790 {
1791         static const char *const dynf_names[] = {
1792                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1793                 RTE_MBUF_DYNFLAG_METADATA_NAME
1794         };
1795         unsigned int i;
1796
1797         if (n < RTE_DIM(dynf_names))
1798                 return -ENOMEM;
1799         for (i = 0; i < RTE_DIM(dynf_names); i++) {
1800                 if (names[i] == NULL)
1801                         return -EINVAL;
1802                 strcpy(names[i], dynf_names[i]);
1803         }
1804         return RTE_DIM(dynf_names);
1805 }
1806
1807 /**
1808  * Comparison callback to sort device data.
1809  *
1810  * This is meant to be used with qsort().
1811  *
1812  * @param a[in]
1813  *   Pointer to pointer to first data object.
1814  * @param b[in]
1815  *   Pointer to pointer to second data object.
1816  *
1817  * @return
1818  *   0 if both objects are equal, less than 0 if the first argument is less
1819  *   than the second, greater than 0 otherwise.
1820  */
1821 int
1822 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1823                               struct mlx5_dev_config *config)
1824 {
1825         struct mlx5_dev_ctx_shared *sh = priv->sh;
1826         struct mlx5_dev_config *sh_conf = NULL;
1827         uint16_t port_id;
1828
1829         MLX5_ASSERT(sh);
1830         /* Nothing to compare for the single/first device. */
1831         if (sh->refcnt == 1)
1832                 return 0;
1833         /* Find the device with shared context. */
1834         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1835                 struct mlx5_priv *opriv =
1836                         rte_eth_devices[port_id].data->dev_private;
1837
1838                 if (opriv && opriv != priv && opriv->sh == sh) {
1839                         sh_conf = &opriv->config;
1840                         break;
1841                 }
1842         }
1843         if (!sh_conf)
1844                 return 0;
1845         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1846                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1847                              " for shared %s context", sh->ibdev_name);
1848                 rte_errno = EINVAL;
1849                 return rte_errno;
1850         }
1851         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1852                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1853                              " for shared %s context", sh->ibdev_name);
1854                 rte_errno = EINVAL;
1855                 return rte_errno;
1856         }
1857         return 0;
1858 }
1859
1860 /**
1861  * Look for the ethernet device belonging to mlx5 driver.
1862  *
1863  * @param[in] port_id
1864  *   port_id to start looking for device.
1865  * @param[in] pci_dev
1866  *   Pointer to the hint PCI device. When device is being probed
1867  *   the its siblings (master and preceding representors might
1868  *   not have assigned driver yet (because the mlx5_os_pci_probe()
1869  *   is not completed yet, for this case match on hint PCI
1870  *   device may be used to detect sibling device.
1871  *
1872  * @return
1873  *   port_id of found device, RTE_MAX_ETHPORT if not found.
1874  */
1875 uint16_t
1876 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
1877 {
1878         while (port_id < RTE_MAX_ETHPORTS) {
1879                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
1880
1881                 if (dev->state != RTE_ETH_DEV_UNUSED &&
1882                     dev->device &&
1883                     (dev->device == &pci_dev->device ||
1884                      (dev->device->driver &&
1885                      dev->device->driver->name &&
1886                      !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
1887                         break;
1888                 port_id++;
1889         }
1890         if (port_id >= RTE_MAX_ETHPORTS)
1891                 return RTE_MAX_ETHPORTS;
1892         return port_id;
1893 }
1894
1895 /**
1896  * DPDK callback to remove a PCI device.
1897  *
1898  * This function removes all Ethernet devices belong to a given PCI device.
1899  *
1900  * @param[in] pci_dev
1901  *   Pointer to the PCI device.
1902  *
1903  * @return
1904  *   0 on success, the function cannot fail.
1905  */
1906 static int
1907 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1908 {
1909         uint16_t port_id;
1910
1911         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
1912                 /*
1913                  * mlx5_dev_close() is not registered to secondary process,
1914                  * call the close function explicitly for secondary process.
1915                  */
1916                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
1917                         mlx5_dev_close(&rte_eth_devices[port_id]);
1918                 else
1919                         rte_eth_dev_close(port_id);
1920         }
1921         return 0;
1922 }
1923
1924 static const struct rte_pci_id mlx5_pci_id_map[] = {
1925         {
1926                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1927                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1928         },
1929         {
1930                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1931                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1932         },
1933         {
1934                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1935                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1936         },
1937         {
1938                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1939                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1940         },
1941         {
1942                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1943                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1944         },
1945         {
1946                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1947                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1948         },
1949         {
1950                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1951                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1952         },
1953         {
1954                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1955                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1956         },
1957         {
1958                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1959                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
1960         },
1961         {
1962                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1963                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
1964         },
1965         {
1966                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1967                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
1968         },
1969         {
1970                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1971                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
1972         },
1973         {
1974                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1975                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
1976         },
1977         {
1978                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1979                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
1980         },
1981         {
1982                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1983                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
1984         },
1985         {
1986                 .vendor_id = 0
1987         }
1988 };
1989
1990 struct rte_pci_driver mlx5_driver = {
1991         .driver = {
1992                 .name = MLX5_DRIVER_NAME
1993         },
1994         .id_table = mlx5_pci_id_map,
1995         .probe = mlx5_os_pci_probe,
1996         .remove = mlx5_pci_remove,
1997         .dma_map = mlx5_dma_map,
1998         .dma_unmap = mlx5_dma_unmap,
1999         .drv_flags = PCI_DRV_FLAGS,
2000 };
2001
2002 /**
2003  * Driver initialization routine.
2004  */
2005 RTE_INIT(rte_mlx5_pmd_init)
2006 {
2007         /* Initialize driver log type. */
2008         mlx5_logtype = rte_log_register("pmd.net.mlx5");
2009         if (mlx5_logtype >= 0)
2010                 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
2011
2012         /* Build the static tables for Verbs conversion. */
2013         mlx5_set_ptype_table();
2014         mlx5_set_cksum_table();
2015         mlx5_set_swp_types_table();
2016         if (mlx5_glue)
2017                 rte_pci_register(&mlx5_driver);
2018 }
2019
2020 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2021 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2022 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");