drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12 #include <net/if.h>
  13 #include <sys/mman.h>
  14 #include <linux/rtnetlink.h>
  15
  16 /* Verbs header. */
  17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  18 #ifdef PEDANTIC
  19 #pragma GCC diagnostic ignored "-Wpedantic"
  20 #endif
  21 #include <infiniband/verbs.h>
  22 #ifdef PEDANTIC
  23 #pragma GCC diagnostic error "-Wpedantic"
  24 #endif
  25
  26 #include <rte_malloc.h>
  27 #include <rte_ethdev_driver.h>
  28 #include <rte_ethdev_pci.h>
  29 #include <rte_pci.h>
  30 #include <rte_bus_pci.h>
  31 #include <rte_common.h>
  32 #include <rte_kvargs.h>
  33 #include <rte_rwlock.h>
  34 #include <rte_spinlock.h>
  35 #include <rte_string_fns.h>
  36 #include <rte_alarm.h>
  37
  38 #include <mlx5_glue.h>
  39 #include <mlx5_devx_cmds.h>
  40 #include <mlx5_common.h>
  41 #include <mlx5_common_mp.h>
  42
  43 #include "mlx5_defs.h"
  44 #include "mlx5.h"
  45 #include "mlx5_utils.h"
  46 #include "mlx5_rxtx.h"
  47 #include "mlx5_autoconf.h"
  48 #include "mlx5_mr.h"
  49 #include "mlx5_flow.h"
  50 #include "rte_pmd_mlx5.h"
  51
  52 /* Device parameter to enable RX completion queue compression. */
  53 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  54
  55 /* Device parameter to enable RX completion entry padding to 128B. */
  56 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
  57
  58 /* Device parameter to enable padding Rx packet to cacheline size. */
  59 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  60
  61 /* Device parameter to enable Multi-Packet Rx queue. */
  62 #define MLX5_RX_MPRQ_EN "mprq_en"
  63
  64 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  65 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  66
  67 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  68 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  69
  70 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  71 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  72
  73 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  74 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  75
  76 /* Device parameter to configure inline send. Deprecated, ignored.*/
  77 #define MLX5_TXQ_INLINE "txq_inline"
  78
  79 /* Device parameter to limit packet size to inline with ordinary SEND. */
  80 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  81
  82 /* Device parameter to configure minimal data size to inline. */
  83 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  84
  85 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  86 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  87
  88 /*
  89  * Device parameter to configure the number of TX queues threshold for
  90  * enabling inline send.
  91  */
  92 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  93
  94 /*
  95  * Device parameter to configure the number of TX queues threshold for
  96  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  97  */
  98 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  99
 100 /* Device parameter to enable multi-packet send WQEs. */
 101 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
 102
 103 /*
 104  * Device parameter to force doorbell register mapping
 105  * to non-cahed region eliminating the extra write memory barrier.
 106  */
 107 #define MLX5_TX_DB_NC "tx_db_nc"
 108
 109 /*
 110  * Device parameter to include 2 dsegs in the title WQEBB.
 111  * Deprecated, ignored.
 112  */
 113 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 114
 115 /*
 116  * Device parameter to limit the size of inlining packet.
 117  * Deprecated, ignored.
 118  */
 119 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 120
 121 /*
 122  * Device parameter to enable hardware Tx vector.
 123  * Deprecated, ignored (no vectorized Tx routines anymore).
 124  */
 125 #define MLX5_TX_VEC_EN "tx_vec_en"
 126
 127 /* Device parameter to enable hardware Rx vector. */
 128 #define MLX5_RX_VEC_EN "rx_vec_en"
 129
 130 /* Allow L3 VXLAN flow creation. */
 131 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 132
 133 /* Activate DV E-Switch flow steering. */
 134 #define MLX5_DV_ESW_EN "dv_esw_en"
 135
 136 /* Activate DV flow steering. */
 137 #define MLX5_DV_FLOW_EN "dv_flow_en"
 138
 139 /* Enable extensive flow metadata support. */
 140 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 141
 142 /* Activate Netlink support in VF mode. */
 143 #define MLX5_VF_NL_EN "vf_nl_en"
 144
 145 /* Enable extending memsegs when creating a MR. */
 146 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 147
 148 /* Select port representors to instantiate. */
 149 #define MLX5_REPRESENTOR "representor"
 150
 151 /* Device parameter to configure the maximum number of dump files per queue. */
 152 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 153
 154 /* Configure timeout of LRO session (in microseconds). */
 155 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 156
 157 /*
 158  * Device parameter to configure the total data buffer size for a single
 159  * hairpin queue (logarithm value).
 160  */
 161 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 162
 163 #ifndef HAVE_IBV_MLX5_MOD_MPW
 164 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
 165 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
 166 #endif
 167
 168 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
 169 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
 170 #endif
 171
 172 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
 173
 174 /* Shared memory between primary and secondary processes. */
 175 struct mlx5_shared_data *mlx5_shared_data;
 176
 177 /* Spinlock for mlx5_shared_data allocation. */
 178 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
 179
 180 /* Process local data for secondary processes. */
 181 static struct mlx5_local_data mlx5_local_data;
 182
 183 /** Driver-specific log messages type. */
 184 int mlx5_logtype;
 185
 186 /** Data associated with devices to spawn. */
 187 struct mlx5_dev_spawn_data {
 188         uint32_t ifindex; /**< Network interface index. */
 189         uint32_t max_port; /**< IB device maximal port index. */
 190         uint32_t ibv_port; /**< IB device physical port index. */
 191         int pf_bond; /**< bonding device PF index. < 0 - no bonding */
 192         struct mlx5_switch_info info; /**< Switch information. */
 193         struct ibv_device *ibv_dev; /**< Associated IB device. */
 194         struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
 195         struct rte_pci_device *pci_dev; /**< Backend PCI device. */
 196 };
 197
 198 static LIST_HEAD(, mlx5_ibv_shared) mlx5_ibv_list = LIST_HEAD_INITIALIZER();
 199 static pthread_mutex_t mlx5_ibv_list_mutex = PTHREAD_MUTEX_INITIALIZER;
 200
 201 static struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 202 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 203         {
 204                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 205                 .trunk_size = 64,
 206                 .grow_trunk = 3,
 207                 .grow_shift = 2,
 208                 .need_lock = 0,
 209                 .release_mem_en = 1,
 210                 .malloc = rte_malloc_socket,
 211                 .free = rte_free,
 212                 .type = "mlx5_encap_decap_ipool",
 213         },
 214         {
 215                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 216                 .trunk_size = 64,
 217                 .grow_trunk = 3,
 218                 .grow_shift = 2,
 219                 .need_lock = 0,
 220                 .release_mem_en = 1,
 221                 .malloc = rte_malloc_socket,
 222                 .free = rte_free,
 223                 .type = "mlx5_push_vlan_ipool",
 224         },
 225         {
 226                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 227                 .trunk_size = 64,
 228                 .grow_trunk = 3,
 229                 .grow_shift = 2,
 230                 .need_lock = 0,
 231                 .release_mem_en = 1,
 232                 .malloc = rte_malloc_socket,
 233                 .free = rte_free,
 234                 .type = "mlx5_tag_ipool",
 235         },
 236         {
 237                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 238                 .trunk_size = 64,
 239                 .grow_trunk = 3,
 240                 .grow_shift = 2,
 241                 .need_lock = 0,
 242                 .release_mem_en = 1,
 243                 .malloc = rte_malloc_socket,
 244                 .free = rte_free,
 245                 .type = "mlx5_port_id_ipool",
 246         },
 247         {
 248                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 249                 .trunk_size = 64,
 250                 .grow_trunk = 3,
 251                 .grow_shift = 2,
 252                 .need_lock = 0,
 253                 .release_mem_en = 1,
 254                 .malloc = rte_malloc_socket,
 255                 .free = rte_free,
 256                 .type = "mlx5_jump_ipool",
 257         },
 258 #endif
 259         {
 260                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 261                 .trunk_size = 64,
 262                 .grow_trunk = 3,
 263                 .grow_shift = 2,
 264                 .need_lock = 0,
 265                 .release_mem_en = 1,
 266                 .malloc = rte_malloc_socket,
 267                 .free = rte_free,
 268                 .type = "mlx5_hrxq_ipool",
 269         },
 270         {
 271                 .size = sizeof(struct mlx5_flow_handle),
 272                 .trunk_size = 64,
 273                 .grow_trunk = 3,
 274                 .grow_shift = 2,
 275                 .need_lock = 0,
 276                 .release_mem_en = 1,
 277                 .malloc = rte_malloc_socket,
 278                 .free = rte_free,
 279                 .type = "mlx5_flow_handle_ipool",
 280         },
 281 };
 282
 283
 284 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 285 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 286
 287 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 288 #define MLX5_TAGS_HLIST_ARRAY_SIZE 8192
 289
 290 /**
 291  * Allocate ID pool structure.
 292  *
 293  * @param[in] max_id
 294  *   The maximum id can be allocated from the pool.
 295  *
 296  * @return
 297  *   Pointer to pool object, NULL value otherwise.
 298  */
 299 struct mlx5_flow_id_pool *
 300 mlx5_flow_id_pool_alloc(uint32_t max_id)
 301 {
 302         struct mlx5_flow_id_pool *pool;
 303         void *mem;
 304
 305         pool = rte_zmalloc("id pool allocation", sizeof(*pool),
 306                            RTE_CACHE_LINE_SIZE);
 307         if (!pool) {
 308                 DRV_LOG(ERR, "can't allocate id pool");
 309                 rte_errno  = ENOMEM;
 310                 return NULL;
 311         }
 312         mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
 313                           RTE_CACHE_LINE_SIZE);
 314         if (!mem) {
 315                 DRV_LOG(ERR, "can't allocate mem for id pool");
 316                 rte_errno  = ENOMEM;
 317                 goto error;
 318         }
 319         pool->free_arr = mem;
 320         pool->curr = pool->free_arr;
 321         pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
 322         pool->base_index = 0;
 323         pool->max_id = max_id;
 324         return pool;
 325 error:
 326         rte_free(pool);
 327         return NULL;
 328 }
 329
 330 /**
 331  * Release ID pool structure.
 332  *
 333  * @param[in] pool
 334  *   Pointer to flow id pool object to free.
 335  */
 336 void
 337 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
 338 {
 339         rte_free(pool->free_arr);
 340         rte_free(pool);
 341 }
 342
 343 /**
 344  * Generate ID.
 345  *
 346  * @param[in] pool
 347  *   Pointer to flow id pool.
 348  * @param[out] id
 349  *   The generated ID.
 350  *
 351  * @return
 352  *   0 on success, error value otherwise.
 353  */
 354 uint32_t
 355 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
 356 {
 357         if (pool->curr == pool->free_arr) {
 358                 if (pool->base_index == pool->max_id) {
 359                         rte_errno  = ENOMEM;
 360                         DRV_LOG(ERR, "no free id");
 361                         return -rte_errno;
 362                 }
 363                 *id = ++pool->base_index;
 364                 return 0;
 365         }
 366         *id = *(--pool->curr);
 367         return 0;
 368 }
 369
 370 /**
 371  * Release ID.
 372  *
 373  * @param[in] pool
 374  *   Pointer to flow id pool.
 375  * @param[out] id
 376  *   The generated ID.
 377  *
 378  * @return
 379  *   0 on success, error value otherwise.
 380  */
 381 uint32_t
 382 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
 383 {
 384         uint32_t size;
 385         uint32_t size2;
 386         void *mem;
 387
 388         if (pool->curr == pool->last) {
 389                 size = pool->curr - pool->free_arr;
 390                 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
 391                 MLX5_ASSERT(size2 > size);
 392                 mem = rte_malloc("", size2 * sizeof(uint32_t), 0);
 393                 if (!mem) {
 394                         DRV_LOG(ERR, "can't allocate mem for id pool");
 395                         rte_errno  = ENOMEM;
 396                         return -rte_errno;
 397                 }
 398                 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
 399                 rte_free(pool->free_arr);
 400                 pool->free_arr = mem;
 401                 pool->curr = pool->free_arr + size;
 402                 pool->last = pool->free_arr + size2;
 403         }
 404         *pool->curr = id;
 405         pool->curr++;
 406         return 0;
 407 }
 408
 409 /**
 410  * Initialize the counters management structure.
 411  *
 412  * @param[in] sh
 413  *   Pointer to mlx5_ibv_shared object to free
 414  */
 415 static void
 416 mlx5_flow_counters_mng_init(struct mlx5_ibv_shared *sh)
 417 {
 418         uint8_t i;
 419
 420         TAILQ_INIT(&sh->cmng.flow_counters);
 421         for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i)
 422                 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
 423 }
 424
 425 /**
 426  * Destroy all the resources allocated for a counter memory management.
 427  *
 428  * @param[in] mng
 429  *   Pointer to the memory management structure.
 430  */
 431 static void
 432 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 433 {
 434         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 435
 436         LIST_REMOVE(mng, next);
 437         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 438         claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
 439         rte_free(mem);
 440 }
 441
 442 /**
 443  * Close and release all the resources of the counters management.
 444  *
 445  * @param[in] sh
 446  *   Pointer to mlx5_ibv_shared object to free.
 447  */
 448 static void
 449 mlx5_flow_counters_mng_close(struct mlx5_ibv_shared *sh)
 450 {
 451         struct mlx5_counter_stats_mem_mng *mng;
 452         uint8_t i;
 453         int j;
 454         int retries = 1024;
 455
 456         rte_errno = 0;
 457         while (--retries) {
 458                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 459                 if (rte_errno != EINPROGRESS)
 460                         break;
 461                 rte_pause();
 462         }
 463         for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i) {
 464                 struct mlx5_flow_counter_pool *pool;
 465                 uint32_t batch = !!(i % 2);
 466
 467                 if (!sh->cmng.ccont[i].pools)
 468                         continue;
 469                 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 470                 while (pool) {
 471                         if (batch) {
 472                                 if (pool->min_dcs)
 473                                         claim_zero
 474                                         (mlx5_devx_cmd_destroy(pool->min_dcs));
 475                         }
 476                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 477                                 if (pool->counters_raw[j].action)
 478                                         claim_zero
 479                                         (mlx5_glue->destroy_flow_action
 480                                                (pool->counters_raw[j].action));
 481                                 if (!batch && MLX5_GET_POOL_CNT_EXT
 482                                     (pool, j)->dcs)
 483                                         claim_zero(mlx5_devx_cmd_destroy
 484                                                   (MLX5_GET_POOL_CNT_EXT
 485                                                   (pool, j)->dcs));
 486                         }
 487                         TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool,
 488                                      next);
 489                         rte_free(pool);
 490                         pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 491                 }
 492                 rte_free(sh->cmng.ccont[i].pools);
 493         }
 494         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 495         while (mng) {
 496                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 497                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 498         }
 499         memset(&sh->cmng, 0, sizeof(sh->cmng));
 500 }
 501
 502 /**
 503  * Initialize the flow resources' indexed mempool.
 504  *
 505  * @param[in] sh
 506  *   Pointer to mlx5_ibv_shared object.
 507  * @param[in] sh
 508  *   Pointer to user dev config.
 509  */
 510 static void
 511 mlx5_flow_ipool_create(struct mlx5_ibv_shared *sh,
 512                        const struct mlx5_dev_config *config __rte_unused)
 513 {
 514         uint8_t i;
 515
 516 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 517         /*
 518          * While DV is supported, user chooses the verbs mode,
 519          * the mlx5 flow handle size is different with the
 520          * MLX5_FLOW_HANDLE_VERBS_SIZE.
 521          */
 522         if (!config->dv_flow_en)
 523                 mlx5_ipool_cfg[MLX5_IPOOL_MLX5_FLOW].size =
 524                                         MLX5_FLOW_HANDLE_VERBS_SIZE;
 525 #endif
 526         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 527                 sh->ipool[i] = mlx5_ipool_create(&mlx5_ipool_cfg[i]);
 528 }
 529
 530 /**
 531  * Release the flow resources' indexed mempool.
 532  *
 533  * @param[in] sh
 534  *   Pointer to mlx5_ibv_shared object.
 535  */
 536 static void
 537 mlx5_flow_ipool_destroy(struct mlx5_ibv_shared *sh)
 538 {
 539         uint8_t i;
 540
 541         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 542                 mlx5_ipool_destroy(sh->ipool[i]);
 543 }
 544
 545 /**
 546  * Extract pdn of PD object using DV API.
 547  *
 548  * @param[in] pd
 549  *   Pointer to the verbs PD object.
 550  * @param[out] pdn
 551  *   Pointer to the PD object number variable.
 552  *
 553  * @return
 554  *   0 on success, error value otherwise.
 555  */
 556 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 557 static int
 558 mlx5_get_pdn(struct ibv_pd *pd __rte_unused, uint32_t *pdn __rte_unused)
 559 {
 560         struct mlx5dv_obj obj;
 561         struct mlx5dv_pd pd_info;
 562         int ret = 0;
 563
 564         obj.pd.in = pd;
 565         obj.pd.out = &pd_info;
 566         ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);
 567         if (ret) {
 568                 DRV_LOG(DEBUG, "Fail to get PD object info");
 569                 return ret;
 570         }
 571         *pdn = pd_info.pdn;
 572         return 0;
 573 }
 574 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
 575
 576 static int
 577 mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config)
 578 {
 579         char *env;
 580         int value;
 581
 582         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 583         /* Get environment variable to store. */
 584         env = getenv(MLX5_SHUT_UP_BF);
 585         value = env ? !!strcmp(env, "0") : MLX5_ARG_UNSET;
 586         if (config->dbnc == MLX5_ARG_UNSET)
 587                 setenv(MLX5_SHUT_UP_BF, MLX5_SHUT_UP_BF_DEFAULT, 1);
 588         else
 589                 setenv(MLX5_SHUT_UP_BF,
 590                        config->dbnc == MLX5_TXDB_NCACHED ? "1" : "0", 1);
 591         return value;
 592 }
 593
 594 static void
 595 mlx5_restore_doorbell_mapping_env(int value)
 596 {
 597         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 598         /* Restore the original environment variable state. */
 599         if (value == MLX5_ARG_UNSET)
 600                 unsetenv(MLX5_SHUT_UP_BF);
 601         else
 602                 setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1);
 603 }
 604
 605 /**
 606  * Allocate shared IB device context. If there is multiport device the
 607  * master and representors will share this context, if there is single
 608  * port dedicated IB device, the context will be used by only given
 609  * port due to unification.
 610  *
 611  * Routine first searches the context for the specified IB device name,
 612  * if found the shared context assumed and reference counter is incremented.
 613  * If no context found the new one is created and initialized with specified
 614  * IB device context and parameters.
 615  *
 616  * @param[in] spawn
 617  *   Pointer to the IB device attributes (name, port, etc).
 618  * @param[in] config
 619  *   Pointer to device configuration structure.
 620  *
 621  * @return
 622  *   Pointer to mlx5_ibv_shared object on success,
 623  *   otherwise NULL and rte_errno is set.
 624  */
 625 static struct mlx5_ibv_shared *
 626 mlx5_alloc_shared_ibctx(const struct mlx5_dev_spawn_data *spawn,
 627                         const struct mlx5_dev_config *config)
 628 {
 629         struct mlx5_ibv_shared *sh;
 630         int dbmap_env;
 631         int err = 0;
 632         uint32_t i;
 633 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 634         struct mlx5_devx_tis_attr tis_attr = { 0 };
 635 #endif
 636
 637         MLX5_ASSERT(spawn);
 638         /* Secondary process should not create the shared context. */
 639         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 640         pthread_mutex_lock(&mlx5_ibv_list_mutex);
 641         /* Search for IB context by device name. */
 642         LIST_FOREACH(sh, &mlx5_ibv_list, next) {
 643                 if (!strcmp(sh->ibdev_name, spawn->ibv_dev->name)) {
 644                         sh->refcnt++;
 645                         goto exit;
 646                 }
 647         }
 648         /* No device found, we have to create new shared context. */
 649         MLX5_ASSERT(spawn->max_port);
 650         sh = rte_zmalloc("ethdev shared ib context",
 651                          sizeof(struct mlx5_ibv_shared) +
 652                          spawn->max_port *
 653                          sizeof(struct mlx5_ibv_shared_port),
 654                          RTE_CACHE_LINE_SIZE);
 655         if (!sh) {
 656                 DRV_LOG(ERR, "shared context allocation failure");
 657                 rte_errno  = ENOMEM;
 658                 goto exit;
 659         }
 660         /*
 661          * Configure environment variable "MLX5_BF_SHUT_UP"
 662          * before the device creation. The rdma_core library
 663          * checks the variable at device creation and
 664          * stores the result internally.
 665          */
 666         dbmap_env = mlx5_config_doorbell_mapping_env(config);
 667         /* Try to open IB device with DV first, then usual Verbs. */
 668         errno = 0;
 669         sh->ctx = mlx5_glue->dv_open_device(spawn->ibv_dev);
 670         if (sh->ctx) {
 671                 sh->devx = 1;
 672                 DRV_LOG(DEBUG, "DevX is supported");
 673                 /* The device is created, no need for environment. */
 674                 mlx5_restore_doorbell_mapping_env(dbmap_env);
 675         } else {
 676                 /* The environment variable is still configured. */
 677                 sh->ctx = mlx5_glue->open_device(spawn->ibv_dev);
 678                 err = errno ? errno : ENODEV;
 679                 /*
 680                  * The environment variable is not needed anymore,
 681                  * all device creation attempts are completed.
 682                  */
 683                 mlx5_restore_doorbell_mapping_env(dbmap_env);
 684                 if (!sh->ctx)
 685                         goto error;
 686                 DRV_LOG(DEBUG, "DevX is NOT supported");
 687         }
 688         err = mlx5_glue->query_device_ex(sh->ctx, NULL, &sh->device_attr);
 689         if (err) {
 690                 DRV_LOG(DEBUG, "ibv_query_device_ex() failed");
 691                 goto error;
 692         }
 693         sh->refcnt = 1;
 694         sh->max_port = spawn->max_port;
 695         strncpy(sh->ibdev_name, sh->ctx->device->name,
 696                 sizeof(sh->ibdev_name));
 697         strncpy(sh->ibdev_path, sh->ctx->device->ibdev_path,
 698                 sizeof(sh->ibdev_path));
 699         pthread_mutex_init(&sh->intr_mutex, NULL);
 700         /*
 701          * Setting port_id to max unallowed value means
 702          * there is no interrupt subhandler installed for
 703          * the given port index i.
 704          */
 705         for (i = 0; i < sh->max_port; i++) {
 706                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 707                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
 708         }
 709         sh->pd = mlx5_glue->alloc_pd(sh->ctx);
 710         if (sh->pd == NULL) {
 711                 DRV_LOG(ERR, "PD allocation failure");
 712                 err = ENOMEM;
 713                 goto error;
 714         }
 715 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 716         if (sh->devx) {
 717                 err = mlx5_get_pdn(sh->pd, &sh->pdn);
 718                 if (err) {
 719                         DRV_LOG(ERR, "Fail to extract pdn from PD");
 720                         goto error;
 721                 }
 722                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
 723                 if (!sh->td) {
 724                         DRV_LOG(ERR, "TD allocation failure");
 725                         err = ENOMEM;
 726                         goto error;
 727                 }
 728                 tis_attr.transport_domain = sh->td->id;
 729                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
 730                 if (!sh->tis) {
 731                         DRV_LOG(ERR, "TIS allocation failure");
 732                         err = ENOMEM;
 733                         goto error;
 734                 }
 735         }
 736         sh->flow_id_pool = mlx5_flow_id_pool_alloc(UINT32_MAX);
 737         if (!sh->flow_id_pool) {
 738                 DRV_LOG(ERR, "can't create flow id pool");
 739                 err = ENOMEM;
 740                 goto error;
 741         }
 742 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
 743         /*
 744          * Once the device is added to the list of memory event
 745          * callback, its global MR cache table cannot be expanded
 746          * on the fly because of deadlock. If it overflows, lookup
 747          * should be done by searching MR list linearly, which is slow.
 748          *
 749          * At this point the device is not added to the memory
 750          * event list yet, context is just being created.
 751          */
 752         err = mlx5_mr_btree_init(&sh->share_cache.cache,
 753                                  MLX5_MR_BTREE_CACHE_N * 2,
 754                                  spawn->pci_dev->device.numa_node);
 755         if (err) {
 756                 err = rte_errno;
 757                 goto error;
 758         }
 759         mlx5_flow_counters_mng_init(sh);
 760         mlx5_flow_ipool_create(sh, config);
 761         /* Add device to memory callback list. */
 762         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 763         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
 764                          sh, mem_event_cb);
 765         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 766         /* Add context to the global device list. */
 767         LIST_INSERT_HEAD(&mlx5_ibv_list, sh, next);
 768 exit:
 769         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 770         return sh;
 771 error:
 772         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 773         MLX5_ASSERT(sh);
 774         if (sh->tis)
 775                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 776         if (sh->td)
 777                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 778         if (sh->pd)
 779                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 780         if (sh->ctx)
 781                 claim_zero(mlx5_glue->close_device(sh->ctx));
 782         if (sh->flow_id_pool)
 783                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 784         rte_free(sh);
 785         MLX5_ASSERT(err > 0);
 786         rte_errno = err;
 787         return NULL;
 788 }
 789
 790 /**
 791  * Free shared IB device context. Decrement counter and if zero free
 792  * all allocated resources and close handles.
 793  *
 794  * @param[in] sh
 795  *   Pointer to mlx5_ibv_shared object to free
 796  */
 797 static void
 798 mlx5_free_shared_ibctx(struct mlx5_ibv_shared *sh)
 799 {
 800         pthread_mutex_lock(&mlx5_ibv_list_mutex);
 801 #ifdef RTE_LIBRTE_MLX5_DEBUG
 802         /* Check the object presence in the list. */
 803         struct mlx5_ibv_shared *lctx;
 804
 805         LIST_FOREACH(lctx, &mlx5_ibv_list, next)
 806                 if (lctx == sh)
 807                         break;
 808         MLX5_ASSERT(lctx);
 809         if (lctx != sh) {
 810                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
 811                 goto exit;
 812         }
 813 #endif
 814         MLX5_ASSERT(sh);
 815         MLX5_ASSERT(sh->refcnt);
 816         /* Secondary process should not free the shared context. */
 817         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 818         if (--sh->refcnt)
 819                 goto exit;
 820         /* Remove from memory callback device list. */
 821         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 822         LIST_REMOVE(sh, mem_event_cb);
 823         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 824         /* Release created Memory Regions. */
 825         mlx5_mr_release_cache(&sh->share_cache);
 826         /* Remove context from the global device list. */
 827         LIST_REMOVE(sh, next);
 828         /*
 829          *  Ensure there is no async event handler installed.
 830          *  Only primary process handles async device events.
 831          **/
 832         mlx5_flow_counters_mng_close(sh);
 833         mlx5_flow_ipool_destroy(sh);
 834         MLX5_ASSERT(!sh->intr_cnt);
 835         if (sh->intr_cnt)
 836                 mlx5_intr_callback_unregister
 837                         (&sh->intr_handle, mlx5_dev_interrupt_handler, sh);
 838 #ifdef HAVE_MLX5_DEVX_ASYNC_SUPPORT
 839         if (sh->devx_intr_cnt) {
 840                 if (sh->intr_handle_devx.fd)
 841                         rte_intr_callback_unregister(&sh->intr_handle_devx,
 842                                           mlx5_dev_interrupt_handler_devx, sh);
 843                 if (sh->devx_comp)
 844                         mlx5dv_devx_destroy_cmd_comp(sh->devx_comp);
 845         }
 846 #endif
 847         pthread_mutex_destroy(&sh->intr_mutex);
 848         if (sh->pd)
 849                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 850         if (sh->tis)
 851                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 852         if (sh->td)
 853                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 854         if (sh->ctx)
 855                 claim_zero(mlx5_glue->close_device(sh->ctx));
 856         if (sh->flow_id_pool)
 857                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 858         rte_free(sh);
 859 exit:
 860         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 861 }
 862
 863 /**
 864  * Destroy table hash list and all the root entries per domain.
 865  *
 866  * @param[in] priv
 867  *   Pointer to the private device data structure.
 868  */
 869 static void
 870 mlx5_free_table_hash_list(struct mlx5_priv *priv)
 871 {
 872         struct mlx5_ibv_shared *sh = priv->sh;
 873         struct mlx5_flow_tbl_data_entry *tbl_data;
 874         union mlx5_flow_tbl_key table_key = {
 875                 {
 876                         .table_id = 0,
 877                         .reserved = 0,
 878                         .domain = 0,
 879                         .direction = 0,
 880                 }
 881         };
 882         struct mlx5_hlist_entry *pos;
 883
 884         if (!sh->flow_tbls)
 885                 return;
 886         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 887         if (pos) {
 888                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 889                                         entry);
 890                 MLX5_ASSERT(tbl_data);
 891                 mlx5_hlist_remove(sh->flow_tbls, pos);
 892                 rte_free(tbl_data);
 893         }
 894         table_key.direction = 1;
 895         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 896         if (pos) {
 897                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 898                                         entry);
 899                 MLX5_ASSERT(tbl_data);
 900                 mlx5_hlist_remove(sh->flow_tbls, pos);
 901                 rte_free(tbl_data);
 902         }
 903         table_key.direction = 0;
 904         table_key.domain = 1;
 905         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 906         if (pos) {
 907                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 908                                         entry);
 909                 MLX5_ASSERT(tbl_data);
 910                 mlx5_hlist_remove(sh->flow_tbls, pos);
 911                 rte_free(tbl_data);
 912         }
 913         mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
 914 }
 915
 916 /**
 917  * Initialize flow table hash list and create the root tables entry
 918  * for each domain.
 919  *
 920  * @param[in] priv
 921  *   Pointer to the private device data structure.
 922  *
 923  * @return
 924  *   Zero on success, positive error code otherwise.
 925  */
 926 static int
 927 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
 928 {
 929         struct mlx5_ibv_shared *sh = priv->sh;
 930         char s[MLX5_HLIST_NAMESIZE];
 931         int err = 0;
 932
 933         MLX5_ASSERT(sh);
 934         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
 935         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
 936         if (!sh->flow_tbls) {
 937                 DRV_LOG(ERR, "flow tables with hash creation failed.\n");
 938                 err = ENOMEM;
 939                 return err;
 940         }
 941 #ifndef HAVE_MLX5DV_DR
 942         /*
 943          * In case we have not DR support, the zero tables should be created
 944          * because DV expect to see them even if they cannot be created by
 945          * RDMA-CORE.
 946          */
 947         union mlx5_flow_tbl_key table_key = {
 948                 {
 949                         .table_id = 0,
 950                         .reserved = 0,
 951                         .domain = 0,
 952                         .direction = 0,
 953                 }
 954         };
 955         struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL,
 956                                                           sizeof(*tbl_data), 0);
 957
 958         if (!tbl_data) {
 959                 err = ENOMEM;
 960                 goto error;
 961         }
 962         tbl_data->entry.key = table_key.v64;
 963         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 964         if (err)
 965                 goto error;
 966         rte_atomic32_init(&tbl_data->tbl.refcnt);
 967         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 968         table_key.direction = 1;
 969         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 970         if (!tbl_data) {
 971                 err = ENOMEM;
 972                 goto error;
 973         }
 974         tbl_data->entry.key = table_key.v64;
 975         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 976         if (err)
 977                 goto error;
 978         rte_atomic32_init(&tbl_data->tbl.refcnt);
 979         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 980         table_key.direction = 0;
 981         table_key.domain = 1;
 982         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 983         if (!tbl_data) {
 984                 err = ENOMEM;
 985                 goto error;
 986         }
 987         tbl_data->entry.key = table_key.v64;
 988         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 989         if (err)
 990                 goto error;
 991         rte_atomic32_init(&tbl_data->tbl.refcnt);
 992         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 993         return err;
 994 error:
 995         mlx5_free_table_hash_list(priv);
 996 #endif /* HAVE_MLX5DV_DR */
 997         return err;
 998 }
 999
1000 /**
1001  * Initialize DR related data within private structure.
1002  * Routine checks the reference counter and does actual
1003  * resources creation/initialization only if counter is zero.
1004  *
1005  * @param[in] priv
1006  *   Pointer to the private device data structure.
1007  *
1008  * @return
1009  *   Zero on success, positive error code otherwise.
1010  */
1011 static int
1012 mlx5_alloc_shared_dr(struct mlx5_priv *priv)
1013 {
1014         struct mlx5_ibv_shared *sh = priv->sh;
1015         char s[MLX5_HLIST_NAMESIZE];
1016         int err = 0;
1017
1018         if (!sh->flow_tbls)
1019                 err = mlx5_alloc_table_hash_list(priv);
1020         else
1021                 DRV_LOG(DEBUG, "sh->flow_tbls[%p] already created, reuse\n",
1022                         (void *)sh->flow_tbls);
1023         if (err)
1024                 return err;
1025         /* Create tags hash list table. */
1026         snprintf(s, sizeof(s), "%s_tags", sh->ibdev_name);
1027         sh->tag_table = mlx5_hlist_create(s, MLX5_TAGS_HLIST_ARRAY_SIZE);
1028         if (!sh->tag_table) {
1029                 DRV_LOG(ERR, "tags with hash creation failed.\n");
1030                 err = ENOMEM;
1031                 goto error;
1032         }
1033 #ifdef HAVE_MLX5DV_DR
1034         void *domain;
1035
1036         if (sh->dv_refcnt) {
1037                 /* Shared DV/DR structures is already initialized. */
1038                 sh->dv_refcnt++;
1039                 priv->dr_shared = 1;
1040                 return 0;
1041         }
1042         /* Reference counter is zero, we should initialize structures. */
1043         domain = mlx5_glue->dr_create_domain(sh->ctx,
1044                                              MLX5DV_DR_DOMAIN_TYPE_NIC_RX);
1045         if (!domain) {
1046                 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed");
1047                 err = errno;
1048                 goto error;
1049         }
1050         sh->rx_domain = domain;
1051         domain = mlx5_glue->dr_create_domain(sh->ctx,
1052                                              MLX5DV_DR_DOMAIN_TYPE_NIC_TX);
1053         if (!domain) {
1054                 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed");
1055                 err = errno;
1056                 goto error;
1057         }
1058         pthread_mutex_init(&sh->dv_mutex, NULL);
1059         sh->tx_domain = domain;
1060 #ifdef HAVE_MLX5DV_DR_ESWITCH
1061         if (priv->config.dv_esw_en) {
1062                 domain  = mlx5_glue->dr_create_domain
1063                         (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB);
1064                 if (!domain) {
1065                         DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed");
1066                         err = errno;
1067                         goto error;
1068                 }
1069                 sh->fdb_domain = domain;
1070                 sh->esw_drop_action = mlx5_glue->dr_create_flow_action_drop();
1071         }
1072 #endif
1073         sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan();
1074 #endif /* HAVE_MLX5DV_DR */
1075         sh->dv_refcnt++;
1076         priv->dr_shared = 1;
1077         return 0;
1078 error:
1079         /* Rollback the created objects. */
1080         if (sh->rx_domain) {
1081                 mlx5_glue->dr_destroy_domain(sh->rx_domain);
1082                 sh->rx_domain = NULL;
1083         }
1084         if (sh->tx_domain) {
1085                 mlx5_glue->dr_destroy_domain(sh->tx_domain);
1086                 sh->tx_domain = NULL;
1087         }
1088         if (sh->fdb_domain) {
1089                 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
1090                 sh->fdb_domain = NULL;
1091         }
1092         if (sh->esw_drop_action) {
1093                 mlx5_glue->destroy_flow_action(sh->esw_drop_action);
1094                 sh->esw_drop_action = NULL;
1095         }
1096         if (sh->pop_vlan_action) {
1097                 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
1098                 sh->pop_vlan_action = NULL;
1099         }
1100         if (sh->tag_table) {
1101                 /* tags should be destroyed with flow before. */
1102                 mlx5_hlist_destroy(sh->tag_table, NULL, NULL);
1103                 sh->tag_table = NULL;
1104         }
1105         mlx5_free_table_hash_list(priv);
1106         return err;
1107 }
1108
1109 /**
1110  * Destroy DR related data within private structure.
1111  *
1112  * @param[in] priv
1113  *   Pointer to the private device data structure.
1114  */
1115 static void
1116 mlx5_free_shared_dr(struct mlx5_priv *priv)
1117 {
1118         struct mlx5_ibv_shared *sh;
1119
1120         if (!priv->dr_shared)
1121                 return;
1122         priv->dr_shared = 0;
1123         sh = priv->sh;
1124         MLX5_ASSERT(sh);
1125 #ifdef HAVE_MLX5DV_DR
1126         MLX5_ASSERT(sh->dv_refcnt);
1127         if (sh->dv_refcnt && --sh->dv_refcnt)
1128                 return;
1129         if (sh->rx_domain) {
1130                 mlx5_glue->dr_destroy_domain(sh->rx_domain);
1131                 sh->rx_domain = NULL;
1132         }
1133         if (sh->tx_domain) {
1134                 mlx5_glue->dr_destroy_domain(sh->tx_domain);
1135                 sh->tx_domain = NULL;
1136         }
1137 #ifdef HAVE_MLX5DV_DR_ESWITCH
1138         if (sh->fdb_domain) {
1139                 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
1140                 sh->fdb_domain = NULL;
1141         }
1142         if (sh->esw_drop_action) {
1143                 mlx5_glue->destroy_flow_action(sh->esw_drop_action);
1144                 sh->esw_drop_action = NULL;
1145         }
1146 #endif
1147         if (sh->pop_vlan_action) {
1148                 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
1149                 sh->pop_vlan_action = NULL;
1150         }
1151         pthread_mutex_destroy(&sh->dv_mutex);
1152 #endif /* HAVE_MLX5DV_DR */
1153         if (sh->tag_table) {
1154                 /* tags should be destroyed with flow before. */
1155                 mlx5_hlist_destroy(sh->tag_table, NULL, NULL);
1156                 sh->tag_table = NULL;
1157         }
1158         mlx5_free_table_hash_list(priv);
1159 }
1160
1161 /**
1162  * Initialize shared data between primary and secondary process.
1163  *
1164  * A memzone is reserved by primary process and secondary processes attach to
1165  * the memzone.
1166  *
1167  * @return
1168  *   0 on success, a negative errno value otherwise and rte_errno is set.
1169  */
1170 static int
1171 mlx5_init_shared_data(void)
1172 {
1173         const struct rte_memzone *mz;
1174         int ret = 0;
1175
1176         rte_spinlock_lock(&mlx5_shared_data_lock);
1177         if (mlx5_shared_data == NULL) {
1178                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
1179                         /* Allocate shared memory. */
1180                         mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
1181                                                  sizeof(*mlx5_shared_data),
1182                                                  SOCKET_ID_ANY, 0);
1183                         if (mz == NULL) {
1184                                 DRV_LOG(ERR,
1185                                         "Cannot allocate mlx5 shared data");
1186                                 ret = -rte_errno;
1187                                 goto error;
1188                         }
1189                         mlx5_shared_data = mz->addr;
1190                         memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
1191                         rte_spinlock_init(&mlx5_shared_data->lock);
1192                 } else {
1193                         /* Lookup allocated shared memory. */
1194                         mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
1195                         if (mz == NULL) {
1196                                 DRV_LOG(ERR,
1197                                         "Cannot attach mlx5 shared data");
1198                                 ret = -rte_errno;
1199                                 goto error;
1200                         }
1201                         mlx5_shared_data = mz->addr;
1202                         memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
1203                 }
1204         }
1205 error:
1206         rte_spinlock_unlock(&mlx5_shared_data_lock);
1207         return ret;
1208 }
1209
1210 /**
1211  * Retrieve integer value from environment variable.
1212  *
1213  * @param[in] name
1214  *   Environment variable name.
1215  *
1216  * @return
1217  *   Integer value, 0 if the variable is not set.
1218  */
1219 int
1220 mlx5_getenv_int(const char *name)
1221 {
1222         const char *val = getenv(name);
1223
1224         if (val == NULL)
1225                 return 0;
1226         return atoi(val);
1227 }
1228
1229 /**
1230  * Verbs callback to allocate a memory. This function should allocate the space
1231  * according to the size provided residing inside a huge page.
1232  * Please note that all allocation must respect the alignment from libmlx5
1233  * (i.e. currently sysconf(_SC_PAGESIZE)).
1234  *
1235  * @param[in] size
1236  *   The size in bytes of the memory to allocate.
1237  * @param[in] data
1238  *   A pointer to the callback data.
1239  *
1240  * @return
1241  *   Allocated buffer, NULL otherwise and rte_errno is set.
1242  */
1243 static void *
1244 mlx5_alloc_verbs_buf(size_t size, void *data)
1245 {
1246         struct mlx5_priv *priv = data;
1247         void *ret;
1248         size_t alignment = sysconf(_SC_PAGESIZE);
1249         unsigned int socket = SOCKET_ID_ANY;
1250
1251         if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
1252                 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
1253
1254                 socket = ctrl->socket;
1255         } else if (priv->verbs_alloc_ctx.type ==
1256                    MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
1257                 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
1258
1259                 socket = ctrl->socket;
1260         }
1261         MLX5_ASSERT(data != NULL);
1262         ret = rte_malloc_socket(__func__, size, alignment, socket);
1263         if (!ret && size)
1264                 rte_errno = ENOMEM;
1265         return ret;
1266 }
1267
1268 /**
1269  * Verbs callback to free a memory.
1270  *
1271  * @param[in] ptr
1272  *   A pointer to the memory to free.
1273  * @param[in] data
1274  *   A pointer to the callback data.
1275  */
1276 static void
1277 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
1278 {
1279         MLX5_ASSERT(data != NULL);
1280         rte_free(ptr);
1281 }
1282
1283 /**
1284  * DPDK callback to add udp tunnel port
1285  *
1286  * @param[in] dev
1287  *   A pointer to eth_dev
1288  * @param[in] udp_tunnel
1289  *   A pointer to udp tunnel
1290  *
1291  * @return
1292  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1293  */
1294 int
1295 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1296                          struct rte_eth_udp_tunnel *udp_tunnel)
1297 {
1298         MLX5_ASSERT(udp_tunnel != NULL);
1299         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1300             udp_tunnel->udp_port == 4789)
1301                 return 0;
1302         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1303             udp_tunnel->udp_port == 4790)
1304                 return 0;
1305         return -ENOTSUP;
1306 }
1307
1308 /**
1309  * Initialize process private data structure.
1310  *
1311  * @param dev
1312  *   Pointer to Ethernet device structure.
1313  *
1314  * @return
1315  *   0 on success, a negative errno value otherwise and rte_errno is set.
1316  */
1317 int
1318 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1319 {
1320         struct mlx5_priv *priv = dev->data->dev_private;
1321         struct mlx5_proc_priv *ppriv;
1322         size_t ppriv_size;
1323
1324         /*
1325          * UAR register table follows the process private structure. BlueFlame
1326          * registers for Tx queues are stored in the table.
1327          */
1328         ppriv_size =
1329                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1330         ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
1331                                   RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1332         if (!ppriv) {
1333                 rte_errno = ENOMEM;
1334                 return -rte_errno;
1335         }
1336         ppriv->uar_table_sz = ppriv_size;
1337         dev->process_private = ppriv;
1338         return 0;
1339 }
1340
1341 /**
1342  * Un-initialize process private data structure.
1343  *
1344  * @param dev
1345  *   Pointer to Ethernet device structure.
1346  */
1347 static void
1348 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1349 {
1350         if (!dev->process_private)
1351                 return;
1352         rte_free(dev->process_private);
1353         dev->process_private = NULL;
1354 }
1355
1356 /**
1357  * DPDK callback to close the device.
1358  *
1359  * Destroy all queues and objects, free memory.
1360  *
1361  * @param dev
1362  *   Pointer to Ethernet device structure.
1363  */
1364 static void
1365 mlx5_dev_close(struct rte_eth_dev *dev)
1366 {
1367         struct mlx5_priv *priv = dev->data->dev_private;
1368         unsigned int i;
1369         int ret;
1370
1371         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1372                 dev->data->port_id,
1373                 ((priv->sh->ctx != NULL) ? priv->sh->ctx->device->name : ""));
1374         /* In case mlx5_dev_stop() has not been called. */
1375         mlx5_dev_interrupt_handler_uninstall(dev);
1376         mlx5_dev_interrupt_handler_devx_uninstall(dev);
1377         /*
1378          * If default mreg copy action is removed at the stop stage,
1379          * the search will return none and nothing will be done anymore.
1380          */
1381         mlx5_flow_stop_default(dev);
1382         mlx5_traffic_disable(dev);
1383         /*
1384          * If all the flows are already flushed in the device stop stage,
1385          * then this will return directly without any action.
1386          */
1387         mlx5_flow_list_flush(dev, &priv->flows, true);
1388         mlx5_flow_meter_flush(dev, NULL);
1389         /* Free the intermediate buffers for flow creation. */
1390         mlx5_flow_free_intermediate(dev);
1391         /* Prevent crashes when queues are still in use. */
1392         dev->rx_pkt_burst = removed_rx_burst;
1393         dev->tx_pkt_burst = removed_tx_burst;
1394         rte_wmb();
1395         /* Disable datapath on secondary process. */
1396         mlx5_mp_req_stop_rxtx(dev);
1397         if (priv->rxqs != NULL) {
1398                 /* XXX race condition if mlx5_rx_burst() is still running. */
1399                 usleep(1000);
1400                 for (i = 0; (i != priv->rxqs_n); ++i)
1401                         mlx5_rxq_release(dev, i);
1402                 priv->rxqs_n = 0;
1403                 priv->rxqs = NULL;
1404         }
1405         if (priv->txqs != NULL) {
1406                 /* XXX race condition if mlx5_tx_burst() is still running. */
1407                 usleep(1000);
1408                 for (i = 0; (i != priv->txqs_n); ++i)
1409                         mlx5_txq_release(dev, i);
1410                 priv->txqs_n = 0;
1411                 priv->txqs = NULL;
1412         }
1413         mlx5_proc_priv_uninit(dev);
1414         if (priv->mreg_cp_tbl)
1415                 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1416         mlx5_mprq_free_mp(dev);
1417         mlx5_free_shared_dr(priv);
1418         if (priv->rss_conf.rss_key != NULL)
1419                 rte_free(priv->rss_conf.rss_key);
1420         if (priv->reta_idx != NULL)
1421                 rte_free(priv->reta_idx);
1422         if (priv->config.vf)
1423                 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1424                                        dev->data->mac_addrs,
1425                                        MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1426         if (priv->nl_socket_route >= 0)
1427                 close(priv->nl_socket_route);
1428         if (priv->nl_socket_rdma >= 0)
1429                 close(priv->nl_socket_rdma);
1430         if (priv->vmwa_context)
1431                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1432         ret = mlx5_hrxq_verify(dev);
1433         if (ret)
1434                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1435                         dev->data->port_id);
1436         ret = mlx5_ind_table_obj_verify(dev);
1437         if (ret)
1438                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1439                         dev->data->port_id);
1440         ret = mlx5_rxq_obj_verify(dev);
1441         if (ret)
1442                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1443                         dev->data->port_id);
1444         ret = mlx5_rxq_verify(dev);
1445         if (ret)
1446                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1447                         dev->data->port_id);
1448         ret = mlx5_txq_obj_verify(dev);
1449         if (ret)
1450                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1451                         dev->data->port_id);
1452         ret = mlx5_txq_verify(dev);
1453         if (ret)
1454                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1455                         dev->data->port_id);
1456         ret = mlx5_flow_verify(dev);
1457         if (ret)
1458                 DRV_LOG(WARNING, "port %u some flows still remain",
1459                         dev->data->port_id);
1460         if (priv->sh) {
1461                 /*
1462                  * Free the shared context in last turn, because the cleanup
1463                  * routines above may use some shared fields, like
1464                  * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1465                  * ifindex if Netlink fails.
1466                  */
1467                 mlx5_free_shared_ibctx(priv->sh);
1468                 priv->sh = NULL;
1469         }
1470         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1471                 unsigned int c = 0;
1472                 uint16_t port_id;
1473
1474                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1475                         struct mlx5_priv *opriv =
1476                                 rte_eth_devices[port_id].data->dev_private;
1477
1478                         if (!opriv ||
1479                             opriv->domain_id != priv->domain_id ||
1480                             &rte_eth_devices[port_id] == dev)
1481                                 continue;
1482                         ++c;
1483                         break;
1484                 }
1485                 if (!c)
1486                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1487         }
1488         memset(priv, 0, sizeof(*priv));
1489         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1490         /*
1491          * Reset mac_addrs to NULL such that it is not freed as part of
1492          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1493          * it is freed when dev_private is freed.
1494          */
1495         dev->data->mac_addrs = NULL;
1496 }
1497
1498 const struct eth_dev_ops mlx5_dev_ops = {
1499         .dev_configure = mlx5_dev_configure,
1500         .dev_start = mlx5_dev_start,
1501         .dev_stop = mlx5_dev_stop,
1502         .dev_set_link_down = mlx5_set_link_down,
1503         .dev_set_link_up = mlx5_set_link_up,
1504         .dev_close = mlx5_dev_close,
1505         .promiscuous_enable = mlx5_promiscuous_enable,
1506         .promiscuous_disable = mlx5_promiscuous_disable,
1507         .allmulticast_enable = mlx5_allmulticast_enable,
1508         .allmulticast_disable = mlx5_allmulticast_disable,
1509         .link_update = mlx5_link_update,
1510         .stats_get = mlx5_stats_get,
1511         .stats_reset = mlx5_stats_reset,
1512         .xstats_get = mlx5_xstats_get,
1513         .xstats_reset = mlx5_xstats_reset,
1514         .xstats_get_names = mlx5_xstats_get_names,
1515         .fw_version_get = mlx5_fw_version_get,
1516         .dev_infos_get = mlx5_dev_infos_get,
1517         .read_clock = mlx5_read_clock,
1518         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1519         .vlan_filter_set = mlx5_vlan_filter_set,
1520         .rx_queue_setup = mlx5_rx_queue_setup,
1521         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1522         .tx_queue_setup = mlx5_tx_queue_setup,
1523         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1524         .rx_queue_release = mlx5_rx_queue_release,
1525         .tx_queue_release = mlx5_tx_queue_release,
1526         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1527         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1528         .mac_addr_remove = mlx5_mac_addr_remove,
1529         .mac_addr_add = mlx5_mac_addr_add,
1530         .mac_addr_set = mlx5_mac_addr_set,
1531         .set_mc_addr_list = mlx5_set_mc_addr_list,
1532         .mtu_set = mlx5_dev_set_mtu,
1533         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1534         .vlan_offload_set = mlx5_vlan_offload_set,
1535         .reta_update = mlx5_dev_rss_reta_update,
1536         .reta_query = mlx5_dev_rss_reta_query,
1537         .rss_hash_update = mlx5_rss_hash_update,
1538         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1539         .filter_ctrl = mlx5_dev_filter_ctrl,
1540         .rx_descriptor_status = mlx5_rx_descriptor_status,
1541         .tx_descriptor_status = mlx5_tx_descriptor_status,
1542         .rxq_info_get = mlx5_rxq_info_get,
1543         .txq_info_get = mlx5_txq_info_get,
1544         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1545         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1546         .rx_queue_count = mlx5_rx_queue_count,
1547         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1548         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1549         .is_removed = mlx5_is_removed,
1550         .udp_tunnel_port_add  = mlx5_udp_tunnel_port_add,
1551         .get_module_info = mlx5_get_module_info,
1552         .get_module_eeprom = mlx5_get_module_eeprom,
1553         .hairpin_cap_get = mlx5_hairpin_cap_get,
1554         .mtr_ops_get = mlx5_flow_meter_ops_get,
1555 };
1556
1557 /* Available operations from secondary process. */
1558 static const struct eth_dev_ops mlx5_dev_sec_ops = {
1559         .stats_get = mlx5_stats_get,
1560         .stats_reset = mlx5_stats_reset,
1561         .xstats_get = mlx5_xstats_get,
1562         .xstats_reset = mlx5_xstats_reset,
1563         .xstats_get_names = mlx5_xstats_get_names,
1564         .fw_version_get = mlx5_fw_version_get,
1565         .dev_infos_get = mlx5_dev_infos_get,
1566         .rx_descriptor_status = mlx5_rx_descriptor_status,
1567         .tx_descriptor_status = mlx5_tx_descriptor_status,
1568         .rxq_info_get = mlx5_rxq_info_get,
1569         .txq_info_get = mlx5_txq_info_get,
1570         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1571         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1572         .get_module_info = mlx5_get_module_info,
1573         .get_module_eeprom = mlx5_get_module_eeprom,
1574 };
1575
1576 /* Available operations in flow isolated mode. */
1577 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1578         .dev_configure = mlx5_dev_configure,
1579         .dev_start = mlx5_dev_start,
1580         .dev_stop = mlx5_dev_stop,
1581         .dev_set_link_down = mlx5_set_link_down,
1582         .dev_set_link_up = mlx5_set_link_up,
1583         .dev_close = mlx5_dev_close,
1584         .promiscuous_enable = mlx5_promiscuous_enable,
1585         .promiscuous_disable = mlx5_promiscuous_disable,
1586         .allmulticast_enable = mlx5_allmulticast_enable,
1587         .allmulticast_disable = mlx5_allmulticast_disable,
1588         .link_update = mlx5_link_update,
1589         .stats_get = mlx5_stats_get,
1590         .stats_reset = mlx5_stats_reset,
1591         .xstats_get = mlx5_xstats_get,
1592         .xstats_reset = mlx5_xstats_reset,
1593         .xstats_get_names = mlx5_xstats_get_names,
1594         .fw_version_get = mlx5_fw_version_get,
1595         .dev_infos_get = mlx5_dev_infos_get,
1596         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1597         .vlan_filter_set = mlx5_vlan_filter_set,
1598         .rx_queue_setup = mlx5_rx_queue_setup,
1599         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1600         .tx_queue_setup = mlx5_tx_queue_setup,
1601         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1602         .rx_queue_release = mlx5_rx_queue_release,
1603         .tx_queue_release = mlx5_tx_queue_release,
1604         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1605         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1606         .mac_addr_remove = mlx5_mac_addr_remove,
1607         .mac_addr_add = mlx5_mac_addr_add,
1608         .mac_addr_set = mlx5_mac_addr_set,
1609         .set_mc_addr_list = mlx5_set_mc_addr_list,
1610         .mtu_set = mlx5_dev_set_mtu,
1611         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1612         .vlan_offload_set = mlx5_vlan_offload_set,
1613         .filter_ctrl = mlx5_dev_filter_ctrl,
1614         .rx_descriptor_status = mlx5_rx_descriptor_status,
1615         .tx_descriptor_status = mlx5_tx_descriptor_status,
1616         .rxq_info_get = mlx5_rxq_info_get,
1617         .txq_info_get = mlx5_txq_info_get,
1618         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1619         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1620         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1621         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1622         .is_removed = mlx5_is_removed,
1623         .get_module_info = mlx5_get_module_info,
1624         .get_module_eeprom = mlx5_get_module_eeprom,
1625         .hairpin_cap_get = mlx5_hairpin_cap_get,
1626         .mtr_ops_get = mlx5_flow_meter_ops_get,
1627 };
1628
1629 /**
1630  * Verify and store value for device argument.
1631  *
1632  * @param[in] key
1633  *   Key argument to verify.
1634  * @param[in] val
1635  *   Value associated with key.
1636  * @param opaque
1637  *   User data.
1638  *
1639  * @return
1640  *   0 on success, a negative errno value otherwise and rte_errno is set.
1641  */
1642 static int
1643 mlx5_args_check(const char *key, const char *val, void *opaque)
1644 {
1645         struct mlx5_dev_config *config = opaque;
1646         unsigned long tmp;
1647
1648         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1649         if (!strcmp(MLX5_REPRESENTOR, key))
1650                 return 0;
1651         errno = 0;
1652         tmp = strtoul(val, NULL, 0);
1653         if (errno) {
1654                 rte_errno = errno;
1655                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1656                 return -rte_errno;
1657         }
1658         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1659                 config->cqe_comp = !!tmp;
1660         } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1661                 config->cqe_pad = !!tmp;
1662         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1663                 config->hw_padding = !!tmp;
1664         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1665                 config->mprq.enabled = !!tmp;
1666         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1667                 config->mprq.stride_num_n = tmp;
1668         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1669                 config->mprq.stride_size_n = tmp;
1670         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1671                 config->mprq.max_memcpy_len = tmp;
1672         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1673                 config->mprq.min_rxqs_num = tmp;
1674         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1675                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1676                                  " converted to txq_inline_max", key);
1677                 config->txq_inline_max = tmp;
1678         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1679                 config->txq_inline_max = tmp;
1680         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1681                 config->txq_inline_min = tmp;
1682         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1683                 config->txq_inline_mpw = tmp;
1684         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1685                 config->txqs_inline = tmp;
1686         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1687                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1688         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1689                 config->mps = !!tmp;
1690         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1691                 if (tmp != MLX5_TXDB_CACHED &&
1692                     tmp != MLX5_TXDB_NCACHED &&
1693                     tmp != MLX5_TXDB_HEURISTIC) {
1694                         DRV_LOG(ERR, "invalid Tx doorbell "
1695                                      "mapping parameter");
1696                         rte_errno = EINVAL;
1697                         return -rte_errno;
1698                 }
1699                 config->dbnc = tmp;
1700         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1701                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1702         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1703                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1704                                  " converted to txq_inline_mpw", key);
1705                 config->txq_inline_mpw = tmp;
1706         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1707                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1708         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1709                 config->rx_vec_en = !!tmp;
1710         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1711                 config->l3_vxlan_en = !!tmp;
1712         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1713                 config->vf_nl_en = !!tmp;
1714         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1715                 config->dv_esw_en = !!tmp;
1716         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1717                 config->dv_flow_en = !!tmp;
1718         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1719                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1720                     tmp != MLX5_XMETA_MODE_META16 &&
1721                     tmp != MLX5_XMETA_MODE_META32) {
1722                         DRV_LOG(ERR, "invalid extensive "
1723                                      "metadata parameter");
1724                         rte_errno = EINVAL;
1725                         return -rte_errno;
1726                 }
1727                 config->dv_xmeta_en = tmp;
1728         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1729                 config->mr_ext_memseg_en = !!tmp;
1730         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1731                 config->max_dump_files_num = tmp;
1732         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1733                 config->lro.timeout = tmp;
1734         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1735                 DRV_LOG(DEBUG, "class argument is %s.", val);
1736         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1737                 config->log_hp_size = tmp;
1738         } else {
1739                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1740                 rte_errno = EINVAL;
1741                 return -rte_errno;
1742         }
1743         return 0;
1744 }
1745
1746 /**
1747  * Parse device parameters.
1748  *
1749  * @param config
1750  *   Pointer to device configuration structure.
1751  * @param devargs
1752  *   Device arguments structure.
1753  *
1754  * @return
1755  *   0 on success, a negative errno value otherwise and rte_errno is set.
1756  */
1757 static int
1758 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1759 {
1760         const char **params = (const char *[]){
1761                 MLX5_RXQ_CQE_COMP_EN,
1762                 MLX5_RXQ_CQE_PAD_EN,
1763                 MLX5_RXQ_PKT_PAD_EN,
1764                 MLX5_RX_MPRQ_EN,
1765                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1766                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1767                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1768                 MLX5_RXQS_MIN_MPRQ,
1769                 MLX5_TXQ_INLINE,
1770                 MLX5_TXQ_INLINE_MIN,
1771                 MLX5_TXQ_INLINE_MAX,
1772                 MLX5_TXQ_INLINE_MPW,
1773                 MLX5_TXQS_MIN_INLINE,
1774                 MLX5_TXQS_MAX_VEC,
1775                 MLX5_TXQ_MPW_EN,
1776                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1777                 MLX5_TXQ_MAX_INLINE_LEN,
1778                 MLX5_TX_DB_NC,
1779                 MLX5_TX_VEC_EN,
1780                 MLX5_RX_VEC_EN,
1781                 MLX5_L3_VXLAN_EN,
1782                 MLX5_VF_NL_EN,
1783                 MLX5_DV_ESW_EN,
1784                 MLX5_DV_FLOW_EN,
1785                 MLX5_DV_XMETA_EN,
1786                 MLX5_MR_EXT_MEMSEG_EN,
1787                 MLX5_REPRESENTOR,
1788                 MLX5_MAX_DUMP_FILES_NUM,
1789                 MLX5_LRO_TIMEOUT_USEC,
1790                 MLX5_CLASS_ARG_NAME,
1791                 MLX5_HP_BUF_SIZE,
1792                 NULL,
1793         };
1794         struct rte_kvargs *kvlist;
1795         int ret = 0;
1796         int i;
1797
1798         if (devargs == NULL)
1799                 return 0;
1800         /* Following UGLY cast is done to pass checkpatch. */
1801         kvlist = rte_kvargs_parse(devargs->args, params);
1802         if (kvlist == NULL) {
1803                 rte_errno = EINVAL;
1804                 return -rte_errno;
1805         }
1806         /* Process parameters. */
1807         for (i = 0; (params[i] != NULL); ++i) {
1808                 if (rte_kvargs_count(kvlist, params[i])) {
1809                         ret = rte_kvargs_process(kvlist, params[i],
1810                                                  mlx5_args_check, config);
1811                         if (ret) {
1812                                 rte_errno = EINVAL;
1813                                 rte_kvargs_free(kvlist);
1814                                 return -rte_errno;
1815                         }
1816                 }
1817         }
1818         rte_kvargs_free(kvlist);
1819         return 0;
1820 }
1821
1822 static struct rte_pci_driver mlx5_driver;
1823
1824 /**
1825  * PMD global initialization.
1826  *
1827  * Independent from individual device, this function initializes global
1828  * per-PMD data structures distinguishing primary and secondary processes.
1829  * Hence, each initialization is called once per a process.
1830  *
1831  * @return
1832  *   0 on success, a negative errno value otherwise and rte_errno is set.
1833  */
1834 static int
1835 mlx5_init_once(void)
1836 {
1837         struct mlx5_shared_data *sd;
1838         struct mlx5_local_data *ld = &mlx5_local_data;
1839         int ret = 0;
1840
1841         if (mlx5_init_shared_data())
1842                 return -rte_errno;
1843         sd = mlx5_shared_data;
1844         MLX5_ASSERT(sd);
1845         rte_spinlock_lock(&sd->lock);
1846         switch (rte_eal_process_type()) {
1847         case RTE_PROC_PRIMARY:
1848                 if (sd->init_done)
1849                         break;
1850                 LIST_INIT(&sd->mem_event_cb_list);
1851                 rte_rwlock_init(&sd->mem_event_rwlock);
1852                 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1853                                                 mlx5_mr_mem_event_cb, NULL);
1854                 ret = mlx5_mp_init_primary(MLX5_MP_NAME,
1855                                            mlx5_mp_primary_handle);
1856                 if (ret)
1857                         goto out;
1858                 sd->init_done = true;
1859                 break;
1860         case RTE_PROC_SECONDARY:
1861                 if (ld->init_done)
1862                         break;
1863                 ret = mlx5_mp_init_secondary(MLX5_MP_NAME,
1864                                              mlx5_mp_secondary_handle);
1865                 if (ret)
1866                         goto out;
1867                 ++sd->secondary_cnt;
1868                 ld->init_done = true;
1869                 break;
1870         default:
1871                 break;
1872         }
1873 out:
1874         rte_spinlock_unlock(&sd->lock);
1875         return ret;
1876 }
1877
1878 /**
1879  * Configures the minimal amount of data to inline into WQE
1880  * while sending packets.
1881  *
1882  * - the txq_inline_min has the maximal priority, if this
1883  *   key is specified in devargs
1884  * - if DevX is enabled the inline mode is queried from the
1885  *   device (HCA attributes and NIC vport context if needed).
1886  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1887  *   and none (0 bytes) for other NICs
1888  *
1889  * @param spawn
1890  *   Verbs device parameters (name, port, switch_info) to spawn.
1891  * @param config
1892  *   Device configuration parameters.
1893  */
1894 static void
1895 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1896                     struct mlx5_dev_config *config)
1897 {
1898         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1899                 /* Application defines size of inlined data explicitly. */
1900                 switch (spawn->pci_dev->id.device_id) {
1901                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1902                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1903                         if (config->txq_inline_min <
1904                                        (int)MLX5_INLINE_HSIZE_L2) {
1905                                 DRV_LOG(DEBUG,
1906                                         "txq_inline_mix aligned to minimal"
1907                                         " ConnectX-4 required value %d",
1908                                         (int)MLX5_INLINE_HSIZE_L2);
1909                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1910                         }
1911                         break;
1912                 }
1913                 goto exit;
1914         }
1915         if (config->hca_attr.eth_net_offloads) {
1916                 /* We have DevX enabled, inline mode queried successfully. */
1917                 switch (config->hca_attr.wqe_inline_mode) {
1918                 case MLX5_CAP_INLINE_MODE_L2:
1919                         /* outer L2 header must be inlined. */
1920                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1921                         goto exit;
1922                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1923                         /* No inline data are required by NIC. */
1924                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1925                         config->hw_vlan_insert =
1926                                 config->hca_attr.wqe_vlan_insert;
1927                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1928                         goto exit;
1929                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1930                         /* inline mode is defined by NIC vport context. */
1931                         if (!config->hca_attr.eth_virt)
1932                                 break;
1933                         switch (config->hca_attr.vport_inline_mode) {
1934                         case MLX5_INLINE_MODE_NONE:
1935                                 config->txq_inline_min =
1936                                         MLX5_INLINE_HSIZE_NONE;
1937                                 goto exit;
1938                         case MLX5_INLINE_MODE_L2:
1939                                 config->txq_inline_min =
1940                                         MLX5_INLINE_HSIZE_L2;
1941                                 goto exit;
1942                         case MLX5_INLINE_MODE_IP:
1943                                 config->txq_inline_min =
1944                                         MLX5_INLINE_HSIZE_L3;
1945                                 goto exit;
1946                         case MLX5_INLINE_MODE_TCP_UDP:
1947                                 config->txq_inline_min =
1948                                         MLX5_INLINE_HSIZE_L4;
1949                                 goto exit;
1950                         case MLX5_INLINE_MODE_INNER_L2:
1951                                 config->txq_inline_min =
1952                                         MLX5_INLINE_HSIZE_INNER_L2;
1953                                 goto exit;
1954                         case MLX5_INLINE_MODE_INNER_IP:
1955                                 config->txq_inline_min =
1956                                         MLX5_INLINE_HSIZE_INNER_L3;
1957                                 goto exit;
1958                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
1959                                 config->txq_inline_min =
1960                                         MLX5_INLINE_HSIZE_INNER_L4;
1961                                 goto exit;
1962                         }
1963                 }
1964         }
1965         /*
1966          * We get here if we are unable to deduce
1967          * inline data size with DevX. Try PCI ID
1968          * to determine old NICs.
1969          */
1970         switch (spawn->pci_dev->id.device_id) {
1971         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1972         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1973         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1974         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1975                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1976                 config->hw_vlan_insert = 0;
1977                 break;
1978         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1979         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1980         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1981         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1982                 /*
1983                  * These NICs support VLAN insertion from WQE and
1984                  * report the wqe_vlan_insert flag. But there is the bug
1985                  * and PFC control may be broken, so disable feature.
1986                  */
1987                 config->hw_vlan_insert = 0;
1988                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1989                 break;
1990         default:
1991                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1992                 break;
1993         }
1994 exit:
1995         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1996 }
1997
1998 /**
1999  * Configures the metadata mask fields in the shared context.
2000  *
2001  * @param [in] dev
2002  *   Pointer to Ethernet device.
2003  */
2004 static void
2005 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
2006 {
2007         struct mlx5_priv *priv = dev->data->dev_private;
2008         struct mlx5_ibv_shared *sh = priv->sh;
2009         uint32_t meta, mark, reg_c0;
2010
2011         reg_c0 = ~priv->vport_meta_mask;
2012         switch (priv->config.dv_xmeta_en) {
2013         case MLX5_XMETA_MODE_LEGACY:
2014                 meta = UINT32_MAX;
2015                 mark = MLX5_FLOW_MARK_MASK;
2016                 break;
2017         case MLX5_XMETA_MODE_META16:
2018                 meta = reg_c0 >> rte_bsf32(reg_c0);
2019                 mark = MLX5_FLOW_MARK_MASK;
2020                 break;
2021         case MLX5_XMETA_MODE_META32:
2022                 meta = UINT32_MAX;
2023                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2024                 break;
2025         default:
2026                 meta = 0;
2027                 mark = 0;
2028                 MLX5_ASSERT(false);
2029                 break;
2030         }
2031         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2032                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
2033                                  sh->dv_mark_mask, mark);
2034         else
2035                 sh->dv_mark_mask = mark;
2036         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2037                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
2038                                  sh->dv_meta_mask, meta);
2039         else
2040                 sh->dv_meta_mask = meta;
2041         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2042                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
2043                                  sh->dv_meta_mask, reg_c0);
2044         else
2045                 sh->dv_regc0_mask = reg_c0;
2046         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2047         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2048         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2049         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2050 }
2051
2052 /**
2053  * Allocate page of door-bells and register it using DevX API.
2054  *
2055  * @param [in] dev
2056  *   Pointer to Ethernet device.
2057  *
2058  * @return
2059  *   Pointer to new page on success, NULL otherwise.
2060  */
2061 static struct mlx5_devx_dbr_page *
2062 mlx5_alloc_dbr_page(struct rte_eth_dev *dev)
2063 {
2064         struct mlx5_priv *priv = dev->data->dev_private;
2065         struct mlx5_devx_dbr_page *page;
2066
2067         /* Allocate space for door-bell page and management data. */
2068         page = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_devx_dbr_page),
2069                                  RTE_CACHE_LINE_SIZE, dev->device->numa_node);
2070         if (!page) {
2071                 DRV_LOG(ERR, "port %u cannot allocate dbr page",
2072                         dev->data->port_id);
2073                 return NULL;
2074         }
2075         /* Register allocated memory. */
2076         page->umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, page->dbrs,
2077                                               MLX5_DBR_PAGE_SIZE, 0);
2078         if (!page->umem) {
2079                 DRV_LOG(ERR, "port %u cannot umem reg dbr page",
2080                         dev->data->port_id);
2081                 rte_free(page);
2082                 return NULL;
2083         }
2084         return page;
2085 }
2086
2087 /**
2088  * Find the next available door-bell, allocate new page if needed.
2089  *
2090  * @param [in] dev
2091  *   Pointer to Ethernet device.
2092  * @param [out] dbr_page
2093  *   Door-bell page containing the page data.
2094  *
2095  * @return
2096  *   Door-bell address offset on success, a negative error value otherwise.
2097  */
2098 int64_t
2099 mlx5_get_dbr(struct rte_eth_dev *dev, struct mlx5_devx_dbr_page **dbr_page)
2100 {
2101         struct mlx5_priv *priv = dev->data->dev_private;
2102         struct mlx5_devx_dbr_page *page = NULL;
2103         uint32_t i, j;
2104
2105         LIST_FOREACH(page, &priv->dbrpgs, next)
2106                 if (page->dbr_count < MLX5_DBR_PER_PAGE)
2107                         break;
2108         if (!page) { /* No page with free door-bell exists. */
2109                 page = mlx5_alloc_dbr_page(dev);
2110                 if (!page) /* Failed to allocate new page. */
2111                         return (-1);
2112                 LIST_INSERT_HEAD(&priv->dbrpgs, page, next);
2113         }
2114         /* Loop to find bitmap part with clear bit. */
2115         for (i = 0;
2116              i < MLX5_DBR_BITMAP_SIZE && page->dbr_bitmap[i] == UINT64_MAX;
2117              i++)
2118                 ; /* Empty. */
2119         /* Find the first clear bit. */
2120         j = rte_bsf64(~page->dbr_bitmap[i]);
2121         MLX5_ASSERT(i < (MLX5_DBR_PER_PAGE / 64));
2122         page->dbr_bitmap[i] |= (1 << j);
2123         page->dbr_count++;
2124         *dbr_page = page;
2125         return (((i * 64) + j) * sizeof(uint64_t));
2126 }
2127
2128 /**
2129  * Release a door-bell record.
2130  *
2131  * @param [in] dev
2132  *   Pointer to Ethernet device.
2133  * @param [in] umem_id
2134  *   UMEM ID of page containing the door-bell record to release.
2135  * @param [in] offset
2136  *   Offset of door-bell record in page.
2137  *
2138  * @return
2139  *   0 on success, a negative error value otherwise.
2140  */
2141 int32_t
2142 mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id, uint64_t offset)
2143 {
2144         struct mlx5_priv *priv = dev->data->dev_private;
2145         struct mlx5_devx_dbr_page *page = NULL;
2146         int ret = 0;
2147
2148         LIST_FOREACH(page, &priv->dbrpgs, next)
2149                 /* Find the page this address belongs to. */
2150                 if (page->umem->umem_id == umem_id)
2151                         break;
2152         if (!page)
2153                 return -EINVAL;
2154         page->dbr_count--;
2155         if (!page->dbr_count) {
2156                 /* Page not used, free it and remove from list. */
2157                 LIST_REMOVE(page, next);
2158                 if (page->umem)
2159                         ret = -mlx5_glue->devx_umem_dereg(page->umem);
2160                 rte_free(page);
2161         } else {
2162                 /* Mark in bitmap that this door-bell is not in use. */
2163                 offset /= MLX5_DBR_SIZE;
2164                 int i = offset / 64;
2165                 int j = offset % 64;
2166
2167                 page->dbr_bitmap[i] &= ~(1 << j);
2168         }
2169         return ret;
2170 }
2171
2172 int
2173 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2174 {
2175         static const char *const dynf_names[] = {
2176                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2177                 RTE_MBUF_DYNFLAG_METADATA_NAME
2178         };
2179         unsigned int i;
2180
2181         if (n < RTE_DIM(dynf_names))
2182                 return -ENOMEM;
2183         for (i = 0; i < RTE_DIM(dynf_names); i++) {
2184                 if (names[i] == NULL)
2185                         return -EINVAL;
2186                 strcpy(names[i], dynf_names[i]);
2187         }
2188         return RTE_DIM(dynf_names);
2189 }
2190
2191 /**
2192  * Check sibling device configurations.
2193  *
2194  * Sibling devices sharing the Infiniband device context
2195  * should have compatible configurations. This regards
2196  * representors and bonding slaves.
2197  *
2198  * @param priv
2199  *   Private device descriptor.
2200  * @param config
2201  *   Configuration of the device is going to be created.
2202  *
2203  * @return
2204  *   0 on success, EINVAL otherwise
2205  */
2206 static int
2207 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2208                               struct mlx5_dev_config *config)
2209 {
2210         struct mlx5_ibv_shared *sh = priv->sh;
2211         struct mlx5_dev_config *sh_conf = NULL;
2212         uint16_t port_id;
2213
2214         MLX5_ASSERT(sh);
2215         /* Nothing to compare for the single/first device. */
2216         if (sh->refcnt == 1)
2217                 return 0;
2218         /* Find the device with shared context. */
2219         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2220                 struct mlx5_priv *opriv =
2221                         rte_eth_devices[port_id].data->dev_private;
2222
2223                 if (opriv && opriv != priv && opriv->sh == sh) {
2224                         sh_conf = &opriv->config;
2225                         break;
2226                 }
2227         }
2228         if (!sh_conf)
2229                 return 0;
2230         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2231                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2232                              " for shared %s context", sh->ibdev_name);
2233                 rte_errno = EINVAL;
2234                 return rte_errno;
2235         }
2236         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2237                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2238                              " for shared %s context", sh->ibdev_name);
2239                 rte_errno = EINVAL;
2240                 return rte_errno;
2241         }
2242         return 0;
2243 }
2244 /**
2245  * Spawn an Ethernet device from Verbs information.
2246  *
2247  * @param dpdk_dev
2248  *   Backing DPDK device.
2249  * @param spawn
2250  *   Verbs device parameters (name, port, switch_info) to spawn.
2251  * @param config
2252  *   Device configuration parameters.
2253  *
2254  * @return
2255  *   A valid Ethernet device object on success, NULL otherwise and rte_errno
2256  *   is set. The following errors are defined:
2257  *
2258  *   EBUSY: device is not supposed to be spawned.
2259  *   EEXIST: device is already spawned
2260  */
2261 static struct rte_eth_dev *
2262 mlx5_dev_spawn(struct rte_device *dpdk_dev,
2263                struct mlx5_dev_spawn_data *spawn,
2264                struct mlx5_dev_config config)
2265 {
2266         const struct mlx5_switch_info *switch_info = &spawn->info;
2267         struct mlx5_ibv_shared *sh = NULL;
2268         struct ibv_port_attr port_attr;
2269         struct mlx5dv_context dv_attr = { .comp_mask = 0 };
2270         struct rte_eth_dev *eth_dev = NULL;
2271         struct mlx5_priv *priv = NULL;
2272         int err = 0;
2273         unsigned int hw_padding = 0;
2274         unsigned int mps;
2275         unsigned int cqe_comp;
2276         unsigned int cqe_pad = 0;
2277         unsigned int tunnel_en = 0;
2278         unsigned int mpls_en = 0;
2279         unsigned int swp = 0;
2280         unsigned int mprq = 0;
2281         unsigned int mprq_min_stride_size_n = 0;
2282         unsigned int mprq_max_stride_size_n = 0;
2283         unsigned int mprq_min_stride_num_n = 0;
2284         unsigned int mprq_max_stride_num_n = 0;
2285         struct rte_ether_addr mac;
2286         char name[RTE_ETH_NAME_MAX_LEN];
2287         int own_domain_id = 0;
2288         uint16_t port_id;
2289         unsigned int i;
2290 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
2291         struct mlx5dv_devx_port devx_port = { .comp_mask = 0 };
2292 #endif
2293
2294         /* Determine if this port representor is supposed to be spawned. */
2295         if (switch_info->representor && dpdk_dev->devargs) {
2296                 struct rte_eth_devargs eth_da;
2297
2298                 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, &eth_da);
2299                 if (err) {
2300                         rte_errno = -err;
2301                         DRV_LOG(ERR, "failed to process device arguments: %s",
2302                                 strerror(rte_errno));
2303                         return NULL;
2304                 }
2305                 for (i = 0; i < eth_da.nb_representor_ports; ++i)
2306                         if (eth_da.representor_ports[i] ==
2307                             (uint16_t)switch_info->port_name)
2308                                 break;
2309                 if (i == eth_da.nb_representor_ports) {
2310                         rte_errno = EBUSY;
2311                         return NULL;
2312                 }
2313         }
2314         /* Build device name. */
2315         if (spawn->pf_bond <  0) {
2316                 /* Single device. */
2317                 if (!switch_info->representor)
2318                         strlcpy(name, dpdk_dev->name, sizeof(name));
2319                 else
2320                         snprintf(name, sizeof(name), "%s_representor_%u",
2321                                  dpdk_dev->name, switch_info->port_name);
2322         } else {
2323                 /* Bonding device. */
2324                 if (!switch_info->representor)
2325                         snprintf(name, sizeof(name), "%s_%s",
2326                                  dpdk_dev->name, spawn->ibv_dev->name);
2327                 else
2328                         snprintf(name, sizeof(name), "%s_%s_representor_%u",
2329                                  dpdk_dev->name, spawn->ibv_dev->name,
2330                                  switch_info->port_name);
2331         }
2332         /* check if the device is already spawned */
2333         if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
2334                 rte_errno = EEXIST;
2335                 return NULL;
2336         }
2337         DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
2338         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
2339                 struct mlx5_mp_id mp_id;
2340
2341                 eth_dev = rte_eth_dev_attach_secondary(name);
2342                 if (eth_dev == NULL) {
2343                         DRV_LOG(ERR, "can not attach rte ethdev");
2344                         rte_errno = ENOMEM;
2345                         return NULL;
2346                 }
2347                 eth_dev->device = dpdk_dev;
2348                 eth_dev->dev_ops = &mlx5_dev_sec_ops;
2349                 err = mlx5_proc_priv_init(eth_dev);
2350                 if (err)
2351                         return NULL;
2352                 mp_id.port_id = eth_dev->data->port_id;
2353                 strlcpy(mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);
2354                 /* Receive command fd from primary process */
2355                 err = mlx5_mp_req_verbs_cmd_fd(&mp_id);
2356                 if (err < 0)
2357                         return NULL;
2358                 /* Remap UAR for Tx queues. */
2359                 err = mlx5_tx_uar_init_secondary(eth_dev, err);
2360                 if (err)
2361                         return NULL;
2362                 /*
2363                  * Ethdev pointer is still required as input since
2364                  * the primary device is not accessible from the
2365                  * secondary process.
2366                  */
2367                 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev);
2368                 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev);
2369                 return eth_dev;
2370         }
2371         /*
2372          * Some parameters ("tx_db_nc" in particularly) are needed in
2373          * advance to create dv/verbs device context. We proceed the
2374          * devargs here to get ones, and later proceed devargs again
2375          * to override some hardware settings.
2376          */
2377         err = mlx5_args(&config, dpdk_dev->devargs);
2378         if (err) {
2379                 err = rte_errno;
2380                 DRV_LOG(ERR, "failed to process device arguments: %s",
2381                         strerror(rte_errno));
2382                 goto error;
2383         }
2384         sh = mlx5_alloc_shared_ibctx(spawn, &config);
2385         if (!sh)
2386                 return NULL;
2387         config.devx = sh->devx;
2388 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR
2389         config.dest_tir = 1;
2390 #endif
2391 #ifdef HAVE_IBV_MLX5_MOD_SWP
2392         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
2393 #endif
2394         /*
2395          * Multi-packet send is supported by ConnectX-4 Lx PF as well
2396          * as all ConnectX-5 devices.
2397          */
2398 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2399         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
2400 #endif
2401 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
2402         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
2403 #endif
2404         mlx5_glue->dv_query_device(sh->ctx, &dv_attr);
2405         if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
2406                 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
2407                         DRV_LOG(DEBUG, "enhanced MPW is supported");
2408                         mps = MLX5_MPW_ENHANCED;
2409                 } else {
2410                         DRV_LOG(DEBUG, "MPW is supported");
2411                         mps = MLX5_MPW;
2412                 }
2413         } else {
2414                 DRV_LOG(DEBUG, "MPW isn't supported");
2415                 mps = MLX5_MPW_DISABLED;
2416         }
2417 #ifdef HAVE_IBV_MLX5_MOD_SWP
2418         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
2419                 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
2420         DRV_LOG(DEBUG, "SWP support: %u", swp);
2421 #endif
2422         config.swp = !!swp;
2423 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
2424         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
2425                 struct mlx5dv_striding_rq_caps mprq_caps =
2426                         dv_attr.striding_rq_caps;
2427
2428                 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
2429                         mprq_caps.min_single_stride_log_num_of_bytes);
2430                 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
2431                         mprq_caps.max_single_stride_log_num_of_bytes);
2432                 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
2433                         mprq_caps.min_single_wqe_log_num_of_strides);
2434                 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
2435                         mprq_caps.max_single_wqe_log_num_of_strides);
2436                 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
2437                         mprq_caps.supported_qpts);
2438                 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
2439                 mprq = 1;
2440                 mprq_min_stride_size_n =
2441                         mprq_caps.min_single_stride_log_num_of_bytes;
2442                 mprq_max_stride_size_n =
2443                         mprq_caps.max_single_stride_log_num_of_bytes;
2444                 mprq_min_stride_num_n =
2445                         mprq_caps.min_single_wqe_log_num_of_strides;
2446                 mprq_max_stride_num_n =
2447                         mprq_caps.max_single_wqe_log_num_of_strides;
2448         }
2449 #endif
2450         if (RTE_CACHE_LINE_SIZE == 128 &&
2451             !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
2452                 cqe_comp = 0;
2453         else
2454                 cqe_comp = 1;
2455         config.cqe_comp = cqe_comp;
2456 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
2457         /* Whether device supports 128B Rx CQE padding. */
2458         cqe_pad = RTE_CACHE_LINE_SIZE == 128 &&
2459                   (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD);
2460 #endif
2461 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2462         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
2463                 tunnel_en = ((dv_attr.tunnel_offloads_caps &
2464                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
2465                              (dv_attr.tunnel_offloads_caps &
2466                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) &&
2467                              (dv_attr.tunnel_offloads_caps &
2468                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE));
2469         }
2470         DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
2471                 tunnel_en ? "" : "not ");
2472 #else
2473         DRV_LOG(WARNING,
2474                 "tunnel offloading disabled due to old OFED/rdma-core version");
2475 #endif
2476         config.tunnel_en = tunnel_en;
2477 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
2478         mpls_en = ((dv_attr.tunnel_offloads_caps &
2479                     MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
2480                    (dv_attr.tunnel_offloads_caps &
2481                     MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
2482         DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
2483                 mpls_en ? "" : "not ");
2484 #else
2485         DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
2486                 " old OFED/rdma-core version or firmware configuration");
2487 #endif
2488         config.mpls_en = mpls_en;
2489         /* Check port status. */
2490         err = mlx5_glue->query_port(sh->ctx, spawn->ibv_port, &port_attr);
2491         if (err) {
2492                 DRV_LOG(ERR, "port query failed: %s", strerror(err));
2493                 goto error;
2494         }
2495         if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
2496                 DRV_LOG(ERR, "port is not configured in Ethernet mode");
2497                 err = EINVAL;
2498                 goto error;
2499         }
2500         if (port_attr.state != IBV_PORT_ACTIVE)
2501                 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)",
2502                         mlx5_glue->port_state_str(port_attr.state),
2503                         port_attr.state);
2504         /* Allocate private eth device data. */
2505         priv = rte_zmalloc("ethdev private structure",
2506                            sizeof(*priv),
2507                            RTE_CACHE_LINE_SIZE);
2508         if (priv == NULL) {
2509                 DRV_LOG(ERR, "priv allocation failure");
2510                 err = ENOMEM;
2511                 goto error;
2512         }
2513         priv->sh = sh;
2514         priv->ibv_port = spawn->ibv_port;
2515         priv->pci_dev = spawn->pci_dev;
2516         priv->mtu = RTE_ETHER_MTU;
2517         priv->mp_id.port_id = port_id;
2518         strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);
2519 #ifndef RTE_ARCH_64
2520         /* Initialize UAR access locks for 32bit implementations. */
2521         rte_spinlock_init(&priv->uar_lock_cq);
2522         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
2523                 rte_spinlock_init(&priv->uar_lock[i]);
2524 #endif
2525         /* Some internal functions rely on Netlink sockets, open them now. */
2526         priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA);
2527         priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE);
2528         priv->representor = !!switch_info->representor;
2529         priv->master = !!switch_info->master;
2530         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
2531         priv->vport_meta_tag = 0;
2532         priv->vport_meta_mask = 0;
2533         priv->pf_bond = spawn->pf_bond;
2534 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
2535         /*
2536          * The DevX port query API is implemented. E-Switch may use
2537          * either vport or reg_c[0] metadata register to match on
2538          * vport index. The engaged part of metadata register is
2539          * defined by mask.
2540          */
2541         if (switch_info->representor || switch_info->master) {
2542                 devx_port.comp_mask = MLX5DV_DEVX_PORT_VPORT |
2543                                       MLX5DV_DEVX_PORT_MATCH_REG_C_0;
2544                 err = mlx5_glue->devx_port_query(sh->ctx, spawn->ibv_port,
2545                                                  &devx_port);
2546                 if (err) {
2547                         DRV_LOG(WARNING,
2548                                 "can't query devx port %d on device %s",
2549                                 spawn->ibv_port, spawn->ibv_dev->name);
2550                         devx_port.comp_mask = 0;
2551                 }
2552         }
2553         if (devx_port.comp_mask & MLX5DV_DEVX_PORT_MATCH_REG_C_0) {
2554                 priv->vport_meta_tag = devx_port.reg_c_0.value;
2555                 priv->vport_meta_mask = devx_port.reg_c_0.mask;
2556                 if (!priv->vport_meta_mask) {
2557                         DRV_LOG(ERR, "vport zero mask for port %d"
2558                                      " on bonding device %s",
2559                                      spawn->ibv_port, spawn->ibv_dev->name);
2560                         err = ENOTSUP;
2561                         goto error;
2562                 }
2563                 if (priv->vport_meta_tag & ~priv->vport_meta_mask) {
2564                         DRV_LOG(ERR, "invalid vport tag for port %d"
2565                                      " on bonding device %s",
2566                                      spawn->ibv_port, spawn->ibv_dev->name);
2567                         err = ENOTSUP;
2568                         goto error;
2569                 }
2570         }
2571         if (devx_port.comp_mask & MLX5DV_DEVX_PORT_VPORT) {
2572                 priv->vport_id = devx_port.vport_num;
2573         } else if (spawn->pf_bond >= 0) {
2574                 DRV_LOG(ERR, "can't deduce vport index for port %d"
2575                              " on bonding device %s",
2576                              spawn->ibv_port, spawn->ibv_dev->name);
2577                 err = ENOTSUP;
2578                 goto error;
2579         } else {
2580                 /* Suppose vport index in compatible way. */
2581                 priv->vport_id = switch_info->representor ?
2582                                  switch_info->port_name + 1 : -1;
2583         }
2584 #else
2585         /*
2586          * Kernel/rdma_core support single E-Switch per PF configurations
2587          * only and vport_id field contains the vport index for
2588          * associated VF, which is deduced from representor port name.
2589          * For example, let's have the IB device port 10, it has
2590          * attached network device eth0, which has port name attribute
2591          * pf0vf2, we can deduce the VF number as 2, and set vport index
2592          * as 3 (2+1). This assigning schema should be changed if the
2593          * multiple E-Switch instances per PF configurations or/and PCI
2594          * subfunctions are added.
2595          */
2596         priv->vport_id = switch_info->representor ?
2597                          switch_info->port_name + 1 : -1;
2598 #endif
2599         /* representor_id field keeps the unmodified VF index. */
2600         priv->representor_id = switch_info->representor ?
2601                                switch_info->port_name : -1;
2602         /*
2603          * Look for sibling devices in order to reuse their switch domain
2604          * if any, otherwise allocate one.
2605          */
2606         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2607                 const struct mlx5_priv *opriv =
2608                         rte_eth_devices[port_id].data->dev_private;
2609
2610                 if (!opriv ||
2611                     opriv->sh != priv->sh ||
2612                         opriv->domain_id ==
2613                         RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
2614                         continue;
2615                 priv->domain_id = opriv->domain_id;
2616                 break;
2617         }
2618         if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
2619                 err = rte_eth_switch_domain_alloc(&priv->domain_id);
2620                 if (err) {
2621                         err = rte_errno;
2622                         DRV_LOG(ERR, "unable to allocate switch domain: %s",
2623                                 strerror(rte_errno));
2624                         goto error;
2625                 }
2626                 own_domain_id = 1;
2627         }
2628         /* Override some values set by hardware configuration. */
2629         mlx5_args(&config, dpdk_dev->devargs);
2630         err = mlx5_dev_check_sibling_config(priv, &config);
2631         if (err)
2632                 goto error;
2633         config.hw_csum = !!(sh->device_attr.device_cap_flags_ex &
2634                             IBV_DEVICE_RAW_IP_CSUM);
2635         DRV_LOG(DEBUG, "checksum offloading is %ssupported",
2636                 (config.hw_csum ? "" : "not "));
2637 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \
2638         !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
2639         DRV_LOG(DEBUG, "counters are not supported");
2640 #endif
2641 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR)
2642         if (config.dv_flow_en) {
2643                 DRV_LOG(WARNING, "DV flow is not supported");
2644                 config.dv_flow_en = 0;
2645         }
2646 #endif
2647         config.ind_table_max_size =
2648                 sh->device_attr.rss_caps.max_rwq_indirection_table_size;
2649         /*
2650          * Remove this check once DPDK supports larger/variable
2651          * indirection tables.
2652          */
2653         if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
2654                 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
2655         DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
2656                 config.ind_table_max_size);
2657         config.hw_vlan_strip = !!(sh->device_attr.raw_packet_caps &
2658                                   IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
2659         DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
2660                 (config.hw_vlan_strip ? "" : "not "));
2661         config.hw_fcs_strip = !!(sh->device_attr.raw_packet_caps &
2662                                  IBV_RAW_PACKET_CAP_SCATTER_FCS);
2663         DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
2664                 (config.hw_fcs_strip ? "" : "not "));
2665 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
2666         hw_padding = !!sh->device_attr.rx_pad_end_addr_align;
2667 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
2668         hw_padding = !!(sh->device_attr.device_cap_flags_ex &
2669                         IBV_DEVICE_PCI_WRITE_END_PADDING);
2670 #endif
2671         if (config.hw_padding && !hw_padding) {
2672                 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
2673                 config.hw_padding = 0;
2674         } else if (config.hw_padding) {
2675                 DRV_LOG(DEBUG, "Rx end alignment padding is enabled");
2676         }
2677         config.tso = (sh->device_attr.tso_caps.max_tso > 0 &&
2678                       (sh->device_attr.tso_caps.supported_qpts &
2679                        (1 << IBV_QPT_RAW_PACKET)));
2680         if (config.tso)
2681                 config.tso_max_payload_sz = sh->device_attr.tso_caps.max_tso;
2682         /*
2683          * MPW is disabled by default, while the Enhanced MPW is enabled
2684          * by default.
2685          */
2686         if (config.mps == MLX5_ARG_UNSET)
2687                 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED :
2688                                                           MLX5_MPW_DISABLED;
2689         else
2690                 config.mps = config.mps ? mps : MLX5_MPW_DISABLED;
2691         DRV_LOG(INFO, "%sMPS is %s",
2692                 config.mps == MLX5_MPW_ENHANCED ? "enhanced " :
2693                 config.mps == MLX5_MPW ? "legacy " : "",
2694                 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
2695         if (config.cqe_comp && !cqe_comp) {
2696                 DRV_LOG(WARNING, "Rx CQE compression isn't supported");
2697                 config.cqe_comp = 0;
2698         }
2699         if (config.cqe_pad && !cqe_pad) {
2700                 DRV_LOG(WARNING, "Rx CQE padding isn't supported");
2701                 config.cqe_pad = 0;
2702         } else if (config.cqe_pad) {
2703                 DRV_LOG(INFO, "Rx CQE padding is enabled");
2704         }
2705         if (config.devx) {
2706                 priv->counter_fallback = 0;
2707                 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config.hca_attr);
2708                 if (err) {
2709                         err = -err;
2710                         goto error;
2711                 }
2712                 if (!config.hca_attr.flow_counters_dump)
2713                         priv->counter_fallback = 1;
2714 #ifndef HAVE_IBV_DEVX_ASYNC
2715                 priv->counter_fallback = 1;
2716 #endif
2717                 if (priv->counter_fallback)
2718                         DRV_LOG(INFO, "Use fall-back DV counter management");
2719                 /* Check for LRO support. */
2720                 if (config.dest_tir && config.hca_attr.lro_cap &&
2721                     config.dv_flow_en) {
2722                         /* TBD check tunnel lro caps. */
2723                         config.lro.supported = config.hca_attr.lro_cap;
2724                         DRV_LOG(DEBUG, "Device supports LRO");
2725                         /*
2726                          * If LRO timeout is not configured by application,
2727                          * use the minimal supported value.
2728                          */
2729                         if (!config.lro.timeout)
2730                                 config.lro.timeout =
2731                                 config.hca_attr.lro_timer_supported_periods[0];
2732                         DRV_LOG(DEBUG, "LRO session timeout set to %d usec",
2733                                 config.lro.timeout);
2734                 }
2735 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER)
2736                 if (config.hca_attr.qos.sup && config.hca_attr.qos.srtcm_sup &&
2737                     config.dv_flow_en) {
2738                         uint8_t reg_c_mask =
2739                                 config.hca_attr.qos.flow_meter_reg_c_ids;
2740                         /*
2741                          * Meter needs two REG_C's for color match and pre-sfx
2742                          * flow match. Here get the REG_C for color match.
2743                          * REG_C_0 and REG_C_1 is reserved for metadata feature.
2744                          */
2745                         reg_c_mask &= 0xfc;
2746                         if (__builtin_popcount(reg_c_mask) < 1) {
2747                                 priv->mtr_en = 0;
2748                                 DRV_LOG(WARNING, "No available register for"
2749                                         " meter.");
2750                         } else {
2751                                 priv->mtr_color_reg = ffs(reg_c_mask) - 1 +
2752                                                       REG_C_0;
2753                                 priv->mtr_en = 1;
2754                                 priv->mtr_reg_share =
2755                                       config.hca_attr.qos.flow_meter_reg_share;
2756                                 DRV_LOG(DEBUG, "The REG_C meter uses is %d",
2757                                         priv->mtr_color_reg);
2758                         }
2759                 }
2760 #endif
2761         }
2762         if (config.mprq.enabled && mprq) {
2763                 if (config.mprq.stride_num_n &&
2764                     (config.mprq.stride_num_n > mprq_max_stride_num_n ||
2765                      config.mprq.stride_num_n < mprq_min_stride_num_n)) {
2766                         config.mprq.stride_num_n =
2767                                 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
2768                                                 mprq_min_stride_num_n),
2769                                         mprq_max_stride_num_n);
2770                         DRV_LOG(WARNING,
2771                                 "the number of strides"
2772                                 " for Multi-Packet RQ is out of range,"
2773                                 " setting default value (%u)",
2774                                 1 << config.mprq.stride_num_n);
2775                 }
2776                 if (config.mprq.stride_size_n &&
2777                     (config.mprq.stride_size_n > mprq_max_stride_size_n ||
2778                      config.mprq.stride_size_n < mprq_min_stride_size_n)) {
2779                         config.mprq.stride_size_n =
2780                                 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N,
2781                                                 mprq_min_stride_size_n),
2782                                         mprq_max_stride_size_n);
2783                         DRV_LOG(WARNING,
2784                                 "the size of a stride"
2785                                 " for Multi-Packet RQ is out of range,"
2786                                 " setting default value (%u)",
2787                                 1 << config.mprq.stride_size_n);
2788                 }
2789                 config.mprq.min_stride_size_n = mprq_min_stride_size_n;
2790                 config.mprq.max_stride_size_n = mprq_max_stride_size_n;
2791         } else if (config.mprq.enabled && !mprq) {
2792                 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
2793                 config.mprq.enabled = 0;
2794         }
2795         if (config.max_dump_files_num == 0)
2796                 config.max_dump_files_num = 128;
2797         eth_dev = rte_eth_dev_allocate(name);
2798         if (eth_dev == NULL) {
2799                 DRV_LOG(ERR, "can not allocate rte ethdev");
2800                 err = ENOMEM;
2801                 goto error;
2802         }
2803         /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */
2804         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2805         if (priv->representor) {
2806                 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
2807                 eth_dev->data->representor_id = priv->representor_id;
2808         }
2809         /*
2810          * Store associated network device interface index. This index
2811          * is permanent throughout the lifetime of device. So, we may store
2812          * the ifindex here and use the cached value further.
2813          */
2814         MLX5_ASSERT(spawn->ifindex);
2815         priv->if_index = spawn->ifindex;
2816         eth_dev->data->dev_private = priv;
2817         priv->dev_data = eth_dev->data;
2818         eth_dev->data->mac_addrs = priv->mac;
2819         eth_dev->device = dpdk_dev;
2820         /* Configure the first MAC address by default. */
2821         if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
2822                 DRV_LOG(ERR,
2823                         "port %u cannot get MAC address, is mlx5_en"
2824                         " loaded? (errno: %s)",
2825                         eth_dev->data->port_id, strerror(rte_errno));
2826                 err = ENODEV;
2827                 goto error;
2828         }
2829         DRV_LOG(INFO,
2830                 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
2831                 eth_dev->data->port_id,
2832                 mac.addr_bytes[0], mac.addr_bytes[1],
2833                 mac.addr_bytes[2], mac.addr_bytes[3],
2834                 mac.addr_bytes[4], mac.addr_bytes[5]);
2835 #ifdef RTE_LIBRTE_MLX5_DEBUG
2836         {
2837                 char ifname[IF_NAMESIZE];
2838
2839                 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
2840                         DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
2841                                 eth_dev->data->port_id, ifname);
2842                 else
2843                         DRV_LOG(DEBUG, "port %u ifname is unknown",
2844                                 eth_dev->data->port_id);
2845         }
2846 #endif
2847         /* Get actual MTU if possible. */
2848         err = mlx5_get_mtu(eth_dev, &priv->mtu);
2849         if (err) {
2850                 err = rte_errno;
2851                 goto error;
2852         }
2853         DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
2854                 priv->mtu);
2855         /* Initialize burst functions to prevent crashes before link-up. */
2856         eth_dev->rx_pkt_burst = removed_rx_burst;
2857         eth_dev->tx_pkt_burst = removed_tx_burst;
2858         eth_dev->dev_ops = &mlx5_dev_ops;
2859         /* Register MAC address. */
2860         claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
2861         if (config.vf && config.vf_nl_en)
2862                 mlx5_nl_mac_addr_sync(priv->nl_socket_route,
2863                                       mlx5_ifindex(eth_dev),
2864                                       eth_dev->data->mac_addrs,
2865                                       MLX5_MAX_MAC_ADDRESSES);
2866         TAILQ_INIT(&priv->flows);
2867         TAILQ_INIT(&priv->ctrl_flows);
2868         TAILQ_INIT(&priv->flow_meters);
2869         TAILQ_INIT(&priv->flow_meter_profiles);
2870         /* Hint libmlx5 to use PMD allocator for data plane resources */
2871         struct mlx5dv_ctx_allocators alctr = {
2872                 .alloc = &mlx5_alloc_verbs_buf,
2873                 .free = &mlx5_free_verbs_buf,
2874                 .data = priv,
2875         };
2876         mlx5_glue->dv_set_context_attr(sh->ctx,
2877                                        MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
2878                                        (void *)((uintptr_t)&alctr));
2879         /* Bring Ethernet device up. */
2880         DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
2881                 eth_dev->data->port_id);
2882         mlx5_set_link_up(eth_dev);
2883         /*
2884          * Even though the interrupt handler is not installed yet,
2885          * interrupts will still trigger on the async_fd from
2886          * Verbs context returned by ibv_open_device().
2887          */
2888         mlx5_link_update(eth_dev, 0);
2889 #ifdef HAVE_MLX5DV_DR_ESWITCH
2890         if (!(config.hca_attr.eswitch_manager && config.dv_flow_en &&
2891               (switch_info->representor || switch_info->master)))
2892                 config.dv_esw_en = 0;
2893 #else
2894         config.dv_esw_en = 0;
2895 #endif
2896         /* Detect minimal data bytes to inline. */
2897         mlx5_set_min_inline(spawn, &config);
2898         /* Store device configuration on private structure. */
2899         priv->config = config;
2900         /* Create context for virtual machine VLAN workaround. */
2901         priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex);
2902         if (config.dv_flow_en) {
2903                 err = mlx5_alloc_shared_dr(priv);
2904                 if (err)
2905                         goto error;
2906                 /*
2907                  * RSS id is shared with meter flow id. Meter flow id can only
2908                  * use the 24 MSB of the register.
2909                  */
2910                 priv->qrss_id_pool = mlx5_flow_id_pool_alloc(UINT32_MAX >>
2911                                      MLX5_MTR_COLOR_BITS);
2912                 if (!priv->qrss_id_pool) {
2913                         DRV_LOG(ERR, "can't create flow id pool");
2914                         err = ENOMEM;
2915                         goto error;
2916                 }
2917         }
2918         /* Supported Verbs flow priority number detection. */
2919         err = mlx5_flow_discover_priorities(eth_dev);
2920         if (err < 0) {
2921                 err = -err;
2922                 goto error;
2923         }
2924         priv->config.flow_prio = err;
2925         if (!priv->config.dv_esw_en &&
2926             priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2927                 DRV_LOG(WARNING, "metadata mode %u is not supported "
2928                                  "(no E-Switch)", priv->config.dv_xmeta_en);
2929                 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY;
2930         }
2931         mlx5_set_metadata_mask(eth_dev);
2932         if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
2933             !priv->sh->dv_regc0_mask) {
2934                 DRV_LOG(ERR, "metadata mode %u is not supported "
2935                              "(no metadata reg_c[0] is available)",
2936                              priv->config.dv_xmeta_en);
2937                         err = ENOTSUP;
2938                         goto error;
2939         }
2940         /*
2941          * Allocate the buffer for flow creating, just once.
2942          * The allocation must be done before any flow creating.
2943          */
2944         mlx5_flow_alloc_intermediate(eth_dev);
2945         /* Query availibility of metadata reg_c's. */
2946         err = mlx5_flow_discover_mreg_c(eth_dev);
2947         if (err < 0) {
2948                 err = -err;
2949                 goto error;
2950         }
2951         if (!mlx5_flow_ext_mreg_supported(eth_dev)) {
2952                 DRV_LOG(DEBUG,
2953                         "port %u extensive metadata register is not supported",
2954                         eth_dev->data->port_id);
2955                 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2956                         DRV_LOG(ERR, "metadata mode %u is not supported "
2957                                      "(no metadata registers available)",
2958                                      priv->config.dv_xmeta_en);
2959                         err = ENOTSUP;
2960                         goto error;
2961                 }
2962         }
2963         if (priv->config.dv_flow_en &&
2964             priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
2965             mlx5_flow_ext_mreg_supported(eth_dev) &&
2966             priv->sh->dv_regc0_mask) {
2967                 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME,
2968                                                       MLX5_FLOW_MREG_HTABLE_SZ);
2969                 if (!priv->mreg_cp_tbl) {
2970                         err = ENOMEM;
2971                         goto error;
2972                 }
2973         }
2974         return eth_dev;
2975 error:
2976         if (priv) {
2977                 if (priv->mreg_cp_tbl)
2978                         mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
2979                 if (priv->sh)
2980                         mlx5_free_shared_dr(priv);
2981                 if (priv->nl_socket_route >= 0)
2982                         close(priv->nl_socket_route);
2983                 if (priv->nl_socket_rdma >= 0)
2984                         close(priv->nl_socket_rdma);
2985                 if (priv->vmwa_context)
2986                         mlx5_vlan_vmwa_exit(priv->vmwa_context);
2987                 if (priv->qrss_id_pool)
2988                         mlx5_flow_id_pool_release(priv->qrss_id_pool);
2989                 if (own_domain_id)
2990                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
2991                 rte_free(priv);
2992                 if (eth_dev != NULL)
2993                         eth_dev->data->dev_private = NULL;
2994         }
2995         if (eth_dev != NULL) {
2996                 /* mac_addrs must not be freed alone because part of dev_private */
2997                 eth_dev->data->mac_addrs = NULL;
2998                 rte_eth_dev_release_port(eth_dev);
2999         }
3000         if (sh)
3001                 mlx5_free_shared_ibctx(sh);
3002         MLX5_ASSERT(err > 0);
3003         rte_errno = err;
3004         return NULL;
3005 }
3006
3007 /**
3008  * Comparison callback to sort device data.
3009  *
3010  * This is meant to be used with qsort().
3011  *
3012  * @param a[in]
3013  *   Pointer to pointer to first data object.
3014  * @param b[in]
3015  *   Pointer to pointer to second data object.
3016  *
3017  * @return
3018  *   0 if both objects are equal, less than 0 if the first argument is less
3019  *   than the second, greater than 0 otherwise.
3020  */
3021 static int
3022 mlx5_dev_spawn_data_cmp(const void *a, const void *b)
3023 {
3024         const struct mlx5_switch_info *si_a =
3025                 &((const struct mlx5_dev_spawn_data *)a)->info;
3026         const struct mlx5_switch_info *si_b =
3027                 &((const struct mlx5_dev_spawn_data *)b)->info;
3028         int ret;
3029
3030         /* Master device first. */
3031         ret = si_b->master - si_a->master;
3032         if (ret)
3033                 return ret;
3034         /* Then representor devices. */
3035         ret = si_b->representor - si_a->representor;
3036         if (ret)
3037                 return ret;
3038         /* Unidentified devices come last in no specific order. */
3039         if (!si_a->representor)
3040                 return 0;
3041         /* Order representors by name. */
3042         return si_a->port_name - si_b->port_name;
3043 }
3044
3045 /**
3046  * Match PCI information for possible slaves of bonding device.
3047  *
3048  * @param[in] ibv_dev
3049  *   Pointer to Infiniband device structure.
3050  * @param[in] pci_dev
3051  *   Pointer to PCI device structure to match PCI address.
3052  * @param[in] nl_rdma
3053  *   Netlink RDMA group socket handle.
3054  *
3055  * @return
3056  *   negative value if no bonding device found, otherwise
3057  *   positive index of slave PF in bonding.
3058  */
3059 static int
3060 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev,
3061                            const struct rte_pci_device *pci_dev,
3062                            int nl_rdma)
3063 {
3064         char ifname[IF_NAMESIZE + 1];
3065         unsigned int ifindex;
3066         unsigned int np, i;
3067         FILE *file = NULL;
3068         int pf = -1;
3069
3070         /*
3071          * Try to get master device name. If something goes
3072          * wrong suppose the lack of kernel support and no
3073          * bonding devices.
3074          */
3075         if (nl_rdma < 0)
3076                 return -1;
3077         if (!strstr(ibv_dev->name, "bond"))
3078                 return -1;
3079         np = mlx5_nl_portnum(nl_rdma, ibv_dev->name);
3080         if (!np)
3081                 return -1;
3082         /*
3083          * The Master device might not be on the predefined
3084          * port (not on port index 1, it is not garanted),
3085          * we have to scan all Infiniband device port and
3086          * find master.
3087          */
3088         for (i = 1; i <= np; ++i) {
3089                 /* Check whether Infiniband port is populated. */
3090                 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i);
3091                 if (!ifindex)
3092                         continue;
3093                 if (!if_indextoname(ifindex, ifname))
3094                         continue;
3095                 /* Try to read bonding slave names from sysfs. */
3096                 MKSTR(slaves,
3097                       "/sys/class/net/%s/master/bonding/slaves", ifname);
3098                 file = fopen(slaves, "r");
3099                 if (file)
3100                         break;
3101         }
3102         if (!file)
3103                 return -1;
3104         /* Use safe format to check maximal buffer length. */
3105         MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE);
3106         while (fscanf(file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) {
3107                 char tmp_str[IF_NAMESIZE + 32];
3108                 struct rte_pci_addr pci_addr;
3109                 struct mlx5_switch_info info;
3110
3111                 /* Process slave interface names in the loop. */
3112                 snprintf(tmp_str, sizeof(tmp_str),
3113                          "/sys/class/net/%s", ifname);
3114                 if (mlx5_dev_to_pci_addr(tmp_str, &pci_addr)) {
3115                         DRV_LOG(WARNING, "can not get PCI address"
3116                                          " for netdev \"%s\"", ifname);
3117                         continue;
3118                 }
3119                 if (pci_dev->addr.domain != pci_addr.domain ||
3120                     pci_dev->addr.bus != pci_addr.bus ||
3121                     pci_dev->addr.devid != pci_addr.devid ||
3122                     pci_dev->addr.function != pci_addr.function)
3123                         continue;
3124                 /* Slave interface PCI address match found. */
3125                 fclose(file);
3126                 snprintf(tmp_str, sizeof(tmp_str),
3127                          "/sys/class/net/%s/phys_port_name", ifname);
3128                 file = fopen(tmp_str, "rb");
3129                 if (!file)
3130                         break;
3131                 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET;
3132                 if (fscanf(file, "%32s", tmp_str) == 1)
3133                         mlx5_translate_port_name(tmp_str, &info);
3134                 if (info.name_type == MLX5_PHYS_PORT_NAME_TYPE_LEGACY ||
3135                     info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK)
3136                         pf = info.port_name;
3137                 break;
3138         }
3139         if (file)
3140                 fclose(file);
3141         return pf;
3142 }
3143
3144 /**
3145  * DPDK callback to register a PCI device.
3146  *
3147  * This function spawns Ethernet devices out of a given PCI device.
3148  *
3149  * @param[in] pci_drv
3150  *   PCI driver structure (mlx5_driver).
3151  * @param[in] pci_dev
3152  *   PCI device information.
3153  *
3154  * @return
3155  *   0 on success, a negative errno value otherwise and rte_errno is set.
3156  */
3157 static int
3158 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3159                struct rte_pci_device *pci_dev)
3160 {
3161         struct ibv_device **ibv_list;
3162         /*
3163          * Number of found IB Devices matching with requested PCI BDF.
3164          * nd != 1 means there are multiple IB devices over the same
3165          * PCI device and we have representors and master.
3166          */
3167         unsigned int nd = 0;
3168         /*
3169          * Number of found IB device Ports. nd = 1 and np = 1..n means
3170          * we have the single multiport IB device, and there may be
3171          * representors attached to some of found ports.
3172          */
3173         unsigned int np = 0;
3174         /*
3175          * Number of DPDK ethernet devices to Spawn - either over
3176          * multiple IB devices or multiple ports of single IB device.
3177          * Actually this is the number of iterations to spawn.
3178          */
3179         unsigned int ns = 0;
3180         /*
3181          * Bonding device
3182          *   < 0 - no bonding device (single one)
3183          *  >= 0 - bonding device (value is slave PF index)
3184          */
3185         int bd = -1;
3186         struct mlx5_dev_spawn_data *list = NULL;
3187         struct mlx5_dev_config dev_config;
3188         int ret;
3189
3190         if (mlx5_class_get(pci_dev->device.devargs) != MLX5_CLASS_NET) {
3191                 DRV_LOG(DEBUG, "Skip probing - should be probed by other mlx5"
3192                         " driver.");
3193                 return 1;
3194         }
3195         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
3196                 mlx5_pmd_socket_init();
3197         ret = mlx5_init_once();
3198         if (ret) {
3199                 DRV_LOG(ERR, "unable to init PMD global data: %s",
3200                         strerror(rte_errno));
3201                 return -rte_errno;
3202         }
3203         MLX5_ASSERT(pci_drv == &mlx5_driver);
3204         errno = 0;
3205         ibv_list = mlx5_glue->get_device_list(&ret);
3206         if (!ibv_list) {
3207                 rte_errno = errno ? errno : ENOSYS;
3208                 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?");
3209                 return -rte_errno;
3210         }
3211         /*
3212          * First scan the list of all Infiniband devices to find
3213          * matching ones, gathering into the list.
3214          */
3215         struct ibv_device *ibv_match[ret + 1];
3216         int nl_route = mlx5_nl_init(NETLINK_ROUTE);
3217         int nl_rdma = mlx5_nl_init(NETLINK_RDMA);
3218         unsigned int i;
3219
3220         while (ret-- > 0) {
3221                 struct rte_pci_addr pci_addr;
3222
3223                 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name);
3224                 bd = mlx5_device_bond_pci_match
3225                                 (ibv_list[ret], pci_dev, nl_rdma);
3226                 if (bd >= 0) {
3227                         /*
3228                          * Bonding device detected. Only one match is allowed,
3229                          * the bonding is supported over multi-port IB device,
3230                          * there should be no matches on representor PCI
3231                          * functions or non VF LAG bonding devices with
3232                          * specified address.
3233                          */
3234                         if (nd) {
3235                                 DRV_LOG(ERR,
3236                                         "multiple PCI match on bonding device"
3237                                         "\"%s\" found", ibv_list[ret]->name);
3238                                 rte_errno = ENOENT;
3239                                 ret = -rte_errno;
3240                                 goto exit;
3241                         }
3242                         DRV_LOG(INFO, "PCI information matches for"
3243                                       " slave %d bonding device \"%s\"",
3244                                       bd, ibv_list[ret]->name);
3245                         ibv_match[nd++] = ibv_list[ret];
3246                         break;
3247                 }
3248                 if (mlx5_dev_to_pci_addr
3249                         (ibv_list[ret]->ibdev_path, &pci_addr))
3250                         continue;
3251                 if (pci_dev->addr.domain != pci_addr.domain ||
3252                     pci_dev->addr.bus != pci_addr.bus ||
3253                     pci_dev->addr.devid != pci_addr.devid ||
3254                     pci_dev->addr.function != pci_addr.function)
3255                         continue;
3256                 DRV_LOG(INFO, "PCI information matches for device \"%s\"",
3257                         ibv_list[ret]->name);
3258                 ibv_match[nd++] = ibv_list[ret];
3259         }
3260         ibv_match[nd] = NULL;
3261         if (!nd) {
3262                 /* No device matches, just complain and bail out. */
3263                 DRV_LOG(WARNING,
3264                         "no Verbs device matches PCI device " PCI_PRI_FMT ","
3265                         " are kernel drivers loaded?",
3266                         pci_dev->addr.domain, pci_dev->addr.bus,
3267                         pci_dev->addr.devid, pci_dev->addr.function);
3268                 rte_errno = ENOENT;
3269                 ret = -rte_errno;
3270                 goto exit;
3271         }
3272         if (nd == 1) {
3273                 /*
3274                  * Found single matching device may have multiple ports.
3275                  * Each port may be representor, we have to check the port
3276                  * number and check the representors existence.
3277                  */
3278                 if (nl_rdma >= 0)
3279                         np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name);
3280                 if (!np)
3281                         DRV_LOG(WARNING, "can not get IB device \"%s\""
3282                                          " ports number", ibv_match[0]->name);
3283                 if (bd >= 0 && !np) {
3284                         DRV_LOG(ERR, "can not get ports"
3285                                      " for bonding device");
3286                         rte_errno = ENOENT;
3287                         ret = -rte_errno;
3288                         goto exit;
3289                 }
3290         }
3291 #ifndef HAVE_MLX5DV_DR_DEVX_PORT
3292         if (bd >= 0) {
3293                 /*
3294                  * This may happen if there is VF LAG kernel support and
3295                  * application is compiled with older rdma_core library.
3296                  */
3297                 DRV_LOG(ERR,
3298                         "No kernel/verbs support for VF LAG bonding found.");
3299                 rte_errno = ENOTSUP;
3300                 ret = -rte_errno;
3301                 goto exit;
3302         }
3303 #endif
3304         /*
3305          * Now we can determine the maximal
3306          * amount of devices to be spawned.
3307          */
3308         list = rte_zmalloc("device spawn data",
3309                          sizeof(struct mlx5_dev_spawn_data) *
3310                          (np ? np : nd),
3311                          RTE_CACHE_LINE_SIZE);
3312         if (!list) {
3313                 DRV_LOG(ERR, "spawn data array allocation failure");
3314                 rte_errno = ENOMEM;
3315                 ret = -rte_errno;
3316                 goto exit;
3317         }
3318         if (bd >= 0 || np > 1) {
3319                 /*
3320                  * Single IB device with multiple ports found,
3321                  * it may be E-Switch master device and representors.
3322                  * We have to perform identification trough the ports.
3323                  */
3324                 MLX5_ASSERT(nl_rdma >= 0);
3325                 MLX5_ASSERT(ns == 0);
3326                 MLX5_ASSERT(nd == 1);
3327                 MLX5_ASSERT(np);
3328                 for (i = 1; i <= np; ++i) {
3329                         list[ns].max_port = np;
3330                         list[ns].ibv_port = i;
3331                         list[ns].ibv_dev = ibv_match[0];
3332                         list[ns].eth_dev = NULL;
3333                         list[ns].pci_dev = pci_dev;
3334                         list[ns].pf_bond = bd;
3335                         list[ns].ifindex = mlx5_nl_ifindex
3336                                         (nl_rdma, list[ns].ibv_dev->name, i);
3337                         if (!list[ns].ifindex) {
3338                                 /*
3339                                  * No network interface index found for the
3340                                  * specified port, it means there is no
3341                                  * representor on this port. It's OK,
3342                                  * there can be disabled ports, for example
3343                                  * if sriov_numvfs < sriov_totalvfs.
3344                                  */
3345                                 continue;
3346                         }
3347                         ret = -1;
3348                         if (nl_route >= 0)
3349                                 ret = mlx5_nl_switch_info
3350                                                (nl_route,
3351                                                 list[ns].ifindex,
3352                                                 &list[ns].info);
3353                         if (ret || (!list[ns].info.representor &&
3354                                     !list[ns].info.master)) {
3355                                 /*
3356                                  * We failed to recognize representors with
3357                                  * Netlink, let's try to perform the task
3358                                  * with sysfs.
3359                                  */
3360                                 ret =  mlx5_sysfs_switch_info
3361                                                 (list[ns].ifindex,
3362                                                  &list[ns].info);
3363                         }
3364                         if (!ret && bd >= 0) {
3365                                 switch (list[ns].info.name_type) {
3366                                 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK:
3367                                         if (list[ns].info.port_name == bd)
3368                                                 ns++;
3369                                         break;
3370                                 case MLX5_PHYS_PORT_NAME_TYPE_PFVF:
3371                                         if (list[ns].info.pf_num == bd)
3372                                                 ns++;
3373                                         break;
3374                                 default:
3375                                         break;
3376                                 }
3377                                 continue;
3378                         }
3379                         if (!ret && (list[ns].info.representor ^
3380                                      list[ns].info.master))
3381                                 ns++;
3382                 }
3383                 if (!ns) {
3384                         DRV_LOG(ERR,
3385                                 "unable to recognize master/representors"
3386                                 " on the IB device with multiple ports");
3387                         rte_errno = ENOENT;
3388                         ret = -rte_errno;
3389                         goto exit;
3390                 }
3391         } else {
3392                 /*
3393                  * The existence of several matching entries (nd > 1) means
3394                  * port representors have been instantiated. No existing Verbs
3395                  * call nor sysfs entries can tell them apart, this can only
3396                  * be done through Netlink calls assuming kernel drivers are
3397                  * recent enough to support them.
3398                  *
3399                  * In the event of identification failure through Netlink,
3400                  * try again through sysfs, then:
3401                  *
3402                  * 1. A single IB device matches (nd == 1) with single
3403                  *    port (np=0/1) and is not a representor, assume
3404                  *    no switch support.
3405                  *
3406                  * 2. Otherwise no safe assumptions can be made;
3407                  *    complain louder and bail out.
3408                  */
3409                 np = 1;
3410                 for (i = 0; i != nd; ++i) {
3411                         memset(&list[ns].info, 0, sizeof(list[ns].info));
3412                         list[ns].max_port = 1;
3413                         list[ns].ibv_port = 1;
3414                         list[ns].ibv_dev = ibv_match[i];
3415                         list[ns].eth_dev = NULL;
3416                         list[ns].pci_dev = pci_dev;
3417                         list[ns].pf_bond = -1;
3418                         list[ns].ifindex = 0;
3419                         if (nl_rdma >= 0)
3420                                 list[ns].ifindex = mlx5_nl_ifindex
3421                                         (nl_rdma, list[ns].ibv_dev->name, 1);
3422                         if (!list[ns].ifindex) {
3423                                 char ifname[IF_NAMESIZE];
3424
3425                                 /*
3426                                  * Netlink failed, it may happen with old
3427                                  * ib_core kernel driver (before 4.16).
3428                                  * We can assume there is old driver because
3429                                  * here we are processing single ports IB
3430                                  * devices. Let's try sysfs to retrieve
3431                                  * the ifindex. The method works for
3432                                  * master device only.
3433                                  */
3434                                 if (nd > 1) {
3435                                         /*
3436                                          * Multiple devices found, assume
3437                                          * representors, can not distinguish
3438                                          * master/representor and retrieve
3439                                          * ifindex via sysfs.
3440                                          */
3441                                         continue;
3442                                 }
3443                                 ret = mlx5_get_master_ifname
3444                                         (ibv_match[i]->ibdev_path, &ifname);
3445                                 if (!ret)
3446                                         list[ns].ifindex =
3447                                                 if_nametoindex(ifname);
3448                                 if (!list[ns].ifindex) {
3449                                         /*
3450                                          * No network interface index found
3451                                          * for the specified device, it means
3452                                          * there it is neither representor
3453                                          * nor master.
3454                                          */
3455                                         continue;
3456                                 }
3457                         }
3458                         ret = -1;
3459                         if (nl_route >= 0)
3460                                 ret = mlx5_nl_switch_info
3461                                                (nl_route,
3462                                                 list[ns].ifindex,
3463                                                 &list[ns].info);
3464                         if (ret || (!list[ns].info.representor &&
3465                                     !list[ns].info.master)) {
3466                                 /*
3467                                  * We failed to recognize representors with
3468                                  * Netlink, let's try to perform the task
3469                                  * with sysfs.
3470                                  */
3471                                 ret =  mlx5_sysfs_switch_info
3472                                                 (list[ns].ifindex,
3473                                                  &list[ns].info);
3474                         }
3475                         if (!ret && (list[ns].info.representor ^
3476                                      list[ns].info.master)) {
3477                                 ns++;
3478                         } else if ((nd == 1) &&
3479                                    !list[ns].info.representor &&
3480                                    !list[ns].info.master) {
3481                                 /*
3482                                  * Single IB device with
3483                                  * one physical port and
3484                                  * attached network device.
3485                                  * May be SRIOV is not enabled
3486                                  * or there is no representors.
3487                                  */
3488                                 DRV_LOG(INFO, "no E-Switch support detected");
3489                                 ns++;
3490                                 break;
3491                         }
3492                 }
3493                 if (!ns) {
3494                         DRV_LOG(ERR,
3495                                 "unable to recognize master/representors"
3496                                 " on the multiple IB devices");
3497                         rte_errno = ENOENT;
3498                         ret = -rte_errno;
3499                         goto exit;
3500                 }
3501         }
3502         MLX5_ASSERT(ns);
3503         /*
3504          * Sort list to probe devices in natural order for users convenience
3505          * (i.e. master first, then representors from lowest to highest ID).
3506          */
3507         qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp);
3508         /* Default configuration. */
3509         dev_config = (struct mlx5_dev_config){
3510                 .hw_padding = 0,
3511                 .mps = MLX5_ARG_UNSET,
3512                 .dbnc = MLX5_ARG_UNSET,
3513                 .rx_vec_en = 1,
3514                 .txq_inline_max = MLX5_ARG_UNSET,
3515                 .txq_inline_min = MLX5_ARG_UNSET,
3516                 .txq_inline_mpw = MLX5_ARG_UNSET,
3517                 .txqs_inline = MLX5_ARG_UNSET,
3518                 .vf_nl_en = 1,
3519                 .mr_ext_memseg_en = 1,
3520                 .mprq = {
3521                         .enabled = 0, /* Disabled by default. */
3522                         .stride_num_n = 0,
3523                         .stride_size_n = 0,
3524                         .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
3525                         .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
3526                 },
3527                 .dv_esw_en = 1,
3528                 .dv_flow_en = 1,
3529                 .log_hp_size = MLX5_ARG_UNSET,
3530         };
3531         /* Device specific configuration. */
3532         switch (pci_dev->id.device_id) {
3533         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
3534         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
3535         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
3536         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
3537         case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF:
3538         case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF:
3539         case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF:
3540                 dev_config.vf = 1;
3541                 break;
3542         default:
3543                 break;
3544         }
3545         for (i = 0; i != ns; ++i) {
3546                 uint32_t restore;
3547
3548                 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device,
3549                                                  &list[i],
3550                                                  dev_config);
3551                 if (!list[i].eth_dev) {
3552                         if (rte_errno != EBUSY && rte_errno != EEXIST)
3553                                 break;
3554                         /* Device is disabled or already spawned. Ignore it. */
3555                         continue;
3556                 }
3557                 restore = list[i].eth_dev->data->dev_flags;
3558                 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev);
3559                 /* Restore non-PCI flags cleared by the above call. */
3560                 list[i].eth_dev->data->dev_flags |= restore;
3561                 mlx5_dev_interrupt_handler_devx_install(list[i].eth_dev);
3562                 rte_eth_dev_probing_finish(list[i].eth_dev);
3563         }
3564         if (i != ns) {
3565                 DRV_LOG(ERR,
3566                         "probe of PCI device " PCI_PRI_FMT " aborted after"
3567                         " encountering an error: %s",
3568                         pci_dev->addr.domain, pci_dev->addr.bus,
3569                         pci_dev->addr.devid, pci_dev->addr.function,
3570                         strerror(rte_errno));
3571                 ret = -rte_errno;
3572                 /* Roll back. */
3573                 while (i--) {
3574                         if (!list[i].eth_dev)
3575                                 continue;
3576                         mlx5_dev_close(list[i].eth_dev);
3577                         /* mac_addrs must not be freed because in dev_private */
3578                         list[i].eth_dev->data->mac_addrs = NULL;
3579                         claim_zero(rte_eth_dev_release_port(list[i].eth_dev));
3580                 }
3581                 /* Restore original error. */
3582                 rte_errno = -ret;
3583         } else {
3584                 ret = 0;
3585         }
3586 exit:
3587         /*
3588          * Do the routine cleanup:
3589          * - close opened Netlink sockets
3590          * - free allocated spawn data array
3591          * - free the Infiniband device list
3592          */
3593         if (nl_rdma >= 0)
3594                 close(nl_rdma);
3595         if (nl_route >= 0)
3596                 close(nl_route);
3597         if (list)
3598                 rte_free(list);
3599         MLX5_ASSERT(ibv_list);
3600         mlx5_glue->free_device_list(ibv_list);
3601         return ret;
3602 }
3603
3604 /**
3605  * Look for the ethernet device belonging to mlx5 driver.
3606  *
3607  * @param[in] port_id
3608  *   port_id to start looking for device.
3609  * @param[in] pci_dev
3610  *   Pointer to the hint PCI device. When device is being probed
3611  *   the its siblings (master and preceding representors might
3612  *   not have assigned driver yet (because the mlx5_pci_probe()
3613  *   is not completed yet, for this case match on hint PCI
3614  *   device may be used to detect sibling device.
3615  *
3616  * @return
3617  *   port_id of found device, RTE_MAX_ETHPORT if not found.
3618  */
3619 uint16_t
3620 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
3621 {
3622         while (port_id < RTE_MAX_ETHPORTS) {
3623                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
3624
3625                 if (dev->state != RTE_ETH_DEV_UNUSED &&
3626                     dev->device &&
3627                     (dev->device == &pci_dev->device ||
3628                      (dev->device->driver &&
3629                      dev->device->driver->name &&
3630                      !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
3631                         break;
3632                 port_id++;
3633         }
3634         if (port_id >= RTE_MAX_ETHPORTS)
3635                 return RTE_MAX_ETHPORTS;
3636         return port_id;
3637 }
3638
3639 /**
3640  * DPDK callback to remove a PCI device.
3641  *
3642  * This function removes all Ethernet devices belong to a given PCI device.
3643  *
3644  * @param[in] pci_dev
3645  *   Pointer to the PCI device.
3646  *
3647  * @return
3648  *   0 on success, the function cannot fail.
3649  */
3650 static int
3651 mlx5_pci_remove(struct rte_pci_device *pci_dev)
3652 {
3653         uint16_t port_id;
3654
3655         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device)
3656                 rte_eth_dev_close(port_id);
3657         return 0;
3658 }
3659
3660 static const struct rte_pci_id mlx5_pci_id_map[] = {
3661         {
3662                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3663                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
3664         },
3665         {
3666                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3667                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
3668         },
3669         {
3670                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3671                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
3672         },
3673         {
3674                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3675                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
3676         },
3677         {
3678                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3679                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
3680         },
3681         {
3682                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3683                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
3684         },
3685         {
3686                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3687                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
3688         },
3689         {
3690                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3691                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
3692         },
3693         {
3694                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3695                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
3696         },
3697         {
3698                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3699                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
3700         },
3701         {
3702                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3703                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
3704         },
3705         {
3706                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3707                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
3708         },
3709         {
3710                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3711                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
3712         },
3713         {
3714                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3715                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
3716         },
3717         {
3718                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3719                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
3720         },
3721         {
3722                 .vendor_id = 0
3723         }
3724 };
3725
3726 static struct rte_pci_driver mlx5_driver = {
3727         .driver = {
3728                 .name = MLX5_DRIVER_NAME
3729         },
3730         .id_table = mlx5_pci_id_map,
3731         .probe = mlx5_pci_probe,
3732         .remove = mlx5_pci_remove,
3733         .dma_map = mlx5_dma_map,
3734         .dma_unmap = mlx5_dma_unmap,
3735         .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV |
3736                      RTE_PCI_DRV_PROBE_AGAIN,
3737 };
3738
3739 /**
3740  * Driver initialization routine.
3741  */
3742 RTE_INIT(rte_mlx5_pmd_init)
3743 {
3744         /* Initialize driver log type. */
3745         mlx5_logtype = rte_log_register("pmd.net.mlx5");
3746         if (mlx5_logtype >= 0)
3747                 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
3748
3749         /* Build the static tables for Verbs conversion. */
3750         mlx5_set_ptype_table();
3751         mlx5_set_cksum_table();
3752         mlx5_set_swp_types_table();
3753         if (mlx5_glue)
3754                 rte_pci_register(&mlx5_driver);
3755 }
3756
3757 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
3758 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
3759 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");