1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
14 #include <linux/rtnetlink.h>
17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
19 #pragma GCC diagnostic ignored "-Wpedantic"
21 #include <infiniband/verbs.h>
23 #pragma GCC diagnostic error "-Wpedantic"
26 #include <rte_malloc.h>
27 #include <rte_ethdev_driver.h>
28 #include <rte_ethdev_pci.h>
30 #include <rte_bus_pci.h>
31 #include <rte_common.h>
32 #include <rte_kvargs.h>
33 #include <rte_rwlock.h>
34 #include <rte_spinlock.h>
35 #include <rte_string_fns.h>
36 #include <rte_alarm.h>
38 #include <mlx5_glue.h>
39 #include <mlx5_devx_cmds.h>
40 #include <mlx5_common.h>
41 #include <mlx5_common_os.h>
42 #include <mlx5_common_mp.h>
43 #include <mlx5_malloc.h>
45 #include "mlx5_defs.h"
47 #include "mlx5_utils.h"
48 #include "mlx5_rxtx.h"
49 #include "mlx5_autoconf.h"
51 #include "mlx5_flow.h"
52 #include "rte_pmd_mlx5.h"
54 /* Device parameter to enable RX completion queue compression. */
55 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
57 /* Device parameter to enable RX completion entry padding to 128B. */
58 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
60 /* Device parameter to enable padding Rx packet to cacheline size. */
61 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
63 /* Device parameter to enable Multi-Packet Rx queue. */
64 #define MLX5_RX_MPRQ_EN "mprq_en"
66 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
67 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
69 /* Device parameter to configure log 2 of the stride size for MPRQ. */
70 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
72 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
73 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
75 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
76 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
78 /* Device parameter to configure inline send. Deprecated, ignored.*/
79 #define MLX5_TXQ_INLINE "txq_inline"
81 /* Device parameter to limit packet size to inline with ordinary SEND. */
82 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
84 /* Device parameter to configure minimal data size to inline. */
85 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
87 /* Device parameter to limit packet size to inline with Enhanced MPW. */
88 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
91 * Device parameter to configure the number of TX queues threshold for
92 * enabling inline send.
94 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
97 * Device parameter to configure the number of TX queues threshold for
98 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
100 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
102 /* Device parameter to enable multi-packet send WQEs. */
103 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
106 * Device parameter to force doorbell register mapping
107 * to non-cahed region eliminating the extra write memory barrier.
109 #define MLX5_TX_DB_NC "tx_db_nc"
112 * Device parameter to include 2 dsegs in the title WQEBB.
113 * Deprecated, ignored.
115 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
118 * Device parameter to limit the size of inlining packet.
119 * Deprecated, ignored.
121 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
124 * Device parameter to enable Tx scheduling on timestamps
125 * and specify the packet pacing granularity in nanoseconds.
127 #define MLX5_TX_PP "tx_pp"
130 * Device parameter to specify skew in nanoseconds on Tx datapath,
131 * it represents the time between SQ start WQE processing and
132 * appearing actual packet data on the wire.
134 #define MLX5_TX_SKEW "tx_skew"
137 * Device parameter to enable hardware Tx vector.
138 * Deprecated, ignored (no vectorized Tx routines anymore).
140 #define MLX5_TX_VEC_EN "tx_vec_en"
142 /* Device parameter to enable hardware Rx vector. */
143 #define MLX5_RX_VEC_EN "rx_vec_en"
145 /* Allow L3 VXLAN flow creation. */
146 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
148 /* Activate DV E-Switch flow steering. */
149 #define MLX5_DV_ESW_EN "dv_esw_en"
151 /* Activate DV flow steering. */
152 #define MLX5_DV_FLOW_EN "dv_flow_en"
154 /* Enable extensive flow metadata support. */
155 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
157 /* Device parameter to let the user manage the lacp traffic of bonded device */
158 #define MLX5_LACP_BY_USER "lacp_by_user"
160 /* Activate Netlink support in VF mode. */
161 #define MLX5_VF_NL_EN "vf_nl_en"
163 /* Enable extending memsegs when creating a MR. */
164 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
166 /* Select port representors to instantiate. */
167 #define MLX5_REPRESENTOR "representor"
169 /* Device parameter to configure the maximum number of dump files per queue. */
170 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
172 /* Configure timeout of LRO session (in microseconds). */
173 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
176 * Device parameter to configure the total data buffer size for a single
177 * hairpin queue (logarithm value).
179 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
181 /* Flow memory reclaim mode. */
182 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
184 /* The default memory allocator used in PMD. */
185 #define MLX5_SYS_MEM_EN "sys_mem_en"
186 /* Decap will be used or not. */
187 #define MLX5_DECAP_EN "decap_en"
189 /* Shared memory between primary and secondary processes. */
190 struct mlx5_shared_data *mlx5_shared_data;
192 /** Driver-specific log messages type. */
195 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
196 LIST_HEAD_INITIALIZER();
197 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
199 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
200 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
202 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
208 .malloc = mlx5_malloc,
210 .type = "mlx5_encap_decap_ipool",
213 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
219 .malloc = mlx5_malloc,
221 .type = "mlx5_push_vlan_ipool",
224 .size = sizeof(struct mlx5_flow_dv_tag_resource),
230 .malloc = mlx5_malloc,
232 .type = "mlx5_tag_ipool",
235 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
241 .malloc = mlx5_malloc,
243 .type = "mlx5_port_id_ipool",
246 .size = sizeof(struct mlx5_flow_tbl_data_entry),
252 .malloc = mlx5_malloc,
254 .type = "mlx5_jump_ipool",
258 .size = sizeof(struct mlx5_flow_meter),
264 .malloc = mlx5_malloc,
266 .type = "mlx5_meter_ipool",
269 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
275 .malloc = mlx5_malloc,
277 .type = "mlx5_mcp_ipool",
280 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
286 .malloc = mlx5_malloc,
288 .type = "mlx5_hrxq_ipool",
292 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
293 * It set in run time according to PCI function configuration.
301 .malloc = mlx5_malloc,
303 .type = "mlx5_flow_handle_ipool",
306 .size = sizeof(struct rte_flow),
310 .malloc = mlx5_malloc,
312 .type = "rte_flow_ipool",
317 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
318 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
320 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
323 * Allocate ID pool structure.
326 * The maximum id can be allocated from the pool.
329 * Pointer to pool object, NULL value otherwise.
331 struct mlx5_flow_id_pool *
332 mlx5_flow_id_pool_alloc(uint32_t max_id)
334 struct mlx5_flow_id_pool *pool;
337 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool),
338 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
340 DRV_LOG(ERR, "can't allocate id pool");
344 mem = mlx5_malloc(MLX5_MEM_ZERO,
345 MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
346 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
348 DRV_LOG(ERR, "can't allocate mem for id pool");
352 pool->free_arr = mem;
353 pool->curr = pool->free_arr;
354 pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
355 pool->base_index = 0;
356 pool->max_id = max_id;
364 * Release ID pool structure.
367 * Pointer to flow id pool object to free.
370 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
372 mlx5_free(pool->free_arr);
380 * Pointer to flow id pool.
385 * 0 on success, error value otherwise.
388 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
390 if (pool->curr == pool->free_arr) {
391 if (pool->base_index == pool->max_id) {
393 DRV_LOG(ERR, "no free id");
396 *id = ++pool->base_index;
399 *id = *(--pool->curr);
407 * Pointer to flow id pool.
412 * 0 on success, error value otherwise.
415 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
421 if (pool->curr == pool->last) {
422 size = pool->curr - pool->free_arr;
423 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
424 MLX5_ASSERT(size2 > size);
425 mem = mlx5_malloc(0, size2 * sizeof(uint32_t), 0,
428 DRV_LOG(ERR, "can't allocate mem for id pool");
432 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
433 mlx5_free(pool->free_arr);
434 pool->free_arr = mem;
435 pool->curr = pool->free_arr + size;
436 pool->last = pool->free_arr + size2;
444 * Initialize the shared aging list information per port.
447 * Pointer to mlx5_dev_ctx_shared object.
450 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
453 struct mlx5_age_info *age_info;
455 for (i = 0; i < sh->max_port; i++) {
456 age_info = &sh->port[i].age_info;
458 TAILQ_INIT(&age_info->aged_counters);
459 rte_spinlock_init(&age_info->aged_sl);
460 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
465 * Initialize the counters management structure.
468 * Pointer to mlx5_dev_ctx_shared object to free
471 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
475 memset(&sh->cmng, 0, sizeof(sh->cmng));
476 TAILQ_INIT(&sh->cmng.flow_counters);
477 for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
478 sh->cmng.ccont[i].min_id = MLX5_CNT_BATCH_OFFSET;
479 sh->cmng.ccont[i].max_id = -1;
480 sh->cmng.ccont[i].last_pool_idx = POOL_IDX_INVALID;
481 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
482 rte_spinlock_init(&sh->cmng.ccont[i].resize_sl);
483 TAILQ_INIT(&sh->cmng.ccont[i].counters);
484 rte_spinlock_init(&sh->cmng.ccont[i].csl);
489 * Destroy all the resources allocated for a counter memory management.
492 * Pointer to the memory management structure.
495 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
497 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
499 LIST_REMOVE(mng, next);
500 claim_zero(mlx5_devx_cmd_destroy(mng->dm));
501 claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
506 * Close and release all the resources of the counters management.
509 * Pointer to mlx5_dev_ctx_shared object to free.
512 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
514 struct mlx5_counter_stats_mem_mng *mng;
521 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
522 if (rte_errno != EINPROGRESS)
526 for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
527 struct mlx5_flow_counter_pool *pool;
528 uint32_t batch = !!(i > 1);
530 if (!sh->cmng.ccont[i].pools)
532 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
534 if (batch && pool->min_dcs)
535 claim_zero(mlx5_devx_cmd_destroy
537 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
538 if (MLX5_POOL_GET_CNT(pool, j)->action)
540 (mlx5_glue->destroy_flow_action
543 if (!batch && MLX5_GET_POOL_CNT_EXT
545 claim_zero(mlx5_devx_cmd_destroy
546 (MLX5_GET_POOL_CNT_EXT
549 TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, next);
551 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
553 mlx5_free(sh->cmng.ccont[i].pools);
555 mng = LIST_FIRST(&sh->cmng.mem_mngs);
557 mlx5_flow_destroy_counter_stat_mem_mng(mng);
558 mng = LIST_FIRST(&sh->cmng.mem_mngs);
560 memset(&sh->cmng, 0, sizeof(sh->cmng));
564 * Initialize the flow resources' indexed mempool.
567 * Pointer to mlx5_dev_ctx_shared object.
569 * Pointer to user dev config.
572 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
573 const struct mlx5_dev_config *config)
576 struct mlx5_indexed_pool_config cfg;
578 for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
579 cfg = mlx5_ipool_cfg[i];
584 * Set MLX5_IPOOL_MLX5_FLOW ipool size
585 * according to PCI function flow configuration.
587 case MLX5_IPOOL_MLX5_FLOW:
588 cfg.size = config->dv_flow_en ?
589 sizeof(struct mlx5_flow_handle) :
590 MLX5_FLOW_HANDLE_VERBS_SIZE;
593 if (config->reclaim_mode)
594 cfg.release_mem_en = 1;
595 sh->ipool[i] = mlx5_ipool_create(&cfg);
600 * Release the flow resources' indexed mempool.
603 * Pointer to mlx5_dev_ctx_shared object.
606 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
610 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
611 mlx5_ipool_destroy(sh->ipool[i]);
615 * Check if dynamic flex parser for eCPRI already exists.
618 * Pointer to Ethernet device structure.
621 * true on exists, false on not.
624 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
626 struct mlx5_priv *priv = dev->data->dev_private;
627 struct mlx5_flex_parser_profiles *prf =
628 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
634 * Allocation of a flex parser for eCPRI. Once created, this parser related
635 * resources will be held until the device is closed.
638 * Pointer to Ethernet device structure.
641 * 0 on success, a negative errno value otherwise and rte_errno is set.
644 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
646 struct mlx5_priv *priv = dev->data->dev_private;
647 struct mlx5_flex_parser_profiles *prf =
648 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
649 struct mlx5_devx_graph_node_attr node = {
650 .modify_field_select = 0,
655 if (!priv->config.hca_attr.parse_graph_flex_node) {
656 DRV_LOG(ERR, "Dynamic flex parser is not supported "
657 "for device %s.", priv->dev_data->name);
660 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
661 /* 8 bytes now: 4B common header + 4B message body header. */
662 node.header_length_base_value = 0x8;
663 /* After MAC layer: Ether / VLAN. */
664 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
665 /* Type of compared condition should be 0xAEFE in the L2 layer. */
666 node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
667 /* Sample #0: type in common header. */
668 node.sample[0].flow_match_sample_en = 1;
670 node.sample[0].flow_match_sample_offset_mode = 0x0;
671 /* Only the 2nd byte will be used. */
672 node.sample[0].flow_match_sample_field_base_offset = 0x0;
673 /* Sample #1: message payload. */
674 node.sample[1].flow_match_sample_en = 1;
676 node.sample[1].flow_match_sample_offset_mode = 0x0;
678 * Only the first two bytes will be used right now, and its offset will
679 * start after the common header that with the length of a DW(u32).
681 node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
682 prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
684 DRV_LOG(ERR, "Failed to create flex parser node object.");
685 return (rte_errno == 0) ? -ENODEV : -rte_errno;
688 ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
690 DRV_LOG(ERR, "Failed to query sample IDs.");
691 return (rte_errno == 0) ? -ENODEV : -rte_errno;
693 prf->offset[0] = 0x0;
694 prf->offset[1] = sizeof(uint32_t);
695 prf->ids[0] = ids[0];
696 prf->ids[1] = ids[1];
701 * Destroy the flex parser node, including the parser itself, input / output
702 * arcs and DW samples. Resources could be reused then.
705 * Pointer to Ethernet device structure.
708 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
710 struct mlx5_priv *priv = dev->data->dev_private;
711 struct mlx5_flex_parser_profiles *prf =
712 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
715 mlx5_devx_cmd_destroy(prf->obj);
720 * Allocate shared device context. If there is multiport device the
721 * master and representors will share this context, if there is single
722 * port dedicated device, the context will be used by only given
723 * port due to unification.
725 * Routine first searches the context for the specified device name,
726 * if found the shared context assumed and reference counter is incremented.
727 * If no context found the new one is created and initialized with specified
728 * device context and parameters.
731 * Pointer to the device attributes (name, port, etc).
733 * Pointer to device configuration structure.
736 * Pointer to mlx5_dev_ctx_shared object on success,
737 * otherwise NULL and rte_errno is set.
739 struct mlx5_dev_ctx_shared *
740 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
741 const struct mlx5_dev_config *config)
743 struct mlx5_dev_ctx_shared *sh;
746 struct mlx5_devx_tis_attr tis_attr = { 0 };
749 /* Secondary process should not create the shared context. */
750 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
751 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
752 /* Search for IB context by device name. */
753 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
754 if (!strcmp(sh->ibdev_name,
755 mlx5_os_get_dev_device_name(spawn->phys_dev))) {
760 /* No device found, we have to create new shared context. */
761 MLX5_ASSERT(spawn->max_port);
762 sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
763 sizeof(struct mlx5_dev_ctx_shared) +
765 sizeof(struct mlx5_dev_shared_port),
766 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
768 DRV_LOG(ERR, "shared context allocation failure");
772 err = mlx5_os_open_device(spawn, config, sh);
775 err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
777 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
781 sh->max_port = spawn->max_port;
782 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
783 sizeof(sh->ibdev_name) - 1);
784 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
785 sizeof(sh->ibdev_path) - 1);
787 * Setting port_id to max unallowed value means
788 * there is no interrupt subhandler installed for
789 * the given port index i.
791 for (i = 0; i < sh->max_port; i++) {
792 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
793 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
795 sh->pd = mlx5_glue->alloc_pd(sh->ctx);
796 if (sh->pd == NULL) {
797 DRV_LOG(ERR, "PD allocation failure");
802 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
804 DRV_LOG(ERR, "Fail to extract pdn from PD");
807 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
809 DRV_LOG(ERR, "TD allocation failure");
813 tis_attr.transport_domain = sh->td->id;
814 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
816 DRV_LOG(ERR, "TIS allocation failure");
820 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, 0);
822 DRV_LOG(ERR, "Failed to allocate DevX UAR.");
827 sh->flow_id_pool = mlx5_flow_id_pool_alloc
828 ((1 << HAIRPIN_FLOW_ID_BITS) - 1);
829 if (!sh->flow_id_pool) {
830 DRV_LOG(ERR, "can't create flow id pool");
835 /* Initialize UAR access locks for 32bit implementations. */
836 rte_spinlock_init(&sh->uar_lock_cq);
837 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
838 rte_spinlock_init(&sh->uar_lock[i]);
841 * Once the device is added to the list of memory event
842 * callback, its global MR cache table cannot be expanded
843 * on the fly because of deadlock. If it overflows, lookup
844 * should be done by searching MR list linearly, which is slow.
846 * At this point the device is not added to the memory
847 * event list yet, context is just being created.
849 err = mlx5_mr_btree_init(&sh->share_cache.cache,
850 MLX5_MR_BTREE_CACHE_N * 2,
851 spawn->pci_dev->device.numa_node);
856 mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
857 &sh->share_cache.dereg_mr_cb);
858 mlx5_os_dev_shared_handler_install(sh);
859 sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
860 if (!sh->cnt_id_tbl) {
864 mlx5_flow_aging_init(sh);
865 mlx5_flow_counters_mng_init(sh);
866 mlx5_flow_ipool_create(sh, config);
867 /* Add device to memory callback list. */
868 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
869 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
871 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
872 /* Add context to the global device list. */
873 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
875 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
878 pthread_mutex_destroy(&sh->txpp.mutex);
879 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
881 if (sh->cnt_id_tbl) {
882 mlx5_l3t_destroy(sh->cnt_id_tbl);
883 sh->cnt_id_tbl = NULL;
886 mlx5_glue->devx_free_uar(sh->tx_uar);
890 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
892 claim_zero(mlx5_devx_cmd_destroy(sh->td));
894 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
896 claim_zero(mlx5_glue->close_device(sh->ctx));
897 if (sh->flow_id_pool)
898 mlx5_flow_id_pool_release(sh->flow_id_pool);
900 MLX5_ASSERT(err > 0);
906 * Free shared IB device context. Decrement counter and if zero free
907 * all allocated resources and close handles.
910 * Pointer to mlx5_dev_ctx_shared object to free
913 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
915 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
916 #ifdef RTE_LIBRTE_MLX5_DEBUG
917 /* Check the object presence in the list. */
918 struct mlx5_dev_ctx_shared *lctx;
920 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
925 DRV_LOG(ERR, "Freeing non-existing shared IB context");
930 MLX5_ASSERT(sh->refcnt);
931 /* Secondary process should not free the shared context. */
932 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
935 /* Remove from memory callback device list. */
936 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
937 LIST_REMOVE(sh, mem_event_cb);
938 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
939 /* Release created Memory Regions. */
940 mlx5_mr_release_cache(&sh->share_cache);
941 /* Remove context from the global device list. */
942 LIST_REMOVE(sh, next);
944 * Ensure there is no async event handler installed.
945 * Only primary process handles async device events.
947 mlx5_flow_counters_mng_close(sh);
948 mlx5_flow_ipool_destroy(sh);
949 mlx5_os_dev_shared_handler_uninstall(sh);
950 if (sh->cnt_id_tbl) {
951 mlx5_l3t_destroy(sh->cnt_id_tbl);
952 sh->cnt_id_tbl = NULL;
955 mlx5_glue->devx_free_uar(sh->tx_uar);
959 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
961 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
963 claim_zero(mlx5_devx_cmd_destroy(sh->td));
965 claim_zero(mlx5_glue->close_device(sh->ctx));
966 if (sh->flow_id_pool)
967 mlx5_flow_id_pool_release(sh->flow_id_pool);
968 pthread_mutex_destroy(&sh->txpp.mutex);
971 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
975 * Destroy table hash list and all the root entries per domain.
978 * Pointer to the private device data structure.
981 mlx5_free_table_hash_list(struct mlx5_priv *priv)
983 struct mlx5_dev_ctx_shared *sh = priv->sh;
984 struct mlx5_flow_tbl_data_entry *tbl_data;
985 union mlx5_flow_tbl_key table_key = {
993 struct mlx5_hlist_entry *pos;
997 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
999 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1001 MLX5_ASSERT(tbl_data);
1002 mlx5_hlist_remove(sh->flow_tbls, pos);
1003 mlx5_free(tbl_data);
1005 table_key.direction = 1;
1006 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1008 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1010 MLX5_ASSERT(tbl_data);
1011 mlx5_hlist_remove(sh->flow_tbls, pos);
1012 mlx5_free(tbl_data);
1014 table_key.direction = 0;
1015 table_key.domain = 1;
1016 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1018 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1020 MLX5_ASSERT(tbl_data);
1021 mlx5_hlist_remove(sh->flow_tbls, pos);
1022 mlx5_free(tbl_data);
1024 mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
1028 * Initialize flow table hash list and create the root tables entry
1032 * Pointer to the private device data structure.
1035 * Zero on success, positive error code otherwise.
1038 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
1040 struct mlx5_dev_ctx_shared *sh = priv->sh;
1041 char s[MLX5_HLIST_NAMESIZE];
1045 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1046 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
1047 if (!sh->flow_tbls) {
1048 DRV_LOG(ERR, "flow tables with hash creation failed.");
1052 #ifndef HAVE_MLX5DV_DR
1054 * In case we have not DR support, the zero tables should be created
1055 * because DV expect to see them even if they cannot be created by
1058 union mlx5_flow_tbl_key table_key = {
1066 struct mlx5_flow_tbl_data_entry *tbl_data = mlx5_malloc(MLX5_MEM_ZERO,
1067 sizeof(*tbl_data), 0,
1074 tbl_data->entry.key = table_key.v64;
1075 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1078 rte_atomic32_init(&tbl_data->tbl.refcnt);
1079 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1080 table_key.direction = 1;
1081 tbl_data = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tbl_data), 0,
1087 tbl_data->entry.key = table_key.v64;
1088 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1091 rte_atomic32_init(&tbl_data->tbl.refcnt);
1092 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1093 table_key.direction = 0;
1094 table_key.domain = 1;
1095 tbl_data = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tbl_data), 0,
1101 tbl_data->entry.key = table_key.v64;
1102 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1105 rte_atomic32_init(&tbl_data->tbl.refcnt);
1106 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1109 mlx5_free_table_hash_list(priv);
1110 #endif /* HAVE_MLX5DV_DR */
1115 * Retrieve integer value from environment variable.
1118 * Environment variable name.
1121 * Integer value, 0 if the variable is not set.
1124 mlx5_getenv_int(const char *name)
1126 const char *val = getenv(name);
1134 * DPDK callback to add udp tunnel port
1137 * A pointer to eth_dev
1138 * @param[in] udp_tunnel
1139 * A pointer to udp tunnel
1142 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1145 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1146 struct rte_eth_udp_tunnel *udp_tunnel)
1148 MLX5_ASSERT(udp_tunnel != NULL);
1149 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1150 udp_tunnel->udp_port == 4789)
1152 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1153 udp_tunnel->udp_port == 4790)
1159 * Initialize process private data structure.
1162 * Pointer to Ethernet device structure.
1165 * 0 on success, a negative errno value otherwise and rte_errno is set.
1168 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1170 struct mlx5_priv *priv = dev->data->dev_private;
1171 struct mlx5_proc_priv *ppriv;
1175 * UAR register table follows the process private structure. BlueFlame
1176 * registers for Tx queues are stored in the table.
1179 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1180 ppriv = mlx5_malloc(MLX5_MEM_RTE, ppriv_size, RTE_CACHE_LINE_SIZE,
1181 dev->device->numa_node);
1186 ppriv->uar_table_sz = ppriv_size;
1187 dev->process_private = ppriv;
1192 * Un-initialize process private data structure.
1195 * Pointer to Ethernet device structure.
1198 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1200 if (!dev->process_private)
1202 mlx5_free(dev->process_private);
1203 dev->process_private = NULL;
1207 * DPDK callback to close the device.
1209 * Destroy all queues and objects, free memory.
1212 * Pointer to Ethernet device structure.
1215 mlx5_dev_close(struct rte_eth_dev *dev)
1217 struct mlx5_priv *priv = dev->data->dev_private;
1221 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1222 /* Check if process_private released. */
1223 if (!dev->process_private)
1225 mlx5_tx_uar_uninit_secondary(dev);
1226 mlx5_proc_priv_uninit(dev);
1227 rte_eth_dev_release_port(dev);
1232 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1234 ((priv->sh->ctx != NULL) ?
1235 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1237 * If default mreg copy action is removed at the stop stage,
1238 * the search will return none and nothing will be done anymore.
1240 mlx5_flow_stop_default(dev);
1241 mlx5_traffic_disable(dev);
1243 * If all the flows are already flushed in the device stop stage,
1244 * then this will return directly without any action.
1246 mlx5_flow_list_flush(dev, &priv->flows, true);
1247 mlx5_flow_meter_flush(dev, NULL);
1248 /* Free the intermediate buffers for flow creation. */
1249 mlx5_flow_free_intermediate(dev);
1250 /* Prevent crashes when queues are still in use. */
1251 dev->rx_pkt_burst = removed_rx_burst;
1252 dev->tx_pkt_burst = removed_tx_burst;
1254 /* Disable datapath on secondary process. */
1255 mlx5_mp_os_req_stop_rxtx(dev);
1256 /* Free the eCPRI flex parser resource. */
1257 mlx5_flex_parser_ecpri_release(dev);
1258 if (priv->rxqs != NULL) {
1259 /* XXX race condition if mlx5_rx_burst() is still running. */
1261 for (i = 0; (i != priv->rxqs_n); ++i)
1262 mlx5_rxq_release(dev, i);
1266 if (priv->txqs != NULL) {
1267 /* XXX race condition if mlx5_tx_burst() is still running. */
1269 for (i = 0; (i != priv->txqs_n); ++i)
1270 mlx5_txq_release(dev, i);
1274 mlx5_proc_priv_uninit(dev);
1275 if (priv->mreg_cp_tbl)
1276 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1277 mlx5_mprq_free_mp(dev);
1278 mlx5_os_free_shared_dr(priv);
1279 if (priv->rss_conf.rss_key != NULL)
1280 mlx5_free(priv->rss_conf.rss_key);
1281 if (priv->reta_idx != NULL)
1282 mlx5_free(priv->reta_idx);
1283 if (priv->config.vf)
1284 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1285 dev->data->mac_addrs,
1286 MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1287 if (priv->nl_socket_route >= 0)
1288 close(priv->nl_socket_route);
1289 if (priv->nl_socket_rdma >= 0)
1290 close(priv->nl_socket_rdma);
1291 if (priv->vmwa_context)
1292 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1293 ret = mlx5_hrxq_verify(dev);
1295 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1296 dev->data->port_id);
1297 ret = mlx5_ind_table_obj_verify(dev);
1299 DRV_LOG(WARNING, "port %u some indirection table still remain",
1300 dev->data->port_id);
1301 ret = mlx5_rxq_obj_verify(dev);
1303 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1304 dev->data->port_id);
1305 ret = mlx5_rxq_verify(dev);
1307 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1308 dev->data->port_id);
1309 ret = mlx5_txq_obj_verify(dev);
1311 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1312 dev->data->port_id);
1313 ret = mlx5_txq_verify(dev);
1315 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1316 dev->data->port_id);
1317 ret = mlx5_flow_verify(dev);
1319 DRV_LOG(WARNING, "port %u some flows still remain",
1320 dev->data->port_id);
1322 * Free the shared context in last turn, because the cleanup
1323 * routines above may use some shared fields, like
1324 * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1325 * ifindex if Netlink fails.
1327 mlx5_free_shared_dev_ctx(priv->sh);
1328 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1332 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1333 struct mlx5_priv *opriv =
1334 rte_eth_devices[port_id].data->dev_private;
1337 opriv->domain_id != priv->domain_id ||
1338 &rte_eth_devices[port_id] == dev)
1344 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1346 memset(priv, 0, sizeof(*priv));
1347 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1349 * Reset mac_addrs to NULL such that it is not freed as part of
1350 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1351 * it is freed when dev_private is freed.
1353 dev->data->mac_addrs = NULL;
1357 * Verify and store value for device argument.
1360 * Key argument to verify.
1362 * Value associated with key.
1367 * 0 on success, a negative errno value otherwise and rte_errno is set.
1370 mlx5_args_check(const char *key, const char *val, void *opaque)
1372 struct mlx5_dev_config *config = opaque;
1376 /* No-op, port representors are processed in mlx5_dev_spawn(). */
1377 if (!strcmp(MLX5_REPRESENTOR, key))
1380 tmp = strtol(val, NULL, 0);
1383 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1386 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1387 /* Negative values are acceptable for some keys only. */
1389 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1392 mod = tmp >= 0 ? tmp : -tmp;
1393 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1394 config->cqe_comp = !!tmp;
1395 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1396 config->cqe_pad = !!tmp;
1397 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1398 config->hw_padding = !!tmp;
1399 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1400 config->mprq.enabled = !!tmp;
1401 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1402 config->mprq.stride_num_n = tmp;
1403 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1404 config->mprq.stride_size_n = tmp;
1405 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1406 config->mprq.max_memcpy_len = tmp;
1407 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1408 config->mprq.min_rxqs_num = tmp;
1409 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1410 DRV_LOG(WARNING, "%s: deprecated parameter,"
1411 " converted to txq_inline_max", key);
1412 config->txq_inline_max = tmp;
1413 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1414 config->txq_inline_max = tmp;
1415 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1416 config->txq_inline_min = tmp;
1417 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1418 config->txq_inline_mpw = tmp;
1419 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1420 config->txqs_inline = tmp;
1421 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1422 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1423 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1424 config->mps = !!tmp;
1425 } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1426 if (tmp != MLX5_TXDB_CACHED &&
1427 tmp != MLX5_TXDB_NCACHED &&
1428 tmp != MLX5_TXDB_HEURISTIC) {
1429 DRV_LOG(ERR, "invalid Tx doorbell "
1430 "mapping parameter");
1435 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1436 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1437 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1438 DRV_LOG(WARNING, "%s: deprecated parameter,"
1439 " converted to txq_inline_mpw", key);
1440 config->txq_inline_mpw = tmp;
1441 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1442 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1443 } else if (strcmp(MLX5_TX_PP, key) == 0) {
1445 DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1449 config->tx_pp = tmp;
1450 } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1451 config->tx_skew = tmp;
1452 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1453 config->rx_vec_en = !!tmp;
1454 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1455 config->l3_vxlan_en = !!tmp;
1456 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1457 config->vf_nl_en = !!tmp;
1458 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1459 config->dv_esw_en = !!tmp;
1460 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1461 config->dv_flow_en = !!tmp;
1462 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1463 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1464 tmp != MLX5_XMETA_MODE_META16 &&
1465 tmp != MLX5_XMETA_MODE_META32) {
1466 DRV_LOG(ERR, "invalid extensive "
1467 "metadata parameter");
1471 config->dv_xmeta_en = tmp;
1472 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1473 config->lacp_by_user = !!tmp;
1474 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1475 config->mr_ext_memseg_en = !!tmp;
1476 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1477 config->max_dump_files_num = tmp;
1478 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1479 config->lro.timeout = tmp;
1480 } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1481 DRV_LOG(DEBUG, "class argument is %s.", val);
1482 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1483 config->log_hp_size = tmp;
1484 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1485 if (tmp != MLX5_RCM_NONE &&
1486 tmp != MLX5_RCM_LIGHT &&
1487 tmp != MLX5_RCM_AGGR) {
1488 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1492 config->reclaim_mode = tmp;
1493 } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1494 config->sys_mem_en = !!tmp;
1495 } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1496 config->decap_en = !!tmp;
1498 DRV_LOG(WARNING, "%s: unknown parameter", key);
1506 * Parse device parameters.
1509 * Pointer to device configuration structure.
1511 * Device arguments structure.
1514 * 0 on success, a negative errno value otherwise and rte_errno is set.
1517 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1519 const char **params = (const char *[]){
1520 MLX5_RXQ_CQE_COMP_EN,
1521 MLX5_RXQ_CQE_PAD_EN,
1522 MLX5_RXQ_PKT_PAD_EN,
1524 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1525 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1526 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1529 MLX5_TXQ_INLINE_MIN,
1530 MLX5_TXQ_INLINE_MAX,
1531 MLX5_TXQ_INLINE_MPW,
1532 MLX5_TXQS_MIN_INLINE,
1535 MLX5_TXQ_MPW_HDR_DSEG_EN,
1536 MLX5_TXQ_MAX_INLINE_LEN,
1548 MLX5_MR_EXT_MEMSEG_EN,
1550 MLX5_MAX_DUMP_FILES_NUM,
1551 MLX5_LRO_TIMEOUT_USEC,
1552 MLX5_CLASS_ARG_NAME,
1559 struct rte_kvargs *kvlist;
1563 if (devargs == NULL)
1565 /* Following UGLY cast is done to pass checkpatch. */
1566 kvlist = rte_kvargs_parse(devargs->args, params);
1567 if (kvlist == NULL) {
1571 /* Process parameters. */
1572 for (i = 0; (params[i] != NULL); ++i) {
1573 if (rte_kvargs_count(kvlist, params[i])) {
1574 ret = rte_kvargs_process(kvlist, params[i],
1575 mlx5_args_check, config);
1578 rte_kvargs_free(kvlist);
1583 rte_kvargs_free(kvlist);
1588 * Configures the minimal amount of data to inline into WQE
1589 * while sending packets.
1591 * - the txq_inline_min has the maximal priority, if this
1592 * key is specified in devargs
1593 * - if DevX is enabled the inline mode is queried from the
1594 * device (HCA attributes and NIC vport context if needed).
1595 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1596 * and none (0 bytes) for other NICs
1599 * Verbs device parameters (name, port, switch_info) to spawn.
1601 * Device configuration parameters.
1604 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1605 struct mlx5_dev_config *config)
1607 if (config->txq_inline_min != MLX5_ARG_UNSET) {
1608 /* Application defines size of inlined data explicitly. */
1609 switch (spawn->pci_dev->id.device_id) {
1610 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1611 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1612 if (config->txq_inline_min <
1613 (int)MLX5_INLINE_HSIZE_L2) {
1615 "txq_inline_mix aligned to minimal"
1616 " ConnectX-4 required value %d",
1617 (int)MLX5_INLINE_HSIZE_L2);
1618 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1624 if (config->hca_attr.eth_net_offloads) {
1625 /* We have DevX enabled, inline mode queried successfully. */
1626 switch (config->hca_attr.wqe_inline_mode) {
1627 case MLX5_CAP_INLINE_MODE_L2:
1628 /* outer L2 header must be inlined. */
1629 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1631 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1632 /* No inline data are required by NIC. */
1633 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1634 config->hw_vlan_insert =
1635 config->hca_attr.wqe_vlan_insert;
1636 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1638 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1639 /* inline mode is defined by NIC vport context. */
1640 if (!config->hca_attr.eth_virt)
1642 switch (config->hca_attr.vport_inline_mode) {
1643 case MLX5_INLINE_MODE_NONE:
1644 config->txq_inline_min =
1645 MLX5_INLINE_HSIZE_NONE;
1647 case MLX5_INLINE_MODE_L2:
1648 config->txq_inline_min =
1649 MLX5_INLINE_HSIZE_L2;
1651 case MLX5_INLINE_MODE_IP:
1652 config->txq_inline_min =
1653 MLX5_INLINE_HSIZE_L3;
1655 case MLX5_INLINE_MODE_TCP_UDP:
1656 config->txq_inline_min =
1657 MLX5_INLINE_HSIZE_L4;
1659 case MLX5_INLINE_MODE_INNER_L2:
1660 config->txq_inline_min =
1661 MLX5_INLINE_HSIZE_INNER_L2;
1663 case MLX5_INLINE_MODE_INNER_IP:
1664 config->txq_inline_min =
1665 MLX5_INLINE_HSIZE_INNER_L3;
1667 case MLX5_INLINE_MODE_INNER_TCP_UDP:
1668 config->txq_inline_min =
1669 MLX5_INLINE_HSIZE_INNER_L4;
1675 * We get here if we are unable to deduce
1676 * inline data size with DevX. Try PCI ID
1677 * to determine old NICs.
1679 switch (spawn->pci_dev->id.device_id) {
1680 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1681 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1682 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1683 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1684 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1685 config->hw_vlan_insert = 0;
1687 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1688 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1689 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1690 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1692 * These NICs support VLAN insertion from WQE and
1693 * report the wqe_vlan_insert flag. But there is the bug
1694 * and PFC control may be broken, so disable feature.
1696 config->hw_vlan_insert = 0;
1697 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1700 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1704 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1708 * Configures the metadata mask fields in the shared context.
1711 * Pointer to Ethernet device.
1714 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1716 struct mlx5_priv *priv = dev->data->dev_private;
1717 struct mlx5_dev_ctx_shared *sh = priv->sh;
1718 uint32_t meta, mark, reg_c0;
1720 reg_c0 = ~priv->vport_meta_mask;
1721 switch (priv->config.dv_xmeta_en) {
1722 case MLX5_XMETA_MODE_LEGACY:
1724 mark = MLX5_FLOW_MARK_MASK;
1726 case MLX5_XMETA_MODE_META16:
1727 meta = reg_c0 >> rte_bsf32(reg_c0);
1728 mark = MLX5_FLOW_MARK_MASK;
1730 case MLX5_XMETA_MODE_META32:
1732 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1740 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1741 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1742 sh->dv_mark_mask, mark);
1744 sh->dv_mark_mask = mark;
1745 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1746 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1747 sh->dv_meta_mask, meta);
1749 sh->dv_meta_mask = meta;
1750 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1751 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1752 sh->dv_meta_mask, reg_c0);
1754 sh->dv_regc0_mask = reg_c0;
1755 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1756 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1757 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1758 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1762 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1764 static const char *const dynf_names[] = {
1765 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1766 RTE_MBUF_DYNFLAG_METADATA_NAME,
1767 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
1771 if (n < RTE_DIM(dynf_names))
1773 for (i = 0; i < RTE_DIM(dynf_names); i++) {
1774 if (names[i] == NULL)
1776 strcpy(names[i], dynf_names[i]);
1778 return RTE_DIM(dynf_names);
1782 * Comparison callback to sort device data.
1784 * This is meant to be used with qsort().
1787 * Pointer to pointer to first data object.
1789 * Pointer to pointer to second data object.
1792 * 0 if both objects are equal, less than 0 if the first argument is less
1793 * than the second, greater than 0 otherwise.
1796 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1797 struct mlx5_dev_config *config)
1799 struct mlx5_dev_ctx_shared *sh = priv->sh;
1800 struct mlx5_dev_config *sh_conf = NULL;
1804 /* Nothing to compare for the single/first device. */
1805 if (sh->refcnt == 1)
1807 /* Find the device with shared context. */
1808 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1809 struct mlx5_priv *opriv =
1810 rte_eth_devices[port_id].data->dev_private;
1812 if (opriv && opriv != priv && opriv->sh == sh) {
1813 sh_conf = &opriv->config;
1819 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1820 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1821 " for shared %s context", sh->ibdev_name);
1825 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1826 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1827 " for shared %s context", sh->ibdev_name);
1835 * Look for the ethernet device belonging to mlx5 driver.
1837 * @param[in] port_id
1838 * port_id to start looking for device.
1839 * @param[in] pci_dev
1840 * Pointer to the hint PCI device. When device is being probed
1841 * the its siblings (master and preceding representors might
1842 * not have assigned driver yet (because the mlx5_os_pci_probe()
1843 * is not completed yet, for this case match on hint PCI
1844 * device may be used to detect sibling device.
1847 * port_id of found device, RTE_MAX_ETHPORT if not found.
1850 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
1852 while (port_id < RTE_MAX_ETHPORTS) {
1853 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
1855 if (dev->state != RTE_ETH_DEV_UNUSED &&
1857 (dev->device == &pci_dev->device ||
1858 (dev->device->driver &&
1859 dev->device->driver->name &&
1860 !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
1864 if (port_id >= RTE_MAX_ETHPORTS)
1865 return RTE_MAX_ETHPORTS;
1870 * DPDK callback to remove a PCI device.
1872 * This function removes all Ethernet devices belong to a given PCI device.
1874 * @param[in] pci_dev
1875 * Pointer to the PCI device.
1878 * 0 on success, the function cannot fail.
1881 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1885 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
1887 * mlx5_dev_close() is not registered to secondary process,
1888 * call the close function explicitly for secondary process.
1890 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
1891 mlx5_dev_close(&rte_eth_devices[port_id]);
1893 rte_eth_dev_close(port_id);
1898 static const struct rte_pci_id mlx5_pci_id_map[] = {
1900 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1901 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1904 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1905 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1908 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1909 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1912 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1913 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1916 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1917 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1920 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1921 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1924 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1925 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1928 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1929 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1932 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1933 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
1936 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1937 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
1940 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1941 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
1944 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1945 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
1948 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1949 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
1952 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1953 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
1956 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1957 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
1960 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1961 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
1968 struct rte_pci_driver mlx5_driver = {
1970 .name = MLX5_DRIVER_NAME
1972 .id_table = mlx5_pci_id_map,
1973 .probe = mlx5_os_pci_probe,
1974 .remove = mlx5_pci_remove,
1975 .dma_map = mlx5_dma_map,
1976 .dma_unmap = mlx5_dma_unmap,
1977 .drv_flags = PCI_DRV_FLAGS,
1980 /* Initialize driver log type. */
1981 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
1984 * Driver initialization routine.
1986 RTE_INIT(rte_mlx5_pmd_init)
1988 /* Build the static tables for Verbs conversion. */
1989 mlx5_set_ptype_table();
1990 mlx5_set_cksum_table();
1991 mlx5_set_swp_types_table();
1993 rte_pci_register(&mlx5_driver);
1996 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1997 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1998 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");