drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12 #include <net/if.h>
  13 #include <sys/mman.h>
  14 #include <linux/rtnetlink.h>
  15
  16 /* Verbs header. */
  17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  18 #ifdef PEDANTIC
  19 #pragma GCC diagnostic ignored "-Wpedantic"
  20 #endif
  21 #include <infiniband/verbs.h>
  22 #ifdef PEDANTIC
  23 #pragma GCC diagnostic error "-Wpedantic"
  24 #endif
  25
  26 #include <rte_malloc.h>
  27 #include <rte_ethdev_driver.h>
  28 #include <rte_ethdev_pci.h>
  29 #include <rte_pci.h>
  30 #include <rte_bus_pci.h>
  31 #include <rte_common.h>
  32 #include <rte_kvargs.h>
  33 #include <rte_rwlock.h>
  34 #include <rte_spinlock.h>
  35 #include <rte_string_fns.h>
  36 #include <rte_alarm.h>
  37
  38 #include <mlx5_glue.h>
  39 #include <mlx5_devx_cmds.h>
  40 #include <mlx5_common.h>
  41 #include <mlx5_common_os.h>
  42 #include <mlx5_common_mp.h>
  43
  44 #include "mlx5_defs.h"
  45 #include "mlx5.h"
  46 #include "mlx5_utils.h"
  47 #include "mlx5_rxtx.h"
  48 #include "mlx5_autoconf.h"
  49 #include "mlx5_mr.h"
  50 #include "mlx5_flow.h"
  51 #include "rte_pmd_mlx5.h"
  52
  53 /* Device parameter to enable RX completion queue compression. */
  54 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  55
  56 /* Device parameter to enable RX completion entry padding to 128B. */
  57 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
  58
  59 /* Device parameter to enable padding Rx packet to cacheline size. */
  60 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  61
  62 /* Device parameter to enable Multi-Packet Rx queue. */
  63 #define MLX5_RX_MPRQ_EN "mprq_en"
  64
  65 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  66 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  67
  68 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  69 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  70
  71 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  72 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  73
  74 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  75 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  76
  77 /* Device parameter to configure inline send. Deprecated, ignored.*/
  78 #define MLX5_TXQ_INLINE "txq_inline"
  79
  80 /* Device parameter to limit packet size to inline with ordinary SEND. */
  81 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  82
  83 /* Device parameter to configure minimal data size to inline. */
  84 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  85
  86 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  87 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  88
  89 /*
  90  * Device parameter to configure the number of TX queues threshold for
  91  * enabling inline send.
  92  */
  93 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  94
  95 /*
  96  * Device parameter to configure the number of TX queues threshold for
  97  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  98  */
  99 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
 100
 101 /* Device parameter to enable multi-packet send WQEs. */
 102 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
 103
 104 /*
 105  * Device parameter to force doorbell register mapping
 106  * to non-cahed region eliminating the extra write memory barrier.
 107  */
 108 #define MLX5_TX_DB_NC "tx_db_nc"
 109
 110 /*
 111  * Device parameter to include 2 dsegs in the title WQEBB.
 112  * Deprecated, ignored.
 113  */
 114 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 115
 116 /*
 117  * Device parameter to limit the size of inlining packet.
 118  * Deprecated, ignored.
 119  */
 120 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 121
 122 /*
 123  * Device parameter to enable Tx scheduling on timestamps
 124  * and specify the packet pacing granularity in nanoseconds.
 125  */
 126 #define MLX5_TX_PP "tx_pp"
 127
 128 /*
 129  * Device parameter to specify skew in nanoseconds on Tx datapath,
 130  * it represents the time between SQ start WQE processing and
 131  * appearing actual packet data on the wire.
 132  */
 133 #define MLX5_TX_SKEW "tx_skew"
 134
 135 /*
 136  * Device parameter to enable hardware Tx vector.
 137  * Deprecated, ignored (no vectorized Tx routines anymore).
 138  */
 139 #define MLX5_TX_VEC_EN "tx_vec_en"
 140
 141 /* Device parameter to enable hardware Rx vector. */
 142 #define MLX5_RX_VEC_EN "rx_vec_en"
 143
 144 /* Allow L3 VXLAN flow creation. */
 145 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 146
 147 /* Activate DV E-Switch flow steering. */
 148 #define MLX5_DV_ESW_EN "dv_esw_en"
 149
 150 /* Activate DV flow steering. */
 151 #define MLX5_DV_FLOW_EN "dv_flow_en"
 152
 153 /* Enable extensive flow metadata support. */
 154 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 155
 156 /* Device parameter to let the user manage the lacp traffic of bonded device */
 157 #define MLX5_LACP_BY_USER "lacp_by_user"
 158
 159 /* Activate Netlink support in VF mode. */
 160 #define MLX5_VF_NL_EN "vf_nl_en"
 161
 162 /* Enable extending memsegs when creating a MR. */
 163 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 164
 165 /* Select port representors to instantiate. */
 166 #define MLX5_REPRESENTOR "representor"
 167
 168 /* Device parameter to configure the maximum number of dump files per queue. */
 169 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 170
 171 /* Configure timeout of LRO session (in microseconds). */
 172 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 173
 174 /*
 175  * Device parameter to configure the total data buffer size for a single
 176  * hairpin queue (logarithm value).
 177  */
 178 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 179
 180 /* Flow memory reclaim mode. */
 181 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 182
 183 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
 184
 185 /* Shared memory between primary and secondary processes. */
 186 struct mlx5_shared_data *mlx5_shared_data;
 187
 188 /* Spinlock for mlx5_shared_data allocation. */
 189 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
 190
 191 /* Process local data for secondary processes. */
 192 static struct mlx5_local_data mlx5_local_data;
 193
 194 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 195                                                 LIST_HEAD_INITIALIZER();
 196 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
 197
 198 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 199 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 200         {
 201                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 202                 .trunk_size = 64,
 203                 .grow_trunk = 3,
 204                 .grow_shift = 2,
 205                 .need_lock = 0,
 206                 .release_mem_en = 1,
 207                 .malloc = rte_malloc_socket,
 208                 .free = rte_free,
 209                 .type = "mlx5_encap_decap_ipool",
 210         },
 211         {
 212                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 213                 .trunk_size = 64,
 214                 .grow_trunk = 3,
 215                 .grow_shift = 2,
 216                 .need_lock = 0,
 217                 .release_mem_en = 1,
 218                 .malloc = rte_malloc_socket,
 219                 .free = rte_free,
 220                 .type = "mlx5_push_vlan_ipool",
 221         },
 222         {
 223                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 224                 .trunk_size = 64,
 225                 .grow_trunk = 3,
 226                 .grow_shift = 2,
 227                 .need_lock = 0,
 228                 .release_mem_en = 1,
 229                 .malloc = rte_malloc_socket,
 230                 .free = rte_free,
 231                 .type = "mlx5_tag_ipool",
 232         },
 233         {
 234                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 235                 .trunk_size = 64,
 236                 .grow_trunk = 3,
 237                 .grow_shift = 2,
 238                 .need_lock = 0,
 239                 .release_mem_en = 1,
 240                 .malloc = rte_malloc_socket,
 241                 .free = rte_free,
 242                 .type = "mlx5_port_id_ipool",
 243         },
 244         {
 245                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 246                 .trunk_size = 64,
 247                 .grow_trunk = 3,
 248                 .grow_shift = 2,
 249                 .need_lock = 0,
 250                 .release_mem_en = 1,
 251                 .malloc = rte_malloc_socket,
 252                 .free = rte_free,
 253                 .type = "mlx5_jump_ipool",
 254         },
 255 #endif
 256         {
 257                 .size = sizeof(struct mlx5_flow_meter),
 258                 .trunk_size = 64,
 259                 .grow_trunk = 3,
 260                 .grow_shift = 2,
 261                 .need_lock = 0,
 262                 .release_mem_en = 1,
 263                 .malloc = rte_malloc_socket,
 264                 .free = rte_free,
 265                 .type = "mlx5_meter_ipool",
 266         },
 267         {
 268                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 269                 .trunk_size = 64,
 270                 .grow_trunk = 3,
 271                 .grow_shift = 2,
 272                 .need_lock = 0,
 273                 .release_mem_en = 1,
 274                 .malloc = rte_malloc_socket,
 275                 .free = rte_free,
 276                 .type = "mlx5_mcp_ipool",
 277         },
 278         {
 279                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 280                 .trunk_size = 64,
 281                 .grow_trunk = 3,
 282                 .grow_shift = 2,
 283                 .need_lock = 0,
 284                 .release_mem_en = 1,
 285                 .malloc = rte_malloc_socket,
 286                 .free = rte_free,
 287                 .type = "mlx5_hrxq_ipool",
 288         },
 289         {
 290                 /*
 291                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 292                  * It set in run time according to PCI function configuration.
 293                  */
 294                 .size = 0,
 295                 .trunk_size = 64,
 296                 .grow_trunk = 3,
 297                 .grow_shift = 2,
 298                 .need_lock = 0,
 299                 .release_mem_en = 1,
 300                 .malloc = rte_malloc_socket,
 301                 .free = rte_free,
 302                 .type = "mlx5_flow_handle_ipool",
 303         },
 304         {
 305                 .size = sizeof(struct rte_flow),
 306                 .trunk_size = 4096,
 307                 .need_lock = 1,
 308                 .release_mem_en = 1,
 309                 .malloc = rte_malloc_socket,
 310                 .free = rte_free,
 311                 .type = "rte_flow_ipool",
 312         },
 313 };
 314
 315
 316 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 317 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 318
 319 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 320
 321 /**
 322  * Allocate ID pool structure.
 323  *
 324  * @param[in] max_id
 325  *   The maximum id can be allocated from the pool.
 326  *
 327  * @return
 328  *   Pointer to pool object, NULL value otherwise.
 329  */
 330 struct mlx5_flow_id_pool *
 331 mlx5_flow_id_pool_alloc(uint32_t max_id)
 332 {
 333         struct mlx5_flow_id_pool *pool;
 334         void *mem;
 335
 336         pool = rte_zmalloc("id pool allocation", sizeof(*pool),
 337                            RTE_CACHE_LINE_SIZE);
 338         if (!pool) {
 339                 DRV_LOG(ERR, "can't allocate id pool");
 340                 rte_errno  = ENOMEM;
 341                 return NULL;
 342         }
 343         mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
 344                           RTE_CACHE_LINE_SIZE);
 345         if (!mem) {
 346                 DRV_LOG(ERR, "can't allocate mem for id pool");
 347                 rte_errno  = ENOMEM;
 348                 goto error;
 349         }
 350         pool->free_arr = mem;
 351         pool->curr = pool->free_arr;
 352         pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
 353         pool->base_index = 0;
 354         pool->max_id = max_id;
 355         return pool;
 356 error:
 357         rte_free(pool);
 358         return NULL;
 359 }
 360
 361 /**
 362  * Release ID pool structure.
 363  *
 364  * @param[in] pool
 365  *   Pointer to flow id pool object to free.
 366  */
 367 void
 368 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
 369 {
 370         rte_free(pool->free_arr);
 371         rte_free(pool);
 372 }
 373
 374 /**
 375  * Generate ID.
 376  *
 377  * @param[in] pool
 378  *   Pointer to flow id pool.
 379  * @param[out] id
 380  *   The generated ID.
 381  *
 382  * @return
 383  *   0 on success, error value otherwise.
 384  */
 385 uint32_t
 386 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
 387 {
 388         if (pool->curr == pool->free_arr) {
 389                 if (pool->base_index == pool->max_id) {
 390                         rte_errno  = ENOMEM;
 391                         DRV_LOG(ERR, "no free id");
 392                         return -rte_errno;
 393                 }
 394                 *id = ++pool->base_index;
 395                 return 0;
 396         }
 397         *id = *(--pool->curr);
 398         return 0;
 399 }
 400
 401 /**
 402  * Release ID.
 403  *
 404  * @param[in] pool
 405  *   Pointer to flow id pool.
 406  * @param[out] id
 407  *   The generated ID.
 408  *
 409  * @return
 410  *   0 on success, error value otherwise.
 411  */
 412 uint32_t
 413 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
 414 {
 415         uint32_t size;
 416         uint32_t size2;
 417         void *mem;
 418
 419         if (pool->curr == pool->last) {
 420                 size = pool->curr - pool->free_arr;
 421                 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
 422                 MLX5_ASSERT(size2 > size);
 423                 mem = rte_malloc("", size2 * sizeof(uint32_t), 0);
 424                 if (!mem) {
 425                         DRV_LOG(ERR, "can't allocate mem for id pool");
 426                         rte_errno  = ENOMEM;
 427                         return -rte_errno;
 428                 }
 429                 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
 430                 rte_free(pool->free_arr);
 431                 pool->free_arr = mem;
 432                 pool->curr = pool->free_arr + size;
 433                 pool->last = pool->free_arr + size2;
 434         }
 435         *pool->curr = id;
 436         pool->curr++;
 437         return 0;
 438 }
 439
 440 /**
 441  * Initialize the shared aging list information per port.
 442  *
 443  * @param[in] sh
 444  *   Pointer to mlx5_dev_ctx_shared object.
 445  */
 446 static void
 447 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 448 {
 449         uint32_t i;
 450         struct mlx5_age_info *age_info;
 451
 452         for (i = 0; i < sh->max_port; i++) {
 453                 age_info = &sh->port[i].age_info;
 454                 age_info->flags = 0;
 455                 TAILQ_INIT(&age_info->aged_counters);
 456                 rte_spinlock_init(&age_info->aged_sl);
 457                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 458         }
 459 }
 460
 461 /**
 462  * Initialize the counters management structure.
 463  *
 464  * @param[in] sh
 465  *   Pointer to mlx5_dev_ctx_shared object to free
 466  */
 467 static void
 468 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 469 {
 470         int i;
 471
 472         memset(&sh->cmng, 0, sizeof(sh->cmng));
 473         TAILQ_INIT(&sh->cmng.flow_counters);
 474         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 475                 sh->cmng.ccont[i].min_id = MLX5_CNT_BATCH_OFFSET;
 476                 sh->cmng.ccont[i].max_id = -1;
 477                 sh->cmng.ccont[i].last_pool_idx = POOL_IDX_INVALID;
 478                 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
 479                 rte_spinlock_init(&sh->cmng.ccont[i].resize_sl);
 480                 TAILQ_INIT(&sh->cmng.ccont[i].counters);
 481                 rte_spinlock_init(&sh->cmng.ccont[i].csl);
 482         }
 483 }
 484
 485 /**
 486  * Destroy all the resources allocated for a counter memory management.
 487  *
 488  * @param[in] mng
 489  *   Pointer to the memory management structure.
 490  */
 491 static void
 492 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 493 {
 494         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 495
 496         LIST_REMOVE(mng, next);
 497         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 498         claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
 499         rte_free(mem);
 500 }
 501
 502 /**
 503  * Close and release all the resources of the counters management.
 504  *
 505  * @param[in] sh
 506  *   Pointer to mlx5_dev_ctx_shared object to free.
 507  */
 508 static void
 509 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 510 {
 511         struct mlx5_counter_stats_mem_mng *mng;
 512         int i;
 513         int j;
 514         int retries = 1024;
 515
 516         rte_errno = 0;
 517         while (--retries) {
 518                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 519                 if (rte_errno != EINPROGRESS)
 520                         break;
 521                 rte_pause();
 522         }
 523         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 524                 struct mlx5_flow_counter_pool *pool;
 525                 uint32_t batch = !!(i > 1);
 526
 527                 if (!sh->cmng.ccont[i].pools)
 528                         continue;
 529                 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 530                 while (pool) {
 531                         if (batch && pool->min_dcs)
 532                                 claim_zero(mlx5_devx_cmd_destroy
 533                                                                (pool->min_dcs));
 534                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 535                                 if (MLX5_POOL_GET_CNT(pool, j)->action)
 536                                         claim_zero
 537                                          (mlx5_glue->destroy_flow_action
 538                                           (MLX5_POOL_GET_CNT
 539                                           (pool, j)->action));
 540                                 if (!batch && MLX5_GET_POOL_CNT_EXT
 541                                     (pool, j)->dcs)
 542                                         claim_zero(mlx5_devx_cmd_destroy
 543                                                    (MLX5_GET_POOL_CNT_EXT
 544                                                     (pool, j)->dcs));
 545                         }
 546                         TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, next);
 547                         rte_free(pool);
 548                         pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 549                 }
 550                 rte_free(sh->cmng.ccont[i].pools);
 551         }
 552         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 553         while (mng) {
 554                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 555                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 556         }
 557         memset(&sh->cmng, 0, sizeof(sh->cmng));
 558 }
 559
 560 /**
 561  * Initialize the flow resources' indexed mempool.
 562  *
 563  * @param[in] sh
 564  *   Pointer to mlx5_dev_ctx_shared object.
 565  * @param[in] sh
 566  *   Pointer to user dev config.
 567  */
 568 static void
 569 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 570                        const struct mlx5_dev_config *config)
 571 {
 572         uint8_t i;
 573         struct mlx5_indexed_pool_config cfg;
 574
 575         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 576                 cfg = mlx5_ipool_cfg[i];
 577                 switch (i) {
 578                 default:
 579                         break;
 580                 /*
 581                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 582                  * according to PCI function flow configuration.
 583                  */
 584                 case MLX5_IPOOL_MLX5_FLOW:
 585                         cfg.size = config->dv_flow_en ?
 586                                 sizeof(struct mlx5_flow_handle) :
 587                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 588                         break;
 589                 }
 590                 if (config->reclaim_mode)
 591                         cfg.release_mem_en = 1;
 592                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 593         }
 594 }
 595
 596 /**
 597  * Release the flow resources' indexed mempool.
 598  *
 599  * @param[in] sh
 600  *   Pointer to mlx5_dev_ctx_shared object.
 601  */
 602 static void
 603 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 604 {
 605         uint8_t i;
 606
 607         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 608                 mlx5_ipool_destroy(sh->ipool[i]);
 609 }
 610
 611 /**
 612  * Allocate shared device context. If there is multiport device the
 613  * master and representors will share this context, if there is single
 614  * port dedicated device, the context will be used by only given
 615  * port due to unification.
 616  *
 617  * Routine first searches the context for the specified device name,
 618  * if found the shared context assumed and reference counter is incremented.
 619  * If no context found the new one is created and initialized with specified
 620  * device context and parameters.
 621  *
 622  * @param[in] spawn
 623  *   Pointer to the device attributes (name, port, etc).
 624  * @param[in] config
 625  *   Pointer to device configuration structure.
 626  *
 627  * @return
 628  *   Pointer to mlx5_dev_ctx_shared object on success,
 629  *   otherwise NULL and rte_errno is set.
 630  */
 631 struct mlx5_dev_ctx_shared *
 632 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
 633                            const struct mlx5_dev_config *config)
 634 {
 635         struct mlx5_dev_ctx_shared *sh;
 636         int err = 0;
 637         uint32_t i;
 638         struct mlx5_devx_tis_attr tis_attr = { 0 };
 639
 640         MLX5_ASSERT(spawn);
 641         /* Secondary process should not create the shared context. */
 642         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 643         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 644         /* Search for IB context by device name. */
 645         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
 646                 if (!strcmp(sh->ibdev_name,
 647                         mlx5_os_get_dev_device_name(spawn->phys_dev))) {
 648                         sh->refcnt++;
 649                         goto exit;
 650                 }
 651         }
 652         /* No device found, we have to create new shared context. */
 653         MLX5_ASSERT(spawn->max_port);
 654         sh = rte_zmalloc("ethdev shared ib context",
 655                          sizeof(struct mlx5_dev_ctx_shared) +
 656                          spawn->max_port *
 657                          sizeof(struct mlx5_dev_shared_port),
 658                          RTE_CACHE_LINE_SIZE);
 659         if (!sh) {
 660                 DRV_LOG(ERR, "shared context allocation failure");
 661                 rte_errno  = ENOMEM;
 662                 goto exit;
 663         }
 664         err = mlx5_os_open_device(spawn, config, sh);
 665         if (!sh->ctx)
 666                 goto error;
 667         err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
 668         if (err) {
 669                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
 670                 goto error;
 671         }
 672         sh->refcnt = 1;
 673         sh->max_port = spawn->max_port;
 674         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
 675                 sizeof(sh->ibdev_name) - 1);
 676         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
 677                 sizeof(sh->ibdev_path) - 1);
 678         /*
 679          * Setting port_id to max unallowed value means
 680          * there is no interrupt subhandler installed for
 681          * the given port index i.
 682          */
 683         for (i = 0; i < sh->max_port; i++) {
 684                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 685                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
 686         }
 687         sh->pd = mlx5_glue->alloc_pd(sh->ctx);
 688         if (sh->pd == NULL) {
 689                 DRV_LOG(ERR, "PD allocation failure");
 690                 err = ENOMEM;
 691                 goto error;
 692         }
 693         if (sh->devx) {
 694                 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
 695                 if (err) {
 696                         DRV_LOG(ERR, "Fail to extract pdn from PD");
 697                         goto error;
 698                 }
 699                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
 700                 if (!sh->td) {
 701                         DRV_LOG(ERR, "TD allocation failure");
 702                         err = ENOMEM;
 703                         goto error;
 704                 }
 705                 tis_attr.transport_domain = sh->td->id;
 706                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
 707                 if (!sh->tis) {
 708                         DRV_LOG(ERR, "TIS allocation failure");
 709                         err = ENOMEM;
 710                         goto error;
 711                 }
 712                 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, 0);
 713                 if (!sh->tx_uar) {
 714                         DRV_LOG(ERR, "Failed to allocate DevX UAR.");
 715                         err = ENOMEM;
 716                         goto error;
 717                 }
 718         }
 719         sh->flow_id_pool = mlx5_flow_id_pool_alloc
 720                                         ((1 << HAIRPIN_FLOW_ID_BITS) - 1);
 721         if (!sh->flow_id_pool) {
 722                 DRV_LOG(ERR, "can't create flow id pool");
 723                 err = ENOMEM;
 724                 goto error;
 725         }
 726 #ifndef RTE_ARCH_64
 727         /* Initialize UAR access locks for 32bit implementations. */
 728         rte_spinlock_init(&sh->uar_lock_cq);
 729         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
 730                 rte_spinlock_init(&sh->uar_lock[i]);
 731 #endif
 732         /*
 733          * Once the device is added to the list of memory event
 734          * callback, its global MR cache table cannot be expanded
 735          * on the fly because of deadlock. If it overflows, lookup
 736          * should be done by searching MR list linearly, which is slow.
 737          *
 738          * At this point the device is not added to the memory
 739          * event list yet, context is just being created.
 740          */
 741         err = mlx5_mr_btree_init(&sh->share_cache.cache,
 742                                  MLX5_MR_BTREE_CACHE_N * 2,
 743                                  spawn->pci_dev->device.numa_node);
 744         if (err) {
 745                 err = rte_errno;
 746                 goto error;
 747         }
 748         mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
 749                               &sh->share_cache.dereg_mr_cb);
 750         mlx5_os_dev_shared_handler_install(sh);
 751         sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
 752         if (!sh->cnt_id_tbl) {
 753                 err = rte_errno;
 754                 goto error;
 755         }
 756         mlx5_flow_aging_init(sh);
 757         mlx5_flow_counters_mng_init(sh);
 758         mlx5_flow_ipool_create(sh, config);
 759         /* Add device to memory callback list. */
 760         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 761         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
 762                          sh, mem_event_cb);
 763         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 764         /* Add context to the global device list. */
 765         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
 766 exit:
 767         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 768         return sh;
 769 error:
 770         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 771         MLX5_ASSERT(sh);
 772         if (sh->cnt_id_tbl) {
 773                 mlx5_l3t_destroy(sh->cnt_id_tbl);
 774                 sh->cnt_id_tbl = NULL;
 775         }
 776         if (sh->tx_uar) {
 777                 mlx5_glue->devx_free_uar(sh->tx_uar);
 778                 sh->tx_uar = NULL;
 779         }
 780         if (sh->tis)
 781                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 782         if (sh->td)
 783                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 784         if (sh->pd)
 785                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 786         if (sh->ctx)
 787                 claim_zero(mlx5_glue->close_device(sh->ctx));
 788         if (sh->flow_id_pool)
 789                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 790         rte_free(sh);
 791         MLX5_ASSERT(err > 0);
 792         rte_errno = err;
 793         return NULL;
 794 }
 795
 796 /**
 797  * Free shared IB device context. Decrement counter and if zero free
 798  * all allocated resources and close handles.
 799  *
 800  * @param[in] sh
 801  *   Pointer to mlx5_dev_ctx_shared object to free
 802  */
 803 void
 804 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
 805 {
 806         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 807 #ifdef RTE_LIBRTE_MLX5_DEBUG
 808         /* Check the object presence in the list. */
 809         struct mlx5_dev_ctx_shared *lctx;
 810
 811         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
 812                 if (lctx == sh)
 813                         break;
 814         MLX5_ASSERT(lctx);
 815         if (lctx != sh) {
 816                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
 817                 goto exit;
 818         }
 819 #endif
 820         MLX5_ASSERT(sh);
 821         MLX5_ASSERT(sh->refcnt);
 822         /* Secondary process should not free the shared context. */
 823         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 824         if (--sh->refcnt)
 825                 goto exit;
 826         /* Remove from memory callback device list. */
 827         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 828         LIST_REMOVE(sh, mem_event_cb);
 829         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 830         /* Release created Memory Regions. */
 831         mlx5_mr_release_cache(&sh->share_cache);
 832         /* Remove context from the global device list. */
 833         LIST_REMOVE(sh, next);
 834         /*
 835          *  Ensure there is no async event handler installed.
 836          *  Only primary process handles async device events.
 837          **/
 838         mlx5_flow_counters_mng_close(sh);
 839         mlx5_flow_ipool_destroy(sh);
 840         mlx5_os_dev_shared_handler_uninstall(sh);
 841         if (sh->cnt_id_tbl) {
 842                 mlx5_l3t_destroy(sh->cnt_id_tbl);
 843                 sh->cnt_id_tbl = NULL;
 844         }
 845         if (sh->tx_uar) {
 846                 mlx5_glue->devx_free_uar(sh->tx_uar);
 847                 sh->tx_uar = NULL;
 848         }
 849         if (sh->pd)
 850                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 851         if (sh->tis)
 852                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 853         if (sh->td)
 854                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 855         if (sh->ctx)
 856                 claim_zero(mlx5_glue->close_device(sh->ctx));
 857         if (sh->flow_id_pool)
 858                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 859         rte_free(sh);
 860 exit:
 861         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 862 }
 863
 864 /**
 865  * Destroy table hash list and all the root entries per domain.
 866  *
 867  * @param[in] priv
 868  *   Pointer to the private device data structure.
 869  */
 870 void
 871 mlx5_free_table_hash_list(struct mlx5_priv *priv)
 872 {
 873         struct mlx5_dev_ctx_shared *sh = priv->sh;
 874         struct mlx5_flow_tbl_data_entry *tbl_data;
 875         union mlx5_flow_tbl_key table_key = {
 876                 {
 877                         .table_id = 0,
 878                         .reserved = 0,
 879                         .domain = 0,
 880                         .direction = 0,
 881                 }
 882         };
 883         struct mlx5_hlist_entry *pos;
 884
 885         if (!sh->flow_tbls)
 886                 return;
 887         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 888         if (pos) {
 889                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 890                                         entry);
 891                 MLX5_ASSERT(tbl_data);
 892                 mlx5_hlist_remove(sh->flow_tbls, pos);
 893                 rte_free(tbl_data);
 894         }
 895         table_key.direction = 1;
 896         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 897         if (pos) {
 898                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 899                                         entry);
 900                 MLX5_ASSERT(tbl_data);
 901                 mlx5_hlist_remove(sh->flow_tbls, pos);
 902                 rte_free(tbl_data);
 903         }
 904         table_key.direction = 0;
 905         table_key.domain = 1;
 906         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 907         if (pos) {
 908                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 909                                         entry);
 910                 MLX5_ASSERT(tbl_data);
 911                 mlx5_hlist_remove(sh->flow_tbls, pos);
 912                 rte_free(tbl_data);
 913         }
 914         mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
 915 }
 916
 917 /**
 918  * Initialize flow table hash list and create the root tables entry
 919  * for each domain.
 920  *
 921  * @param[in] priv
 922  *   Pointer to the private device data structure.
 923  *
 924  * @return
 925  *   Zero on success, positive error code otherwise.
 926  */
 927 int
 928 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
 929 {
 930         struct mlx5_dev_ctx_shared *sh = priv->sh;
 931         char s[MLX5_HLIST_NAMESIZE];
 932         int err = 0;
 933
 934         MLX5_ASSERT(sh);
 935         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
 936         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
 937         if (!sh->flow_tbls) {
 938                 DRV_LOG(ERR, "flow tables with hash creation failed.");
 939                 err = ENOMEM;
 940                 return err;
 941         }
 942 #ifndef HAVE_MLX5DV_DR
 943         /*
 944          * In case we have not DR support, the zero tables should be created
 945          * because DV expect to see them even if they cannot be created by
 946          * RDMA-CORE.
 947          */
 948         union mlx5_flow_tbl_key table_key = {
 949                 {
 950                         .table_id = 0,
 951                         .reserved = 0,
 952                         .domain = 0,
 953                         .direction = 0,
 954                 }
 955         };
 956         struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL,
 957                                                           sizeof(*tbl_data), 0);
 958
 959         if (!tbl_data) {
 960                 err = ENOMEM;
 961                 goto error;
 962         }
 963         tbl_data->entry.key = table_key.v64;
 964         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 965         if (err)
 966                 goto error;
 967         rte_atomic32_init(&tbl_data->tbl.refcnt);
 968         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 969         table_key.direction = 1;
 970         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 971         if (!tbl_data) {
 972                 err = ENOMEM;
 973                 goto error;
 974         }
 975         tbl_data->entry.key = table_key.v64;
 976         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 977         if (err)
 978                 goto error;
 979         rte_atomic32_init(&tbl_data->tbl.refcnt);
 980         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 981         table_key.direction = 0;
 982         table_key.domain = 1;
 983         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 984         if (!tbl_data) {
 985                 err = ENOMEM;
 986                 goto error;
 987         }
 988         tbl_data->entry.key = table_key.v64;
 989         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 990         if (err)
 991                 goto error;
 992         rte_atomic32_init(&tbl_data->tbl.refcnt);
 993         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 994         return err;
 995 error:
 996         mlx5_free_table_hash_list(priv);
 997 #endif /* HAVE_MLX5DV_DR */
 998         return err;
 999 }
1000
1001 /**
1002  * Initialize shared data between primary and secondary process.
1003  *
1004  * A memzone is reserved by primary process and secondary processes attach to
1005  * the memzone.
1006  *
1007  * @return
1008  *   0 on success, a negative errno value otherwise and rte_errno is set.
1009  */
1010 static int
1011 mlx5_init_shared_data(void)
1012 {
1013         const struct rte_memzone *mz;
1014         int ret = 0;
1015
1016         rte_spinlock_lock(&mlx5_shared_data_lock);
1017         if (mlx5_shared_data == NULL) {
1018                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
1019                         /* Allocate shared memory. */
1020                         mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
1021                                                  sizeof(*mlx5_shared_data),
1022                                                  SOCKET_ID_ANY, 0);
1023                         if (mz == NULL) {
1024                                 DRV_LOG(ERR,
1025                                         "Cannot allocate mlx5 shared data");
1026                                 ret = -rte_errno;
1027                                 goto error;
1028                         }
1029                         mlx5_shared_data = mz->addr;
1030                         memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
1031                         rte_spinlock_init(&mlx5_shared_data->lock);
1032                 } else {
1033                         /* Lookup allocated shared memory. */
1034                         mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
1035                         if (mz == NULL) {
1036                                 DRV_LOG(ERR,
1037                                         "Cannot attach mlx5 shared data");
1038                                 ret = -rte_errno;
1039                                 goto error;
1040                         }
1041                         mlx5_shared_data = mz->addr;
1042                         memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
1043                 }
1044         }
1045 error:
1046         rte_spinlock_unlock(&mlx5_shared_data_lock);
1047         return ret;
1048 }
1049
1050 /**
1051  * Retrieve integer value from environment variable.
1052  *
1053  * @param[in] name
1054  *   Environment variable name.
1055  *
1056  * @return
1057  *   Integer value, 0 if the variable is not set.
1058  */
1059 int
1060 mlx5_getenv_int(const char *name)
1061 {
1062         const char *val = getenv(name);
1063
1064         if (val == NULL)
1065                 return 0;
1066         return atoi(val);
1067 }
1068
1069 /**
1070  * DPDK callback to add udp tunnel port
1071  *
1072  * @param[in] dev
1073  *   A pointer to eth_dev
1074  * @param[in] udp_tunnel
1075  *   A pointer to udp tunnel
1076  *
1077  * @return
1078  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1079  */
1080 int
1081 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1082                          struct rte_eth_udp_tunnel *udp_tunnel)
1083 {
1084         MLX5_ASSERT(udp_tunnel != NULL);
1085         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1086             udp_tunnel->udp_port == 4789)
1087                 return 0;
1088         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1089             udp_tunnel->udp_port == 4790)
1090                 return 0;
1091         return -ENOTSUP;
1092 }
1093
1094 /**
1095  * Initialize process private data structure.
1096  *
1097  * @param dev
1098  *   Pointer to Ethernet device structure.
1099  *
1100  * @return
1101  *   0 on success, a negative errno value otherwise and rte_errno is set.
1102  */
1103 int
1104 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1105 {
1106         struct mlx5_priv *priv = dev->data->dev_private;
1107         struct mlx5_proc_priv *ppriv;
1108         size_t ppriv_size;
1109
1110         /*
1111          * UAR register table follows the process private structure. BlueFlame
1112          * registers for Tx queues are stored in the table.
1113          */
1114         ppriv_size =
1115                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1116         ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
1117                                   RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1118         if (!ppriv) {
1119                 rte_errno = ENOMEM;
1120                 return -rte_errno;
1121         }
1122         ppriv->uar_table_sz = ppriv_size;
1123         dev->process_private = ppriv;
1124         return 0;
1125 }
1126
1127 /**
1128  * Un-initialize process private data structure.
1129  *
1130  * @param dev
1131  *   Pointer to Ethernet device structure.
1132  */
1133 static void
1134 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1135 {
1136         if (!dev->process_private)
1137                 return;
1138         rte_free(dev->process_private);
1139         dev->process_private = NULL;
1140 }
1141
1142 /**
1143  * DPDK callback to close the device.
1144  *
1145  * Destroy all queues and objects, free memory.
1146  *
1147  * @param dev
1148  *   Pointer to Ethernet device structure.
1149  */
1150 void
1151 mlx5_dev_close(struct rte_eth_dev *dev)
1152 {
1153         struct mlx5_priv *priv = dev->data->dev_private;
1154         unsigned int i;
1155         int ret;
1156
1157         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1158                 /* Check if process_private released. */
1159                 if (!dev->process_private)
1160                         return;
1161                 mlx5_tx_uar_uninit_secondary(dev);
1162                 mlx5_proc_priv_uninit(dev);
1163                 rte_eth_dev_release_port(dev);
1164                 return;
1165         }
1166         if (!priv->sh)
1167                 return;
1168         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1169                 dev->data->port_id,
1170                 ((priv->sh->ctx != NULL) ?
1171                 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1172         /*
1173          * If default mreg copy action is removed at the stop stage,
1174          * the search will return none and nothing will be done anymore.
1175          */
1176         mlx5_flow_stop_default(dev);
1177         mlx5_traffic_disable(dev);
1178         /*
1179          * If all the flows are already flushed in the device stop stage,
1180          * then this will return directly without any action.
1181          */
1182         mlx5_flow_list_flush(dev, &priv->flows, true);
1183         mlx5_flow_meter_flush(dev, NULL);
1184         /* Free the intermediate buffers for flow creation. */
1185         mlx5_flow_free_intermediate(dev);
1186         /* Prevent crashes when queues are still in use. */
1187         dev->rx_pkt_burst = removed_rx_burst;
1188         dev->tx_pkt_burst = removed_tx_burst;
1189         rte_wmb();
1190         /* Disable datapath on secondary process. */
1191         mlx5_mp_req_stop_rxtx(dev);
1192         if (priv->rxqs != NULL) {
1193                 /* XXX race condition if mlx5_rx_burst() is still running. */
1194                 usleep(1000);
1195                 for (i = 0; (i != priv->rxqs_n); ++i)
1196                         mlx5_rxq_release(dev, i);
1197                 priv->rxqs_n = 0;
1198                 priv->rxqs = NULL;
1199         }
1200         if (priv->txqs != NULL) {
1201                 /* XXX race condition if mlx5_tx_burst() is still running. */
1202                 usleep(1000);
1203                 for (i = 0; (i != priv->txqs_n); ++i)
1204                         mlx5_txq_release(dev, i);
1205                 priv->txqs_n = 0;
1206                 priv->txqs = NULL;
1207         }
1208         mlx5_proc_priv_uninit(dev);
1209         if (priv->mreg_cp_tbl)
1210                 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1211         mlx5_mprq_free_mp(dev);
1212         mlx5_os_free_shared_dr(priv);
1213         if (priv->rss_conf.rss_key != NULL)
1214                 rte_free(priv->rss_conf.rss_key);
1215         if (priv->reta_idx != NULL)
1216                 rte_free(priv->reta_idx);
1217         if (priv->config.vf)
1218                 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1219                                        dev->data->mac_addrs,
1220                                        MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1221         if (priv->nl_socket_route >= 0)
1222                 close(priv->nl_socket_route);
1223         if (priv->nl_socket_rdma >= 0)
1224                 close(priv->nl_socket_rdma);
1225         if (priv->vmwa_context)
1226                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1227         ret = mlx5_hrxq_verify(dev);
1228         if (ret)
1229                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1230                         dev->data->port_id);
1231         ret = mlx5_ind_table_obj_verify(dev);
1232         if (ret)
1233                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1234                         dev->data->port_id);
1235         ret = mlx5_rxq_obj_verify(dev);
1236         if (ret)
1237                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1238                         dev->data->port_id);
1239         ret = mlx5_rxq_verify(dev);
1240         if (ret)
1241                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1242                         dev->data->port_id);
1243         ret = mlx5_txq_obj_verify(dev);
1244         if (ret)
1245                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1246                         dev->data->port_id);
1247         ret = mlx5_txq_verify(dev);
1248         if (ret)
1249                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1250                         dev->data->port_id);
1251         ret = mlx5_flow_verify(dev);
1252         if (ret)
1253                 DRV_LOG(WARNING, "port %u some flows still remain",
1254                         dev->data->port_id);
1255         /*
1256          * Free the shared context in last turn, because the cleanup
1257          * routines above may use some shared fields, like
1258          * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1259          * ifindex if Netlink fails.
1260          */
1261         mlx5_free_shared_dev_ctx(priv->sh);
1262         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1263                 unsigned int c = 0;
1264                 uint16_t port_id;
1265
1266                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1267                         struct mlx5_priv *opriv =
1268                                 rte_eth_devices[port_id].data->dev_private;
1269
1270                         if (!opriv ||
1271                             opriv->domain_id != priv->domain_id ||
1272                             &rte_eth_devices[port_id] == dev)
1273                                 continue;
1274                         ++c;
1275                         break;
1276                 }
1277                 if (!c)
1278                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1279         }
1280         memset(priv, 0, sizeof(*priv));
1281         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1282         /*
1283          * Reset mac_addrs to NULL such that it is not freed as part of
1284          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1285          * it is freed when dev_private is freed.
1286          */
1287         dev->data->mac_addrs = NULL;
1288 }
1289
1290 /**
1291  * Verify and store value for device argument.
1292  *
1293  * @param[in] key
1294  *   Key argument to verify.
1295  * @param[in] val
1296  *   Value associated with key.
1297  * @param opaque
1298  *   User data.
1299  *
1300  * @return
1301  *   0 on success, a negative errno value otherwise and rte_errno is set.
1302  */
1303 static int
1304 mlx5_args_check(const char *key, const char *val, void *opaque)
1305 {
1306         struct mlx5_dev_config *config = opaque;
1307         unsigned long mod;
1308         signed long tmp;
1309
1310         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1311         if (!strcmp(MLX5_REPRESENTOR, key))
1312                 return 0;
1313         errno = 0;
1314         tmp = strtol(val, NULL, 0);
1315         if (errno) {
1316                 rte_errno = errno;
1317                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1318                 return -rte_errno;
1319         }
1320         if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1321                 /* Negative values are acceptable for some keys only. */
1322                 rte_errno = EINVAL;
1323                 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1324                 return -rte_errno;
1325         }
1326         mod = tmp >= 0 ? tmp : -tmp;
1327         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1328                 config->cqe_comp = !!tmp;
1329         } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1330                 config->cqe_pad = !!tmp;
1331         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1332                 config->hw_padding = !!tmp;
1333         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1334                 config->mprq.enabled = !!tmp;
1335         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1336                 config->mprq.stride_num_n = tmp;
1337         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1338                 config->mprq.stride_size_n = tmp;
1339         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1340                 config->mprq.max_memcpy_len = tmp;
1341         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1342                 config->mprq.min_rxqs_num = tmp;
1343         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1344                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1345                                  " converted to txq_inline_max", key);
1346                 config->txq_inline_max = tmp;
1347         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1348                 config->txq_inline_max = tmp;
1349         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1350                 config->txq_inline_min = tmp;
1351         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1352                 config->txq_inline_mpw = tmp;
1353         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1354                 config->txqs_inline = tmp;
1355         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1356                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1357         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1358                 config->mps = !!tmp;
1359         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1360                 if (tmp != MLX5_TXDB_CACHED &&
1361                     tmp != MLX5_TXDB_NCACHED &&
1362                     tmp != MLX5_TXDB_HEURISTIC) {
1363                         DRV_LOG(ERR, "invalid Tx doorbell "
1364                                      "mapping parameter");
1365                         rte_errno = EINVAL;
1366                         return -rte_errno;
1367                 }
1368                 config->dbnc = tmp;
1369         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1370                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1371         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1372                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1373                                  " converted to txq_inline_mpw", key);
1374                 config->txq_inline_mpw = tmp;
1375         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1376                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1377         } else if (strcmp(MLX5_TX_PP, key) == 0) {
1378                 if (!mod) {
1379                         DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1380                         rte_errno = EINVAL;
1381                         return -rte_errno;
1382                 }
1383                 config->tx_pp = tmp;
1384         } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1385                 config->tx_skew = tmp;
1386         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1387                 config->rx_vec_en = !!tmp;
1388         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1389                 config->l3_vxlan_en = !!tmp;
1390         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1391                 config->vf_nl_en = !!tmp;
1392         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1393                 config->dv_esw_en = !!tmp;
1394         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1395                 config->dv_flow_en = !!tmp;
1396         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1397                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1398                     tmp != MLX5_XMETA_MODE_META16 &&
1399                     tmp != MLX5_XMETA_MODE_META32) {
1400                         DRV_LOG(ERR, "invalid extensive "
1401                                      "metadata parameter");
1402                         rte_errno = EINVAL;
1403                         return -rte_errno;
1404                 }
1405                 config->dv_xmeta_en = tmp;
1406         } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1407                 config->lacp_by_user = !!tmp;
1408         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1409                 config->mr_ext_memseg_en = !!tmp;
1410         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1411                 config->max_dump_files_num = tmp;
1412         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1413                 config->lro.timeout = tmp;
1414         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1415                 DRV_LOG(DEBUG, "class argument is %s.", val);
1416         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1417                 config->log_hp_size = tmp;
1418         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1419                 if (tmp != MLX5_RCM_NONE &&
1420                     tmp != MLX5_RCM_LIGHT &&
1421                     tmp != MLX5_RCM_AGGR) {
1422                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1423                         rte_errno = EINVAL;
1424                         return -rte_errno;
1425                 }
1426                 config->reclaim_mode = tmp;
1427         } else {
1428                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1429                 rte_errno = EINVAL;
1430                 return -rte_errno;
1431         }
1432         return 0;
1433 }
1434
1435 /**
1436  * Parse device parameters.
1437  *
1438  * @param config
1439  *   Pointer to device configuration structure.
1440  * @param devargs
1441  *   Device arguments structure.
1442  *
1443  * @return
1444  *   0 on success, a negative errno value otherwise and rte_errno is set.
1445  */
1446 int
1447 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1448 {
1449         const char **params = (const char *[]){
1450                 MLX5_RXQ_CQE_COMP_EN,
1451                 MLX5_RXQ_CQE_PAD_EN,
1452                 MLX5_RXQ_PKT_PAD_EN,
1453                 MLX5_RX_MPRQ_EN,
1454                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1455                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1456                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1457                 MLX5_RXQS_MIN_MPRQ,
1458                 MLX5_TXQ_INLINE,
1459                 MLX5_TXQ_INLINE_MIN,
1460                 MLX5_TXQ_INLINE_MAX,
1461                 MLX5_TXQ_INLINE_MPW,
1462                 MLX5_TXQS_MIN_INLINE,
1463                 MLX5_TXQS_MAX_VEC,
1464                 MLX5_TXQ_MPW_EN,
1465                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1466                 MLX5_TXQ_MAX_INLINE_LEN,
1467                 MLX5_TX_DB_NC,
1468                 MLX5_TX_PP,
1469                 MLX5_TX_SKEW,
1470                 MLX5_TX_VEC_EN,
1471                 MLX5_RX_VEC_EN,
1472                 MLX5_L3_VXLAN_EN,
1473                 MLX5_VF_NL_EN,
1474                 MLX5_DV_ESW_EN,
1475                 MLX5_DV_FLOW_EN,
1476                 MLX5_DV_XMETA_EN,
1477                 MLX5_LACP_BY_USER,
1478                 MLX5_MR_EXT_MEMSEG_EN,
1479                 MLX5_REPRESENTOR,
1480                 MLX5_MAX_DUMP_FILES_NUM,
1481                 MLX5_LRO_TIMEOUT_USEC,
1482                 MLX5_CLASS_ARG_NAME,
1483                 MLX5_HP_BUF_SIZE,
1484                 MLX5_RECLAIM_MEM,
1485                 NULL,
1486         };
1487         struct rte_kvargs *kvlist;
1488         int ret = 0;
1489         int i;
1490
1491         if (devargs == NULL)
1492                 return 0;
1493         /* Following UGLY cast is done to pass checkpatch. */
1494         kvlist = rte_kvargs_parse(devargs->args, params);
1495         if (kvlist == NULL) {
1496                 rte_errno = EINVAL;
1497                 return -rte_errno;
1498         }
1499         /* Process parameters. */
1500         for (i = 0; (params[i] != NULL); ++i) {
1501                 if (rte_kvargs_count(kvlist, params[i])) {
1502                         ret = rte_kvargs_process(kvlist, params[i],
1503                                                  mlx5_args_check, config);
1504                         if (ret) {
1505                                 rte_errno = EINVAL;
1506                                 rte_kvargs_free(kvlist);
1507                                 return -rte_errno;
1508                         }
1509                 }
1510         }
1511         rte_kvargs_free(kvlist);
1512         return 0;
1513 }
1514
1515 /**
1516  * PMD global initialization.
1517  *
1518  * Independent from individual device, this function initializes global
1519  * per-PMD data structures distinguishing primary and secondary processes.
1520  * Hence, each initialization is called once per a process.
1521  *
1522  * @return
1523  *   0 on success, a negative errno value otherwise and rte_errno is set.
1524  */
1525 int
1526 mlx5_init_once(void)
1527 {
1528         struct mlx5_shared_data *sd;
1529         struct mlx5_local_data *ld = &mlx5_local_data;
1530         int ret = 0;
1531
1532         if (mlx5_init_shared_data())
1533                 return -rte_errno;
1534         sd = mlx5_shared_data;
1535         MLX5_ASSERT(sd);
1536         rte_spinlock_lock(&sd->lock);
1537         switch (rte_eal_process_type()) {
1538         case RTE_PROC_PRIMARY:
1539                 if (sd->init_done)
1540                         break;
1541                 LIST_INIT(&sd->mem_event_cb_list);
1542                 rte_rwlock_init(&sd->mem_event_rwlock);
1543                 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1544                                                 mlx5_mr_mem_event_cb, NULL);
1545                 ret = mlx5_mp_init_primary(MLX5_MP_NAME,
1546                                            mlx5_mp_primary_handle);
1547                 if (ret)
1548                         goto out;
1549                 sd->init_done = true;
1550                 break;
1551         case RTE_PROC_SECONDARY:
1552                 if (ld->init_done)
1553                         break;
1554                 ret = mlx5_mp_init_secondary(MLX5_MP_NAME,
1555                                              mlx5_mp_secondary_handle);
1556                 if (ret)
1557                         goto out;
1558                 ++sd->secondary_cnt;
1559                 ld->init_done = true;
1560                 break;
1561         default:
1562                 break;
1563         }
1564 out:
1565         rte_spinlock_unlock(&sd->lock);
1566         return ret;
1567 }
1568
1569 /**
1570  * Configures the minimal amount of data to inline into WQE
1571  * while sending packets.
1572  *
1573  * - the txq_inline_min has the maximal priority, if this
1574  *   key is specified in devargs
1575  * - if DevX is enabled the inline mode is queried from the
1576  *   device (HCA attributes and NIC vport context if needed).
1577  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1578  *   and none (0 bytes) for other NICs
1579  *
1580  * @param spawn
1581  *   Verbs device parameters (name, port, switch_info) to spawn.
1582  * @param config
1583  *   Device configuration parameters.
1584  */
1585 void
1586 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1587                     struct mlx5_dev_config *config)
1588 {
1589         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1590                 /* Application defines size of inlined data explicitly. */
1591                 switch (spawn->pci_dev->id.device_id) {
1592                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1593                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1594                         if (config->txq_inline_min <
1595                                        (int)MLX5_INLINE_HSIZE_L2) {
1596                                 DRV_LOG(DEBUG,
1597                                         "txq_inline_mix aligned to minimal"
1598                                         " ConnectX-4 required value %d",
1599                                         (int)MLX5_INLINE_HSIZE_L2);
1600                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1601                         }
1602                         break;
1603                 }
1604                 goto exit;
1605         }
1606         if (config->hca_attr.eth_net_offloads) {
1607                 /* We have DevX enabled, inline mode queried successfully. */
1608                 switch (config->hca_attr.wqe_inline_mode) {
1609                 case MLX5_CAP_INLINE_MODE_L2:
1610                         /* outer L2 header must be inlined. */
1611                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1612                         goto exit;
1613                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1614                         /* No inline data are required by NIC. */
1615                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1616                         config->hw_vlan_insert =
1617                                 config->hca_attr.wqe_vlan_insert;
1618                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1619                         goto exit;
1620                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1621                         /* inline mode is defined by NIC vport context. */
1622                         if (!config->hca_attr.eth_virt)
1623                                 break;
1624                         switch (config->hca_attr.vport_inline_mode) {
1625                         case MLX5_INLINE_MODE_NONE:
1626                                 config->txq_inline_min =
1627                                         MLX5_INLINE_HSIZE_NONE;
1628                                 goto exit;
1629                         case MLX5_INLINE_MODE_L2:
1630                                 config->txq_inline_min =
1631                                         MLX5_INLINE_HSIZE_L2;
1632                                 goto exit;
1633                         case MLX5_INLINE_MODE_IP:
1634                                 config->txq_inline_min =
1635                                         MLX5_INLINE_HSIZE_L3;
1636                                 goto exit;
1637                         case MLX5_INLINE_MODE_TCP_UDP:
1638                                 config->txq_inline_min =
1639                                         MLX5_INLINE_HSIZE_L4;
1640                                 goto exit;
1641                         case MLX5_INLINE_MODE_INNER_L2:
1642                                 config->txq_inline_min =
1643                                         MLX5_INLINE_HSIZE_INNER_L2;
1644                                 goto exit;
1645                         case MLX5_INLINE_MODE_INNER_IP:
1646                                 config->txq_inline_min =
1647                                         MLX5_INLINE_HSIZE_INNER_L3;
1648                                 goto exit;
1649                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
1650                                 config->txq_inline_min =
1651                                         MLX5_INLINE_HSIZE_INNER_L4;
1652                                 goto exit;
1653                         }
1654                 }
1655         }
1656         /*
1657          * We get here if we are unable to deduce
1658          * inline data size with DevX. Try PCI ID
1659          * to determine old NICs.
1660          */
1661         switch (spawn->pci_dev->id.device_id) {
1662         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1663         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1664         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1665         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1666                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1667                 config->hw_vlan_insert = 0;
1668                 break;
1669         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1670         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1671         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1672         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1673                 /*
1674                  * These NICs support VLAN insertion from WQE and
1675                  * report the wqe_vlan_insert flag. But there is the bug
1676                  * and PFC control may be broken, so disable feature.
1677                  */
1678                 config->hw_vlan_insert = 0;
1679                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1680                 break;
1681         default:
1682                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1683                 break;
1684         }
1685 exit:
1686         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1687 }
1688
1689 /**
1690  * Configures the metadata mask fields in the shared context.
1691  *
1692  * @param [in] dev
1693  *   Pointer to Ethernet device.
1694  */
1695 void
1696 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1697 {
1698         struct mlx5_priv *priv = dev->data->dev_private;
1699         struct mlx5_dev_ctx_shared *sh = priv->sh;
1700         uint32_t meta, mark, reg_c0;
1701
1702         reg_c0 = ~priv->vport_meta_mask;
1703         switch (priv->config.dv_xmeta_en) {
1704         case MLX5_XMETA_MODE_LEGACY:
1705                 meta = UINT32_MAX;
1706                 mark = MLX5_FLOW_MARK_MASK;
1707                 break;
1708         case MLX5_XMETA_MODE_META16:
1709                 meta = reg_c0 >> rte_bsf32(reg_c0);
1710                 mark = MLX5_FLOW_MARK_MASK;
1711                 break;
1712         case MLX5_XMETA_MODE_META32:
1713                 meta = UINT32_MAX;
1714                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1715                 break;
1716         default:
1717                 meta = 0;
1718                 mark = 0;
1719                 MLX5_ASSERT(false);
1720                 break;
1721         }
1722         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1723                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1724                                  sh->dv_mark_mask, mark);
1725         else
1726                 sh->dv_mark_mask = mark;
1727         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1728                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1729                                  sh->dv_meta_mask, meta);
1730         else
1731                 sh->dv_meta_mask = meta;
1732         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1733                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1734                                  sh->dv_meta_mask, reg_c0);
1735         else
1736                 sh->dv_regc0_mask = reg_c0;
1737         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1738         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1739         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1740         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1741 }
1742
1743 int
1744 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1745 {
1746         static const char *const dynf_names[] = {
1747                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1748                 RTE_MBUF_DYNFLAG_METADATA_NAME,
1749                 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
1750         };
1751         unsigned int i;
1752
1753         if (n < RTE_DIM(dynf_names))
1754                 return -ENOMEM;
1755         for (i = 0; i < RTE_DIM(dynf_names); i++) {
1756                 if (names[i] == NULL)
1757                         return -EINVAL;
1758                 strcpy(names[i], dynf_names[i]);
1759         }
1760         return RTE_DIM(dynf_names);
1761 }
1762
1763 /**
1764  * Comparison callback to sort device data.
1765  *
1766  * This is meant to be used with qsort().
1767  *
1768  * @param a[in]
1769  *   Pointer to pointer to first data object.
1770  * @param b[in]
1771  *   Pointer to pointer to second data object.
1772  *
1773  * @return
1774  *   0 if both objects are equal, less than 0 if the first argument is less
1775  *   than the second, greater than 0 otherwise.
1776  */
1777 int
1778 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1779                               struct mlx5_dev_config *config)
1780 {
1781         struct mlx5_dev_ctx_shared *sh = priv->sh;
1782         struct mlx5_dev_config *sh_conf = NULL;
1783         uint16_t port_id;
1784
1785         MLX5_ASSERT(sh);
1786         /* Nothing to compare for the single/first device. */
1787         if (sh->refcnt == 1)
1788                 return 0;
1789         /* Find the device with shared context. */
1790         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1791                 struct mlx5_priv *opriv =
1792                         rte_eth_devices[port_id].data->dev_private;
1793
1794                 if (opriv && opriv != priv && opriv->sh == sh) {
1795                         sh_conf = &opriv->config;
1796                         break;
1797                 }
1798         }
1799         if (!sh_conf)
1800                 return 0;
1801         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1802                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1803                              " for shared %s context", sh->ibdev_name);
1804                 rte_errno = EINVAL;
1805                 return rte_errno;
1806         }
1807         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1808                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1809                              " for shared %s context", sh->ibdev_name);
1810                 rte_errno = EINVAL;
1811                 return rte_errno;
1812         }
1813         return 0;
1814 }
1815
1816 /**
1817  * Look for the ethernet device belonging to mlx5 driver.
1818  *
1819  * @param[in] port_id
1820  *   port_id to start looking for device.
1821  * @param[in] pci_dev
1822  *   Pointer to the hint PCI device. When device is being probed
1823  *   the its siblings (master and preceding representors might
1824  *   not have assigned driver yet (because the mlx5_os_pci_probe()
1825  *   is not completed yet, for this case match on hint PCI
1826  *   device may be used to detect sibling device.
1827  *
1828  * @return
1829  *   port_id of found device, RTE_MAX_ETHPORT if not found.
1830  */
1831 uint16_t
1832 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
1833 {
1834         while (port_id < RTE_MAX_ETHPORTS) {
1835                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
1836
1837                 if (dev->state != RTE_ETH_DEV_UNUSED &&
1838                     dev->device &&
1839                     (dev->device == &pci_dev->device ||
1840                      (dev->device->driver &&
1841                      dev->device->driver->name &&
1842                      !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
1843                         break;
1844                 port_id++;
1845         }
1846         if (port_id >= RTE_MAX_ETHPORTS)
1847                 return RTE_MAX_ETHPORTS;
1848         return port_id;
1849 }
1850
1851 /**
1852  * DPDK callback to remove a PCI device.
1853  *
1854  * This function removes all Ethernet devices belong to a given PCI device.
1855  *
1856  * @param[in] pci_dev
1857  *   Pointer to the PCI device.
1858  *
1859  * @return
1860  *   0 on success, the function cannot fail.
1861  */
1862 static int
1863 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1864 {
1865         uint16_t port_id;
1866
1867         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
1868                 /*
1869                  * mlx5_dev_close() is not registered to secondary process,
1870                  * call the close function explicitly for secondary process.
1871                  */
1872                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
1873                         mlx5_dev_close(&rte_eth_devices[port_id]);
1874                 else
1875                         rte_eth_dev_close(port_id);
1876         }
1877         return 0;
1878 }
1879
1880 static const struct rte_pci_id mlx5_pci_id_map[] = {
1881         {
1882                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1883                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1884         },
1885         {
1886                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1887                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1888         },
1889         {
1890                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1891                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1892         },
1893         {
1894                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1895                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1896         },
1897         {
1898                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1899                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1900         },
1901         {
1902                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1903                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1904         },
1905         {
1906                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1907                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1908         },
1909         {
1910                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1911                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1912         },
1913         {
1914                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1915                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
1916         },
1917         {
1918                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1919                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
1920         },
1921         {
1922                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1923                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
1924         },
1925         {
1926                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1927                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
1928         },
1929         {
1930                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1931                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
1932         },
1933         {
1934                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1935                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
1936         },
1937         {
1938                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1939                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
1940         },
1941         {
1942                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1943                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
1944         },
1945         {
1946                 .vendor_id = 0
1947         }
1948 };
1949
1950 struct rte_pci_driver mlx5_driver = {
1951         .driver = {
1952                 .name = MLX5_DRIVER_NAME
1953         },
1954         .id_table = mlx5_pci_id_map,
1955         .probe = mlx5_os_pci_probe,
1956         .remove = mlx5_pci_remove,
1957         .dma_map = mlx5_dma_map,
1958         .dma_unmap = mlx5_dma_unmap,
1959         .drv_flags = PCI_DRV_FLAGS,
1960 };
1961
1962 /* Initialize driver log type. */
1963 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
1964
1965 /**
1966  * Driver initialization routine.
1967  */
1968 RTE_INIT(rte_mlx5_pmd_init)
1969 {
1970         /* Build the static tables for Verbs conversion. */
1971         mlx5_set_ptype_table();
1972         mlx5_set_cksum_table();
1973         mlx5_set_swp_types_table();
1974         if (mlx5_glue)
1975                 rte_pci_register(&mlx5_driver);
1976 }
1977
1978 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1979 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1980 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");