drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <assert.h>
  10 #include <dlfcn.h>
  11 #include <stdint.h>
  12 #include <stdlib.h>
  13 #include <errno.h>
  14 #include <net/if.h>
  15 #include <sys/mman.h>
  16 #include <linux/rtnetlink.h>
  17
  18 /* Verbs header. */
  19 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  20 #ifdef PEDANTIC
  21 #pragma GCC diagnostic ignored "-Wpedantic"
  22 #endif
  23 #include <infiniband/verbs.h>
  24 #ifdef PEDANTIC
  25 #pragma GCC diagnostic error "-Wpedantic"
  26 #endif
  27
  28 #include <rte_malloc.h>
  29 #include <rte_ethdev_driver.h>
  30 #include <rte_ethdev_pci.h>
  31 #include <rte_pci.h>
  32 #include <rte_bus_pci.h>
  33 #include <rte_common.h>
  34 #include <rte_config.h>
  35 #include <rte_eal_memconfig.h>
  36 #include <rte_kvargs.h>
  37
  38 #include "mlx5.h"
  39 #include "mlx5_utils.h"
  40 #include "mlx5_rxtx.h"
  41 #include "mlx5_autoconf.h"
  42 #include "mlx5_defs.h"
  43 #include "mlx5_glue.h"
  44 #include "mlx5_mr.h"
  45
  46 /* Device parameter to enable RX completion queue compression. */
  47 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  48
  49 /* Device parameter to configure inline send. */
  50 #define MLX5_TXQ_INLINE "txq_inline"
  51
  52 /*
  53  * Device parameter to configure the number of TX queues threshold for
  54  * enabling inline send.
  55  */
  56 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  57
  58 /* Device parameter to enable multi-packet send WQEs. */
  59 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  60
  61 /* Device parameter to include 2 dsegs in the title WQEBB. */
  62 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
  63
  64 /* Device parameter to limit the size of inlining packet. */
  65 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
  66
  67 /* Device parameter to enable hardware Tx vector. */
  68 #define MLX5_TX_VEC_EN "tx_vec_en"
  69
  70 /* Device parameter to enable hardware Rx vector. */
  71 #define MLX5_RX_VEC_EN "rx_vec_en"
  72
  73 /* Allow L3 VXLAN flow creation. */
  74 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
  75
  76 /* Activate Netlink support in VF mode. */
  77 #define MLX5_VF_NL_EN "vf_nl_en"
  78
  79 #ifndef HAVE_IBV_MLX5_MOD_MPW
  80 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
  81 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
  82 #endif
  83
  84 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
  85 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
  86 #endif
  87
  88 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
  89
  90 /* Shared memory between primary and secondary processes. */
  91 struct mlx5_shared_data *mlx5_shared_data;
  92
  93 /* Spinlock for mlx5_shared_data allocation. */
  94 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
  95
  96 /** Driver-specific log messages type. */
  97 int mlx5_logtype;
  98
  99 /**
 100  * Prepare shared data between primary and secondary process.
 101  */
 102 static void
 103 mlx5_prepare_shared_data(void)
 104 {
 105         const struct rte_memzone *mz;
 106
 107         rte_spinlock_lock(&mlx5_shared_data_lock);
 108         if (mlx5_shared_data == NULL) {
 109                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
 110                         /* Allocate shared memory. */
 111                         mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
 112                                                  sizeof(*mlx5_shared_data),
 113                                                  SOCKET_ID_ANY, 0);
 114                 } else {
 115                         /* Lookup allocated shared memory. */
 116                         mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
 117                 }
 118                 if (mz == NULL)
 119                         rte_panic("Cannot allocate mlx5 shared data\n");
 120                 mlx5_shared_data = mz->addr;
 121                 /* Initialize shared data. */
 122                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
 123                         LIST_INIT(&mlx5_shared_data->mem_event_cb_list);
 124                         rte_rwlock_init(&mlx5_shared_data->mem_event_rwlock);
 125                 }
 126         }
 127         rte_spinlock_unlock(&mlx5_shared_data_lock);
 128 }
 129
 130 /**
 131  * Retrieve integer value from environment variable.
 132  *
 133  * @param[in] name
 134  *   Environment variable name.
 135  *
 136  * @return
 137  *   Integer value, 0 if the variable is not set.
 138  */
 139 int
 140 mlx5_getenv_int(const char *name)
 141 {
 142         const char *val = getenv(name);
 143
 144         if (val == NULL)
 145                 return 0;
 146         return atoi(val);
 147 }
 148
 149 /**
 150  * Verbs callback to allocate a memory. This function should allocate the space
 151  * according to the size provided residing inside a huge page.
 152  * Please note that all allocation must respect the alignment from libmlx5
 153  * (i.e. currently sysconf(_SC_PAGESIZE)).
 154  *
 155  * @param[in] size
 156  *   The size in bytes of the memory to allocate.
 157  * @param[in] data
 158  *   A pointer to the callback data.
 159  *
 160  * @return
 161  *   Allocated buffer, NULL otherwise and rte_errno is set.
 162  */
 163 static void *
 164 mlx5_alloc_verbs_buf(size_t size, void *data)
 165 {
 166         struct priv *priv = data;
 167         void *ret;
 168         size_t alignment = sysconf(_SC_PAGESIZE);
 169         unsigned int socket = SOCKET_ID_ANY;
 170
 171         if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
 172                 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
 173
 174                 socket = ctrl->socket;
 175         } else if (priv->verbs_alloc_ctx.type ==
 176                    MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
 177                 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
 178
 179                 socket = ctrl->socket;
 180         }
 181         assert(data != NULL);
 182         ret = rte_malloc_socket(__func__, size, alignment, socket);
 183         if (!ret && size)
 184                 rte_errno = ENOMEM;
 185         return ret;
 186 }
 187
 188 /**
 189  * Verbs callback to free a memory.
 190  *
 191  * @param[in] ptr
 192  *   A pointer to the memory to free.
 193  * @param[in] data
 194  *   A pointer to the callback data.
 195  */
 196 static void
 197 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
 198 {
 199         assert(data != NULL);
 200         rte_free(ptr);
 201 }
 202
 203 /**
 204  * DPDK callback to close the device.
 205  *
 206  * Destroy all queues and objects, free memory.
 207  *
 208  * @param dev
 209  *   Pointer to Ethernet device structure.
 210  */
 211 static void
 212 mlx5_dev_close(struct rte_eth_dev *dev)
 213 {
 214         struct priv *priv = dev->data->dev_private;
 215         unsigned int i;
 216         int ret;
 217
 218         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
 219                 dev->data->port_id,
 220                 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
 221         /* In case mlx5_dev_stop() has not been called. */
 222         mlx5_dev_interrupt_handler_uninstall(dev);
 223         mlx5_traffic_disable(dev);
 224         /* Prevent crashes when queues are still in use. */
 225         dev->rx_pkt_burst = removed_rx_burst;
 226         dev->tx_pkt_burst = removed_tx_burst;
 227         if (priv->rxqs != NULL) {
 228                 /* XXX race condition if mlx5_rx_burst() is still running. */
 229                 usleep(1000);
 230                 for (i = 0; (i != priv->rxqs_n); ++i)
 231                         mlx5_rxq_release(dev, i);
 232                 priv->rxqs_n = 0;
 233                 priv->rxqs = NULL;
 234         }
 235         if (priv->txqs != NULL) {
 236                 /* XXX race condition if mlx5_tx_burst() is still running. */
 237                 usleep(1000);
 238                 for (i = 0; (i != priv->txqs_n); ++i)
 239                         mlx5_txq_release(dev, i);
 240                 priv->txqs_n = 0;
 241                 priv->txqs = NULL;
 242         }
 243         mlx5_flow_delete_drop_queue(dev);
 244         mlx5_mr_release(dev);
 245         if (priv->pd != NULL) {
 246                 assert(priv->ctx != NULL);
 247                 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
 248                 claim_zero(mlx5_glue->close_device(priv->ctx));
 249         } else
 250                 assert(priv->ctx == NULL);
 251         if (priv->rss_conf.rss_key != NULL)
 252                 rte_free(priv->rss_conf.rss_key);
 253         if (priv->reta_idx != NULL)
 254                 rte_free(priv->reta_idx);
 255         if (priv->primary_socket)
 256                 mlx5_socket_uninit(dev);
 257         if (priv->config.vf)
 258                 mlx5_nl_mac_addr_flush(dev);
 259         if (priv->nl_socket >= 0)
 260                 close(priv->nl_socket);
 261         ret = mlx5_hrxq_ibv_verify(dev);
 262         if (ret)
 263                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
 264                         dev->data->port_id);
 265         ret = mlx5_ind_table_ibv_verify(dev);
 266         if (ret)
 267                 DRV_LOG(WARNING, "port %u some indirection table still remain",
 268                         dev->data->port_id);
 269         ret = mlx5_rxq_ibv_verify(dev);
 270         if (ret)
 271                 DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain",
 272                         dev->data->port_id);
 273         ret = mlx5_rxq_verify(dev);
 274         if (ret)
 275                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
 276                         dev->data->port_id);
 277         ret = mlx5_txq_ibv_verify(dev);
 278         if (ret)
 279                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
 280                         dev->data->port_id);
 281         ret = mlx5_txq_verify(dev);
 282         if (ret)
 283                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
 284                         dev->data->port_id);
 285         ret = mlx5_flow_verify(dev);
 286         if (ret)
 287                 DRV_LOG(WARNING, "port %u some flows still remain",
 288                         dev->data->port_id);
 289         memset(priv, 0, sizeof(*priv));
 290 }
 291
 292 const struct eth_dev_ops mlx5_dev_ops = {
 293         .dev_configure = mlx5_dev_configure,
 294         .dev_start = mlx5_dev_start,
 295         .dev_stop = mlx5_dev_stop,
 296         .dev_set_link_down = mlx5_set_link_down,
 297         .dev_set_link_up = mlx5_set_link_up,
 298         .dev_close = mlx5_dev_close,
 299         .promiscuous_enable = mlx5_promiscuous_enable,
 300         .promiscuous_disable = mlx5_promiscuous_disable,
 301         .allmulticast_enable = mlx5_allmulticast_enable,
 302         .allmulticast_disable = mlx5_allmulticast_disable,
 303         .link_update = mlx5_link_update,
 304         .stats_get = mlx5_stats_get,
 305         .stats_reset = mlx5_stats_reset,
 306         .xstats_get = mlx5_xstats_get,
 307         .xstats_reset = mlx5_xstats_reset,
 308         .xstats_get_names = mlx5_xstats_get_names,
 309         .dev_infos_get = mlx5_dev_infos_get,
 310         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
 311         .vlan_filter_set = mlx5_vlan_filter_set,
 312         .rx_queue_setup = mlx5_rx_queue_setup,
 313         .tx_queue_setup = mlx5_tx_queue_setup,
 314         .rx_queue_release = mlx5_rx_queue_release,
 315         .tx_queue_release = mlx5_tx_queue_release,
 316         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
 317         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
 318         .mac_addr_remove = mlx5_mac_addr_remove,
 319         .mac_addr_add = mlx5_mac_addr_add,
 320         .mac_addr_set = mlx5_mac_addr_set,
 321         .set_mc_addr_list = mlx5_set_mc_addr_list,
 322         .mtu_set = mlx5_dev_set_mtu,
 323         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
 324         .vlan_offload_set = mlx5_vlan_offload_set,
 325         .reta_update = mlx5_dev_rss_reta_update,
 326         .reta_query = mlx5_dev_rss_reta_query,
 327         .rss_hash_update = mlx5_rss_hash_update,
 328         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
 329         .filter_ctrl = mlx5_dev_filter_ctrl,
 330         .rx_descriptor_status = mlx5_rx_descriptor_status,
 331         .tx_descriptor_status = mlx5_tx_descriptor_status,
 332         .rx_queue_intr_enable = mlx5_rx_intr_enable,
 333         .rx_queue_intr_disable = mlx5_rx_intr_disable,
 334         .is_removed = mlx5_is_removed,
 335 };
 336
 337 static const struct eth_dev_ops mlx5_dev_sec_ops = {
 338         .stats_get = mlx5_stats_get,
 339         .stats_reset = mlx5_stats_reset,
 340         .xstats_get = mlx5_xstats_get,
 341         .xstats_reset = mlx5_xstats_reset,
 342         .xstats_get_names = mlx5_xstats_get_names,
 343         .dev_infos_get = mlx5_dev_infos_get,
 344         .rx_descriptor_status = mlx5_rx_descriptor_status,
 345         .tx_descriptor_status = mlx5_tx_descriptor_status,
 346 };
 347
 348 /* Available operators in flow isolated mode. */
 349 const struct eth_dev_ops mlx5_dev_ops_isolate = {
 350         .dev_configure = mlx5_dev_configure,
 351         .dev_start = mlx5_dev_start,
 352         .dev_stop = mlx5_dev_stop,
 353         .dev_set_link_down = mlx5_set_link_down,
 354         .dev_set_link_up = mlx5_set_link_up,
 355         .dev_close = mlx5_dev_close,
 356         .link_update = mlx5_link_update,
 357         .stats_get = mlx5_stats_get,
 358         .stats_reset = mlx5_stats_reset,
 359         .xstats_get = mlx5_xstats_get,
 360         .xstats_reset = mlx5_xstats_reset,
 361         .xstats_get_names = mlx5_xstats_get_names,
 362         .dev_infos_get = mlx5_dev_infos_get,
 363         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
 364         .vlan_filter_set = mlx5_vlan_filter_set,
 365         .rx_queue_setup = mlx5_rx_queue_setup,
 366         .tx_queue_setup = mlx5_tx_queue_setup,
 367         .rx_queue_release = mlx5_rx_queue_release,
 368         .tx_queue_release = mlx5_tx_queue_release,
 369         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
 370         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
 371         .mac_addr_remove = mlx5_mac_addr_remove,
 372         .mac_addr_add = mlx5_mac_addr_add,
 373         .mac_addr_set = mlx5_mac_addr_set,
 374         .set_mc_addr_list = mlx5_set_mc_addr_list,
 375         .mtu_set = mlx5_dev_set_mtu,
 376         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
 377         .vlan_offload_set = mlx5_vlan_offload_set,
 378         .filter_ctrl = mlx5_dev_filter_ctrl,
 379         .rx_descriptor_status = mlx5_rx_descriptor_status,
 380         .tx_descriptor_status = mlx5_tx_descriptor_status,
 381         .rx_queue_intr_enable = mlx5_rx_intr_enable,
 382         .rx_queue_intr_disable = mlx5_rx_intr_disable,
 383         .is_removed = mlx5_is_removed,
 384 };
 385
 386 static struct {
 387         struct rte_pci_addr pci_addr; /* associated PCI address */
 388         uint32_t ports; /* physical ports bitfield. */
 389 } mlx5_dev[32];
 390
 391 /**
 392  * Get device index in mlx5_dev[] from PCI bus address.
 393  *
 394  * @param[in] pci_addr
 395  *   PCI bus address to look for.
 396  *
 397  * @return
 398  *   mlx5_dev[] index on success, -1 on failure.
 399  */
 400 static int
 401 mlx5_dev_idx(struct rte_pci_addr *pci_addr)
 402 {
 403         unsigned int i;
 404         int ret = -1;
 405
 406         assert(pci_addr != NULL);
 407         for (i = 0; (i != RTE_DIM(mlx5_dev)); ++i) {
 408                 if ((mlx5_dev[i].pci_addr.domain == pci_addr->domain) &&
 409                     (mlx5_dev[i].pci_addr.bus == pci_addr->bus) &&
 410                     (mlx5_dev[i].pci_addr.devid == pci_addr->devid) &&
 411                     (mlx5_dev[i].pci_addr.function == pci_addr->function))
 412                         return i;
 413                 if ((mlx5_dev[i].ports == 0) && (ret == -1))
 414                         ret = i;
 415         }
 416         return ret;
 417 }
 418
 419 /**
 420  * Verify and store value for device argument.
 421  *
 422  * @param[in] key
 423  *   Key argument to verify.
 424  * @param[in] val
 425  *   Value associated with key.
 426  * @param opaque
 427  *   User data.
 428  *
 429  * @return
 430  *   0 on success, a negative errno value otherwise and rte_errno is set.
 431  */
 432 static int
 433 mlx5_args_check(const char *key, const char *val, void *opaque)
 434 {
 435         struct mlx5_dev_config *config = opaque;
 436         unsigned long tmp;
 437
 438         errno = 0;
 439         tmp = strtoul(val, NULL, 0);
 440         if (errno) {
 441                 rte_errno = errno;
 442                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
 443                 return -rte_errno;
 444         }
 445         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
 446                 config->cqe_comp = !!tmp;
 447         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
 448                 config->txq_inline = tmp;
 449         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
 450                 config->txqs_inline = tmp;
 451         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
 452                 config->mps = !!tmp ? config->mps : 0;
 453         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
 454                 config->mpw_hdr_dseg = !!tmp;
 455         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
 456                 config->inline_max_packet_sz = tmp;
 457         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
 458                 config->tx_vec_en = !!tmp;
 459         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
 460                 config->rx_vec_en = !!tmp;
 461         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
 462                 config->l3_vxlan_en = !!tmp;
 463         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
 464                 config->vf_nl_en = !!tmp;
 465         } else {
 466                 DRV_LOG(WARNING, "%s: unknown parameter", key);
 467                 rte_errno = EINVAL;
 468                 return -rte_errno;
 469         }
 470         return 0;
 471 }
 472
 473 /**
 474  * Parse device parameters.
 475  *
 476  * @param config
 477  *   Pointer to device configuration structure.
 478  * @param devargs
 479  *   Device arguments structure.
 480  *
 481  * @return
 482  *   0 on success, a negative errno value otherwise and rte_errno is set.
 483  */
 484 static int
 485 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
 486 {
 487         const char **params = (const char *[]){
 488                 MLX5_RXQ_CQE_COMP_EN,
 489                 MLX5_TXQ_INLINE,
 490                 MLX5_TXQS_MIN_INLINE,
 491                 MLX5_TXQ_MPW_EN,
 492                 MLX5_TXQ_MPW_HDR_DSEG_EN,
 493                 MLX5_TXQ_MAX_INLINE_LEN,
 494                 MLX5_TX_VEC_EN,
 495                 MLX5_RX_VEC_EN,
 496                 MLX5_L3_VXLAN_EN,
 497                 MLX5_VF_NL_EN,
 498                 NULL,
 499         };
 500         struct rte_kvargs *kvlist;
 501         int ret = 0;
 502         int i;
 503
 504         if (devargs == NULL)
 505                 return 0;
 506         /* Following UGLY cast is done to pass checkpatch. */
 507         kvlist = rte_kvargs_parse(devargs->args, params);
 508         if (kvlist == NULL)
 509                 return 0;
 510         /* Process parameters. */
 511         for (i = 0; (params[i] != NULL); ++i) {
 512                 if (rte_kvargs_count(kvlist, params[i])) {
 513                         ret = rte_kvargs_process(kvlist, params[i],
 514                                                  mlx5_args_check, config);
 515                         if (ret) {
 516                                 rte_errno = EINVAL;
 517                                 rte_kvargs_free(kvlist);
 518                                 return -rte_errno;
 519                         }
 520                 }
 521         }
 522         rte_kvargs_free(kvlist);
 523         return 0;
 524 }
 525
 526 static struct rte_pci_driver mlx5_driver;
 527
 528 /*
 529  * Reserved UAR address space for TXQ UAR(hw doorbell) mapping, process
 530  * local resource used by both primary and secondary to avoid duplicate
 531  * reservation.
 532  * The space has to be available on both primary and secondary process,
 533  * TXQ UAR maps to this area using fixed mmap w/o double check.
 534  */
 535 static void *uar_base;
 536
 537 static int
 538 find_lower_va_bound(const struct rte_memseg_list *msl __rte_unused,
 539                 const struct rte_memseg *ms, void *arg)
 540 {
 541         void **addr = arg;
 542
 543         if (*addr == NULL)
 544                 *addr = ms->addr;
 545         else
 546                 *addr = RTE_MIN(*addr, ms->addr);
 547
 548         return 0;
 549 }
 550
 551 /**
 552  * Reserve UAR address space for primary process.
 553  *
 554  * @param[in] dev
 555  *   Pointer to Ethernet device.
 556  *
 557  * @return
 558  *   0 on success, a negative errno value otherwise and rte_errno is set.
 559  */
 560 static int
 561 mlx5_uar_init_primary(struct rte_eth_dev *dev)
 562 {
 563         struct priv *priv = dev->data->dev_private;
 564         void *addr = (void *)0;
 565
 566         if (uar_base) { /* UAR address space mapped. */
 567                 priv->uar_base = uar_base;
 568                 return 0;
 569         }
 570         /* find out lower bound of hugepage segments */
 571         rte_memseg_walk(find_lower_va_bound, &addr);
 572
 573         /* keep distance to hugepages to minimize potential conflicts. */
 574         addr = RTE_PTR_SUB(addr, MLX5_UAR_OFFSET + MLX5_UAR_SIZE);
 575         /* anonymous mmap, no real memory consumption. */
 576         addr = mmap(addr, MLX5_UAR_SIZE,
 577                     PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
 578         if (addr == MAP_FAILED) {
 579                 DRV_LOG(ERR,
 580                         "port %u failed to reserve UAR address space, please"
 581                         " adjust MLX5_UAR_SIZE or try --base-virtaddr",
 582                         dev->data->port_id);
 583                 rte_errno = ENOMEM;
 584                 return -rte_errno;
 585         }
 586         /* Accept either same addr or a new addr returned from mmap if target
 587          * range occupied.
 588          */
 589         DRV_LOG(INFO, "port %u reserved UAR address space: %p",
 590                 dev->data->port_id, addr);
 591         priv->uar_base = addr; /* for primary and secondary UAR re-mmap. */
 592         uar_base = addr; /* process local, don't reserve again. */
 593         return 0;
 594 }
 595
 596 /**
 597  * Reserve UAR address space for secondary process, align with
 598  * primary process.
 599  *
 600  * @param[in] dev
 601  *   Pointer to Ethernet device.
 602  *
 603  * @return
 604  *   0 on success, a negative errno value otherwise and rte_errno is set.
 605  */
 606 static int
 607 mlx5_uar_init_secondary(struct rte_eth_dev *dev)
 608 {
 609         struct priv *priv = dev->data->dev_private;
 610         void *addr;
 611
 612         assert(priv->uar_base);
 613         if (uar_base) { /* already reserved. */
 614                 assert(uar_base == priv->uar_base);
 615                 return 0;
 616         }
 617         /* anonymous mmap, no real memory consumption. */
 618         addr = mmap(priv->uar_base, MLX5_UAR_SIZE,
 619                     PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
 620         if (addr == MAP_FAILED) {
 621                 DRV_LOG(ERR, "port %u UAR mmap failed: %p size: %llu",
 622                         dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
 623                 rte_errno = ENXIO;
 624                 return -rte_errno;
 625         }
 626         if (priv->uar_base != addr) {
 627                 DRV_LOG(ERR,
 628                         "port %u UAR address %p size %llu occupied, please"
 629                         " adjust MLX5_UAR_OFFSET or try EAL parameter"
 630                         " --base-virtaddr",
 631                         dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
 632                 rte_errno = ENXIO;
 633                 return -rte_errno;
 634         }
 635         uar_base = addr; /* process local, don't reserve again */
 636         DRV_LOG(INFO, "port %u reserved UAR address space: %p",
 637                 dev->data->port_id, addr);
 638         return 0;
 639 }
 640
 641 /**
 642  * DPDK callback to register a PCI device.
 643  *
 644  * This function creates an Ethernet device for each port of a given
 645  * PCI device.
 646  *
 647  * @param[in] pci_drv
 648  *   PCI driver structure (mlx5_driver).
 649  * @param[in] pci_dev
 650  *   PCI device information.
 651  *
 652  * @return
 653  *   0 on success, a negative errno value otherwise and rte_errno is set.
 654  */
 655 static int
 656 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 657                struct rte_pci_device *pci_dev)
 658 {
 659         struct ibv_device **list = NULL;
 660         struct ibv_device *ibv_dev;
 661         int err = 0;
 662         struct ibv_context *attr_ctx = NULL;
 663         struct ibv_device_attr_ex device_attr;
 664         unsigned int vf;
 665         unsigned int mps;
 666         unsigned int cqe_comp;
 667         unsigned int tunnel_en = 0;
 668         unsigned int swp = 0;
 669         unsigned int verb_priorities = 0;
 670         int idx;
 671         int i;
 672         struct mlx5dv_context attrs_out = {0};
 673 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
 674         struct ibv_counter_set_description cs_desc;
 675 #endif
 676
 677         /* Prepare shared data between primary and secondary process. */
 678         mlx5_prepare_shared_data();
 679         assert(pci_drv == &mlx5_driver);
 680         /* Get mlx5_dev[] index. */
 681         idx = mlx5_dev_idx(&pci_dev->addr);
 682         if (idx == -1) {
 683                 DRV_LOG(ERR, "this driver cannot support any more adapters");
 684                 err = ENOMEM;
 685                 goto error;
 686         }
 687         DRV_LOG(DEBUG, "using driver device index %d", idx);
 688         /* Save PCI address. */
 689         mlx5_dev[idx].pci_addr = pci_dev->addr;
 690         list = mlx5_glue->get_device_list(&i);
 691         if (list == NULL) {
 692                 assert(errno);
 693                 err = errno;
 694                 if (errno == ENOSYS)
 695                         DRV_LOG(ERR,
 696                                 "cannot list devices, is ib_uverbs loaded?");
 697                 goto error;
 698         }
 699         assert(i >= 0);
 700         /*
 701          * For each listed device, check related sysfs entry against
 702          * the provided PCI ID.
 703          */
 704         while (i != 0) {
 705                 struct rte_pci_addr pci_addr;
 706
 707                 --i;
 708                 DRV_LOG(DEBUG, "checking device \"%s\"", list[i]->name);
 709                 if (mlx5_ibv_device_to_pci_addr(list[i], &pci_addr))
 710                         continue;
 711                 if ((pci_dev->addr.domain != pci_addr.domain) ||
 712                     (pci_dev->addr.bus != pci_addr.bus) ||
 713                     (pci_dev->addr.devid != pci_addr.devid) ||
 714                     (pci_dev->addr.function != pci_addr.function))
 715                         continue;
 716                 DRV_LOG(INFO, "PCI information matches, using device \"%s\"",
 717                         list[i]->name);
 718                 vf = ((pci_dev->id.device_id ==
 719                        PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) ||
 720                       (pci_dev->id.device_id ==
 721                        PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) ||
 722                       (pci_dev->id.device_id ==
 723                        PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) ||
 724                       (pci_dev->id.device_id ==
 725                        PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF));
 726                 attr_ctx = mlx5_glue->open_device(list[i]);
 727                 rte_errno = errno;
 728                 err = rte_errno;
 729                 break;
 730         }
 731         if (attr_ctx == NULL) {
 732                 switch (err) {
 733                 case 0:
 734                         DRV_LOG(ERR,
 735                                 "cannot access device, is mlx5_ib loaded?");
 736                         err = ENODEV;
 737                         break;
 738                 case EINVAL:
 739                         DRV_LOG(ERR,
 740                                 "cannot use device, are drivers up to date?");
 741                         break;
 742                 }
 743                 goto error;
 744         }
 745         ibv_dev = list[i];
 746         DRV_LOG(DEBUG, "device opened");
 747 #ifdef HAVE_IBV_MLX5_MOD_SWP
 748         attrs_out.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
 749 #endif
 750         /*
 751          * Multi-packet send is supported by ConnectX-4 Lx PF as well
 752          * as all ConnectX-5 devices.
 753          */
 754 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
 755         attrs_out.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
 756 #endif
 757         mlx5_glue->dv_query_device(attr_ctx, &attrs_out);
 758         if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
 759                 if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
 760                         DRV_LOG(DEBUG, "enhanced MPW is supported");
 761                         mps = MLX5_MPW_ENHANCED;
 762                 } else {
 763                         DRV_LOG(DEBUG, "MPW is supported");
 764                         mps = MLX5_MPW;
 765                 }
 766         } else {
 767                 DRV_LOG(DEBUG, "MPW isn't supported");
 768                 mps = MLX5_MPW_DISABLED;
 769         }
 770 #ifdef HAVE_IBV_MLX5_MOD_SWP
 771         if (attrs_out.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
 772                 swp = attrs_out.sw_parsing_caps.sw_parsing_offloads;
 773         DRV_LOG(DEBUG, "SWP support: %u", swp);
 774 #endif
 775         if (RTE_CACHE_LINE_SIZE == 128 &&
 776             !(attrs_out.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
 777                 cqe_comp = 0;
 778         else
 779                 cqe_comp = 1;
 780 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
 781         if (attrs_out.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
 782                 tunnel_en = ((attrs_out.tunnel_offloads_caps &
 783                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
 784                              (attrs_out.tunnel_offloads_caps &
 785                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE));
 786         }
 787         DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
 788                 tunnel_en ? "" : "not ");
 789 #else
 790         DRV_LOG(WARNING,
 791                 "tunnel offloading disabled due to old OFED/rdma-core version");
 792 #endif
 793         err = mlx5_glue->query_device_ex(attr_ctx, NULL, &device_attr);
 794         if (err) {
 795                 DEBUG("ibv_query_device_ex() failed");
 796                 goto error;
 797         }
 798         DRV_LOG(INFO, "%u port(s) detected",
 799                 device_attr.orig_attr.phys_port_cnt);
 800         for (i = 0; i < device_attr.orig_attr.phys_port_cnt; i++) {
 801                 char name[RTE_ETH_NAME_MAX_LEN];
 802                 int len;
 803                 uint32_t port = i + 1; /* ports are indexed from one */
 804                 uint32_t test = (1 << i);
 805                 struct ibv_context *ctx = NULL;
 806                 struct ibv_port_attr port_attr;
 807                 struct ibv_pd *pd = NULL;
 808                 struct priv *priv = NULL;
 809                 struct rte_eth_dev *eth_dev = NULL;
 810                 struct ibv_device_attr_ex device_attr_ex;
 811                 struct ether_addr mac;
 812                 struct mlx5_dev_config config = {
 813                         .cqe_comp = cqe_comp,
 814                         .mps = mps,
 815                         .tunnel_en = tunnel_en,
 816                         .tx_vec_en = 1,
 817                         .rx_vec_en = 1,
 818                         .mpw_hdr_dseg = 0,
 819                         .txq_inline = MLX5_ARG_UNSET,
 820                         .txqs_inline = MLX5_ARG_UNSET,
 821                         .inline_max_packet_sz = MLX5_ARG_UNSET,
 822                         .vf_nl_en = 1,
 823                         .swp = !!swp,
 824                 };
 825
 826                 len = snprintf(name, sizeof(name), PCI_PRI_FMT,
 827                          pci_dev->addr.domain, pci_dev->addr.bus,
 828                          pci_dev->addr.devid, pci_dev->addr.function);
 829                 if (device_attr.orig_attr.phys_port_cnt > 1)
 830                         snprintf(name + len, sizeof(name), " port %u", i);
 831                 mlx5_dev[idx].ports |= test;
 832                 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
 833                         eth_dev = rte_eth_dev_attach_secondary(name);
 834                         if (eth_dev == NULL) {
 835                                 DRV_LOG(ERR, "can not attach rte ethdev");
 836                                 rte_errno = ENOMEM;
 837                                 err = rte_errno;
 838                                 goto error;
 839                         }
 840                         eth_dev->device = &pci_dev->device;
 841                         eth_dev->dev_ops = &mlx5_dev_sec_ops;
 842                         err = mlx5_uar_init_secondary(eth_dev);
 843                         if (err) {
 844                                 err = rte_errno;
 845                                 goto error;
 846                         }
 847                         /* Receive command fd from primary process */
 848                         err = mlx5_socket_connect(eth_dev);
 849                         if (err < 0) {
 850                                 err = rte_errno;
 851                                 goto error;
 852                         }
 853                         /* Remap UAR for Tx queues. */
 854                         err = mlx5_tx_uar_remap(eth_dev, err);
 855                         if (err) {
 856                                 err = rte_errno;
 857                                 goto error;
 858                         }
 859                         /*
 860                          * Ethdev pointer is still required as input since
 861                          * the primary device is not accessible from the
 862                          * secondary process.
 863                          */
 864                         eth_dev->rx_pkt_burst =
 865                                 mlx5_select_rx_function(eth_dev);
 866                         eth_dev->tx_pkt_burst =
 867                                 mlx5_select_tx_function(eth_dev);
 868                         continue;
 869                 }
 870                 DRV_LOG(DEBUG, "using port %u (%08" PRIx32 ")", port, test);
 871                 ctx = mlx5_glue->open_device(ibv_dev);
 872                 if (ctx == NULL) {
 873                         err = ENODEV;
 874                         goto port_error;
 875                 }
 876                 /* Check port status. */
 877                 err = mlx5_glue->query_port(ctx, port, &port_attr);
 878                 if (err) {
 879                         DRV_LOG(ERR, "port query failed: %s", strerror(err));
 880                         goto port_error;
 881                 }
 882                 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
 883                         DRV_LOG(ERR,
 884                                 "port %d is not configured in Ethernet mode",
 885                                 port);
 886                         err = EINVAL;
 887                         goto port_error;
 888                 }
 889                 if (port_attr.state != IBV_PORT_ACTIVE)
 890                         DRV_LOG(DEBUG, "port %d is not active: \"%s\" (%d)",
 891                                 port,
 892                                 mlx5_glue->port_state_str(port_attr.state),
 893                                 port_attr.state);
 894                 /* Allocate protection domain. */
 895                 pd = mlx5_glue->alloc_pd(ctx);
 896                 if (pd == NULL) {
 897                         DRV_LOG(ERR, "PD allocation failure");
 898                         err = ENOMEM;
 899                         goto port_error;
 900                 }
 901                 mlx5_dev[idx].ports |= test;
 902                 /* from rte_ethdev.c */
 903                 priv = rte_zmalloc("ethdev private structure",
 904                                    sizeof(*priv),
 905                                    RTE_CACHE_LINE_SIZE);
 906                 if (priv == NULL) {
 907                         DRV_LOG(ERR, "priv allocation failure");
 908                         err = ENOMEM;
 909                         goto port_error;
 910                 }
 911                 priv->ctx = ctx;
 912                 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path,
 913                         sizeof(priv->ibdev_path));
 914                 priv->device_attr = device_attr;
 915                 priv->port = port;
 916                 priv->pd = pd;
 917                 priv->mtu = ETHER_MTU;
 918                 err = mlx5_args(&config, pci_dev->device.devargs);
 919                 if (err) {
 920                         DRV_LOG(ERR, "failed to process device arguments: %s",
 921                                 strerror(err));
 922                         err = rte_errno;
 923                         goto port_error;
 924                 }
 925                 err = mlx5_glue->query_device_ex(ctx, NULL, &device_attr_ex);
 926                 if (err) {
 927                         DRV_LOG(ERR, "ibv_query_device_ex() failed");
 928                         goto port_error;
 929                 }
 930                 config.hw_csum = !!(device_attr_ex.device_cap_flags_ex &
 931                                     IBV_DEVICE_RAW_IP_CSUM);
 932                 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
 933                         (config.hw_csum ? "" : "not "));
 934 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
 935                 config.flow_counter_en = !!(device_attr.max_counter_sets);
 936                 mlx5_glue->describe_counter_set(ctx, 0, &cs_desc);
 937                 DRV_LOG(DEBUG,
 938                         "counter type = %d, num of cs = %ld, attributes = %d",
 939                         cs_desc.counter_type, cs_desc.num_of_cs,
 940                         cs_desc.attributes);
 941 #endif
 942                 config.ind_table_max_size =
 943                         device_attr_ex.rss_caps.max_rwq_indirection_table_size;
 944                 /* Remove this check once DPDK supports larger/variable
 945                  * indirection tables. */
 946                 if (config.ind_table_max_size >
 947                                 (unsigned int)ETH_RSS_RETA_SIZE_512)
 948                         config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
 949                 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
 950                         config.ind_table_max_size);
 951                 config.hw_vlan_strip = !!(device_attr_ex.raw_packet_caps &
 952                                          IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
 953                 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
 954                         (config.hw_vlan_strip ? "" : "not "));
 955
 956                 config.hw_fcs_strip = !!(device_attr_ex.raw_packet_caps &
 957                                          IBV_RAW_PACKET_CAP_SCATTER_FCS);
 958                 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
 959                         (config.hw_fcs_strip ? "" : "not "));
 960
 961 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
 962                 config.hw_padding = !!device_attr_ex.rx_pad_end_addr_align;
 963 #endif
 964                 DRV_LOG(DEBUG,
 965                         "hardware Rx end alignment padding is %ssupported",
 966                         (config.hw_padding ? "" : "not "));
 967                 config.vf = vf;
 968                 config.tso = ((device_attr_ex.tso_caps.max_tso > 0) &&
 969                               (device_attr_ex.tso_caps.supported_qpts &
 970                               (1 << IBV_QPT_RAW_PACKET)));
 971                 if (config.tso)
 972                         config.tso_max_payload_sz =
 973                                         device_attr_ex.tso_caps.max_tso;
 974                 if (config.mps && !mps) {
 975                         DRV_LOG(ERR,
 976                                 "multi-packet send not supported on this device"
 977                                 " (" MLX5_TXQ_MPW_EN ")");
 978                         err = ENOTSUP;
 979                         goto port_error;
 980                 }
 981                 DRV_LOG(INFO, "%s MPS is %s",
 982                         config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "",
 983                         config.mps != MLX5_MPW_DISABLED ? "enabled" :
 984                         "disabled");
 985                 if (config.cqe_comp && !cqe_comp) {
 986                         DRV_LOG(WARNING, "Rx CQE compression isn't supported");
 987                         config.cqe_comp = 0;
 988                 }
 989                 eth_dev = rte_eth_dev_allocate(name);
 990                 if (eth_dev == NULL) {
 991                         DRV_LOG(ERR, "can not allocate rte ethdev");
 992                         err = ENOMEM;
 993                         goto port_error;
 994                 }
 995                 eth_dev->data->dev_private = priv;
 996                 priv->dev_data = eth_dev->data;
 997                 eth_dev->data->mac_addrs = priv->mac;
 998                 eth_dev->device = &pci_dev->device;
 999                 rte_eth_copy_pci_info(eth_dev, pci_dev);
1000                 eth_dev->device->driver = &mlx5_driver.driver;
1001                 err = mlx5_uar_init_primary(eth_dev);
1002                 if (err) {
1003                         err = rte_errno;
1004                         goto port_error;
1005                 }
1006                 /* Configure the first MAC address by default. */
1007                 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
1008                         DRV_LOG(ERR,
1009                                 "port %u cannot get MAC address, is mlx5_en"
1010                                 " loaded? (errno: %s)",
1011                                 eth_dev->data->port_id, strerror(errno));
1012                         err = ENODEV;
1013                         goto port_error;
1014                 }
1015                 DRV_LOG(INFO,
1016                         "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
1017                         eth_dev->data->port_id,
1018                         mac.addr_bytes[0], mac.addr_bytes[1],
1019                         mac.addr_bytes[2], mac.addr_bytes[3],
1020                         mac.addr_bytes[4], mac.addr_bytes[5]);
1021 #ifndef NDEBUG
1022                 {
1023                         char ifname[IF_NAMESIZE];
1024
1025                         if (mlx5_get_ifname(eth_dev, &ifname) == 0)
1026                                 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
1027                                         eth_dev->data->port_id, ifname);
1028                         else
1029                                 DRV_LOG(DEBUG, "port %u ifname is unknown",
1030                                         eth_dev->data->port_id);
1031                 }
1032 #endif
1033                 /* Get actual MTU if possible. */
1034                 err = mlx5_get_mtu(eth_dev, &priv->mtu);
1035                 if (err) {
1036                         err = rte_errno;
1037                         goto port_error;
1038                 }
1039                 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
1040                         priv->mtu);
1041                 /*
1042                  * Initialize burst functions to prevent crashes before link-up.
1043                  */
1044                 eth_dev->rx_pkt_burst = removed_rx_burst;
1045                 eth_dev->tx_pkt_burst = removed_tx_burst;
1046                 eth_dev->dev_ops = &mlx5_dev_ops;
1047                 /* Register MAC address. */
1048                 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
1049                 priv->nl_socket = -1;
1050                 priv->nl_sn = 0;
1051                 if (vf && config.vf_nl_en) {
1052                         priv->nl_socket = mlx5_nl_init(RTMGRP_LINK);
1053                         if (priv->nl_socket < 0)
1054                                 priv->nl_socket = -1;
1055                         mlx5_nl_mac_addr_sync(eth_dev);
1056                 }
1057                 TAILQ_INIT(&priv->flows);
1058                 TAILQ_INIT(&priv->ctrl_flows);
1059                 /* Hint libmlx5 to use PMD allocator for data plane resources */
1060                 struct mlx5dv_ctx_allocators alctr = {
1061                         .alloc = &mlx5_alloc_verbs_buf,
1062                         .free = &mlx5_free_verbs_buf,
1063                         .data = priv,
1064                 };
1065                 mlx5_glue->dv_set_context_attr(ctx,
1066                                                MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
1067                                                (void *)((uintptr_t)&alctr));
1068                 /* Bring Ethernet device up. */
1069                 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
1070                         eth_dev->data->port_id);
1071                 mlx5_set_link_up(eth_dev);
1072                 /*
1073                  * Even though the interrupt handler is not installed yet,
1074                  * interrupts will still trigger on the asyn_fd from
1075                  * Verbs context returned by ibv_open_device().
1076                  */
1077                 mlx5_link_update(eth_dev, 0);
1078                 /* Store device configuration on private structure. */
1079                 priv->config = config;
1080                 /* Create drop queue. */
1081                 err = mlx5_flow_create_drop_queue(eth_dev);
1082                 if (err) {
1083                         DRV_LOG(ERR, "port %u drop queue allocation failed: %s",
1084                                 eth_dev->data->port_id, strerror(rte_errno));
1085                         err = rte_errno;
1086                         goto port_error;
1087                 }
1088                 /* Supported Verbs flow priority number detection. */
1089                 if (verb_priorities == 0)
1090                         verb_priorities = mlx5_get_max_verbs_prio(eth_dev);
1091                 if (verb_priorities < MLX5_VERBS_FLOW_PRIO_8) {
1092                         DRV_LOG(ERR, "port %u wrong Verbs flow priorities: %u",
1093                                 eth_dev->data->port_id, verb_priorities);
1094                         goto port_error;
1095                 }
1096                 priv->config.max_verbs_prio = verb_priorities;
1097                 continue;
1098 port_error:
1099                 if (priv)
1100                         rte_free(priv);
1101                 if (pd)
1102                         claim_zero(mlx5_glue->dealloc_pd(pd));
1103                 if (ctx)
1104                         claim_zero(mlx5_glue->close_device(ctx));
1105                 if (eth_dev && rte_eal_process_type() == RTE_PROC_PRIMARY)
1106                         rte_eth_dev_release_port(eth_dev);
1107                 break;
1108         }
1109         /*
1110          * XXX if something went wrong in the loop above, there is a resource
1111          * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as
1112          * long as the dpdk does not provide a way to deallocate a ethdev and a
1113          * way to enumerate the registered ethdevs to free the previous ones.
1114          */
1115         /* no port found, complain */
1116         if (!mlx5_dev[idx].ports) {
1117                 rte_errno = ENODEV;
1118                 err = rte_errno;
1119         }
1120 error:
1121         if (attr_ctx)
1122                 claim_zero(mlx5_glue->close_device(attr_ctx));
1123         if (list)
1124                 mlx5_glue->free_device_list(list);
1125         if (err) {
1126                 rte_errno = err;
1127                 return -rte_errno;
1128         }
1129         return 0;
1130 }
1131
1132 static const struct rte_pci_id mlx5_pci_id_map[] = {
1133         {
1134                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1135                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1136         },
1137         {
1138                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1139                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1140         },
1141         {
1142                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1143                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1144         },
1145         {
1146                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1147                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1148         },
1149         {
1150                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1151                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1152         },
1153         {
1154                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1155                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1156         },
1157         {
1158                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1159                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1160         },
1161         {
1162                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1163                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1164         },
1165         {
1166                 .vendor_id = 0
1167         }
1168 };
1169
1170 static struct rte_pci_driver mlx5_driver = {
1171         .driver = {
1172                 .name = MLX5_DRIVER_NAME
1173         },
1174         .id_table = mlx5_pci_id_map,
1175         .probe = mlx5_pci_probe,
1176         .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV,
1177 };
1178
1179 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1180
1181 /**
1182  * Suffix RTE_EAL_PMD_PATH with "-glue".
1183  *
1184  * This function performs a sanity check on RTE_EAL_PMD_PATH before
1185  * suffixing its last component.
1186  *
1187  * @param buf[out]
1188  *   Output buffer, should be large enough otherwise NULL is returned.
1189  * @param size
1190  *   Size of @p out.
1191  *
1192  * @return
1193  *   Pointer to @p buf or @p NULL in case suffix cannot be appended.
1194  */
1195 static char *
1196 mlx5_glue_path(char *buf, size_t size)
1197 {
1198         static const char *const bad[] = { "/", ".", "..", NULL };
1199         const char *path = RTE_EAL_PMD_PATH;
1200         size_t len = strlen(path);
1201         size_t off;
1202         int i;
1203
1204         while (len && path[len - 1] == '/')
1205                 --len;
1206         for (off = len; off && path[off - 1] != '/'; --off)
1207                 ;
1208         for (i = 0; bad[i]; ++i)
1209                 if (!strncmp(path + off, bad[i], (int)(len - off)))
1210                         goto error;
1211         i = snprintf(buf, size, "%.*s-glue", (int)len, path);
1212         if (i == -1 || (size_t)i >= size)
1213                 goto error;
1214         return buf;
1215 error:
1216         DRV_LOG(ERR,
1217                 "unable to append \"-glue\" to last component of"
1218                 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\"),"
1219                 " please re-configure DPDK");
1220         return NULL;
1221 }
1222
1223 /**
1224  * Initialization routine for run-time dependency on rdma-core.
1225  */
1226 static int
1227 mlx5_glue_init(void)
1228 {
1229         char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")];
1230         const char *path[] = {
1231                 /*
1232                  * A basic security check is necessary before trusting
1233                  * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH.
1234                  */
1235                 (geteuid() == getuid() && getegid() == getgid() ?
1236                  getenv("MLX5_GLUE_PATH") : NULL),
1237                 /*
1238                  * When RTE_EAL_PMD_PATH is set, use its glue-suffixed
1239                  * variant, otherwise let dlopen() look up libraries on its
1240                  * own.
1241                  */
1242                 (*RTE_EAL_PMD_PATH ?
1243                  mlx5_glue_path(glue_path, sizeof(glue_path)) : ""),
1244         };
1245         unsigned int i = 0;
1246         void *handle = NULL;
1247         void **sym;
1248         const char *dlmsg;
1249
1250         while (!handle && i != RTE_DIM(path)) {
1251                 const char *end;
1252                 size_t len;
1253                 int ret;
1254
1255                 if (!path[i]) {
1256                         ++i;
1257                         continue;
1258                 }
1259                 end = strpbrk(path[i], ":;");
1260                 if (!end)
1261                         end = path[i] + strlen(path[i]);
1262                 len = end - path[i];
1263                 ret = 0;
1264                 do {
1265                         char name[ret + 1];
1266
1267                         ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE,
1268                                        (int)len, path[i],
1269                                        (!len || *(end - 1) == '/') ? "" : "/");
1270                         if (ret == -1)
1271                                 break;
1272                         if (sizeof(name) != (size_t)ret + 1)
1273                                 continue;
1274                         DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"",
1275                                 name);
1276                         handle = dlopen(name, RTLD_LAZY);
1277                         break;
1278                 } while (1);
1279                 path[i] = end + 1;
1280                 if (!*end)
1281                         ++i;
1282         }
1283         if (!handle) {
1284                 rte_errno = EINVAL;
1285                 dlmsg = dlerror();
1286                 if (dlmsg)
1287                         DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg);
1288                 goto glue_error;
1289         }
1290         sym = dlsym(handle, "mlx5_glue");
1291         if (!sym || !*sym) {
1292                 rte_errno = EINVAL;
1293                 dlmsg = dlerror();
1294                 if (dlmsg)
1295                         DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg);
1296                 goto glue_error;
1297         }
1298         mlx5_glue = *sym;
1299         return 0;
1300 glue_error:
1301         if (handle)
1302                 dlclose(handle);
1303         DRV_LOG(WARNING,
1304                 "cannot initialize PMD due to missing run-time dependency on"
1305                 " rdma-core libraries (libibverbs, libmlx5)");
1306         return -rte_errno;
1307 }
1308
1309 #endif
1310
1311 /**
1312  * Driver initialization routine.
1313  */
1314 RTE_INIT(rte_mlx5_pmd_init);
1315 static void
1316 rte_mlx5_pmd_init(void)
1317 {
1318         /* Build the static tables for Verbs conversion. */
1319         mlx5_set_ptype_table();
1320         mlx5_set_cksum_table();
1321         mlx5_set_swp_types_table();
1322         /*
1323          * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
1324          * huge pages. Calling ibv_fork_init() during init allows
1325          * applications to use fork() safely for purposes other than
1326          * using this PMD, which is not supported in forked processes.
1327          */
1328         setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
1329         /* Match the size of Rx completion entry to the size of a cacheline. */
1330         if (RTE_CACHE_LINE_SIZE == 128)
1331                 setenv("MLX5_CQE_SIZE", "128", 0);
1332 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1333         if (mlx5_glue_init())
1334                 return;
1335         assert(mlx5_glue);
1336 #endif
1337 #ifndef NDEBUG
1338         /* Glue structure must not contain any NULL pointers. */
1339         {
1340                 unsigned int i;
1341
1342                 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i)
1343                         assert(((const void *const *)mlx5_glue)[i]);
1344         }
1345 #endif
1346         if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) {
1347                 DRV_LOG(ERR,
1348                         "rdma-core glue \"%s\" mismatch: \"%s\" is required",
1349                         mlx5_glue->version, MLX5_GLUE_VERSION);
1350                 return;
1351         }
1352         mlx5_glue->fork_init();
1353         rte_pci_register(&mlx5_driver);
1354         rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1355                                         mlx5_mr_mem_event_cb, NULL);
1356 }
1357
1358 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1359 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1360 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");
1361
1362 /** Initialize driver log type. */
1363 RTE_INIT(vdev_netvsc_init_log)
1364 {
1365         mlx5_logtype = rte_log_register("pmd.net.mlx5");
1366         if (mlx5_logtype >= 0)
1367                 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
1368 }