drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12 #include <net/if.h>
  13 #include <sys/mman.h>
  14 #include <linux/rtnetlink.h>
  15
  16 /* Verbs header. */
  17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  18 #ifdef PEDANTIC
  19 #pragma GCC diagnostic ignored "-Wpedantic"
  20 #endif
  21 #include <infiniband/verbs.h>
  22 #ifdef PEDANTIC
  23 #pragma GCC diagnostic error "-Wpedantic"
  24 #endif
  25
  26 #include <rte_malloc.h>
  27 #include <rte_ethdev_driver.h>
  28 #include <rte_ethdev_pci.h>
  29 #include <rte_pci.h>
  30 #include <rte_bus_pci.h>
  31 #include <rte_common.h>
  32 #include <rte_kvargs.h>
  33 #include <rte_rwlock.h>
  34 #include <rte_spinlock.h>
  35 #include <rte_string_fns.h>
  36 #include <rte_alarm.h>
  37
  38 #include <mlx5_glue.h>
  39 #include <mlx5_devx_cmds.h>
  40 #include <mlx5_common.h>
  41 #include <mlx5_common_os.h>
  42 #include <mlx5_common_mp.h>
  43
  44 #include "mlx5_defs.h"
  45 #include "mlx5.h"
  46 #include "mlx5_utils.h"
  47 #include "mlx5_rxtx.h"
  48 #include "mlx5_autoconf.h"
  49 #include "mlx5_mr.h"
  50 #include "mlx5_flow.h"
  51 #include "rte_pmd_mlx5.h"
  52
  53 /* Device parameter to enable RX completion queue compression. */
  54 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  55
  56 /* Device parameter to enable RX completion entry padding to 128B. */
  57 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
  58
  59 /* Device parameter to enable padding Rx packet to cacheline size. */
  60 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  61
  62 /* Device parameter to enable Multi-Packet Rx queue. */
  63 #define MLX5_RX_MPRQ_EN "mprq_en"
  64
  65 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  66 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  67
  68 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  69 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  70
  71 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  72 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  73
  74 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  75 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  76
  77 /* Device parameter to configure inline send. Deprecated, ignored.*/
  78 #define MLX5_TXQ_INLINE "txq_inline"
  79
  80 /* Device parameter to limit packet size to inline with ordinary SEND. */
  81 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  82
  83 /* Device parameter to configure minimal data size to inline. */
  84 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  85
  86 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  87 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  88
  89 /*
  90  * Device parameter to configure the number of TX queues threshold for
  91  * enabling inline send.
  92  */
  93 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  94
  95 /*
  96  * Device parameter to configure the number of TX queues threshold for
  97  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  98  */
  99 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
 100
 101 /* Device parameter to enable multi-packet send WQEs. */
 102 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
 103
 104 /*
 105  * Device parameter to force doorbell register mapping
 106  * to non-cahed region eliminating the extra write memory barrier.
 107  */
 108 #define MLX5_TX_DB_NC "tx_db_nc"
 109
 110 /*
 111  * Device parameter to include 2 dsegs in the title WQEBB.
 112  * Deprecated, ignored.
 113  */
 114 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 115
 116 /*
 117  * Device parameter to limit the size of inlining packet.
 118  * Deprecated, ignored.
 119  */
 120 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 121
 122 /*
 123  * Device parameter to enable Tx scheduling on timestamps
 124  * and specify the packet pacing granularity in nanoseconds.
 125  */
 126 #define MLX5_TX_PP "tx_pp"
 127
 128 /*
 129  * Device parameter to specify skew in nanoseconds on Tx datapath,
 130  * it represents the time between SQ start WQE processing and
 131  * appearing actual packet data on the wire.
 132  */
 133 #define MLX5_TX_SKEW "tx_skew"
 134
 135 /*
 136  * Device parameter to enable hardware Tx vector.
 137  * Deprecated, ignored (no vectorized Tx routines anymore).
 138  */
 139 #define MLX5_TX_VEC_EN "tx_vec_en"
 140
 141 /* Device parameter to enable hardware Rx vector. */
 142 #define MLX5_RX_VEC_EN "rx_vec_en"
 143
 144 /* Allow L3 VXLAN flow creation. */
 145 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 146
 147 /* Activate DV E-Switch flow steering. */
 148 #define MLX5_DV_ESW_EN "dv_esw_en"
 149
 150 /* Activate DV flow steering. */
 151 #define MLX5_DV_FLOW_EN "dv_flow_en"
 152
 153 /* Enable extensive flow metadata support. */
 154 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 155
 156 /* Device parameter to let the user manage the lacp traffic of bonded device */
 157 #define MLX5_LACP_BY_USER "lacp_by_user"
 158
 159 /* Activate Netlink support in VF mode. */
 160 #define MLX5_VF_NL_EN "vf_nl_en"
 161
 162 /* Enable extending memsegs when creating a MR. */
 163 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 164
 165 /* Select port representors to instantiate. */
 166 #define MLX5_REPRESENTOR "representor"
 167
 168 /* Device parameter to configure the maximum number of dump files per queue. */
 169 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 170
 171 /* Configure timeout of LRO session (in microseconds). */
 172 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 173
 174 /*
 175  * Device parameter to configure the total data buffer size for a single
 176  * hairpin queue (logarithm value).
 177  */
 178 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 179
 180 /* Flow memory reclaim mode. */
 181 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 182
 183 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
 184
 185 /* Shared memory between primary and secondary processes. */
 186 struct mlx5_shared_data *mlx5_shared_data;
 187
 188 /* Spinlock for mlx5_shared_data allocation. */
 189 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
 190
 191 /* Process local data for secondary processes. */
 192 static struct mlx5_local_data mlx5_local_data;
 193
 194 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 195                                                 LIST_HEAD_INITIALIZER();
 196 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
 197
 198 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 199 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 200         {
 201                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 202                 .trunk_size = 64,
 203                 .grow_trunk = 3,
 204                 .grow_shift = 2,
 205                 .need_lock = 0,
 206                 .release_mem_en = 1,
 207                 .malloc = rte_malloc_socket,
 208                 .free = rte_free,
 209                 .type = "mlx5_encap_decap_ipool",
 210         },
 211         {
 212                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 213                 .trunk_size = 64,
 214                 .grow_trunk = 3,
 215                 .grow_shift = 2,
 216                 .need_lock = 0,
 217                 .release_mem_en = 1,
 218                 .malloc = rte_malloc_socket,
 219                 .free = rte_free,
 220                 .type = "mlx5_push_vlan_ipool",
 221         },
 222         {
 223                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 224                 .trunk_size = 64,
 225                 .grow_trunk = 3,
 226                 .grow_shift = 2,
 227                 .need_lock = 0,
 228                 .release_mem_en = 1,
 229                 .malloc = rte_malloc_socket,
 230                 .free = rte_free,
 231                 .type = "mlx5_tag_ipool",
 232         },
 233         {
 234                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 235                 .trunk_size = 64,
 236                 .grow_trunk = 3,
 237                 .grow_shift = 2,
 238                 .need_lock = 0,
 239                 .release_mem_en = 1,
 240                 .malloc = rte_malloc_socket,
 241                 .free = rte_free,
 242                 .type = "mlx5_port_id_ipool",
 243         },
 244         {
 245                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 246                 .trunk_size = 64,
 247                 .grow_trunk = 3,
 248                 .grow_shift = 2,
 249                 .need_lock = 0,
 250                 .release_mem_en = 1,
 251                 .malloc = rte_malloc_socket,
 252                 .free = rte_free,
 253                 .type = "mlx5_jump_ipool",
 254         },
 255 #endif
 256         {
 257                 .size = sizeof(struct mlx5_flow_meter),
 258                 .trunk_size = 64,
 259                 .grow_trunk = 3,
 260                 .grow_shift = 2,
 261                 .need_lock = 0,
 262                 .release_mem_en = 1,
 263                 .malloc = rte_malloc_socket,
 264                 .free = rte_free,
 265                 .type = "mlx5_meter_ipool",
 266         },
 267         {
 268                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 269                 .trunk_size = 64,
 270                 .grow_trunk = 3,
 271                 .grow_shift = 2,
 272                 .need_lock = 0,
 273                 .release_mem_en = 1,
 274                 .malloc = rte_malloc_socket,
 275                 .free = rte_free,
 276                 .type = "mlx5_mcp_ipool",
 277         },
 278         {
 279                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 280                 .trunk_size = 64,
 281                 .grow_trunk = 3,
 282                 .grow_shift = 2,
 283                 .need_lock = 0,
 284                 .release_mem_en = 1,
 285                 .malloc = rte_malloc_socket,
 286                 .free = rte_free,
 287                 .type = "mlx5_hrxq_ipool",
 288         },
 289         {
 290                 /*
 291                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 292                  * It set in run time according to PCI function configuration.
 293                  */
 294                 .size = 0,
 295                 .trunk_size = 64,
 296                 .grow_trunk = 3,
 297                 .grow_shift = 2,
 298                 .need_lock = 0,
 299                 .release_mem_en = 1,
 300                 .malloc = rte_malloc_socket,
 301                 .free = rte_free,
 302                 .type = "mlx5_flow_handle_ipool",
 303         },
 304         {
 305                 .size = sizeof(struct rte_flow),
 306                 .trunk_size = 4096,
 307                 .need_lock = 1,
 308                 .release_mem_en = 1,
 309                 .malloc = rte_malloc_socket,
 310                 .free = rte_free,
 311                 .type = "rte_flow_ipool",
 312         },
 313 };
 314
 315
 316 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 317 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 318
 319 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 320
 321 /**
 322  * Allocate ID pool structure.
 323  *
 324  * @param[in] max_id
 325  *   The maximum id can be allocated from the pool.
 326  *
 327  * @return
 328  *   Pointer to pool object, NULL value otherwise.
 329  */
 330 struct mlx5_flow_id_pool *
 331 mlx5_flow_id_pool_alloc(uint32_t max_id)
 332 {
 333         struct mlx5_flow_id_pool *pool;
 334         void *mem;
 335
 336         pool = rte_zmalloc("id pool allocation", sizeof(*pool),
 337                            RTE_CACHE_LINE_SIZE);
 338         if (!pool) {
 339                 DRV_LOG(ERR, "can't allocate id pool");
 340                 rte_errno  = ENOMEM;
 341                 return NULL;
 342         }
 343         mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
 344                           RTE_CACHE_LINE_SIZE);
 345         if (!mem) {
 346                 DRV_LOG(ERR, "can't allocate mem for id pool");
 347                 rte_errno  = ENOMEM;
 348                 goto error;
 349         }
 350         pool->free_arr = mem;
 351         pool->curr = pool->free_arr;
 352         pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
 353         pool->base_index = 0;
 354         pool->max_id = max_id;
 355         return pool;
 356 error:
 357         rte_free(pool);
 358         return NULL;
 359 }
 360
 361 /**
 362  * Release ID pool structure.
 363  *
 364  * @param[in] pool
 365  *   Pointer to flow id pool object to free.
 366  */
 367 void
 368 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
 369 {
 370         rte_free(pool->free_arr);
 371         rte_free(pool);
 372 }
 373
 374 /**
 375  * Generate ID.
 376  *
 377  * @param[in] pool
 378  *   Pointer to flow id pool.
 379  * @param[out] id
 380  *   The generated ID.
 381  *
 382  * @return
 383  *   0 on success, error value otherwise.
 384  */
 385 uint32_t
 386 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
 387 {
 388         if (pool->curr == pool->free_arr) {
 389                 if (pool->base_index == pool->max_id) {
 390                         rte_errno  = ENOMEM;
 391                         DRV_LOG(ERR, "no free id");
 392                         return -rte_errno;
 393                 }
 394                 *id = ++pool->base_index;
 395                 return 0;
 396         }
 397         *id = *(--pool->curr);
 398         return 0;
 399 }
 400
 401 /**
 402  * Release ID.
 403  *
 404  * @param[in] pool
 405  *   Pointer to flow id pool.
 406  * @param[out] id
 407  *   The generated ID.
 408  *
 409  * @return
 410  *   0 on success, error value otherwise.
 411  */
 412 uint32_t
 413 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
 414 {
 415         uint32_t size;
 416         uint32_t size2;
 417         void *mem;
 418
 419         if (pool->curr == pool->last) {
 420                 size = pool->curr - pool->free_arr;
 421                 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
 422                 MLX5_ASSERT(size2 > size);
 423                 mem = rte_malloc("", size2 * sizeof(uint32_t), 0);
 424                 if (!mem) {
 425                         DRV_LOG(ERR, "can't allocate mem for id pool");
 426                         rte_errno  = ENOMEM;
 427                         return -rte_errno;
 428                 }
 429                 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
 430                 rte_free(pool->free_arr);
 431                 pool->free_arr = mem;
 432                 pool->curr = pool->free_arr + size;
 433                 pool->last = pool->free_arr + size2;
 434         }
 435         *pool->curr = id;
 436         pool->curr++;
 437         return 0;
 438 }
 439
 440 /**
 441  * Initialize the shared aging list information per port.
 442  *
 443  * @param[in] sh
 444  *   Pointer to mlx5_dev_ctx_shared object.
 445  */
 446 static void
 447 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 448 {
 449         uint32_t i;
 450         struct mlx5_age_info *age_info;
 451
 452         for (i = 0; i < sh->max_port; i++) {
 453                 age_info = &sh->port[i].age_info;
 454                 age_info->flags = 0;
 455                 TAILQ_INIT(&age_info->aged_counters);
 456                 rte_spinlock_init(&age_info->aged_sl);
 457                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 458         }
 459 }
 460
 461 /**
 462  * Initialize the counters management structure.
 463  *
 464  * @param[in] sh
 465  *   Pointer to mlx5_dev_ctx_shared object to free
 466  */
 467 static void
 468 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 469 {
 470         int i;
 471
 472         memset(&sh->cmng, 0, sizeof(sh->cmng));
 473         TAILQ_INIT(&sh->cmng.flow_counters);
 474         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 475                 sh->cmng.ccont[i].min_id = MLX5_CNT_BATCH_OFFSET;
 476                 sh->cmng.ccont[i].max_id = -1;
 477                 sh->cmng.ccont[i].last_pool_idx = POOL_IDX_INVALID;
 478                 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
 479                 rte_spinlock_init(&sh->cmng.ccont[i].resize_sl);
 480                 TAILQ_INIT(&sh->cmng.ccont[i].counters);
 481                 rte_spinlock_init(&sh->cmng.ccont[i].csl);
 482         }
 483 }
 484
 485 /**
 486  * Destroy all the resources allocated for a counter memory management.
 487  *
 488  * @param[in] mng
 489  *   Pointer to the memory management structure.
 490  */
 491 static void
 492 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 493 {
 494         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 495
 496         LIST_REMOVE(mng, next);
 497         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 498         claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
 499         rte_free(mem);
 500 }
 501
 502 /**
 503  * Close and release all the resources of the counters management.
 504  *
 505  * @param[in] sh
 506  *   Pointer to mlx5_dev_ctx_shared object to free.
 507  */
 508 static void
 509 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 510 {
 511         struct mlx5_counter_stats_mem_mng *mng;
 512         int i;
 513         int j;
 514         int retries = 1024;
 515
 516         rte_errno = 0;
 517         while (--retries) {
 518                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 519                 if (rte_errno != EINPROGRESS)
 520                         break;
 521                 rte_pause();
 522         }
 523         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 524                 struct mlx5_flow_counter_pool *pool;
 525                 uint32_t batch = !!(i > 1);
 526
 527                 if (!sh->cmng.ccont[i].pools)
 528                         continue;
 529                 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 530                 while (pool) {
 531                         if (batch && pool->min_dcs)
 532                                 claim_zero(mlx5_devx_cmd_destroy
 533                                                                (pool->min_dcs));
 534                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 535                                 if (MLX5_POOL_GET_CNT(pool, j)->action)
 536                                         claim_zero
 537                                          (mlx5_glue->destroy_flow_action
 538                                           (MLX5_POOL_GET_CNT
 539                                           (pool, j)->action));
 540                                 if (!batch && MLX5_GET_POOL_CNT_EXT
 541                                     (pool, j)->dcs)
 542                                         claim_zero(mlx5_devx_cmd_destroy
 543                                                    (MLX5_GET_POOL_CNT_EXT
 544                                                     (pool, j)->dcs));
 545                         }
 546                         TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, next);
 547                         rte_free(pool);
 548                         pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 549                 }
 550                 rte_free(sh->cmng.ccont[i].pools);
 551         }
 552         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 553         while (mng) {
 554                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 555                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 556         }
 557         memset(&sh->cmng, 0, sizeof(sh->cmng));
 558 }
 559
 560 /**
 561  * Initialize the flow resources' indexed mempool.
 562  *
 563  * @param[in] sh
 564  *   Pointer to mlx5_dev_ctx_shared object.
 565  * @param[in] sh
 566  *   Pointer to user dev config.
 567  */
 568 static void
 569 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 570                        const struct mlx5_dev_config *config)
 571 {
 572         uint8_t i;
 573         struct mlx5_indexed_pool_config cfg;
 574
 575         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 576                 cfg = mlx5_ipool_cfg[i];
 577                 switch (i) {
 578                 default:
 579                         break;
 580                 /*
 581                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 582                  * according to PCI function flow configuration.
 583                  */
 584                 case MLX5_IPOOL_MLX5_FLOW:
 585                         cfg.size = config->dv_flow_en ?
 586                                 sizeof(struct mlx5_flow_handle) :
 587                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 588                         break;
 589                 }
 590                 if (config->reclaim_mode)
 591                         cfg.release_mem_en = 1;
 592                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 593         }
 594 }
 595
 596 /**
 597  * Release the flow resources' indexed mempool.
 598  *
 599  * @param[in] sh
 600  *   Pointer to mlx5_dev_ctx_shared object.
 601  */
 602 static void
 603 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 604 {
 605         uint8_t i;
 606
 607         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 608                 mlx5_ipool_destroy(sh->ipool[i]);
 609 }
 610
 611 /*
 612  * Check if dynamic flex parser for eCPRI already exists.
 613  *
 614  * @param dev
 615  *   Pointer to Ethernet device structure.
 616  *
 617  * @return
 618  *   true on exists, false on not.
 619  */
 620 bool
 621 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
 622 {
 623         struct mlx5_priv *priv = dev->data->dev_private;
 624         struct mlx5_flex_parser_profiles *prf =
 625                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 626
 627         return !!prf->obj;
 628 }
 629
 630 /*
 631  * Allocation of a flex parser for eCPRI. Once created, this parser related
 632  * resources will be held until the device is closed.
 633  *
 634  * @param dev
 635  *   Pointer to Ethernet device structure.
 636  *
 637  * @return
 638  *   0 on success, a negative errno value otherwise and rte_errno is set.
 639  */
 640 int
 641 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
 642 {
 643         struct mlx5_priv *priv = dev->data->dev_private;
 644         struct mlx5_flex_parser_profiles *prf =
 645                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 646         struct mlx5_devx_graph_node_attr node = {
 647                 .modify_field_select = 0,
 648         };
 649         uint32_t ids[8];
 650         int ret;
 651
 652         node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
 653         /* 8 bytes now: 4B common header + 4B message body header. */
 654         node.header_length_base_value = 0x8;
 655         /* After MAC layer: Ether / VLAN. */
 656         node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
 657         /* Type of compared condition should be 0xAEFE in the L2 layer. */
 658         node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
 659         /* Sample #0: type in common header. */
 660         node.sample[0].flow_match_sample_en = 1;
 661         /* Fixed offset. */
 662         node.sample[0].flow_match_sample_offset_mode = 0x0;
 663         /* Only the 2nd byte will be used. */
 664         node.sample[0].flow_match_sample_field_base_offset = 0x0;
 665         /* Sample #1: message payload. */
 666         node.sample[1].flow_match_sample_en = 1;
 667         /* Fixed offset. */
 668         node.sample[1].flow_match_sample_offset_mode = 0x0;
 669         /*
 670          * Only the first two bytes will be used right now, and its offset will
 671          * start after the common header that with the length of a DW(u32).
 672          */
 673         node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
 674         prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
 675         if (!prf->obj) {
 676                 DRV_LOG(ERR, "Failed to create flex parser node object.");
 677                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 678         }
 679         prf->num = 2;
 680         ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
 681         if (ret) {
 682                 DRV_LOG(ERR, "Failed to query sample IDs.");
 683                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 684         }
 685         prf->offset[0] = 0x0;
 686         prf->offset[1] = sizeof(uint32_t);
 687         prf->ids[0] = ids[0];
 688         prf->ids[1] = ids[1];
 689         return 0;
 690 }
 691
 692 /*
 693  * Destroy the flex parser node, including the parser itself, input / output
 694  * arcs and DW samples. Resources could be reused then.
 695  *
 696  * @param dev
 697  *   Pointer to Ethernet device structure.
 698  */
 699 static void
 700 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
 701 {
 702         struct mlx5_priv *priv = dev->data->dev_private;
 703         struct mlx5_flex_parser_profiles *prf =
 704                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 705
 706         if (prf->obj)
 707                 mlx5_devx_cmd_destroy(prf->obj);
 708         prf->obj = NULL;
 709 }
 710
 711 /**
 712  * Allocate shared device context. If there is multiport device the
 713  * master and representors will share this context, if there is single
 714  * port dedicated device, the context will be used by only given
 715  * port due to unification.
 716  *
 717  * Routine first searches the context for the specified device name,
 718  * if found the shared context assumed and reference counter is incremented.
 719  * If no context found the new one is created and initialized with specified
 720  * device context and parameters.
 721  *
 722  * @param[in] spawn
 723  *   Pointer to the device attributes (name, port, etc).
 724  * @param[in] config
 725  *   Pointer to device configuration structure.
 726  *
 727  * @return
 728  *   Pointer to mlx5_dev_ctx_shared object on success,
 729  *   otherwise NULL and rte_errno is set.
 730  */
 731 struct mlx5_dev_ctx_shared *
 732 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
 733                            const struct mlx5_dev_config *config)
 734 {
 735         struct mlx5_dev_ctx_shared *sh;
 736         int err = 0;
 737         uint32_t i;
 738         struct mlx5_devx_tis_attr tis_attr = { 0 };
 739
 740         MLX5_ASSERT(spawn);
 741         /* Secondary process should not create the shared context. */
 742         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 743         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 744         /* Search for IB context by device name. */
 745         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
 746                 if (!strcmp(sh->ibdev_name,
 747                         mlx5_os_get_dev_device_name(spawn->phys_dev))) {
 748                         sh->refcnt++;
 749                         goto exit;
 750                 }
 751         }
 752         /* No device found, we have to create new shared context. */
 753         MLX5_ASSERT(spawn->max_port);
 754         sh = rte_zmalloc("ethdev shared ib context",
 755                          sizeof(struct mlx5_dev_ctx_shared) +
 756                          spawn->max_port *
 757                          sizeof(struct mlx5_dev_shared_port),
 758                          RTE_CACHE_LINE_SIZE);
 759         if (!sh) {
 760                 DRV_LOG(ERR, "shared context allocation failure");
 761                 rte_errno  = ENOMEM;
 762                 goto exit;
 763         }
 764         err = mlx5_os_open_device(spawn, config, sh);
 765         if (!sh->ctx)
 766                 goto error;
 767         err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
 768         if (err) {
 769                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
 770                 goto error;
 771         }
 772         sh->refcnt = 1;
 773         sh->max_port = spawn->max_port;
 774         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
 775                 sizeof(sh->ibdev_name) - 1);
 776         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
 777                 sizeof(sh->ibdev_path) - 1);
 778         /*
 779          * Setting port_id to max unallowed value means
 780          * there is no interrupt subhandler installed for
 781          * the given port index i.
 782          */
 783         for (i = 0; i < sh->max_port; i++) {
 784                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 785                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
 786         }
 787         sh->pd = mlx5_glue->alloc_pd(sh->ctx);
 788         if (sh->pd == NULL) {
 789                 DRV_LOG(ERR, "PD allocation failure");
 790                 err = ENOMEM;
 791                 goto error;
 792         }
 793         if (sh->devx) {
 794                 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
 795                 if (err) {
 796                         DRV_LOG(ERR, "Fail to extract pdn from PD");
 797                         goto error;
 798                 }
 799                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
 800                 if (!sh->td) {
 801                         DRV_LOG(ERR, "TD allocation failure");
 802                         err = ENOMEM;
 803                         goto error;
 804                 }
 805                 tis_attr.transport_domain = sh->td->id;
 806                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
 807                 if (!sh->tis) {
 808                         DRV_LOG(ERR, "TIS allocation failure");
 809                         err = ENOMEM;
 810                         goto error;
 811                 }
 812                 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, 0);
 813                 if (!sh->tx_uar) {
 814                         DRV_LOG(ERR, "Failed to allocate DevX UAR.");
 815                         err = ENOMEM;
 816                         goto error;
 817                 }
 818         }
 819         sh->flow_id_pool = mlx5_flow_id_pool_alloc
 820                                         ((1 << HAIRPIN_FLOW_ID_BITS) - 1);
 821         if (!sh->flow_id_pool) {
 822                 DRV_LOG(ERR, "can't create flow id pool");
 823                 err = ENOMEM;
 824                 goto error;
 825         }
 826 #ifndef RTE_ARCH_64
 827         /* Initialize UAR access locks for 32bit implementations. */
 828         rte_spinlock_init(&sh->uar_lock_cq);
 829         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
 830                 rte_spinlock_init(&sh->uar_lock[i]);
 831 #endif
 832         /*
 833          * Once the device is added to the list of memory event
 834          * callback, its global MR cache table cannot be expanded
 835          * on the fly because of deadlock. If it overflows, lookup
 836          * should be done by searching MR list linearly, which is slow.
 837          *
 838          * At this point the device is not added to the memory
 839          * event list yet, context is just being created.
 840          */
 841         err = mlx5_mr_btree_init(&sh->share_cache.cache,
 842                                  MLX5_MR_BTREE_CACHE_N * 2,
 843                                  spawn->pci_dev->device.numa_node);
 844         if (err) {
 845                 err = rte_errno;
 846                 goto error;
 847         }
 848         mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
 849                               &sh->share_cache.dereg_mr_cb);
 850         mlx5_os_dev_shared_handler_install(sh);
 851         sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
 852         if (!sh->cnt_id_tbl) {
 853                 err = rte_errno;
 854                 goto error;
 855         }
 856         mlx5_flow_aging_init(sh);
 857         mlx5_flow_counters_mng_init(sh);
 858         mlx5_flow_ipool_create(sh, config);
 859         /* Add device to memory callback list. */
 860         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 861         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
 862                          sh, mem_event_cb);
 863         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 864         /* Add context to the global device list. */
 865         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
 866 exit:
 867         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 868         return sh;
 869 error:
 870         pthread_mutex_destroy(&sh->txpp.mutex);
 871         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 872         MLX5_ASSERT(sh);
 873         if (sh->cnt_id_tbl) {
 874                 mlx5_l3t_destroy(sh->cnt_id_tbl);
 875                 sh->cnt_id_tbl = NULL;
 876         }
 877         if (sh->tx_uar) {
 878                 mlx5_glue->devx_free_uar(sh->tx_uar);
 879                 sh->tx_uar = NULL;
 880         }
 881         if (sh->tis)
 882                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 883         if (sh->td)
 884                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 885         if (sh->pd)
 886                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 887         if (sh->ctx)
 888                 claim_zero(mlx5_glue->close_device(sh->ctx));
 889         if (sh->flow_id_pool)
 890                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 891         rte_free(sh);
 892         MLX5_ASSERT(err > 0);
 893         rte_errno = err;
 894         return NULL;
 895 }
 896
 897 /**
 898  * Free shared IB device context. Decrement counter and if zero free
 899  * all allocated resources and close handles.
 900  *
 901  * @param[in] sh
 902  *   Pointer to mlx5_dev_ctx_shared object to free
 903  */
 904 void
 905 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
 906 {
 907         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 908 #ifdef RTE_LIBRTE_MLX5_DEBUG
 909         /* Check the object presence in the list. */
 910         struct mlx5_dev_ctx_shared *lctx;
 911
 912         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
 913                 if (lctx == sh)
 914                         break;
 915         MLX5_ASSERT(lctx);
 916         if (lctx != sh) {
 917                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
 918                 goto exit;
 919         }
 920 #endif
 921         MLX5_ASSERT(sh);
 922         MLX5_ASSERT(sh->refcnt);
 923         /* Secondary process should not free the shared context. */
 924         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 925         if (--sh->refcnt)
 926                 goto exit;
 927         /* Remove from memory callback device list. */
 928         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 929         LIST_REMOVE(sh, mem_event_cb);
 930         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 931         /* Release created Memory Regions. */
 932         mlx5_mr_release_cache(&sh->share_cache);
 933         /* Remove context from the global device list. */
 934         LIST_REMOVE(sh, next);
 935         /*
 936          *  Ensure there is no async event handler installed.
 937          *  Only primary process handles async device events.
 938          **/
 939         mlx5_flow_counters_mng_close(sh);
 940         mlx5_flow_ipool_destroy(sh);
 941         mlx5_os_dev_shared_handler_uninstall(sh);
 942         if (sh->cnt_id_tbl) {
 943                 mlx5_l3t_destroy(sh->cnt_id_tbl);
 944                 sh->cnt_id_tbl = NULL;
 945         }
 946         if (sh->tx_uar) {
 947                 mlx5_glue->devx_free_uar(sh->tx_uar);
 948                 sh->tx_uar = NULL;
 949         }
 950         if (sh->pd)
 951                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 952         if (sh->tis)
 953                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 954         if (sh->td)
 955                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 956         if (sh->ctx)
 957                 claim_zero(mlx5_glue->close_device(sh->ctx));
 958         if (sh->flow_id_pool)
 959                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 960         pthread_mutex_destroy(&sh->txpp.mutex);
 961         rte_free(sh);
 962 exit:
 963         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 964 }
 965
 966 /**
 967  * Destroy table hash list and all the root entries per domain.
 968  *
 969  * @param[in] priv
 970  *   Pointer to the private device data structure.
 971  */
 972 void
 973 mlx5_free_table_hash_list(struct mlx5_priv *priv)
 974 {
 975         struct mlx5_dev_ctx_shared *sh = priv->sh;
 976         struct mlx5_flow_tbl_data_entry *tbl_data;
 977         union mlx5_flow_tbl_key table_key = {
 978                 {
 979                         .table_id = 0,
 980                         .reserved = 0,
 981                         .domain = 0,
 982                         .direction = 0,
 983                 }
 984         };
 985         struct mlx5_hlist_entry *pos;
 986
 987         if (!sh->flow_tbls)
 988                 return;
 989         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 990         if (pos) {
 991                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 992                                         entry);
 993                 MLX5_ASSERT(tbl_data);
 994                 mlx5_hlist_remove(sh->flow_tbls, pos);
 995                 rte_free(tbl_data);
 996         }
 997         table_key.direction = 1;
 998         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 999         if (pos) {
1000                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1001                                         entry);
1002                 MLX5_ASSERT(tbl_data);
1003                 mlx5_hlist_remove(sh->flow_tbls, pos);
1004                 rte_free(tbl_data);
1005         }
1006         table_key.direction = 0;
1007         table_key.domain = 1;
1008         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1009         if (pos) {
1010                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1011                                         entry);
1012                 MLX5_ASSERT(tbl_data);
1013                 mlx5_hlist_remove(sh->flow_tbls, pos);
1014                 rte_free(tbl_data);
1015         }
1016         mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
1017 }
1018
1019 /**
1020  * Initialize flow table hash list and create the root tables entry
1021  * for each domain.
1022  *
1023  * @param[in] priv
1024  *   Pointer to the private device data structure.
1025  *
1026  * @return
1027  *   Zero on success, positive error code otherwise.
1028  */
1029 int
1030 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
1031 {
1032         struct mlx5_dev_ctx_shared *sh = priv->sh;
1033         char s[MLX5_HLIST_NAMESIZE];
1034         int err = 0;
1035
1036         MLX5_ASSERT(sh);
1037         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1038         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
1039         if (!sh->flow_tbls) {
1040                 DRV_LOG(ERR, "flow tables with hash creation failed.");
1041                 err = ENOMEM;
1042                 return err;
1043         }
1044 #ifndef HAVE_MLX5DV_DR
1045         /*
1046          * In case we have not DR support, the zero tables should be created
1047          * because DV expect to see them even if they cannot be created by
1048          * RDMA-CORE.
1049          */
1050         union mlx5_flow_tbl_key table_key = {
1051                 {
1052                         .table_id = 0,
1053                         .reserved = 0,
1054                         .domain = 0,
1055                         .direction = 0,
1056                 }
1057         };
1058         struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL,
1059                                                           sizeof(*tbl_data), 0);
1060
1061         if (!tbl_data) {
1062                 err = ENOMEM;
1063                 goto error;
1064         }
1065         tbl_data->entry.key = table_key.v64;
1066         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1067         if (err)
1068                 goto error;
1069         rte_atomic32_init(&tbl_data->tbl.refcnt);
1070         rte_atomic32_inc(&tbl_data->tbl.refcnt);
1071         table_key.direction = 1;
1072         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
1073         if (!tbl_data) {
1074                 err = ENOMEM;
1075                 goto error;
1076         }
1077         tbl_data->entry.key = table_key.v64;
1078         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1079         if (err)
1080                 goto error;
1081         rte_atomic32_init(&tbl_data->tbl.refcnt);
1082         rte_atomic32_inc(&tbl_data->tbl.refcnt);
1083         table_key.direction = 0;
1084         table_key.domain = 1;
1085         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
1086         if (!tbl_data) {
1087                 err = ENOMEM;
1088                 goto error;
1089         }
1090         tbl_data->entry.key = table_key.v64;
1091         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1092         if (err)
1093                 goto error;
1094         rte_atomic32_init(&tbl_data->tbl.refcnt);
1095         rte_atomic32_inc(&tbl_data->tbl.refcnt);
1096         return err;
1097 error:
1098         mlx5_free_table_hash_list(priv);
1099 #endif /* HAVE_MLX5DV_DR */
1100         return err;
1101 }
1102
1103 /**
1104  * Initialize shared data between primary and secondary process.
1105  *
1106  * A memzone is reserved by primary process and secondary processes attach to
1107  * the memzone.
1108  *
1109  * @return
1110  *   0 on success, a negative errno value otherwise and rte_errno is set.
1111  */
1112 static int
1113 mlx5_init_shared_data(void)
1114 {
1115         const struct rte_memzone *mz;
1116         int ret = 0;
1117
1118         rte_spinlock_lock(&mlx5_shared_data_lock);
1119         if (mlx5_shared_data == NULL) {
1120                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
1121                         /* Allocate shared memory. */
1122                         mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
1123                                                  sizeof(*mlx5_shared_data),
1124                                                  SOCKET_ID_ANY, 0);
1125                         if (mz == NULL) {
1126                                 DRV_LOG(ERR,
1127                                         "Cannot allocate mlx5 shared data");
1128                                 ret = -rte_errno;
1129                                 goto error;
1130                         }
1131                         mlx5_shared_data = mz->addr;
1132                         memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
1133                         rte_spinlock_init(&mlx5_shared_data->lock);
1134                 } else {
1135                         /* Lookup allocated shared memory. */
1136                         mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
1137                         if (mz == NULL) {
1138                                 DRV_LOG(ERR,
1139                                         "Cannot attach mlx5 shared data");
1140                                 ret = -rte_errno;
1141                                 goto error;
1142                         }
1143                         mlx5_shared_data = mz->addr;
1144                         memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
1145                 }
1146         }
1147 error:
1148         rte_spinlock_unlock(&mlx5_shared_data_lock);
1149         return ret;
1150 }
1151
1152 /**
1153  * Retrieve integer value from environment variable.
1154  *
1155  * @param[in] name
1156  *   Environment variable name.
1157  *
1158  * @return
1159  *   Integer value, 0 if the variable is not set.
1160  */
1161 int
1162 mlx5_getenv_int(const char *name)
1163 {
1164         const char *val = getenv(name);
1165
1166         if (val == NULL)
1167                 return 0;
1168         return atoi(val);
1169 }
1170
1171 /**
1172  * DPDK callback to add udp tunnel port
1173  *
1174  * @param[in] dev
1175  *   A pointer to eth_dev
1176  * @param[in] udp_tunnel
1177  *   A pointer to udp tunnel
1178  *
1179  * @return
1180  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1181  */
1182 int
1183 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1184                          struct rte_eth_udp_tunnel *udp_tunnel)
1185 {
1186         MLX5_ASSERT(udp_tunnel != NULL);
1187         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1188             udp_tunnel->udp_port == 4789)
1189                 return 0;
1190         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1191             udp_tunnel->udp_port == 4790)
1192                 return 0;
1193         return -ENOTSUP;
1194 }
1195
1196 /**
1197  * Initialize process private data structure.
1198  *
1199  * @param dev
1200  *   Pointer to Ethernet device structure.
1201  *
1202  * @return
1203  *   0 on success, a negative errno value otherwise and rte_errno is set.
1204  */
1205 int
1206 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1207 {
1208         struct mlx5_priv *priv = dev->data->dev_private;
1209         struct mlx5_proc_priv *ppriv;
1210         size_t ppriv_size;
1211
1212         /*
1213          * UAR register table follows the process private structure. BlueFlame
1214          * registers for Tx queues are stored in the table.
1215          */
1216         ppriv_size =
1217                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1218         ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
1219                                   RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1220         if (!ppriv) {
1221                 rte_errno = ENOMEM;
1222                 return -rte_errno;
1223         }
1224         ppriv->uar_table_sz = ppriv_size;
1225         dev->process_private = ppriv;
1226         return 0;
1227 }
1228
1229 /**
1230  * Un-initialize process private data structure.
1231  *
1232  * @param dev
1233  *   Pointer to Ethernet device structure.
1234  */
1235 static void
1236 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1237 {
1238         if (!dev->process_private)
1239                 return;
1240         rte_free(dev->process_private);
1241         dev->process_private = NULL;
1242 }
1243
1244 /**
1245  * DPDK callback to close the device.
1246  *
1247  * Destroy all queues and objects, free memory.
1248  *
1249  * @param dev
1250  *   Pointer to Ethernet device structure.
1251  */
1252 void
1253 mlx5_dev_close(struct rte_eth_dev *dev)
1254 {
1255         struct mlx5_priv *priv = dev->data->dev_private;
1256         unsigned int i;
1257         int ret;
1258
1259         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1260                 /* Check if process_private released. */
1261                 if (!dev->process_private)
1262                         return;
1263                 mlx5_tx_uar_uninit_secondary(dev);
1264                 mlx5_proc_priv_uninit(dev);
1265                 rte_eth_dev_release_port(dev);
1266                 return;
1267         }
1268         if (!priv->sh)
1269                 return;
1270         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1271                 dev->data->port_id,
1272                 ((priv->sh->ctx != NULL) ?
1273                 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1274         /*
1275          * If default mreg copy action is removed at the stop stage,
1276          * the search will return none and nothing will be done anymore.
1277          */
1278         mlx5_flow_stop_default(dev);
1279         mlx5_traffic_disable(dev);
1280         /*
1281          * If all the flows are already flushed in the device stop stage,
1282          * then this will return directly without any action.
1283          */
1284         mlx5_flow_list_flush(dev, &priv->flows, true);
1285         mlx5_flow_meter_flush(dev, NULL);
1286         /* Free the intermediate buffers for flow creation. */
1287         mlx5_flow_free_intermediate(dev);
1288         /* Prevent crashes when queues are still in use. */
1289         dev->rx_pkt_burst = removed_rx_burst;
1290         dev->tx_pkt_burst = removed_tx_burst;
1291         rte_wmb();
1292         /* Disable datapath on secondary process. */
1293         mlx5_mp_req_stop_rxtx(dev);
1294         /* Free the eCPRI flex parser resource. */
1295         mlx5_flex_parser_ecpri_release(dev);
1296         if (priv->rxqs != NULL) {
1297                 /* XXX race condition if mlx5_rx_burst() is still running. */
1298                 usleep(1000);
1299                 for (i = 0; (i != priv->rxqs_n); ++i)
1300                         mlx5_rxq_release(dev, i);
1301                 priv->rxqs_n = 0;
1302                 priv->rxqs = NULL;
1303         }
1304         if (priv->txqs != NULL) {
1305                 /* XXX race condition if mlx5_tx_burst() is still running. */
1306                 usleep(1000);
1307                 for (i = 0; (i != priv->txqs_n); ++i)
1308                         mlx5_txq_release(dev, i);
1309                 priv->txqs_n = 0;
1310                 priv->txqs = NULL;
1311         }
1312         mlx5_proc_priv_uninit(dev);
1313         if (priv->mreg_cp_tbl)
1314                 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1315         mlx5_mprq_free_mp(dev);
1316         mlx5_os_free_shared_dr(priv);
1317         if (priv->rss_conf.rss_key != NULL)
1318                 rte_free(priv->rss_conf.rss_key);
1319         if (priv->reta_idx != NULL)
1320                 rte_free(priv->reta_idx);
1321         if (priv->config.vf)
1322                 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1323                                        dev->data->mac_addrs,
1324                                        MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1325         if (priv->nl_socket_route >= 0)
1326                 close(priv->nl_socket_route);
1327         if (priv->nl_socket_rdma >= 0)
1328                 close(priv->nl_socket_rdma);
1329         if (priv->vmwa_context)
1330                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1331         ret = mlx5_hrxq_verify(dev);
1332         if (ret)
1333                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1334                         dev->data->port_id);
1335         ret = mlx5_ind_table_obj_verify(dev);
1336         if (ret)
1337                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1338                         dev->data->port_id);
1339         ret = mlx5_rxq_obj_verify(dev);
1340         if (ret)
1341                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1342                         dev->data->port_id);
1343         ret = mlx5_rxq_verify(dev);
1344         if (ret)
1345                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1346                         dev->data->port_id);
1347         ret = mlx5_txq_obj_verify(dev);
1348         if (ret)
1349                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1350                         dev->data->port_id);
1351         ret = mlx5_txq_verify(dev);
1352         if (ret)
1353                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1354                         dev->data->port_id);
1355         ret = mlx5_flow_verify(dev);
1356         if (ret)
1357                 DRV_LOG(WARNING, "port %u some flows still remain",
1358                         dev->data->port_id);
1359         /*
1360          * Free the shared context in last turn, because the cleanup
1361          * routines above may use some shared fields, like
1362          * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1363          * ifindex if Netlink fails.
1364          */
1365         mlx5_free_shared_dev_ctx(priv->sh);
1366         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1367                 unsigned int c = 0;
1368                 uint16_t port_id;
1369
1370                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1371                         struct mlx5_priv *opriv =
1372                                 rte_eth_devices[port_id].data->dev_private;
1373
1374                         if (!opriv ||
1375                             opriv->domain_id != priv->domain_id ||
1376                             &rte_eth_devices[port_id] == dev)
1377                                 continue;
1378                         ++c;
1379                         break;
1380                 }
1381                 if (!c)
1382                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1383         }
1384         memset(priv, 0, sizeof(*priv));
1385         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1386         /*
1387          * Reset mac_addrs to NULL such that it is not freed as part of
1388          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1389          * it is freed when dev_private is freed.
1390          */
1391         dev->data->mac_addrs = NULL;
1392 }
1393
1394 /**
1395  * Verify and store value for device argument.
1396  *
1397  * @param[in] key
1398  *   Key argument to verify.
1399  * @param[in] val
1400  *   Value associated with key.
1401  * @param opaque
1402  *   User data.
1403  *
1404  * @return
1405  *   0 on success, a negative errno value otherwise and rte_errno is set.
1406  */
1407 static int
1408 mlx5_args_check(const char *key, const char *val, void *opaque)
1409 {
1410         struct mlx5_dev_config *config = opaque;
1411         unsigned long mod;
1412         signed long tmp;
1413
1414         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1415         if (!strcmp(MLX5_REPRESENTOR, key))
1416                 return 0;
1417         errno = 0;
1418         tmp = strtol(val, NULL, 0);
1419         if (errno) {
1420                 rte_errno = errno;
1421                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1422                 return -rte_errno;
1423         }
1424         if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1425                 /* Negative values are acceptable for some keys only. */
1426                 rte_errno = EINVAL;
1427                 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1428                 return -rte_errno;
1429         }
1430         mod = tmp >= 0 ? tmp : -tmp;
1431         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1432                 config->cqe_comp = !!tmp;
1433         } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1434                 config->cqe_pad = !!tmp;
1435         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1436                 config->hw_padding = !!tmp;
1437         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1438                 config->mprq.enabled = !!tmp;
1439         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1440                 config->mprq.stride_num_n = tmp;
1441         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1442                 config->mprq.stride_size_n = tmp;
1443         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1444                 config->mprq.max_memcpy_len = tmp;
1445         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1446                 config->mprq.min_rxqs_num = tmp;
1447         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1448                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1449                                  " converted to txq_inline_max", key);
1450                 config->txq_inline_max = tmp;
1451         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1452                 config->txq_inline_max = tmp;
1453         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1454                 config->txq_inline_min = tmp;
1455         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1456                 config->txq_inline_mpw = tmp;
1457         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1458                 config->txqs_inline = tmp;
1459         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1460                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1461         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1462                 config->mps = !!tmp;
1463         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1464                 if (tmp != MLX5_TXDB_CACHED &&
1465                     tmp != MLX5_TXDB_NCACHED &&
1466                     tmp != MLX5_TXDB_HEURISTIC) {
1467                         DRV_LOG(ERR, "invalid Tx doorbell "
1468                                      "mapping parameter");
1469                         rte_errno = EINVAL;
1470                         return -rte_errno;
1471                 }
1472                 config->dbnc = tmp;
1473         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1474                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1475         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1476                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1477                                  " converted to txq_inline_mpw", key);
1478                 config->txq_inline_mpw = tmp;
1479         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1480                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1481         } else if (strcmp(MLX5_TX_PP, key) == 0) {
1482                 if (!mod) {
1483                         DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1484                         rte_errno = EINVAL;
1485                         return -rte_errno;
1486                 }
1487                 config->tx_pp = tmp;
1488         } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1489                 config->tx_skew = tmp;
1490         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1491                 config->rx_vec_en = !!tmp;
1492         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1493                 config->l3_vxlan_en = !!tmp;
1494         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1495                 config->vf_nl_en = !!tmp;
1496         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1497                 config->dv_esw_en = !!tmp;
1498         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1499                 config->dv_flow_en = !!tmp;
1500         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1501                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1502                     tmp != MLX5_XMETA_MODE_META16 &&
1503                     tmp != MLX5_XMETA_MODE_META32) {
1504                         DRV_LOG(ERR, "invalid extensive "
1505                                      "metadata parameter");
1506                         rte_errno = EINVAL;
1507                         return -rte_errno;
1508                 }
1509                 config->dv_xmeta_en = tmp;
1510         } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1511                 config->lacp_by_user = !!tmp;
1512         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1513                 config->mr_ext_memseg_en = !!tmp;
1514         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1515                 config->max_dump_files_num = tmp;
1516         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1517                 config->lro.timeout = tmp;
1518         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1519                 DRV_LOG(DEBUG, "class argument is %s.", val);
1520         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1521                 config->log_hp_size = tmp;
1522         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1523                 if (tmp != MLX5_RCM_NONE &&
1524                     tmp != MLX5_RCM_LIGHT &&
1525                     tmp != MLX5_RCM_AGGR) {
1526                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1527                         rte_errno = EINVAL;
1528                         return -rte_errno;
1529                 }
1530                 config->reclaim_mode = tmp;
1531         } else {
1532                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1533                 rte_errno = EINVAL;
1534                 return -rte_errno;
1535         }
1536         return 0;
1537 }
1538
1539 /**
1540  * Parse device parameters.
1541  *
1542  * @param config
1543  *   Pointer to device configuration structure.
1544  * @param devargs
1545  *   Device arguments structure.
1546  *
1547  * @return
1548  *   0 on success, a negative errno value otherwise and rte_errno is set.
1549  */
1550 int
1551 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1552 {
1553         const char **params = (const char *[]){
1554                 MLX5_RXQ_CQE_COMP_EN,
1555                 MLX5_RXQ_CQE_PAD_EN,
1556                 MLX5_RXQ_PKT_PAD_EN,
1557                 MLX5_RX_MPRQ_EN,
1558                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1559                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1560                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1561                 MLX5_RXQS_MIN_MPRQ,
1562                 MLX5_TXQ_INLINE,
1563                 MLX5_TXQ_INLINE_MIN,
1564                 MLX5_TXQ_INLINE_MAX,
1565                 MLX5_TXQ_INLINE_MPW,
1566                 MLX5_TXQS_MIN_INLINE,
1567                 MLX5_TXQS_MAX_VEC,
1568                 MLX5_TXQ_MPW_EN,
1569                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1570                 MLX5_TXQ_MAX_INLINE_LEN,
1571                 MLX5_TX_DB_NC,
1572                 MLX5_TX_PP,
1573                 MLX5_TX_SKEW,
1574                 MLX5_TX_VEC_EN,
1575                 MLX5_RX_VEC_EN,
1576                 MLX5_L3_VXLAN_EN,
1577                 MLX5_VF_NL_EN,
1578                 MLX5_DV_ESW_EN,
1579                 MLX5_DV_FLOW_EN,
1580                 MLX5_DV_XMETA_EN,
1581                 MLX5_LACP_BY_USER,
1582                 MLX5_MR_EXT_MEMSEG_EN,
1583                 MLX5_REPRESENTOR,
1584                 MLX5_MAX_DUMP_FILES_NUM,
1585                 MLX5_LRO_TIMEOUT_USEC,
1586                 MLX5_CLASS_ARG_NAME,
1587                 MLX5_HP_BUF_SIZE,
1588                 MLX5_RECLAIM_MEM,
1589                 NULL,
1590         };
1591         struct rte_kvargs *kvlist;
1592         int ret = 0;
1593         int i;
1594
1595         if (devargs == NULL)
1596                 return 0;
1597         /* Following UGLY cast is done to pass checkpatch. */
1598         kvlist = rte_kvargs_parse(devargs->args, params);
1599         if (kvlist == NULL) {
1600                 rte_errno = EINVAL;
1601                 return -rte_errno;
1602         }
1603         /* Process parameters. */
1604         for (i = 0; (params[i] != NULL); ++i) {
1605                 if (rte_kvargs_count(kvlist, params[i])) {
1606                         ret = rte_kvargs_process(kvlist, params[i],
1607                                                  mlx5_args_check, config);
1608                         if (ret) {
1609                                 rte_errno = EINVAL;
1610                                 rte_kvargs_free(kvlist);
1611                                 return -rte_errno;
1612                         }
1613                 }
1614         }
1615         rte_kvargs_free(kvlist);
1616         return 0;
1617 }
1618
1619 /**
1620  * PMD global initialization.
1621  *
1622  * Independent from individual device, this function initializes global
1623  * per-PMD data structures distinguishing primary and secondary processes.
1624  * Hence, each initialization is called once per a process.
1625  *
1626  * @return
1627  *   0 on success, a negative errno value otherwise and rte_errno is set.
1628  */
1629 int
1630 mlx5_init_once(void)
1631 {
1632         struct mlx5_shared_data *sd;
1633         struct mlx5_local_data *ld = &mlx5_local_data;
1634         int ret = 0;
1635
1636         if (mlx5_init_shared_data())
1637                 return -rte_errno;
1638         sd = mlx5_shared_data;
1639         MLX5_ASSERT(sd);
1640         rte_spinlock_lock(&sd->lock);
1641         switch (rte_eal_process_type()) {
1642         case RTE_PROC_PRIMARY:
1643                 if (sd->init_done)
1644                         break;
1645                 LIST_INIT(&sd->mem_event_cb_list);
1646                 rte_rwlock_init(&sd->mem_event_rwlock);
1647                 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1648                                                 mlx5_mr_mem_event_cb, NULL);
1649                 ret = mlx5_mp_init_primary(MLX5_MP_NAME,
1650                                            mlx5_mp_primary_handle);
1651                 if (ret)
1652                         goto out;
1653                 sd->init_done = true;
1654                 break;
1655         case RTE_PROC_SECONDARY:
1656                 if (ld->init_done)
1657                         break;
1658                 ret = mlx5_mp_init_secondary(MLX5_MP_NAME,
1659                                              mlx5_mp_secondary_handle);
1660                 if (ret)
1661                         goto out;
1662                 ++sd->secondary_cnt;
1663                 ld->init_done = true;
1664                 break;
1665         default:
1666                 break;
1667         }
1668 out:
1669         rte_spinlock_unlock(&sd->lock);
1670         return ret;
1671 }
1672
1673 /**
1674  * Configures the minimal amount of data to inline into WQE
1675  * while sending packets.
1676  *
1677  * - the txq_inline_min has the maximal priority, if this
1678  *   key is specified in devargs
1679  * - if DevX is enabled the inline mode is queried from the
1680  *   device (HCA attributes and NIC vport context if needed).
1681  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1682  *   and none (0 bytes) for other NICs
1683  *
1684  * @param spawn
1685  *   Verbs device parameters (name, port, switch_info) to spawn.
1686  * @param config
1687  *   Device configuration parameters.
1688  */
1689 void
1690 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1691                     struct mlx5_dev_config *config)
1692 {
1693         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1694                 /* Application defines size of inlined data explicitly. */
1695                 switch (spawn->pci_dev->id.device_id) {
1696                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1697                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1698                         if (config->txq_inline_min <
1699                                        (int)MLX5_INLINE_HSIZE_L2) {
1700                                 DRV_LOG(DEBUG,
1701                                         "txq_inline_mix aligned to minimal"
1702                                         " ConnectX-4 required value %d",
1703                                         (int)MLX5_INLINE_HSIZE_L2);
1704                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1705                         }
1706                         break;
1707                 }
1708                 goto exit;
1709         }
1710         if (config->hca_attr.eth_net_offloads) {
1711                 /* We have DevX enabled, inline mode queried successfully. */
1712                 switch (config->hca_attr.wqe_inline_mode) {
1713                 case MLX5_CAP_INLINE_MODE_L2:
1714                         /* outer L2 header must be inlined. */
1715                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1716                         goto exit;
1717                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1718                         /* No inline data are required by NIC. */
1719                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1720                         config->hw_vlan_insert =
1721                                 config->hca_attr.wqe_vlan_insert;
1722                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1723                         goto exit;
1724                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1725                         /* inline mode is defined by NIC vport context. */
1726                         if (!config->hca_attr.eth_virt)
1727                                 break;
1728                         switch (config->hca_attr.vport_inline_mode) {
1729                         case MLX5_INLINE_MODE_NONE:
1730                                 config->txq_inline_min =
1731                                         MLX5_INLINE_HSIZE_NONE;
1732                                 goto exit;
1733                         case MLX5_INLINE_MODE_L2:
1734                                 config->txq_inline_min =
1735                                         MLX5_INLINE_HSIZE_L2;
1736                                 goto exit;
1737                         case MLX5_INLINE_MODE_IP:
1738                                 config->txq_inline_min =
1739                                         MLX5_INLINE_HSIZE_L3;
1740                                 goto exit;
1741                         case MLX5_INLINE_MODE_TCP_UDP:
1742                                 config->txq_inline_min =
1743                                         MLX5_INLINE_HSIZE_L4;
1744                                 goto exit;
1745                         case MLX5_INLINE_MODE_INNER_L2:
1746                                 config->txq_inline_min =
1747                                         MLX5_INLINE_HSIZE_INNER_L2;
1748                                 goto exit;
1749                         case MLX5_INLINE_MODE_INNER_IP:
1750                                 config->txq_inline_min =
1751                                         MLX5_INLINE_HSIZE_INNER_L3;
1752                                 goto exit;
1753                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
1754                                 config->txq_inline_min =
1755                                         MLX5_INLINE_HSIZE_INNER_L4;
1756                                 goto exit;
1757                         }
1758                 }
1759         }
1760         /*
1761          * We get here if we are unable to deduce
1762          * inline data size with DevX. Try PCI ID
1763          * to determine old NICs.
1764          */
1765         switch (spawn->pci_dev->id.device_id) {
1766         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1767         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1768         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1769         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1770                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1771                 config->hw_vlan_insert = 0;
1772                 break;
1773         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1774         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1775         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1776         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1777                 /*
1778                  * These NICs support VLAN insertion from WQE and
1779                  * report the wqe_vlan_insert flag. But there is the bug
1780                  * and PFC control may be broken, so disable feature.
1781                  */
1782                 config->hw_vlan_insert = 0;
1783                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1784                 break;
1785         default:
1786                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1787                 break;
1788         }
1789 exit:
1790         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1791 }
1792
1793 /**
1794  * Configures the metadata mask fields in the shared context.
1795  *
1796  * @param [in] dev
1797  *   Pointer to Ethernet device.
1798  */
1799 void
1800 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1801 {
1802         struct mlx5_priv *priv = dev->data->dev_private;
1803         struct mlx5_dev_ctx_shared *sh = priv->sh;
1804         uint32_t meta, mark, reg_c0;
1805
1806         reg_c0 = ~priv->vport_meta_mask;
1807         switch (priv->config.dv_xmeta_en) {
1808         case MLX5_XMETA_MODE_LEGACY:
1809                 meta = UINT32_MAX;
1810                 mark = MLX5_FLOW_MARK_MASK;
1811                 break;
1812         case MLX5_XMETA_MODE_META16:
1813                 meta = reg_c0 >> rte_bsf32(reg_c0);
1814                 mark = MLX5_FLOW_MARK_MASK;
1815                 break;
1816         case MLX5_XMETA_MODE_META32:
1817                 meta = UINT32_MAX;
1818                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1819                 break;
1820         default:
1821                 meta = 0;
1822                 mark = 0;
1823                 MLX5_ASSERT(false);
1824                 break;
1825         }
1826         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1827                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1828                                  sh->dv_mark_mask, mark);
1829         else
1830                 sh->dv_mark_mask = mark;
1831         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1832                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1833                                  sh->dv_meta_mask, meta);
1834         else
1835                 sh->dv_meta_mask = meta;
1836         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1837                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1838                                  sh->dv_meta_mask, reg_c0);
1839         else
1840                 sh->dv_regc0_mask = reg_c0;
1841         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1842         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1843         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1844         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1845 }
1846
1847 int
1848 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1849 {
1850         static const char *const dynf_names[] = {
1851                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1852                 RTE_MBUF_DYNFLAG_METADATA_NAME,
1853                 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
1854         };
1855         unsigned int i;
1856
1857         if (n < RTE_DIM(dynf_names))
1858                 return -ENOMEM;
1859         for (i = 0; i < RTE_DIM(dynf_names); i++) {
1860                 if (names[i] == NULL)
1861                         return -EINVAL;
1862                 strcpy(names[i], dynf_names[i]);
1863         }
1864         return RTE_DIM(dynf_names);
1865 }
1866
1867 /**
1868  * Comparison callback to sort device data.
1869  *
1870  * This is meant to be used with qsort().
1871  *
1872  * @param a[in]
1873  *   Pointer to pointer to first data object.
1874  * @param b[in]
1875  *   Pointer to pointer to second data object.
1876  *
1877  * @return
1878  *   0 if both objects are equal, less than 0 if the first argument is less
1879  *   than the second, greater than 0 otherwise.
1880  */
1881 int
1882 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1883                               struct mlx5_dev_config *config)
1884 {
1885         struct mlx5_dev_ctx_shared *sh = priv->sh;
1886         struct mlx5_dev_config *sh_conf = NULL;
1887         uint16_t port_id;
1888
1889         MLX5_ASSERT(sh);
1890         /* Nothing to compare for the single/first device. */
1891         if (sh->refcnt == 1)
1892                 return 0;
1893         /* Find the device with shared context. */
1894         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1895                 struct mlx5_priv *opriv =
1896                         rte_eth_devices[port_id].data->dev_private;
1897
1898                 if (opriv && opriv != priv && opriv->sh == sh) {
1899                         sh_conf = &opriv->config;
1900                         break;
1901                 }
1902         }
1903         if (!sh_conf)
1904                 return 0;
1905         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1906                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1907                              " for shared %s context", sh->ibdev_name);
1908                 rte_errno = EINVAL;
1909                 return rte_errno;
1910         }
1911         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1912                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1913                              " for shared %s context", sh->ibdev_name);
1914                 rte_errno = EINVAL;
1915                 return rte_errno;
1916         }
1917         return 0;
1918 }
1919
1920 /**
1921  * Look for the ethernet device belonging to mlx5 driver.
1922  *
1923  * @param[in] port_id
1924  *   port_id to start looking for device.
1925  * @param[in] pci_dev
1926  *   Pointer to the hint PCI device. When device is being probed
1927  *   the its siblings (master and preceding representors might
1928  *   not have assigned driver yet (because the mlx5_os_pci_probe()
1929  *   is not completed yet, for this case match on hint PCI
1930  *   device may be used to detect sibling device.
1931  *
1932  * @return
1933  *   port_id of found device, RTE_MAX_ETHPORT if not found.
1934  */
1935 uint16_t
1936 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
1937 {
1938         while (port_id < RTE_MAX_ETHPORTS) {
1939                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
1940
1941                 if (dev->state != RTE_ETH_DEV_UNUSED &&
1942                     dev->device &&
1943                     (dev->device == &pci_dev->device ||
1944                      (dev->device->driver &&
1945                      dev->device->driver->name &&
1946                      !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
1947                         break;
1948                 port_id++;
1949         }
1950         if (port_id >= RTE_MAX_ETHPORTS)
1951                 return RTE_MAX_ETHPORTS;
1952         return port_id;
1953 }
1954
1955 /**
1956  * DPDK callback to remove a PCI device.
1957  *
1958  * This function removes all Ethernet devices belong to a given PCI device.
1959  *
1960  * @param[in] pci_dev
1961  *   Pointer to the PCI device.
1962  *
1963  * @return
1964  *   0 on success, the function cannot fail.
1965  */
1966 static int
1967 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1968 {
1969         uint16_t port_id;
1970
1971         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
1972                 /*
1973                  * mlx5_dev_close() is not registered to secondary process,
1974                  * call the close function explicitly for secondary process.
1975                  */
1976                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
1977                         mlx5_dev_close(&rte_eth_devices[port_id]);
1978                 else
1979                         rte_eth_dev_close(port_id);
1980         }
1981         return 0;
1982 }
1983
1984 static const struct rte_pci_id mlx5_pci_id_map[] = {
1985         {
1986                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1987                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1988         },
1989         {
1990                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1991                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1992         },
1993         {
1994                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1995                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1996         },
1997         {
1998                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1999                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2000         },
2001         {
2002                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2003                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2004         },
2005         {
2006                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2007                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2008         },
2009         {
2010                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2011                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2012         },
2013         {
2014                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2015                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2016         },
2017         {
2018                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2019                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2020         },
2021         {
2022                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2023                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2024         },
2025         {
2026                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2027                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2028         },
2029         {
2030                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2031                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2032         },
2033         {
2034                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2035                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2036         },
2037         {
2038                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2039                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
2040         },
2041         {
2042                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2043                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2044         },
2045         {
2046                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2047                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2048         },
2049         {
2050                 .vendor_id = 0
2051         }
2052 };
2053
2054 struct rte_pci_driver mlx5_driver = {
2055         .driver = {
2056                 .name = MLX5_DRIVER_NAME
2057         },
2058         .id_table = mlx5_pci_id_map,
2059         .probe = mlx5_os_pci_probe,
2060         .remove = mlx5_pci_remove,
2061         .dma_map = mlx5_dma_map,
2062         .dma_unmap = mlx5_dma_unmap,
2063         .drv_flags = PCI_DRV_FLAGS,
2064 };
2065
2066 /* Initialize driver log type. */
2067 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
2068
2069 /**
2070  * Driver initialization routine.
2071  */
2072 RTE_INIT(rte_mlx5_pmd_init)
2073 {
2074         /* Build the static tables for Verbs conversion. */
2075         mlx5_set_ptype_table();
2076         mlx5_set_cksum_table();
2077         mlx5_set_swp_types_table();
2078         if (mlx5_glue)
2079                 rte_pci_register(&mlx5_driver);
2080 }
2081
2082 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2083 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2084 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");