drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12
  13 #include <rte_malloc.h>
  14 #include <rte_ethdev_driver.h>
  15 #include <rte_ethdev_pci.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_common.h>
  19 #include <rte_kvargs.h>
  20 #include <rte_rwlock.h>
  21 #include <rte_spinlock.h>
  22 #include <rte_string_fns.h>
  23 #include <rte_alarm.h>
  24 #include <rte_cycles.h>
  25
  26 #include <mlx5_glue.h>
  27 #include <mlx5_devx_cmds.h>
  28 #include <mlx5_common.h>
  29 #include <mlx5_common_os.h>
  30 #include <mlx5_common_mp.h>
  31 #include <mlx5_common_pci.h>
  32 #include <mlx5_malloc.h>
  33
  34 #include "mlx5_defs.h"
  35 #include "mlx5.h"
  36 #include "mlx5_utils.h"
  37 #include "mlx5_rxtx.h"
  38 #include "mlx5_autoconf.h"
  39 #include "mlx5_mr.h"
  40 #include "mlx5_flow.h"
  41 #include "mlx5_flow_os.h"
  42 #include "rte_pmd_mlx5.h"
  43
  44 /* Device parameter to enable RX completion queue compression. */
  45 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  46
  47 /* Device parameter to enable RX completion entry padding to 128B. */
  48 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
  49
  50 /* Device parameter to enable padding Rx packet to cacheline size. */
  51 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  52
  53 /* Device parameter to enable Multi-Packet Rx queue. */
  54 #define MLX5_RX_MPRQ_EN "mprq_en"
  55
  56 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  57 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  58
  59 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  60 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  61
  62 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  63 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  64
  65 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  66 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  67
  68 /* Device parameter to configure inline send. Deprecated, ignored.*/
  69 #define MLX5_TXQ_INLINE "txq_inline"
  70
  71 /* Device parameter to limit packet size to inline with ordinary SEND. */
  72 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  73
  74 /* Device parameter to configure minimal data size to inline. */
  75 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  76
  77 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  78 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  79
  80 /*
  81  * Device parameter to configure the number of TX queues threshold for
  82  * enabling inline send.
  83  */
  84 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  85
  86 /*
  87  * Device parameter to configure the number of TX queues threshold for
  88  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  89  */
  90 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  91
  92 /* Device parameter to enable multi-packet send WQEs. */
  93 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  94
  95 /*
  96  * Device parameter to force doorbell register mapping
  97  * to non-cahed region eliminating the extra write memory barrier.
  98  */
  99 #define MLX5_TX_DB_NC "tx_db_nc"
 100
 101 /*
 102  * Device parameter to include 2 dsegs in the title WQEBB.
 103  * Deprecated, ignored.
 104  */
 105 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 106
 107 /*
 108  * Device parameter to limit the size of inlining packet.
 109  * Deprecated, ignored.
 110  */
 111 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 112
 113 /*
 114  * Device parameter to enable Tx scheduling on timestamps
 115  * and specify the packet pacing granularity in nanoseconds.
 116  */
 117 #define MLX5_TX_PP "tx_pp"
 118
 119 /*
 120  * Device parameter to specify skew in nanoseconds on Tx datapath,
 121  * it represents the time between SQ start WQE processing and
 122  * appearing actual packet data on the wire.
 123  */
 124 #define MLX5_TX_SKEW "tx_skew"
 125
 126 /*
 127  * Device parameter to enable hardware Tx vector.
 128  * Deprecated, ignored (no vectorized Tx routines anymore).
 129  */
 130 #define MLX5_TX_VEC_EN "tx_vec_en"
 131
 132 /* Device parameter to enable hardware Rx vector. */
 133 #define MLX5_RX_VEC_EN "rx_vec_en"
 134
 135 /* Allow L3 VXLAN flow creation. */
 136 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 137
 138 /* Activate DV E-Switch flow steering. */
 139 #define MLX5_DV_ESW_EN "dv_esw_en"
 140
 141 /* Activate DV flow steering. */
 142 #define MLX5_DV_FLOW_EN "dv_flow_en"
 143
 144 /* Enable extensive flow metadata support. */
 145 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 146
 147 /* Device parameter to let the user manage the lacp traffic of bonded device */
 148 #define MLX5_LACP_BY_USER "lacp_by_user"
 149
 150 /* Activate Netlink support in VF mode. */
 151 #define MLX5_VF_NL_EN "vf_nl_en"
 152
 153 /* Enable extending memsegs when creating a MR. */
 154 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 155
 156 /* Select port representors to instantiate. */
 157 #define MLX5_REPRESENTOR "representor"
 158
 159 /* Device parameter to configure the maximum number of dump files per queue. */
 160 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 161
 162 /* Configure timeout of LRO session (in microseconds). */
 163 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 164
 165 /*
 166  * Device parameter to configure the total data buffer size for a single
 167  * hairpin queue (logarithm value).
 168  */
 169 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 170
 171 /* Flow memory reclaim mode. */
 172 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 173
 174 /* The default memory allocator used in PMD. */
 175 #define MLX5_SYS_MEM_EN "sys_mem_en"
 176 /* Decap will be used or not. */
 177 #define MLX5_DECAP_EN "decap_en"
 178
 179 /* Shared memory between primary and secondary processes. */
 180 struct mlx5_shared_data *mlx5_shared_data;
 181
 182 /** Driver-specific log messages type. */
 183 int mlx5_logtype;
 184
 185 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 186                                                 LIST_HEAD_INITIALIZER();
 187 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
 188
 189 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 190 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
 191         [MLX5_IPOOL_DECAP_ENCAP] = {
 192                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 193                 .trunk_size = 64,
 194                 .grow_trunk = 3,
 195                 .grow_shift = 2,
 196                 .need_lock = 1,
 197                 .release_mem_en = 1,
 198                 .malloc = mlx5_malloc,
 199                 .free = mlx5_free,
 200                 .type = "mlx5_encap_decap_ipool",
 201         },
 202         [MLX5_IPOOL_PUSH_VLAN] = {
 203                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 204                 .trunk_size = 64,
 205                 .grow_trunk = 3,
 206                 .grow_shift = 2,
 207                 .need_lock = 1,
 208                 .release_mem_en = 1,
 209                 .malloc = mlx5_malloc,
 210                 .free = mlx5_free,
 211                 .type = "mlx5_push_vlan_ipool",
 212         },
 213         [MLX5_IPOOL_TAG] = {
 214                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 215                 .trunk_size = 64,
 216                 .grow_trunk = 3,
 217                 .grow_shift = 2,
 218                 .need_lock = 1,
 219                 .release_mem_en = 1,
 220                 .malloc = mlx5_malloc,
 221                 .free = mlx5_free,
 222                 .type = "mlx5_tag_ipool",
 223         },
 224         [MLX5_IPOOL_PORT_ID] = {
 225                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 226                 .trunk_size = 64,
 227                 .grow_trunk = 3,
 228                 .grow_shift = 2,
 229                 .need_lock = 1,
 230                 .release_mem_en = 1,
 231                 .malloc = mlx5_malloc,
 232                 .free = mlx5_free,
 233                 .type = "mlx5_port_id_ipool",
 234         },
 235         [MLX5_IPOOL_JUMP] = {
 236                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 237                 .trunk_size = 64,
 238                 .grow_trunk = 3,
 239                 .grow_shift = 2,
 240                 .need_lock = 1,
 241                 .release_mem_en = 1,
 242                 .malloc = mlx5_malloc,
 243                 .free = mlx5_free,
 244                 .type = "mlx5_jump_ipool",
 245         },
 246         [MLX5_IPOOL_SAMPLE] = {
 247                 .size = sizeof(struct mlx5_flow_dv_sample_resource),
 248                 .trunk_size = 64,
 249                 .grow_trunk = 3,
 250                 .grow_shift = 2,
 251                 .need_lock = 1,
 252                 .release_mem_en = 1,
 253                 .malloc = mlx5_malloc,
 254                 .free = mlx5_free,
 255                 .type = "mlx5_sample_ipool",
 256         },
 257         [MLX5_IPOOL_DEST_ARRAY] = {
 258                 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
 259                 .trunk_size = 64,
 260                 .grow_trunk = 3,
 261                 .grow_shift = 2,
 262                 .need_lock = 1,
 263                 .release_mem_en = 1,
 264                 .malloc = mlx5_malloc,
 265                 .free = mlx5_free,
 266                 .type = "mlx5_dest_array_ipool",
 267         },
 268         [MLX5_IPOOL_TUNNEL_ID] = {
 269                 .size = sizeof(struct mlx5_flow_tunnel),
 270                 .trunk_size = MLX5_MAX_TUNNELS,
 271                 .need_lock = 1,
 272                 .release_mem_en = 1,
 273                 .type = "mlx5_tunnel_offload",
 274         },
 275         [MLX5_IPOOL_TNL_TBL_ID] = {
 276                 .size = 0,
 277                 .need_lock = 1,
 278                 .type = "mlx5_flow_tnl_tbl_ipool",
 279         },
 280 #endif
 281         [MLX5_IPOOL_MTR] = {
 282                 .size = sizeof(struct mlx5_flow_meter),
 283                 .trunk_size = 64,
 284                 .grow_trunk = 3,
 285                 .grow_shift = 2,
 286                 .need_lock = 1,
 287                 .release_mem_en = 1,
 288                 .malloc = mlx5_malloc,
 289                 .free = mlx5_free,
 290                 .type = "mlx5_meter_ipool",
 291         },
 292         [MLX5_IPOOL_MCP] = {
 293                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 294                 .trunk_size = 64,
 295                 .grow_trunk = 3,
 296                 .grow_shift = 2,
 297                 .need_lock = 1,
 298                 .release_mem_en = 1,
 299                 .malloc = mlx5_malloc,
 300                 .free = mlx5_free,
 301                 .type = "mlx5_mcp_ipool",
 302         },
 303         [MLX5_IPOOL_HRXQ] = {
 304                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 305                 .trunk_size = 64,
 306                 .grow_trunk = 3,
 307                 .grow_shift = 2,
 308                 .need_lock = 1,
 309                 .release_mem_en = 1,
 310                 .malloc = mlx5_malloc,
 311                 .free = mlx5_free,
 312                 .type = "mlx5_hrxq_ipool",
 313         },
 314         [MLX5_IPOOL_MLX5_FLOW] = {
 315                 /*
 316                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 317                  * It set in run time according to PCI function configuration.
 318                  */
 319                 .size = 0,
 320                 .trunk_size = 64,
 321                 .grow_trunk = 3,
 322                 .grow_shift = 2,
 323                 .need_lock = 1,
 324                 .release_mem_en = 1,
 325                 .malloc = mlx5_malloc,
 326                 .free = mlx5_free,
 327                 .type = "mlx5_flow_handle_ipool",
 328         },
 329         [MLX5_IPOOL_RTE_FLOW] = {
 330                 .size = sizeof(struct rte_flow),
 331                 .trunk_size = 4096,
 332                 .need_lock = 1,
 333                 .release_mem_en = 1,
 334                 .malloc = mlx5_malloc,
 335                 .free = mlx5_free,
 336                 .type = "rte_flow_ipool",
 337         },
 338         [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
 339                 .size = 0,
 340                 .need_lock = 1,
 341                 .type = "mlx5_flow_rss_id_ipool",
 342         },
 343         [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
 344                 .size = sizeof(struct mlx5_shared_action_rss),
 345                 .trunk_size = 64,
 346                 .grow_trunk = 3,
 347                 .grow_shift = 2,
 348                 .need_lock = 1,
 349                 .release_mem_en = 1,
 350                 .malloc = mlx5_malloc,
 351                 .free = mlx5_free,
 352                 .type = "mlx5_shared_action_rss",
 353         },
 354 };
 355
 356
 357 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 358 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 359
 360 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 361
 362 /**
 363  * Initialize the ASO aging management structure.
 364  *
 365  * @param[in] sh
 366  *   Pointer to mlx5_dev_ctx_shared object to free
 367  *
 368  * @return
 369  *   0 on success, a negative errno value otherwise and rte_errno is set.
 370  */
 371 int
 372 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
 373 {
 374         int err;
 375
 376         if (sh->aso_age_mng)
 377                 return 0;
 378         sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
 379                                       RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 380         if (!sh->aso_age_mng) {
 381                 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
 382                 rte_errno = ENOMEM;
 383                 return -ENOMEM;
 384         }
 385         err = mlx5_aso_queue_init(sh);
 386         if (err) {
 387                 mlx5_free(sh->aso_age_mng);
 388                 return -1;
 389         }
 390         rte_spinlock_init(&sh->aso_age_mng->resize_sl);
 391         rte_spinlock_init(&sh->aso_age_mng->free_sl);
 392         LIST_INIT(&sh->aso_age_mng->free);
 393         return 0;
 394 }
 395
 396 /**
 397  * Close and release all the resources of the ASO aging management structure.
 398  *
 399  * @param[in] sh
 400  *   Pointer to mlx5_dev_ctx_shared object to free.
 401  */
 402 static void
 403 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
 404 {
 405         int i, j;
 406
 407         mlx5_aso_queue_stop(sh);
 408         mlx5_aso_queue_uninit(sh);
 409         if (sh->aso_age_mng->pools) {
 410                 struct mlx5_aso_age_pool *pool;
 411
 412                 for (i = 0; i < sh->aso_age_mng->next; ++i) {
 413                         pool = sh->aso_age_mng->pools[i];
 414                         claim_zero(mlx5_devx_cmd_destroy
 415                                                 (pool->flow_hit_aso_obj));
 416                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
 417                                 if (pool->actions[j].dr_action)
 418                                         claim_zero
 419                                             (mlx5_flow_os_destroy_flow_action
 420                                               (pool->actions[j].dr_action));
 421                         mlx5_free(pool);
 422                 }
 423                 mlx5_free(sh->aso_age_mng->pools);
 424         }
 425         mlx5_free(sh->aso_age_mng);
 426 }
 427
 428 /**
 429  * Initialize the shared aging list information per port.
 430  *
 431  * @param[in] sh
 432  *   Pointer to mlx5_dev_ctx_shared object.
 433  */
 434 static void
 435 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 436 {
 437         uint32_t i;
 438         struct mlx5_age_info *age_info;
 439
 440         for (i = 0; i < sh->max_port; i++) {
 441                 age_info = &sh->port[i].age_info;
 442                 age_info->flags = 0;
 443                 TAILQ_INIT(&age_info->aged_counters);
 444                 LIST_INIT(&age_info->aged_aso);
 445                 rte_spinlock_init(&age_info->aged_sl);
 446                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 447         }
 448 }
 449
 450 /**
 451  * Initialize the counters management structure.
 452  *
 453  * @param[in] sh
 454  *   Pointer to mlx5_dev_ctx_shared object to free
 455  */
 456 static void
 457 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 458 {
 459         int i;
 460
 461         memset(&sh->cmng, 0, sizeof(sh->cmng));
 462         TAILQ_INIT(&sh->cmng.flow_counters);
 463         sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
 464         sh->cmng.max_id = -1;
 465         sh->cmng.last_pool_idx = POOL_IDX_INVALID;
 466         rte_spinlock_init(&sh->cmng.pool_update_sl);
 467         for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
 468                 TAILQ_INIT(&sh->cmng.counters[i]);
 469                 rte_spinlock_init(&sh->cmng.csl[i]);
 470         }
 471 }
 472
 473 /**
 474  * Destroy all the resources allocated for a counter memory management.
 475  *
 476  * @param[in] mng
 477  *   Pointer to the memory management structure.
 478  */
 479 static void
 480 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 481 {
 482         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 483
 484         LIST_REMOVE(mng, next);
 485         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 486         claim_zero(mlx5_os_umem_dereg(mng->umem));
 487         mlx5_free(mem);
 488 }
 489
 490 /**
 491  * Close and release all the resources of the counters management.
 492  *
 493  * @param[in] sh
 494  *   Pointer to mlx5_dev_ctx_shared object to free.
 495  */
 496 static void
 497 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 498 {
 499         struct mlx5_counter_stats_mem_mng *mng;
 500         int i, j;
 501         int retries = 1024;
 502
 503         rte_errno = 0;
 504         while (--retries) {
 505                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 506                 if (rte_errno != EINPROGRESS)
 507                         break;
 508                 rte_pause();
 509         }
 510
 511         if (sh->cmng.pools) {
 512                 struct mlx5_flow_counter_pool *pool;
 513                 uint16_t n_valid = sh->cmng.n_valid;
 514                 bool fallback = sh->cmng.counter_fallback;
 515
 516                 for (i = 0; i < n_valid; ++i) {
 517                         pool = sh->cmng.pools[i];
 518                         if (!fallback && pool->min_dcs)
 519                                 claim_zero(mlx5_devx_cmd_destroy
 520                                                                (pool->min_dcs));
 521                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 522                                 struct mlx5_flow_counter *cnt =
 523                                                 MLX5_POOL_GET_CNT(pool, j);
 524
 525                                 if (cnt->action)
 526                                         claim_zero
 527                                          (mlx5_flow_os_destroy_flow_action
 528                                           (cnt->action));
 529                                 if (fallback && MLX5_POOL_GET_CNT
 530                                     (pool, j)->dcs_when_free)
 531                                         claim_zero(mlx5_devx_cmd_destroy
 532                                                    (cnt->dcs_when_free));
 533                         }
 534                         mlx5_free(pool);
 535                 }
 536                 mlx5_free(sh->cmng.pools);
 537         }
 538         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 539         while (mng) {
 540                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 541                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 542         }
 543         memset(&sh->cmng, 0, sizeof(sh->cmng));
 544 }
 545
 546 /* Send FLOW_AGED event if needed. */
 547 void
 548 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
 549 {
 550         struct mlx5_age_info *age_info;
 551         uint32_t i;
 552
 553         for (i = 0; i < sh->max_port; i++) {
 554                 age_info = &sh->port[i].age_info;
 555                 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
 556                         continue;
 557                 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER))
 558                         rte_eth_dev_callback_process
 559                                 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
 560                                 RTE_ETH_EVENT_FLOW_AGED, NULL);
 561                 age_info->flags = 0;
 562         }
 563 }
 564
 565 /**
 566  * Initialize the flow resources' indexed mempool.
 567  *
 568  * @param[in] sh
 569  *   Pointer to mlx5_dev_ctx_shared object.
 570  * @param[in] sh
 571  *   Pointer to user dev config.
 572  */
 573 static void
 574 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 575                        const struct mlx5_dev_config *config)
 576 {
 577         uint8_t i;
 578         struct mlx5_indexed_pool_config cfg;
 579
 580         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 581                 cfg = mlx5_ipool_cfg[i];
 582                 switch (i) {
 583                 default:
 584                         break;
 585                 /*
 586                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 587                  * according to PCI function flow configuration.
 588                  */
 589                 case MLX5_IPOOL_MLX5_FLOW:
 590                         cfg.size = config->dv_flow_en ?
 591                                 sizeof(struct mlx5_flow_handle) :
 592                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 593                         break;
 594                 }
 595                 if (config->reclaim_mode)
 596                         cfg.release_mem_en = 1;
 597                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 598         }
 599 }
 600
 601 /**
 602  * Release the flow resources' indexed mempool.
 603  *
 604  * @param[in] sh
 605  *   Pointer to mlx5_dev_ctx_shared object.
 606  */
 607 static void
 608 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 609 {
 610         uint8_t i;
 611
 612         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 613                 mlx5_ipool_destroy(sh->ipool[i]);
 614 }
 615
 616 /*
 617  * Check if dynamic flex parser for eCPRI already exists.
 618  *
 619  * @param dev
 620  *   Pointer to Ethernet device structure.
 621  *
 622  * @return
 623  *   true on exists, false on not.
 624  */
 625 bool
 626 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
 627 {
 628         struct mlx5_priv *priv = dev->data->dev_private;
 629         struct mlx5_flex_parser_profiles *prf =
 630                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 631
 632         return !!prf->obj;
 633 }
 634
 635 /*
 636  * Allocation of a flex parser for eCPRI. Once created, this parser related
 637  * resources will be held until the device is closed.
 638  *
 639  * @param dev
 640  *   Pointer to Ethernet device structure.
 641  *
 642  * @return
 643  *   0 on success, a negative errno value otherwise and rte_errno is set.
 644  */
 645 int
 646 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
 647 {
 648         struct mlx5_priv *priv = dev->data->dev_private;
 649         struct mlx5_flex_parser_profiles *prf =
 650                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 651         struct mlx5_devx_graph_node_attr node = {
 652                 .modify_field_select = 0,
 653         };
 654         uint32_t ids[8];
 655         int ret;
 656
 657         if (!priv->config.hca_attr.parse_graph_flex_node) {
 658                 DRV_LOG(ERR, "Dynamic flex parser is not supported "
 659                         "for device %s.", priv->dev_data->name);
 660                 return -ENOTSUP;
 661         }
 662         node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
 663         /* 8 bytes now: 4B common header + 4B message body header. */
 664         node.header_length_base_value = 0x8;
 665         /* After MAC layer: Ether / VLAN. */
 666         node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
 667         /* Type of compared condition should be 0xAEFE in the L2 layer. */
 668         node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
 669         /* Sample #0: type in common header. */
 670         node.sample[0].flow_match_sample_en = 1;
 671         /* Fixed offset. */
 672         node.sample[0].flow_match_sample_offset_mode = 0x0;
 673         /* Only the 2nd byte will be used. */
 674         node.sample[0].flow_match_sample_field_base_offset = 0x0;
 675         /* Sample #1: message payload. */
 676         node.sample[1].flow_match_sample_en = 1;
 677         /* Fixed offset. */
 678         node.sample[1].flow_match_sample_offset_mode = 0x0;
 679         /*
 680          * Only the first two bytes will be used right now, and its offset will
 681          * start after the common header that with the length of a DW(u32).
 682          */
 683         node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
 684         prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
 685         if (!prf->obj) {
 686                 DRV_LOG(ERR, "Failed to create flex parser node object.");
 687                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 688         }
 689         prf->num = 2;
 690         ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
 691         if (ret) {
 692                 DRV_LOG(ERR, "Failed to query sample IDs.");
 693                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 694         }
 695         prf->offset[0] = 0x0;
 696         prf->offset[1] = sizeof(uint32_t);
 697         prf->ids[0] = ids[0];
 698         prf->ids[1] = ids[1];
 699         return 0;
 700 }
 701
 702 /*
 703  * Destroy the flex parser node, including the parser itself, input / output
 704  * arcs and DW samples. Resources could be reused then.
 705  *
 706  * @param dev
 707  *   Pointer to Ethernet device structure.
 708  */
 709 static void
 710 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
 711 {
 712         struct mlx5_priv *priv = dev->data->dev_private;
 713         struct mlx5_flex_parser_profiles *prf =
 714                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 715
 716         if (prf->obj)
 717                 mlx5_devx_cmd_destroy(prf->obj);
 718         prf->obj = NULL;
 719 }
 720
 721 /*
 722  * Allocate Rx and Tx UARs in robust fashion.
 723  * This routine handles the following UAR allocation issues:
 724  *
 725  *  - tries to allocate the UAR with the most appropriate memory
 726  *    mapping type from the ones supported by the host
 727  *
 728  *  - tries to allocate the UAR with non-NULL base address
 729  *    OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
 730  *    UAR base address if UAR was not the first object in the UAR page.
 731  *    It caused the PMD failure and we should try to get another UAR
 732  *    till we get the first one with non-NULL base address returned.
 733  */
 734 static int
 735 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
 736                      const struct mlx5_dev_config *config)
 737 {
 738         uint32_t uar_mapping, retry;
 739         int err = 0;
 740         void *base_addr;
 741
 742         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
 743 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 744                 /* Control the mapping type according to the settings. */
 745                 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
 746                               MLX5DV_UAR_ALLOC_TYPE_NC :
 747                               MLX5DV_UAR_ALLOC_TYPE_BF;
 748 #else
 749                 RTE_SET_USED(config);
 750                 /*
 751                  * It seems we have no way to control the memory mapping type
 752                  * for the UAR, the default "Write-Combining" type is supposed.
 753                  * The UAR initialization on queue creation queries the
 754                  * actual mapping type done by Verbs/kernel and setups the
 755                  * PMD datapath accordingly.
 756                  */
 757                 uar_mapping = 0;
 758 #endif
 759                 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
 760 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 761                 if (!sh->tx_uar &&
 762                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
 763                         if (config->dbnc == MLX5_TXDB_CACHED ||
 764                             config->dbnc == MLX5_TXDB_HEURISTIC)
 765                                 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
 766                                                  "is not supported by DevX");
 767                         /*
 768                          * In some environments like virtual machine
 769                          * the Write Combining mapped might be not supported
 770                          * and UAR allocation fails. We try "Non-Cached"
 771                          * mapping for the case. The tx_burst routines take
 772                          * the UAR mapping type into account on UAR setup
 773                          * on queue creation.
 774                          */
 775                         DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (BF)");
 776                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
 777                         sh->tx_uar = mlx5_glue->devx_alloc_uar
 778                                                         (sh->ctx, uar_mapping);
 779                 } else if (!sh->tx_uar &&
 780                            uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
 781                         if (config->dbnc == MLX5_TXDB_NCACHED)
 782                                 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
 783                                                  "is not supported by DevX");
 784                         /*
 785                          * If Verbs/kernel does not support "Non-Cached"
 786                          * try the "Write-Combining".
 787                          */
 788                         DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (NC)");
 789                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
 790                         sh->tx_uar = mlx5_glue->devx_alloc_uar
 791                                                         (sh->ctx, uar_mapping);
 792                 }
 793 #endif
 794                 if (!sh->tx_uar) {
 795                         DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
 796                         err = ENOMEM;
 797                         goto exit;
 798                 }
 799                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
 800                 if (base_addr)
 801                         break;
 802                 /*
 803                  * The UARs are allocated by rdma_core within the
 804                  * IB device context, on context closure all UARs
 805                  * will be freed, should be no memory/object leakage.
 806                  */
 807                 DRV_LOG(WARNING, "Retrying to allocate Tx DevX UAR");
 808                 sh->tx_uar = NULL;
 809         }
 810         /* Check whether we finally succeeded with valid UAR allocation. */
 811         if (!sh->tx_uar) {
 812                 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
 813                 err = ENOMEM;
 814                 goto exit;
 815         }
 816         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
 817                 uar_mapping = 0;
 818                 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
 819                                                         (sh->ctx, uar_mapping);
 820 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 821                 if (!sh->devx_rx_uar &&
 822                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
 823                         /*
 824                          * Rx UAR is used to control interrupts only,
 825                          * should be no datapath noticeable impact,
 826                          * can try "Non-Cached" mapping safely.
 827                          */
 828                         DRV_LOG(WARNING, "Failed to allocate Rx DevX UAR (BF)");
 829                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
 830                         sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
 831                                                         (sh->ctx, uar_mapping);
 832                 }
 833 #endif
 834                 if (!sh->devx_rx_uar) {
 835                         DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
 836                         err = ENOMEM;
 837                         goto exit;
 838                 }
 839                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
 840                 if (base_addr)
 841                         break;
 842                 /*
 843                  * The UARs are allocated by rdma_core within the
 844                  * IB device context, on context closure all UARs
 845                  * will be freed, should be no memory/object leakage.
 846                  */
 847                 DRV_LOG(WARNING, "Retrying to allocate Rx DevX UAR");
 848                 sh->devx_rx_uar = NULL;
 849         }
 850         /* Check whether we finally succeeded with valid UAR allocation. */
 851         if (!sh->devx_rx_uar) {
 852                 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
 853                 err = ENOMEM;
 854         }
 855 exit:
 856         return err;
 857 }
 858
 859 /**
 860  * Allocate shared device context. If there is multiport device the
 861  * master and representors will share this context, if there is single
 862  * port dedicated device, the context will be used by only given
 863  * port due to unification.
 864  *
 865  * Routine first searches the context for the specified device name,
 866  * if found the shared context assumed and reference counter is incremented.
 867  * If no context found the new one is created and initialized with specified
 868  * device context and parameters.
 869  *
 870  * @param[in] spawn
 871  *   Pointer to the device attributes (name, port, etc).
 872  * @param[in] config
 873  *   Pointer to device configuration structure.
 874  *
 875  * @return
 876  *   Pointer to mlx5_dev_ctx_shared object on success,
 877  *   otherwise NULL and rte_errno is set.
 878  */
 879 struct mlx5_dev_ctx_shared *
 880 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
 881                            const struct mlx5_dev_config *config)
 882 {
 883         struct mlx5_dev_ctx_shared *sh;
 884         int err = 0;
 885         uint32_t i;
 886         struct mlx5_devx_tis_attr tis_attr = { 0 };
 887
 888         MLX5_ASSERT(spawn);
 889         /* Secondary process should not create the shared context. */
 890         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 891         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 892         /* Search for IB context by device name. */
 893         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
 894                 if (!strcmp(sh->ibdev_name,
 895                         mlx5_os_get_dev_device_name(spawn->phys_dev))) {
 896                         sh->refcnt++;
 897                         goto exit;
 898                 }
 899         }
 900         /* No device found, we have to create new shared context. */
 901         MLX5_ASSERT(spawn->max_port);
 902         sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
 903                          sizeof(struct mlx5_dev_ctx_shared) +
 904                          spawn->max_port *
 905                          sizeof(struct mlx5_dev_shared_port),
 906                          RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 907         if (!sh) {
 908                 DRV_LOG(ERR, "shared context allocation failure");
 909                 rte_errno  = ENOMEM;
 910                 goto exit;
 911         }
 912         err = mlx5_os_open_device(spawn, config, sh);
 913         if (!sh->ctx)
 914                 goto error;
 915         err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
 916         if (err) {
 917                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
 918                 goto error;
 919         }
 920         sh->refcnt = 1;
 921         sh->bond_dev = UINT16_MAX;
 922         sh->max_port = spawn->max_port;
 923         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
 924                 sizeof(sh->ibdev_name) - 1);
 925         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
 926                 sizeof(sh->ibdev_path) - 1);
 927         /*
 928          * Setting port_id to max unallowed value means
 929          * there is no interrupt subhandler installed for
 930          * the given port index i.
 931          */
 932         for (i = 0; i < sh->max_port; i++) {
 933                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 934                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
 935         }
 936         sh->pd = mlx5_os_alloc_pd(sh->ctx);
 937         if (sh->pd == NULL) {
 938                 DRV_LOG(ERR, "PD allocation failure");
 939                 err = ENOMEM;
 940                 goto error;
 941         }
 942         if (sh->devx) {
 943                 /* Query the EQN for this core. */
 944                 err = mlx5_glue->devx_query_eqn(sh->ctx, 0, &sh->eqn);
 945                 if (err) {
 946                         rte_errno = errno;
 947                         DRV_LOG(ERR, "Failed to query event queue number %d.",
 948                                 rte_errno);
 949                         goto error;
 950                 }
 951                 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
 952                 if (err) {
 953                         DRV_LOG(ERR, "Fail to extract pdn from PD");
 954                         goto error;
 955                 }
 956                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
 957                 if (!sh->td) {
 958                         DRV_LOG(ERR, "TD allocation failure");
 959                         err = ENOMEM;
 960                         goto error;
 961                 }
 962                 tis_attr.transport_domain = sh->td->id;
 963                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
 964                 if (!sh->tis) {
 965                         DRV_LOG(ERR, "TIS allocation failure");
 966                         err = ENOMEM;
 967                         goto error;
 968                 }
 969                 err = mlx5_alloc_rxtx_uars(sh, config);
 970                 if (err)
 971                         goto error;
 972                 MLX5_ASSERT(sh->tx_uar);
 973                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
 974
 975                 MLX5_ASSERT(sh->devx_rx_uar);
 976                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
 977         }
 978 #ifndef RTE_ARCH_64
 979         /* Initialize UAR access locks for 32bit implementations. */
 980         rte_spinlock_init(&sh->uar_lock_cq);
 981         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
 982                 rte_spinlock_init(&sh->uar_lock[i]);
 983 #endif
 984         /*
 985          * Once the device is added to the list of memory event
 986          * callback, its global MR cache table cannot be expanded
 987          * on the fly because of deadlock. If it overflows, lookup
 988          * should be done by searching MR list linearly, which is slow.
 989          *
 990          * At this point the device is not added to the memory
 991          * event list yet, context is just being created.
 992          */
 993         err = mlx5_mr_btree_init(&sh->share_cache.cache,
 994                                  MLX5_MR_BTREE_CACHE_N * 2,
 995                                  spawn->pci_dev->device.numa_node);
 996         if (err) {
 997                 err = rte_errno;
 998                 goto error;
 999         }
1000         mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
1001                               &sh->share_cache.dereg_mr_cb);
1002         mlx5_os_dev_shared_handler_install(sh);
1003         sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
1004         if (!sh->cnt_id_tbl) {
1005                 err = rte_errno;
1006                 goto error;
1007         }
1008         mlx5_flow_aging_init(sh);
1009         mlx5_flow_counters_mng_init(sh);
1010         mlx5_flow_ipool_create(sh, config);
1011         /* Add device to memory callback list. */
1012         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1013         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1014                          sh, mem_event_cb);
1015         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1016         /* Add context to the global device list. */
1017         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1018 exit:
1019         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1020         return sh;
1021 error:
1022         pthread_mutex_destroy(&sh->txpp.mutex);
1023         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1024         MLX5_ASSERT(sh);
1025         if (sh->cnt_id_tbl)
1026                 mlx5_l3t_destroy(sh->cnt_id_tbl);
1027         if (sh->tis)
1028                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1029         if (sh->td)
1030                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1031         if (sh->devx_rx_uar)
1032                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1033         if (sh->tx_uar)
1034                 mlx5_glue->devx_free_uar(sh->tx_uar);
1035         if (sh->pd)
1036                 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1037         if (sh->ctx)
1038                 claim_zero(mlx5_glue->close_device(sh->ctx));
1039         mlx5_free(sh);
1040         MLX5_ASSERT(err > 0);
1041         rte_errno = err;
1042         return NULL;
1043 }
1044
1045 /**
1046  * Free shared IB device context. Decrement counter and if zero free
1047  * all allocated resources and close handles.
1048  *
1049  * @param[in] sh
1050  *   Pointer to mlx5_dev_ctx_shared object to free
1051  */
1052 void
1053 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1054 {
1055         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1056 #ifdef RTE_LIBRTE_MLX5_DEBUG
1057         /* Check the object presence in the list. */
1058         struct mlx5_dev_ctx_shared *lctx;
1059
1060         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1061                 if (lctx == sh)
1062                         break;
1063         MLX5_ASSERT(lctx);
1064         if (lctx != sh) {
1065                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1066                 goto exit;
1067         }
1068 #endif
1069         MLX5_ASSERT(sh);
1070         MLX5_ASSERT(sh->refcnt);
1071         /* Secondary process should not free the shared context. */
1072         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1073         if (--sh->refcnt)
1074                 goto exit;
1075         /* Remove from memory callback device list. */
1076         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1077         LIST_REMOVE(sh, mem_event_cb);
1078         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1079         /* Release created Memory Regions. */
1080         mlx5_mr_release_cache(&sh->share_cache);
1081         /* Remove context from the global device list. */
1082         LIST_REMOVE(sh, next);
1083         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1084         /*
1085          *  Ensure there is no async event handler installed.
1086          *  Only primary process handles async device events.
1087          **/
1088         mlx5_flow_counters_mng_close(sh);
1089         if (sh->aso_age_mng) {
1090                 mlx5_flow_aso_age_mng_close(sh);
1091                 sh->aso_age_mng = NULL;
1092         }
1093         mlx5_flow_ipool_destroy(sh);
1094         mlx5_os_dev_shared_handler_uninstall(sh);
1095         if (sh->cnt_id_tbl) {
1096                 mlx5_l3t_destroy(sh->cnt_id_tbl);
1097                 sh->cnt_id_tbl = NULL;
1098         }
1099         if (sh->tx_uar) {
1100                 mlx5_glue->devx_free_uar(sh->tx_uar);
1101                 sh->tx_uar = NULL;
1102         }
1103         if (sh->pd)
1104                 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1105         if (sh->tis)
1106                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1107         if (sh->td)
1108                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1109         if (sh->devx_rx_uar)
1110                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1111         if (sh->ctx)
1112                 claim_zero(mlx5_glue->close_device(sh->ctx));
1113         pthread_mutex_destroy(&sh->txpp.mutex);
1114         mlx5_free(sh);
1115         return;
1116 exit:
1117         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1118 }
1119
1120 /**
1121  * Destroy table hash list.
1122  *
1123  * @param[in] priv
1124  *   Pointer to the private device data structure.
1125  */
1126 void
1127 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1128 {
1129         struct mlx5_dev_ctx_shared *sh = priv->sh;
1130
1131         if (!sh->flow_tbls)
1132                 return;
1133         mlx5_hlist_destroy(sh->flow_tbls);
1134 }
1135
1136 /**
1137  * Initialize flow table hash list and create the root tables entry
1138  * for each domain.
1139  *
1140  * @param[in] priv
1141  *   Pointer to the private device data structure.
1142  *
1143  * @return
1144  *   Zero on success, positive error code otherwise.
1145  */
1146 int
1147 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1148 {
1149         int err = 0;
1150         /* Tables are only used in DV and DR modes. */
1151 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1152         struct mlx5_dev_ctx_shared *sh = priv->sh;
1153         char s[MLX5_HLIST_NAMESIZE];
1154
1155         MLX5_ASSERT(sh);
1156         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1157         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1158                                           0, 0, flow_dv_tbl_create_cb,
1159                                           flow_dv_tbl_match_cb,
1160                                           flow_dv_tbl_remove_cb);
1161         if (!sh->flow_tbls) {
1162                 DRV_LOG(ERR, "flow tables with hash creation failed.");
1163                 err = ENOMEM;
1164                 return err;
1165         }
1166         sh->flow_tbls->ctx = sh;
1167 #ifndef HAVE_MLX5DV_DR
1168         struct rte_flow_error error;
1169         struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1170
1171         /*
1172          * In case we have not DR support, the zero tables should be created
1173          * because DV expect to see them even if they cannot be created by
1174          * RDMA-CORE.
1175          */
1176         if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0, NULL, 0, 1, &error) ||
1177             !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0, NULL, 0, 1, &error) ||
1178             !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0, NULL, 0, 1, &error)) {
1179                 err = ENOMEM;
1180                 goto error;
1181         }
1182         return err;
1183 error:
1184         mlx5_free_table_hash_list(priv);
1185 #endif /* HAVE_MLX5DV_DR */
1186 #endif
1187         return err;
1188 }
1189
1190 /**
1191  * Retrieve integer value from environment variable.
1192  *
1193  * @param[in] name
1194  *   Environment variable name.
1195  *
1196  * @return
1197  *   Integer value, 0 if the variable is not set.
1198  */
1199 int
1200 mlx5_getenv_int(const char *name)
1201 {
1202         const char *val = getenv(name);
1203
1204         if (val == NULL)
1205                 return 0;
1206         return atoi(val);
1207 }
1208
1209 /**
1210  * DPDK callback to add udp tunnel port
1211  *
1212  * @param[in] dev
1213  *   A pointer to eth_dev
1214  * @param[in] udp_tunnel
1215  *   A pointer to udp tunnel
1216  *
1217  * @return
1218  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1219  */
1220 int
1221 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1222                          struct rte_eth_udp_tunnel *udp_tunnel)
1223 {
1224         MLX5_ASSERT(udp_tunnel != NULL);
1225         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1226             udp_tunnel->udp_port == 4789)
1227                 return 0;
1228         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1229             udp_tunnel->udp_port == 4790)
1230                 return 0;
1231         return -ENOTSUP;
1232 }
1233
1234 /**
1235  * Initialize process private data structure.
1236  *
1237  * @param dev
1238  *   Pointer to Ethernet device structure.
1239  *
1240  * @return
1241  *   0 on success, a negative errno value otherwise and rte_errno is set.
1242  */
1243 int
1244 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1245 {
1246         struct mlx5_priv *priv = dev->data->dev_private;
1247         struct mlx5_proc_priv *ppriv;
1248         size_t ppriv_size;
1249
1250         /*
1251          * UAR register table follows the process private structure. BlueFlame
1252          * registers for Tx queues are stored in the table.
1253          */
1254         ppriv_size =
1255                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1256         ppriv = mlx5_malloc(MLX5_MEM_RTE, ppriv_size, RTE_CACHE_LINE_SIZE,
1257                             dev->device->numa_node);
1258         if (!ppriv) {
1259                 rte_errno = ENOMEM;
1260                 return -rte_errno;
1261         }
1262         ppriv->uar_table_sz = ppriv_size;
1263         dev->process_private = ppriv;
1264         return 0;
1265 }
1266
1267 /**
1268  * Un-initialize process private data structure.
1269  *
1270  * @param dev
1271  *   Pointer to Ethernet device structure.
1272  */
1273 static void
1274 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1275 {
1276         if (!dev->process_private)
1277                 return;
1278         mlx5_free(dev->process_private);
1279         dev->process_private = NULL;
1280 }
1281
1282 /**
1283  * DPDK callback to close the device.
1284  *
1285  * Destroy all queues and objects, free memory.
1286  *
1287  * @param dev
1288  *   Pointer to Ethernet device structure.
1289  */
1290 int
1291 mlx5_dev_close(struct rte_eth_dev *dev)
1292 {
1293         struct mlx5_priv *priv = dev->data->dev_private;
1294         unsigned int i;
1295         int ret;
1296
1297         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1298                 /* Check if process_private released. */
1299                 if (!dev->process_private)
1300                         return 0;
1301                 mlx5_tx_uar_uninit_secondary(dev);
1302                 mlx5_proc_priv_uninit(dev);
1303                 rte_eth_dev_release_port(dev);
1304                 return 0;
1305         }
1306         if (!priv->sh)
1307                 return 0;
1308         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1309                 dev->data->port_id,
1310                 ((priv->sh->ctx != NULL) ?
1311                 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1312         /*
1313          * If default mreg copy action is removed at the stop stage,
1314          * the search will return none and nothing will be done anymore.
1315          */
1316         mlx5_flow_stop_default(dev);
1317         mlx5_traffic_disable(dev);
1318         /*
1319          * If all the flows are already flushed in the device stop stage,
1320          * then this will return directly without any action.
1321          */
1322         mlx5_flow_list_flush(dev, &priv->flows, true);
1323         mlx5_shared_action_flush(dev);
1324         mlx5_flow_meter_flush(dev, NULL);
1325         /* Prevent crashes when queues are still in use. */
1326         dev->rx_pkt_burst = removed_rx_burst;
1327         dev->tx_pkt_burst = removed_tx_burst;
1328         rte_wmb();
1329         /* Disable datapath on secondary process. */
1330         mlx5_mp_os_req_stop_rxtx(dev);
1331         /* Free the eCPRI flex parser resource. */
1332         mlx5_flex_parser_ecpri_release(dev);
1333         if (priv->rxqs != NULL) {
1334                 /* XXX race condition if mlx5_rx_burst() is still running. */
1335                 rte_delay_us_sleep(1000);
1336                 for (i = 0; (i != priv->rxqs_n); ++i)
1337                         mlx5_rxq_release(dev, i);
1338                 priv->rxqs_n = 0;
1339                 priv->rxqs = NULL;
1340         }
1341         if (priv->txqs != NULL) {
1342                 /* XXX race condition if mlx5_tx_burst() is still running. */
1343                 rte_delay_us_sleep(1000);
1344                 for (i = 0; (i != priv->txqs_n); ++i)
1345                         mlx5_txq_release(dev, i);
1346                 priv->txqs_n = 0;
1347                 priv->txqs = NULL;
1348         }
1349         mlx5_proc_priv_uninit(dev);
1350         if (priv->drop_queue.hrxq)
1351                 mlx5_drop_action_destroy(dev);
1352         if (priv->mreg_cp_tbl)
1353                 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1354         mlx5_mprq_free_mp(dev);
1355         mlx5_os_free_shared_dr(priv);
1356         if (priv->rss_conf.rss_key != NULL)
1357                 mlx5_free(priv->rss_conf.rss_key);
1358         if (priv->reta_idx != NULL)
1359                 mlx5_free(priv->reta_idx);
1360         if (priv->config.vf)
1361                 mlx5_os_mac_addr_flush(dev);
1362         if (priv->nl_socket_route >= 0)
1363                 close(priv->nl_socket_route);
1364         if (priv->nl_socket_rdma >= 0)
1365                 close(priv->nl_socket_rdma);
1366         if (priv->vmwa_context)
1367                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1368         ret = mlx5_hrxq_verify(dev);
1369         if (ret)
1370                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1371                         dev->data->port_id);
1372         ret = mlx5_ind_table_obj_verify(dev);
1373         if (ret)
1374                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1375                         dev->data->port_id);
1376         ret = mlx5_rxq_obj_verify(dev);
1377         if (ret)
1378                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1379                         dev->data->port_id);
1380         ret = mlx5_rxq_verify(dev);
1381         if (ret)
1382                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1383                         dev->data->port_id);
1384         ret = mlx5_txq_obj_verify(dev);
1385         if (ret)
1386                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1387                         dev->data->port_id);
1388         ret = mlx5_txq_verify(dev);
1389         if (ret)
1390                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1391                         dev->data->port_id);
1392         ret = mlx5_flow_verify(dev);
1393         if (ret)
1394                 DRV_LOG(WARNING, "port %u some flows still remain",
1395                         dev->data->port_id);
1396         mlx5_cache_list_destroy(&priv->hrxqs);
1397         /*
1398          * Free the shared context in last turn, because the cleanup
1399          * routines above may use some shared fields, like
1400          * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1401          * ifindex if Netlink fails.
1402          */
1403         mlx5_free_shared_dev_ctx(priv->sh);
1404         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1405                 unsigned int c = 0;
1406                 uint16_t port_id;
1407
1408                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1409                         struct mlx5_priv *opriv =
1410                                 rte_eth_devices[port_id].data->dev_private;
1411
1412                         if (!opriv ||
1413                             opriv->domain_id != priv->domain_id ||
1414                             &rte_eth_devices[port_id] == dev)
1415                                 continue;
1416                         ++c;
1417                         break;
1418                 }
1419                 if (!c)
1420                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1421         }
1422         memset(priv, 0, sizeof(*priv));
1423         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1424         /*
1425          * Reset mac_addrs to NULL such that it is not freed as part of
1426          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1427          * it is freed when dev_private is freed.
1428          */
1429         dev->data->mac_addrs = NULL;
1430         return 0;
1431 }
1432
1433 const struct eth_dev_ops mlx5_dev_ops = {
1434         .dev_configure = mlx5_dev_configure,
1435         .dev_start = mlx5_dev_start,
1436         .dev_stop = mlx5_dev_stop,
1437         .dev_set_link_down = mlx5_set_link_down,
1438         .dev_set_link_up = mlx5_set_link_up,
1439         .dev_close = mlx5_dev_close,
1440         .promiscuous_enable = mlx5_promiscuous_enable,
1441         .promiscuous_disable = mlx5_promiscuous_disable,
1442         .allmulticast_enable = mlx5_allmulticast_enable,
1443         .allmulticast_disable = mlx5_allmulticast_disable,
1444         .link_update = mlx5_link_update,
1445         .stats_get = mlx5_stats_get,
1446         .stats_reset = mlx5_stats_reset,
1447         .xstats_get = mlx5_xstats_get,
1448         .xstats_reset = mlx5_xstats_reset,
1449         .xstats_get_names = mlx5_xstats_get_names,
1450         .fw_version_get = mlx5_fw_version_get,
1451         .dev_infos_get = mlx5_dev_infos_get,
1452         .read_clock = mlx5_txpp_read_clock,
1453         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1454         .vlan_filter_set = mlx5_vlan_filter_set,
1455         .rx_queue_setup = mlx5_rx_queue_setup,
1456         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1457         .tx_queue_setup = mlx5_tx_queue_setup,
1458         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1459         .rx_queue_release = mlx5_rx_queue_release,
1460         .tx_queue_release = mlx5_tx_queue_release,
1461         .rx_queue_start = mlx5_rx_queue_start,
1462         .rx_queue_stop = mlx5_rx_queue_stop,
1463         .tx_queue_start = mlx5_tx_queue_start,
1464         .tx_queue_stop = mlx5_tx_queue_stop,
1465         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1466         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1467         .mac_addr_remove = mlx5_mac_addr_remove,
1468         .mac_addr_add = mlx5_mac_addr_add,
1469         .mac_addr_set = mlx5_mac_addr_set,
1470         .set_mc_addr_list = mlx5_set_mc_addr_list,
1471         .mtu_set = mlx5_dev_set_mtu,
1472         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1473         .vlan_offload_set = mlx5_vlan_offload_set,
1474         .reta_update = mlx5_dev_rss_reta_update,
1475         .reta_query = mlx5_dev_rss_reta_query,
1476         .rss_hash_update = mlx5_rss_hash_update,
1477         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1478         .filter_ctrl = mlx5_dev_filter_ctrl,
1479         .rxq_info_get = mlx5_rxq_info_get,
1480         .txq_info_get = mlx5_txq_info_get,
1481         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1482         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1483         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1484         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1485         .is_removed = mlx5_is_removed,
1486         .udp_tunnel_port_add  = mlx5_udp_tunnel_port_add,
1487         .get_module_info = mlx5_get_module_info,
1488         .get_module_eeprom = mlx5_get_module_eeprom,
1489         .hairpin_cap_get = mlx5_hairpin_cap_get,
1490         .mtr_ops_get = mlx5_flow_meter_ops_get,
1491         .hairpin_bind = mlx5_hairpin_bind,
1492         .hairpin_unbind = mlx5_hairpin_unbind,
1493         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1494         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1495         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1496         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1497 };
1498
1499 /* Available operations from secondary process. */
1500 const struct eth_dev_ops mlx5_dev_sec_ops = {
1501         .stats_get = mlx5_stats_get,
1502         .stats_reset = mlx5_stats_reset,
1503         .xstats_get = mlx5_xstats_get,
1504         .xstats_reset = mlx5_xstats_reset,
1505         .xstats_get_names = mlx5_xstats_get_names,
1506         .fw_version_get = mlx5_fw_version_get,
1507         .dev_infos_get = mlx5_dev_infos_get,
1508         .read_clock = mlx5_txpp_read_clock,
1509         .rx_queue_start = mlx5_rx_queue_start,
1510         .rx_queue_stop = mlx5_rx_queue_stop,
1511         .tx_queue_start = mlx5_tx_queue_start,
1512         .tx_queue_stop = mlx5_tx_queue_stop,
1513         .rxq_info_get = mlx5_rxq_info_get,
1514         .txq_info_get = mlx5_txq_info_get,
1515         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1516         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1517         .get_module_info = mlx5_get_module_info,
1518         .get_module_eeprom = mlx5_get_module_eeprom,
1519 };
1520
1521 /* Available operations in flow isolated mode. */
1522 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1523         .dev_configure = mlx5_dev_configure,
1524         .dev_start = mlx5_dev_start,
1525         .dev_stop = mlx5_dev_stop,
1526         .dev_set_link_down = mlx5_set_link_down,
1527         .dev_set_link_up = mlx5_set_link_up,
1528         .dev_close = mlx5_dev_close,
1529         .promiscuous_enable = mlx5_promiscuous_enable,
1530         .promiscuous_disable = mlx5_promiscuous_disable,
1531         .allmulticast_enable = mlx5_allmulticast_enable,
1532         .allmulticast_disable = mlx5_allmulticast_disable,
1533         .link_update = mlx5_link_update,
1534         .stats_get = mlx5_stats_get,
1535         .stats_reset = mlx5_stats_reset,
1536         .xstats_get = mlx5_xstats_get,
1537         .xstats_reset = mlx5_xstats_reset,
1538         .xstats_get_names = mlx5_xstats_get_names,
1539         .fw_version_get = mlx5_fw_version_get,
1540         .dev_infos_get = mlx5_dev_infos_get,
1541         .read_clock = mlx5_txpp_read_clock,
1542         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1543         .vlan_filter_set = mlx5_vlan_filter_set,
1544         .rx_queue_setup = mlx5_rx_queue_setup,
1545         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1546         .tx_queue_setup = mlx5_tx_queue_setup,
1547         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1548         .rx_queue_release = mlx5_rx_queue_release,
1549         .tx_queue_release = mlx5_tx_queue_release,
1550         .rx_queue_start = mlx5_rx_queue_start,
1551         .rx_queue_stop = mlx5_rx_queue_stop,
1552         .tx_queue_start = mlx5_tx_queue_start,
1553         .tx_queue_stop = mlx5_tx_queue_stop,
1554         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1555         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1556         .mac_addr_remove = mlx5_mac_addr_remove,
1557         .mac_addr_add = mlx5_mac_addr_add,
1558         .mac_addr_set = mlx5_mac_addr_set,
1559         .set_mc_addr_list = mlx5_set_mc_addr_list,
1560         .mtu_set = mlx5_dev_set_mtu,
1561         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1562         .vlan_offload_set = mlx5_vlan_offload_set,
1563         .filter_ctrl = mlx5_dev_filter_ctrl,
1564         .rxq_info_get = mlx5_rxq_info_get,
1565         .txq_info_get = mlx5_txq_info_get,
1566         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1567         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1568         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1569         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1570         .is_removed = mlx5_is_removed,
1571         .get_module_info = mlx5_get_module_info,
1572         .get_module_eeprom = mlx5_get_module_eeprom,
1573         .hairpin_cap_get = mlx5_hairpin_cap_get,
1574         .mtr_ops_get = mlx5_flow_meter_ops_get,
1575         .hairpin_bind = mlx5_hairpin_bind,
1576         .hairpin_unbind = mlx5_hairpin_unbind,
1577         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1578         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1579         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1580         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1581 };
1582
1583 /**
1584  * Verify and store value for device argument.
1585  *
1586  * @param[in] key
1587  *   Key argument to verify.
1588  * @param[in] val
1589  *   Value associated with key.
1590  * @param opaque
1591  *   User data.
1592  *
1593  * @return
1594  *   0 on success, a negative errno value otherwise and rte_errno is set.
1595  */
1596 static int
1597 mlx5_args_check(const char *key, const char *val, void *opaque)
1598 {
1599         struct mlx5_dev_config *config = opaque;
1600         unsigned long mod;
1601         signed long tmp;
1602
1603         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1604         if (!strcmp(MLX5_REPRESENTOR, key))
1605                 return 0;
1606         errno = 0;
1607         tmp = strtol(val, NULL, 0);
1608         if (errno) {
1609                 rte_errno = errno;
1610                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1611                 return -rte_errno;
1612         }
1613         if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1614                 /* Negative values are acceptable for some keys only. */
1615                 rte_errno = EINVAL;
1616                 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1617                 return -rte_errno;
1618         }
1619         mod = tmp >= 0 ? tmp : -tmp;
1620         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1621                 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1622                         DRV_LOG(ERR, "invalid CQE compression "
1623                                      "format parameter");
1624                         rte_errno = EINVAL;
1625                         return -rte_errno;
1626                 }
1627                 config->cqe_comp = !!tmp;
1628                 config->cqe_comp_fmt = tmp;
1629         } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1630                 config->cqe_pad = !!tmp;
1631         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1632                 config->hw_padding = !!tmp;
1633         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1634                 config->mprq.enabled = !!tmp;
1635         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1636                 config->mprq.stride_num_n = tmp;
1637         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1638                 config->mprq.stride_size_n = tmp;
1639         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1640                 config->mprq.max_memcpy_len = tmp;
1641         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1642                 config->mprq.min_rxqs_num = tmp;
1643         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1644                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1645                                  " converted to txq_inline_max", key);
1646                 config->txq_inline_max = tmp;
1647         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1648                 config->txq_inline_max = tmp;
1649         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1650                 config->txq_inline_min = tmp;
1651         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1652                 config->txq_inline_mpw = tmp;
1653         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1654                 config->txqs_inline = tmp;
1655         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1656                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1657         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1658                 config->mps = !!tmp;
1659         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1660                 if (tmp != MLX5_TXDB_CACHED &&
1661                     tmp != MLX5_TXDB_NCACHED &&
1662                     tmp != MLX5_TXDB_HEURISTIC) {
1663                         DRV_LOG(ERR, "invalid Tx doorbell "
1664                                      "mapping parameter");
1665                         rte_errno = EINVAL;
1666                         return -rte_errno;
1667                 }
1668                 config->dbnc = tmp;
1669         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1670                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1671         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1672                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1673                                  " converted to txq_inline_mpw", key);
1674                 config->txq_inline_mpw = tmp;
1675         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1676                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1677         } else if (strcmp(MLX5_TX_PP, key) == 0) {
1678                 if (!mod) {
1679                         DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1680                         rte_errno = EINVAL;
1681                         return -rte_errno;
1682                 }
1683                 config->tx_pp = tmp;
1684         } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1685                 config->tx_skew = tmp;
1686         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1687                 config->rx_vec_en = !!tmp;
1688         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1689                 config->l3_vxlan_en = !!tmp;
1690         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1691                 config->vf_nl_en = !!tmp;
1692         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1693                 config->dv_esw_en = !!tmp;
1694         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1695                 config->dv_flow_en = !!tmp;
1696         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1697                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1698                     tmp != MLX5_XMETA_MODE_META16 &&
1699                     tmp != MLX5_XMETA_MODE_META32 &&
1700                     tmp != MLX5_XMETA_MODE_MISS_INFO) {
1701                         DRV_LOG(ERR, "invalid extensive "
1702                                      "metadata parameter");
1703                         rte_errno = EINVAL;
1704                         return -rte_errno;
1705                 }
1706                 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
1707                         config->dv_xmeta_en = tmp;
1708                 else
1709                         config->dv_miss_info = 1;
1710         } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1711                 config->lacp_by_user = !!tmp;
1712         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1713                 config->mr_ext_memseg_en = !!tmp;
1714         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1715                 config->max_dump_files_num = tmp;
1716         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1717                 config->lro.timeout = tmp;
1718         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1719                 DRV_LOG(DEBUG, "class argument is %s.", val);
1720         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1721                 config->log_hp_size = tmp;
1722         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1723                 if (tmp != MLX5_RCM_NONE &&
1724                     tmp != MLX5_RCM_LIGHT &&
1725                     tmp != MLX5_RCM_AGGR) {
1726                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1727                         rte_errno = EINVAL;
1728                         return -rte_errno;
1729                 }
1730                 config->reclaim_mode = tmp;
1731         } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1732                 config->sys_mem_en = !!tmp;
1733         } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1734                 config->decap_en = !!tmp;
1735         } else {
1736                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1737                 rte_errno = EINVAL;
1738                 return -rte_errno;
1739         }
1740         return 0;
1741 }
1742
1743 /**
1744  * Parse device parameters.
1745  *
1746  * @param config
1747  *   Pointer to device configuration structure.
1748  * @param devargs
1749  *   Device arguments structure.
1750  *
1751  * @return
1752  *   0 on success, a negative errno value otherwise and rte_errno is set.
1753  */
1754 int
1755 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1756 {
1757         const char **params = (const char *[]){
1758                 MLX5_RXQ_CQE_COMP_EN,
1759                 MLX5_RXQ_CQE_PAD_EN,
1760                 MLX5_RXQ_PKT_PAD_EN,
1761                 MLX5_RX_MPRQ_EN,
1762                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1763                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1764                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1765                 MLX5_RXQS_MIN_MPRQ,
1766                 MLX5_TXQ_INLINE,
1767                 MLX5_TXQ_INLINE_MIN,
1768                 MLX5_TXQ_INLINE_MAX,
1769                 MLX5_TXQ_INLINE_MPW,
1770                 MLX5_TXQS_MIN_INLINE,
1771                 MLX5_TXQS_MAX_VEC,
1772                 MLX5_TXQ_MPW_EN,
1773                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1774                 MLX5_TXQ_MAX_INLINE_LEN,
1775                 MLX5_TX_DB_NC,
1776                 MLX5_TX_PP,
1777                 MLX5_TX_SKEW,
1778                 MLX5_TX_VEC_EN,
1779                 MLX5_RX_VEC_EN,
1780                 MLX5_L3_VXLAN_EN,
1781                 MLX5_VF_NL_EN,
1782                 MLX5_DV_ESW_EN,
1783                 MLX5_DV_FLOW_EN,
1784                 MLX5_DV_XMETA_EN,
1785                 MLX5_LACP_BY_USER,
1786                 MLX5_MR_EXT_MEMSEG_EN,
1787                 MLX5_REPRESENTOR,
1788                 MLX5_MAX_DUMP_FILES_NUM,
1789                 MLX5_LRO_TIMEOUT_USEC,
1790                 MLX5_CLASS_ARG_NAME,
1791                 MLX5_HP_BUF_SIZE,
1792                 MLX5_RECLAIM_MEM,
1793                 MLX5_SYS_MEM_EN,
1794                 MLX5_DECAP_EN,
1795                 NULL,
1796         };
1797         struct rte_kvargs *kvlist;
1798         int ret = 0;
1799         int i;
1800
1801         if (devargs == NULL)
1802                 return 0;
1803         /* Following UGLY cast is done to pass checkpatch. */
1804         kvlist = rte_kvargs_parse(devargs->args, params);
1805         if (kvlist == NULL) {
1806                 rte_errno = EINVAL;
1807                 return -rte_errno;
1808         }
1809         /* Process parameters. */
1810         for (i = 0; (params[i] != NULL); ++i) {
1811                 if (rte_kvargs_count(kvlist, params[i])) {
1812                         ret = rte_kvargs_process(kvlist, params[i],
1813                                                  mlx5_args_check, config);
1814                         if (ret) {
1815                                 rte_errno = EINVAL;
1816                                 rte_kvargs_free(kvlist);
1817                                 return -rte_errno;
1818                         }
1819                 }
1820         }
1821         rte_kvargs_free(kvlist);
1822         return 0;
1823 }
1824
1825 /**
1826  * Configures the minimal amount of data to inline into WQE
1827  * while sending packets.
1828  *
1829  * - the txq_inline_min has the maximal priority, if this
1830  *   key is specified in devargs
1831  * - if DevX is enabled the inline mode is queried from the
1832  *   device (HCA attributes and NIC vport context if needed).
1833  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1834  *   and none (0 bytes) for other NICs
1835  *
1836  * @param spawn
1837  *   Verbs device parameters (name, port, switch_info) to spawn.
1838  * @param config
1839  *   Device configuration parameters.
1840  */
1841 void
1842 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1843                     struct mlx5_dev_config *config)
1844 {
1845         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1846                 /* Application defines size of inlined data explicitly. */
1847                 switch (spawn->pci_dev->id.device_id) {
1848                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1849                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1850                         if (config->txq_inline_min <
1851                                        (int)MLX5_INLINE_HSIZE_L2) {
1852                                 DRV_LOG(DEBUG,
1853                                         "txq_inline_mix aligned to minimal"
1854                                         " ConnectX-4 required value %d",
1855                                         (int)MLX5_INLINE_HSIZE_L2);
1856                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1857                         }
1858                         break;
1859                 }
1860                 goto exit;
1861         }
1862         if (config->hca_attr.eth_net_offloads) {
1863                 /* We have DevX enabled, inline mode queried successfully. */
1864                 switch (config->hca_attr.wqe_inline_mode) {
1865                 case MLX5_CAP_INLINE_MODE_L2:
1866                         /* outer L2 header must be inlined. */
1867                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1868                         goto exit;
1869                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1870                         /* No inline data are required by NIC. */
1871                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1872                         config->hw_vlan_insert =
1873                                 config->hca_attr.wqe_vlan_insert;
1874                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1875                         goto exit;
1876                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1877                         /* inline mode is defined by NIC vport context. */
1878                         if (!config->hca_attr.eth_virt)
1879                                 break;
1880                         switch (config->hca_attr.vport_inline_mode) {
1881                         case MLX5_INLINE_MODE_NONE:
1882                                 config->txq_inline_min =
1883                                         MLX5_INLINE_HSIZE_NONE;
1884                                 goto exit;
1885                         case MLX5_INLINE_MODE_L2:
1886                                 config->txq_inline_min =
1887                                         MLX5_INLINE_HSIZE_L2;
1888                                 goto exit;
1889                         case MLX5_INLINE_MODE_IP:
1890                                 config->txq_inline_min =
1891                                         MLX5_INLINE_HSIZE_L3;
1892                                 goto exit;
1893                         case MLX5_INLINE_MODE_TCP_UDP:
1894                                 config->txq_inline_min =
1895                                         MLX5_INLINE_HSIZE_L4;
1896                                 goto exit;
1897                         case MLX5_INLINE_MODE_INNER_L2:
1898                                 config->txq_inline_min =
1899                                         MLX5_INLINE_HSIZE_INNER_L2;
1900                                 goto exit;
1901                         case MLX5_INLINE_MODE_INNER_IP:
1902                                 config->txq_inline_min =
1903                                         MLX5_INLINE_HSIZE_INNER_L3;
1904                                 goto exit;
1905                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
1906                                 config->txq_inline_min =
1907                                         MLX5_INLINE_HSIZE_INNER_L4;
1908                                 goto exit;
1909                         }
1910                 }
1911         }
1912         /*
1913          * We get here if we are unable to deduce
1914          * inline data size with DevX. Try PCI ID
1915          * to determine old NICs.
1916          */
1917         switch (spawn->pci_dev->id.device_id) {
1918         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1919         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1920         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1921         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1922                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1923                 config->hw_vlan_insert = 0;
1924                 break;
1925         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1926         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1927         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1928         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1929                 /*
1930                  * These NICs support VLAN insertion from WQE and
1931                  * report the wqe_vlan_insert flag. But there is the bug
1932                  * and PFC control may be broken, so disable feature.
1933                  */
1934                 config->hw_vlan_insert = 0;
1935                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1936                 break;
1937         default:
1938                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1939                 break;
1940         }
1941 exit:
1942         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1943 }
1944
1945 /**
1946  * Configures the metadata mask fields in the shared context.
1947  *
1948  * @param [in] dev
1949  *   Pointer to Ethernet device.
1950  */
1951 void
1952 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1953 {
1954         struct mlx5_priv *priv = dev->data->dev_private;
1955         struct mlx5_dev_ctx_shared *sh = priv->sh;
1956         uint32_t meta, mark, reg_c0;
1957
1958         reg_c0 = ~priv->vport_meta_mask;
1959         switch (priv->config.dv_xmeta_en) {
1960         case MLX5_XMETA_MODE_LEGACY:
1961                 meta = UINT32_MAX;
1962                 mark = MLX5_FLOW_MARK_MASK;
1963                 break;
1964         case MLX5_XMETA_MODE_META16:
1965                 meta = reg_c0 >> rte_bsf32(reg_c0);
1966                 mark = MLX5_FLOW_MARK_MASK;
1967                 break;
1968         case MLX5_XMETA_MODE_META32:
1969                 meta = UINT32_MAX;
1970                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1971                 break;
1972         default:
1973                 meta = 0;
1974                 mark = 0;
1975                 MLX5_ASSERT(false);
1976                 break;
1977         }
1978         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1979                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1980                                  sh->dv_mark_mask, mark);
1981         else
1982                 sh->dv_mark_mask = mark;
1983         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1984                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1985                                  sh->dv_meta_mask, meta);
1986         else
1987                 sh->dv_meta_mask = meta;
1988         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1989                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1990                                  sh->dv_meta_mask, reg_c0);
1991         else
1992                 sh->dv_regc0_mask = reg_c0;
1993         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1994         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1995         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1996         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1997 }
1998
1999 int
2000 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2001 {
2002         static const char *const dynf_names[] = {
2003                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2004                 RTE_MBUF_DYNFLAG_METADATA_NAME,
2005                 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
2006         };
2007         unsigned int i;
2008
2009         if (n < RTE_DIM(dynf_names))
2010                 return -ENOMEM;
2011         for (i = 0; i < RTE_DIM(dynf_names); i++) {
2012                 if (names[i] == NULL)
2013                         return -EINVAL;
2014                 strcpy(names[i], dynf_names[i]);
2015         }
2016         return RTE_DIM(dynf_names);
2017 }
2018
2019 /**
2020  * Comparison callback to sort device data.
2021  *
2022  * This is meant to be used with qsort().
2023  *
2024  * @param a[in]
2025  *   Pointer to pointer to first data object.
2026  * @param b[in]
2027  *   Pointer to pointer to second data object.
2028  *
2029  * @return
2030  *   0 if both objects are equal, less than 0 if the first argument is less
2031  *   than the second, greater than 0 otherwise.
2032  */
2033 int
2034 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2035                               struct mlx5_dev_config *config)
2036 {
2037         struct mlx5_dev_ctx_shared *sh = priv->sh;
2038         struct mlx5_dev_config *sh_conf = NULL;
2039         uint16_t port_id;
2040
2041         MLX5_ASSERT(sh);
2042         /* Nothing to compare for the single/first device. */
2043         if (sh->refcnt == 1)
2044                 return 0;
2045         /* Find the device with shared context. */
2046         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2047                 struct mlx5_priv *opriv =
2048                         rte_eth_devices[port_id].data->dev_private;
2049
2050                 if (opriv && opriv != priv && opriv->sh == sh) {
2051                         sh_conf = &opriv->config;
2052                         break;
2053                 }
2054         }
2055         if (!sh_conf)
2056                 return 0;
2057         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2058                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2059                              " for shared %s context", sh->ibdev_name);
2060                 rte_errno = EINVAL;
2061                 return rte_errno;
2062         }
2063         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2064                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2065                              " for shared %s context", sh->ibdev_name);
2066                 rte_errno = EINVAL;
2067                 return rte_errno;
2068         }
2069         return 0;
2070 }
2071
2072 /**
2073  * Look for the ethernet device belonging to mlx5 driver.
2074  *
2075  * @param[in] port_id
2076  *   port_id to start looking for device.
2077  * @param[in] pci_dev
2078  *   Pointer to the hint PCI device. When device is being probed
2079  *   the its siblings (master and preceding representors might
2080  *   not have assigned driver yet (because the mlx5_os_pci_probe()
2081  *   is not completed yet, for this case match on hint PCI
2082  *   device may be used to detect sibling device.
2083  *
2084  * @return
2085  *   port_id of found device, RTE_MAX_ETHPORT if not found.
2086  */
2087 uint16_t
2088 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
2089 {
2090         while (port_id < RTE_MAX_ETHPORTS) {
2091                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2092
2093                 if (dev->state != RTE_ETH_DEV_UNUSED &&
2094                     dev->device &&
2095                     (dev->device == &pci_dev->device ||
2096                      (dev->device->driver &&
2097                      dev->device->driver->name &&
2098                      !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
2099                         break;
2100                 port_id++;
2101         }
2102         if (port_id >= RTE_MAX_ETHPORTS)
2103                 return RTE_MAX_ETHPORTS;
2104         return port_id;
2105 }
2106
2107 /**
2108  * DPDK callback to remove a PCI device.
2109  *
2110  * This function removes all Ethernet devices belong to a given PCI device.
2111  *
2112  * @param[in] pci_dev
2113  *   Pointer to the PCI device.
2114  *
2115  * @return
2116  *   0 on success, the function cannot fail.
2117  */
2118 static int
2119 mlx5_pci_remove(struct rte_pci_device *pci_dev)
2120 {
2121         uint16_t port_id;
2122         int ret = 0;
2123
2124         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
2125                 /*
2126                  * mlx5_dev_close() is not registered to secondary process,
2127                  * call the close function explicitly for secondary process.
2128                  */
2129                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2130                         ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2131                 else
2132                         ret |= rte_eth_dev_close(port_id);
2133         }
2134         return ret == 0 ? 0 : -EIO;
2135 }
2136
2137 static const struct rte_pci_id mlx5_pci_id_map[] = {
2138         {
2139                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2140                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2141         },
2142         {
2143                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2144                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2145         },
2146         {
2147                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2148                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2149         },
2150         {
2151                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2152                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2153         },
2154         {
2155                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2156                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2157         },
2158         {
2159                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2160                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2161         },
2162         {
2163                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2164                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2165         },
2166         {
2167                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2168                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2169         },
2170         {
2171                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2172                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2173         },
2174         {
2175                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2176                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2177         },
2178         {
2179                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2180                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2181         },
2182         {
2183                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2184                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2185         },
2186         {
2187                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2188                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2189         },
2190         {
2191                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2192                                 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2193         },
2194         {
2195                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2196                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2197         },
2198         {
2199                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2200                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2201         },
2202         {
2203                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2204                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2205         },
2206         {
2207                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2208                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2209         },
2210         {
2211                 .vendor_id = 0
2212         }
2213 };
2214
2215 static struct mlx5_pci_driver mlx5_driver = {
2216         .driver_class = MLX5_CLASS_NET,
2217         .pci_driver = {
2218                 .driver = {
2219                         .name = MLX5_DRIVER_NAME,
2220                 },
2221                 .id_table = mlx5_pci_id_map,
2222                 .probe = mlx5_os_pci_probe,
2223                 .remove = mlx5_pci_remove,
2224                 .dma_map = mlx5_dma_map,
2225                 .dma_unmap = mlx5_dma_unmap,
2226                 .drv_flags = PCI_DRV_FLAGS,
2227         },
2228 };
2229
2230 /* Initialize driver log type. */
2231 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
2232
2233 /**
2234  * Driver initialization routine.
2235  */
2236 RTE_INIT(rte_mlx5_pmd_init)
2237 {
2238         mlx5_common_init();
2239         /* Build the static tables for Verbs conversion. */
2240         mlx5_set_ptype_table();
2241         mlx5_set_cksum_table();
2242         mlx5_set_swp_types_table();
2243         if (mlx5_glue)
2244                 mlx5_pci_driver_register(&mlx5_driver);
2245 }
2246
2247 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2248 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2249 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");