drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12
  13 #include <rte_malloc.h>
  14 #include <ethdev_driver.h>
  15 #include <ethdev_pci.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_common.h>
  19 #include <rte_kvargs.h>
  20 #include <rte_rwlock.h>
  21 #include <rte_spinlock.h>
  22 #include <rte_string_fns.h>
  23 #include <rte_alarm.h>
  24 #include <rte_cycles.h>
  25
  26 #include <mlx5_glue.h>
  27 #include <mlx5_devx_cmds.h>
  28 #include <mlx5_common.h>
  29 #include <mlx5_common_os.h>
  30 #include <mlx5_common_mp.h>
  31 #include <mlx5_common_pci.h>
  32 #include <mlx5_malloc.h>
  33
  34 #include "mlx5_defs.h"
  35 #include "mlx5.h"
  36 #include "mlx5_utils.h"
  37 #include "mlx5_rxtx.h"
  38 #include "mlx5_rx.h"
  39 #include "mlx5_tx.h"
  40 #include "mlx5_autoconf.h"
  41 #include "mlx5_mr.h"
  42 #include "mlx5_flow.h"
  43 #include "mlx5_flow_os.h"
  44 #include "rte_pmd_mlx5.h"
  45
  46 /* Device parameter to enable RX completion queue compression. */
  47 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  48
  49 /* Device parameter to enable padding Rx packet to cacheline size. */
  50 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  51
  52 /* Device parameter to enable Multi-Packet Rx queue. */
  53 #define MLX5_RX_MPRQ_EN "mprq_en"
  54
  55 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  56 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  57
  58 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  59 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  60
  61 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  62 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  63
  64 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  65 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  66
  67 /* Device parameter to configure inline send. Deprecated, ignored.*/
  68 #define MLX5_TXQ_INLINE "txq_inline"
  69
  70 /* Device parameter to limit packet size to inline with ordinary SEND. */
  71 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  72
  73 /* Device parameter to configure minimal data size to inline. */
  74 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  75
  76 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  77 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  78
  79 /*
  80  * Device parameter to configure the number of TX queues threshold for
  81  * enabling inline send.
  82  */
  83 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  84
  85 /*
  86  * Device parameter to configure the number of TX queues threshold for
  87  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  88  */
  89 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  90
  91 /* Device parameter to enable multi-packet send WQEs. */
  92 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  93
  94 /*
  95  * Device parameter to force doorbell register mapping
  96  * to non-cahed region eliminating the extra write memory barrier.
  97  */
  98 #define MLX5_TX_DB_NC "tx_db_nc"
  99
 100 /*
 101  * Device parameter to include 2 dsegs in the title WQEBB.
 102  * Deprecated, ignored.
 103  */
 104 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 105
 106 /*
 107  * Device parameter to limit the size of inlining packet.
 108  * Deprecated, ignored.
 109  */
 110 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 111
 112 /*
 113  * Device parameter to enable Tx scheduling on timestamps
 114  * and specify the packet pacing granularity in nanoseconds.
 115  */
 116 #define MLX5_TX_PP "tx_pp"
 117
 118 /*
 119  * Device parameter to specify skew in nanoseconds on Tx datapath,
 120  * it represents the time between SQ start WQE processing and
 121  * appearing actual packet data on the wire.
 122  */
 123 #define MLX5_TX_SKEW "tx_skew"
 124
 125 /*
 126  * Device parameter to enable hardware Tx vector.
 127  * Deprecated, ignored (no vectorized Tx routines anymore).
 128  */
 129 #define MLX5_TX_VEC_EN "tx_vec_en"
 130
 131 /* Device parameter to enable hardware Rx vector. */
 132 #define MLX5_RX_VEC_EN "rx_vec_en"
 133
 134 /* Allow L3 VXLAN flow creation. */
 135 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 136
 137 /* Activate DV E-Switch flow steering. */
 138 #define MLX5_DV_ESW_EN "dv_esw_en"
 139
 140 /* Activate DV flow steering. */
 141 #define MLX5_DV_FLOW_EN "dv_flow_en"
 142
 143 /* Enable extensive flow metadata support. */
 144 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 145
 146 /* Device parameter to let the user manage the lacp traffic of bonded device */
 147 #define MLX5_LACP_BY_USER "lacp_by_user"
 148
 149 /* Activate Netlink support in VF mode. */
 150 #define MLX5_VF_NL_EN "vf_nl_en"
 151
 152 /* Enable extending memsegs when creating a MR. */
 153 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 154
 155 /* Select port representors to instantiate. */
 156 #define MLX5_REPRESENTOR "representor"
 157
 158 /* Device parameter to configure the maximum number of dump files per queue. */
 159 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 160
 161 /* Configure timeout of LRO session (in microseconds). */
 162 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 163
 164 /*
 165  * Device parameter to configure the total data buffer size for a single
 166  * hairpin queue (logarithm value).
 167  */
 168 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 169
 170 /* Flow memory reclaim mode. */
 171 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 172
 173 /* The default memory allocator used in PMD. */
 174 #define MLX5_SYS_MEM_EN "sys_mem_en"
 175 /* Decap will be used or not. */
 176 #define MLX5_DECAP_EN "decap_en"
 177
 178 /* Shared memory between primary and secondary processes. */
 179 struct mlx5_shared_data *mlx5_shared_data;
 180
 181 /** Driver-specific log messages type. */
 182 int mlx5_logtype;
 183
 184 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 185                                                 LIST_HEAD_INITIALIZER();
 186 static pthread_mutex_t mlx5_dev_ctx_list_mutex;
 187 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 188 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
 189         [MLX5_IPOOL_DECAP_ENCAP] = {
 190                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 191                 .trunk_size = 64,
 192                 .grow_trunk = 3,
 193                 .grow_shift = 2,
 194                 .need_lock = 1,
 195                 .release_mem_en = 1,
 196                 .malloc = mlx5_malloc,
 197                 .free = mlx5_free,
 198                 .type = "mlx5_encap_decap_ipool",
 199         },
 200         [MLX5_IPOOL_PUSH_VLAN] = {
 201                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 202                 .trunk_size = 64,
 203                 .grow_trunk = 3,
 204                 .grow_shift = 2,
 205                 .need_lock = 1,
 206                 .release_mem_en = 1,
 207                 .malloc = mlx5_malloc,
 208                 .free = mlx5_free,
 209                 .type = "mlx5_push_vlan_ipool",
 210         },
 211         [MLX5_IPOOL_TAG] = {
 212                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 213                 .trunk_size = 64,
 214                 .grow_trunk = 3,
 215                 .grow_shift = 2,
 216                 .need_lock = 1,
 217                 .release_mem_en = 1,
 218                 .malloc = mlx5_malloc,
 219                 .free = mlx5_free,
 220                 .type = "mlx5_tag_ipool",
 221         },
 222         [MLX5_IPOOL_PORT_ID] = {
 223                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 224                 .trunk_size = 64,
 225                 .grow_trunk = 3,
 226                 .grow_shift = 2,
 227                 .need_lock = 1,
 228                 .release_mem_en = 1,
 229                 .malloc = mlx5_malloc,
 230                 .free = mlx5_free,
 231                 .type = "mlx5_port_id_ipool",
 232         },
 233         [MLX5_IPOOL_JUMP] = {
 234                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 235                 .trunk_size = 64,
 236                 .grow_trunk = 3,
 237                 .grow_shift = 2,
 238                 .need_lock = 1,
 239                 .release_mem_en = 1,
 240                 .malloc = mlx5_malloc,
 241                 .free = mlx5_free,
 242                 .type = "mlx5_jump_ipool",
 243         },
 244         [MLX5_IPOOL_SAMPLE] = {
 245                 .size = sizeof(struct mlx5_flow_dv_sample_resource),
 246                 .trunk_size = 64,
 247                 .grow_trunk = 3,
 248                 .grow_shift = 2,
 249                 .need_lock = 1,
 250                 .release_mem_en = 1,
 251                 .malloc = mlx5_malloc,
 252                 .free = mlx5_free,
 253                 .type = "mlx5_sample_ipool",
 254         },
 255         [MLX5_IPOOL_DEST_ARRAY] = {
 256                 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
 257                 .trunk_size = 64,
 258                 .grow_trunk = 3,
 259                 .grow_shift = 2,
 260                 .need_lock = 1,
 261                 .release_mem_en = 1,
 262                 .malloc = mlx5_malloc,
 263                 .free = mlx5_free,
 264                 .type = "mlx5_dest_array_ipool",
 265         },
 266         [MLX5_IPOOL_TUNNEL_ID] = {
 267                 .size = sizeof(struct mlx5_flow_tunnel),
 268                 .trunk_size = MLX5_MAX_TUNNELS,
 269                 .need_lock = 1,
 270                 .release_mem_en = 1,
 271                 .type = "mlx5_tunnel_offload",
 272         },
 273         [MLX5_IPOOL_TNL_TBL_ID] = {
 274                 .size = 0,
 275                 .need_lock = 1,
 276                 .type = "mlx5_flow_tnl_tbl_ipool",
 277         },
 278 #endif
 279         [MLX5_IPOOL_MTR] = {
 280                 /**
 281                  * The ipool index should grow continually from small to big,
 282                  * for meter idx, so not set grow_trunk to avoid meter index
 283                  * not jump continually.
 284                  */
 285                 .size = sizeof(struct mlx5_flow_meter),
 286                 .trunk_size = 64,
 287                 .need_lock = 1,
 288                 .release_mem_en = 1,
 289                 .malloc = mlx5_malloc,
 290                 .free = mlx5_free,
 291                 .type = "mlx5_meter_ipool",
 292         },
 293         [MLX5_IPOOL_MCP] = {
 294                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 295                 .trunk_size = 64,
 296                 .grow_trunk = 3,
 297                 .grow_shift = 2,
 298                 .need_lock = 1,
 299                 .release_mem_en = 1,
 300                 .malloc = mlx5_malloc,
 301                 .free = mlx5_free,
 302                 .type = "mlx5_mcp_ipool",
 303         },
 304         [MLX5_IPOOL_HRXQ] = {
 305                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 306                 .trunk_size = 64,
 307                 .grow_trunk = 3,
 308                 .grow_shift = 2,
 309                 .need_lock = 1,
 310                 .release_mem_en = 1,
 311                 .malloc = mlx5_malloc,
 312                 .free = mlx5_free,
 313                 .type = "mlx5_hrxq_ipool",
 314         },
 315         [MLX5_IPOOL_MLX5_FLOW] = {
 316                 /*
 317                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 318                  * It set in run time according to PCI function configuration.
 319                  */
 320                 .size = 0,
 321                 .trunk_size = 64,
 322                 .grow_trunk = 3,
 323                 .grow_shift = 2,
 324                 .need_lock = 1,
 325                 .release_mem_en = 1,
 326                 .malloc = mlx5_malloc,
 327                 .free = mlx5_free,
 328                 .type = "mlx5_flow_handle_ipool",
 329         },
 330         [MLX5_IPOOL_RTE_FLOW] = {
 331                 .size = sizeof(struct rte_flow),
 332                 .trunk_size = 4096,
 333                 .need_lock = 1,
 334                 .release_mem_en = 1,
 335                 .malloc = mlx5_malloc,
 336                 .free = mlx5_free,
 337                 .type = "rte_flow_ipool",
 338         },
 339         [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
 340                 .size = 0,
 341                 .need_lock = 1,
 342                 .type = "mlx5_flow_rss_id_ipool",
 343         },
 344         [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
 345                 .size = sizeof(struct mlx5_shared_action_rss),
 346                 .trunk_size = 64,
 347                 .grow_trunk = 3,
 348                 .grow_shift = 2,
 349                 .need_lock = 1,
 350                 .release_mem_en = 1,
 351                 .malloc = mlx5_malloc,
 352                 .free = mlx5_free,
 353                 .type = "mlx5_shared_action_rss",
 354         },
 355 };
 356
 357
 358 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 359 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 360
 361 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 362
 363 /**
 364  * Decide whether representor ID is a HPF(host PF) port on BF2.
 365  *
 366  * @param dev
 367  *   Pointer to Ethernet device structure.
 368  *
 369  * @return
 370  *   Non-zero if HPF, otherwise 0.
 371  */
 372 bool
 373 mlx5_is_hpf(struct rte_eth_dev *dev)
 374 {
 375         struct mlx5_priv *priv = dev->data->dev_private;
 376         uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id);
 377         int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
 378
 379         return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF &&
 380                MLX5_REPRESENTOR_REPR(-1) == repr;
 381 }
 382
 383 /**
 384  * Initialize the ASO aging management structure.
 385  *
 386  * @param[in] sh
 387  *   Pointer to mlx5_dev_ctx_shared object to free
 388  *
 389  * @return
 390  *   0 on success, a negative errno value otherwise and rte_errno is set.
 391  */
 392 int
 393 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
 394 {
 395         int err;
 396
 397         if (sh->aso_age_mng)
 398                 return 0;
 399         sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
 400                                       RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 401         if (!sh->aso_age_mng) {
 402                 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
 403                 rte_errno = ENOMEM;
 404                 return -ENOMEM;
 405         }
 406         err = mlx5_aso_queue_init(sh);
 407         if (err) {
 408                 mlx5_free(sh->aso_age_mng);
 409                 return -1;
 410         }
 411         rte_spinlock_init(&sh->aso_age_mng->resize_sl);
 412         rte_spinlock_init(&sh->aso_age_mng->free_sl);
 413         LIST_INIT(&sh->aso_age_mng->free);
 414         return 0;
 415 }
 416
 417 /**
 418  * Close and release all the resources of the ASO aging management structure.
 419  *
 420  * @param[in] sh
 421  *   Pointer to mlx5_dev_ctx_shared object to free.
 422  */
 423 static void
 424 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
 425 {
 426         int i, j;
 427
 428         mlx5_aso_queue_stop(sh);
 429         mlx5_aso_queue_uninit(sh);
 430         if (sh->aso_age_mng->pools) {
 431                 struct mlx5_aso_age_pool *pool;
 432
 433                 for (i = 0; i < sh->aso_age_mng->next; ++i) {
 434                         pool = sh->aso_age_mng->pools[i];
 435                         claim_zero(mlx5_devx_cmd_destroy
 436                                                 (pool->flow_hit_aso_obj));
 437                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
 438                                 if (pool->actions[j].dr_action)
 439                                         claim_zero
 440                                             (mlx5_flow_os_destroy_flow_action
 441                                               (pool->actions[j].dr_action));
 442                         mlx5_free(pool);
 443                 }
 444                 mlx5_free(sh->aso_age_mng->pools);
 445         }
 446         mlx5_free(sh->aso_age_mng);
 447 }
 448
 449 /**
 450  * Initialize the shared aging list information per port.
 451  *
 452  * @param[in] sh
 453  *   Pointer to mlx5_dev_ctx_shared object.
 454  */
 455 static void
 456 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 457 {
 458         uint32_t i;
 459         struct mlx5_age_info *age_info;
 460
 461         for (i = 0; i < sh->max_port; i++) {
 462                 age_info = &sh->port[i].age_info;
 463                 age_info->flags = 0;
 464                 TAILQ_INIT(&age_info->aged_counters);
 465                 LIST_INIT(&age_info->aged_aso);
 466                 rte_spinlock_init(&age_info->aged_sl);
 467                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 468         }
 469 }
 470
 471 /**
 472  * Initialize the counters management structure.
 473  *
 474  * @param[in] sh
 475  *   Pointer to mlx5_dev_ctx_shared object to free
 476  */
 477 static void
 478 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 479 {
 480         int i;
 481
 482         memset(&sh->cmng, 0, sizeof(sh->cmng));
 483         TAILQ_INIT(&sh->cmng.flow_counters);
 484         sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
 485         sh->cmng.max_id = -1;
 486         sh->cmng.last_pool_idx = POOL_IDX_INVALID;
 487         rte_spinlock_init(&sh->cmng.pool_update_sl);
 488         for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
 489                 TAILQ_INIT(&sh->cmng.counters[i]);
 490                 rte_spinlock_init(&sh->cmng.csl[i]);
 491         }
 492 }
 493
 494 /**
 495  * Destroy all the resources allocated for a counter memory management.
 496  *
 497  * @param[in] mng
 498  *   Pointer to the memory management structure.
 499  */
 500 static void
 501 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 502 {
 503         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 504
 505         LIST_REMOVE(mng, next);
 506         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 507         claim_zero(mlx5_os_umem_dereg(mng->umem));
 508         mlx5_free(mem);
 509 }
 510
 511 /**
 512  * Close and release all the resources of the counters management.
 513  *
 514  * @param[in] sh
 515  *   Pointer to mlx5_dev_ctx_shared object to free.
 516  */
 517 static void
 518 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 519 {
 520         struct mlx5_counter_stats_mem_mng *mng;
 521         int i, j;
 522         int retries = 1024;
 523
 524         rte_errno = 0;
 525         while (--retries) {
 526                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 527                 if (rte_errno != EINPROGRESS)
 528                         break;
 529                 rte_pause();
 530         }
 531
 532         if (sh->cmng.pools) {
 533                 struct mlx5_flow_counter_pool *pool;
 534                 uint16_t n_valid = sh->cmng.n_valid;
 535                 bool fallback = sh->cmng.counter_fallback;
 536
 537                 for (i = 0; i < n_valid; ++i) {
 538                         pool = sh->cmng.pools[i];
 539                         if (!fallback && pool->min_dcs)
 540                                 claim_zero(mlx5_devx_cmd_destroy
 541                                                                (pool->min_dcs));
 542                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 543                                 struct mlx5_flow_counter *cnt =
 544                                                 MLX5_POOL_GET_CNT(pool, j);
 545
 546                                 if (cnt->action)
 547                                         claim_zero
 548                                          (mlx5_flow_os_destroy_flow_action
 549                                           (cnt->action));
 550                                 if (fallback && MLX5_POOL_GET_CNT
 551                                     (pool, j)->dcs_when_free)
 552                                         claim_zero(mlx5_devx_cmd_destroy
 553                                                    (cnt->dcs_when_free));
 554                         }
 555                         mlx5_free(pool);
 556                 }
 557                 mlx5_free(sh->cmng.pools);
 558         }
 559         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 560         while (mng) {
 561                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 562                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 563         }
 564         memset(&sh->cmng, 0, sizeof(sh->cmng));
 565 }
 566
 567 /* Send FLOW_AGED event if needed. */
 568 void
 569 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
 570 {
 571         struct mlx5_age_info *age_info;
 572         uint32_t i;
 573
 574         for (i = 0; i < sh->max_port; i++) {
 575                 age_info = &sh->port[i].age_info;
 576                 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
 577                         continue;
 578                 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER))
 579                         rte_eth_dev_callback_process
 580                                 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
 581                                 RTE_ETH_EVENT_FLOW_AGED, NULL);
 582                 age_info->flags = 0;
 583         }
 584 }
 585
 586 /**
 587  * Initialize the flow resources' indexed mempool.
 588  *
 589  * @param[in] sh
 590  *   Pointer to mlx5_dev_ctx_shared object.
 591  * @param[in] sh
 592  *   Pointer to user dev config.
 593  */
 594 static void
 595 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 596                        const struct mlx5_dev_config *config)
 597 {
 598         uint8_t i;
 599         struct mlx5_indexed_pool_config cfg;
 600
 601         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 602                 cfg = mlx5_ipool_cfg[i];
 603                 switch (i) {
 604                 default:
 605                         break;
 606                 /*
 607                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 608                  * according to PCI function flow configuration.
 609                  */
 610                 case MLX5_IPOOL_MLX5_FLOW:
 611                         cfg.size = config->dv_flow_en ?
 612                                 sizeof(struct mlx5_flow_handle) :
 613                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 614                         break;
 615                 }
 616                 if (config->reclaim_mode)
 617                         cfg.release_mem_en = 1;
 618                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 619         }
 620 }
 621
 622 /**
 623  * Release the flow resources' indexed mempool.
 624  *
 625  * @param[in] sh
 626  *   Pointer to mlx5_dev_ctx_shared object.
 627  */
 628 static void
 629 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 630 {
 631         uint8_t i;
 632
 633         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 634                 mlx5_ipool_destroy(sh->ipool[i]);
 635 }
 636
 637 /*
 638  * Check if dynamic flex parser for eCPRI already exists.
 639  *
 640  * @param dev
 641  *   Pointer to Ethernet device structure.
 642  *
 643  * @return
 644  *   true on exists, false on not.
 645  */
 646 bool
 647 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
 648 {
 649         struct mlx5_priv *priv = dev->data->dev_private;
 650         struct mlx5_flex_parser_profiles *prf =
 651                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 652
 653         return !!prf->obj;
 654 }
 655
 656 /*
 657  * Allocation of a flex parser for eCPRI. Once created, this parser related
 658  * resources will be held until the device is closed.
 659  *
 660  * @param dev
 661  *   Pointer to Ethernet device structure.
 662  *
 663  * @return
 664  *   0 on success, a negative errno value otherwise and rte_errno is set.
 665  */
 666 int
 667 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
 668 {
 669         struct mlx5_priv *priv = dev->data->dev_private;
 670         struct mlx5_flex_parser_profiles *prf =
 671                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 672         struct mlx5_devx_graph_node_attr node = {
 673                 .modify_field_select = 0,
 674         };
 675         uint32_t ids[8];
 676         int ret;
 677
 678         if (!priv->config.hca_attr.parse_graph_flex_node) {
 679                 DRV_LOG(ERR, "Dynamic flex parser is not supported "
 680                         "for device %s.", priv->dev_data->name);
 681                 return -ENOTSUP;
 682         }
 683         node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
 684         /* 8 bytes now: 4B common header + 4B message body header. */
 685         node.header_length_base_value = 0x8;
 686         /* After MAC layer: Ether / VLAN. */
 687         node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
 688         /* Type of compared condition should be 0xAEFE in the L2 layer. */
 689         node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
 690         /* Sample #0: type in common header. */
 691         node.sample[0].flow_match_sample_en = 1;
 692         /* Fixed offset. */
 693         node.sample[0].flow_match_sample_offset_mode = 0x0;
 694         /* Only the 2nd byte will be used. */
 695         node.sample[0].flow_match_sample_field_base_offset = 0x0;
 696         /* Sample #1: message payload. */
 697         node.sample[1].flow_match_sample_en = 1;
 698         /* Fixed offset. */
 699         node.sample[1].flow_match_sample_offset_mode = 0x0;
 700         /*
 701          * Only the first two bytes will be used right now, and its offset will
 702          * start after the common header that with the length of a DW(u32).
 703          */
 704         node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
 705         prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
 706         if (!prf->obj) {
 707                 DRV_LOG(ERR, "Failed to create flex parser node object.");
 708                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 709         }
 710         prf->num = 2;
 711         ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
 712         if (ret) {
 713                 DRV_LOG(ERR, "Failed to query sample IDs.");
 714                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 715         }
 716         prf->offset[0] = 0x0;
 717         prf->offset[1] = sizeof(uint32_t);
 718         prf->ids[0] = ids[0];
 719         prf->ids[1] = ids[1];
 720         return 0;
 721 }
 722
 723 /*
 724  * Destroy the flex parser node, including the parser itself, input / output
 725  * arcs and DW samples. Resources could be reused then.
 726  *
 727  * @param dev
 728  *   Pointer to Ethernet device structure.
 729  */
 730 static void
 731 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
 732 {
 733         struct mlx5_priv *priv = dev->data->dev_private;
 734         struct mlx5_flex_parser_profiles *prf =
 735                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 736
 737         if (prf->obj)
 738                 mlx5_devx_cmd_destroy(prf->obj);
 739         prf->obj = NULL;
 740 }
 741
 742 /*
 743  * Allocate Rx and Tx UARs in robust fashion.
 744  * This routine handles the following UAR allocation issues:
 745  *
 746  *  - tries to allocate the UAR with the most appropriate memory
 747  *    mapping type from the ones supported by the host
 748  *
 749  *  - tries to allocate the UAR with non-NULL base address
 750  *    OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
 751  *    UAR base address if UAR was not the first object in the UAR page.
 752  *    It caused the PMD failure and we should try to get another UAR
 753  *    till we get the first one with non-NULL base address returned.
 754  */
 755 static int
 756 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
 757                      const struct mlx5_dev_config *config)
 758 {
 759         uint32_t uar_mapping, retry;
 760         int err = 0;
 761         void *base_addr;
 762
 763         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
 764 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 765                 /* Control the mapping type according to the settings. */
 766                 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
 767                               MLX5DV_UAR_ALLOC_TYPE_NC :
 768                               MLX5DV_UAR_ALLOC_TYPE_BF;
 769 #else
 770                 RTE_SET_USED(config);
 771                 /*
 772                  * It seems we have no way to control the memory mapping type
 773                  * for the UAR, the default "Write-Combining" type is supposed.
 774                  * The UAR initialization on queue creation queries the
 775                  * actual mapping type done by Verbs/kernel and setups the
 776                  * PMD datapath accordingly.
 777                  */
 778                 uar_mapping = 0;
 779 #endif
 780                 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
 781 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 782                 if (!sh->tx_uar &&
 783                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
 784                         if (config->dbnc == MLX5_TXDB_CACHED ||
 785                             config->dbnc == MLX5_TXDB_HEURISTIC)
 786                                 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
 787                                                  "is not supported by DevX");
 788                         /*
 789                          * In some environments like virtual machine
 790                          * the Write Combining mapped might be not supported
 791                          * and UAR allocation fails. We try "Non-Cached"
 792                          * mapping for the case. The tx_burst routines take
 793                          * the UAR mapping type into account on UAR setup
 794                          * on queue creation.
 795                          */
 796                         DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (BF)");
 797                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
 798                         sh->tx_uar = mlx5_glue->devx_alloc_uar
 799                                                         (sh->ctx, uar_mapping);
 800                 } else if (!sh->tx_uar &&
 801                            uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
 802                         if (config->dbnc == MLX5_TXDB_NCACHED)
 803                                 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
 804                                                  "is not supported by DevX");
 805                         /*
 806                          * If Verbs/kernel does not support "Non-Cached"
 807                          * try the "Write-Combining".
 808                          */
 809                         DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (NC)");
 810                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
 811                         sh->tx_uar = mlx5_glue->devx_alloc_uar
 812                                                         (sh->ctx, uar_mapping);
 813                 }
 814 #endif
 815                 if (!sh->tx_uar) {
 816                         DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
 817                         err = ENOMEM;
 818                         goto exit;
 819                 }
 820                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
 821                 if (base_addr)
 822                         break;
 823                 /*
 824                  * The UARs are allocated by rdma_core within the
 825                  * IB device context, on context closure all UARs
 826                  * will be freed, should be no memory/object leakage.
 827                  */
 828                 DRV_LOG(DEBUG, "Retrying to allocate Tx DevX UAR");
 829                 sh->tx_uar = NULL;
 830         }
 831         /* Check whether we finally succeeded with valid UAR allocation. */
 832         if (!sh->tx_uar) {
 833                 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
 834                 err = ENOMEM;
 835                 goto exit;
 836         }
 837         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
 838                 uar_mapping = 0;
 839                 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
 840                                                         (sh->ctx, uar_mapping);
 841 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 842                 if (!sh->devx_rx_uar &&
 843                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
 844                         /*
 845                          * Rx UAR is used to control interrupts only,
 846                          * should be no datapath noticeable impact,
 847                          * can try "Non-Cached" mapping safely.
 848                          */
 849                         DRV_LOG(DEBUG, "Failed to allocate Rx DevX UAR (BF)");
 850                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
 851                         sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
 852                                                         (sh->ctx, uar_mapping);
 853                 }
 854 #endif
 855                 if (!sh->devx_rx_uar) {
 856                         DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
 857                         err = ENOMEM;
 858                         goto exit;
 859                 }
 860                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
 861                 if (base_addr)
 862                         break;
 863                 /*
 864                  * The UARs are allocated by rdma_core within the
 865                  * IB device context, on context closure all UARs
 866                  * will be freed, should be no memory/object leakage.
 867                  */
 868                 DRV_LOG(DEBUG, "Retrying to allocate Rx DevX UAR");
 869                 sh->devx_rx_uar = NULL;
 870         }
 871         /* Check whether we finally succeeded with valid UAR allocation. */
 872         if (!sh->devx_rx_uar) {
 873                 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
 874                 err = ENOMEM;
 875         }
 876 exit:
 877         return err;
 878 }
 879
 880 /**
 881  * Allocate shared device context. If there is multiport device the
 882  * master and representors will share this context, if there is single
 883  * port dedicated device, the context will be used by only given
 884  * port due to unification.
 885  *
 886  * Routine first searches the context for the specified device name,
 887  * if found the shared context assumed and reference counter is incremented.
 888  * If no context found the new one is created and initialized with specified
 889  * device context and parameters.
 890  *
 891  * @param[in] spawn
 892  *   Pointer to the device attributes (name, port, etc).
 893  * @param[in] config
 894  *   Pointer to device configuration structure.
 895  *
 896  * @return
 897  *   Pointer to mlx5_dev_ctx_shared object on success,
 898  *   otherwise NULL and rte_errno is set.
 899  */
 900 struct mlx5_dev_ctx_shared *
 901 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
 902                            const struct mlx5_dev_config *config)
 903 {
 904         struct mlx5_dev_ctx_shared *sh;
 905         int err = 0;
 906         uint32_t i;
 907         struct mlx5_devx_tis_attr tis_attr = { 0 };
 908
 909         MLX5_ASSERT(spawn);
 910         /* Secondary process should not create the shared context. */
 911         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 912         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 913         /* Search for IB context by device name. */
 914         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
 915                 if (!strcmp(sh->ibdev_name,
 916                         mlx5_os_get_dev_device_name(spawn->phys_dev))) {
 917                         sh->refcnt++;
 918                         goto exit;
 919                 }
 920         }
 921         /* No device found, we have to create new shared context. */
 922         MLX5_ASSERT(spawn->max_port);
 923         sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
 924                          sizeof(struct mlx5_dev_ctx_shared) +
 925                          spawn->max_port *
 926                          sizeof(struct mlx5_dev_shared_port),
 927                          RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 928         if (!sh) {
 929                 DRV_LOG(ERR, "shared context allocation failure");
 930                 rte_errno  = ENOMEM;
 931                 goto exit;
 932         }
 933         if (spawn->bond_info)
 934                 sh->bond = *spawn->bond_info;
 935         err = mlx5_os_open_device(spawn, config, sh);
 936         if (!sh->ctx)
 937                 goto error;
 938         err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
 939         if (err) {
 940                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
 941                 goto error;
 942         }
 943         sh->refcnt = 1;
 944         sh->max_port = spawn->max_port;
 945         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
 946                 sizeof(sh->ibdev_name) - 1);
 947         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
 948                 sizeof(sh->ibdev_path) - 1);
 949         /*
 950          * Setting port_id to max unallowed value means
 951          * there is no interrupt subhandler installed for
 952          * the given port index i.
 953          */
 954         for (i = 0; i < sh->max_port; i++) {
 955                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 956                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
 957         }
 958         sh->pd = mlx5_os_alloc_pd(sh->ctx);
 959         if (sh->pd == NULL) {
 960                 DRV_LOG(ERR, "PD allocation failure");
 961                 err = ENOMEM;
 962                 goto error;
 963         }
 964         if (sh->devx) {
 965                 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
 966                 if (err) {
 967                         DRV_LOG(ERR, "Fail to extract pdn from PD");
 968                         goto error;
 969                 }
 970                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
 971                 if (!sh->td) {
 972                         DRV_LOG(ERR, "TD allocation failure");
 973                         err = ENOMEM;
 974                         goto error;
 975                 }
 976                 tis_attr.transport_domain = sh->td->id;
 977                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
 978                 if (!sh->tis) {
 979                         DRV_LOG(ERR, "TIS allocation failure");
 980                         err = ENOMEM;
 981                         goto error;
 982                 }
 983                 err = mlx5_alloc_rxtx_uars(sh, config);
 984                 if (err)
 985                         goto error;
 986                 MLX5_ASSERT(sh->tx_uar);
 987                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
 988
 989                 MLX5_ASSERT(sh->devx_rx_uar);
 990                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
 991         }
 992 #ifndef RTE_ARCH_64
 993         /* Initialize UAR access locks for 32bit implementations. */
 994         rte_spinlock_init(&sh->uar_lock_cq);
 995         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
 996                 rte_spinlock_init(&sh->uar_lock[i]);
 997 #endif
 998         /*
 999          * Once the device is added to the list of memory event
1000          * callback, its global MR cache table cannot be expanded
1001          * on the fly because of deadlock. If it overflows, lookup
1002          * should be done by searching MR list linearly, which is slow.
1003          *
1004          * At this point the device is not added to the memory
1005          * event list yet, context is just being created.
1006          */
1007         err = mlx5_mr_btree_init(&sh->share_cache.cache,
1008                                  MLX5_MR_BTREE_CACHE_N * 2,
1009                                  spawn->pci_dev->device.numa_node);
1010         if (err) {
1011                 err = rte_errno;
1012                 goto error;
1013         }
1014         mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
1015                               &sh->share_cache.dereg_mr_cb);
1016         mlx5_os_dev_shared_handler_install(sh);
1017         sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
1018         if (!sh->cnt_id_tbl) {
1019                 err = rte_errno;
1020                 goto error;
1021         }
1022         if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1023                 err = mlx5_flow_os_init_workspace_once();
1024                 if (err)
1025                         goto error;
1026         }
1027         mlx5_flow_aging_init(sh);
1028         mlx5_flow_counters_mng_init(sh);
1029         mlx5_flow_ipool_create(sh, config);
1030         /* Add device to memory callback list. */
1031         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1032         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1033                          sh, mem_event_cb);
1034         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1035         /* Add context to the global device list. */
1036         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1037         rte_spinlock_init(&sh->geneve_tlv_opt_sl);
1038 exit:
1039         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1040         return sh;
1041 error:
1042         pthread_mutex_destroy(&sh->txpp.mutex);
1043         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1044         MLX5_ASSERT(sh);
1045         if (sh->cnt_id_tbl)
1046                 mlx5_l3t_destroy(sh->cnt_id_tbl);
1047         if (sh->tis)
1048                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1049         if (sh->td)
1050                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1051         if (sh->devx_rx_uar)
1052                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1053         if (sh->tx_uar)
1054                 mlx5_glue->devx_free_uar(sh->tx_uar);
1055         if (sh->pd)
1056                 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1057         if (sh->ctx)
1058                 claim_zero(mlx5_glue->close_device(sh->ctx));
1059         mlx5_free(sh);
1060         MLX5_ASSERT(err > 0);
1061         rte_errno = err;
1062         return NULL;
1063 }
1064
1065 /**
1066  * Free shared IB device context. Decrement counter and if zero free
1067  * all allocated resources and close handles.
1068  *
1069  * @param[in] sh
1070  *   Pointer to mlx5_dev_ctx_shared object to free
1071  */
1072 void
1073 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1074 {
1075         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1076 #ifdef RTE_LIBRTE_MLX5_DEBUG
1077         /* Check the object presence in the list. */
1078         struct mlx5_dev_ctx_shared *lctx;
1079
1080         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1081                 if (lctx == sh)
1082                         break;
1083         MLX5_ASSERT(lctx);
1084         if (lctx != sh) {
1085                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1086                 goto exit;
1087         }
1088 #endif
1089         MLX5_ASSERT(sh);
1090         MLX5_ASSERT(sh->refcnt);
1091         /* Secondary process should not free the shared context. */
1092         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1093         if (--sh->refcnt)
1094                 goto exit;
1095         /* Remove from memory callback device list. */
1096         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1097         LIST_REMOVE(sh, mem_event_cb);
1098         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1099         /* Release created Memory Regions. */
1100         mlx5_mr_release_cache(&sh->share_cache);
1101         /* Remove context from the global device list. */
1102         LIST_REMOVE(sh, next);
1103         /* Release flow workspaces objects on the last device. */
1104         if (LIST_EMPTY(&mlx5_dev_ctx_list))
1105                 mlx5_flow_os_release_workspace();
1106         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1107         /*
1108          *  Ensure there is no async event handler installed.
1109          *  Only primary process handles async device events.
1110          **/
1111         mlx5_flow_counters_mng_close(sh);
1112         if (sh->aso_age_mng) {
1113                 mlx5_flow_aso_age_mng_close(sh);
1114                 sh->aso_age_mng = NULL;
1115         }
1116         mlx5_flow_ipool_destroy(sh);
1117         mlx5_os_dev_shared_handler_uninstall(sh);
1118         if (sh->cnt_id_tbl) {
1119                 mlx5_l3t_destroy(sh->cnt_id_tbl);
1120                 sh->cnt_id_tbl = NULL;
1121         }
1122         if (sh->tx_uar) {
1123                 mlx5_glue->devx_free_uar(sh->tx_uar);
1124                 sh->tx_uar = NULL;
1125         }
1126         if (sh->pd)
1127                 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1128         if (sh->tis)
1129                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1130         if (sh->td)
1131                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1132         if (sh->devx_rx_uar)
1133                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1134         if (sh->ctx)
1135                 claim_zero(mlx5_glue->close_device(sh->ctx));
1136         MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
1137         pthread_mutex_destroy(&sh->txpp.mutex);
1138         mlx5_free(sh);
1139         return;
1140 exit:
1141         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1142 }
1143
1144 /**
1145  * Destroy table hash list.
1146  *
1147  * @param[in] priv
1148  *   Pointer to the private device data structure.
1149  */
1150 void
1151 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1152 {
1153         struct mlx5_dev_ctx_shared *sh = priv->sh;
1154
1155         if (!sh->flow_tbls)
1156                 return;
1157         mlx5_hlist_destroy(sh->flow_tbls);
1158 }
1159
1160 /**
1161  * Initialize flow table hash list and create the root tables entry
1162  * for each domain.
1163  *
1164  * @param[in] priv
1165  *   Pointer to the private device data structure.
1166  *
1167  * @return
1168  *   Zero on success, positive error code otherwise.
1169  */
1170 int
1171 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1172 {
1173         int err = 0;
1174         /* Tables are only used in DV and DR modes. */
1175 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1176         struct mlx5_dev_ctx_shared *sh = priv->sh;
1177         char s[MLX5_HLIST_NAMESIZE];
1178
1179         MLX5_ASSERT(sh);
1180         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1181         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1182                                           0, 0, flow_dv_tbl_create_cb,
1183                                           flow_dv_tbl_match_cb,
1184                                           flow_dv_tbl_remove_cb);
1185         if (!sh->flow_tbls) {
1186                 DRV_LOG(ERR, "flow tables with hash creation failed.");
1187                 err = ENOMEM;
1188                 return err;
1189         }
1190         sh->flow_tbls->ctx = sh;
1191 #ifndef HAVE_MLX5DV_DR
1192         struct rte_flow_error error;
1193         struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1194
1195         /*
1196          * In case we have not DR support, the zero tables should be created
1197          * because DV expect to see them even if they cannot be created by
1198          * RDMA-CORE.
1199          */
1200         if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0, NULL, 0, 1, &error) ||
1201             !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0, NULL, 0, 1, &error) ||
1202             !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0, NULL, 0, 1, &error)) {
1203                 err = ENOMEM;
1204                 goto error;
1205         }
1206         return err;
1207 error:
1208         mlx5_free_table_hash_list(priv);
1209 #endif /* HAVE_MLX5DV_DR */
1210 #endif
1211         return err;
1212 }
1213
1214 /**
1215  * Retrieve integer value from environment variable.
1216  *
1217  * @param[in] name
1218  *   Environment variable name.
1219  *
1220  * @return
1221  *   Integer value, 0 if the variable is not set.
1222  */
1223 int
1224 mlx5_getenv_int(const char *name)
1225 {
1226         const char *val = getenv(name);
1227
1228         if (val == NULL)
1229                 return 0;
1230         return atoi(val);
1231 }
1232
1233 /**
1234  * DPDK callback to add udp tunnel port
1235  *
1236  * @param[in] dev
1237  *   A pointer to eth_dev
1238  * @param[in] udp_tunnel
1239  *   A pointer to udp tunnel
1240  *
1241  * @return
1242  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1243  */
1244 int
1245 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1246                          struct rte_eth_udp_tunnel *udp_tunnel)
1247 {
1248         MLX5_ASSERT(udp_tunnel != NULL);
1249         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1250             udp_tunnel->udp_port == 4789)
1251                 return 0;
1252         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1253             udp_tunnel->udp_port == 4790)
1254                 return 0;
1255         return -ENOTSUP;
1256 }
1257
1258 /**
1259  * Initialize process private data structure.
1260  *
1261  * @param dev
1262  *   Pointer to Ethernet device structure.
1263  *
1264  * @return
1265  *   0 on success, a negative errno value otherwise and rte_errno is set.
1266  */
1267 int
1268 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1269 {
1270         struct mlx5_priv *priv = dev->data->dev_private;
1271         struct mlx5_proc_priv *ppriv;
1272         size_t ppriv_size;
1273
1274         /*
1275          * UAR register table follows the process private structure. BlueFlame
1276          * registers for Tx queues are stored in the table.
1277          */
1278         ppriv_size =
1279                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1280         ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
1281                             RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1282         if (!ppriv) {
1283                 rte_errno = ENOMEM;
1284                 return -rte_errno;
1285         }
1286         ppriv->uar_table_sz = priv->txqs_n;
1287         dev->process_private = ppriv;
1288         return 0;
1289 }
1290
1291 /**
1292  * Un-initialize process private data structure.
1293  *
1294  * @param dev
1295  *   Pointer to Ethernet device structure.
1296  */
1297 void
1298 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1299 {
1300         if (!dev->process_private)
1301                 return;
1302         mlx5_free(dev->process_private);
1303         dev->process_private = NULL;
1304 }
1305
1306 /**
1307  * DPDK callback to close the device.
1308  *
1309  * Destroy all queues and objects, free memory.
1310  *
1311  * @param dev
1312  *   Pointer to Ethernet device structure.
1313  */
1314 int
1315 mlx5_dev_close(struct rte_eth_dev *dev)
1316 {
1317         struct mlx5_priv *priv = dev->data->dev_private;
1318         unsigned int i;
1319         int ret;
1320
1321         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1322                 /* Check if process_private released. */
1323                 if (!dev->process_private)
1324                         return 0;
1325                 mlx5_tx_uar_uninit_secondary(dev);
1326                 mlx5_proc_priv_uninit(dev);
1327                 rte_eth_dev_release_port(dev);
1328                 return 0;
1329         }
1330         if (!priv->sh)
1331                 return 0;
1332         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1333                 dev->data->port_id,
1334                 ((priv->sh->ctx != NULL) ?
1335                 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1336         /*
1337          * If default mreg copy action is removed at the stop stage,
1338          * the search will return none and nothing will be done anymore.
1339          */
1340         mlx5_flow_stop_default(dev);
1341         mlx5_traffic_disable(dev);
1342         /*
1343          * If all the flows are already flushed in the device stop stage,
1344          * then this will return directly without any action.
1345          */
1346         mlx5_flow_list_flush(dev, &priv->flows, true);
1347         mlx5_action_handle_flush(dev);
1348         mlx5_flow_meter_flush(dev, NULL);
1349         /* Prevent crashes when queues are still in use. */
1350         dev->rx_pkt_burst = removed_rx_burst;
1351         dev->tx_pkt_burst = removed_tx_burst;
1352         rte_wmb();
1353         /* Disable datapath on secondary process. */
1354         mlx5_mp_os_req_stop_rxtx(dev);
1355         /* Free the eCPRI flex parser resource. */
1356         mlx5_flex_parser_ecpri_release(dev);
1357         if (priv->rxqs != NULL) {
1358                 /* XXX race condition if mlx5_rx_burst() is still running. */
1359                 rte_delay_us_sleep(1000);
1360                 for (i = 0; (i != priv->rxqs_n); ++i)
1361                         mlx5_rxq_release(dev, i);
1362                 priv->rxqs_n = 0;
1363                 priv->rxqs = NULL;
1364         }
1365         if (priv->txqs != NULL) {
1366                 /* XXX race condition if mlx5_tx_burst() is still running. */
1367                 rte_delay_us_sleep(1000);
1368                 for (i = 0; (i != priv->txqs_n); ++i)
1369                         mlx5_txq_release(dev, i);
1370                 priv->txqs_n = 0;
1371                 priv->txqs = NULL;
1372         }
1373         mlx5_proc_priv_uninit(dev);
1374         if (priv->q_counters) {
1375                 mlx5_devx_cmd_destroy(priv->q_counters);
1376                 priv->q_counters = NULL;
1377         }
1378         if (priv->drop_queue.hrxq)
1379                 mlx5_drop_action_destroy(dev);
1380         if (priv->mreg_cp_tbl)
1381                 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1382         mlx5_mprq_free_mp(dev);
1383         mlx5_os_free_shared_dr(priv);
1384         if (priv->rss_conf.rss_key != NULL)
1385                 mlx5_free(priv->rss_conf.rss_key);
1386         if (priv->reta_idx != NULL)
1387                 mlx5_free(priv->reta_idx);
1388         if (priv->config.vf)
1389                 mlx5_os_mac_addr_flush(dev);
1390         if (priv->nl_socket_route >= 0)
1391                 close(priv->nl_socket_route);
1392         if (priv->nl_socket_rdma >= 0)
1393                 close(priv->nl_socket_rdma);
1394         if (priv->vmwa_context)
1395                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1396         ret = mlx5_hrxq_verify(dev);
1397         if (ret)
1398                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1399                         dev->data->port_id);
1400         ret = mlx5_ind_table_obj_verify(dev);
1401         if (ret)
1402                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1403                         dev->data->port_id);
1404         ret = mlx5_rxq_obj_verify(dev);
1405         if (ret)
1406                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1407                         dev->data->port_id);
1408         ret = mlx5_rxq_verify(dev);
1409         if (ret)
1410                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1411                         dev->data->port_id);
1412         ret = mlx5_txq_obj_verify(dev);
1413         if (ret)
1414                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1415                         dev->data->port_id);
1416         ret = mlx5_txq_verify(dev);
1417         if (ret)
1418                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1419                         dev->data->port_id);
1420         ret = mlx5_flow_verify(dev);
1421         if (ret)
1422                 DRV_LOG(WARNING, "port %u some flows still remain",
1423                         dev->data->port_id);
1424         mlx5_cache_list_destroy(&priv->hrxqs);
1425         /*
1426          * Free the shared context in last turn, because the cleanup
1427          * routines above may use some shared fields, like
1428          * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1429          * ifindex if Netlink fails.
1430          */
1431         mlx5_free_shared_dev_ctx(priv->sh);
1432         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1433                 unsigned int c = 0;
1434                 uint16_t port_id;
1435
1436                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1437                         struct mlx5_priv *opriv =
1438                                 rte_eth_devices[port_id].data->dev_private;
1439
1440                         if (!opriv ||
1441                             opriv->domain_id != priv->domain_id ||
1442                             &rte_eth_devices[port_id] == dev)
1443                                 continue;
1444                         ++c;
1445                         break;
1446                 }
1447                 if (!c)
1448                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1449         }
1450         memset(priv, 0, sizeof(*priv));
1451         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1452         /*
1453          * Reset mac_addrs to NULL such that it is not freed as part of
1454          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1455          * it is freed when dev_private is freed.
1456          */
1457         dev->data->mac_addrs = NULL;
1458         return 0;
1459 }
1460
1461 const struct eth_dev_ops mlx5_dev_ops = {
1462         .dev_configure = mlx5_dev_configure,
1463         .dev_start = mlx5_dev_start,
1464         .dev_stop = mlx5_dev_stop,
1465         .dev_set_link_down = mlx5_set_link_down,
1466         .dev_set_link_up = mlx5_set_link_up,
1467         .dev_close = mlx5_dev_close,
1468         .promiscuous_enable = mlx5_promiscuous_enable,
1469         .promiscuous_disable = mlx5_promiscuous_disable,
1470         .allmulticast_enable = mlx5_allmulticast_enable,
1471         .allmulticast_disable = mlx5_allmulticast_disable,
1472         .link_update = mlx5_link_update,
1473         .stats_get = mlx5_stats_get,
1474         .stats_reset = mlx5_stats_reset,
1475         .xstats_get = mlx5_xstats_get,
1476         .xstats_reset = mlx5_xstats_reset,
1477         .xstats_get_names = mlx5_xstats_get_names,
1478         .fw_version_get = mlx5_fw_version_get,
1479         .dev_infos_get = mlx5_dev_infos_get,
1480         .representor_info_get = mlx5_representor_info_get,
1481         .read_clock = mlx5_txpp_read_clock,
1482         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1483         .vlan_filter_set = mlx5_vlan_filter_set,
1484         .rx_queue_setup = mlx5_rx_queue_setup,
1485         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1486         .tx_queue_setup = mlx5_tx_queue_setup,
1487         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1488         .rx_queue_release = mlx5_rx_queue_release,
1489         .tx_queue_release = mlx5_tx_queue_release,
1490         .rx_queue_start = mlx5_rx_queue_start,
1491         .rx_queue_stop = mlx5_rx_queue_stop,
1492         .tx_queue_start = mlx5_tx_queue_start,
1493         .tx_queue_stop = mlx5_tx_queue_stop,
1494         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1495         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1496         .mac_addr_remove = mlx5_mac_addr_remove,
1497         .mac_addr_add = mlx5_mac_addr_add,
1498         .mac_addr_set = mlx5_mac_addr_set,
1499         .set_mc_addr_list = mlx5_set_mc_addr_list,
1500         .mtu_set = mlx5_dev_set_mtu,
1501         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1502         .vlan_offload_set = mlx5_vlan_offload_set,
1503         .reta_update = mlx5_dev_rss_reta_update,
1504         .reta_query = mlx5_dev_rss_reta_query,
1505         .rss_hash_update = mlx5_rss_hash_update,
1506         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1507         .flow_ops_get = mlx5_flow_ops_get,
1508         .rxq_info_get = mlx5_rxq_info_get,
1509         .txq_info_get = mlx5_txq_info_get,
1510         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1511         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1512         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1513         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1514         .is_removed = mlx5_is_removed,
1515         .udp_tunnel_port_add  = mlx5_udp_tunnel_port_add,
1516         .get_module_info = mlx5_get_module_info,
1517         .get_module_eeprom = mlx5_get_module_eeprom,
1518         .hairpin_cap_get = mlx5_hairpin_cap_get,
1519         .mtr_ops_get = mlx5_flow_meter_ops_get,
1520         .hairpin_bind = mlx5_hairpin_bind,
1521         .hairpin_unbind = mlx5_hairpin_unbind,
1522         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1523         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1524         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1525         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1526 };
1527
1528 /* Available operations from secondary process. */
1529 const struct eth_dev_ops mlx5_dev_sec_ops = {
1530         .stats_get = mlx5_stats_get,
1531         .stats_reset = mlx5_stats_reset,
1532         .xstats_get = mlx5_xstats_get,
1533         .xstats_reset = mlx5_xstats_reset,
1534         .xstats_get_names = mlx5_xstats_get_names,
1535         .fw_version_get = mlx5_fw_version_get,
1536         .dev_infos_get = mlx5_dev_infos_get,
1537         .read_clock = mlx5_txpp_read_clock,
1538         .rx_queue_start = mlx5_rx_queue_start,
1539         .rx_queue_stop = mlx5_rx_queue_stop,
1540         .tx_queue_start = mlx5_tx_queue_start,
1541         .tx_queue_stop = mlx5_tx_queue_stop,
1542         .rxq_info_get = mlx5_rxq_info_get,
1543         .txq_info_get = mlx5_txq_info_get,
1544         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1545         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1546         .get_module_info = mlx5_get_module_info,
1547         .get_module_eeprom = mlx5_get_module_eeprom,
1548 };
1549
1550 /* Available operations in flow isolated mode. */
1551 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1552         .dev_configure = mlx5_dev_configure,
1553         .dev_start = mlx5_dev_start,
1554         .dev_stop = mlx5_dev_stop,
1555         .dev_set_link_down = mlx5_set_link_down,
1556         .dev_set_link_up = mlx5_set_link_up,
1557         .dev_close = mlx5_dev_close,
1558         .promiscuous_enable = mlx5_promiscuous_enable,
1559         .promiscuous_disable = mlx5_promiscuous_disable,
1560         .allmulticast_enable = mlx5_allmulticast_enable,
1561         .allmulticast_disable = mlx5_allmulticast_disable,
1562         .link_update = mlx5_link_update,
1563         .stats_get = mlx5_stats_get,
1564         .stats_reset = mlx5_stats_reset,
1565         .xstats_get = mlx5_xstats_get,
1566         .xstats_reset = mlx5_xstats_reset,
1567         .xstats_get_names = mlx5_xstats_get_names,
1568         .fw_version_get = mlx5_fw_version_get,
1569         .dev_infos_get = mlx5_dev_infos_get,
1570         .read_clock = mlx5_txpp_read_clock,
1571         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1572         .vlan_filter_set = mlx5_vlan_filter_set,
1573         .rx_queue_setup = mlx5_rx_queue_setup,
1574         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1575         .tx_queue_setup = mlx5_tx_queue_setup,
1576         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1577         .rx_queue_release = mlx5_rx_queue_release,
1578         .tx_queue_release = mlx5_tx_queue_release,
1579         .rx_queue_start = mlx5_rx_queue_start,
1580         .rx_queue_stop = mlx5_rx_queue_stop,
1581         .tx_queue_start = mlx5_tx_queue_start,
1582         .tx_queue_stop = mlx5_tx_queue_stop,
1583         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1584         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1585         .mac_addr_remove = mlx5_mac_addr_remove,
1586         .mac_addr_add = mlx5_mac_addr_add,
1587         .mac_addr_set = mlx5_mac_addr_set,
1588         .set_mc_addr_list = mlx5_set_mc_addr_list,
1589         .mtu_set = mlx5_dev_set_mtu,
1590         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1591         .vlan_offload_set = mlx5_vlan_offload_set,
1592         .flow_ops_get = mlx5_flow_ops_get,
1593         .rxq_info_get = mlx5_rxq_info_get,
1594         .txq_info_get = mlx5_txq_info_get,
1595         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1596         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1597         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1598         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1599         .is_removed = mlx5_is_removed,
1600         .get_module_info = mlx5_get_module_info,
1601         .get_module_eeprom = mlx5_get_module_eeprom,
1602         .hairpin_cap_get = mlx5_hairpin_cap_get,
1603         .mtr_ops_get = mlx5_flow_meter_ops_get,
1604         .hairpin_bind = mlx5_hairpin_bind,
1605         .hairpin_unbind = mlx5_hairpin_unbind,
1606         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1607         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1608         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1609         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1610 };
1611
1612 /**
1613  * Verify and store value for device argument.
1614  *
1615  * @param[in] key
1616  *   Key argument to verify.
1617  * @param[in] val
1618  *   Value associated with key.
1619  * @param opaque
1620  *   User data.
1621  *
1622  * @return
1623  *   0 on success, a negative errno value otherwise and rte_errno is set.
1624  */
1625 static int
1626 mlx5_args_check(const char *key, const char *val, void *opaque)
1627 {
1628         struct mlx5_dev_config *config = opaque;
1629         unsigned long mod;
1630         signed long tmp;
1631
1632         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1633         if (!strcmp(MLX5_REPRESENTOR, key))
1634                 return 0;
1635         errno = 0;
1636         tmp = strtol(val, NULL, 0);
1637         if (errno) {
1638                 rte_errno = errno;
1639                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1640                 return -rte_errno;
1641         }
1642         if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1643                 /* Negative values are acceptable for some keys only. */
1644                 rte_errno = EINVAL;
1645                 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1646                 return -rte_errno;
1647         }
1648         mod = tmp >= 0 ? tmp : -tmp;
1649         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1650                 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1651                         DRV_LOG(ERR, "invalid CQE compression "
1652                                      "format parameter");
1653                         rte_errno = EINVAL;
1654                         return -rte_errno;
1655                 }
1656                 config->cqe_comp = !!tmp;
1657                 config->cqe_comp_fmt = tmp;
1658         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1659                 config->hw_padding = !!tmp;
1660         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1661                 config->mprq.enabled = !!tmp;
1662         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1663                 config->mprq.stride_num_n = tmp;
1664         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1665                 config->mprq.stride_size_n = tmp;
1666         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1667                 config->mprq.max_memcpy_len = tmp;
1668         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1669                 config->mprq.min_rxqs_num = tmp;
1670         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1671                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1672                                  " converted to txq_inline_max", key);
1673                 config->txq_inline_max = tmp;
1674         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1675                 config->txq_inline_max = tmp;
1676         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1677                 config->txq_inline_min = tmp;
1678         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1679                 config->txq_inline_mpw = tmp;
1680         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1681                 config->txqs_inline = tmp;
1682         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1683                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1684         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1685                 config->mps = !!tmp;
1686         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1687                 if (tmp != MLX5_TXDB_CACHED &&
1688                     tmp != MLX5_TXDB_NCACHED &&
1689                     tmp != MLX5_TXDB_HEURISTIC) {
1690                         DRV_LOG(ERR, "invalid Tx doorbell "
1691                                      "mapping parameter");
1692                         rte_errno = EINVAL;
1693                         return -rte_errno;
1694                 }
1695                 config->dbnc = tmp;
1696         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1697                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1698         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1699                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1700                                  " converted to txq_inline_mpw", key);
1701                 config->txq_inline_mpw = tmp;
1702         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1703                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1704         } else if (strcmp(MLX5_TX_PP, key) == 0) {
1705                 if (!mod) {
1706                         DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1707                         rte_errno = EINVAL;
1708                         return -rte_errno;
1709                 }
1710                 config->tx_pp = tmp;
1711         } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1712                 config->tx_skew = tmp;
1713         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1714                 config->rx_vec_en = !!tmp;
1715         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1716                 config->l3_vxlan_en = !!tmp;
1717         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1718                 config->vf_nl_en = !!tmp;
1719         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1720                 config->dv_esw_en = !!tmp;
1721         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1722                 config->dv_flow_en = !!tmp;
1723         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1724                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1725                     tmp != MLX5_XMETA_MODE_META16 &&
1726                     tmp != MLX5_XMETA_MODE_META32 &&
1727                     tmp != MLX5_XMETA_MODE_MISS_INFO) {
1728                         DRV_LOG(ERR, "invalid extensive "
1729                                      "metadata parameter");
1730                         rte_errno = EINVAL;
1731                         return -rte_errno;
1732                 }
1733                 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
1734                         config->dv_xmeta_en = tmp;
1735                 else
1736                         config->dv_miss_info = 1;
1737         } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1738                 config->lacp_by_user = !!tmp;
1739         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1740                 config->mr_ext_memseg_en = !!tmp;
1741         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1742                 config->max_dump_files_num = tmp;
1743         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1744                 config->lro.timeout = tmp;
1745         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1746                 DRV_LOG(DEBUG, "class argument is %s.", val);
1747         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1748                 config->log_hp_size = tmp;
1749         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1750                 if (tmp != MLX5_RCM_NONE &&
1751                     tmp != MLX5_RCM_LIGHT &&
1752                     tmp != MLX5_RCM_AGGR) {
1753                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1754                         rte_errno = EINVAL;
1755                         return -rte_errno;
1756                 }
1757                 config->reclaim_mode = tmp;
1758         } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1759                 config->sys_mem_en = !!tmp;
1760         } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1761                 config->decap_en = !!tmp;
1762         } else {
1763                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1764                 rte_errno = EINVAL;
1765                 return -rte_errno;
1766         }
1767         return 0;
1768 }
1769
1770 /**
1771  * Parse device parameters.
1772  *
1773  * @param config
1774  *   Pointer to device configuration structure.
1775  * @param devargs
1776  *   Device arguments structure.
1777  *
1778  * @return
1779  *   0 on success, a negative errno value otherwise and rte_errno is set.
1780  */
1781 int
1782 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1783 {
1784         const char **params = (const char *[]){
1785                 MLX5_RXQ_CQE_COMP_EN,
1786                 MLX5_RXQ_PKT_PAD_EN,
1787                 MLX5_RX_MPRQ_EN,
1788                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1789                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1790                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1791                 MLX5_RXQS_MIN_MPRQ,
1792                 MLX5_TXQ_INLINE,
1793                 MLX5_TXQ_INLINE_MIN,
1794                 MLX5_TXQ_INLINE_MAX,
1795                 MLX5_TXQ_INLINE_MPW,
1796                 MLX5_TXQS_MIN_INLINE,
1797                 MLX5_TXQS_MAX_VEC,
1798                 MLX5_TXQ_MPW_EN,
1799                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1800                 MLX5_TXQ_MAX_INLINE_LEN,
1801                 MLX5_TX_DB_NC,
1802                 MLX5_TX_PP,
1803                 MLX5_TX_SKEW,
1804                 MLX5_TX_VEC_EN,
1805                 MLX5_RX_VEC_EN,
1806                 MLX5_L3_VXLAN_EN,
1807                 MLX5_VF_NL_EN,
1808                 MLX5_DV_ESW_EN,
1809                 MLX5_DV_FLOW_EN,
1810                 MLX5_DV_XMETA_EN,
1811                 MLX5_LACP_BY_USER,
1812                 MLX5_MR_EXT_MEMSEG_EN,
1813                 MLX5_REPRESENTOR,
1814                 MLX5_MAX_DUMP_FILES_NUM,
1815                 MLX5_LRO_TIMEOUT_USEC,
1816                 MLX5_CLASS_ARG_NAME,
1817                 MLX5_HP_BUF_SIZE,
1818                 MLX5_RECLAIM_MEM,
1819                 MLX5_SYS_MEM_EN,
1820                 MLX5_DECAP_EN,
1821                 NULL,
1822         };
1823         struct rte_kvargs *kvlist;
1824         int ret = 0;
1825         int i;
1826
1827         if (devargs == NULL)
1828                 return 0;
1829         /* Following UGLY cast is done to pass checkpatch. */
1830         kvlist = rte_kvargs_parse(devargs->args, params);
1831         if (kvlist == NULL) {
1832                 rte_errno = EINVAL;
1833                 return -rte_errno;
1834         }
1835         /* Process parameters. */
1836         for (i = 0; (params[i] != NULL); ++i) {
1837                 if (rte_kvargs_count(kvlist, params[i])) {
1838                         ret = rte_kvargs_process(kvlist, params[i],
1839                                                  mlx5_args_check, config);
1840                         if (ret) {
1841                                 rte_errno = EINVAL;
1842                                 rte_kvargs_free(kvlist);
1843                                 return -rte_errno;
1844                         }
1845                 }
1846         }
1847         rte_kvargs_free(kvlist);
1848         return 0;
1849 }
1850
1851 /**
1852  * Configures the minimal amount of data to inline into WQE
1853  * while sending packets.
1854  *
1855  * - the txq_inline_min has the maximal priority, if this
1856  *   key is specified in devargs
1857  * - if DevX is enabled the inline mode is queried from the
1858  *   device (HCA attributes and NIC vport context if needed).
1859  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1860  *   and none (0 bytes) for other NICs
1861  *
1862  * @param spawn
1863  *   Verbs device parameters (name, port, switch_info) to spawn.
1864  * @param config
1865  *   Device configuration parameters.
1866  */
1867 void
1868 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1869                     struct mlx5_dev_config *config)
1870 {
1871         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1872                 /* Application defines size of inlined data explicitly. */
1873                 switch (spawn->pci_dev->id.device_id) {
1874                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1875                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1876                         if (config->txq_inline_min <
1877                                        (int)MLX5_INLINE_HSIZE_L2) {
1878                                 DRV_LOG(DEBUG,
1879                                         "txq_inline_mix aligned to minimal"
1880                                         " ConnectX-4 required value %d",
1881                                         (int)MLX5_INLINE_HSIZE_L2);
1882                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1883                         }
1884                         break;
1885                 }
1886                 goto exit;
1887         }
1888         if (config->hca_attr.eth_net_offloads) {
1889                 /* We have DevX enabled, inline mode queried successfully. */
1890                 switch (config->hca_attr.wqe_inline_mode) {
1891                 case MLX5_CAP_INLINE_MODE_L2:
1892                         /* outer L2 header must be inlined. */
1893                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1894                         goto exit;
1895                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1896                         /* No inline data are required by NIC. */
1897                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1898                         config->hw_vlan_insert =
1899                                 config->hca_attr.wqe_vlan_insert;
1900                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1901                         goto exit;
1902                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1903                         /* inline mode is defined by NIC vport context. */
1904                         if (!config->hca_attr.eth_virt)
1905                                 break;
1906                         switch (config->hca_attr.vport_inline_mode) {
1907                         case MLX5_INLINE_MODE_NONE:
1908                                 config->txq_inline_min =
1909                                         MLX5_INLINE_HSIZE_NONE;
1910                                 goto exit;
1911                         case MLX5_INLINE_MODE_L2:
1912                                 config->txq_inline_min =
1913                                         MLX5_INLINE_HSIZE_L2;
1914                                 goto exit;
1915                         case MLX5_INLINE_MODE_IP:
1916                                 config->txq_inline_min =
1917                                         MLX5_INLINE_HSIZE_L3;
1918                                 goto exit;
1919                         case MLX5_INLINE_MODE_TCP_UDP:
1920                                 config->txq_inline_min =
1921                                         MLX5_INLINE_HSIZE_L4;
1922                                 goto exit;
1923                         case MLX5_INLINE_MODE_INNER_L2:
1924                                 config->txq_inline_min =
1925                                         MLX5_INLINE_HSIZE_INNER_L2;
1926                                 goto exit;
1927                         case MLX5_INLINE_MODE_INNER_IP:
1928                                 config->txq_inline_min =
1929                                         MLX5_INLINE_HSIZE_INNER_L3;
1930                                 goto exit;
1931                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
1932                                 config->txq_inline_min =
1933                                         MLX5_INLINE_HSIZE_INNER_L4;
1934                                 goto exit;
1935                         }
1936                 }
1937         }
1938         /*
1939          * We get here if we are unable to deduce
1940          * inline data size with DevX. Try PCI ID
1941          * to determine old NICs.
1942          */
1943         switch (spawn->pci_dev->id.device_id) {
1944         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1945         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1946         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1947         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1948                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1949                 config->hw_vlan_insert = 0;
1950                 break;
1951         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1952         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1953         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1954         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1955                 /*
1956                  * These NICs support VLAN insertion from WQE and
1957                  * report the wqe_vlan_insert flag. But there is the bug
1958                  * and PFC control may be broken, so disable feature.
1959                  */
1960                 config->hw_vlan_insert = 0;
1961                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1962                 break;
1963         default:
1964                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1965                 break;
1966         }
1967 exit:
1968         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1969 }
1970
1971 /**
1972  * Configures the metadata mask fields in the shared context.
1973  *
1974  * @param [in] dev
1975  *   Pointer to Ethernet device.
1976  */
1977 void
1978 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1979 {
1980         struct mlx5_priv *priv = dev->data->dev_private;
1981         struct mlx5_dev_ctx_shared *sh = priv->sh;
1982         uint32_t meta, mark, reg_c0;
1983
1984         reg_c0 = ~priv->vport_meta_mask;
1985         switch (priv->config.dv_xmeta_en) {
1986         case MLX5_XMETA_MODE_LEGACY:
1987                 meta = UINT32_MAX;
1988                 mark = MLX5_FLOW_MARK_MASK;
1989                 break;
1990         case MLX5_XMETA_MODE_META16:
1991                 meta = reg_c0 >> rte_bsf32(reg_c0);
1992                 mark = MLX5_FLOW_MARK_MASK;
1993                 break;
1994         case MLX5_XMETA_MODE_META32:
1995                 meta = UINT32_MAX;
1996                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1997                 break;
1998         default:
1999                 meta = 0;
2000                 mark = 0;
2001                 MLX5_ASSERT(false);
2002                 break;
2003         }
2004         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2005                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
2006                                  sh->dv_mark_mask, mark);
2007         else
2008                 sh->dv_mark_mask = mark;
2009         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2010                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
2011                                  sh->dv_meta_mask, meta);
2012         else
2013                 sh->dv_meta_mask = meta;
2014         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2015                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
2016                                  sh->dv_meta_mask, reg_c0);
2017         else
2018                 sh->dv_regc0_mask = reg_c0;
2019         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2020         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2021         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2022         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2023 }
2024
2025 int
2026 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2027 {
2028         static const char *const dynf_names[] = {
2029                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2030                 RTE_MBUF_DYNFLAG_METADATA_NAME,
2031                 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
2032         };
2033         unsigned int i;
2034
2035         if (n < RTE_DIM(dynf_names))
2036                 return -ENOMEM;
2037         for (i = 0; i < RTE_DIM(dynf_names); i++) {
2038                 if (names[i] == NULL)
2039                         return -EINVAL;
2040                 strcpy(names[i], dynf_names[i]);
2041         }
2042         return RTE_DIM(dynf_names);
2043 }
2044
2045 /**
2046  * Comparison callback to sort device data.
2047  *
2048  * This is meant to be used with qsort().
2049  *
2050  * @param a[in]
2051  *   Pointer to pointer to first data object.
2052  * @param b[in]
2053  *   Pointer to pointer to second data object.
2054  *
2055  * @return
2056  *   0 if both objects are equal, less than 0 if the first argument is less
2057  *   than the second, greater than 0 otherwise.
2058  */
2059 int
2060 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2061                               struct mlx5_dev_config *config)
2062 {
2063         struct mlx5_dev_ctx_shared *sh = priv->sh;
2064         struct mlx5_dev_config *sh_conf = NULL;
2065         uint16_t port_id;
2066
2067         MLX5_ASSERT(sh);
2068         /* Nothing to compare for the single/first device. */
2069         if (sh->refcnt == 1)
2070                 return 0;
2071         /* Find the device with shared context. */
2072         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2073                 struct mlx5_priv *opriv =
2074                         rte_eth_devices[port_id].data->dev_private;
2075
2076                 if (opriv && opriv != priv && opriv->sh == sh) {
2077                         sh_conf = &opriv->config;
2078                         break;
2079                 }
2080         }
2081         if (!sh_conf)
2082                 return 0;
2083         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2084                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2085                              " for shared %s context", sh->ibdev_name);
2086                 rte_errno = EINVAL;
2087                 return rte_errno;
2088         }
2089         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2090                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2091                              " for shared %s context", sh->ibdev_name);
2092                 rte_errno = EINVAL;
2093                 return rte_errno;
2094         }
2095         return 0;
2096 }
2097
2098 /**
2099  * Look for the ethernet device belonging to mlx5 driver.
2100  *
2101  * @param[in] port_id
2102  *   port_id to start looking for device.
2103  * @param[in] pci_dev
2104  *   Pointer to the hint PCI device. When device is being probed
2105  *   the its siblings (master and preceding representors might
2106  *   not have assigned driver yet (because the mlx5_os_pci_probe()
2107  *   is not completed yet, for this case match on hint PCI
2108  *   device may be used to detect sibling device.
2109  *
2110  * @return
2111  *   port_id of found device, RTE_MAX_ETHPORT if not found.
2112  */
2113 uint16_t
2114 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
2115 {
2116         while (port_id < RTE_MAX_ETHPORTS) {
2117                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2118
2119                 if (dev->state != RTE_ETH_DEV_UNUSED &&
2120                     dev->device &&
2121                     (dev->device == &pci_dev->device ||
2122                      (dev->device->driver &&
2123                      dev->device->driver->name &&
2124                      !strcmp(dev->device->driver->name, MLX5_PCI_DRIVER_NAME))))
2125                         break;
2126                 port_id++;
2127         }
2128         if (port_id >= RTE_MAX_ETHPORTS)
2129                 return RTE_MAX_ETHPORTS;
2130         return port_id;
2131 }
2132
2133 /**
2134  * DPDK callback to remove a PCI device.
2135  *
2136  * This function removes all Ethernet devices belong to a given PCI device.
2137  *
2138  * @param[in] pci_dev
2139  *   Pointer to the PCI device.
2140  *
2141  * @return
2142  *   0 on success, the function cannot fail.
2143  */
2144 static int
2145 mlx5_pci_remove(struct rte_pci_device *pci_dev)
2146 {
2147         uint16_t port_id;
2148         int ret = 0;
2149
2150         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
2151                 /*
2152                  * mlx5_dev_close() is not registered to secondary process,
2153                  * call the close function explicitly for secondary process.
2154                  */
2155                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2156                         ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2157                 else
2158                         ret |= rte_eth_dev_close(port_id);
2159         }
2160         return ret == 0 ? 0 : -EIO;
2161 }
2162
2163 static const struct rte_pci_id mlx5_pci_id_map[] = {
2164         {
2165                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2166                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2167         },
2168         {
2169                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2170                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2171         },
2172         {
2173                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2174                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2175         },
2176         {
2177                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2178                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2179         },
2180         {
2181                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2182                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2183         },
2184         {
2185                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2186                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2187         },
2188         {
2189                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2190                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2191         },
2192         {
2193                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2194                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2195         },
2196         {
2197                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2198                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2199         },
2200         {
2201                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2202                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2203         },
2204         {
2205                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2206                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2207         },
2208         {
2209                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2210                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2211         },
2212         {
2213                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2214                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2215         },
2216         {
2217                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2218                                 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2219         },
2220         {
2221                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2222                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2223         },
2224         {
2225                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2226                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2227         },
2228         {
2229                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2230                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2231         },
2232         {
2233                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2234                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2235         },
2236         {
2237                 .vendor_id = 0
2238         }
2239 };
2240
2241 static struct mlx5_pci_driver mlx5_driver = {
2242         .driver_class = MLX5_CLASS_NET,
2243         .pci_driver = {
2244                 .driver = {
2245                         .name = MLX5_PCI_DRIVER_NAME,
2246                 },
2247                 .id_table = mlx5_pci_id_map,
2248                 .probe = mlx5_os_pci_probe,
2249                 .remove = mlx5_pci_remove,
2250                 .dma_map = mlx5_dma_map,
2251                 .dma_unmap = mlx5_dma_unmap,
2252                 .drv_flags = PCI_DRV_FLAGS,
2253         },
2254 };
2255
2256 /* Initialize driver log type. */
2257 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
2258
2259 /**
2260  * Driver initialization routine.
2261  */
2262 RTE_INIT(rte_mlx5_pmd_init)
2263 {
2264         pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
2265         mlx5_common_init();
2266         /* Build the static tables for Verbs conversion. */
2267         mlx5_set_ptype_table();
2268         mlx5_set_cksum_table();
2269         mlx5_set_swp_types_table();
2270         if (mlx5_glue)
2271                 mlx5_pci_driver_register(&mlx5_driver);
2272 }
2273
2274 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2275 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2276 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");