drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <assert.h>
  10 #include <dlfcn.h>
  11 #include <stdint.h>
  12 #include <stdlib.h>
  13 #include <errno.h>
  14 #include <net/if.h>
  15 #include <sys/mman.h>
  16 #include <linux/rtnetlink.h>
  17
  18 /* Verbs header. */
  19 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  20 #ifdef PEDANTIC
  21 #pragma GCC diagnostic ignored "-Wpedantic"
  22 #endif
  23 #include <infiniband/verbs.h>
  24 #ifdef PEDANTIC
  25 #pragma GCC diagnostic error "-Wpedantic"
  26 #endif
  27
  28 #include <rte_malloc.h>
  29 #include <rte_ethdev_driver.h>
  30 #include <rte_ethdev_pci.h>
  31 #include <rte_pci.h>
  32 #include <rte_bus_pci.h>
  33 #include <rte_common.h>
  34 #include <rte_config.h>
  35 #include <rte_kvargs.h>
  36 #include <rte_rwlock.h>
  37 #include <rte_spinlock.h>
  38 #include <rte_string_fns.h>
  39 #include <rte_alarm.h>
  40
  41 #include "mlx5.h"
  42 #include "mlx5_utils.h"
  43 #include "mlx5_rxtx.h"
  44 #include "mlx5_autoconf.h"
  45 #include "mlx5_defs.h"
  46 #include "mlx5_glue.h"
  47 #include "mlx5_mr.h"
  48 #include "mlx5_flow.h"
  49
  50 /* Device parameter to enable RX completion queue compression. */
  51 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  52
  53 /* Device parameter to enable RX completion entry padding to 128B. */
  54 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
  55
  56 /* Device parameter to enable padding Rx packet to cacheline size. */
  57 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  58
  59 /* Device parameter to enable Multi-Packet Rx queue. */
  60 #define MLX5_RX_MPRQ_EN "mprq_en"
  61
  62 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  63 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  64
  65 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  66 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  67
  68 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  69 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  70
  71 /* Device parameter to configure inline send. Deprecated, ignored.*/
  72 #define MLX5_TXQ_INLINE "txq_inline"
  73
  74 /* Device parameter to limit packet size to inline with ordinary SEND. */
  75 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  76
  77 /* Device parameter to configure minimal data size to inline. */
  78 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  79
  80 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  81 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  82
  83 /*
  84  * Device parameter to configure the number of TX queues threshold for
  85  * enabling inline send.
  86  */
  87 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  88
  89 /*
  90  * Device parameter to configure the number of TX queues threshold for
  91  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  92  */
  93 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  94
  95 /* Device parameter to enable multi-packet send WQEs. */
  96 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  97
  98 /*
  99  * Device parameter to include 2 dsegs in the title WQEBB.
 100  * Deprecated, ignored.
 101  */
 102 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 103
 104 /*
 105  * Device parameter to limit the size of inlining packet.
 106  * Deprecated, ignored.
 107  */
 108 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 109
 110 /*
 111  * Device parameter to enable hardware Tx vector.
 112  * Deprecated, ignored (no vectorized Tx routines anymore).
 113  */
 114 #define MLX5_TX_VEC_EN "tx_vec_en"
 115
 116 /* Device parameter to enable hardware Rx vector. */
 117 #define MLX5_RX_VEC_EN "rx_vec_en"
 118
 119 /* Allow L3 VXLAN flow creation. */
 120 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 121
 122 /* Activate DV E-Switch flow steering. */
 123 #define MLX5_DV_ESW_EN "dv_esw_en"
 124
 125 /* Activate DV flow steering. */
 126 #define MLX5_DV_FLOW_EN "dv_flow_en"
 127
 128 /* Enable extensive flow metadata support. */
 129 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 130
 131 /* Activate Netlink support in VF mode. */
 132 #define MLX5_VF_NL_EN "vf_nl_en"
 133
 134 /* Enable extending memsegs when creating a MR. */
 135 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 136
 137 /* Select port representors to instantiate. */
 138 #define MLX5_REPRESENTOR "representor"
 139
 140 /* Device parameter to configure the maximum number of dump files per queue. */
 141 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 142
 143 /* Configure timeout of LRO session (in microseconds). */
 144 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 145
 146 #ifndef HAVE_IBV_MLX5_MOD_MPW
 147 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
 148 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
 149 #endif
 150
 151 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
 152 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
 153 #endif
 154
 155 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
 156
 157 /* Shared memory between primary and secondary processes. */
 158 struct mlx5_shared_data *mlx5_shared_data;
 159
 160 /* Spinlock for mlx5_shared_data allocation. */
 161 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
 162
 163 /* Process local data for secondary processes. */
 164 static struct mlx5_local_data mlx5_local_data;
 165
 166 /** Driver-specific log messages type. */
 167 int mlx5_logtype;
 168
 169 /** Data associated with devices to spawn. */
 170 struct mlx5_dev_spawn_data {
 171         uint32_t ifindex; /**< Network interface index. */
 172         uint32_t max_port; /**< IB device maximal port index. */
 173         uint32_t ibv_port; /**< IB device physical port index. */
 174         int pf_bond; /**< bonding device PF index. < 0 - no bonding */
 175         struct mlx5_switch_info info; /**< Switch information. */
 176         struct ibv_device *ibv_dev; /**< Associated IB device. */
 177         struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
 178         struct rte_pci_device *pci_dev; /**< Backend PCI device. */
 179 };
 180
 181 static LIST_HEAD(, mlx5_ibv_shared) mlx5_ibv_list = LIST_HEAD_INITIALIZER();
 182 static pthread_mutex_t mlx5_ibv_list_mutex = PTHREAD_MUTEX_INITIALIZER;
 183
 184 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 185 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 186
 187 /**
 188  * Allocate ID pool structure.
 189  *
 190  * @return
 191  *   Pointer to pool object, NULL value otherwise.
 192  */
 193 struct mlx5_flow_id_pool *
 194 mlx5_flow_id_pool_alloc(void)
 195 {
 196         struct mlx5_flow_id_pool *pool;
 197         void *mem;
 198
 199         pool = rte_zmalloc("id pool allocation", sizeof(*pool),
 200                            RTE_CACHE_LINE_SIZE);
 201         if (!pool) {
 202                 DRV_LOG(ERR, "can't allocate id pool");
 203                 rte_errno  = ENOMEM;
 204                 return NULL;
 205         }
 206         mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
 207                           RTE_CACHE_LINE_SIZE);
 208         if (!mem) {
 209                 DRV_LOG(ERR, "can't allocate mem for id pool");
 210                 rte_errno  = ENOMEM;
 211                 goto error;
 212         }
 213         pool->free_arr = mem;
 214         pool->curr = pool->free_arr;
 215         pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
 216         pool->base_index = 0;
 217         return pool;
 218 error:
 219         rte_free(pool);
 220         return NULL;
 221 }
 222
 223 /**
 224  * Release ID pool structure.
 225  *
 226  * @param[in] pool
 227  *   Pointer to flow id pool object to free.
 228  */
 229 void
 230 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
 231 {
 232         rte_free(pool->free_arr);
 233         rte_free(pool);
 234 }
 235
 236 /**
 237  * Generate ID.
 238  *
 239  * @param[in] pool
 240  *   Pointer to flow id pool.
 241  * @param[out] id
 242  *   The generated ID.
 243  *
 244  * @return
 245  *   0 on success, error value otherwise.
 246  */
 247 uint32_t
 248 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
 249 {
 250         if (pool->curr == pool->free_arr) {
 251                 if (pool->base_index == UINT32_MAX) {
 252                         rte_errno  = ENOMEM;
 253                         DRV_LOG(ERR, "no free id");
 254                         return -rte_errno;
 255                 }
 256                 *id = ++pool->base_index;
 257                 return 0;
 258         }
 259         *id = *(--pool->curr);
 260         return 0;
 261 }
 262
 263 /**
 264  * Release ID.
 265  *
 266  * @param[in] pool
 267  *   Pointer to flow id pool.
 268  * @param[out] id
 269  *   The generated ID.
 270  *
 271  * @return
 272  *   0 on success, error value otherwise.
 273  */
 274 uint32_t
 275 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
 276 {
 277         uint32_t size;
 278         uint32_t size2;
 279         void *mem;
 280
 281         if (pool->curr == pool->last) {
 282                 size = pool->curr - pool->free_arr;
 283                 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
 284                 assert(size2 > size);
 285                 mem = rte_malloc("", size2 * sizeof(uint32_t), 0);
 286                 if (!mem) {
 287                         DRV_LOG(ERR, "can't allocate mem for id pool");
 288                         rte_errno  = ENOMEM;
 289                         return -rte_errno;
 290                 }
 291                 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
 292                 rte_free(pool->free_arr);
 293                 pool->free_arr = mem;
 294                 pool->curr = pool->free_arr + size;
 295                 pool->last = pool->free_arr + size2;
 296         }
 297         *pool->curr = id;
 298         pool->curr++;
 299         return 0;
 300 }
 301
 302 /**
 303  * Initialize the counters management structure.
 304  *
 305  * @param[in] sh
 306  *   Pointer to mlx5_ibv_shared object to free
 307  */
 308 static void
 309 mlx5_flow_counters_mng_init(struct mlx5_ibv_shared *sh)
 310 {
 311         uint8_t i;
 312
 313         TAILQ_INIT(&sh->cmng.flow_counters);
 314         for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i)
 315                 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
 316 }
 317
 318 /**
 319  * Destroy all the resources allocated for a counter memory management.
 320  *
 321  * @param[in] mng
 322  *   Pointer to the memory management structure.
 323  */
 324 static void
 325 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 326 {
 327         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 328
 329         LIST_REMOVE(mng, next);
 330         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 331         claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
 332         rte_free(mem);
 333 }
 334
 335 /**
 336  * Close and release all the resources of the counters management.
 337  *
 338  * @param[in] sh
 339  *   Pointer to mlx5_ibv_shared object to free.
 340  */
 341 static void
 342 mlx5_flow_counters_mng_close(struct mlx5_ibv_shared *sh)
 343 {
 344         struct mlx5_counter_stats_mem_mng *mng;
 345         uint8_t i;
 346         int j;
 347         int retries = 1024;
 348
 349         rte_errno = 0;
 350         while (--retries) {
 351                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 352                 if (rte_errno != EINPROGRESS)
 353                         break;
 354                 rte_pause();
 355         }
 356         for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i) {
 357                 struct mlx5_flow_counter_pool *pool;
 358                 uint32_t batch = !!(i % 2);
 359
 360                 if (!sh->cmng.ccont[i].pools)
 361                         continue;
 362                 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 363                 while (pool) {
 364                         if (batch) {
 365                                 if (pool->min_dcs)
 366                                         claim_zero
 367                                         (mlx5_devx_cmd_destroy(pool->min_dcs));
 368                         }
 369                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 370                                 if (pool->counters_raw[j].action)
 371                                         claim_zero
 372                                         (mlx5_glue->destroy_flow_action
 373                                                (pool->counters_raw[j].action));
 374                                 if (!batch && pool->counters_raw[j].dcs)
 375                                         claim_zero(mlx5_devx_cmd_destroy
 376                                                   (pool->counters_raw[j].dcs));
 377                         }
 378                         TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool,
 379                                      next);
 380                         rte_free(pool);
 381                         pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 382                 }
 383                 rte_free(sh->cmng.ccont[i].pools);
 384         }
 385         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 386         while (mng) {
 387                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 388                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 389         }
 390         memset(&sh->cmng, 0, sizeof(sh->cmng));
 391 }
 392
 393 /**
 394  * Extract pdn of PD object using DV API.
 395  *
 396  * @param[in] pd
 397  *   Pointer to the verbs PD object.
 398  * @param[out] pdn
 399  *   Pointer to the PD object number variable.
 400  *
 401  * @return
 402  *   0 on success, error value otherwise.
 403  */
 404 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 405 static int
 406 mlx5_get_pdn(struct ibv_pd *pd __rte_unused, uint32_t *pdn __rte_unused)
 407 {
 408         struct mlx5dv_obj obj;
 409         struct mlx5dv_pd pd_info;
 410         int ret = 0;
 411
 412         obj.pd.in = pd;
 413         obj.pd.out = &pd_info;
 414         ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);
 415         if (ret) {
 416                 DRV_LOG(DEBUG, "Fail to get PD object info");
 417                 return ret;
 418         }
 419         *pdn = pd_info.pdn;
 420         return 0;
 421 }
 422 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
 423
 424 /**
 425  * Allocate shared IB device context. If there is multiport device the
 426  * master and representors will share this context, if there is single
 427  * port dedicated IB device, the context will be used by only given
 428  * port due to unification.
 429  *
 430  * Routine first searches the context for the specified IB device name,
 431  * if found the shared context assumed and reference counter is incremented.
 432  * If no context found the new one is created and initialized with specified
 433  * IB device context and parameters.
 434  *
 435  * @param[in] spawn
 436  *   Pointer to the IB device attributes (name, port, etc).
 437  *
 438  * @return
 439  *   Pointer to mlx5_ibv_shared object on success,
 440  *   otherwise NULL and rte_errno is set.
 441  */
 442 static struct mlx5_ibv_shared *
 443 mlx5_alloc_shared_ibctx(const struct mlx5_dev_spawn_data *spawn)
 444 {
 445         struct mlx5_ibv_shared *sh;
 446         int err = 0;
 447         uint32_t i;
 448 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 449         struct mlx5_devx_tis_attr tis_attr = { 0 };
 450 #endif
 451
 452 assert(spawn);
 453         /* Secondary process should not create the shared context. */
 454         assert(rte_eal_process_type() == RTE_PROC_PRIMARY);
 455         pthread_mutex_lock(&mlx5_ibv_list_mutex);
 456         /* Search for IB context by device name. */
 457         LIST_FOREACH(sh, &mlx5_ibv_list, next) {
 458                 if (!strcmp(sh->ibdev_name, spawn->ibv_dev->name)) {
 459                         sh->refcnt++;
 460                         goto exit;
 461                 }
 462         }
 463         /* No device found, we have to create new shared context. */
 464         assert(spawn->max_port);
 465         sh = rte_zmalloc("ethdev shared ib context",
 466                          sizeof(struct mlx5_ibv_shared) +
 467                          spawn->max_port *
 468                          sizeof(struct mlx5_ibv_shared_port),
 469                          RTE_CACHE_LINE_SIZE);
 470         if (!sh) {
 471                 DRV_LOG(ERR, "shared context allocation failure");
 472                 rte_errno  = ENOMEM;
 473                 goto exit;
 474         }
 475         /* Try to open IB device with DV first, then usual Verbs. */
 476         errno = 0;
 477         sh->ctx = mlx5_glue->dv_open_device(spawn->ibv_dev);
 478         if (sh->ctx) {
 479                 sh->devx = 1;
 480                 DRV_LOG(DEBUG, "DevX is supported");
 481         } else {
 482                 sh->ctx = mlx5_glue->open_device(spawn->ibv_dev);
 483                 if (!sh->ctx) {
 484                         err = errno ? errno : ENODEV;
 485                         goto error;
 486                 }
 487                 DRV_LOG(DEBUG, "DevX is NOT supported");
 488         }
 489         err = mlx5_glue->query_device_ex(sh->ctx, NULL, &sh->device_attr);
 490         if (err) {
 491                 DRV_LOG(DEBUG, "ibv_query_device_ex() failed");
 492                 goto error;
 493         }
 494         sh->refcnt = 1;
 495         sh->max_port = spawn->max_port;
 496         strncpy(sh->ibdev_name, sh->ctx->device->name,
 497                 sizeof(sh->ibdev_name));
 498         strncpy(sh->ibdev_path, sh->ctx->device->ibdev_path,
 499                 sizeof(sh->ibdev_path));
 500         pthread_mutex_init(&sh->intr_mutex, NULL);
 501         /*
 502          * Setting port_id to max unallowed value means
 503          * there is no interrupt subhandler installed for
 504          * the given port index i.
 505          */
 506         for (i = 0; i < sh->max_port; i++) {
 507                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 508                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
 509         }
 510         sh->pd = mlx5_glue->alloc_pd(sh->ctx);
 511         if (sh->pd == NULL) {
 512                 DRV_LOG(ERR, "PD allocation failure");
 513                 err = ENOMEM;
 514                 goto error;
 515         }
 516 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 517         if (sh->devx) {
 518                 err = mlx5_get_pdn(sh->pd, &sh->pdn);
 519                 if (err) {
 520                         DRV_LOG(ERR, "Fail to extract pdn from PD");
 521                         goto error;
 522                 }
 523                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
 524                 if (!sh->td) {
 525                         DRV_LOG(ERR, "TD allocation failure");
 526                         err = ENOMEM;
 527                         goto error;
 528                 }
 529                 tis_attr.transport_domain = sh->td->id;
 530                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
 531                 if (!sh->tis) {
 532                         DRV_LOG(ERR, "TIS allocation failure");
 533                         err = ENOMEM;
 534                         goto error;
 535                 }
 536         }
 537         sh->flow_id_pool = mlx5_flow_id_pool_alloc();
 538         if (!sh->flow_id_pool) {
 539                 DRV_LOG(ERR, "can't create flow id pool");
 540                 err = ENOMEM;
 541                 goto error;
 542         }
 543 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
 544         /*
 545          * Once the device is added to the list of memory event
 546          * callback, its global MR cache table cannot be expanded
 547          * on the fly because of deadlock. If it overflows, lookup
 548          * should be done by searching MR list linearly, which is slow.
 549          *
 550          * At this point the device is not added to the memory
 551          * event list yet, context is just being created.
 552          */
 553         err = mlx5_mr_btree_init(&sh->mr.cache,
 554                                  MLX5_MR_BTREE_CACHE_N * 2,
 555                                  spawn->pci_dev->device.numa_node);
 556         if (err) {
 557                 err = rte_errno;
 558                 goto error;
 559         }
 560         mlx5_flow_counters_mng_init(sh);
 561         /* Add device to memory callback list. */
 562         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 563         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
 564                          sh, mem_event_cb);
 565         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 566         /* Add context to the global device list. */
 567         LIST_INSERT_HEAD(&mlx5_ibv_list, sh, next);
 568 exit:
 569         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 570         return sh;
 571 error:
 572         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 573         assert(sh);
 574         if (sh->tis)
 575                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 576         if (sh->td)
 577                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 578         if (sh->pd)
 579                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 580         if (sh->ctx)
 581                 claim_zero(mlx5_glue->close_device(sh->ctx));
 582         if (sh->flow_id_pool)
 583                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 584         rte_free(sh);
 585         assert(err > 0);
 586         rte_errno = err;
 587         return NULL;
 588 }
 589
 590 /**
 591  * Free shared IB device context. Decrement counter and if zero free
 592  * all allocated resources and close handles.
 593  *
 594  * @param[in] sh
 595  *   Pointer to mlx5_ibv_shared object to free
 596  */
 597 static void
 598 mlx5_free_shared_ibctx(struct mlx5_ibv_shared *sh)
 599 {
 600         pthread_mutex_lock(&mlx5_ibv_list_mutex);
 601 #ifndef NDEBUG
 602         /* Check the object presence in the list. */
 603         struct mlx5_ibv_shared *lctx;
 604
 605         LIST_FOREACH(lctx, &mlx5_ibv_list, next)
 606                 if (lctx == sh)
 607                         break;
 608         assert(lctx);
 609         if (lctx != sh) {
 610                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
 611                 goto exit;
 612         }
 613 #endif
 614         assert(sh);
 615         assert(sh->refcnt);
 616         /* Secondary process should not free the shared context. */
 617         assert(rte_eal_process_type() == RTE_PROC_PRIMARY);
 618         if (--sh->refcnt)
 619                 goto exit;
 620         /* Release created Memory Regions. */
 621         mlx5_mr_release(sh);
 622         /* Remove from memory callback device list. */
 623         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 624         LIST_REMOVE(sh, mem_event_cb);
 625         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 626         /* Remove context from the global device list. */
 627         LIST_REMOVE(sh, next);
 628         /*
 629          *  Ensure there is no async event handler installed.
 630          *  Only primary process handles async device events.
 631          **/
 632         mlx5_flow_counters_mng_close(sh);
 633         assert(!sh->intr_cnt);
 634         if (sh->intr_cnt)
 635                 mlx5_intr_callback_unregister
 636                         (&sh->intr_handle, mlx5_dev_interrupt_handler, sh);
 637 #ifdef HAVE_MLX5_DEVX_ASYNC_SUPPORT
 638         if (sh->devx_intr_cnt) {
 639                 if (sh->intr_handle_devx.fd)
 640                         rte_intr_callback_unregister(&sh->intr_handle_devx,
 641                                           mlx5_dev_interrupt_handler_devx, sh);
 642                 if (sh->devx_comp)
 643                         mlx5dv_devx_destroy_cmd_comp(sh->devx_comp);
 644         }
 645 #endif
 646         pthread_mutex_destroy(&sh->intr_mutex);
 647         if (sh->pd)
 648                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 649         if (sh->tis)
 650                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 651         if (sh->td)
 652                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 653         if (sh->ctx)
 654                 claim_zero(mlx5_glue->close_device(sh->ctx));
 655         if (sh->flow_id_pool)
 656                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 657         rte_free(sh);
 658 exit:
 659         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 660 }
 661
 662 /**
 663  * Initialize DR related data within private structure.
 664  * Routine checks the reference counter and does actual
 665  * resources creation/initialization only if counter is zero.
 666  *
 667  * @param[in] priv
 668  *   Pointer to the private device data structure.
 669  *
 670  * @return
 671  *   Zero on success, positive error code otherwise.
 672  */
 673 static int
 674 mlx5_alloc_shared_dr(struct mlx5_priv *priv)
 675 {
 676 #ifdef HAVE_MLX5DV_DR
 677         struct mlx5_ibv_shared *sh = priv->sh;
 678         int err = 0;
 679         void *domain;
 680
 681         assert(sh);
 682         if (sh->dv_refcnt) {
 683                 /* Shared DV/DR structures is already initialized. */
 684                 sh->dv_refcnt++;
 685                 priv->dr_shared = 1;
 686                 return 0;
 687         }
 688         /* Reference counter is zero, we should initialize structures. */
 689         domain = mlx5_glue->dr_create_domain(sh->ctx,
 690                                              MLX5DV_DR_DOMAIN_TYPE_NIC_RX);
 691         if (!domain) {
 692                 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed");
 693                 err = errno;
 694                 goto error;
 695         }
 696         sh->rx_domain = domain;
 697         domain = mlx5_glue->dr_create_domain(sh->ctx,
 698                                              MLX5DV_DR_DOMAIN_TYPE_NIC_TX);
 699         if (!domain) {
 700                 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed");
 701                 err = errno;
 702                 goto error;
 703         }
 704         pthread_mutex_init(&sh->dv_mutex, NULL);
 705         sh->tx_domain = domain;
 706 #ifdef HAVE_MLX5DV_DR_ESWITCH
 707         if (priv->config.dv_esw_en) {
 708                 domain  = mlx5_glue->dr_create_domain
 709                         (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB);
 710                 if (!domain) {
 711                         DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed");
 712                         err = errno;
 713                         goto error;
 714                 }
 715                 sh->fdb_domain = domain;
 716                 sh->esw_drop_action = mlx5_glue->dr_create_flow_action_drop();
 717         }
 718 #endif
 719         sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan();
 720         sh->dv_refcnt++;
 721         priv->dr_shared = 1;
 722         return 0;
 723
 724 error:
 725        /* Rollback the created objects. */
 726         if (sh->rx_domain) {
 727                 mlx5_glue->dr_destroy_domain(sh->rx_domain);
 728                 sh->rx_domain = NULL;
 729         }
 730         if (sh->tx_domain) {
 731                 mlx5_glue->dr_destroy_domain(sh->tx_domain);
 732                 sh->tx_domain = NULL;
 733         }
 734         if (sh->fdb_domain) {
 735                 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
 736                 sh->fdb_domain = NULL;
 737         }
 738         if (sh->esw_drop_action) {
 739                 mlx5_glue->destroy_flow_action(sh->esw_drop_action);
 740                 sh->esw_drop_action = NULL;
 741         }
 742         if (sh->pop_vlan_action) {
 743                 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
 744                 sh->pop_vlan_action = NULL;
 745         }
 746         return err;
 747 #else
 748         (void)priv;
 749         return 0;
 750 #endif
 751 }
 752
 753 /**
 754  * Destroy DR related data within private structure.
 755  *
 756  * @param[in] priv
 757  *   Pointer to the private device data structure.
 758  */
 759 static void
 760 mlx5_free_shared_dr(struct mlx5_priv *priv)
 761 {
 762 #ifdef HAVE_MLX5DV_DR
 763         struct mlx5_ibv_shared *sh;
 764
 765         if (!priv->dr_shared)
 766                 return;
 767         priv->dr_shared = 0;
 768         sh = priv->sh;
 769         assert(sh);
 770         assert(sh->dv_refcnt);
 771         if (sh->dv_refcnt && --sh->dv_refcnt)
 772                 return;
 773         if (sh->rx_domain) {
 774                 mlx5_glue->dr_destroy_domain(sh->rx_domain);
 775                 sh->rx_domain = NULL;
 776         }
 777         if (sh->tx_domain) {
 778                 mlx5_glue->dr_destroy_domain(sh->tx_domain);
 779                 sh->tx_domain = NULL;
 780         }
 781 #ifdef HAVE_MLX5DV_DR_ESWITCH
 782         if (sh->fdb_domain) {
 783                 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
 784                 sh->fdb_domain = NULL;
 785         }
 786         if (sh->esw_drop_action) {
 787                 mlx5_glue->destroy_flow_action(sh->esw_drop_action);
 788                 sh->esw_drop_action = NULL;
 789         }
 790 #endif
 791         if (sh->pop_vlan_action) {
 792                 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
 793                 sh->pop_vlan_action = NULL;
 794         }
 795         pthread_mutex_destroy(&sh->dv_mutex);
 796 #else
 797         (void)priv;
 798 #endif
 799 }
 800
 801 /**
 802  * Initialize shared data between primary and secondary process.
 803  *
 804  * A memzone is reserved by primary process and secondary processes attach to
 805  * the memzone.
 806  *
 807  * @return
 808  *   0 on success, a negative errno value otherwise and rte_errno is set.
 809  */
 810 static int
 811 mlx5_init_shared_data(void)
 812 {
 813         const struct rte_memzone *mz;
 814         int ret = 0;
 815
 816         rte_spinlock_lock(&mlx5_shared_data_lock);
 817         if (mlx5_shared_data == NULL) {
 818                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
 819                         /* Allocate shared memory. */
 820                         mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
 821                                                  sizeof(*mlx5_shared_data),
 822                                                  SOCKET_ID_ANY, 0);
 823                         if (mz == NULL) {
 824                                 DRV_LOG(ERR,
 825                                         "Cannot allocate mlx5 shared data");
 826                                 ret = -rte_errno;
 827                                 goto error;
 828                         }
 829                         mlx5_shared_data = mz->addr;
 830                         memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
 831                         rte_spinlock_init(&mlx5_shared_data->lock);
 832                 } else {
 833                         /* Lookup allocated shared memory. */
 834                         mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
 835                         if (mz == NULL) {
 836                                 DRV_LOG(ERR,
 837                                         "Cannot attach mlx5 shared data");
 838                                 ret = -rte_errno;
 839                                 goto error;
 840                         }
 841                         mlx5_shared_data = mz->addr;
 842                         memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
 843                 }
 844         }
 845 error:
 846         rte_spinlock_unlock(&mlx5_shared_data_lock);
 847         return ret;
 848 }
 849
 850 /**
 851  * Retrieve integer value from environment variable.
 852  *
 853  * @param[in] name
 854  *   Environment variable name.
 855  *
 856  * @return
 857  *   Integer value, 0 if the variable is not set.
 858  */
 859 int
 860 mlx5_getenv_int(const char *name)
 861 {
 862         const char *val = getenv(name);
 863
 864         if (val == NULL)
 865                 return 0;
 866         return atoi(val);
 867 }
 868
 869 /**
 870  * Verbs callback to allocate a memory. This function should allocate the space
 871  * according to the size provided residing inside a huge page.
 872  * Please note that all allocation must respect the alignment from libmlx5
 873  * (i.e. currently sysconf(_SC_PAGESIZE)).
 874  *
 875  * @param[in] size
 876  *   The size in bytes of the memory to allocate.
 877  * @param[in] data
 878  *   A pointer to the callback data.
 879  *
 880  * @return
 881  *   Allocated buffer, NULL otherwise and rte_errno is set.
 882  */
 883 static void *
 884 mlx5_alloc_verbs_buf(size_t size, void *data)
 885 {
 886         struct mlx5_priv *priv = data;
 887         void *ret;
 888         size_t alignment = sysconf(_SC_PAGESIZE);
 889         unsigned int socket = SOCKET_ID_ANY;
 890
 891         if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
 892                 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
 893
 894                 socket = ctrl->socket;
 895         } else if (priv->verbs_alloc_ctx.type ==
 896                    MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
 897                 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
 898
 899                 socket = ctrl->socket;
 900         }
 901         assert(data != NULL);
 902         ret = rte_malloc_socket(__func__, size, alignment, socket);
 903         if (!ret && size)
 904                 rte_errno = ENOMEM;
 905         return ret;
 906 }
 907
 908 /**
 909  * Verbs callback to free a memory.
 910  *
 911  * @param[in] ptr
 912  *   A pointer to the memory to free.
 913  * @param[in] data
 914  *   A pointer to the callback data.
 915  */
 916 static void
 917 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
 918 {
 919         assert(data != NULL);
 920         rte_free(ptr);
 921 }
 922
 923 /**
 924  * DPDK callback to add udp tunnel port
 925  *
 926  * @param[in] dev
 927  *   A pointer to eth_dev
 928  * @param[in] udp_tunnel
 929  *   A pointer to udp tunnel
 930  *
 931  * @return
 932  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
 933  */
 934 int
 935 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
 936                          struct rte_eth_udp_tunnel *udp_tunnel)
 937 {
 938         assert(udp_tunnel != NULL);
 939         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
 940             udp_tunnel->udp_port == 4789)
 941                 return 0;
 942         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
 943             udp_tunnel->udp_port == 4790)
 944                 return 0;
 945         return -ENOTSUP;
 946 }
 947
 948 /**
 949  * Initialize process private data structure.
 950  *
 951  * @param dev
 952  *   Pointer to Ethernet device structure.
 953  *
 954  * @return
 955  *   0 on success, a negative errno value otherwise and rte_errno is set.
 956  */
 957 int
 958 mlx5_proc_priv_init(struct rte_eth_dev *dev)
 959 {
 960         struct mlx5_priv *priv = dev->data->dev_private;
 961         struct mlx5_proc_priv *ppriv;
 962         size_t ppriv_size;
 963
 964         /*
 965          * UAR register table follows the process private structure. BlueFlame
 966          * registers for Tx queues are stored in the table.
 967          */
 968         ppriv_size =
 969                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
 970         ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
 971                                   RTE_CACHE_LINE_SIZE, dev->device->numa_node);
 972         if (!ppriv) {
 973                 rte_errno = ENOMEM;
 974                 return -rte_errno;
 975         }
 976         ppriv->uar_table_sz = ppriv_size;
 977         dev->process_private = ppriv;
 978         return 0;
 979 }
 980
 981 /**
 982  * Un-initialize process private data structure.
 983  *
 984  * @param dev
 985  *   Pointer to Ethernet device structure.
 986  */
 987 static void
 988 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
 989 {
 990         if (!dev->process_private)
 991                 return;
 992         rte_free(dev->process_private);
 993         dev->process_private = NULL;
 994 }
 995
 996 /**
 997  * DPDK callback to close the device.
 998  *
 999  * Destroy all queues and objects, free memory.
1000  *
1001  * @param dev
1002  *   Pointer to Ethernet device structure.
1003  */
1004 static void
1005 mlx5_dev_close(struct rte_eth_dev *dev)
1006 {
1007         struct mlx5_priv *priv = dev->data->dev_private;
1008         unsigned int i;
1009         int ret;
1010
1011         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1012                 dev->data->port_id,
1013                 ((priv->sh->ctx != NULL) ? priv->sh->ctx->device->name : ""));
1014         /* In case mlx5_dev_stop() has not been called. */
1015         mlx5_dev_interrupt_handler_uninstall(dev);
1016         mlx5_dev_interrupt_handler_devx_uninstall(dev);
1017         mlx5_traffic_disable(dev);
1018         mlx5_flow_flush(dev, NULL);
1019         mlx5_flow_meter_flush(dev, NULL);
1020         /* Prevent crashes when queues are still in use. */
1021         dev->rx_pkt_burst = removed_rx_burst;
1022         dev->tx_pkt_burst = removed_tx_burst;
1023         rte_wmb();
1024         /* Disable datapath on secondary process. */
1025         mlx5_mp_req_stop_rxtx(dev);
1026         if (priv->rxqs != NULL) {
1027                 /* XXX race condition if mlx5_rx_burst() is still running. */
1028                 usleep(1000);
1029                 for (i = 0; (i != priv->rxqs_n); ++i)
1030                         mlx5_rxq_release(dev, i);
1031                 priv->rxqs_n = 0;
1032                 priv->rxqs = NULL;
1033         }
1034         if (priv->txqs != NULL) {
1035                 /* XXX race condition if mlx5_tx_burst() is still running. */
1036                 usleep(1000);
1037                 for (i = 0; (i != priv->txqs_n); ++i)
1038                         mlx5_txq_release(dev, i);
1039                 priv->txqs_n = 0;
1040                 priv->txqs = NULL;
1041         }
1042         mlx5_proc_priv_uninit(dev);
1043         if (priv->mreg_cp_tbl)
1044                 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1045         mlx5_mprq_free_mp(dev);
1046         mlx5_free_shared_dr(priv);
1047         if (priv->rss_conf.rss_key != NULL)
1048                 rte_free(priv->rss_conf.rss_key);
1049         if (priv->reta_idx != NULL)
1050                 rte_free(priv->reta_idx);
1051         if (priv->config.vf)
1052                 mlx5_nl_mac_addr_flush(dev);
1053         if (priv->nl_socket_route >= 0)
1054                 close(priv->nl_socket_route);
1055         if (priv->nl_socket_rdma >= 0)
1056                 close(priv->nl_socket_rdma);
1057         if (priv->vmwa_context)
1058                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1059         if (priv->sh) {
1060                 /*
1061                  * Free the shared context in last turn, because the cleanup
1062                  * routines above may use some shared fields, like
1063                  * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1064                  * ifindex if Netlink fails.
1065                  */
1066                 mlx5_free_shared_ibctx(priv->sh);
1067                 priv->sh = NULL;
1068         }
1069         ret = mlx5_hrxq_verify(dev);
1070         if (ret)
1071                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1072                         dev->data->port_id);
1073         ret = mlx5_ind_table_obj_verify(dev);
1074         if (ret)
1075                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1076                         dev->data->port_id);
1077         ret = mlx5_rxq_obj_verify(dev);
1078         if (ret)
1079                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1080                         dev->data->port_id);
1081         ret = mlx5_rxq_verify(dev);
1082         if (ret)
1083                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1084                         dev->data->port_id);
1085         ret = mlx5_txq_obj_verify(dev);
1086         if (ret)
1087                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1088                         dev->data->port_id);
1089         ret = mlx5_txq_verify(dev);
1090         if (ret)
1091                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1092                         dev->data->port_id);
1093         ret = mlx5_flow_verify(dev);
1094         if (ret)
1095                 DRV_LOG(WARNING, "port %u some flows still remain",
1096                         dev->data->port_id);
1097         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1098                 unsigned int c = 0;
1099                 uint16_t port_id;
1100
1101                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1102                         struct mlx5_priv *opriv =
1103                                 rte_eth_devices[port_id].data->dev_private;
1104
1105                         if (!opriv ||
1106                             opriv->domain_id != priv->domain_id ||
1107                             &rte_eth_devices[port_id] == dev)
1108                                 continue;
1109                         ++c;
1110                         break;
1111                 }
1112                 if (!c)
1113                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1114         }
1115         memset(priv, 0, sizeof(*priv));
1116         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1117         /*
1118          * Reset mac_addrs to NULL such that it is not freed as part of
1119          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1120          * it is freed when dev_private is freed.
1121          */
1122         dev->data->mac_addrs = NULL;
1123 }
1124
1125 const struct eth_dev_ops mlx5_dev_ops = {
1126         .dev_configure = mlx5_dev_configure,
1127         .dev_start = mlx5_dev_start,
1128         .dev_stop = mlx5_dev_stop,
1129         .dev_set_link_down = mlx5_set_link_down,
1130         .dev_set_link_up = mlx5_set_link_up,
1131         .dev_close = mlx5_dev_close,
1132         .promiscuous_enable = mlx5_promiscuous_enable,
1133         .promiscuous_disable = mlx5_promiscuous_disable,
1134         .allmulticast_enable = mlx5_allmulticast_enable,
1135         .allmulticast_disable = mlx5_allmulticast_disable,
1136         .link_update = mlx5_link_update,
1137         .stats_get = mlx5_stats_get,
1138         .stats_reset = mlx5_stats_reset,
1139         .xstats_get = mlx5_xstats_get,
1140         .xstats_reset = mlx5_xstats_reset,
1141         .xstats_get_names = mlx5_xstats_get_names,
1142         .fw_version_get = mlx5_fw_version_get,
1143         .dev_infos_get = mlx5_dev_infos_get,
1144         .read_clock = mlx5_read_clock,
1145         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1146         .vlan_filter_set = mlx5_vlan_filter_set,
1147         .rx_queue_setup = mlx5_rx_queue_setup,
1148         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1149         .tx_queue_setup = mlx5_tx_queue_setup,
1150         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1151         .rx_queue_release = mlx5_rx_queue_release,
1152         .tx_queue_release = mlx5_tx_queue_release,
1153         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1154         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1155         .mac_addr_remove = mlx5_mac_addr_remove,
1156         .mac_addr_add = mlx5_mac_addr_add,
1157         .mac_addr_set = mlx5_mac_addr_set,
1158         .set_mc_addr_list = mlx5_set_mc_addr_list,
1159         .mtu_set = mlx5_dev_set_mtu,
1160         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1161         .vlan_offload_set = mlx5_vlan_offload_set,
1162         .reta_update = mlx5_dev_rss_reta_update,
1163         .reta_query = mlx5_dev_rss_reta_query,
1164         .rss_hash_update = mlx5_rss_hash_update,
1165         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1166         .filter_ctrl = mlx5_dev_filter_ctrl,
1167         .rx_descriptor_status = mlx5_rx_descriptor_status,
1168         .tx_descriptor_status = mlx5_tx_descriptor_status,
1169         .rx_queue_count = mlx5_rx_queue_count,
1170         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1171         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1172         .is_removed = mlx5_is_removed,
1173         .udp_tunnel_port_add  = mlx5_udp_tunnel_port_add,
1174         .get_module_info = mlx5_get_module_info,
1175         .get_module_eeprom = mlx5_get_module_eeprom,
1176         .hairpin_cap_get = mlx5_hairpin_cap_get,
1177         .mtr_ops_get = mlx5_flow_meter_ops_get,
1178 };
1179
1180 /* Available operations from secondary process. */
1181 static const struct eth_dev_ops mlx5_dev_sec_ops = {
1182         .stats_get = mlx5_stats_get,
1183         .stats_reset = mlx5_stats_reset,
1184         .xstats_get = mlx5_xstats_get,
1185         .xstats_reset = mlx5_xstats_reset,
1186         .xstats_get_names = mlx5_xstats_get_names,
1187         .fw_version_get = mlx5_fw_version_get,
1188         .dev_infos_get = mlx5_dev_infos_get,
1189         .rx_descriptor_status = mlx5_rx_descriptor_status,
1190         .tx_descriptor_status = mlx5_tx_descriptor_status,
1191         .get_module_info = mlx5_get_module_info,
1192         .get_module_eeprom = mlx5_get_module_eeprom,
1193 };
1194
1195 /* Available operations in flow isolated mode. */
1196 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1197         .dev_configure = mlx5_dev_configure,
1198         .dev_start = mlx5_dev_start,
1199         .dev_stop = mlx5_dev_stop,
1200         .dev_set_link_down = mlx5_set_link_down,
1201         .dev_set_link_up = mlx5_set_link_up,
1202         .dev_close = mlx5_dev_close,
1203         .promiscuous_enable = mlx5_promiscuous_enable,
1204         .promiscuous_disable = mlx5_promiscuous_disable,
1205         .allmulticast_enable = mlx5_allmulticast_enable,
1206         .allmulticast_disable = mlx5_allmulticast_disable,
1207         .link_update = mlx5_link_update,
1208         .stats_get = mlx5_stats_get,
1209         .stats_reset = mlx5_stats_reset,
1210         .xstats_get = mlx5_xstats_get,
1211         .xstats_reset = mlx5_xstats_reset,
1212         .xstats_get_names = mlx5_xstats_get_names,
1213         .fw_version_get = mlx5_fw_version_get,
1214         .dev_infos_get = mlx5_dev_infos_get,
1215         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1216         .vlan_filter_set = mlx5_vlan_filter_set,
1217         .rx_queue_setup = mlx5_rx_queue_setup,
1218         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1219         .tx_queue_setup = mlx5_tx_queue_setup,
1220         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1221         .rx_queue_release = mlx5_rx_queue_release,
1222         .tx_queue_release = mlx5_tx_queue_release,
1223         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1224         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1225         .mac_addr_remove = mlx5_mac_addr_remove,
1226         .mac_addr_add = mlx5_mac_addr_add,
1227         .mac_addr_set = mlx5_mac_addr_set,
1228         .set_mc_addr_list = mlx5_set_mc_addr_list,
1229         .mtu_set = mlx5_dev_set_mtu,
1230         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1231         .vlan_offload_set = mlx5_vlan_offload_set,
1232         .filter_ctrl = mlx5_dev_filter_ctrl,
1233         .rx_descriptor_status = mlx5_rx_descriptor_status,
1234         .tx_descriptor_status = mlx5_tx_descriptor_status,
1235         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1236         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1237         .is_removed = mlx5_is_removed,
1238         .get_module_info = mlx5_get_module_info,
1239         .get_module_eeprom = mlx5_get_module_eeprom,
1240         .hairpin_cap_get = mlx5_hairpin_cap_get,
1241         .mtr_ops_get = mlx5_flow_meter_ops_get,
1242 };
1243
1244 /**
1245  * Verify and store value for device argument.
1246  *
1247  * @param[in] key
1248  *   Key argument to verify.
1249  * @param[in] val
1250  *   Value associated with key.
1251  * @param opaque
1252  *   User data.
1253  *
1254  * @return
1255  *   0 on success, a negative errno value otherwise and rte_errno is set.
1256  */
1257 static int
1258 mlx5_args_check(const char *key, const char *val, void *opaque)
1259 {
1260         struct mlx5_dev_config *config = opaque;
1261         unsigned long tmp;
1262
1263         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1264         if (!strcmp(MLX5_REPRESENTOR, key))
1265                 return 0;
1266         errno = 0;
1267         tmp = strtoul(val, NULL, 0);
1268         if (errno) {
1269                 rte_errno = errno;
1270                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1271                 return -rte_errno;
1272         }
1273         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1274                 config->cqe_comp = !!tmp;
1275         } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1276                 config->cqe_pad = !!tmp;
1277         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1278                 config->hw_padding = !!tmp;
1279         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1280                 config->mprq.enabled = !!tmp;
1281         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1282                 config->mprq.stride_num_n = tmp;
1283         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1284                 config->mprq.max_memcpy_len = tmp;
1285         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1286                 config->mprq.min_rxqs_num = tmp;
1287         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1288                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1289                                  " converted to txq_inline_max", key);
1290                 config->txq_inline_max = tmp;
1291         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1292                 config->txq_inline_max = tmp;
1293         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1294                 config->txq_inline_min = tmp;
1295         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1296                 config->txq_inline_mpw = tmp;
1297         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1298                 config->txqs_inline = tmp;
1299         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1300                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1301         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1302                 config->mps = !!tmp;
1303         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1304                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1305         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1306                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1307                                  " converted to txq_inline_mpw", key);
1308                 config->txq_inline_mpw = tmp;
1309         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1310                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1311         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1312                 config->rx_vec_en = !!tmp;
1313         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1314                 config->l3_vxlan_en = !!tmp;
1315         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1316                 config->vf_nl_en = !!tmp;
1317         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1318                 config->dv_esw_en = !!tmp;
1319         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1320                 config->dv_flow_en = !!tmp;
1321         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1322                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1323                     tmp != MLX5_XMETA_MODE_META16 &&
1324                     tmp != MLX5_XMETA_MODE_META32) {
1325                         DRV_LOG(WARNING, "invalid extensive "
1326                                          "metadata parameter");
1327                         rte_errno = EINVAL;
1328                         return -rte_errno;
1329                 }
1330                 config->dv_xmeta_en = tmp;
1331         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1332                 config->mr_ext_memseg_en = !!tmp;
1333         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1334                 config->max_dump_files_num = tmp;
1335         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1336                 config->lro.timeout = tmp;
1337         } else {
1338                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1339                 rte_errno = EINVAL;
1340                 return -rte_errno;
1341         }
1342         return 0;
1343 }
1344
1345 /**
1346  * Parse device parameters.
1347  *
1348  * @param config
1349  *   Pointer to device configuration structure.
1350  * @param devargs
1351  *   Device arguments structure.
1352  *
1353  * @return
1354  *   0 on success, a negative errno value otherwise and rte_errno is set.
1355  */
1356 static int
1357 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1358 {
1359         const char **params = (const char *[]){
1360                 MLX5_RXQ_CQE_COMP_EN,
1361                 MLX5_RXQ_CQE_PAD_EN,
1362                 MLX5_RXQ_PKT_PAD_EN,
1363                 MLX5_RX_MPRQ_EN,
1364                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1365                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1366                 MLX5_RXQS_MIN_MPRQ,
1367                 MLX5_TXQ_INLINE,
1368                 MLX5_TXQ_INLINE_MIN,
1369                 MLX5_TXQ_INLINE_MAX,
1370                 MLX5_TXQ_INLINE_MPW,
1371                 MLX5_TXQS_MIN_INLINE,
1372                 MLX5_TXQS_MAX_VEC,
1373                 MLX5_TXQ_MPW_EN,
1374                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1375                 MLX5_TXQ_MAX_INLINE_LEN,
1376                 MLX5_TX_VEC_EN,
1377                 MLX5_RX_VEC_EN,
1378                 MLX5_L3_VXLAN_EN,
1379                 MLX5_VF_NL_EN,
1380                 MLX5_DV_ESW_EN,
1381                 MLX5_DV_FLOW_EN,
1382                 MLX5_DV_XMETA_EN,
1383                 MLX5_MR_EXT_MEMSEG_EN,
1384                 MLX5_REPRESENTOR,
1385                 MLX5_MAX_DUMP_FILES_NUM,
1386                 MLX5_LRO_TIMEOUT_USEC,
1387                 NULL,
1388         };
1389         struct rte_kvargs *kvlist;
1390         int ret = 0;
1391         int i;
1392
1393         if (devargs == NULL)
1394                 return 0;
1395         /* Following UGLY cast is done to pass checkpatch. */
1396         kvlist = rte_kvargs_parse(devargs->args, params);
1397         if (kvlist == NULL) {
1398                 rte_errno = EINVAL;
1399                 return -rte_errno;
1400         }
1401         /* Process parameters. */
1402         for (i = 0; (params[i] != NULL); ++i) {
1403                 if (rte_kvargs_count(kvlist, params[i])) {
1404                         ret = rte_kvargs_process(kvlist, params[i],
1405                                                  mlx5_args_check, config);
1406                         if (ret) {
1407                                 rte_errno = EINVAL;
1408                                 rte_kvargs_free(kvlist);
1409                                 return -rte_errno;
1410                         }
1411                 }
1412         }
1413         rte_kvargs_free(kvlist);
1414         return 0;
1415 }
1416
1417 static struct rte_pci_driver mlx5_driver;
1418
1419 /**
1420  * PMD global initialization.
1421  *
1422  * Independent from individual device, this function initializes global
1423  * per-PMD data structures distinguishing primary and secondary processes.
1424  * Hence, each initialization is called once per a process.
1425  *
1426  * @return
1427  *   0 on success, a negative errno value otherwise and rte_errno is set.
1428  */
1429 static int
1430 mlx5_init_once(void)
1431 {
1432         struct mlx5_shared_data *sd;
1433         struct mlx5_local_data *ld = &mlx5_local_data;
1434         int ret = 0;
1435
1436         if (mlx5_init_shared_data())
1437                 return -rte_errno;
1438         sd = mlx5_shared_data;
1439         assert(sd);
1440         rte_spinlock_lock(&sd->lock);
1441         switch (rte_eal_process_type()) {
1442         case RTE_PROC_PRIMARY:
1443                 if (sd->init_done)
1444                         break;
1445                 LIST_INIT(&sd->mem_event_cb_list);
1446                 rte_rwlock_init(&sd->mem_event_rwlock);
1447                 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1448                                                 mlx5_mr_mem_event_cb, NULL);
1449                 ret = mlx5_mp_init_primary();
1450                 if (ret)
1451                         goto out;
1452                 sd->init_done = true;
1453                 break;
1454         case RTE_PROC_SECONDARY:
1455                 if (ld->init_done)
1456                         break;
1457                 ret = mlx5_mp_init_secondary();
1458                 if (ret)
1459                         goto out;
1460                 ++sd->secondary_cnt;
1461                 ld->init_done = true;
1462                 break;
1463         default:
1464                 break;
1465         }
1466 out:
1467         rte_spinlock_unlock(&sd->lock);
1468         return ret;
1469 }
1470
1471 /**
1472  * Configures the minimal amount of data to inline into WQE
1473  * while sending packets.
1474  *
1475  * - the txq_inline_min has the maximal priority, if this
1476  *   key is specified in devargs
1477  * - if DevX is enabled the inline mode is queried from the
1478  *   device (HCA attributes and NIC vport context if needed).
1479  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4LX
1480  *   and none (0 bytes) for other NICs
1481  *
1482  * @param spawn
1483  *   Verbs device parameters (name, port, switch_info) to spawn.
1484  * @param config
1485  *   Device configuration parameters.
1486  */
1487 static void
1488 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1489                     struct mlx5_dev_config *config)
1490 {
1491         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1492                 /* Application defines size of inlined data explicitly. */
1493                 switch (spawn->pci_dev->id.device_id) {
1494                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1495                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1496                         if (config->txq_inline_min <
1497                                        (int)MLX5_INLINE_HSIZE_L2) {
1498                                 DRV_LOG(DEBUG,
1499                                         "txq_inline_mix aligned to minimal"
1500                                         " ConnectX-4 required value %d",
1501                                         (int)MLX5_INLINE_HSIZE_L2);
1502                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1503                         }
1504                         break;
1505                 }
1506                 goto exit;
1507         }
1508         if (config->hca_attr.eth_net_offloads) {
1509                 /* We have DevX enabled, inline mode queried successfully. */
1510                 switch (config->hca_attr.wqe_inline_mode) {
1511                 case MLX5_CAP_INLINE_MODE_L2:
1512                         /* outer L2 header must be inlined. */
1513                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1514                         goto exit;
1515                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1516                         /* No inline data are required by NIC. */
1517                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1518                         config->hw_vlan_insert =
1519                                 config->hca_attr.wqe_vlan_insert;
1520                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1521                         goto exit;
1522                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1523                         /* inline mode is defined by NIC vport context. */
1524                         if (!config->hca_attr.eth_virt)
1525                                 break;
1526                         switch (config->hca_attr.vport_inline_mode) {
1527                         case MLX5_INLINE_MODE_NONE:
1528                                 config->txq_inline_min =
1529                                         MLX5_INLINE_HSIZE_NONE;
1530                                 goto exit;
1531                         case MLX5_INLINE_MODE_L2:
1532                                 config->txq_inline_min =
1533                                         MLX5_INLINE_HSIZE_L2;
1534                                 goto exit;
1535                         case MLX5_INLINE_MODE_IP:
1536                                 config->txq_inline_min =
1537                                         MLX5_INLINE_HSIZE_L3;
1538                                 goto exit;
1539                         case MLX5_INLINE_MODE_TCP_UDP:
1540                                 config->txq_inline_min =
1541                                         MLX5_INLINE_HSIZE_L4;
1542                                 goto exit;
1543                         case MLX5_INLINE_MODE_INNER_L2:
1544                                 config->txq_inline_min =
1545                                         MLX5_INLINE_HSIZE_INNER_L2;
1546                                 goto exit;
1547                         case MLX5_INLINE_MODE_INNER_IP:
1548                                 config->txq_inline_min =
1549                                         MLX5_INLINE_HSIZE_INNER_L3;
1550                                 goto exit;
1551                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
1552                                 config->txq_inline_min =
1553                                         MLX5_INLINE_HSIZE_INNER_L4;
1554                                 goto exit;
1555                         }
1556                 }
1557         }
1558         /*
1559          * We get here if we are unable to deduce
1560          * inline data size with DevX. Try PCI ID
1561          * to determine old NICs.
1562          */
1563         switch (spawn->pci_dev->id.device_id) {
1564         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1565         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1566         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1567         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1568                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1569                 config->hw_vlan_insert = 0;
1570                 break;
1571         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1572         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1573         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1574         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1575                 /*
1576                  * These NICs support VLAN insertion from WQE and
1577                  * report the wqe_vlan_insert flag. But there is the bug
1578                  * and PFC control may be broken, so disable feature.
1579                  */
1580                 config->hw_vlan_insert = 0;
1581                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1582                 break;
1583         default:
1584                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1585                 break;
1586         }
1587 exit:
1588         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1589 }
1590
1591 /**
1592  * Configures the metadata mask fields in the shared context.
1593  *
1594  * @param [in] dev
1595  *   Pointer to Ethernet device.
1596  */
1597 static void
1598 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1599 {
1600         struct mlx5_priv *priv = dev->data->dev_private;
1601         struct mlx5_ibv_shared *sh = priv->sh;
1602         uint32_t meta, mark, reg_c0;
1603
1604         reg_c0 = ~priv->vport_meta_mask;
1605         switch (priv->config.dv_xmeta_en) {
1606         case MLX5_XMETA_MODE_LEGACY:
1607                 meta = UINT32_MAX;
1608                 mark = MLX5_FLOW_MARK_MASK;
1609                 break;
1610         case MLX5_XMETA_MODE_META16:
1611                 meta = reg_c0 >> rte_bsf32(reg_c0);
1612                 mark = MLX5_FLOW_MARK_MASK;
1613                 break;
1614         case MLX5_XMETA_MODE_META32:
1615                 meta = UINT32_MAX;
1616                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1617                 break;
1618         default:
1619                 meta = 0;
1620                 mark = 0;
1621                 assert(false);
1622                 break;
1623         }
1624         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1625                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1626                                  sh->dv_mark_mask, mark);
1627         else
1628                 sh->dv_mark_mask = mark;
1629         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1630                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1631                                  sh->dv_meta_mask, meta);
1632         else
1633                 sh->dv_meta_mask = meta;
1634         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1635                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1636                                  sh->dv_meta_mask, reg_c0);
1637         else
1638                 sh->dv_regc0_mask = reg_c0;
1639         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1640         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1641         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1642         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1643 }
1644
1645 /**
1646  * Allocate page of door-bells and register it using DevX API.
1647  *
1648  * @param [in] dev
1649  *   Pointer to Ethernet device.
1650  *
1651  * @return
1652  *   Pointer to new page on success, NULL otherwise.
1653  */
1654 static struct mlx5_devx_dbr_page *
1655 mlx5_alloc_dbr_page(struct rte_eth_dev *dev)
1656 {
1657         struct mlx5_priv *priv = dev->data->dev_private;
1658         struct mlx5_devx_dbr_page *page;
1659
1660         /* Allocate space for door-bell page and management data. */
1661         page = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_devx_dbr_page),
1662                                  RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1663         if (!page) {
1664                 DRV_LOG(ERR, "port %u cannot allocate dbr page",
1665                         dev->data->port_id);
1666                 return NULL;
1667         }
1668         /* Register allocated memory. */
1669         page->umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, page->dbrs,
1670                                               MLX5_DBR_PAGE_SIZE, 0);
1671         if (!page->umem) {
1672                 DRV_LOG(ERR, "port %u cannot umem reg dbr page",
1673                         dev->data->port_id);
1674                 rte_free(page);
1675                 return NULL;
1676         }
1677         return page;
1678 }
1679
1680 /**
1681  * Find the next available door-bell, allocate new page if needed.
1682  *
1683  * @param [in] dev
1684  *   Pointer to Ethernet device.
1685  * @param [out] dbr_page
1686  *   Door-bell page containing the page data.
1687  *
1688  * @return
1689  *   Door-bell address offset on success, a negative error value otherwise.
1690  */
1691 int64_t
1692 mlx5_get_dbr(struct rte_eth_dev *dev, struct mlx5_devx_dbr_page **dbr_page)
1693 {
1694         struct mlx5_priv *priv = dev->data->dev_private;
1695         struct mlx5_devx_dbr_page *page = NULL;
1696         uint32_t i, j;
1697
1698         LIST_FOREACH(page, &priv->dbrpgs, next)
1699                 if (page->dbr_count < MLX5_DBR_PER_PAGE)
1700                         break;
1701         if (!page) { /* No page with free door-bell exists. */
1702                 page = mlx5_alloc_dbr_page(dev);
1703                 if (!page) /* Failed to allocate new page. */
1704                         return (-1);
1705                 LIST_INSERT_HEAD(&priv->dbrpgs, page, next);
1706         }
1707         /* Loop to find bitmap part with clear bit. */
1708         for (i = 0;
1709              i < MLX5_DBR_BITMAP_SIZE && page->dbr_bitmap[i] == UINT64_MAX;
1710              i++)
1711                 ; /* Empty. */
1712         /* Find the first clear bit. */
1713         j = rte_bsf64(~page->dbr_bitmap[i]);
1714         assert(i < (MLX5_DBR_PER_PAGE / 64));
1715         page->dbr_bitmap[i] |= (1 << j);
1716         page->dbr_count++;
1717         *dbr_page = page;
1718         return (((i * 64) + j) * sizeof(uint64_t));
1719 }
1720
1721 /**
1722  * Release a door-bell record.
1723  *
1724  * @param [in] dev
1725  *   Pointer to Ethernet device.
1726  * @param [in] umem_id
1727  *   UMEM ID of page containing the door-bell record to release.
1728  * @param [in] offset
1729  *   Offset of door-bell record in page.
1730  *
1731  * @return
1732  *   0 on success, a negative error value otherwise.
1733  */
1734 int32_t
1735 mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id, uint64_t offset)
1736 {
1737         struct mlx5_priv *priv = dev->data->dev_private;
1738         struct mlx5_devx_dbr_page *page = NULL;
1739         int ret = 0;
1740
1741         LIST_FOREACH(page, &priv->dbrpgs, next)
1742                 /* Find the page this address belongs to. */
1743                 if (page->umem->umem_id == umem_id)
1744                         break;
1745         if (!page)
1746                 return -EINVAL;
1747         page->dbr_count--;
1748         if (!page->dbr_count) {
1749                 /* Page not used, free it and remove from list. */
1750                 LIST_REMOVE(page, next);
1751                 if (page->umem)
1752                         ret = -mlx5_glue->devx_umem_dereg(page->umem);
1753                 rte_free(page);
1754         } else {
1755                 /* Mark in bitmap that this door-bell is not in use. */
1756                 offset /= MLX5_DBR_SIZE;
1757                 int i = offset / 64;
1758                 int j = offset % 64;
1759
1760                 page->dbr_bitmap[i] &= ~(1 << j);
1761         }
1762         return ret;
1763 }
1764
1765 /**
1766  * Check sibling device configurations.
1767  *
1768  * Sibling devices sharing the Infiniband device context
1769  * should have compatible configurations. This regards
1770  * representors and bonding slaves.
1771  *
1772  * @param priv
1773  *   Private device descriptor.
1774  * @param config
1775  *   Configuration of the device is going to be created.
1776  *
1777  * @return
1778  *   0 on success, EINVAL otherwise
1779  */
1780 static int
1781 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1782                               struct mlx5_dev_config *config)
1783 {
1784         struct mlx5_ibv_shared *sh = priv->sh;
1785         struct mlx5_dev_config *sh_conf = NULL;
1786         uint16_t port_id;
1787
1788         assert(sh);
1789         /* Nothing to compare for the single/first device. */
1790         if (sh->refcnt == 1)
1791                 return 0;
1792         /* Find the device with shared context. */
1793         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1794                 struct mlx5_priv *opriv =
1795                         rte_eth_devices[port_id].data->dev_private;
1796
1797                 if (opriv && opriv != priv && opriv->sh == sh) {
1798                         sh_conf = &opriv->config;
1799                         break;
1800                 }
1801         }
1802         if (!sh_conf)
1803                 return 0;
1804         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1805                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1806                              " for shared %s context", sh->ibdev_name);
1807                 rte_errno = EINVAL;
1808                 return rte_errno;
1809         }
1810         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1811                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1812                              " for shared %s context", sh->ibdev_name);
1813                 rte_errno = EINVAL;
1814                 return rte_errno;
1815         }
1816         return 0;
1817 }
1818 /**
1819  * Spawn an Ethernet device from Verbs information.
1820  *
1821  * @param dpdk_dev
1822  *   Backing DPDK device.
1823  * @param spawn
1824  *   Verbs device parameters (name, port, switch_info) to spawn.
1825  * @param config
1826  *   Device configuration parameters.
1827  *
1828  * @return
1829  *   A valid Ethernet device object on success, NULL otherwise and rte_errno
1830  *   is set. The following errors are defined:
1831  *
1832  *   EBUSY: device is not supposed to be spawned.
1833  *   EEXIST: device is already spawned
1834  */
1835 static struct rte_eth_dev *
1836 mlx5_dev_spawn(struct rte_device *dpdk_dev,
1837                struct mlx5_dev_spawn_data *spawn,
1838                struct mlx5_dev_config config)
1839 {
1840         const struct mlx5_switch_info *switch_info = &spawn->info;
1841         struct mlx5_ibv_shared *sh = NULL;
1842         struct ibv_port_attr port_attr;
1843         struct mlx5dv_context dv_attr = { .comp_mask = 0 };
1844         struct rte_eth_dev *eth_dev = NULL;
1845         struct mlx5_priv *priv = NULL;
1846         int err = 0;
1847         unsigned int hw_padding = 0;
1848         unsigned int mps;
1849         unsigned int cqe_comp;
1850         unsigned int cqe_pad = 0;
1851         unsigned int tunnel_en = 0;
1852         unsigned int mpls_en = 0;
1853         unsigned int swp = 0;
1854         unsigned int mprq = 0;
1855         unsigned int mprq_min_stride_size_n = 0;
1856         unsigned int mprq_max_stride_size_n = 0;
1857         unsigned int mprq_min_stride_num_n = 0;
1858         unsigned int mprq_max_stride_num_n = 0;
1859         struct rte_ether_addr mac;
1860         char name[RTE_ETH_NAME_MAX_LEN];
1861         int own_domain_id = 0;
1862         uint16_t port_id;
1863         unsigned int i;
1864 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
1865         struct mlx5dv_devx_port devx_port = { .comp_mask = 0 };
1866 #endif
1867
1868         /* Determine if this port representor is supposed to be spawned. */
1869         if (switch_info->representor && dpdk_dev->devargs) {
1870                 struct rte_eth_devargs eth_da;
1871
1872                 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, &eth_da);
1873                 if (err) {
1874                         rte_errno = -err;
1875                         DRV_LOG(ERR, "failed to process device arguments: %s",
1876                                 strerror(rte_errno));
1877                         return NULL;
1878                 }
1879                 for (i = 0; i < eth_da.nb_representor_ports; ++i)
1880                         if (eth_da.representor_ports[i] ==
1881                             (uint16_t)switch_info->port_name)
1882                                 break;
1883                 if (i == eth_da.nb_representor_ports) {
1884                         rte_errno = EBUSY;
1885                         return NULL;
1886                 }
1887         }
1888         /* Build device name. */
1889         if (spawn->pf_bond <  0) {
1890                 /* Single device. */
1891                 if (!switch_info->representor)
1892                         strlcpy(name, dpdk_dev->name, sizeof(name));
1893                 else
1894                         snprintf(name, sizeof(name), "%s_representor_%u",
1895                                  dpdk_dev->name, switch_info->port_name);
1896         } else {
1897                 /* Bonding device. */
1898                 if (!switch_info->representor)
1899                         snprintf(name, sizeof(name), "%s_%s",
1900                                  dpdk_dev->name, spawn->ibv_dev->name);
1901                 else
1902                         snprintf(name, sizeof(name), "%s_%s_representor_%u",
1903                                  dpdk_dev->name, spawn->ibv_dev->name,
1904                                  switch_info->port_name);
1905         }
1906         /* check if the device is already spawned */
1907         if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
1908                 rte_errno = EEXIST;
1909                 return NULL;
1910         }
1911         DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
1912         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1913                 eth_dev = rte_eth_dev_attach_secondary(name);
1914                 if (eth_dev == NULL) {
1915                         DRV_LOG(ERR, "can not attach rte ethdev");
1916                         rte_errno = ENOMEM;
1917                         return NULL;
1918                 }
1919                 eth_dev->device = dpdk_dev;
1920                 eth_dev->dev_ops = &mlx5_dev_sec_ops;
1921                 err = mlx5_proc_priv_init(eth_dev);
1922                 if (err)
1923                         return NULL;
1924                 /* Receive command fd from primary process */
1925                 err = mlx5_mp_req_verbs_cmd_fd(eth_dev);
1926                 if (err < 0)
1927                         return NULL;
1928                 /* Remap UAR for Tx queues. */
1929                 err = mlx5_tx_uar_init_secondary(eth_dev, err);
1930                 if (err)
1931                         return NULL;
1932                 /*
1933                  * Ethdev pointer is still required as input since
1934                  * the primary device is not accessible from the
1935                  * secondary process.
1936                  */
1937                 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev);
1938                 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev);
1939                 return eth_dev;
1940         }
1941         sh = mlx5_alloc_shared_ibctx(spawn);
1942         if (!sh)
1943                 return NULL;
1944         config.devx = sh->devx;
1945 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR
1946         config.dest_tir = 1;
1947 #endif
1948 #ifdef HAVE_IBV_MLX5_MOD_SWP
1949         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
1950 #endif
1951         /*
1952          * Multi-packet send is supported by ConnectX-4 Lx PF as well
1953          * as all ConnectX-5 devices.
1954          */
1955 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
1956         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
1957 #endif
1958 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1959         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
1960 #endif
1961         mlx5_glue->dv_query_device(sh->ctx, &dv_attr);
1962         if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
1963                 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
1964                         DRV_LOG(DEBUG, "enhanced MPW is supported");
1965                         mps = MLX5_MPW_ENHANCED;
1966                 } else {
1967                         DRV_LOG(DEBUG, "MPW is supported");
1968                         mps = MLX5_MPW;
1969                 }
1970         } else {
1971                 DRV_LOG(DEBUG, "MPW isn't supported");
1972                 mps = MLX5_MPW_DISABLED;
1973         }
1974 #ifdef HAVE_IBV_MLX5_MOD_SWP
1975         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
1976                 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
1977         DRV_LOG(DEBUG, "SWP support: %u", swp);
1978 #endif
1979         config.swp = !!swp;
1980 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1981         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
1982                 struct mlx5dv_striding_rq_caps mprq_caps =
1983                         dv_attr.striding_rq_caps;
1984
1985                 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
1986                         mprq_caps.min_single_stride_log_num_of_bytes);
1987                 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
1988                         mprq_caps.max_single_stride_log_num_of_bytes);
1989                 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
1990                         mprq_caps.min_single_wqe_log_num_of_strides);
1991                 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
1992                         mprq_caps.max_single_wqe_log_num_of_strides);
1993                 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
1994                         mprq_caps.supported_qpts);
1995                 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
1996                 mprq = 1;
1997                 mprq_min_stride_size_n =
1998                         mprq_caps.min_single_stride_log_num_of_bytes;
1999                 mprq_max_stride_size_n =
2000                         mprq_caps.max_single_stride_log_num_of_bytes;
2001                 mprq_min_stride_num_n =
2002                         mprq_caps.min_single_wqe_log_num_of_strides;
2003                 mprq_max_stride_num_n =
2004                         mprq_caps.max_single_wqe_log_num_of_strides;
2005                 config.mprq.stride_num_n = RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
2006                                                    mprq_min_stride_num_n);
2007         }
2008 #endif
2009         if (RTE_CACHE_LINE_SIZE == 128 &&
2010             !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
2011                 cqe_comp = 0;
2012         else
2013                 cqe_comp = 1;
2014         config.cqe_comp = cqe_comp;
2015 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
2016         /* Whether device supports 128B Rx CQE padding. */
2017         cqe_pad = RTE_CACHE_LINE_SIZE == 128 &&
2018                   (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD);
2019 #endif
2020 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2021         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
2022                 tunnel_en = ((dv_attr.tunnel_offloads_caps &
2023                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
2024                              (dv_attr.tunnel_offloads_caps &
2025                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE));
2026         }
2027         DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
2028                 tunnel_en ? "" : "not ");
2029 #else
2030         DRV_LOG(WARNING,
2031                 "tunnel offloading disabled due to old OFED/rdma-core version");
2032 #endif
2033         config.tunnel_en = tunnel_en;
2034 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
2035         mpls_en = ((dv_attr.tunnel_offloads_caps &
2036                     MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
2037                    (dv_attr.tunnel_offloads_caps &
2038                     MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
2039         DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
2040                 mpls_en ? "" : "not ");
2041 #else
2042         DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
2043                 " old OFED/rdma-core version or firmware configuration");
2044 #endif
2045         config.mpls_en = mpls_en;
2046         /* Check port status. */
2047         err = mlx5_glue->query_port(sh->ctx, spawn->ibv_port, &port_attr);
2048         if (err) {
2049                 DRV_LOG(ERR, "port query failed: %s", strerror(err));
2050                 goto error;
2051         }
2052         if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
2053                 DRV_LOG(ERR, "port is not configured in Ethernet mode");
2054                 err = EINVAL;
2055                 goto error;
2056         }
2057         if (port_attr.state != IBV_PORT_ACTIVE)
2058                 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)",
2059                         mlx5_glue->port_state_str(port_attr.state),
2060                         port_attr.state);
2061         /* Allocate private eth device data. */
2062         priv = rte_zmalloc("ethdev private structure",
2063                            sizeof(*priv),
2064                            RTE_CACHE_LINE_SIZE);
2065         if (priv == NULL) {
2066                 DRV_LOG(ERR, "priv allocation failure");
2067                 err = ENOMEM;
2068                 goto error;
2069         }
2070         priv->sh = sh;
2071         priv->ibv_port = spawn->ibv_port;
2072         priv->pci_dev = spawn->pci_dev;
2073         priv->mtu = RTE_ETHER_MTU;
2074 #ifndef RTE_ARCH_64
2075         /* Initialize UAR access locks for 32bit implementations. */
2076         rte_spinlock_init(&priv->uar_lock_cq);
2077         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
2078                 rte_spinlock_init(&priv->uar_lock[i]);
2079 #endif
2080         /* Some internal functions rely on Netlink sockets, open them now. */
2081         priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA);
2082         priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE);
2083         priv->nl_sn = 0;
2084         priv->representor = !!switch_info->representor;
2085         priv->master = !!switch_info->master;
2086         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
2087         priv->vport_meta_tag = 0;
2088         priv->vport_meta_mask = 0;
2089         priv->pf_bond = spawn->pf_bond;
2090 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
2091         /*
2092          * The DevX port query API is implemented. E-Switch may use
2093          * either vport or reg_c[0] metadata register to match on
2094          * vport index. The engaged part of metadata register is
2095          * defined by mask.
2096          */
2097         if (switch_info->representor || switch_info->master) {
2098                 devx_port.comp_mask = MLX5DV_DEVX_PORT_VPORT |
2099                                       MLX5DV_DEVX_PORT_MATCH_REG_C_0;
2100                 err = mlx5_glue->devx_port_query(sh->ctx, spawn->ibv_port,
2101                                                  &devx_port);
2102                 if (err) {
2103                         DRV_LOG(WARNING,
2104                                 "can't query devx port %d on device %s",
2105                                 spawn->ibv_port, spawn->ibv_dev->name);
2106                         devx_port.comp_mask = 0;
2107                 }
2108         }
2109         if (devx_port.comp_mask & MLX5DV_DEVX_PORT_MATCH_REG_C_0) {
2110                 priv->vport_meta_tag = devx_port.reg_c_0.value;
2111                 priv->vport_meta_mask = devx_port.reg_c_0.mask;
2112                 if (!priv->vport_meta_mask) {
2113                         DRV_LOG(ERR, "vport zero mask for port %d"
2114                                      " on bonding device %s",
2115                                      spawn->ibv_port, spawn->ibv_dev->name);
2116                         err = ENOTSUP;
2117                         goto error;
2118                 }
2119                 if (priv->vport_meta_tag & ~priv->vport_meta_mask) {
2120                         DRV_LOG(ERR, "invalid vport tag for port %d"
2121                                      " on bonding device %s",
2122                                      spawn->ibv_port, spawn->ibv_dev->name);
2123                         err = ENOTSUP;
2124                         goto error;
2125                 }
2126         } else if (devx_port.comp_mask & MLX5DV_DEVX_PORT_VPORT) {
2127                 priv->vport_id = devx_port.vport_num;
2128         } else if (spawn->pf_bond >= 0) {
2129                 DRV_LOG(ERR, "can't deduce vport index for port %d"
2130                              " on bonding device %s",
2131                              spawn->ibv_port, spawn->ibv_dev->name);
2132                 err = ENOTSUP;
2133                 goto error;
2134         } else {
2135                 /* Suppose vport index in compatible way. */
2136                 priv->vport_id = switch_info->representor ?
2137                                  switch_info->port_name + 1 : -1;
2138         }
2139 #else
2140         /*
2141          * Kernel/rdma_core support single E-Switch per PF configurations
2142          * only and vport_id field contains the vport index for
2143          * associated VF, which is deduced from representor port name.
2144          * For example, let's have the IB device port 10, it has
2145          * attached network device eth0, which has port name attribute
2146          * pf0vf2, we can deduce the VF number as 2, and set vport index
2147          * as 3 (2+1). This assigning schema should be changed if the
2148          * multiple E-Switch instances per PF configurations or/and PCI
2149          * subfunctions are added.
2150          */
2151         priv->vport_id = switch_info->representor ?
2152                          switch_info->port_name + 1 : -1;
2153 #endif
2154         /* representor_id field keeps the unmodified VF index. */
2155         priv->representor_id = switch_info->representor ?
2156                                switch_info->port_name : -1;
2157         /*
2158          * Look for sibling devices in order to reuse their switch domain
2159          * if any, otherwise allocate one.
2160          */
2161         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2162                 const struct mlx5_priv *opriv =
2163                         rte_eth_devices[port_id].data->dev_private;
2164
2165                 if (!opriv ||
2166                     opriv->sh != priv->sh ||
2167                         opriv->domain_id ==
2168                         RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
2169                         continue;
2170                 priv->domain_id = opriv->domain_id;
2171                 break;
2172         }
2173         if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
2174                 err = rte_eth_switch_domain_alloc(&priv->domain_id);
2175                 if (err) {
2176                         err = rte_errno;
2177                         DRV_LOG(ERR, "unable to allocate switch domain: %s",
2178                                 strerror(rte_errno));
2179                         goto error;
2180                 }
2181                 own_domain_id = 1;
2182         }
2183         err = mlx5_args(&config, dpdk_dev->devargs);
2184         if (err) {
2185                 err = rte_errno;
2186                 DRV_LOG(ERR, "failed to process device arguments: %s",
2187                         strerror(rte_errno));
2188                 goto error;
2189         }
2190         err = mlx5_dev_check_sibling_config(priv, &config);
2191         if (err)
2192                 goto error;
2193         config.hw_csum = !!(sh->device_attr.device_cap_flags_ex &
2194                             IBV_DEVICE_RAW_IP_CSUM);
2195         DRV_LOG(DEBUG, "checksum offloading is %ssupported",
2196                 (config.hw_csum ? "" : "not "));
2197 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \
2198         !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
2199         DRV_LOG(DEBUG, "counters are not supported");
2200 #endif
2201 #ifndef HAVE_IBV_FLOW_DV_SUPPORT
2202         if (config.dv_flow_en) {
2203                 DRV_LOG(WARNING, "DV flow is not supported");
2204                 config.dv_flow_en = 0;
2205         }
2206 #endif
2207         config.ind_table_max_size =
2208                 sh->device_attr.rss_caps.max_rwq_indirection_table_size;
2209         /*
2210          * Remove this check once DPDK supports larger/variable
2211          * indirection tables.
2212          */
2213         if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
2214                 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
2215         DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
2216                 config.ind_table_max_size);
2217         config.hw_vlan_strip = !!(sh->device_attr.raw_packet_caps &
2218                                   IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
2219         DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
2220                 (config.hw_vlan_strip ? "" : "not "));
2221         config.hw_fcs_strip = !!(sh->device_attr.raw_packet_caps &
2222                                  IBV_RAW_PACKET_CAP_SCATTER_FCS);
2223         DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
2224                 (config.hw_fcs_strip ? "" : "not "));
2225 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
2226         hw_padding = !!sh->device_attr.rx_pad_end_addr_align;
2227 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
2228         hw_padding = !!(sh->device_attr.device_cap_flags_ex &
2229                         IBV_DEVICE_PCI_WRITE_END_PADDING);
2230 #endif
2231         if (config.hw_padding && !hw_padding) {
2232                 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
2233                 config.hw_padding = 0;
2234         } else if (config.hw_padding) {
2235                 DRV_LOG(DEBUG, "Rx end alignment padding is enabled");
2236         }
2237         config.tso = (sh->device_attr.tso_caps.max_tso > 0 &&
2238                       (sh->device_attr.tso_caps.supported_qpts &
2239                        (1 << IBV_QPT_RAW_PACKET)));
2240         if (config.tso)
2241                 config.tso_max_payload_sz = sh->device_attr.tso_caps.max_tso;
2242         /*
2243          * MPW is disabled by default, while the Enhanced MPW is enabled
2244          * by default.
2245          */
2246         if (config.mps == MLX5_ARG_UNSET)
2247                 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED :
2248                                                           MLX5_MPW_DISABLED;
2249         else
2250                 config.mps = config.mps ? mps : MLX5_MPW_DISABLED;
2251         DRV_LOG(INFO, "%sMPS is %s",
2252                 config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "",
2253                 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
2254         if (config.cqe_comp && !cqe_comp) {
2255                 DRV_LOG(WARNING, "Rx CQE compression isn't supported");
2256                 config.cqe_comp = 0;
2257         }
2258         if (config.cqe_pad && !cqe_pad) {
2259                 DRV_LOG(WARNING, "Rx CQE padding isn't supported");
2260                 config.cqe_pad = 0;
2261         } else if (config.cqe_pad) {
2262                 DRV_LOG(INFO, "Rx CQE padding is enabled");
2263         }
2264         if (config.devx) {
2265                 priv->counter_fallback = 0;
2266                 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config.hca_attr);
2267                 if (err) {
2268                         err = -err;
2269                         goto error;
2270                 }
2271                 if (!config.hca_attr.flow_counters_dump)
2272                         priv->counter_fallback = 1;
2273 #ifndef HAVE_IBV_DEVX_ASYNC
2274                 priv->counter_fallback = 1;
2275 #endif
2276                 if (priv->counter_fallback)
2277                         DRV_LOG(INFO, "Use fall-back DV counter management");
2278                 /* Check for LRO support. */
2279                 if (config.dest_tir && config.hca_attr.lro_cap &&
2280                     config.dv_flow_en) {
2281                         /* TBD check tunnel lro caps. */
2282                         config.lro.supported = config.hca_attr.lro_cap;
2283                         DRV_LOG(DEBUG, "Device supports LRO");
2284                         /*
2285                          * If LRO timeout is not configured by application,
2286                          * use the minimal supported value.
2287                          */
2288                         if (!config.lro.timeout)
2289                                 config.lro.timeout =
2290                                 config.hca_attr.lro_timer_supported_periods[0];
2291                         DRV_LOG(DEBUG, "LRO session timeout set to %d usec",
2292                                 config.lro.timeout);
2293                 }
2294 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER)
2295                 if (config.hca_attr.qos.sup && config.hca_attr.qos.srtcm_sup &&
2296                     config.dv_flow_en) {
2297                         uint8_t reg_c_mask =
2298                                 config.hca_attr.qos.flow_meter_reg_c_ids;
2299                         /*
2300                          * Meter needs two REG_C's for color match and pre-sfx
2301                          * flow match. Here get the REG_C for color match.
2302                          * REG_C_0 and REG_C_1 is reserved for metadata feature.
2303                          */
2304                         reg_c_mask &= 0xfc;
2305                         if (__builtin_popcount(reg_c_mask) < 1) {
2306                                 priv->mtr_en = 0;
2307                                 DRV_LOG(WARNING, "No available register for"
2308                                         " meter.");
2309                         } else {
2310                                 priv->mtr_color_reg = ffs(reg_c_mask) - 1 +
2311                                                       REG_C_0;
2312                                 priv->mtr_en = 1;
2313                                 DRV_LOG(DEBUG, "The REG_C meter uses is %d",
2314                                         priv->mtr_color_reg);
2315                         }
2316                 }
2317 #endif
2318         }
2319         if (config.mprq.enabled && mprq) {
2320                 if (config.mprq.stride_num_n > mprq_max_stride_num_n ||
2321                     config.mprq.stride_num_n < mprq_min_stride_num_n) {
2322                         config.mprq.stride_num_n =
2323                                 RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
2324                                         mprq_min_stride_num_n);
2325                         DRV_LOG(WARNING,
2326                                 "the number of strides"
2327                                 " for Multi-Packet RQ is out of range,"
2328                                 " setting default value (%u)",
2329                                 1 << config.mprq.stride_num_n);
2330                 }
2331                 config.mprq.min_stride_size_n = mprq_min_stride_size_n;
2332                 config.mprq.max_stride_size_n = mprq_max_stride_size_n;
2333         } else if (config.mprq.enabled && !mprq) {
2334                 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
2335                 config.mprq.enabled = 0;
2336         }
2337         if (config.max_dump_files_num == 0)
2338                 config.max_dump_files_num = 128;
2339         eth_dev = rte_eth_dev_allocate(name);
2340         if (eth_dev == NULL) {
2341                 DRV_LOG(ERR, "can not allocate rte ethdev");
2342                 err = ENOMEM;
2343                 goto error;
2344         }
2345         /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */
2346         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2347         if (priv->representor) {
2348                 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
2349                 eth_dev->data->representor_id = priv->representor_id;
2350         }
2351         /*
2352          * Store associated network device interface index. This index
2353          * is permanent throughout the lifetime of device. So, we may store
2354          * the ifindex here and use the cached value further.
2355          */
2356         assert(spawn->ifindex);
2357         priv->if_index = spawn->ifindex;
2358         eth_dev->data->dev_private = priv;
2359         priv->dev_data = eth_dev->data;
2360         eth_dev->data->mac_addrs = priv->mac;
2361         eth_dev->device = dpdk_dev;
2362         /* Configure the first MAC address by default. */
2363         if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
2364                 DRV_LOG(ERR,
2365                         "port %u cannot get MAC address, is mlx5_en"
2366                         " loaded? (errno: %s)",
2367                         eth_dev->data->port_id, strerror(rte_errno));
2368                 err = ENODEV;
2369                 goto error;
2370         }
2371         DRV_LOG(INFO,
2372                 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
2373                 eth_dev->data->port_id,
2374                 mac.addr_bytes[0], mac.addr_bytes[1],
2375                 mac.addr_bytes[2], mac.addr_bytes[3],
2376                 mac.addr_bytes[4], mac.addr_bytes[5]);
2377 #ifndef NDEBUG
2378         {
2379                 char ifname[IF_NAMESIZE];
2380
2381                 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
2382                         DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
2383                                 eth_dev->data->port_id, ifname);
2384                 else
2385                         DRV_LOG(DEBUG, "port %u ifname is unknown",
2386                                 eth_dev->data->port_id);
2387         }
2388 #endif
2389         /* Get actual MTU if possible. */
2390         err = mlx5_get_mtu(eth_dev, &priv->mtu);
2391         if (err) {
2392                 err = rte_errno;
2393                 goto error;
2394         }
2395         DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
2396                 priv->mtu);
2397         /* Initialize burst functions to prevent crashes before link-up. */
2398         eth_dev->rx_pkt_burst = removed_rx_burst;
2399         eth_dev->tx_pkt_burst = removed_tx_burst;
2400         eth_dev->dev_ops = &mlx5_dev_ops;
2401         /* Register MAC address. */
2402         claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
2403         if (config.vf && config.vf_nl_en)
2404                 mlx5_nl_mac_addr_sync(eth_dev);
2405         TAILQ_INIT(&priv->flows);
2406         TAILQ_INIT(&priv->ctrl_flows);
2407         TAILQ_INIT(&priv->flow_meters);
2408         TAILQ_INIT(&priv->flow_meter_profiles);
2409         /* Hint libmlx5 to use PMD allocator for data plane resources */
2410         struct mlx5dv_ctx_allocators alctr = {
2411                 .alloc = &mlx5_alloc_verbs_buf,
2412                 .free = &mlx5_free_verbs_buf,
2413                 .data = priv,
2414         };
2415         mlx5_glue->dv_set_context_attr(sh->ctx,
2416                                        MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
2417                                        (void *)((uintptr_t)&alctr));
2418         /* Bring Ethernet device up. */
2419         DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
2420                 eth_dev->data->port_id);
2421         mlx5_set_link_up(eth_dev);
2422         /*
2423          * Even though the interrupt handler is not installed yet,
2424          * interrupts will still trigger on the async_fd from
2425          * Verbs context returned by ibv_open_device().
2426          */
2427         mlx5_link_update(eth_dev, 0);
2428 #ifdef HAVE_MLX5DV_DR_ESWITCH
2429         if (!(config.hca_attr.eswitch_manager && config.dv_flow_en &&
2430               (switch_info->representor || switch_info->master)))
2431                 config.dv_esw_en = 0;
2432 #else
2433         config.dv_esw_en = 0;
2434 #endif
2435         /* Detect minimal data bytes to inline. */
2436         mlx5_set_min_inline(spawn, &config);
2437         /* Store device configuration on private structure. */
2438         priv->config = config;
2439         /* Create context for virtual machine VLAN workaround. */
2440         priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex);
2441         if (config.dv_flow_en) {
2442                 err = mlx5_alloc_shared_dr(priv);
2443                 if (err)
2444                         goto error;
2445                 priv->qrss_id_pool = mlx5_flow_id_pool_alloc();
2446                 if (!priv->qrss_id_pool) {
2447                         DRV_LOG(ERR, "can't create flow id pool");
2448                         err = ENOMEM;
2449                         goto error;
2450                 }
2451         }
2452         /* Supported Verbs flow priority number detection. */
2453         err = mlx5_flow_discover_priorities(eth_dev);
2454         if (err < 0) {
2455                 err = -err;
2456                 goto error;
2457         }
2458         priv->config.flow_prio = err;
2459         if (!priv->config.dv_esw_en &&
2460             priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2461                 DRV_LOG(WARNING, "metadata mode %u is not supported "
2462                                  "(no E-Switch)", priv->config.dv_xmeta_en);
2463                 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY;
2464         }
2465         mlx5_set_metadata_mask(eth_dev);
2466         if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
2467             !priv->sh->dv_regc0_mask) {
2468                 DRV_LOG(ERR, "metadata mode %u is not supported "
2469                              "(no metadata reg_c[0] is available)",
2470                              priv->config.dv_xmeta_en);
2471                         err = ENOTSUP;
2472                         goto error;
2473         }
2474         /* Query availibility of metadata reg_c's. */
2475         err = mlx5_flow_discover_mreg_c(eth_dev);
2476         if (err < 0) {
2477                 err = -err;
2478                 goto error;
2479         }
2480         if (!mlx5_flow_ext_mreg_supported(eth_dev)) {
2481                 DRV_LOG(DEBUG,
2482                         "port %u extensive metadata register is not supported",
2483                         eth_dev->data->port_id);
2484                 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2485                         DRV_LOG(ERR, "metadata mode %u is not supported "
2486                                      "(no metadata registers available)",
2487                                      priv->config.dv_xmeta_en);
2488                         err = ENOTSUP;
2489                         goto error;
2490                 }
2491         }
2492         if (priv->config.dv_flow_en &&
2493             priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
2494             mlx5_flow_ext_mreg_supported(eth_dev) &&
2495             priv->sh->dv_regc0_mask) {
2496                 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME,
2497                                                       MLX5_FLOW_MREG_HTABLE_SZ);
2498                 if (!priv->mreg_cp_tbl) {
2499                         err = ENOMEM;
2500                         goto error;
2501                 }
2502         }
2503         return eth_dev;
2504 error:
2505         if (priv) {
2506                 if (priv->mreg_cp_tbl)
2507                         mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
2508                 if (priv->sh)
2509                         mlx5_free_shared_dr(priv);
2510                 if (priv->nl_socket_route >= 0)
2511                         close(priv->nl_socket_route);
2512                 if (priv->nl_socket_rdma >= 0)
2513                         close(priv->nl_socket_rdma);
2514                 if (priv->vmwa_context)
2515                         mlx5_vlan_vmwa_exit(priv->vmwa_context);
2516                 if (priv->qrss_id_pool)
2517                         mlx5_flow_id_pool_release(priv->qrss_id_pool);
2518                 if (own_domain_id)
2519                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
2520                 rte_free(priv);
2521                 if (eth_dev != NULL)
2522                         eth_dev->data->dev_private = NULL;
2523         }
2524         if (eth_dev != NULL) {
2525                 /* mac_addrs must not be freed alone because part of dev_private */
2526                 eth_dev->data->mac_addrs = NULL;
2527                 rte_eth_dev_release_port(eth_dev);
2528         }
2529         if (sh)
2530                 mlx5_free_shared_ibctx(sh);
2531         assert(err > 0);
2532         rte_errno = err;
2533         return NULL;
2534 }
2535
2536 /**
2537  * Comparison callback to sort device data.
2538  *
2539  * This is meant to be used with qsort().
2540  *
2541  * @param a[in]
2542  *   Pointer to pointer to first data object.
2543  * @param b[in]
2544  *   Pointer to pointer to second data object.
2545  *
2546  * @return
2547  *   0 if both objects are equal, less than 0 if the first argument is less
2548  *   than the second, greater than 0 otherwise.
2549  */
2550 static int
2551 mlx5_dev_spawn_data_cmp(const void *a, const void *b)
2552 {
2553         const struct mlx5_switch_info *si_a =
2554                 &((const struct mlx5_dev_spawn_data *)a)->info;
2555         const struct mlx5_switch_info *si_b =
2556                 &((const struct mlx5_dev_spawn_data *)b)->info;
2557         int ret;
2558
2559         /* Master device first. */
2560         ret = si_b->master - si_a->master;
2561         if (ret)
2562                 return ret;
2563         /* Then representor devices. */
2564         ret = si_b->representor - si_a->representor;
2565         if (ret)
2566                 return ret;
2567         /* Unidentified devices come last in no specific order. */
2568         if (!si_a->representor)
2569                 return 0;
2570         /* Order representors by name. */
2571         return si_a->port_name - si_b->port_name;
2572 }
2573
2574 /**
2575  * Match PCI information for possible slaves of bonding device.
2576  *
2577  * @param[in] ibv_dev
2578  *   Pointer to Infiniband device structure.
2579  * @param[in] pci_dev
2580  *   Pointer to PCI device structure to match PCI address.
2581  * @param[in] nl_rdma
2582  *   Netlink RDMA group socket handle.
2583  *
2584  * @return
2585  *   negative value if no bonding device found, otherwise
2586  *   positive index of slave PF in bonding.
2587  */
2588 static int
2589 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev,
2590                            const struct rte_pci_device *pci_dev,
2591                            int nl_rdma)
2592 {
2593         char ifname[IF_NAMESIZE + 1];
2594         unsigned int ifindex;
2595         unsigned int np, i;
2596         FILE *file = NULL;
2597         int pf = -1;
2598
2599         /*
2600          * Try to get master device name. If something goes
2601          * wrong suppose the lack of kernel support and no
2602          * bonding devices.
2603          */
2604         if (nl_rdma < 0)
2605                 return -1;
2606         if (!strstr(ibv_dev->name, "bond"))
2607                 return -1;
2608         np = mlx5_nl_portnum(nl_rdma, ibv_dev->name);
2609         if (!np)
2610                 return -1;
2611         /*
2612          * The Master device might not be on the predefined
2613          * port (not on port index 1, it is not garanted),
2614          * we have to scan all Infiniband device port and
2615          * find master.
2616          */
2617         for (i = 1; i <= np; ++i) {
2618                 /* Check whether Infiniband port is populated. */
2619                 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i);
2620                 if (!ifindex)
2621                         continue;
2622                 if (!if_indextoname(ifindex, ifname))
2623                         continue;
2624                 /* Try to read bonding slave names from sysfs. */
2625                 MKSTR(slaves,
2626                       "/sys/class/net/%s/master/bonding/slaves", ifname);
2627                 file = fopen(slaves, "r");
2628                 if (file)
2629                         break;
2630         }
2631         if (!file)
2632                 return -1;
2633         /* Use safe format to check maximal buffer length. */
2634         assert(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE);
2635         while (fscanf(file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) {
2636                 char tmp_str[IF_NAMESIZE + 32];
2637                 struct rte_pci_addr pci_addr;
2638                 struct mlx5_switch_info info;
2639
2640                 /* Process slave interface names in the loop. */
2641                 snprintf(tmp_str, sizeof(tmp_str),
2642                          "/sys/class/net/%s", ifname);
2643                 if (mlx5_dev_to_pci_addr(tmp_str, &pci_addr)) {
2644                         DRV_LOG(WARNING, "can not get PCI address"
2645                                          " for netdev \"%s\"", ifname);
2646                         continue;
2647                 }
2648                 if (pci_dev->addr.domain != pci_addr.domain ||
2649                     pci_dev->addr.bus != pci_addr.bus ||
2650                     pci_dev->addr.devid != pci_addr.devid ||
2651                     pci_dev->addr.function != pci_addr.function)
2652                         continue;
2653                 /* Slave interface PCI address match found. */
2654                 fclose(file);
2655                 snprintf(tmp_str, sizeof(tmp_str),
2656                          "/sys/class/net/%s/phys_port_name", ifname);
2657                 file = fopen(tmp_str, "rb");
2658                 if (!file)
2659                         break;
2660                 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET;
2661                 if (fscanf(file, "%32s", tmp_str) == 1)
2662                         mlx5_translate_port_name(tmp_str, &info);
2663                 if (info.name_type == MLX5_PHYS_PORT_NAME_TYPE_LEGACY ||
2664                     info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK)
2665                         pf = info.port_name;
2666                 break;
2667         }
2668         if (file)
2669                 fclose(file);
2670         return pf;
2671 }
2672
2673 /**
2674  * DPDK callback to register a PCI device.
2675  *
2676  * This function spawns Ethernet devices out of a given PCI device.
2677  *
2678  * @param[in] pci_drv
2679  *   PCI driver structure (mlx5_driver).
2680  * @param[in] pci_dev
2681  *   PCI device information.
2682  *
2683  * @return
2684  *   0 on success, a negative errno value otherwise and rte_errno is set.
2685  */
2686 static int
2687 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2688                struct rte_pci_device *pci_dev)
2689 {
2690         struct ibv_device **ibv_list;
2691         /*
2692          * Number of found IB Devices matching with requested PCI BDF.
2693          * nd != 1 means there are multiple IB devices over the same
2694          * PCI device and we have representors and master.
2695          */
2696         unsigned int nd = 0;
2697         /*
2698          * Number of found IB device Ports. nd = 1 and np = 1..n means
2699          * we have the single multiport IB device, and there may be
2700          * representors attached to some of found ports.
2701          */
2702         unsigned int np = 0;
2703         /*
2704          * Number of DPDK ethernet devices to Spawn - either over
2705          * multiple IB devices or multiple ports of single IB device.
2706          * Actually this is the number of iterations to spawn.
2707          */
2708         unsigned int ns = 0;
2709         /*
2710          * Bonding device
2711          *   < 0 - no bonding device (single one)
2712          *  >= 0 - bonding device (value is slave PF index)
2713          */
2714         int bd = -1;
2715         struct mlx5_dev_spawn_data *list = NULL;
2716         struct mlx5_dev_config dev_config;
2717         int ret;
2718
2719         ret = mlx5_init_once();
2720         if (ret) {
2721                 DRV_LOG(ERR, "unable to init PMD global data: %s",
2722                         strerror(rte_errno));
2723                 return -rte_errno;
2724         }
2725         assert(pci_drv == &mlx5_driver);
2726         errno = 0;
2727         ibv_list = mlx5_glue->get_device_list(&ret);
2728         if (!ibv_list) {
2729                 rte_errno = errno ? errno : ENOSYS;
2730                 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?");
2731                 return -rte_errno;
2732         }
2733         /*
2734          * First scan the list of all Infiniband devices to find
2735          * matching ones, gathering into the list.
2736          */
2737         struct ibv_device *ibv_match[ret + 1];
2738         int nl_route = mlx5_nl_init(NETLINK_ROUTE);
2739         int nl_rdma = mlx5_nl_init(NETLINK_RDMA);
2740         unsigned int i;
2741
2742         while (ret-- > 0) {
2743                 struct rte_pci_addr pci_addr;
2744
2745                 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name);
2746                 bd = mlx5_device_bond_pci_match
2747                                 (ibv_list[ret], pci_dev, nl_rdma);
2748                 if (bd >= 0) {
2749                         /*
2750                          * Bonding device detected. Only one match is allowed,
2751                          * the bonding is supported over multi-port IB device,
2752                          * there should be no matches on representor PCI
2753                          * functions or non VF LAG bonding devices with
2754                          * specified address.
2755                          */
2756                         if (nd) {
2757                                 DRV_LOG(ERR,
2758                                         "multiple PCI match on bonding device"
2759                                         "\"%s\" found", ibv_list[ret]->name);
2760                                 rte_errno = ENOENT;
2761                                 ret = -rte_errno;
2762                                 goto exit;
2763                         }
2764                         DRV_LOG(INFO, "PCI information matches for"
2765                                       " slave %d bonding device \"%s\"",
2766                                       bd, ibv_list[ret]->name);
2767                         ibv_match[nd++] = ibv_list[ret];
2768                         break;
2769                 }
2770                 if (mlx5_dev_to_pci_addr
2771                         (ibv_list[ret]->ibdev_path, &pci_addr))
2772                         continue;
2773                 if (pci_dev->addr.domain != pci_addr.domain ||
2774                     pci_dev->addr.bus != pci_addr.bus ||
2775                     pci_dev->addr.devid != pci_addr.devid ||
2776                     pci_dev->addr.function != pci_addr.function)
2777                         continue;
2778                 DRV_LOG(INFO, "PCI information matches for device \"%s\"",
2779                         ibv_list[ret]->name);
2780                 ibv_match[nd++] = ibv_list[ret];
2781         }
2782         ibv_match[nd] = NULL;
2783         if (!nd) {
2784                 /* No device matches, just complain and bail out. */
2785                 DRV_LOG(WARNING,
2786                         "no Verbs device matches PCI device " PCI_PRI_FMT ","
2787                         " are kernel drivers loaded?",
2788                         pci_dev->addr.domain, pci_dev->addr.bus,
2789                         pci_dev->addr.devid, pci_dev->addr.function);
2790                 rte_errno = ENOENT;
2791                 ret = -rte_errno;
2792                 goto exit;
2793         }
2794         if (nd == 1) {
2795                 /*
2796                  * Found single matching device may have multiple ports.
2797                  * Each port may be representor, we have to check the port
2798                  * number and check the representors existence.
2799                  */
2800                 if (nl_rdma >= 0)
2801                         np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name);
2802                 if (!np)
2803                         DRV_LOG(WARNING, "can not get IB device \"%s\""
2804                                          " ports number", ibv_match[0]->name);
2805                 if (bd >= 0 && !np) {
2806                         DRV_LOG(ERR, "can not get ports"
2807                                      " for bonding device");
2808                         rte_errno = ENOENT;
2809                         ret = -rte_errno;
2810                         goto exit;
2811                 }
2812         }
2813 #ifndef HAVE_MLX5DV_DR_DEVX_PORT
2814         if (bd >= 0) {
2815                 /*
2816                  * This may happen if there is VF LAG kernel support and
2817                  * application is compiled with older rdma_core library.
2818                  */
2819                 DRV_LOG(ERR,
2820                         "No kernel/verbs support for VF LAG bonding found.");
2821                 rte_errno = ENOTSUP;
2822                 ret = -rte_errno;
2823                 goto exit;
2824         }
2825 #endif
2826         /*
2827          * Now we can determine the maximal
2828          * amount of devices to be spawned.
2829          */
2830         list = rte_zmalloc("device spawn data",
2831                          sizeof(struct mlx5_dev_spawn_data) *
2832                          (np ? np : nd),
2833                          RTE_CACHE_LINE_SIZE);
2834         if (!list) {
2835                 DRV_LOG(ERR, "spawn data array allocation failure");
2836                 rte_errno = ENOMEM;
2837                 ret = -rte_errno;
2838                 goto exit;
2839         }
2840         if (bd >= 0 || np > 1) {
2841                 /*
2842                  * Single IB device with multiple ports found,
2843                  * it may be E-Switch master device and representors.
2844                  * We have to perform identification trough the ports.
2845                  */
2846                 assert(nl_rdma >= 0);
2847                 assert(ns == 0);
2848                 assert(nd == 1);
2849                 assert(np);
2850                 for (i = 1; i <= np; ++i) {
2851                         list[ns].max_port = np;
2852                         list[ns].ibv_port = i;
2853                         list[ns].ibv_dev = ibv_match[0];
2854                         list[ns].eth_dev = NULL;
2855                         list[ns].pci_dev = pci_dev;
2856                         list[ns].pf_bond = bd;
2857                         list[ns].ifindex = mlx5_nl_ifindex
2858                                         (nl_rdma, list[ns].ibv_dev->name, i);
2859                         if (!list[ns].ifindex) {
2860                                 /*
2861                                  * No network interface index found for the
2862                                  * specified port, it means there is no
2863                                  * representor on this port. It's OK,
2864                                  * there can be disabled ports, for example
2865                                  * if sriov_numvfs < sriov_totalvfs.
2866                                  */
2867                                 continue;
2868                         }
2869                         ret = -1;
2870                         if (nl_route >= 0)
2871                                 ret = mlx5_nl_switch_info
2872                                                (nl_route,
2873                                                 list[ns].ifindex,
2874                                                 &list[ns].info);
2875                         if (ret || (!list[ns].info.representor &&
2876                                     !list[ns].info.master)) {
2877                                 /*
2878                                  * We failed to recognize representors with
2879                                  * Netlink, let's try to perform the task
2880                                  * with sysfs.
2881                                  */
2882                                 ret =  mlx5_sysfs_switch_info
2883                                                 (list[ns].ifindex,
2884                                                  &list[ns].info);
2885                         }
2886                         if (!ret && bd >= 0) {
2887                                 switch (list[ns].info.name_type) {
2888                                 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK:
2889                                         if (list[ns].info.port_name == bd)
2890                                                 ns++;
2891                                         break;
2892                                 case MLX5_PHYS_PORT_NAME_TYPE_PFVF:
2893                                         if (list[ns].info.pf_num == bd)
2894                                                 ns++;
2895                                         break;
2896                                 default:
2897                                         break;
2898                                 }
2899                                 continue;
2900                         }
2901                         if (!ret && (list[ns].info.representor ^
2902                                      list[ns].info.master))
2903                                 ns++;
2904                 }
2905                 if (!ns) {
2906                         DRV_LOG(ERR,
2907                                 "unable to recognize master/representors"
2908                                 " on the IB device with multiple ports");
2909                         rte_errno = ENOENT;
2910                         ret = -rte_errno;
2911                         goto exit;
2912                 }
2913         } else {
2914                 /*
2915                  * The existence of several matching entries (nd > 1) means
2916                  * port representors have been instantiated. No existing Verbs
2917                  * call nor sysfs entries can tell them apart, this can only
2918                  * be done through Netlink calls assuming kernel drivers are
2919                  * recent enough to support them.
2920                  *
2921                  * In the event of identification failure through Netlink,
2922                  * try again through sysfs, then:
2923                  *
2924                  * 1. A single IB device matches (nd == 1) with single
2925                  *    port (np=0/1) and is not a representor, assume
2926                  *    no switch support.
2927                  *
2928                  * 2. Otherwise no safe assumptions can be made;
2929                  *    complain louder and bail out.
2930                  */
2931                 np = 1;
2932                 for (i = 0; i != nd; ++i) {
2933                         memset(&list[ns].info, 0, sizeof(list[ns].info));
2934                         list[ns].max_port = 1;
2935                         list[ns].ibv_port = 1;
2936                         list[ns].ibv_dev = ibv_match[i];
2937                         list[ns].eth_dev = NULL;
2938                         list[ns].pci_dev = pci_dev;
2939                         list[ns].pf_bond = -1;
2940                         list[ns].ifindex = 0;
2941                         if (nl_rdma >= 0)
2942                                 list[ns].ifindex = mlx5_nl_ifindex
2943                                         (nl_rdma, list[ns].ibv_dev->name, 1);
2944                         if (!list[ns].ifindex) {
2945                                 char ifname[IF_NAMESIZE];
2946
2947                                 /*
2948                                  * Netlink failed, it may happen with old
2949                                  * ib_core kernel driver (before 4.16).
2950                                  * We can assume there is old driver because
2951                                  * here we are processing single ports IB
2952                                  * devices. Let's try sysfs to retrieve
2953                                  * the ifindex. The method works for
2954                                  * master device only.
2955                                  */
2956                                 if (nd > 1) {
2957                                         /*
2958                                          * Multiple devices found, assume
2959                                          * representors, can not distinguish
2960                                          * master/representor and retrieve
2961                                          * ifindex via sysfs.
2962                                          */
2963                                         continue;
2964                                 }
2965                                 ret = mlx5_get_master_ifname
2966                                         (ibv_match[i]->ibdev_path, &ifname);
2967                                 if (!ret)
2968                                         list[ns].ifindex =
2969                                                 if_nametoindex(ifname);
2970                                 if (!list[ns].ifindex) {
2971                                         /*
2972                                          * No network interface index found
2973                                          * for the specified device, it means
2974                                          * there it is neither representor
2975                                          * nor master.
2976                                          */
2977                                         continue;
2978                                 }
2979                         }
2980                         ret = -1;
2981                         if (nl_route >= 0)
2982                                 ret = mlx5_nl_switch_info
2983                                                (nl_route,
2984                                                 list[ns].ifindex,
2985                                                 &list[ns].info);
2986                         if (ret || (!list[ns].info.representor &&
2987                                     !list[ns].info.master)) {
2988                                 /*
2989                                  * We failed to recognize representors with
2990                                  * Netlink, let's try to perform the task
2991                                  * with sysfs.
2992                                  */
2993                                 ret =  mlx5_sysfs_switch_info
2994                                                 (list[ns].ifindex,
2995                                                  &list[ns].info);
2996                         }
2997                         if (!ret && (list[ns].info.representor ^
2998                                      list[ns].info.master)) {
2999                                 ns++;
3000                         } else if ((nd == 1) &&
3001                                    !list[ns].info.representor &&
3002                                    !list[ns].info.master) {
3003                                 /*
3004                                  * Single IB device with
3005                                  * one physical port and
3006                                  * attached network device.
3007                                  * May be SRIOV is not enabled
3008                                  * or there is no representors.
3009                                  */
3010                                 DRV_LOG(INFO, "no E-Switch support detected");
3011                                 ns++;
3012                                 break;
3013                         }
3014                 }
3015                 if (!ns) {
3016                         DRV_LOG(ERR,
3017                                 "unable to recognize master/representors"
3018                                 " on the multiple IB devices");
3019                         rte_errno = ENOENT;
3020                         ret = -rte_errno;
3021                         goto exit;
3022                 }
3023         }
3024         assert(ns);
3025         /*
3026          * Sort list to probe devices in natural order for users convenience
3027          * (i.e. master first, then representors from lowest to highest ID).
3028          */
3029         qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp);
3030         /* Default configuration. */
3031         dev_config = (struct mlx5_dev_config){
3032                 .hw_padding = 0,
3033                 .mps = MLX5_ARG_UNSET,
3034                 .rx_vec_en = 1,
3035                 .txq_inline_max = MLX5_ARG_UNSET,
3036                 .txq_inline_min = MLX5_ARG_UNSET,
3037                 .txq_inline_mpw = MLX5_ARG_UNSET,
3038                 .txqs_inline = MLX5_ARG_UNSET,
3039                 .vf_nl_en = 1,
3040                 .mr_ext_memseg_en = 1,
3041                 .mprq = {
3042                         .enabled = 0, /* Disabled by default. */
3043                         .stride_num_n = MLX5_MPRQ_STRIDE_NUM_N,
3044                         .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
3045                         .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
3046                 },
3047                 .dv_esw_en = 1,
3048         };
3049         /* Device specific configuration. */
3050         switch (pci_dev->id.device_id) {
3051         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
3052         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
3053         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
3054         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
3055         case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF:
3056         case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF:
3057         case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF:
3058                 dev_config.vf = 1;
3059                 break;
3060         default:
3061                 break;
3062         }
3063         for (i = 0; i != ns; ++i) {
3064                 uint32_t restore;
3065
3066                 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device,
3067                                                  &list[i],
3068                                                  dev_config);
3069                 if (!list[i].eth_dev) {
3070                         if (rte_errno != EBUSY && rte_errno != EEXIST)
3071                                 break;
3072                         /* Device is disabled or already spawned. Ignore it. */
3073                         continue;
3074                 }
3075                 restore = list[i].eth_dev->data->dev_flags;
3076                 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev);
3077                 /* Restore non-PCI flags cleared by the above call. */
3078                 list[i].eth_dev->data->dev_flags |= restore;
3079                 mlx5_dev_interrupt_handler_devx_install(list[i].eth_dev);
3080                 rte_eth_dev_probing_finish(list[i].eth_dev);
3081         }
3082         if (i != ns) {
3083                 DRV_LOG(ERR,
3084                         "probe of PCI device " PCI_PRI_FMT " aborted after"
3085                         " encountering an error: %s",
3086                         pci_dev->addr.domain, pci_dev->addr.bus,
3087                         pci_dev->addr.devid, pci_dev->addr.function,
3088                         strerror(rte_errno));
3089                 ret = -rte_errno;
3090                 /* Roll back. */
3091                 while (i--) {
3092                         if (!list[i].eth_dev)
3093                                 continue;
3094                         mlx5_dev_close(list[i].eth_dev);
3095                         /* mac_addrs must not be freed because in dev_private */
3096                         list[i].eth_dev->data->mac_addrs = NULL;
3097                         claim_zero(rte_eth_dev_release_port(list[i].eth_dev));
3098                 }
3099                 /* Restore original error. */
3100                 rte_errno = -ret;
3101         } else {
3102                 ret = 0;
3103         }
3104 exit:
3105         /*
3106          * Do the routine cleanup:
3107          * - close opened Netlink sockets
3108          * - free allocated spawn data array
3109          * - free the Infiniband device list
3110          */
3111         if (nl_rdma >= 0)
3112                 close(nl_rdma);
3113         if (nl_route >= 0)
3114                 close(nl_route);
3115         if (list)
3116                 rte_free(list);
3117         assert(ibv_list);
3118         mlx5_glue->free_device_list(ibv_list);
3119         return ret;
3120 }
3121
3122 /**
3123  * Look for the ethernet device belonging to mlx5 driver.
3124  *
3125  * @param[in] port_id
3126  *   port_id to start looking for device.
3127  * @param[in] pci_dev
3128  *   Pointer to the hint PCI device. When device is being probed
3129  *   the its siblings (master and preceding representors might
3130  *   not have assigned driver yet (because the mlx5_pci_probe()
3131  *   is not completed yet, for this case match on hint PCI
3132  *   device may be used to detect sibling device.
3133  *
3134  * @return
3135  *   port_id of found device, RTE_MAX_ETHPORT if not found.
3136  */
3137 uint16_t
3138 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
3139 {
3140         while (port_id < RTE_MAX_ETHPORTS) {
3141                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
3142
3143                 if (dev->state != RTE_ETH_DEV_UNUSED &&
3144                     dev->device &&
3145                     (dev->device == &pci_dev->device ||
3146                      (dev->device->driver &&
3147                      dev->device->driver->name &&
3148                      !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
3149                         break;
3150                 port_id++;
3151         }
3152         if (port_id >= RTE_MAX_ETHPORTS)
3153                 return RTE_MAX_ETHPORTS;
3154         return port_id;
3155 }
3156
3157 /**
3158  * DPDK callback to remove a PCI device.
3159  *
3160  * This function removes all Ethernet devices belong to a given PCI device.
3161  *
3162  * @param[in] pci_dev
3163  *   Pointer to the PCI device.
3164  *
3165  * @return
3166  *   0 on success, the function cannot fail.
3167  */
3168 static int
3169 mlx5_pci_remove(struct rte_pci_device *pci_dev)
3170 {
3171         uint16_t port_id;
3172
3173         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device)
3174                 rte_eth_dev_close(port_id);
3175         return 0;
3176 }
3177
3178 static const struct rte_pci_id mlx5_pci_id_map[] = {
3179         {
3180                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3181                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
3182         },
3183         {
3184                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3185                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
3186         },
3187         {
3188                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3189                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
3190         },
3191         {
3192                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3193                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
3194         },
3195         {
3196                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3197                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
3198         },
3199         {
3200                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3201                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
3202         },
3203         {
3204                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3205                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
3206         },
3207         {
3208                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3209                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
3210         },
3211         {
3212                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3213                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
3214         },
3215         {
3216                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3217                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
3218         },
3219         {
3220                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3221                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
3222         },
3223         {
3224                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3225                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
3226         },
3227         {
3228                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3229                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
3230         },
3231         {
3232                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3233                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
3234         },
3235         {
3236                 .vendor_id = 0
3237         }
3238 };
3239
3240 static struct rte_pci_driver mlx5_driver = {
3241         .driver = {
3242                 .name = MLX5_DRIVER_NAME
3243         },
3244         .id_table = mlx5_pci_id_map,
3245         .probe = mlx5_pci_probe,
3246         .remove = mlx5_pci_remove,
3247         .dma_map = mlx5_dma_map,
3248         .dma_unmap = mlx5_dma_unmap,
3249         .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV |
3250                      RTE_PCI_DRV_PROBE_AGAIN,
3251 };
3252
3253 #ifdef RTE_IBVERBS_LINK_DLOPEN
3254
3255 /**
3256  * Suffix RTE_EAL_PMD_PATH with "-glue".
3257  *
3258  * This function performs a sanity check on RTE_EAL_PMD_PATH before
3259  * suffixing its last component.
3260  *
3261  * @param buf[out]
3262  *   Output buffer, should be large enough otherwise NULL is returned.
3263  * @param size
3264  *   Size of @p out.
3265  *
3266  * @return
3267  *   Pointer to @p buf or @p NULL in case suffix cannot be appended.
3268  */
3269 static char *
3270 mlx5_glue_path(char *buf, size_t size)
3271 {
3272         static const char *const bad[] = { "/", ".", "..", NULL };
3273         const char *path = RTE_EAL_PMD_PATH;
3274         size_t len = strlen(path);
3275         size_t off;
3276         int i;
3277
3278         while (len && path[len - 1] == '/')
3279                 --len;
3280         for (off = len; off && path[off - 1] != '/'; --off)
3281                 ;
3282         for (i = 0; bad[i]; ++i)
3283                 if (!strncmp(path + off, bad[i], (int)(len - off)))
3284                         goto error;
3285         i = snprintf(buf, size, "%.*s-glue", (int)len, path);
3286         if (i == -1 || (size_t)i >= size)
3287                 goto error;
3288         return buf;
3289 error:
3290         DRV_LOG(ERR,
3291                 "unable to append \"-glue\" to last component of"
3292                 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\"),"
3293                 " please re-configure DPDK");
3294         return NULL;
3295 }
3296
3297 /**
3298  * Initialization routine for run-time dependency on rdma-core.
3299  */
3300 static int
3301 mlx5_glue_init(void)
3302 {
3303         char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")];
3304         const char *path[] = {
3305                 /*
3306                  * A basic security check is necessary before trusting
3307                  * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH.
3308                  */
3309                 (geteuid() == getuid() && getegid() == getgid() ?
3310                  getenv("MLX5_GLUE_PATH") : NULL),
3311                 /*
3312                  * When RTE_EAL_PMD_PATH is set, use its glue-suffixed
3313                  * variant, otherwise let dlopen() look up libraries on its
3314                  * own.
3315                  */
3316                 (*RTE_EAL_PMD_PATH ?
3317                  mlx5_glue_path(glue_path, sizeof(glue_path)) : ""),
3318         };
3319         unsigned int i = 0;
3320         void *handle = NULL;
3321         void **sym;
3322         const char *dlmsg;
3323
3324         while (!handle && i != RTE_DIM(path)) {
3325                 const char *end;
3326                 size_t len;
3327                 int ret;
3328
3329                 if (!path[i]) {
3330                         ++i;
3331                         continue;
3332                 }
3333                 end = strpbrk(path[i], ":;");
3334                 if (!end)
3335                         end = path[i] + strlen(path[i]);
3336                 len = end - path[i];
3337                 ret = 0;
3338                 do {
3339                         char name[ret + 1];
3340
3341                         ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE,
3342                                        (int)len, path[i],
3343                                        (!len || *(end - 1) == '/') ? "" : "/");
3344                         if (ret == -1)
3345                                 break;
3346                         if (sizeof(name) != (size_t)ret + 1)
3347                                 continue;
3348                         DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"",
3349                                 name);
3350                         handle = dlopen(name, RTLD_LAZY);
3351                         break;
3352                 } while (1);
3353                 path[i] = end + 1;
3354                 if (!*end)
3355                         ++i;
3356         }
3357         if (!handle) {
3358                 rte_errno = EINVAL;
3359                 dlmsg = dlerror();
3360                 if (dlmsg)
3361                         DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg);
3362                 goto glue_error;
3363         }
3364         sym = dlsym(handle, "mlx5_glue");
3365         if (!sym || !*sym) {
3366                 rte_errno = EINVAL;
3367                 dlmsg = dlerror();
3368                 if (dlmsg)
3369                         DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg);
3370                 goto glue_error;
3371         }
3372         mlx5_glue = *sym;
3373         return 0;
3374 glue_error:
3375         if (handle)
3376                 dlclose(handle);
3377         DRV_LOG(WARNING,
3378                 "cannot initialize PMD due to missing run-time dependency on"
3379                 " rdma-core libraries (libibverbs, libmlx5)");
3380         return -rte_errno;
3381 }
3382
3383 #endif
3384
3385 /**
3386  * Driver initialization routine.
3387  */
3388 RTE_INIT(rte_mlx5_pmd_init)
3389 {
3390         /* Initialize driver log type. */
3391         mlx5_logtype = rte_log_register("pmd.net.mlx5");
3392         if (mlx5_logtype >= 0)
3393                 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
3394
3395         /* Build the static tables for Verbs conversion. */
3396         mlx5_set_ptype_table();
3397         mlx5_set_cksum_table();
3398         mlx5_set_swp_types_table();
3399         /*
3400          * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
3401          * huge pages. Calling ibv_fork_init() during init allows
3402          * applications to use fork() safely for purposes other than
3403          * using this PMD, which is not supported in forked processes.
3404          */
3405         setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
3406         /* Match the size of Rx completion entry to the size of a cacheline. */
3407         if (RTE_CACHE_LINE_SIZE == 128)
3408                 setenv("MLX5_CQE_SIZE", "128", 0);
3409         /*
3410          * MLX5_DEVICE_FATAL_CLEANUP tells ibv_destroy functions to
3411          * cleanup all the Verbs resources even when the device was removed.
3412          */
3413         setenv("MLX5_DEVICE_FATAL_CLEANUP", "1", 1);
3414 #ifdef RTE_IBVERBS_LINK_DLOPEN
3415         if (mlx5_glue_init())
3416                 return;
3417         assert(mlx5_glue);
3418 #endif
3419 #ifndef NDEBUG
3420         /* Glue structure must not contain any NULL pointers. */
3421         {
3422                 unsigned int i;
3423
3424                 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i)
3425                         assert(((const void *const *)mlx5_glue)[i]);
3426         }
3427 #endif
3428         if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) {
3429                 DRV_LOG(ERR,
3430                         "rdma-core glue \"%s\" mismatch: \"%s\" is required",
3431                         mlx5_glue->version, MLX5_GLUE_VERSION);
3432                 return;
3433         }
3434         mlx5_glue->fork_init();
3435         rte_pci_register(&mlx5_driver);
3436 }
3437
3438 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
3439 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
3440 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");