drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12 #include <net/if.h>
  13 #include <sys/mman.h>
  14 #include <linux/rtnetlink.h>
  15
  16 #include <rte_malloc.h>
  17 #include <rte_ethdev_driver.h>
  18 #include <rte_ethdev_pci.h>
  19 #include <rte_pci.h>
  20 #include <rte_bus_pci.h>
  21 #include <rte_common.h>
  22 #include <rte_kvargs.h>
  23 #include <rte_rwlock.h>
  24 #include <rte_spinlock.h>
  25 #include <rte_string_fns.h>
  26 #include <rte_alarm.h>
  27
  28 #include <mlx5_glue.h>
  29 #include <mlx5_devx_cmds.h>
  30 #include <mlx5_common.h>
  31 #include <mlx5_common_os.h>
  32 #include <mlx5_common_mp.h>
  33 #include <mlx5_malloc.h>
  34
  35 #include "mlx5_defs.h"
  36 #include "mlx5.h"
  37 #include "mlx5_utils.h"
  38 #include "mlx5_rxtx.h"
  39 #include "mlx5_autoconf.h"
  40 #include "mlx5_mr.h"
  41 #include "mlx5_flow.h"
  42 #include "rte_pmd_mlx5.h"
  43
  44 /* Device parameter to enable RX completion queue compression. */
  45 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  46
  47 /* Device parameter to enable RX completion entry padding to 128B. */
  48 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
  49
  50 /* Device parameter to enable padding Rx packet to cacheline size. */
  51 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  52
  53 /* Device parameter to enable Multi-Packet Rx queue. */
  54 #define MLX5_RX_MPRQ_EN "mprq_en"
  55
  56 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  57 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  58
  59 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  60 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  61
  62 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  63 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  64
  65 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  66 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  67
  68 /* Device parameter to configure inline send. Deprecated, ignored.*/
  69 #define MLX5_TXQ_INLINE "txq_inline"
  70
  71 /* Device parameter to limit packet size to inline with ordinary SEND. */
  72 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  73
  74 /* Device parameter to configure minimal data size to inline. */
  75 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  76
  77 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  78 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  79
  80 /*
  81  * Device parameter to configure the number of TX queues threshold for
  82  * enabling inline send.
  83  */
  84 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  85
  86 /*
  87  * Device parameter to configure the number of TX queues threshold for
  88  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  89  */
  90 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  91
  92 /* Device parameter to enable multi-packet send WQEs. */
  93 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  94
  95 /*
  96  * Device parameter to force doorbell register mapping
  97  * to non-cahed region eliminating the extra write memory barrier.
  98  */
  99 #define MLX5_TX_DB_NC "tx_db_nc"
 100
 101 /*
 102  * Device parameter to include 2 dsegs in the title WQEBB.
 103  * Deprecated, ignored.
 104  */
 105 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 106
 107 /*
 108  * Device parameter to limit the size of inlining packet.
 109  * Deprecated, ignored.
 110  */
 111 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 112
 113 /*
 114  * Device parameter to enable Tx scheduling on timestamps
 115  * and specify the packet pacing granularity in nanoseconds.
 116  */
 117 #define MLX5_TX_PP "tx_pp"
 118
 119 /*
 120  * Device parameter to specify skew in nanoseconds on Tx datapath,
 121  * it represents the time between SQ start WQE processing and
 122  * appearing actual packet data on the wire.
 123  */
 124 #define MLX5_TX_SKEW "tx_skew"
 125
 126 /*
 127  * Device parameter to enable hardware Tx vector.
 128  * Deprecated, ignored (no vectorized Tx routines anymore).
 129  */
 130 #define MLX5_TX_VEC_EN "tx_vec_en"
 131
 132 /* Device parameter to enable hardware Rx vector. */
 133 #define MLX5_RX_VEC_EN "rx_vec_en"
 134
 135 /* Allow L3 VXLAN flow creation. */
 136 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 137
 138 /* Activate DV E-Switch flow steering. */
 139 #define MLX5_DV_ESW_EN "dv_esw_en"
 140
 141 /* Activate DV flow steering. */
 142 #define MLX5_DV_FLOW_EN "dv_flow_en"
 143
 144 /* Enable extensive flow metadata support. */
 145 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 146
 147 /* Device parameter to let the user manage the lacp traffic of bonded device */
 148 #define MLX5_LACP_BY_USER "lacp_by_user"
 149
 150 /* Activate Netlink support in VF mode. */
 151 #define MLX5_VF_NL_EN "vf_nl_en"
 152
 153 /* Enable extending memsegs when creating a MR. */
 154 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 155
 156 /* Select port representors to instantiate. */
 157 #define MLX5_REPRESENTOR "representor"
 158
 159 /* Device parameter to configure the maximum number of dump files per queue. */
 160 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 161
 162 /* Configure timeout of LRO session (in microseconds). */
 163 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 164
 165 /*
 166  * Device parameter to configure the total data buffer size for a single
 167  * hairpin queue (logarithm value).
 168  */
 169 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 170
 171 /* Flow memory reclaim mode. */
 172 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 173
 174 /* The default memory allocator used in PMD. */
 175 #define MLX5_SYS_MEM_EN "sys_mem_en"
 176 /* Decap will be used or not. */
 177 #define MLX5_DECAP_EN "decap_en"
 178
 179 /* Shared memory between primary and secondary processes. */
 180 struct mlx5_shared_data *mlx5_shared_data;
 181
 182 /** Driver-specific log messages type. */
 183 int mlx5_logtype;
 184
 185 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 186                                                 LIST_HEAD_INITIALIZER();
 187 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
 188
 189 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 190 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 191         {
 192                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 193                 .trunk_size = 64,
 194                 .grow_trunk = 3,
 195                 .grow_shift = 2,
 196                 .need_lock = 0,
 197                 .release_mem_en = 1,
 198                 .malloc = mlx5_malloc,
 199                 .free = mlx5_free,
 200                 .type = "mlx5_encap_decap_ipool",
 201         },
 202         {
 203                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 204                 .trunk_size = 64,
 205                 .grow_trunk = 3,
 206                 .grow_shift = 2,
 207                 .need_lock = 0,
 208                 .release_mem_en = 1,
 209                 .malloc = mlx5_malloc,
 210                 .free = mlx5_free,
 211                 .type = "mlx5_push_vlan_ipool",
 212         },
 213         {
 214                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 215                 .trunk_size = 64,
 216                 .grow_trunk = 3,
 217                 .grow_shift = 2,
 218                 .need_lock = 0,
 219                 .release_mem_en = 1,
 220                 .malloc = mlx5_malloc,
 221                 .free = mlx5_free,
 222                 .type = "mlx5_tag_ipool",
 223         },
 224         {
 225                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 226                 .trunk_size = 64,
 227                 .grow_trunk = 3,
 228                 .grow_shift = 2,
 229                 .need_lock = 0,
 230                 .release_mem_en = 1,
 231                 .malloc = mlx5_malloc,
 232                 .free = mlx5_free,
 233                 .type = "mlx5_port_id_ipool",
 234         },
 235         {
 236                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 237                 .trunk_size = 64,
 238                 .grow_trunk = 3,
 239                 .grow_shift = 2,
 240                 .need_lock = 0,
 241                 .release_mem_en = 1,
 242                 .malloc = mlx5_malloc,
 243                 .free = mlx5_free,
 244                 .type = "mlx5_jump_ipool",
 245         },
 246 #endif
 247         {
 248                 .size = sizeof(struct mlx5_flow_meter),
 249                 .trunk_size = 64,
 250                 .grow_trunk = 3,
 251                 .grow_shift = 2,
 252                 .need_lock = 0,
 253                 .release_mem_en = 1,
 254                 .malloc = mlx5_malloc,
 255                 .free = mlx5_free,
 256                 .type = "mlx5_meter_ipool",
 257         },
 258         {
 259                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 260                 .trunk_size = 64,
 261                 .grow_trunk = 3,
 262                 .grow_shift = 2,
 263                 .need_lock = 0,
 264                 .release_mem_en = 1,
 265                 .malloc = mlx5_malloc,
 266                 .free = mlx5_free,
 267                 .type = "mlx5_mcp_ipool",
 268         },
 269         {
 270                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 271                 .trunk_size = 64,
 272                 .grow_trunk = 3,
 273                 .grow_shift = 2,
 274                 .need_lock = 0,
 275                 .release_mem_en = 1,
 276                 .malloc = mlx5_malloc,
 277                 .free = mlx5_free,
 278                 .type = "mlx5_hrxq_ipool",
 279         },
 280         {
 281                 /*
 282                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 283                  * It set in run time according to PCI function configuration.
 284                  */
 285                 .size = 0,
 286                 .trunk_size = 64,
 287                 .grow_trunk = 3,
 288                 .grow_shift = 2,
 289                 .need_lock = 0,
 290                 .release_mem_en = 1,
 291                 .malloc = mlx5_malloc,
 292                 .free = mlx5_free,
 293                 .type = "mlx5_flow_handle_ipool",
 294         },
 295         {
 296                 .size = sizeof(struct rte_flow),
 297                 .trunk_size = 4096,
 298                 .need_lock = 1,
 299                 .release_mem_en = 1,
 300                 .malloc = mlx5_malloc,
 301                 .free = mlx5_free,
 302                 .type = "rte_flow_ipool",
 303         },
 304 };
 305
 306
 307 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 308 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 309
 310 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 311
 312 /**
 313  * Allocate ID pool structure.
 314  *
 315  * @param[in] max_id
 316  *   The maximum id can be allocated from the pool.
 317  *
 318  * @return
 319  *   Pointer to pool object, NULL value otherwise.
 320  */
 321 struct mlx5_flow_id_pool *
 322 mlx5_flow_id_pool_alloc(uint32_t max_id)
 323 {
 324         struct mlx5_flow_id_pool *pool;
 325         void *mem;
 326
 327         pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool),
 328                            RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 329         if (!pool) {
 330                 DRV_LOG(ERR, "can't allocate id pool");
 331                 rte_errno  = ENOMEM;
 332                 return NULL;
 333         }
 334         mem = mlx5_malloc(MLX5_MEM_ZERO,
 335                           MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
 336                           RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 337         if (!mem) {
 338                 DRV_LOG(ERR, "can't allocate mem for id pool");
 339                 rte_errno  = ENOMEM;
 340                 goto error;
 341         }
 342         pool->free_arr = mem;
 343         pool->curr = pool->free_arr;
 344         pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
 345         pool->base_index = 0;
 346         pool->max_id = max_id;
 347         return pool;
 348 error:
 349         mlx5_free(pool);
 350         return NULL;
 351 }
 352
 353 /**
 354  * Release ID pool structure.
 355  *
 356  * @param[in] pool
 357  *   Pointer to flow id pool object to free.
 358  */
 359 void
 360 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
 361 {
 362         mlx5_free(pool->free_arr);
 363         mlx5_free(pool);
 364 }
 365
 366 /**
 367  * Generate ID.
 368  *
 369  * @param[in] pool
 370  *   Pointer to flow id pool.
 371  * @param[out] id
 372  *   The generated ID.
 373  *
 374  * @return
 375  *   0 on success, error value otherwise.
 376  */
 377 uint32_t
 378 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
 379 {
 380         if (pool->curr == pool->free_arr) {
 381                 if (pool->base_index == pool->max_id) {
 382                         rte_errno  = ENOMEM;
 383                         DRV_LOG(ERR, "no free id");
 384                         return -rte_errno;
 385                 }
 386                 *id = ++pool->base_index;
 387                 return 0;
 388         }
 389         *id = *(--pool->curr);
 390         return 0;
 391 }
 392
 393 /**
 394  * Release ID.
 395  *
 396  * @param[in] pool
 397  *   Pointer to flow id pool.
 398  * @param[out] id
 399  *   The generated ID.
 400  *
 401  * @return
 402  *   0 on success, error value otherwise.
 403  */
 404 uint32_t
 405 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
 406 {
 407         uint32_t size;
 408         uint32_t size2;
 409         void *mem;
 410
 411         if (pool->curr == pool->last) {
 412                 size = pool->curr - pool->free_arr;
 413                 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
 414                 MLX5_ASSERT(size2 > size);
 415                 mem = mlx5_malloc(0, size2 * sizeof(uint32_t), 0,
 416                                   SOCKET_ID_ANY);
 417                 if (!mem) {
 418                         DRV_LOG(ERR, "can't allocate mem for id pool");
 419                         rte_errno  = ENOMEM;
 420                         return -rte_errno;
 421                 }
 422                 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
 423                 mlx5_free(pool->free_arr);
 424                 pool->free_arr = mem;
 425                 pool->curr = pool->free_arr + size;
 426                 pool->last = pool->free_arr + size2;
 427         }
 428         *pool->curr = id;
 429         pool->curr++;
 430         return 0;
 431 }
 432
 433 /**
 434  * Initialize the shared aging list information per port.
 435  *
 436  * @param[in] sh
 437  *   Pointer to mlx5_dev_ctx_shared object.
 438  */
 439 static void
 440 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 441 {
 442         uint32_t i;
 443         struct mlx5_age_info *age_info;
 444
 445         for (i = 0; i < sh->max_port; i++) {
 446                 age_info = &sh->port[i].age_info;
 447                 age_info->flags = 0;
 448                 TAILQ_INIT(&age_info->aged_counters);
 449                 rte_spinlock_init(&age_info->aged_sl);
 450                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 451         }
 452 }
 453
 454 /**
 455  * Initialize the counters management structure.
 456  *
 457  * @param[in] sh
 458  *   Pointer to mlx5_dev_ctx_shared object to free
 459  */
 460 static void
 461 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 462 {
 463         int i;
 464
 465         memset(&sh->cmng, 0, sizeof(sh->cmng));
 466         TAILQ_INIT(&sh->cmng.flow_counters);
 467         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 468                 sh->cmng.ccont[i].min_id = MLX5_CNT_BATCH_OFFSET;
 469                 sh->cmng.ccont[i].max_id = -1;
 470                 sh->cmng.ccont[i].last_pool_idx = POOL_IDX_INVALID;
 471                 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
 472                 rte_spinlock_init(&sh->cmng.ccont[i].resize_sl);
 473                 TAILQ_INIT(&sh->cmng.ccont[i].counters);
 474                 rte_spinlock_init(&sh->cmng.ccont[i].csl);
 475         }
 476 }
 477
 478 /**
 479  * Destroy all the resources allocated for a counter memory management.
 480  *
 481  * @param[in] mng
 482  *   Pointer to the memory management structure.
 483  */
 484 static void
 485 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 486 {
 487         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 488
 489         LIST_REMOVE(mng, next);
 490         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 491         claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
 492         mlx5_free(mem);
 493 }
 494
 495 /**
 496  * Close and release all the resources of the counters management.
 497  *
 498  * @param[in] sh
 499  *   Pointer to mlx5_dev_ctx_shared object to free.
 500  */
 501 static void
 502 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 503 {
 504         struct mlx5_counter_stats_mem_mng *mng;
 505         int i;
 506         int j;
 507         int retries = 1024;
 508
 509         rte_errno = 0;
 510         while (--retries) {
 511                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 512                 if (rte_errno != EINPROGRESS)
 513                         break;
 514                 rte_pause();
 515         }
 516         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 517                 struct mlx5_flow_counter_pool *pool;
 518                 uint32_t batch = !!(i > 1);
 519
 520                 if (!sh->cmng.ccont[i].pools)
 521                         continue;
 522                 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 523                 while (pool) {
 524                         if (batch && pool->min_dcs)
 525                                 claim_zero(mlx5_devx_cmd_destroy
 526                                                                (pool->min_dcs));
 527                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 528                                 if (MLX5_POOL_GET_CNT(pool, j)->action)
 529                                         claim_zero
 530                                          (mlx5_glue->destroy_flow_action
 531                                           (MLX5_POOL_GET_CNT
 532                                           (pool, j)->action));
 533                                 if (!batch && MLX5_GET_POOL_CNT_EXT
 534                                     (pool, j)->dcs)
 535                                         claim_zero(mlx5_devx_cmd_destroy
 536                                                    (MLX5_GET_POOL_CNT_EXT
 537                                                     (pool, j)->dcs));
 538                         }
 539                         TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, next);
 540                         mlx5_free(pool);
 541                         pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 542                 }
 543                 mlx5_free(sh->cmng.ccont[i].pools);
 544         }
 545         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 546         while (mng) {
 547                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 548                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 549         }
 550         memset(&sh->cmng, 0, sizeof(sh->cmng));
 551 }
 552
 553 /**
 554  * Initialize the flow resources' indexed mempool.
 555  *
 556  * @param[in] sh
 557  *   Pointer to mlx5_dev_ctx_shared object.
 558  * @param[in] sh
 559  *   Pointer to user dev config.
 560  */
 561 static void
 562 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 563                        const struct mlx5_dev_config *config)
 564 {
 565         uint8_t i;
 566         struct mlx5_indexed_pool_config cfg;
 567
 568         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 569                 cfg = mlx5_ipool_cfg[i];
 570                 switch (i) {
 571                 default:
 572                         break;
 573                 /*
 574                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 575                  * according to PCI function flow configuration.
 576                  */
 577                 case MLX5_IPOOL_MLX5_FLOW:
 578                         cfg.size = config->dv_flow_en ?
 579                                 sizeof(struct mlx5_flow_handle) :
 580                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 581                         break;
 582                 }
 583                 if (config->reclaim_mode)
 584                         cfg.release_mem_en = 1;
 585                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 586         }
 587 }
 588
 589 /**
 590  * Release the flow resources' indexed mempool.
 591  *
 592  * @param[in] sh
 593  *   Pointer to mlx5_dev_ctx_shared object.
 594  */
 595 static void
 596 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 597 {
 598         uint8_t i;
 599
 600         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 601                 mlx5_ipool_destroy(sh->ipool[i]);
 602 }
 603
 604 /*
 605  * Check if dynamic flex parser for eCPRI already exists.
 606  *
 607  * @param dev
 608  *   Pointer to Ethernet device structure.
 609  *
 610  * @return
 611  *   true on exists, false on not.
 612  */
 613 bool
 614 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
 615 {
 616         struct mlx5_priv *priv = dev->data->dev_private;
 617         struct mlx5_flex_parser_profiles *prf =
 618                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 619
 620         return !!prf->obj;
 621 }
 622
 623 /*
 624  * Allocation of a flex parser for eCPRI. Once created, this parser related
 625  * resources will be held until the device is closed.
 626  *
 627  * @param dev
 628  *   Pointer to Ethernet device structure.
 629  *
 630  * @return
 631  *   0 on success, a negative errno value otherwise and rte_errno is set.
 632  */
 633 int
 634 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
 635 {
 636         struct mlx5_priv *priv = dev->data->dev_private;
 637         struct mlx5_flex_parser_profiles *prf =
 638                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 639         struct mlx5_devx_graph_node_attr node = {
 640                 .modify_field_select = 0,
 641         };
 642         uint32_t ids[8];
 643         int ret;
 644
 645         if (!priv->config.hca_attr.parse_graph_flex_node) {
 646                 DRV_LOG(ERR, "Dynamic flex parser is not supported "
 647                         "for device %s.", priv->dev_data->name);
 648                 return -ENOTSUP;
 649         }
 650         node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
 651         /* 8 bytes now: 4B common header + 4B message body header. */
 652         node.header_length_base_value = 0x8;
 653         /* After MAC layer: Ether / VLAN. */
 654         node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
 655         /* Type of compared condition should be 0xAEFE in the L2 layer. */
 656         node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
 657         /* Sample #0: type in common header. */
 658         node.sample[0].flow_match_sample_en = 1;
 659         /* Fixed offset. */
 660         node.sample[0].flow_match_sample_offset_mode = 0x0;
 661         /* Only the 2nd byte will be used. */
 662         node.sample[0].flow_match_sample_field_base_offset = 0x0;
 663         /* Sample #1: message payload. */
 664         node.sample[1].flow_match_sample_en = 1;
 665         /* Fixed offset. */
 666         node.sample[1].flow_match_sample_offset_mode = 0x0;
 667         /*
 668          * Only the first two bytes will be used right now, and its offset will
 669          * start after the common header that with the length of a DW(u32).
 670          */
 671         node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
 672         prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
 673         if (!prf->obj) {
 674                 DRV_LOG(ERR, "Failed to create flex parser node object.");
 675                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 676         }
 677         prf->num = 2;
 678         ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
 679         if (ret) {
 680                 DRV_LOG(ERR, "Failed to query sample IDs.");
 681                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 682         }
 683         prf->offset[0] = 0x0;
 684         prf->offset[1] = sizeof(uint32_t);
 685         prf->ids[0] = ids[0];
 686         prf->ids[1] = ids[1];
 687         return 0;
 688 }
 689
 690 /*
 691  * Destroy the flex parser node, including the parser itself, input / output
 692  * arcs and DW samples. Resources could be reused then.
 693  *
 694  * @param dev
 695  *   Pointer to Ethernet device structure.
 696  */
 697 static void
 698 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
 699 {
 700         struct mlx5_priv *priv = dev->data->dev_private;
 701         struct mlx5_flex_parser_profiles *prf =
 702                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 703
 704         if (prf->obj)
 705                 mlx5_devx_cmd_destroy(prf->obj);
 706         prf->obj = NULL;
 707 }
 708
 709 /**
 710  * Allocate shared device context. If there is multiport device the
 711  * master and representors will share this context, if there is single
 712  * port dedicated device, the context will be used by only given
 713  * port due to unification.
 714  *
 715  * Routine first searches the context for the specified device name,
 716  * if found the shared context assumed and reference counter is incremented.
 717  * If no context found the new one is created and initialized with specified
 718  * device context and parameters.
 719  *
 720  * @param[in] spawn
 721  *   Pointer to the device attributes (name, port, etc).
 722  * @param[in] config
 723  *   Pointer to device configuration structure.
 724  *
 725  * @return
 726  *   Pointer to mlx5_dev_ctx_shared object on success,
 727  *   otherwise NULL and rte_errno is set.
 728  */
 729 struct mlx5_dev_ctx_shared *
 730 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
 731                            const struct mlx5_dev_config *config)
 732 {
 733         struct mlx5_dev_ctx_shared *sh;
 734         int err = 0;
 735         uint32_t i;
 736         struct mlx5_devx_tis_attr tis_attr = { 0 };
 737
 738         MLX5_ASSERT(spawn);
 739         /* Secondary process should not create the shared context. */
 740         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 741         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 742         /* Search for IB context by device name. */
 743         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
 744                 if (!strcmp(sh->ibdev_name,
 745                         mlx5_os_get_dev_device_name(spawn->phys_dev))) {
 746                         sh->refcnt++;
 747                         goto exit;
 748                 }
 749         }
 750         /* No device found, we have to create new shared context. */
 751         MLX5_ASSERT(spawn->max_port);
 752         sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
 753                          sizeof(struct mlx5_dev_ctx_shared) +
 754                          spawn->max_port *
 755                          sizeof(struct mlx5_dev_shared_port),
 756                          RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 757         if (!sh) {
 758                 DRV_LOG(ERR, "shared context allocation failure");
 759                 rte_errno  = ENOMEM;
 760                 goto exit;
 761         }
 762         err = mlx5_os_open_device(spawn, config, sh);
 763         if (!sh->ctx)
 764                 goto error;
 765         err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
 766         if (err) {
 767                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
 768                 goto error;
 769         }
 770         sh->refcnt = 1;
 771         sh->max_port = spawn->max_port;
 772         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
 773                 sizeof(sh->ibdev_name) - 1);
 774         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
 775                 sizeof(sh->ibdev_path) - 1);
 776         /*
 777          * Setting port_id to max unallowed value means
 778          * there is no interrupt subhandler installed for
 779          * the given port index i.
 780          */
 781         for (i = 0; i < sh->max_port; i++) {
 782                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 783                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
 784         }
 785         sh->pd = mlx5_glue->alloc_pd(sh->ctx);
 786         if (sh->pd == NULL) {
 787                 DRV_LOG(ERR, "PD allocation failure");
 788                 err = ENOMEM;
 789                 goto error;
 790         }
 791         if (sh->devx) {
 792                 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
 793                 if (err) {
 794                         DRV_LOG(ERR, "Fail to extract pdn from PD");
 795                         goto error;
 796                 }
 797                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
 798                 if (!sh->td) {
 799                         DRV_LOG(ERR, "TD allocation failure");
 800                         err = ENOMEM;
 801                         goto error;
 802                 }
 803                 tis_attr.transport_domain = sh->td->id;
 804                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
 805                 if (!sh->tis) {
 806                         DRV_LOG(ERR, "TIS allocation failure");
 807                         err = ENOMEM;
 808                         goto error;
 809                 }
 810                 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, 0);
 811                 if (!sh->tx_uar) {
 812                         DRV_LOG(ERR, "Failed to allocate DevX UAR.");
 813                         err = ENOMEM;
 814                         goto error;
 815                 }
 816                 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, 0);
 817                 if (!sh->devx_rx_uar) {
 818                         DRV_LOG(ERR, "Failed to allocate Rx DevX UAR.");
 819                         err = ENOMEM;
 820                         goto error;
 821                 }
 822         }
 823         sh->flow_id_pool = mlx5_flow_id_pool_alloc
 824                                         ((1 << HAIRPIN_FLOW_ID_BITS) - 1);
 825         if (!sh->flow_id_pool) {
 826                 DRV_LOG(ERR, "can't create flow id pool");
 827                 err = ENOMEM;
 828                 goto error;
 829         }
 830 #ifndef RTE_ARCH_64
 831         /* Initialize UAR access locks for 32bit implementations. */
 832         rte_spinlock_init(&sh->uar_lock_cq);
 833         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
 834                 rte_spinlock_init(&sh->uar_lock[i]);
 835 #endif
 836         /*
 837          * Once the device is added to the list of memory event
 838          * callback, its global MR cache table cannot be expanded
 839          * on the fly because of deadlock. If it overflows, lookup
 840          * should be done by searching MR list linearly, which is slow.
 841          *
 842          * At this point the device is not added to the memory
 843          * event list yet, context is just being created.
 844          */
 845         err = mlx5_mr_btree_init(&sh->share_cache.cache,
 846                                  MLX5_MR_BTREE_CACHE_N * 2,
 847                                  spawn->pci_dev->device.numa_node);
 848         if (err) {
 849                 err = rte_errno;
 850                 goto error;
 851         }
 852         mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
 853                               &sh->share_cache.dereg_mr_cb);
 854         mlx5_os_dev_shared_handler_install(sh);
 855         sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
 856         if (!sh->cnt_id_tbl) {
 857                 err = rte_errno;
 858                 goto error;
 859         }
 860         mlx5_flow_aging_init(sh);
 861         mlx5_flow_counters_mng_init(sh);
 862         mlx5_flow_ipool_create(sh, config);
 863         /* Add device to memory callback list. */
 864         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 865         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
 866                          sh, mem_event_cb);
 867         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 868         /* Add context to the global device list. */
 869         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
 870 exit:
 871         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 872         return sh;
 873 error:
 874         pthread_mutex_destroy(&sh->txpp.mutex);
 875         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 876         MLX5_ASSERT(sh);
 877         if (sh->cnt_id_tbl) {
 878                 mlx5_l3t_destroy(sh->cnt_id_tbl);
 879                 sh->cnt_id_tbl = NULL;
 880         }
 881         if (sh->tx_uar) {
 882                 mlx5_glue->devx_free_uar(sh->tx_uar);
 883                 sh->tx_uar = NULL;
 884         }
 885         if (sh->tis)
 886                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 887         if (sh->td)
 888                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 889         if (sh->devx_rx_uar)
 890                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
 891         if (sh->pd)
 892                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 893         if (sh->ctx)
 894                 claim_zero(mlx5_glue->close_device(sh->ctx));
 895         if (sh->flow_id_pool)
 896                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 897         mlx5_free(sh);
 898         MLX5_ASSERT(err > 0);
 899         rte_errno = err;
 900         return NULL;
 901 }
 902
 903 /**
 904  * Free shared IB device context. Decrement counter and if zero free
 905  * all allocated resources and close handles.
 906  *
 907  * @param[in] sh
 908  *   Pointer to mlx5_dev_ctx_shared object to free
 909  */
 910 void
 911 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
 912 {
 913         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 914 #ifdef RTE_LIBRTE_MLX5_DEBUG
 915         /* Check the object presence in the list. */
 916         struct mlx5_dev_ctx_shared *lctx;
 917
 918         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
 919                 if (lctx == sh)
 920                         break;
 921         MLX5_ASSERT(lctx);
 922         if (lctx != sh) {
 923                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
 924                 goto exit;
 925         }
 926 #endif
 927         MLX5_ASSERT(sh);
 928         MLX5_ASSERT(sh->refcnt);
 929         /* Secondary process should not free the shared context. */
 930         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 931         if (--sh->refcnt)
 932                 goto exit;
 933         /* Remove from memory callback device list. */
 934         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 935         LIST_REMOVE(sh, mem_event_cb);
 936         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 937         /* Release created Memory Regions. */
 938         mlx5_mr_release_cache(&sh->share_cache);
 939         /* Remove context from the global device list. */
 940         LIST_REMOVE(sh, next);
 941         /*
 942          *  Ensure there is no async event handler installed.
 943          *  Only primary process handles async device events.
 944          **/
 945         mlx5_flow_counters_mng_close(sh);
 946         mlx5_flow_ipool_destroy(sh);
 947         mlx5_os_dev_shared_handler_uninstall(sh);
 948         if (sh->cnt_id_tbl) {
 949                 mlx5_l3t_destroy(sh->cnt_id_tbl);
 950                 sh->cnt_id_tbl = NULL;
 951         }
 952         if (sh->tx_uar) {
 953                 mlx5_glue->devx_free_uar(sh->tx_uar);
 954                 sh->tx_uar = NULL;
 955         }
 956         if (sh->pd)
 957                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 958         if (sh->tis)
 959                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 960         if (sh->td)
 961                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 962         if (sh->devx_rx_uar)
 963                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
 964         if (sh->ctx)
 965                 claim_zero(mlx5_glue->close_device(sh->ctx));
 966         if (sh->flow_id_pool)
 967                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 968         pthread_mutex_destroy(&sh->txpp.mutex);
 969         mlx5_free(sh);
 970 exit:
 971         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 972 }
 973
 974 /**
 975  * Destroy table hash list and all the root entries per domain.
 976  *
 977  * @param[in] priv
 978  *   Pointer to the private device data structure.
 979  */
 980 void
 981 mlx5_free_table_hash_list(struct mlx5_priv *priv)
 982 {
 983         struct mlx5_dev_ctx_shared *sh = priv->sh;
 984         struct mlx5_flow_tbl_data_entry *tbl_data;
 985         union mlx5_flow_tbl_key table_key = {
 986                 {
 987                         .table_id = 0,
 988                         .reserved = 0,
 989                         .domain = 0,
 990                         .direction = 0,
 991                 }
 992         };
 993         struct mlx5_hlist_entry *pos;
 994
 995         if (!sh->flow_tbls)
 996                 return;
 997         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 998         if (pos) {
 999                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1000                                         entry);
1001                 MLX5_ASSERT(tbl_data);
1002                 mlx5_hlist_remove(sh->flow_tbls, pos);
1003                 mlx5_free(tbl_data);
1004         }
1005         table_key.direction = 1;
1006         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1007         if (pos) {
1008                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1009                                         entry);
1010                 MLX5_ASSERT(tbl_data);
1011                 mlx5_hlist_remove(sh->flow_tbls, pos);
1012                 mlx5_free(tbl_data);
1013         }
1014         table_key.direction = 0;
1015         table_key.domain = 1;
1016         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1017         if (pos) {
1018                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1019                                         entry);
1020                 MLX5_ASSERT(tbl_data);
1021                 mlx5_hlist_remove(sh->flow_tbls, pos);
1022                 mlx5_free(tbl_data);
1023         }
1024         mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
1025 }
1026
1027 /**
1028  * Initialize flow table hash list and create the root tables entry
1029  * for each domain.
1030  *
1031  * @param[in] priv
1032  *   Pointer to the private device data structure.
1033  *
1034  * @return
1035  *   Zero on success, positive error code otherwise.
1036  */
1037 int
1038 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
1039 {
1040         struct mlx5_dev_ctx_shared *sh = priv->sh;
1041         char s[MLX5_HLIST_NAMESIZE];
1042         int err = 0;
1043
1044         MLX5_ASSERT(sh);
1045         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1046         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
1047         if (!sh->flow_tbls) {
1048                 DRV_LOG(ERR, "flow tables with hash creation failed.");
1049                 err = ENOMEM;
1050                 return err;
1051         }
1052 #ifndef HAVE_MLX5DV_DR
1053         /*
1054          * In case we have not DR support, the zero tables should be created
1055          * because DV expect to see them even if they cannot be created by
1056          * RDMA-CORE.
1057          */
1058         union mlx5_flow_tbl_key table_key = {
1059                 {
1060                         .table_id = 0,
1061                         .reserved = 0,
1062                         .domain = 0,
1063                         .direction = 0,
1064                 }
1065         };
1066         struct mlx5_flow_tbl_data_entry *tbl_data = mlx5_malloc(MLX5_MEM_ZERO,
1067                                                           sizeof(*tbl_data), 0,
1068                                                           SOCKET_ID_ANY);
1069
1070         if (!tbl_data) {
1071                 err = ENOMEM;
1072                 goto error;
1073         }
1074         tbl_data->entry.key = table_key.v64;
1075         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1076         if (err)
1077                 goto error;
1078         rte_atomic32_init(&tbl_data->tbl.refcnt);
1079         rte_atomic32_inc(&tbl_data->tbl.refcnt);
1080         table_key.direction = 1;
1081         tbl_data = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tbl_data), 0,
1082                                SOCKET_ID_ANY);
1083         if (!tbl_data) {
1084                 err = ENOMEM;
1085                 goto error;
1086         }
1087         tbl_data->entry.key = table_key.v64;
1088         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1089         if (err)
1090                 goto error;
1091         rte_atomic32_init(&tbl_data->tbl.refcnt);
1092         rte_atomic32_inc(&tbl_data->tbl.refcnt);
1093         table_key.direction = 0;
1094         table_key.domain = 1;
1095         tbl_data = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tbl_data), 0,
1096                                SOCKET_ID_ANY);
1097         if (!tbl_data) {
1098                 err = ENOMEM;
1099                 goto error;
1100         }
1101         tbl_data->entry.key = table_key.v64;
1102         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1103         if (err)
1104                 goto error;
1105         rte_atomic32_init(&tbl_data->tbl.refcnt);
1106         rte_atomic32_inc(&tbl_data->tbl.refcnt);
1107         return err;
1108 error:
1109         mlx5_free_table_hash_list(priv);
1110 #endif /* HAVE_MLX5DV_DR */
1111         return err;
1112 }
1113
1114 /**
1115  * Retrieve integer value from environment variable.
1116  *
1117  * @param[in] name
1118  *   Environment variable name.
1119  *
1120  * @return
1121  *   Integer value, 0 if the variable is not set.
1122  */
1123 int
1124 mlx5_getenv_int(const char *name)
1125 {
1126         const char *val = getenv(name);
1127
1128         if (val == NULL)
1129                 return 0;
1130         return atoi(val);
1131 }
1132
1133 /**
1134  * DPDK callback to add udp tunnel port
1135  *
1136  * @param[in] dev
1137  *   A pointer to eth_dev
1138  * @param[in] udp_tunnel
1139  *   A pointer to udp tunnel
1140  *
1141  * @return
1142  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1143  */
1144 int
1145 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1146                          struct rte_eth_udp_tunnel *udp_tunnel)
1147 {
1148         MLX5_ASSERT(udp_tunnel != NULL);
1149         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1150             udp_tunnel->udp_port == 4789)
1151                 return 0;
1152         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1153             udp_tunnel->udp_port == 4790)
1154                 return 0;
1155         return -ENOTSUP;
1156 }
1157
1158 /**
1159  * Initialize process private data structure.
1160  *
1161  * @param dev
1162  *   Pointer to Ethernet device structure.
1163  *
1164  * @return
1165  *   0 on success, a negative errno value otherwise and rte_errno is set.
1166  */
1167 int
1168 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1169 {
1170         struct mlx5_priv *priv = dev->data->dev_private;
1171         struct mlx5_proc_priv *ppriv;
1172         size_t ppriv_size;
1173
1174         /*
1175          * UAR register table follows the process private structure. BlueFlame
1176          * registers for Tx queues are stored in the table.
1177          */
1178         ppriv_size =
1179                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1180         ppriv = mlx5_malloc(MLX5_MEM_RTE, ppriv_size, RTE_CACHE_LINE_SIZE,
1181                             dev->device->numa_node);
1182         if (!ppriv) {
1183                 rte_errno = ENOMEM;
1184                 return -rte_errno;
1185         }
1186         ppriv->uar_table_sz = ppriv_size;
1187         dev->process_private = ppriv;
1188         return 0;
1189 }
1190
1191 /**
1192  * Un-initialize process private data structure.
1193  *
1194  * @param dev
1195  *   Pointer to Ethernet device structure.
1196  */
1197 static void
1198 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1199 {
1200         if (!dev->process_private)
1201                 return;
1202         mlx5_free(dev->process_private);
1203         dev->process_private = NULL;
1204 }
1205
1206 /**
1207  * DPDK callback to close the device.
1208  *
1209  * Destroy all queues and objects, free memory.
1210  *
1211  * @param dev
1212  *   Pointer to Ethernet device structure.
1213  */
1214 void
1215 mlx5_dev_close(struct rte_eth_dev *dev)
1216 {
1217         struct mlx5_priv *priv = dev->data->dev_private;
1218         unsigned int i;
1219         int ret;
1220
1221         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1222                 /* Check if process_private released. */
1223                 if (!dev->process_private)
1224                         return;
1225                 mlx5_tx_uar_uninit_secondary(dev);
1226                 mlx5_proc_priv_uninit(dev);
1227                 rte_eth_dev_release_port(dev);
1228                 return;
1229         }
1230         if (!priv->sh)
1231                 return;
1232         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1233                 dev->data->port_id,
1234                 ((priv->sh->ctx != NULL) ?
1235                 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1236         /*
1237          * If default mreg copy action is removed at the stop stage,
1238          * the search will return none and nothing will be done anymore.
1239          */
1240         mlx5_flow_stop_default(dev);
1241         mlx5_traffic_disable(dev);
1242         /*
1243          * If all the flows are already flushed in the device stop stage,
1244          * then this will return directly without any action.
1245          */
1246         mlx5_flow_list_flush(dev, &priv->flows, true);
1247         mlx5_flow_meter_flush(dev, NULL);
1248         /* Free the intermediate buffers for flow creation. */
1249         mlx5_flow_free_intermediate(dev);
1250         /* Prevent crashes when queues are still in use. */
1251         dev->rx_pkt_burst = removed_rx_burst;
1252         dev->tx_pkt_burst = removed_tx_burst;
1253         rte_wmb();
1254         /* Disable datapath on secondary process. */
1255         mlx5_mp_os_req_stop_rxtx(dev);
1256         /* Free the eCPRI flex parser resource. */
1257         mlx5_flex_parser_ecpri_release(dev);
1258         if (priv->rxqs != NULL) {
1259                 /* XXX race condition if mlx5_rx_burst() is still running. */
1260                 usleep(1000);
1261                 for (i = 0; (i != priv->rxqs_n); ++i)
1262                         mlx5_rxq_release(dev, i);
1263                 priv->rxqs_n = 0;
1264                 priv->rxqs = NULL;
1265         }
1266         if (priv->txqs != NULL) {
1267                 /* XXX race condition if mlx5_tx_burst() is still running. */
1268                 usleep(1000);
1269                 for (i = 0; (i != priv->txqs_n); ++i)
1270                         mlx5_txq_release(dev, i);
1271                 priv->txqs_n = 0;
1272                 priv->txqs = NULL;
1273         }
1274         mlx5_proc_priv_uninit(dev);
1275         if (priv->mreg_cp_tbl)
1276                 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1277         mlx5_mprq_free_mp(dev);
1278         mlx5_os_free_shared_dr(priv);
1279         if (priv->rss_conf.rss_key != NULL)
1280                 mlx5_free(priv->rss_conf.rss_key);
1281         if (priv->reta_idx != NULL)
1282                 mlx5_free(priv->reta_idx);
1283         if (priv->config.vf)
1284                 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1285                                        dev->data->mac_addrs,
1286                                        MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1287         if (priv->nl_socket_route >= 0)
1288                 close(priv->nl_socket_route);
1289         if (priv->nl_socket_rdma >= 0)
1290                 close(priv->nl_socket_rdma);
1291         if (priv->vmwa_context)
1292                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1293         ret = mlx5_hrxq_verify(dev);
1294         if (ret)
1295                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1296                         dev->data->port_id);
1297         ret = mlx5_ind_table_obj_verify(dev);
1298         if (ret)
1299                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1300                         dev->data->port_id);
1301         ret = mlx5_rxq_obj_verify(dev);
1302         if (ret)
1303                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1304                         dev->data->port_id);
1305         ret = mlx5_rxq_verify(dev);
1306         if (ret)
1307                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1308                         dev->data->port_id);
1309         ret = mlx5_txq_obj_verify(dev);
1310         if (ret)
1311                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1312                         dev->data->port_id);
1313         ret = mlx5_txq_verify(dev);
1314         if (ret)
1315                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1316                         dev->data->port_id);
1317         ret = mlx5_flow_verify(dev);
1318         if (ret)
1319                 DRV_LOG(WARNING, "port %u some flows still remain",
1320                         dev->data->port_id);
1321         /*
1322          * Free the shared context in last turn, because the cleanup
1323          * routines above may use some shared fields, like
1324          * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1325          * ifindex if Netlink fails.
1326          */
1327         mlx5_free_shared_dev_ctx(priv->sh);
1328         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1329                 unsigned int c = 0;
1330                 uint16_t port_id;
1331
1332                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1333                         struct mlx5_priv *opriv =
1334                                 rte_eth_devices[port_id].data->dev_private;
1335
1336                         if (!opriv ||
1337                             opriv->domain_id != priv->domain_id ||
1338                             &rte_eth_devices[port_id] == dev)
1339                                 continue;
1340                         ++c;
1341                         break;
1342                 }
1343                 if (!c)
1344                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1345         }
1346         memset(priv, 0, sizeof(*priv));
1347         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1348         /*
1349          * Reset mac_addrs to NULL such that it is not freed as part of
1350          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1351          * it is freed when dev_private is freed.
1352          */
1353         dev->data->mac_addrs = NULL;
1354 }
1355
1356 /**
1357  * Verify and store value for device argument.
1358  *
1359  * @param[in] key
1360  *   Key argument to verify.
1361  * @param[in] val
1362  *   Value associated with key.
1363  * @param opaque
1364  *   User data.
1365  *
1366  * @return
1367  *   0 on success, a negative errno value otherwise and rte_errno is set.
1368  */
1369 static int
1370 mlx5_args_check(const char *key, const char *val, void *opaque)
1371 {
1372         struct mlx5_dev_config *config = opaque;
1373         unsigned long mod;
1374         signed long tmp;
1375
1376         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1377         if (!strcmp(MLX5_REPRESENTOR, key))
1378                 return 0;
1379         errno = 0;
1380         tmp = strtol(val, NULL, 0);
1381         if (errno) {
1382                 rte_errno = errno;
1383                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1384                 return -rte_errno;
1385         }
1386         if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1387                 /* Negative values are acceptable for some keys only. */
1388                 rte_errno = EINVAL;
1389                 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1390                 return -rte_errno;
1391         }
1392         mod = tmp >= 0 ? tmp : -tmp;
1393         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1394                 config->cqe_comp = !!tmp;
1395         } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1396                 config->cqe_pad = !!tmp;
1397         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1398                 config->hw_padding = !!tmp;
1399         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1400                 config->mprq.enabled = !!tmp;
1401         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1402                 config->mprq.stride_num_n = tmp;
1403         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1404                 config->mprq.stride_size_n = tmp;
1405         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1406                 config->mprq.max_memcpy_len = tmp;
1407         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1408                 config->mprq.min_rxqs_num = tmp;
1409         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1410                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1411                                  " converted to txq_inline_max", key);
1412                 config->txq_inline_max = tmp;
1413         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1414                 config->txq_inline_max = tmp;
1415         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1416                 config->txq_inline_min = tmp;
1417         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1418                 config->txq_inline_mpw = tmp;
1419         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1420                 config->txqs_inline = tmp;
1421         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1422                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1423         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1424                 config->mps = !!tmp;
1425         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1426                 if (tmp != MLX5_TXDB_CACHED &&
1427                     tmp != MLX5_TXDB_NCACHED &&
1428                     tmp != MLX5_TXDB_HEURISTIC) {
1429                         DRV_LOG(ERR, "invalid Tx doorbell "
1430                                      "mapping parameter");
1431                         rte_errno = EINVAL;
1432                         return -rte_errno;
1433                 }
1434                 config->dbnc = tmp;
1435         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1436                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1437         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1438                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1439                                  " converted to txq_inline_mpw", key);
1440                 config->txq_inline_mpw = tmp;
1441         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1442                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1443         } else if (strcmp(MLX5_TX_PP, key) == 0) {
1444                 if (!mod) {
1445                         DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1446                         rte_errno = EINVAL;
1447                         return -rte_errno;
1448                 }
1449                 config->tx_pp = tmp;
1450         } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1451                 config->tx_skew = tmp;
1452         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1453                 config->rx_vec_en = !!tmp;
1454         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1455                 config->l3_vxlan_en = !!tmp;
1456         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1457                 config->vf_nl_en = !!tmp;
1458         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1459                 config->dv_esw_en = !!tmp;
1460         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1461                 config->dv_flow_en = !!tmp;
1462         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1463                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1464                     tmp != MLX5_XMETA_MODE_META16 &&
1465                     tmp != MLX5_XMETA_MODE_META32) {
1466                         DRV_LOG(ERR, "invalid extensive "
1467                                      "metadata parameter");
1468                         rte_errno = EINVAL;
1469                         return -rte_errno;
1470                 }
1471                 config->dv_xmeta_en = tmp;
1472         } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1473                 config->lacp_by_user = !!tmp;
1474         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1475                 config->mr_ext_memseg_en = !!tmp;
1476         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1477                 config->max_dump_files_num = tmp;
1478         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1479                 config->lro.timeout = tmp;
1480         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1481                 DRV_LOG(DEBUG, "class argument is %s.", val);
1482         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1483                 config->log_hp_size = tmp;
1484         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1485                 if (tmp != MLX5_RCM_NONE &&
1486                     tmp != MLX5_RCM_LIGHT &&
1487                     tmp != MLX5_RCM_AGGR) {
1488                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1489                         rte_errno = EINVAL;
1490                         return -rte_errno;
1491                 }
1492                 config->reclaim_mode = tmp;
1493         } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1494                 config->sys_mem_en = !!tmp;
1495         } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1496                 config->decap_en = !!tmp;
1497         } else {
1498                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1499                 rte_errno = EINVAL;
1500                 return -rte_errno;
1501         }
1502         return 0;
1503 }
1504
1505 /**
1506  * Parse device parameters.
1507  *
1508  * @param config
1509  *   Pointer to device configuration structure.
1510  * @param devargs
1511  *   Device arguments structure.
1512  *
1513  * @return
1514  *   0 on success, a negative errno value otherwise and rte_errno is set.
1515  */
1516 int
1517 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1518 {
1519         const char **params = (const char *[]){
1520                 MLX5_RXQ_CQE_COMP_EN,
1521                 MLX5_RXQ_CQE_PAD_EN,
1522                 MLX5_RXQ_PKT_PAD_EN,
1523                 MLX5_RX_MPRQ_EN,
1524                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1525                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1526                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1527                 MLX5_RXQS_MIN_MPRQ,
1528                 MLX5_TXQ_INLINE,
1529                 MLX5_TXQ_INLINE_MIN,
1530                 MLX5_TXQ_INLINE_MAX,
1531                 MLX5_TXQ_INLINE_MPW,
1532                 MLX5_TXQS_MIN_INLINE,
1533                 MLX5_TXQS_MAX_VEC,
1534                 MLX5_TXQ_MPW_EN,
1535                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1536                 MLX5_TXQ_MAX_INLINE_LEN,
1537                 MLX5_TX_DB_NC,
1538                 MLX5_TX_PP,
1539                 MLX5_TX_SKEW,
1540                 MLX5_TX_VEC_EN,
1541                 MLX5_RX_VEC_EN,
1542                 MLX5_L3_VXLAN_EN,
1543                 MLX5_VF_NL_EN,
1544                 MLX5_DV_ESW_EN,
1545                 MLX5_DV_FLOW_EN,
1546                 MLX5_DV_XMETA_EN,
1547                 MLX5_LACP_BY_USER,
1548                 MLX5_MR_EXT_MEMSEG_EN,
1549                 MLX5_REPRESENTOR,
1550                 MLX5_MAX_DUMP_FILES_NUM,
1551                 MLX5_LRO_TIMEOUT_USEC,
1552                 MLX5_CLASS_ARG_NAME,
1553                 MLX5_HP_BUF_SIZE,
1554                 MLX5_RECLAIM_MEM,
1555                 MLX5_SYS_MEM_EN,
1556                 MLX5_DECAP_EN,
1557                 NULL,
1558         };
1559         struct rte_kvargs *kvlist;
1560         int ret = 0;
1561         int i;
1562
1563         if (devargs == NULL)
1564                 return 0;
1565         /* Following UGLY cast is done to pass checkpatch. */
1566         kvlist = rte_kvargs_parse(devargs->args, params);
1567         if (kvlist == NULL) {
1568                 rte_errno = EINVAL;
1569                 return -rte_errno;
1570         }
1571         /* Process parameters. */
1572         for (i = 0; (params[i] != NULL); ++i) {
1573                 if (rte_kvargs_count(kvlist, params[i])) {
1574                         ret = rte_kvargs_process(kvlist, params[i],
1575                                                  mlx5_args_check, config);
1576                         if (ret) {
1577                                 rte_errno = EINVAL;
1578                                 rte_kvargs_free(kvlist);
1579                                 return -rte_errno;
1580                         }
1581                 }
1582         }
1583         rte_kvargs_free(kvlist);
1584         return 0;
1585 }
1586
1587 /**
1588  * Configures the minimal amount of data to inline into WQE
1589  * while sending packets.
1590  *
1591  * - the txq_inline_min has the maximal priority, if this
1592  *   key is specified in devargs
1593  * - if DevX is enabled the inline mode is queried from the
1594  *   device (HCA attributes and NIC vport context if needed).
1595  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1596  *   and none (0 bytes) for other NICs
1597  *
1598  * @param spawn
1599  *   Verbs device parameters (name, port, switch_info) to spawn.
1600  * @param config
1601  *   Device configuration parameters.
1602  */
1603 void
1604 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1605                     struct mlx5_dev_config *config)
1606 {
1607         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1608                 /* Application defines size of inlined data explicitly. */
1609                 switch (spawn->pci_dev->id.device_id) {
1610                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1611                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1612                         if (config->txq_inline_min <
1613                                        (int)MLX5_INLINE_HSIZE_L2) {
1614                                 DRV_LOG(DEBUG,
1615                                         "txq_inline_mix aligned to minimal"
1616                                         " ConnectX-4 required value %d",
1617                                         (int)MLX5_INLINE_HSIZE_L2);
1618                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1619                         }
1620                         break;
1621                 }
1622                 goto exit;
1623         }
1624         if (config->hca_attr.eth_net_offloads) {
1625                 /* We have DevX enabled, inline mode queried successfully. */
1626                 switch (config->hca_attr.wqe_inline_mode) {
1627                 case MLX5_CAP_INLINE_MODE_L2:
1628                         /* outer L2 header must be inlined. */
1629                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1630                         goto exit;
1631                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1632                         /* No inline data are required by NIC. */
1633                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1634                         config->hw_vlan_insert =
1635                                 config->hca_attr.wqe_vlan_insert;
1636                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1637                         goto exit;
1638                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1639                         /* inline mode is defined by NIC vport context. */
1640                         if (!config->hca_attr.eth_virt)
1641                                 break;
1642                         switch (config->hca_attr.vport_inline_mode) {
1643                         case MLX5_INLINE_MODE_NONE:
1644                                 config->txq_inline_min =
1645                                         MLX5_INLINE_HSIZE_NONE;
1646                                 goto exit;
1647                         case MLX5_INLINE_MODE_L2:
1648                                 config->txq_inline_min =
1649                                         MLX5_INLINE_HSIZE_L2;
1650                                 goto exit;
1651                         case MLX5_INLINE_MODE_IP:
1652                                 config->txq_inline_min =
1653                                         MLX5_INLINE_HSIZE_L3;
1654                                 goto exit;
1655                         case MLX5_INLINE_MODE_TCP_UDP:
1656                                 config->txq_inline_min =
1657                                         MLX5_INLINE_HSIZE_L4;
1658                                 goto exit;
1659                         case MLX5_INLINE_MODE_INNER_L2:
1660                                 config->txq_inline_min =
1661                                         MLX5_INLINE_HSIZE_INNER_L2;
1662                                 goto exit;
1663                         case MLX5_INLINE_MODE_INNER_IP:
1664                                 config->txq_inline_min =
1665                                         MLX5_INLINE_HSIZE_INNER_L3;
1666                                 goto exit;
1667                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
1668                                 config->txq_inline_min =
1669                                         MLX5_INLINE_HSIZE_INNER_L4;
1670                                 goto exit;
1671                         }
1672                 }
1673         }
1674         /*
1675          * We get here if we are unable to deduce
1676          * inline data size with DevX. Try PCI ID
1677          * to determine old NICs.
1678          */
1679         switch (spawn->pci_dev->id.device_id) {
1680         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1681         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1682         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1683         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1684                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1685                 config->hw_vlan_insert = 0;
1686                 break;
1687         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1688         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1689         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1690         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1691                 /*
1692                  * These NICs support VLAN insertion from WQE and
1693                  * report the wqe_vlan_insert flag. But there is the bug
1694                  * and PFC control may be broken, so disable feature.
1695                  */
1696                 config->hw_vlan_insert = 0;
1697                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1698                 break;
1699         default:
1700                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1701                 break;
1702         }
1703 exit:
1704         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1705 }
1706
1707 /**
1708  * Configures the metadata mask fields in the shared context.
1709  *
1710  * @param [in] dev
1711  *   Pointer to Ethernet device.
1712  */
1713 void
1714 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1715 {
1716         struct mlx5_priv *priv = dev->data->dev_private;
1717         struct mlx5_dev_ctx_shared *sh = priv->sh;
1718         uint32_t meta, mark, reg_c0;
1719
1720         reg_c0 = ~priv->vport_meta_mask;
1721         switch (priv->config.dv_xmeta_en) {
1722         case MLX5_XMETA_MODE_LEGACY:
1723                 meta = UINT32_MAX;
1724                 mark = MLX5_FLOW_MARK_MASK;
1725                 break;
1726         case MLX5_XMETA_MODE_META16:
1727                 meta = reg_c0 >> rte_bsf32(reg_c0);
1728                 mark = MLX5_FLOW_MARK_MASK;
1729                 break;
1730         case MLX5_XMETA_MODE_META32:
1731                 meta = UINT32_MAX;
1732                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1733                 break;
1734         default:
1735                 meta = 0;
1736                 mark = 0;
1737                 MLX5_ASSERT(false);
1738                 break;
1739         }
1740         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1741                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1742                                  sh->dv_mark_mask, mark);
1743         else
1744                 sh->dv_mark_mask = mark;
1745         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1746                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1747                                  sh->dv_meta_mask, meta);
1748         else
1749                 sh->dv_meta_mask = meta;
1750         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1751                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1752                                  sh->dv_meta_mask, reg_c0);
1753         else
1754                 sh->dv_regc0_mask = reg_c0;
1755         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1756         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1757         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1758         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1759 }
1760
1761 int
1762 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1763 {
1764         static const char *const dynf_names[] = {
1765                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1766                 RTE_MBUF_DYNFLAG_METADATA_NAME,
1767                 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
1768         };
1769         unsigned int i;
1770
1771         if (n < RTE_DIM(dynf_names))
1772                 return -ENOMEM;
1773         for (i = 0; i < RTE_DIM(dynf_names); i++) {
1774                 if (names[i] == NULL)
1775                         return -EINVAL;
1776                 strcpy(names[i], dynf_names[i]);
1777         }
1778         return RTE_DIM(dynf_names);
1779 }
1780
1781 /**
1782  * Comparison callback to sort device data.
1783  *
1784  * This is meant to be used with qsort().
1785  *
1786  * @param a[in]
1787  *   Pointer to pointer to first data object.
1788  * @param b[in]
1789  *   Pointer to pointer to second data object.
1790  *
1791  * @return
1792  *   0 if both objects are equal, less than 0 if the first argument is less
1793  *   than the second, greater than 0 otherwise.
1794  */
1795 int
1796 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1797                               struct mlx5_dev_config *config)
1798 {
1799         struct mlx5_dev_ctx_shared *sh = priv->sh;
1800         struct mlx5_dev_config *sh_conf = NULL;
1801         uint16_t port_id;
1802
1803         MLX5_ASSERT(sh);
1804         /* Nothing to compare for the single/first device. */
1805         if (sh->refcnt == 1)
1806                 return 0;
1807         /* Find the device with shared context. */
1808         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1809                 struct mlx5_priv *opriv =
1810                         rte_eth_devices[port_id].data->dev_private;
1811
1812                 if (opriv && opriv != priv && opriv->sh == sh) {
1813                         sh_conf = &opriv->config;
1814                         break;
1815                 }
1816         }
1817         if (!sh_conf)
1818                 return 0;
1819         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1820                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1821                              " for shared %s context", sh->ibdev_name);
1822                 rte_errno = EINVAL;
1823                 return rte_errno;
1824         }
1825         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1826                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1827                              " for shared %s context", sh->ibdev_name);
1828                 rte_errno = EINVAL;
1829                 return rte_errno;
1830         }
1831         return 0;
1832 }
1833
1834 /**
1835  * Look for the ethernet device belonging to mlx5 driver.
1836  *
1837  * @param[in] port_id
1838  *   port_id to start looking for device.
1839  * @param[in] pci_dev
1840  *   Pointer to the hint PCI device. When device is being probed
1841  *   the its siblings (master and preceding representors might
1842  *   not have assigned driver yet (because the mlx5_os_pci_probe()
1843  *   is not completed yet, for this case match on hint PCI
1844  *   device may be used to detect sibling device.
1845  *
1846  * @return
1847  *   port_id of found device, RTE_MAX_ETHPORT if not found.
1848  */
1849 uint16_t
1850 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
1851 {
1852         while (port_id < RTE_MAX_ETHPORTS) {
1853                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
1854
1855                 if (dev->state != RTE_ETH_DEV_UNUSED &&
1856                     dev->device &&
1857                     (dev->device == &pci_dev->device ||
1858                      (dev->device->driver &&
1859                      dev->device->driver->name &&
1860                      !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
1861                         break;
1862                 port_id++;
1863         }
1864         if (port_id >= RTE_MAX_ETHPORTS)
1865                 return RTE_MAX_ETHPORTS;
1866         return port_id;
1867 }
1868
1869 /**
1870  * DPDK callback to remove a PCI device.
1871  *
1872  * This function removes all Ethernet devices belong to a given PCI device.
1873  *
1874  * @param[in] pci_dev
1875  *   Pointer to the PCI device.
1876  *
1877  * @return
1878  *   0 on success, the function cannot fail.
1879  */
1880 static int
1881 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1882 {
1883         uint16_t port_id;
1884
1885         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
1886                 /*
1887                  * mlx5_dev_close() is not registered to secondary process,
1888                  * call the close function explicitly for secondary process.
1889                  */
1890                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
1891                         mlx5_dev_close(&rte_eth_devices[port_id]);
1892                 else
1893                         rte_eth_dev_close(port_id);
1894         }
1895         return 0;
1896 }
1897
1898 static const struct rte_pci_id mlx5_pci_id_map[] = {
1899         {
1900                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1901                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1902         },
1903         {
1904                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1905                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1906         },
1907         {
1908                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1909                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1910         },
1911         {
1912                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1913                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1914         },
1915         {
1916                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1917                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1918         },
1919         {
1920                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1921                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1922         },
1923         {
1924                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1925                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1926         },
1927         {
1928                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1929                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1930         },
1931         {
1932                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1933                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
1934         },
1935         {
1936                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1937                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
1938         },
1939         {
1940                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1941                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
1942         },
1943         {
1944                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1945                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
1946         },
1947         {
1948                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1949                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
1950         },
1951         {
1952                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1953                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
1954         },
1955         {
1956                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1957                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
1958         },
1959         {
1960                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1961                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
1962         },
1963         {
1964                 .vendor_id = 0
1965         }
1966 };
1967
1968 struct rte_pci_driver mlx5_driver = {
1969         .driver = {
1970                 .name = MLX5_DRIVER_NAME
1971         },
1972         .id_table = mlx5_pci_id_map,
1973         .probe = mlx5_os_pci_probe,
1974         .remove = mlx5_pci_remove,
1975         .dma_map = mlx5_dma_map,
1976         .dma_unmap = mlx5_dma_unmap,
1977         .drv_flags = PCI_DRV_FLAGS,
1978 };
1979
1980 /* Initialize driver log type. */
1981 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
1982
1983 /**
1984  * Driver initialization routine.
1985  */
1986 RTE_INIT(rte_mlx5_pmd_init)
1987 {
1988         /* Build the static tables for Verbs conversion. */
1989         mlx5_set_ptype_table();
1990         mlx5_set_cksum_table();
1991         mlx5_set_swp_types_table();
1992         if (mlx5_glue)
1993                 rte_pci_register(&mlx5_driver);
1994 }
1995
1996 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1997 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1998 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");