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5 * Copyright 2015 Mellanox.
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45 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
47 #pragma GCC diagnostic ignored "-Wpedantic"
49 #include <infiniband/verbs.h>
51 #pragma GCC diagnostic error "-Wpedantic"
54 #include <rte_malloc.h>
55 #include <rte_ethdev_driver.h>
56 #include <rte_ethdev_pci.h>
58 #include <rte_bus_pci.h>
59 #include <rte_common.h>
60 #include <rte_eal_memconfig.h>
61 #include <rte_kvargs.h>
64 #include "mlx5_utils.h"
65 #include "mlx5_rxtx.h"
66 #include "mlx5_autoconf.h"
67 #include "mlx5_defs.h"
68 #include "mlx5_glue.h"
70 /* Device parameter to enable RX completion queue compression. */
71 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
73 /* Device parameter to configure inline send. */
74 #define MLX5_TXQ_INLINE "txq_inline"
77 * Device parameter to configure the number of TX queues threshold for
78 * enabling inline send.
80 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
82 /* Device parameter to enable multi-packet send WQEs. */
83 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
85 /* Device parameter to include 2 dsegs in the title WQEBB. */
86 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
88 /* Device parameter to limit the size of inlining packet. */
89 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
91 /* Device parameter to enable hardware Tx vector. */
92 #define MLX5_TX_VEC_EN "tx_vec_en"
94 /* Device parameter to enable hardware Rx vector. */
95 #define MLX5_RX_VEC_EN "rx_vec_en"
97 #ifndef HAVE_IBV_MLX5_MOD_MPW
98 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
99 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
102 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
103 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
107 * Retrieve integer value from environment variable.
110 * Environment variable name.
113 * Integer value, 0 if the variable is not set.
116 mlx5_getenv_int(const char *name)
118 const char *val = getenv(name);
126 * Verbs callback to allocate a memory. This function should allocate the space
127 * according to the size provided residing inside a huge page.
128 * Please note that all allocation must respect the alignment from libmlx5
129 * (i.e. currently sysconf(_SC_PAGESIZE)).
132 * The size in bytes of the memory to allocate.
134 * A pointer to the callback data.
137 * a pointer to the allocate space.
140 mlx5_alloc_verbs_buf(size_t size, void *data)
142 struct priv *priv = data;
144 size_t alignment = sysconf(_SC_PAGESIZE);
145 unsigned int socket = SOCKET_ID_ANY;
147 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
148 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
150 socket = ctrl->socket;
151 } else if (priv->verbs_alloc_ctx.type ==
152 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
153 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
155 socket = ctrl->socket;
157 assert(data != NULL);
158 ret = rte_malloc_socket(__func__, size, alignment, socket);
159 DEBUG("Extern alloc size: %lu, align: %lu: %p", size, alignment, ret);
164 * Verbs callback to free a memory.
167 * A pointer to the memory to free.
169 * A pointer to the callback data.
172 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
174 assert(data != NULL);
175 DEBUG("Extern free request: %p", ptr);
180 * DPDK callback to close the device.
182 * Destroy all queues and objects, free memory.
185 * Pointer to Ethernet device structure.
188 mlx5_dev_close(struct rte_eth_dev *dev)
190 struct priv *priv = dev->data->dev_private;
195 DEBUG("%p: closing device \"%s\"",
197 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
198 /* In case mlx5_dev_stop() has not been called. */
199 priv_dev_interrupt_handler_uninstall(priv, dev);
200 priv_dev_traffic_disable(priv, dev);
201 /* Prevent crashes when queues are still in use. */
202 dev->rx_pkt_burst = removed_rx_burst;
203 dev->tx_pkt_burst = removed_tx_burst;
204 if (priv->rxqs != NULL) {
205 /* XXX race condition if mlx5_rx_burst() is still running. */
207 for (i = 0; (i != priv->rxqs_n); ++i)
208 mlx5_priv_rxq_release(priv, i);
212 if (priv->txqs != NULL) {
213 /* XXX race condition if mlx5_tx_burst() is still running. */
215 for (i = 0; (i != priv->txqs_n); ++i)
216 mlx5_priv_txq_release(priv, i);
220 if (priv->pd != NULL) {
221 assert(priv->ctx != NULL);
222 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
223 claim_zero(mlx5_glue->close_device(priv->ctx));
225 assert(priv->ctx == NULL);
226 if (priv->rss_conf.rss_key != NULL)
227 rte_free(priv->rss_conf.rss_key);
228 if (priv->reta_idx != NULL)
229 rte_free(priv->reta_idx);
230 priv_socket_uninit(priv);
231 ret = mlx5_priv_hrxq_ibv_verify(priv);
233 WARN("%p: some Hash Rx queue still remain", (void *)priv);
234 ret = mlx5_priv_ind_table_ibv_verify(priv);
236 WARN("%p: some Indirection table still remain", (void *)priv);
237 ret = mlx5_priv_rxq_ibv_verify(priv);
239 WARN("%p: some Verbs Rx queue still remain", (void *)priv);
240 ret = mlx5_priv_rxq_verify(priv);
242 WARN("%p: some Rx Queues still remain", (void *)priv);
243 ret = mlx5_priv_txq_ibv_verify(priv);
245 WARN("%p: some Verbs Tx queue still remain", (void *)priv);
246 ret = mlx5_priv_txq_verify(priv);
248 WARN("%p: some Tx Queues still remain", (void *)priv);
249 ret = priv_flow_verify(priv);
251 WARN("%p: some flows still remain", (void *)priv);
252 ret = priv_mr_verify(priv);
254 WARN("%p: some Memory Region still remain", (void *)priv);
256 memset(priv, 0, sizeof(*priv));
259 const struct eth_dev_ops mlx5_dev_ops = {
260 .dev_configure = mlx5_dev_configure,
261 .dev_start = mlx5_dev_start,
262 .dev_stop = mlx5_dev_stop,
263 .dev_set_link_down = mlx5_set_link_down,
264 .dev_set_link_up = mlx5_set_link_up,
265 .dev_close = mlx5_dev_close,
266 .promiscuous_enable = mlx5_promiscuous_enable,
267 .promiscuous_disable = mlx5_promiscuous_disable,
268 .allmulticast_enable = mlx5_allmulticast_enable,
269 .allmulticast_disable = mlx5_allmulticast_disable,
270 .link_update = mlx5_link_update,
271 .stats_get = mlx5_stats_get,
272 .stats_reset = mlx5_stats_reset,
273 .xstats_get = mlx5_xstats_get,
274 .xstats_reset = mlx5_xstats_reset,
275 .xstats_get_names = mlx5_xstats_get_names,
276 .dev_infos_get = mlx5_dev_infos_get,
277 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
278 .vlan_filter_set = mlx5_vlan_filter_set,
279 .rx_queue_setup = mlx5_rx_queue_setup,
280 .tx_queue_setup = mlx5_tx_queue_setup,
281 .rx_queue_release = mlx5_rx_queue_release,
282 .tx_queue_release = mlx5_tx_queue_release,
283 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
284 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
285 .mac_addr_remove = mlx5_mac_addr_remove,
286 .mac_addr_add = mlx5_mac_addr_add,
287 .mac_addr_set = mlx5_mac_addr_set,
288 .mtu_set = mlx5_dev_set_mtu,
289 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
290 .vlan_offload_set = mlx5_vlan_offload_set,
291 .reta_update = mlx5_dev_rss_reta_update,
292 .reta_query = mlx5_dev_rss_reta_query,
293 .rss_hash_update = mlx5_rss_hash_update,
294 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
295 .filter_ctrl = mlx5_dev_filter_ctrl,
296 .rx_descriptor_status = mlx5_rx_descriptor_status,
297 .tx_descriptor_status = mlx5_tx_descriptor_status,
298 .rx_queue_intr_enable = mlx5_rx_intr_enable,
299 .rx_queue_intr_disable = mlx5_rx_intr_disable,
300 .is_removed = mlx5_is_removed,
303 static const struct eth_dev_ops mlx5_dev_sec_ops = {
304 .stats_get = mlx5_stats_get,
305 .stats_reset = mlx5_stats_reset,
306 .xstats_get = mlx5_xstats_get,
307 .xstats_reset = mlx5_xstats_reset,
308 .xstats_get_names = mlx5_xstats_get_names,
309 .dev_infos_get = mlx5_dev_infos_get,
310 .rx_descriptor_status = mlx5_rx_descriptor_status,
311 .tx_descriptor_status = mlx5_tx_descriptor_status,
314 /* Available operators in flow isolated mode. */
315 const struct eth_dev_ops mlx5_dev_ops_isolate = {
316 .dev_configure = mlx5_dev_configure,
317 .dev_start = mlx5_dev_start,
318 .dev_stop = mlx5_dev_stop,
319 .dev_set_link_down = mlx5_set_link_down,
320 .dev_set_link_up = mlx5_set_link_up,
321 .dev_close = mlx5_dev_close,
322 .link_update = mlx5_link_update,
323 .stats_get = mlx5_stats_get,
324 .stats_reset = mlx5_stats_reset,
325 .xstats_get = mlx5_xstats_get,
326 .xstats_reset = mlx5_xstats_reset,
327 .xstats_get_names = mlx5_xstats_get_names,
328 .dev_infos_get = mlx5_dev_infos_get,
329 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
330 .vlan_filter_set = mlx5_vlan_filter_set,
331 .rx_queue_setup = mlx5_rx_queue_setup,
332 .tx_queue_setup = mlx5_tx_queue_setup,
333 .rx_queue_release = mlx5_rx_queue_release,
334 .tx_queue_release = mlx5_tx_queue_release,
335 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
336 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
337 .mac_addr_remove = mlx5_mac_addr_remove,
338 .mac_addr_add = mlx5_mac_addr_add,
339 .mac_addr_set = mlx5_mac_addr_set,
340 .mtu_set = mlx5_dev_set_mtu,
341 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
342 .vlan_offload_set = mlx5_vlan_offload_set,
343 .filter_ctrl = mlx5_dev_filter_ctrl,
344 .rx_descriptor_status = mlx5_rx_descriptor_status,
345 .tx_descriptor_status = mlx5_tx_descriptor_status,
346 .rx_queue_intr_enable = mlx5_rx_intr_enable,
347 .rx_queue_intr_disable = mlx5_rx_intr_disable,
348 .is_removed = mlx5_is_removed,
352 struct rte_pci_addr pci_addr; /* associated PCI address */
353 uint32_t ports; /* physical ports bitfield. */
357 * Get device index in mlx5_dev[] from PCI bus address.
359 * @param[in] pci_addr
360 * PCI bus address to look for.
363 * mlx5_dev[] index on success, -1 on failure.
366 mlx5_dev_idx(struct rte_pci_addr *pci_addr)
371 assert(pci_addr != NULL);
372 for (i = 0; (i != RTE_DIM(mlx5_dev)); ++i) {
373 if ((mlx5_dev[i].pci_addr.domain == pci_addr->domain) &&
374 (mlx5_dev[i].pci_addr.bus == pci_addr->bus) &&
375 (mlx5_dev[i].pci_addr.devid == pci_addr->devid) &&
376 (mlx5_dev[i].pci_addr.function == pci_addr->function))
378 if ((mlx5_dev[i].ports == 0) && (ret == -1))
385 * Verify and store value for device argument.
388 * Key argument to verify.
390 * Value associated with key.
395 * 0 on success, negative errno value on failure.
398 mlx5_args_check(const char *key, const char *val, void *opaque)
400 struct mlx5_dev_config *config = opaque;
404 tmp = strtoul(val, NULL, 0);
406 WARN("%s: \"%s\" is not a valid integer", key, val);
409 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
410 config->cqe_comp = !!tmp;
411 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
412 config->txq_inline = tmp;
413 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
414 config->txqs_inline = tmp;
415 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
416 config->mps = !!tmp ? config->mps : 0;
417 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
418 config->mpw_hdr_dseg = !!tmp;
419 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
420 config->inline_max_packet_sz = tmp;
421 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
422 config->tx_vec_en = !!tmp;
423 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
424 config->rx_vec_en = !!tmp;
426 WARN("%s: unknown parameter", key);
433 * Parse device parameters.
436 * Pointer to device configuration structure.
438 * Device arguments structure.
441 * 0 on success, errno value on failure.
444 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
446 const char **params = (const char *[]){
447 MLX5_RXQ_CQE_COMP_EN,
449 MLX5_TXQS_MIN_INLINE,
451 MLX5_TXQ_MPW_HDR_DSEG_EN,
452 MLX5_TXQ_MAX_INLINE_LEN,
457 struct rte_kvargs *kvlist;
463 /* Following UGLY cast is done to pass checkpatch. */
464 kvlist = rte_kvargs_parse(devargs->args, params);
467 /* Process parameters. */
468 for (i = 0; (params[i] != NULL); ++i) {
469 if (rte_kvargs_count(kvlist, params[i])) {
470 ret = rte_kvargs_process(kvlist, params[i],
471 mlx5_args_check, config);
473 rte_kvargs_free(kvlist);
478 rte_kvargs_free(kvlist);
482 static struct rte_pci_driver mlx5_driver;
485 * Reserved UAR address space for TXQ UAR(hw doorbell) mapping, process
486 * local resource used by both primary and secondary to avoid duplicate
488 * The space has to be available on both primary and secondary process,
489 * TXQ UAR maps to this area using fixed mmap w/o double check.
491 static void *uar_base;
494 * Reserve UAR address space for primary process.
497 * Pointer to private structure.
500 * 0 on success, errno value on failure.
503 priv_uar_init_primary(struct priv *priv)
505 void *addr = (void *)0;
507 const struct rte_mem_config *mcfg;
510 if (uar_base) { /* UAR address space mapped. */
511 priv->uar_base = uar_base;
514 /* find out lower bound of hugepage segments */
515 mcfg = rte_eal_get_configuration()->mem_config;
516 for (i = 0; i < RTE_MAX_MEMSEG && mcfg->memseg[i].addr; i++) {
518 addr = RTE_MIN(addr, mcfg->memseg[i].addr);
520 addr = mcfg->memseg[i].addr;
522 /* keep distance to hugepages to minimize potential conflicts. */
523 addr = RTE_PTR_SUB(addr, MLX5_UAR_OFFSET + MLX5_UAR_SIZE);
524 /* anonymous mmap, no real memory consumption. */
525 addr = mmap(addr, MLX5_UAR_SIZE,
526 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
527 if (addr == MAP_FAILED) {
528 ERROR("Failed to reserve UAR address space, please adjust "
529 "MLX5_UAR_SIZE or try --base-virtaddr");
533 /* Accept either same addr or a new addr returned from mmap if target
536 INFO("Reserved UAR address space: %p", addr);
537 priv->uar_base = addr; /* for primary and secondary UAR re-mmap. */
538 uar_base = addr; /* process local, don't reserve again. */
543 * Reserve UAR address space for secondary process, align with
547 * Pointer to private structure.
550 * 0 on success, errno value on failure.
553 priv_uar_init_secondary(struct priv *priv)
558 assert(priv->uar_base);
559 if (uar_base) { /* already reserved. */
560 assert(uar_base == priv->uar_base);
563 /* anonymous mmap, no real memory consumption. */
564 addr = mmap(priv->uar_base, MLX5_UAR_SIZE,
565 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
566 if (addr == MAP_FAILED) {
567 ERROR("UAR mmap failed: %p size: %llu",
568 priv->uar_base, MLX5_UAR_SIZE);
572 if (priv->uar_base != addr) {
573 ERROR("UAR address %p size %llu occupied, please adjust "
574 "MLX5_UAR_OFFSET or try EAL parameter --base-virtaddr",
575 priv->uar_base, MLX5_UAR_SIZE);
579 uar_base = addr; /* process local, don't reserve again */
580 INFO("Reserved UAR address space: %p", addr);
585 * DPDK callback to register a PCI device.
587 * This function creates an Ethernet device for each port of a given
591 * PCI driver structure (mlx5_driver).
593 * PCI device information.
596 * 0 on success, negative errno value on failure.
599 mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
601 struct ibv_device **list;
602 struct ibv_device *ibv_dev;
604 struct ibv_context *attr_ctx = NULL;
605 struct ibv_device_attr_ex device_attr;
608 unsigned int cqe_comp;
609 unsigned int tunnel_en = 0;
612 struct mlx5dv_context attrs_out;
613 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
614 struct ibv_counter_set_description cs_desc;
618 assert(pci_drv == &mlx5_driver);
619 /* Get mlx5_dev[] index. */
620 idx = mlx5_dev_idx(&pci_dev->addr);
622 ERROR("this driver cannot support any more adapters");
625 DEBUG("using driver device index %d", idx);
627 /* Save PCI address. */
628 mlx5_dev[idx].pci_addr = pci_dev->addr;
629 list = mlx5_glue->get_device_list(&i);
633 ERROR("cannot list devices, is ib_uverbs loaded?");
638 * For each listed device, check related sysfs entry against
639 * the provided PCI ID.
642 struct rte_pci_addr pci_addr;
645 DEBUG("checking device \"%s\"", list[i]->name);
646 if (mlx5_ibv_device_to_pci_addr(list[i], &pci_addr))
648 if ((pci_dev->addr.domain != pci_addr.domain) ||
649 (pci_dev->addr.bus != pci_addr.bus) ||
650 (pci_dev->addr.devid != pci_addr.devid) ||
651 (pci_dev->addr.function != pci_addr.function))
653 sriov = ((pci_dev->id.device_id ==
654 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) ||
655 (pci_dev->id.device_id ==
656 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) ||
657 (pci_dev->id.device_id ==
658 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) ||
659 (pci_dev->id.device_id ==
660 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF));
661 switch (pci_dev->id.device_id) {
662 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
665 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
666 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
667 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
668 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
669 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
675 INFO("PCI information matches, using device \"%s\""
678 sriov ? "true" : "false");
679 attr_ctx = mlx5_glue->open_device(list[i]);
683 if (attr_ctx == NULL) {
684 mlx5_glue->free_device_list(list);
687 ERROR("cannot access device, is mlx5_ib loaded?");
690 ERROR("cannot use device, are drivers up to date?");
698 DEBUG("device opened");
700 * Multi-packet send is supported by ConnectX-4 Lx PF as well
701 * as all ConnectX-5 devices.
703 mlx5_glue->dv_query_device(attr_ctx, &attrs_out);
704 if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
705 if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
706 DEBUG("Enhanced MPW is supported");
707 mps = MLX5_MPW_ENHANCED;
709 DEBUG("MPW is supported");
713 DEBUG("MPW isn't supported");
714 mps = MLX5_MPW_DISABLED;
716 if (RTE_CACHE_LINE_SIZE == 128 &&
717 !(attrs_out.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
721 if (mlx5_glue->query_device_ex(attr_ctx, NULL, &device_attr))
723 INFO("%u port(s) detected", device_attr.orig_attr.phys_port_cnt);
725 for (i = 0; i < device_attr.orig_attr.phys_port_cnt; i++) {
726 char name[RTE_ETH_NAME_MAX_LEN];
728 uint32_t port = i + 1; /* ports are indexed from one */
729 uint32_t test = (1 << i);
730 struct ibv_context *ctx = NULL;
731 struct ibv_port_attr port_attr;
732 struct ibv_pd *pd = NULL;
733 struct priv *priv = NULL;
734 struct rte_eth_dev *eth_dev;
735 struct ibv_device_attr_ex device_attr_ex;
736 struct ether_addr mac;
737 uint16_t num_vfs = 0;
738 struct ibv_device_attr_ex device_attr;
739 struct mlx5_dev_config config = {
740 .cqe_comp = cqe_comp,
742 .tunnel_en = tunnel_en,
746 .txq_inline = MLX5_ARG_UNSET,
747 .txqs_inline = MLX5_ARG_UNSET,
748 .inline_max_packet_sz = MLX5_ARG_UNSET,
751 len = snprintf(name, sizeof(name), PCI_PRI_FMT,
752 pci_dev->addr.domain, pci_dev->addr.bus,
753 pci_dev->addr.devid, pci_dev->addr.function);
754 if (device_attr.orig_attr.phys_port_cnt > 1)
755 snprintf(name + len, sizeof(name), " port %u", i);
757 mlx5_dev[idx].ports |= test;
759 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
760 eth_dev = rte_eth_dev_attach_secondary(name);
761 if (eth_dev == NULL) {
762 ERROR("can not attach rte ethdev");
766 eth_dev->device = &pci_dev->device;
767 eth_dev->dev_ops = &mlx5_dev_sec_ops;
768 priv = eth_dev->data->dev_private;
769 err = priv_uar_init_secondary(priv);
774 /* Receive command fd from primary process */
775 err = priv_socket_connect(priv);
780 /* Remap UAR for Tx queues. */
781 err = priv_tx_uar_remap(priv, err);
785 * Ethdev pointer is still required as input since
786 * the primary device is not accessible from the
789 eth_dev->rx_pkt_burst =
790 priv_select_rx_function(priv, eth_dev);
791 eth_dev->tx_pkt_burst =
792 priv_select_tx_function(priv, eth_dev);
796 DEBUG("using port %u (%08" PRIx32 ")", port, test);
798 ctx = mlx5_glue->open_device(ibv_dev);
804 mlx5_glue->query_device_ex(ctx, NULL, &device_attr);
805 /* Check port status. */
806 err = mlx5_glue->query_port(ctx, port, &port_attr);
808 ERROR("port query failed: %s", strerror(err));
812 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
813 ERROR("port %d is not configured in Ethernet mode",
819 if (port_attr.state != IBV_PORT_ACTIVE)
820 DEBUG("port %d is not active: \"%s\" (%d)",
821 port, mlx5_glue->port_state_str(port_attr.state),
824 /* Allocate protection domain. */
825 pd = mlx5_glue->alloc_pd(ctx);
827 ERROR("PD allocation failure");
832 mlx5_dev[idx].ports |= test;
834 /* from rte_ethdev.c */
835 priv = rte_zmalloc("ethdev private structure",
837 RTE_CACHE_LINE_SIZE);
839 ERROR("priv allocation failure");
845 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path,
846 sizeof(priv->ibdev_path));
847 priv->device_attr = device_attr;
850 priv->mtu = ETHER_MTU;
851 err = mlx5_args(&config, pci_dev->device.devargs);
853 ERROR("failed to process device arguments: %s",
857 if (mlx5_glue->query_device_ex(ctx, NULL, &device_attr_ex)) {
858 ERROR("ibv_query_device_ex() failed");
862 config.hw_csum = !!(device_attr_ex.device_cap_flags_ex &
863 IBV_DEVICE_RAW_IP_CSUM);
864 DEBUG("checksum offloading is %ssupported",
865 (config.hw_csum ? "" : "not "));
867 #ifdef HAVE_IBV_DEVICE_VXLAN_SUPPORT
868 config.hw_csum_l2tun =
869 !!(exp_device_attr.exp_device_cap_flags &
870 IBV_DEVICE_VXLAN_SUPPORT);
872 DEBUG("Rx L2 tunnel checksum offloads are %ssupported",
873 (config.hw_csum_l2tun ? "" : "not "));
875 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
876 config.flow_counter_en = !!(device_attr.max_counter_sets);
877 mlx5_glue->describe_counter_set(ctx, 0, &cs_desc);
878 DEBUG("counter type = %d, num of cs = %ld, attributes = %d",
879 cs_desc.counter_type, cs_desc.num_of_cs,
882 config.ind_table_max_size =
883 device_attr_ex.rss_caps.max_rwq_indirection_table_size;
884 /* Remove this check once DPDK supports larger/variable
885 * indirection tables. */
886 if (config.ind_table_max_size >
887 (unsigned int)ETH_RSS_RETA_SIZE_512)
888 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
889 DEBUG("maximum RX indirection table size is %u",
890 config.ind_table_max_size);
891 config.hw_vlan_strip = !!(device_attr_ex.raw_packet_caps &
892 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
893 DEBUG("VLAN stripping is %ssupported",
894 (config.hw_vlan_strip ? "" : "not "));
896 config.hw_fcs_strip =
897 !!(device_attr_ex.orig_attr.device_cap_flags &
898 IBV_WQ_FLAGS_SCATTER_FCS);
899 DEBUG("FCS stripping configuration is %ssupported",
900 (config.hw_fcs_strip ? "" : "not "));
902 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
903 config.hw_padding = !!device_attr_ex.rx_pad_end_addr_align;
905 DEBUG("hardware RX end alignment padding is %ssupported",
906 (config.hw_padding ? "" : "not "));
908 priv_get_num_vfs(priv, &num_vfs);
909 config.sriov = (num_vfs || sriov);
910 config.tso = ((device_attr_ex.tso_caps.max_tso > 0) &&
911 (device_attr_ex.tso_caps.supported_qpts &
912 (1 << IBV_QPT_RAW_PACKET)));
914 config.tso_max_payload_sz =
915 device_attr_ex.tso_caps.max_tso;
916 if (config.mps && !mps) {
917 ERROR("multi-packet send not supported on this device"
918 " (" MLX5_TXQ_MPW_EN ")");
923 config.mps == MLX5_MPW_ENHANCED ? "Enhanced " : "",
924 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
925 if (config.cqe_comp && !cqe_comp) {
926 WARN("Rx CQE compression isn't supported");
929 err = priv_uar_init_primary(priv);
932 /* Configure the first MAC address by default. */
933 if (priv_get_mac(priv, &mac.addr_bytes)) {
934 ERROR("cannot get MAC address, is mlx5_en loaded?"
935 " (errno: %s)", strerror(errno));
939 INFO("port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
941 mac.addr_bytes[0], mac.addr_bytes[1],
942 mac.addr_bytes[2], mac.addr_bytes[3],
943 mac.addr_bytes[4], mac.addr_bytes[5]);
946 char ifname[IF_NAMESIZE];
948 if (priv_get_ifname(priv, &ifname) == 0)
949 DEBUG("port %u ifname is \"%s\"",
952 DEBUG("port %u ifname is unknown", priv->port);
955 /* Get actual MTU if possible. */
956 priv_get_mtu(priv, &priv->mtu);
957 DEBUG("port %u MTU is %u", priv->port, priv->mtu);
959 eth_dev = rte_eth_dev_allocate(name);
960 if (eth_dev == NULL) {
961 ERROR("can not allocate rte ethdev");
965 eth_dev->data->dev_private = priv;
966 eth_dev->data->mac_addrs = priv->mac;
967 eth_dev->device = &pci_dev->device;
968 rte_eth_copy_pci_info(eth_dev, pci_dev);
969 eth_dev->device->driver = &mlx5_driver.driver;
971 * Initialize burst functions to prevent crashes before link-up.
973 eth_dev->rx_pkt_burst = removed_rx_burst;
974 eth_dev->tx_pkt_burst = removed_tx_burst;
976 eth_dev->dev_ops = &mlx5_dev_ops;
977 /* Register MAC address. */
978 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
979 TAILQ_INIT(&priv->flows);
980 TAILQ_INIT(&priv->ctrl_flows);
982 /* Hint libmlx5 to use PMD allocator for data plane resources */
983 struct mlx5dv_ctx_allocators alctr = {
984 .alloc = &mlx5_alloc_verbs_buf,
985 .free = &mlx5_free_verbs_buf,
988 mlx5_glue->dv_set_context_attr(ctx,
989 MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
990 (void *)((uintptr_t)&alctr));
992 /* Bring Ethernet device up. */
993 DEBUG("forcing Ethernet interface up");
994 priv_set_flags(priv, ~IFF_UP, IFF_UP);
995 /* Store device configuration on private structure. */
996 priv->config = config;
1003 claim_zero(mlx5_glue->dealloc_pd(pd));
1005 claim_zero(mlx5_glue->close_device(ctx));
1010 * XXX if something went wrong in the loop above, there is a resource
1011 * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as
1012 * long as the dpdk does not provide a way to deallocate a ethdev and a
1013 * way to enumerate the registered ethdevs to free the previous ones.
1016 /* no port found, complain */
1017 if (!mlx5_dev[idx].ports) {
1024 claim_zero(mlx5_glue->close_device(attr_ctx));
1026 mlx5_glue->free_device_list(list);
1031 static const struct rte_pci_id mlx5_pci_id_map[] = {
1033 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1034 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1037 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1038 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1041 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1042 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1045 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1046 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1049 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1050 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1053 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1054 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1057 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1058 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1061 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1062 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1069 static struct rte_pci_driver mlx5_driver = {
1071 .name = MLX5_DRIVER_NAME
1073 .id_table = mlx5_pci_id_map,
1074 .probe = mlx5_pci_probe,
1075 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV,
1079 * Driver initialization routine.
1081 RTE_INIT(rte_mlx5_pmd_init);
1083 rte_mlx5_pmd_init(void)
1085 /* Build the static table for ptype conversion. */
1086 mlx5_set_ptype_table();
1088 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
1089 * huge pages. Calling ibv_fork_init() during init allows
1090 * applications to use fork() safely for purposes other than
1091 * using this PMD, which is not supported in forked processes.
1093 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
1094 /* Match the size of Rx completion entry to the size of a cacheline. */
1095 if (RTE_CACHE_LINE_SIZE == 128)
1096 setenv("MLX5_CQE_SIZE", "128", 0);
1097 mlx5_glue->fork_init();
1098 rte_pci_register(&mlx5_driver);
1101 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1102 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1103 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");