drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <assert.h>
  10 #include <dlfcn.h>
  11 #include <stdint.h>
  12 #include <stdlib.h>
  13 #include <errno.h>
  14 #include <net/if.h>
  15 #include <sys/mman.h>
  16 #include <linux/rtnetlink.h>
  17
  18 /* Verbs header. */
  19 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  20 #ifdef PEDANTIC
  21 #pragma GCC diagnostic ignored "-Wpedantic"
  22 #endif
  23 #include <infiniband/verbs.h>
  24 #ifdef PEDANTIC
  25 #pragma GCC diagnostic error "-Wpedantic"
  26 #endif
  27
  28 #include <rte_malloc.h>
  29 #include <rte_ethdev_driver.h>
  30 #include <rte_ethdev_pci.h>
  31 #include <rte_pci.h>
  32 #include <rte_bus_pci.h>
  33 #include <rte_common.h>
  34 #include <rte_config.h>
  35 #include <rte_eal_memconfig.h>
  36 #include <rte_kvargs.h>
  37
  38 #include "mlx5.h"
  39 #include "mlx5_utils.h"
  40 #include "mlx5_rxtx.h"
  41 #include "mlx5_autoconf.h"
  42 #include "mlx5_defs.h"
  43 #include "mlx5_glue.h"
  44 #include "mlx5_mr.h"
  45
  46 /* Device parameter to enable RX completion queue compression. */
  47 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  48
  49 /* Device parameter to enable Multi-Packet Rx queue. */
  50 #define MLX5_RX_MPRQ_EN "mprq_en"
  51
  52 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  53 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  54
  55 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  56 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  57
  58 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  59 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  60
  61 /* Device parameter to configure inline send. */
  62 #define MLX5_TXQ_INLINE "txq_inline"
  63
  64 /*
  65  * Device parameter to configure the number of TX queues threshold for
  66  * enabling inline send.
  67  */
  68 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  69
  70 /* Device parameter to enable multi-packet send WQEs. */
  71 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  72
  73 /* Device parameter to include 2 dsegs in the title WQEBB. */
  74 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
  75
  76 /* Device parameter to limit the size of inlining packet. */
  77 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
  78
  79 /* Device parameter to enable hardware Tx vector. */
  80 #define MLX5_TX_VEC_EN "tx_vec_en"
  81
  82 /* Device parameter to enable hardware Rx vector. */
  83 #define MLX5_RX_VEC_EN "rx_vec_en"
  84
  85 /* Allow L3 VXLAN flow creation. */
  86 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
  87
  88 /* Activate Netlink support in VF mode. */
  89 #define MLX5_VF_NL_EN "vf_nl_en"
  90
  91 #ifndef HAVE_IBV_MLX5_MOD_MPW
  92 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
  93 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
  94 #endif
  95
  96 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
  97 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
  98 #endif
  99
 100 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
 101
 102 /* Shared memory between primary and secondary processes. */
 103 struct mlx5_shared_data *mlx5_shared_data;
 104
 105 /* Spinlock for mlx5_shared_data allocation. */
 106 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
 107
 108 /** Driver-specific log messages type. */
 109 int mlx5_logtype;
 110
 111 /**
 112  * Prepare shared data between primary and secondary process.
 113  */
 114 static void
 115 mlx5_prepare_shared_data(void)
 116 {
 117         const struct rte_memzone *mz;
 118
 119         rte_spinlock_lock(&mlx5_shared_data_lock);
 120         if (mlx5_shared_data == NULL) {
 121                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
 122                         /* Allocate shared memory. */
 123                         mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
 124                                                  sizeof(*mlx5_shared_data),
 125                                                  SOCKET_ID_ANY, 0);
 126                 } else {
 127                         /* Lookup allocated shared memory. */
 128                         mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
 129                 }
 130                 if (mz == NULL)
 131                         rte_panic("Cannot allocate mlx5 shared data\n");
 132                 mlx5_shared_data = mz->addr;
 133                 /* Initialize shared data. */
 134                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
 135                         LIST_INIT(&mlx5_shared_data->mem_event_cb_list);
 136                         rte_rwlock_init(&mlx5_shared_data->mem_event_rwlock);
 137                 }
 138         }
 139         rte_spinlock_unlock(&mlx5_shared_data_lock);
 140 }
 141
 142 /**
 143  * Retrieve integer value from environment variable.
 144  *
 145  * @param[in] name
 146  *   Environment variable name.
 147  *
 148  * @return
 149  *   Integer value, 0 if the variable is not set.
 150  */
 151 int
 152 mlx5_getenv_int(const char *name)
 153 {
 154         const char *val = getenv(name);
 155
 156         if (val == NULL)
 157                 return 0;
 158         return atoi(val);
 159 }
 160
 161 /**
 162  * Verbs callback to allocate a memory. This function should allocate the space
 163  * according to the size provided residing inside a huge page.
 164  * Please note that all allocation must respect the alignment from libmlx5
 165  * (i.e. currently sysconf(_SC_PAGESIZE)).
 166  *
 167  * @param[in] size
 168  *   The size in bytes of the memory to allocate.
 169  * @param[in] data
 170  *   A pointer to the callback data.
 171  *
 172  * @return
 173  *   Allocated buffer, NULL otherwise and rte_errno is set.
 174  */
 175 static void *
 176 mlx5_alloc_verbs_buf(size_t size, void *data)
 177 {
 178         struct priv *priv = data;
 179         void *ret;
 180         size_t alignment = sysconf(_SC_PAGESIZE);
 181         unsigned int socket = SOCKET_ID_ANY;
 182
 183         if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
 184                 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
 185
 186                 socket = ctrl->socket;
 187         } else if (priv->verbs_alloc_ctx.type ==
 188                    MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
 189                 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
 190
 191                 socket = ctrl->socket;
 192         }
 193         assert(data != NULL);
 194         ret = rte_malloc_socket(__func__, size, alignment, socket);
 195         if (!ret && size)
 196                 rte_errno = ENOMEM;
 197         return ret;
 198 }
 199
 200 /**
 201  * Verbs callback to free a memory.
 202  *
 203  * @param[in] ptr
 204  *   A pointer to the memory to free.
 205  * @param[in] data
 206  *   A pointer to the callback data.
 207  */
 208 static void
 209 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
 210 {
 211         assert(data != NULL);
 212         rte_free(ptr);
 213 }
 214
 215 /**
 216  * DPDK callback to close the device.
 217  *
 218  * Destroy all queues and objects, free memory.
 219  *
 220  * @param dev
 221  *   Pointer to Ethernet device structure.
 222  */
 223 static void
 224 mlx5_dev_close(struct rte_eth_dev *dev)
 225 {
 226         struct priv *priv = dev->data->dev_private;
 227         unsigned int i;
 228         int ret;
 229
 230         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
 231                 dev->data->port_id,
 232                 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
 233         /* In case mlx5_dev_stop() has not been called. */
 234         mlx5_dev_interrupt_handler_uninstall(dev);
 235         mlx5_traffic_disable(dev);
 236         /* Prevent crashes when queues are still in use. */
 237         dev->rx_pkt_burst = removed_rx_burst;
 238         dev->tx_pkt_burst = removed_tx_burst;
 239         if (priv->rxqs != NULL) {
 240                 /* XXX race condition if mlx5_rx_burst() is still running. */
 241                 usleep(1000);
 242                 for (i = 0; (i != priv->rxqs_n); ++i)
 243                         mlx5_rxq_release(dev, i);
 244                 priv->rxqs_n = 0;
 245                 priv->rxqs = NULL;
 246         }
 247         if (priv->txqs != NULL) {
 248                 /* XXX race condition if mlx5_tx_burst() is still running. */
 249                 usleep(1000);
 250                 for (i = 0; (i != priv->txqs_n); ++i)
 251                         mlx5_txq_release(dev, i);
 252                 priv->txqs_n = 0;
 253                 priv->txqs = NULL;
 254         }
 255         mlx5_flow_delete_drop_queue(dev);
 256         mlx5_mprq_free_mp(dev);
 257         mlx5_mr_release(dev);
 258         if (priv->pd != NULL) {
 259                 assert(priv->ctx != NULL);
 260                 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
 261                 claim_zero(mlx5_glue->close_device(priv->ctx));
 262         } else
 263                 assert(priv->ctx == NULL);
 264         if (priv->rss_conf.rss_key != NULL)
 265                 rte_free(priv->rss_conf.rss_key);
 266         if (priv->reta_idx != NULL)
 267                 rte_free(priv->reta_idx);
 268         if (priv->primary_socket)
 269                 mlx5_socket_uninit(dev);
 270         if (priv->config.vf)
 271                 mlx5_nl_mac_addr_flush(dev);
 272         if (priv->nl_socket >= 0)
 273                 close(priv->nl_socket);
 274         ret = mlx5_hrxq_ibv_verify(dev);
 275         if (ret)
 276                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
 277                         dev->data->port_id);
 278         ret = mlx5_ind_table_ibv_verify(dev);
 279         if (ret)
 280                 DRV_LOG(WARNING, "port %u some indirection table still remain",
 281                         dev->data->port_id);
 282         ret = mlx5_rxq_ibv_verify(dev);
 283         if (ret)
 284                 DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain",
 285                         dev->data->port_id);
 286         ret = mlx5_rxq_verify(dev);
 287         if (ret)
 288                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
 289                         dev->data->port_id);
 290         ret = mlx5_txq_ibv_verify(dev);
 291         if (ret)
 292                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
 293                         dev->data->port_id);
 294         ret = mlx5_txq_verify(dev);
 295         if (ret)
 296                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
 297                         dev->data->port_id);
 298         ret = mlx5_flow_verify(dev);
 299         if (ret)
 300                 DRV_LOG(WARNING, "port %u some flows still remain",
 301                         dev->data->port_id);
 302         memset(priv, 0, sizeof(*priv));
 303 }
 304
 305 const struct eth_dev_ops mlx5_dev_ops = {
 306         .dev_configure = mlx5_dev_configure,
 307         .dev_start = mlx5_dev_start,
 308         .dev_stop = mlx5_dev_stop,
 309         .dev_set_link_down = mlx5_set_link_down,
 310         .dev_set_link_up = mlx5_set_link_up,
 311         .dev_close = mlx5_dev_close,
 312         .promiscuous_enable = mlx5_promiscuous_enable,
 313         .promiscuous_disable = mlx5_promiscuous_disable,
 314         .allmulticast_enable = mlx5_allmulticast_enable,
 315         .allmulticast_disable = mlx5_allmulticast_disable,
 316         .link_update = mlx5_link_update,
 317         .stats_get = mlx5_stats_get,
 318         .stats_reset = mlx5_stats_reset,
 319         .xstats_get = mlx5_xstats_get,
 320         .xstats_reset = mlx5_xstats_reset,
 321         .xstats_get_names = mlx5_xstats_get_names,
 322         .dev_infos_get = mlx5_dev_infos_get,
 323         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
 324         .vlan_filter_set = mlx5_vlan_filter_set,
 325         .rx_queue_setup = mlx5_rx_queue_setup,
 326         .tx_queue_setup = mlx5_tx_queue_setup,
 327         .rx_queue_release = mlx5_rx_queue_release,
 328         .tx_queue_release = mlx5_tx_queue_release,
 329         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
 330         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
 331         .mac_addr_remove = mlx5_mac_addr_remove,
 332         .mac_addr_add = mlx5_mac_addr_add,
 333         .mac_addr_set = mlx5_mac_addr_set,
 334         .set_mc_addr_list = mlx5_set_mc_addr_list,
 335         .mtu_set = mlx5_dev_set_mtu,
 336         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
 337         .vlan_offload_set = mlx5_vlan_offload_set,
 338         .reta_update = mlx5_dev_rss_reta_update,
 339         .reta_query = mlx5_dev_rss_reta_query,
 340         .rss_hash_update = mlx5_rss_hash_update,
 341         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
 342         .filter_ctrl = mlx5_dev_filter_ctrl,
 343         .rx_descriptor_status = mlx5_rx_descriptor_status,
 344         .tx_descriptor_status = mlx5_tx_descriptor_status,
 345         .rx_queue_intr_enable = mlx5_rx_intr_enable,
 346         .rx_queue_intr_disable = mlx5_rx_intr_disable,
 347         .is_removed = mlx5_is_removed,
 348 };
 349
 350 static const struct eth_dev_ops mlx5_dev_sec_ops = {
 351         .stats_get = mlx5_stats_get,
 352         .stats_reset = mlx5_stats_reset,
 353         .xstats_get = mlx5_xstats_get,
 354         .xstats_reset = mlx5_xstats_reset,
 355         .xstats_get_names = mlx5_xstats_get_names,
 356         .dev_infos_get = mlx5_dev_infos_get,
 357         .rx_descriptor_status = mlx5_rx_descriptor_status,
 358         .tx_descriptor_status = mlx5_tx_descriptor_status,
 359 };
 360
 361 /* Available operators in flow isolated mode. */
 362 const struct eth_dev_ops mlx5_dev_ops_isolate = {
 363         .dev_configure = mlx5_dev_configure,
 364         .dev_start = mlx5_dev_start,
 365         .dev_stop = mlx5_dev_stop,
 366         .dev_set_link_down = mlx5_set_link_down,
 367         .dev_set_link_up = mlx5_set_link_up,
 368         .dev_close = mlx5_dev_close,
 369         .link_update = mlx5_link_update,
 370         .stats_get = mlx5_stats_get,
 371         .stats_reset = mlx5_stats_reset,
 372         .xstats_get = mlx5_xstats_get,
 373         .xstats_reset = mlx5_xstats_reset,
 374         .xstats_get_names = mlx5_xstats_get_names,
 375         .dev_infos_get = mlx5_dev_infos_get,
 376         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
 377         .vlan_filter_set = mlx5_vlan_filter_set,
 378         .rx_queue_setup = mlx5_rx_queue_setup,
 379         .tx_queue_setup = mlx5_tx_queue_setup,
 380         .rx_queue_release = mlx5_rx_queue_release,
 381         .tx_queue_release = mlx5_tx_queue_release,
 382         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
 383         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
 384         .mac_addr_remove = mlx5_mac_addr_remove,
 385         .mac_addr_add = mlx5_mac_addr_add,
 386         .mac_addr_set = mlx5_mac_addr_set,
 387         .set_mc_addr_list = mlx5_set_mc_addr_list,
 388         .mtu_set = mlx5_dev_set_mtu,
 389         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
 390         .vlan_offload_set = mlx5_vlan_offload_set,
 391         .filter_ctrl = mlx5_dev_filter_ctrl,
 392         .rx_descriptor_status = mlx5_rx_descriptor_status,
 393         .tx_descriptor_status = mlx5_tx_descriptor_status,
 394         .rx_queue_intr_enable = mlx5_rx_intr_enable,
 395         .rx_queue_intr_disable = mlx5_rx_intr_disable,
 396         .is_removed = mlx5_is_removed,
 397 };
 398
 399 static struct {
 400         struct rte_pci_addr pci_addr; /* associated PCI address */
 401         uint32_t ports; /* physical ports bitfield. */
 402 } mlx5_dev[32];
 403
 404 /**
 405  * Get device index in mlx5_dev[] from PCI bus address.
 406  *
 407  * @param[in] pci_addr
 408  *   PCI bus address to look for.
 409  *
 410  * @return
 411  *   mlx5_dev[] index on success, -1 on failure.
 412  */
 413 static int
 414 mlx5_dev_idx(struct rte_pci_addr *pci_addr)
 415 {
 416         unsigned int i;
 417         int ret = -1;
 418
 419         assert(pci_addr != NULL);
 420         for (i = 0; (i != RTE_DIM(mlx5_dev)); ++i) {
 421                 if ((mlx5_dev[i].pci_addr.domain == pci_addr->domain) &&
 422                     (mlx5_dev[i].pci_addr.bus == pci_addr->bus) &&
 423                     (mlx5_dev[i].pci_addr.devid == pci_addr->devid) &&
 424                     (mlx5_dev[i].pci_addr.function == pci_addr->function))
 425                         return i;
 426                 if ((mlx5_dev[i].ports == 0) && (ret == -1))
 427                         ret = i;
 428         }
 429         return ret;
 430 }
 431
 432 /**
 433  * Verify and store value for device argument.
 434  *
 435  * @param[in] key
 436  *   Key argument to verify.
 437  * @param[in] val
 438  *   Value associated with key.
 439  * @param opaque
 440  *   User data.
 441  *
 442  * @return
 443  *   0 on success, a negative errno value otherwise and rte_errno is set.
 444  */
 445 static int
 446 mlx5_args_check(const char *key, const char *val, void *opaque)
 447 {
 448         struct mlx5_dev_config *config = opaque;
 449         unsigned long tmp;
 450
 451         errno = 0;
 452         tmp = strtoul(val, NULL, 0);
 453         if (errno) {
 454                 rte_errno = errno;
 455                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
 456                 return -rte_errno;
 457         }
 458         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
 459                 config->cqe_comp = !!tmp;
 460         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
 461                 config->mprq.enabled = !!tmp;
 462         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
 463                 config->mprq.stride_num_n = tmp;
 464         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
 465                 config->mprq.max_memcpy_len = tmp;
 466         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
 467                 config->mprq.min_rxqs_num = tmp;
 468         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
 469                 config->txq_inline = tmp;
 470         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
 471                 config->txqs_inline = tmp;
 472         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
 473                 config->mps = !!tmp ? config->mps : 0;
 474         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
 475                 config->mpw_hdr_dseg = !!tmp;
 476         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
 477                 config->inline_max_packet_sz = tmp;
 478         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
 479                 config->tx_vec_en = !!tmp;
 480         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
 481                 config->rx_vec_en = !!tmp;
 482         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
 483                 config->l3_vxlan_en = !!tmp;
 484         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
 485                 config->vf_nl_en = !!tmp;
 486         } else {
 487                 DRV_LOG(WARNING, "%s: unknown parameter", key);
 488                 rte_errno = EINVAL;
 489                 return -rte_errno;
 490         }
 491         return 0;
 492 }
 493
 494 /**
 495  * Parse device parameters.
 496  *
 497  * @param config
 498  *   Pointer to device configuration structure.
 499  * @param devargs
 500  *   Device arguments structure.
 501  *
 502  * @return
 503  *   0 on success, a negative errno value otherwise and rte_errno is set.
 504  */
 505 static int
 506 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
 507 {
 508         const char **params = (const char *[]){
 509                 MLX5_RXQ_CQE_COMP_EN,
 510                 MLX5_RX_MPRQ_EN,
 511                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
 512                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
 513                 MLX5_RXQS_MIN_MPRQ,
 514                 MLX5_TXQ_INLINE,
 515                 MLX5_TXQS_MIN_INLINE,
 516                 MLX5_TXQ_MPW_EN,
 517                 MLX5_TXQ_MPW_HDR_DSEG_EN,
 518                 MLX5_TXQ_MAX_INLINE_LEN,
 519                 MLX5_TX_VEC_EN,
 520                 MLX5_RX_VEC_EN,
 521                 MLX5_L3_VXLAN_EN,
 522                 MLX5_VF_NL_EN,
 523                 NULL,
 524         };
 525         struct rte_kvargs *kvlist;
 526         int ret = 0;
 527         int i;
 528
 529         if (devargs == NULL)
 530                 return 0;
 531         /* Following UGLY cast is done to pass checkpatch. */
 532         kvlist = rte_kvargs_parse(devargs->args, params);
 533         if (kvlist == NULL)
 534                 return 0;
 535         /* Process parameters. */
 536         for (i = 0; (params[i] != NULL); ++i) {
 537                 if (rte_kvargs_count(kvlist, params[i])) {
 538                         ret = rte_kvargs_process(kvlist, params[i],
 539                                                  mlx5_args_check, config);
 540                         if (ret) {
 541                                 rte_errno = EINVAL;
 542                                 rte_kvargs_free(kvlist);
 543                                 return -rte_errno;
 544                         }
 545                 }
 546         }
 547         rte_kvargs_free(kvlist);
 548         return 0;
 549 }
 550
 551 static struct rte_pci_driver mlx5_driver;
 552
 553 /*
 554  * Reserved UAR address space for TXQ UAR(hw doorbell) mapping, process
 555  * local resource used by both primary and secondary to avoid duplicate
 556  * reservation.
 557  * The space has to be available on both primary and secondary process,
 558  * TXQ UAR maps to this area using fixed mmap w/o double check.
 559  */
 560 static void *uar_base;
 561
 562 static int
 563 find_lower_va_bound(const struct rte_memseg_list *msl __rte_unused,
 564                 const struct rte_memseg *ms, void *arg)
 565 {
 566         void **addr = arg;
 567
 568         if (*addr == NULL)
 569                 *addr = ms->addr;
 570         else
 571                 *addr = RTE_MIN(*addr, ms->addr);
 572
 573         return 0;
 574 }
 575
 576 /**
 577  * Reserve UAR address space for primary process.
 578  *
 579  * @param[in] dev
 580  *   Pointer to Ethernet device.
 581  *
 582  * @return
 583  *   0 on success, a negative errno value otherwise and rte_errno is set.
 584  */
 585 static int
 586 mlx5_uar_init_primary(struct rte_eth_dev *dev)
 587 {
 588         struct priv *priv = dev->data->dev_private;
 589         void *addr = (void *)0;
 590
 591         if (uar_base) { /* UAR address space mapped. */
 592                 priv->uar_base = uar_base;
 593                 return 0;
 594         }
 595         /* find out lower bound of hugepage segments */
 596         rte_memseg_walk(find_lower_va_bound, &addr);
 597
 598         /* keep distance to hugepages to minimize potential conflicts. */
 599         addr = RTE_PTR_SUB(addr, MLX5_UAR_OFFSET + MLX5_UAR_SIZE);
 600         /* anonymous mmap, no real memory consumption. */
 601         addr = mmap(addr, MLX5_UAR_SIZE,
 602                     PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
 603         if (addr == MAP_FAILED) {
 604                 DRV_LOG(ERR,
 605                         "port %u failed to reserve UAR address space, please"
 606                         " adjust MLX5_UAR_SIZE or try --base-virtaddr",
 607                         dev->data->port_id);
 608                 rte_errno = ENOMEM;
 609                 return -rte_errno;
 610         }
 611         /* Accept either same addr or a new addr returned from mmap if target
 612          * range occupied.
 613          */
 614         DRV_LOG(INFO, "port %u reserved UAR address space: %p",
 615                 dev->data->port_id, addr);
 616         priv->uar_base = addr; /* for primary and secondary UAR re-mmap. */
 617         uar_base = addr; /* process local, don't reserve again. */
 618         return 0;
 619 }
 620
 621 /**
 622  * Reserve UAR address space for secondary process, align with
 623  * primary process.
 624  *
 625  * @param[in] dev
 626  *   Pointer to Ethernet device.
 627  *
 628  * @return
 629  *   0 on success, a negative errno value otherwise and rte_errno is set.
 630  */
 631 static int
 632 mlx5_uar_init_secondary(struct rte_eth_dev *dev)
 633 {
 634         struct priv *priv = dev->data->dev_private;
 635         void *addr;
 636
 637         assert(priv->uar_base);
 638         if (uar_base) { /* already reserved. */
 639                 assert(uar_base == priv->uar_base);
 640                 return 0;
 641         }
 642         /* anonymous mmap, no real memory consumption. */
 643         addr = mmap(priv->uar_base, MLX5_UAR_SIZE,
 644                     PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
 645         if (addr == MAP_FAILED) {
 646                 DRV_LOG(ERR, "port %u UAR mmap failed: %p size: %llu",
 647                         dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
 648                 rte_errno = ENXIO;
 649                 return -rte_errno;
 650         }
 651         if (priv->uar_base != addr) {
 652                 DRV_LOG(ERR,
 653                         "port %u UAR address %p size %llu occupied, please"
 654                         " adjust MLX5_UAR_OFFSET or try EAL parameter"
 655                         " --base-virtaddr",
 656                         dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
 657                 rte_errno = ENXIO;
 658                 return -rte_errno;
 659         }
 660         uar_base = addr; /* process local, don't reserve again */
 661         DRV_LOG(INFO, "port %u reserved UAR address space: %p",
 662                 dev->data->port_id, addr);
 663         return 0;
 664 }
 665
 666 /**
 667  * DPDK callback to register a PCI device.
 668  *
 669  * This function creates an Ethernet device for each port of a given
 670  * PCI device.
 671  *
 672  * @param[in] pci_drv
 673  *   PCI driver structure (mlx5_driver).
 674  * @param[in] pci_dev
 675  *   PCI device information.
 676  *
 677  * @return
 678  *   0 on success, a negative errno value otherwise and rte_errno is set.
 679  */
 680 static int
 681 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 682                struct rte_pci_device *pci_dev)
 683 {
 684         struct ibv_device **list = NULL;
 685         struct ibv_device *ibv_dev;
 686         int err = 0;
 687         struct ibv_context *attr_ctx = NULL;
 688         struct ibv_device_attr_ex device_attr;
 689         unsigned int vf = 0;
 690         unsigned int mps;
 691         unsigned int cqe_comp;
 692         unsigned int tunnel_en = 0;
 693         unsigned int mpls_en = 0;
 694         unsigned int swp = 0;
 695         unsigned int verb_priorities = 0;
 696         unsigned int mprq = 0;
 697         unsigned int mprq_min_stride_size_n = 0;
 698         unsigned int mprq_max_stride_size_n = 0;
 699         unsigned int mprq_min_stride_num_n = 0;
 700         unsigned int mprq_max_stride_num_n = 0;
 701         int idx;
 702         int i;
 703         struct mlx5dv_context attrs_out = {0};
 704 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
 705         struct ibv_counter_set_description cs_desc;
 706 #endif
 707
 708         /* Prepare shared data between primary and secondary process. */
 709         mlx5_prepare_shared_data();
 710         assert(pci_drv == &mlx5_driver);
 711         /* Get mlx5_dev[] index. */
 712         idx = mlx5_dev_idx(&pci_dev->addr);
 713         if (idx == -1) {
 714                 DRV_LOG(ERR, "this driver cannot support any more adapters");
 715                 err = ENOMEM;
 716                 goto error;
 717         }
 718         DRV_LOG(DEBUG, "using driver device index %d", idx);
 719         /* Save PCI address. */
 720         mlx5_dev[idx].pci_addr = pci_dev->addr;
 721         list = mlx5_glue->get_device_list(&i);
 722         if (list == NULL) {
 723                 assert(errno);
 724                 err = errno;
 725                 if (errno == ENOSYS)
 726                         DRV_LOG(ERR,
 727                                 "cannot list devices, is ib_uverbs loaded?");
 728                 goto error;
 729         }
 730         assert(i >= 0);
 731         /*
 732          * For each listed device, check related sysfs entry against
 733          * the provided PCI ID.
 734          */
 735         while (i != 0) {
 736                 struct rte_pci_addr pci_addr;
 737
 738                 --i;
 739                 DRV_LOG(DEBUG, "checking device \"%s\"", list[i]->name);
 740                 if (mlx5_ibv_device_to_pci_addr(list[i], &pci_addr))
 741                         continue;
 742                 if ((pci_dev->addr.domain != pci_addr.domain) ||
 743                     (pci_dev->addr.bus != pci_addr.bus) ||
 744                     (pci_dev->addr.devid != pci_addr.devid) ||
 745                     (pci_dev->addr.function != pci_addr.function))
 746                         continue;
 747                 DRV_LOG(INFO, "PCI information matches, using device \"%s\"",
 748                         list[i]->name);
 749                 vf = ((pci_dev->id.device_id ==
 750                        PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) ||
 751                       (pci_dev->id.device_id ==
 752                        PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) ||
 753                       (pci_dev->id.device_id ==
 754                        PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) ||
 755                       (pci_dev->id.device_id ==
 756                        PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF));
 757                 attr_ctx = mlx5_glue->open_device(list[i]);
 758                 rte_errno = errno;
 759                 err = rte_errno;
 760                 break;
 761         }
 762         if (attr_ctx == NULL) {
 763                 switch (err) {
 764                 case 0:
 765                         DRV_LOG(ERR,
 766                                 "cannot access device, is mlx5_ib loaded?");
 767                         err = ENODEV;
 768                         break;
 769                 case EINVAL:
 770                         DRV_LOG(ERR,
 771                                 "cannot use device, are drivers up to date?");
 772                         break;
 773                 }
 774                 goto error;
 775         }
 776         ibv_dev = list[i];
 777         DRV_LOG(DEBUG, "device opened");
 778 #ifdef HAVE_IBV_MLX5_MOD_SWP
 779         attrs_out.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
 780 #endif
 781         /*
 782          * Multi-packet send is supported by ConnectX-4 Lx PF as well
 783          * as all ConnectX-5 devices.
 784          */
 785 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
 786         attrs_out.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
 787 #endif
 788 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
 789         attrs_out.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
 790 #endif
 791         mlx5_glue->dv_query_device(attr_ctx, &attrs_out);
 792         if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
 793                 if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
 794                         DRV_LOG(DEBUG, "enhanced MPW is supported");
 795                         mps = MLX5_MPW_ENHANCED;
 796                 } else {
 797                         DRV_LOG(DEBUG, "MPW is supported");
 798                         mps = MLX5_MPW;
 799                 }
 800         } else {
 801                 DRV_LOG(DEBUG, "MPW isn't supported");
 802                 mps = MLX5_MPW_DISABLED;
 803         }
 804 #ifdef HAVE_IBV_MLX5_MOD_SWP
 805         if (attrs_out.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
 806                 swp = attrs_out.sw_parsing_caps.sw_parsing_offloads;
 807         DRV_LOG(DEBUG, "SWP support: %u", swp);
 808 #endif
 809 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
 810         if (attrs_out.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
 811                 struct mlx5dv_striding_rq_caps mprq_caps =
 812                         attrs_out.striding_rq_caps;
 813
 814                 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
 815                         mprq_caps.min_single_stride_log_num_of_bytes);
 816                 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
 817                         mprq_caps.max_single_stride_log_num_of_bytes);
 818                 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
 819                         mprq_caps.min_single_wqe_log_num_of_strides);
 820                 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
 821                         mprq_caps.max_single_wqe_log_num_of_strides);
 822                 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
 823                         mprq_caps.supported_qpts);
 824                 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
 825                 mprq = 1;
 826                 mprq_min_stride_size_n =
 827                         mprq_caps.min_single_stride_log_num_of_bytes;
 828                 mprq_max_stride_size_n =
 829                         mprq_caps.max_single_stride_log_num_of_bytes;
 830                 mprq_min_stride_num_n =
 831                         mprq_caps.min_single_wqe_log_num_of_strides;
 832                 mprq_max_stride_num_n =
 833                         mprq_caps.max_single_wqe_log_num_of_strides;
 834         }
 835 #endif
 836         if (RTE_CACHE_LINE_SIZE == 128 &&
 837             !(attrs_out.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
 838                 cqe_comp = 0;
 839         else
 840                 cqe_comp = 1;
 841 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
 842         if (attrs_out.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
 843                 tunnel_en = ((attrs_out.tunnel_offloads_caps &
 844                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
 845                              (attrs_out.tunnel_offloads_caps &
 846                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE));
 847         }
 848         DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
 849                 tunnel_en ? "" : "not ");
 850 #else
 851         DRV_LOG(WARNING,
 852                 "tunnel offloading disabled due to old OFED/rdma-core version");
 853 #endif
 854 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
 855         mpls_en = ((attrs_out.tunnel_offloads_caps &
 856                     MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
 857                    (attrs_out.tunnel_offloads_caps &
 858                     MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
 859         DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
 860                 mpls_en ? "" : "not ");
 861 #else
 862         DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
 863                 " old OFED/rdma-core version or firmware configuration");
 864 #endif
 865         err = mlx5_glue->query_device_ex(attr_ctx, NULL, &device_attr);
 866         if (err) {
 867                 DEBUG("ibv_query_device_ex() failed");
 868                 goto error;
 869         }
 870         DRV_LOG(INFO, "%u port(s) detected",
 871                 device_attr.orig_attr.phys_port_cnt);
 872         for (i = 0; i < device_attr.orig_attr.phys_port_cnt; i++) {
 873                 char name[RTE_ETH_NAME_MAX_LEN];
 874                 int len;
 875                 uint32_t port = i + 1; /* ports are indexed from one */
 876                 uint32_t test = (1 << i);
 877                 struct ibv_context *ctx = NULL;
 878                 struct ibv_port_attr port_attr;
 879                 struct ibv_pd *pd = NULL;
 880                 struct priv *priv = NULL;
 881                 struct rte_eth_dev *eth_dev = NULL;
 882                 struct ibv_device_attr_ex device_attr_ex;
 883                 struct ether_addr mac;
 884                 struct mlx5_dev_config config = {
 885                         .cqe_comp = cqe_comp,
 886                         .mps = mps,
 887                         .tunnel_en = tunnel_en,
 888                         .mpls_en = mpls_en,
 889                         .tx_vec_en = 1,
 890                         .rx_vec_en = 1,
 891                         .mpw_hdr_dseg = 0,
 892                         .txq_inline = MLX5_ARG_UNSET,
 893                         .txqs_inline = MLX5_ARG_UNSET,
 894                         .inline_max_packet_sz = MLX5_ARG_UNSET,
 895                         .vf_nl_en = 1,
 896                         .swp = !!swp,
 897                         .mprq = {
 898                                 .enabled = 0, /* Disabled by default. */
 899                                 .stride_num_n = RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
 900                                                         mprq_min_stride_num_n),
 901                                 .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
 902                                 .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
 903                         },
 904                 };
 905
 906                 len = snprintf(name, sizeof(name), PCI_PRI_FMT,
 907                          pci_dev->addr.domain, pci_dev->addr.bus,
 908                          pci_dev->addr.devid, pci_dev->addr.function);
 909                 if (device_attr.orig_attr.phys_port_cnt > 1)
 910                         snprintf(name + len, sizeof(name), " port %u", i);
 911                 mlx5_dev[idx].ports |= test;
 912                 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
 913                         eth_dev = rte_eth_dev_attach_secondary(name);
 914                         if (eth_dev == NULL) {
 915                                 DRV_LOG(ERR, "can not attach rte ethdev");
 916                                 rte_errno = ENOMEM;
 917                                 err = rte_errno;
 918                                 goto error;
 919                         }
 920                         eth_dev->device = &pci_dev->device;
 921                         eth_dev->dev_ops = &mlx5_dev_sec_ops;
 922                         err = mlx5_uar_init_secondary(eth_dev);
 923                         if (err) {
 924                                 err = rte_errno;
 925                                 goto error;
 926                         }
 927                         /* Receive command fd from primary process */
 928                         err = mlx5_socket_connect(eth_dev);
 929                         if (err < 0) {
 930                                 err = rte_errno;
 931                                 goto error;
 932                         }
 933                         /* Remap UAR for Tx queues. */
 934                         err = mlx5_tx_uar_remap(eth_dev, err);
 935                         if (err) {
 936                                 err = rte_errno;
 937                                 goto error;
 938                         }
 939                         /*
 940                          * Ethdev pointer is still required as input since
 941                          * the primary device is not accessible from the
 942                          * secondary process.
 943                          */
 944                         eth_dev->rx_pkt_burst =
 945                                 mlx5_select_rx_function(eth_dev);
 946                         eth_dev->tx_pkt_burst =
 947                                 mlx5_select_tx_function(eth_dev);
 948                         rte_eth_dev_probing_finish(eth_dev);
 949                         continue;
 950                 }
 951                 DRV_LOG(DEBUG, "using port %u (%08" PRIx32 ")", port, test);
 952                 ctx = mlx5_glue->open_device(ibv_dev);
 953                 if (ctx == NULL) {
 954                         err = ENODEV;
 955                         goto port_error;
 956                 }
 957                 /* Check port status. */
 958                 err = mlx5_glue->query_port(ctx, port, &port_attr);
 959                 if (err) {
 960                         DRV_LOG(ERR, "port query failed: %s", strerror(err));
 961                         goto port_error;
 962                 }
 963                 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
 964                         DRV_LOG(ERR,
 965                                 "port %d is not configured in Ethernet mode",
 966                                 port);
 967                         err = EINVAL;
 968                         goto port_error;
 969                 }
 970                 if (port_attr.state != IBV_PORT_ACTIVE)
 971                         DRV_LOG(DEBUG, "port %d is not active: \"%s\" (%d)",
 972                                 port,
 973                                 mlx5_glue->port_state_str(port_attr.state),
 974                                 port_attr.state);
 975                 /* Allocate protection domain. */
 976                 pd = mlx5_glue->alloc_pd(ctx);
 977                 if (pd == NULL) {
 978                         DRV_LOG(ERR, "PD allocation failure");
 979                         err = ENOMEM;
 980                         goto port_error;
 981                 }
 982                 mlx5_dev[idx].ports |= test;
 983                 /* from rte_ethdev.c */
 984                 priv = rte_zmalloc("ethdev private structure",
 985                                    sizeof(*priv),
 986                                    RTE_CACHE_LINE_SIZE);
 987                 if (priv == NULL) {
 988                         DRV_LOG(ERR, "priv allocation failure");
 989                         err = ENOMEM;
 990                         goto port_error;
 991                 }
 992                 priv->ctx = ctx;
 993                 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path,
 994                         sizeof(priv->ibdev_path));
 995                 priv->device_attr = device_attr;
 996                 priv->port = port;
 997                 priv->pd = pd;
 998                 priv->mtu = ETHER_MTU;
 999                 err = mlx5_args(&config, pci_dev->device.devargs);
1000                 if (err) {
1001                         DRV_LOG(ERR, "failed to process device arguments: %s",
1002                                 strerror(err));
1003                         err = rte_errno;
1004                         goto port_error;
1005                 }
1006                 err = mlx5_glue->query_device_ex(ctx, NULL, &device_attr_ex);
1007                 if (err) {
1008                         DRV_LOG(ERR, "ibv_query_device_ex() failed");
1009                         goto port_error;
1010                 }
1011                 config.hw_csum = !!(device_attr_ex.device_cap_flags_ex &
1012                                     IBV_DEVICE_RAW_IP_CSUM);
1013                 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
1014                         (config.hw_csum ? "" : "not "));
1015 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
1016                 config.flow_counter_en = !!(device_attr.max_counter_sets);
1017                 mlx5_glue->describe_counter_set(ctx, 0, &cs_desc);
1018                 DRV_LOG(DEBUG,
1019                         "counter type = %d, num of cs = %ld, attributes = %d",
1020                         cs_desc.counter_type, cs_desc.num_of_cs,
1021                         cs_desc.attributes);
1022 #endif
1023                 config.ind_table_max_size =
1024                         device_attr_ex.rss_caps.max_rwq_indirection_table_size;
1025                 /* Remove this check once DPDK supports larger/variable
1026                  * indirection tables. */
1027                 if (config.ind_table_max_size >
1028                                 (unsigned int)ETH_RSS_RETA_SIZE_512)
1029                         config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
1030                 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
1031                         config.ind_table_max_size);
1032                 config.hw_vlan_strip = !!(device_attr_ex.raw_packet_caps &
1033                                          IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
1034                 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
1035                         (config.hw_vlan_strip ? "" : "not "));
1036
1037                 config.hw_fcs_strip = !!(device_attr_ex.raw_packet_caps &
1038                                          IBV_RAW_PACKET_CAP_SCATTER_FCS);
1039                 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
1040                         (config.hw_fcs_strip ? "" : "not "));
1041
1042 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
1043                 config.hw_padding = !!device_attr_ex.rx_pad_end_addr_align;
1044 #endif
1045                 DRV_LOG(DEBUG,
1046                         "hardware Rx end alignment padding is %ssupported",
1047                         (config.hw_padding ? "" : "not "));
1048                 config.vf = vf;
1049                 config.tso = ((device_attr_ex.tso_caps.max_tso > 0) &&
1050                               (device_attr_ex.tso_caps.supported_qpts &
1051                               (1 << IBV_QPT_RAW_PACKET)));
1052                 if (config.tso)
1053                         config.tso_max_payload_sz =
1054                                         device_attr_ex.tso_caps.max_tso;
1055                 if (config.mps && !mps) {
1056                         DRV_LOG(ERR,
1057                                 "multi-packet send not supported on this device"
1058                                 " (" MLX5_TXQ_MPW_EN ")");
1059                         err = ENOTSUP;
1060                         goto port_error;
1061                 }
1062                 DRV_LOG(INFO, "%s MPS is %s",
1063                         config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "",
1064                         config.mps != MLX5_MPW_DISABLED ? "enabled" :
1065                         "disabled");
1066                 if (config.cqe_comp && !cqe_comp) {
1067                         DRV_LOG(WARNING, "Rx CQE compression isn't supported");
1068                         config.cqe_comp = 0;
1069                 }
1070                 config.mprq.enabled = config.mprq.enabled && mprq;
1071                 if (config.mprq.enabled) {
1072                         if (config.mprq.stride_num_n > mprq_max_stride_num_n ||
1073                             config.mprq.stride_num_n < mprq_min_stride_num_n) {
1074                                 config.mprq.stride_num_n =
1075                                         RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
1076                                                 mprq_min_stride_num_n);
1077                                 DRV_LOG(WARNING,
1078                                         "the number of strides"
1079                                         " for Multi-Packet RQ is out of range,"
1080                                         " setting default value (%u)",
1081                                         1 << config.mprq.stride_num_n);
1082                         }
1083                         config.mprq.min_stride_size_n = mprq_min_stride_size_n;
1084                         config.mprq.max_stride_size_n = mprq_max_stride_size_n;
1085                 }
1086                 eth_dev = rte_eth_dev_allocate(name);
1087                 if (eth_dev == NULL) {
1088                         DRV_LOG(ERR, "can not allocate rte ethdev");
1089                         err = ENOMEM;
1090                         goto port_error;
1091                 }
1092                 eth_dev->data->dev_private = priv;
1093                 priv->dev_data = eth_dev->data;
1094                 eth_dev->data->mac_addrs = priv->mac;
1095                 eth_dev->device = &pci_dev->device;
1096                 rte_eth_copy_pci_info(eth_dev, pci_dev);
1097                 eth_dev->device->driver = &mlx5_driver.driver;
1098                 err = mlx5_uar_init_primary(eth_dev);
1099                 if (err) {
1100                         err = rte_errno;
1101                         goto port_error;
1102                 }
1103                 /* Configure the first MAC address by default. */
1104                 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
1105                         DRV_LOG(ERR,
1106                                 "port %u cannot get MAC address, is mlx5_en"
1107                                 " loaded? (errno: %s)",
1108                                 eth_dev->data->port_id, strerror(errno));
1109                         err = ENODEV;
1110                         goto port_error;
1111                 }
1112                 DRV_LOG(INFO,
1113                         "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
1114                         eth_dev->data->port_id,
1115                         mac.addr_bytes[0], mac.addr_bytes[1],
1116                         mac.addr_bytes[2], mac.addr_bytes[3],
1117                         mac.addr_bytes[4], mac.addr_bytes[5]);
1118 #ifndef NDEBUG
1119                 {
1120                         char ifname[IF_NAMESIZE];
1121
1122                         if (mlx5_get_ifname(eth_dev, &ifname) == 0)
1123                                 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
1124                                         eth_dev->data->port_id, ifname);
1125                         else
1126                                 DRV_LOG(DEBUG, "port %u ifname is unknown",
1127                                         eth_dev->data->port_id);
1128                 }
1129 #endif
1130                 /* Get actual MTU if possible. */
1131                 err = mlx5_get_mtu(eth_dev, &priv->mtu);
1132                 if (err) {
1133                         err = rte_errno;
1134                         goto port_error;
1135                 }
1136                 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
1137                         priv->mtu);
1138                 /*
1139                  * Initialize burst functions to prevent crashes before link-up.
1140                  */
1141                 eth_dev->rx_pkt_burst = removed_rx_burst;
1142                 eth_dev->tx_pkt_burst = removed_tx_burst;
1143                 eth_dev->dev_ops = &mlx5_dev_ops;
1144                 /* Register MAC address. */
1145                 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
1146                 priv->nl_socket = -1;
1147                 priv->nl_sn = 0;
1148                 if (vf && config.vf_nl_en) {
1149                         priv->nl_socket = mlx5_nl_init(RTMGRP_LINK);
1150                         if (priv->nl_socket < 0)
1151                                 priv->nl_socket = -1;
1152                         mlx5_nl_mac_addr_sync(eth_dev);
1153                 }
1154                 TAILQ_INIT(&priv->flows);
1155                 TAILQ_INIT(&priv->ctrl_flows);
1156                 /* Hint libmlx5 to use PMD allocator for data plane resources */
1157                 struct mlx5dv_ctx_allocators alctr = {
1158                         .alloc = &mlx5_alloc_verbs_buf,
1159                         .free = &mlx5_free_verbs_buf,
1160                         .data = priv,
1161                 };
1162                 mlx5_glue->dv_set_context_attr(ctx,
1163                                                MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
1164                                                (void *)((uintptr_t)&alctr));
1165                 /* Bring Ethernet device up. */
1166                 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
1167                         eth_dev->data->port_id);
1168                 mlx5_set_link_up(eth_dev);
1169                 /*
1170                  * Even though the interrupt handler is not installed yet,
1171                  * interrupts will still trigger on the asyn_fd from
1172                  * Verbs context returned by ibv_open_device().
1173                  */
1174                 mlx5_link_update(eth_dev, 0);
1175                 /* Store device configuration on private structure. */
1176                 priv->config = config;
1177                 /* Create drop queue. */
1178                 err = mlx5_flow_create_drop_queue(eth_dev);
1179                 if (err) {
1180                         DRV_LOG(ERR, "port %u drop queue allocation failed: %s",
1181                                 eth_dev->data->port_id, strerror(rte_errno));
1182                         err = rte_errno;
1183                         goto port_error;
1184                 }
1185                 /* Supported Verbs flow priority number detection. */
1186                 if (verb_priorities == 0)
1187                         verb_priorities = mlx5_get_max_verbs_prio(eth_dev);
1188                 if (verb_priorities < MLX5_VERBS_FLOW_PRIO_8) {
1189                         DRV_LOG(ERR, "port %u wrong Verbs flow priorities: %u",
1190                                 eth_dev->data->port_id, verb_priorities);
1191                         goto port_error;
1192                 }
1193                 priv->config.max_verbs_prio = verb_priorities;
1194                 rte_eth_dev_probing_finish(eth_dev);
1195                 continue;
1196 port_error:
1197                 if (priv)
1198                         rte_free(priv);
1199                 if (pd)
1200                         claim_zero(mlx5_glue->dealloc_pd(pd));
1201                 if (ctx)
1202                         claim_zero(mlx5_glue->close_device(ctx));
1203                 if (eth_dev && rte_eal_process_type() == RTE_PROC_PRIMARY)
1204                         rte_eth_dev_release_port(eth_dev);
1205                 break;
1206         }
1207         /*
1208          * XXX if something went wrong in the loop above, there is a resource
1209          * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as
1210          * long as the dpdk does not provide a way to deallocate a ethdev and a
1211          * way to enumerate the registered ethdevs to free the previous ones.
1212          */
1213         /* no port found, complain */
1214         if (!mlx5_dev[idx].ports) {
1215                 rte_errno = ENODEV;
1216                 err = rte_errno;
1217         }
1218 error:
1219         if (attr_ctx)
1220                 claim_zero(mlx5_glue->close_device(attr_ctx));
1221         if (list)
1222                 mlx5_glue->free_device_list(list);
1223         if (err) {
1224                 rte_errno = err;
1225                 return -rte_errno;
1226         }
1227         return 0;
1228 }
1229
1230 static const struct rte_pci_id mlx5_pci_id_map[] = {
1231         {
1232                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1233                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1234         },
1235         {
1236                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1237                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1238         },
1239         {
1240                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1241                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1242         },
1243         {
1244                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1245                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1246         },
1247         {
1248                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1249                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1250         },
1251         {
1252                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1253                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1254         },
1255         {
1256                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1257                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1258         },
1259         {
1260                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1261                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1262         },
1263         {
1264                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1265                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
1266         },
1267         {
1268                 .vendor_id = 0
1269         }
1270 };
1271
1272 static struct rte_pci_driver mlx5_driver = {
1273         .driver = {
1274                 .name = MLX5_DRIVER_NAME
1275         },
1276         .id_table = mlx5_pci_id_map,
1277         .probe = mlx5_pci_probe,
1278         .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV,
1279 };
1280
1281 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1282
1283 /**
1284  * Suffix RTE_EAL_PMD_PATH with "-glue".
1285  *
1286  * This function performs a sanity check on RTE_EAL_PMD_PATH before
1287  * suffixing its last component.
1288  *
1289  * @param buf[out]
1290  *   Output buffer, should be large enough otherwise NULL is returned.
1291  * @param size
1292  *   Size of @p out.
1293  *
1294  * @return
1295  *   Pointer to @p buf or @p NULL in case suffix cannot be appended.
1296  */
1297 static char *
1298 mlx5_glue_path(char *buf, size_t size)
1299 {
1300         static const char *const bad[] = { "/", ".", "..", NULL };
1301         const char *path = RTE_EAL_PMD_PATH;
1302         size_t len = strlen(path);
1303         size_t off;
1304         int i;
1305
1306         while (len && path[len - 1] == '/')
1307                 --len;
1308         for (off = len; off && path[off - 1] != '/'; --off)
1309                 ;
1310         for (i = 0; bad[i]; ++i)
1311                 if (!strncmp(path + off, bad[i], (int)(len - off)))
1312                         goto error;
1313         i = snprintf(buf, size, "%.*s-glue", (int)len, path);
1314         if (i == -1 || (size_t)i >= size)
1315                 goto error;
1316         return buf;
1317 error:
1318         DRV_LOG(ERR,
1319                 "unable to append \"-glue\" to last component of"
1320                 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\"),"
1321                 " please re-configure DPDK");
1322         return NULL;
1323 }
1324
1325 /**
1326  * Initialization routine for run-time dependency on rdma-core.
1327  */
1328 static int
1329 mlx5_glue_init(void)
1330 {
1331         char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")];
1332         const char *path[] = {
1333                 /*
1334                  * A basic security check is necessary before trusting
1335                  * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH.
1336                  */
1337                 (geteuid() == getuid() && getegid() == getgid() ?
1338                  getenv("MLX5_GLUE_PATH") : NULL),
1339                 /*
1340                  * When RTE_EAL_PMD_PATH is set, use its glue-suffixed
1341                  * variant, otherwise let dlopen() look up libraries on its
1342                  * own.
1343                  */
1344                 (*RTE_EAL_PMD_PATH ?
1345                  mlx5_glue_path(glue_path, sizeof(glue_path)) : ""),
1346         };
1347         unsigned int i = 0;
1348         void *handle = NULL;
1349         void **sym;
1350         const char *dlmsg;
1351
1352         while (!handle && i != RTE_DIM(path)) {
1353                 const char *end;
1354                 size_t len;
1355                 int ret;
1356
1357                 if (!path[i]) {
1358                         ++i;
1359                         continue;
1360                 }
1361                 end = strpbrk(path[i], ":;");
1362                 if (!end)
1363                         end = path[i] + strlen(path[i]);
1364                 len = end - path[i];
1365                 ret = 0;
1366                 do {
1367                         char name[ret + 1];
1368
1369                         ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE,
1370                                        (int)len, path[i],
1371                                        (!len || *(end - 1) == '/') ? "" : "/");
1372                         if (ret == -1)
1373                                 break;
1374                         if (sizeof(name) != (size_t)ret + 1)
1375                                 continue;
1376                         DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"",
1377                                 name);
1378                         handle = dlopen(name, RTLD_LAZY);
1379                         break;
1380                 } while (1);
1381                 path[i] = end + 1;
1382                 if (!*end)
1383                         ++i;
1384         }
1385         if (!handle) {
1386                 rte_errno = EINVAL;
1387                 dlmsg = dlerror();
1388                 if (dlmsg)
1389                         DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg);
1390                 goto glue_error;
1391         }
1392         sym = dlsym(handle, "mlx5_glue");
1393         if (!sym || !*sym) {
1394                 rte_errno = EINVAL;
1395                 dlmsg = dlerror();
1396                 if (dlmsg)
1397                         DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg);
1398                 goto glue_error;
1399         }
1400         mlx5_glue = *sym;
1401         return 0;
1402 glue_error:
1403         if (handle)
1404                 dlclose(handle);
1405         DRV_LOG(WARNING,
1406                 "cannot initialize PMD due to missing run-time dependency on"
1407                 " rdma-core libraries (libibverbs, libmlx5)");
1408         return -rte_errno;
1409 }
1410
1411 #endif
1412
1413 /**
1414  * Driver initialization routine.
1415  */
1416 RTE_INIT(rte_mlx5_pmd_init);
1417 static void
1418 rte_mlx5_pmd_init(void)
1419 {
1420         /* Build the static tables for Verbs conversion. */
1421         mlx5_set_ptype_table();
1422         mlx5_set_cksum_table();
1423         mlx5_set_swp_types_table();
1424         /*
1425          * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
1426          * huge pages. Calling ibv_fork_init() during init allows
1427          * applications to use fork() safely for purposes other than
1428          * using this PMD, which is not supported in forked processes.
1429          */
1430         setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
1431         /* Match the size of Rx completion entry to the size of a cacheline. */
1432         if (RTE_CACHE_LINE_SIZE == 128)
1433                 setenv("MLX5_CQE_SIZE", "128", 0);
1434 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1435         if (mlx5_glue_init())
1436                 return;
1437         assert(mlx5_glue);
1438 #endif
1439 #ifndef NDEBUG
1440         /* Glue structure must not contain any NULL pointers. */
1441         {
1442                 unsigned int i;
1443
1444                 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i)
1445                         assert(((const void *const *)mlx5_glue)[i]);
1446         }
1447 #endif
1448         if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) {
1449                 DRV_LOG(ERR,
1450                         "rdma-core glue \"%s\" mismatch: \"%s\" is required",
1451                         mlx5_glue->version, MLX5_GLUE_VERSION);
1452                 return;
1453         }
1454         mlx5_glue->fork_init();
1455         rte_pci_register(&mlx5_driver);
1456         rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1457                                         mlx5_mr_mem_event_cb, NULL);
1458 }
1459
1460 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1461 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1462 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");
1463
1464 /** Initialize driver log type. */
1465 RTE_INIT(vdev_netvsc_init_log)
1466 {
1467         mlx5_logtype = rte_log_register("pmd.net.mlx5");
1468         if (mlx5_logtype >= 0)
1469                 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
1470 }