1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
16 #include <linux/netlink.h>
17 #include <linux/rtnetlink.h>
20 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
22 #pragma GCC diagnostic ignored "-Wpedantic"
24 #include <infiniband/verbs.h>
26 #pragma GCC diagnostic error "-Wpedantic"
29 #include <rte_malloc.h>
30 #include <rte_ethdev_driver.h>
31 #include <rte_ethdev_pci.h>
33 #include <rte_bus_pci.h>
34 #include <rte_common.h>
35 #include <rte_config.h>
36 #include <rte_eal_memconfig.h>
37 #include <rte_kvargs.h>
38 #include <rte_rwlock.h>
39 #include <rte_spinlock.h>
40 #include <rte_string_fns.h>
43 #include "mlx5_utils.h"
44 #include "mlx5_rxtx.h"
45 #include "mlx5_autoconf.h"
46 #include "mlx5_defs.h"
47 #include "mlx5_glue.h"
49 #include "mlx5_flow.h"
51 /* Device parameter to enable RX completion queue compression. */
52 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
54 /* Device parameter to enable Multi-Packet Rx queue. */
55 #define MLX5_RX_MPRQ_EN "mprq_en"
57 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
58 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
60 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
61 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
63 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
64 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
66 /* Device parameter to configure inline send. */
67 #define MLX5_TXQ_INLINE "txq_inline"
70 * Device parameter to configure the number of TX queues threshold for
71 * enabling inline send.
73 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
75 /* Device parameter to enable multi-packet send WQEs. */
76 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
78 /* Device parameter to include 2 dsegs in the title WQEBB. */
79 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
81 /* Device parameter to limit the size of inlining packet. */
82 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
84 /* Device parameter to enable hardware Tx vector. */
85 #define MLX5_TX_VEC_EN "tx_vec_en"
87 /* Device parameter to enable hardware Rx vector. */
88 #define MLX5_RX_VEC_EN "rx_vec_en"
90 /* Allow L3 VXLAN flow creation. */
91 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
93 /* Activate DV flow steering. */
94 #define MLX5_DV_FLOW_EN "dv_flow_en"
96 /* Activate Netlink support in VF mode. */
97 #define MLX5_VF_NL_EN "vf_nl_en"
99 /* Select port representors to instantiate. */
100 #define MLX5_REPRESENTOR "representor"
102 #ifndef HAVE_IBV_MLX5_MOD_MPW
103 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
104 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
107 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
108 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
111 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
113 /* Shared memory between primary and secondary processes. */
114 struct mlx5_shared_data *mlx5_shared_data;
116 /* Spinlock for mlx5_shared_data allocation. */
117 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
119 /** Driver-specific log messages type. */
123 * Prepare shared data between primary and secondary process.
126 mlx5_prepare_shared_data(void)
128 const struct rte_memzone *mz;
130 rte_spinlock_lock(&mlx5_shared_data_lock);
131 if (mlx5_shared_data == NULL) {
132 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
133 /* Allocate shared memory. */
134 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
135 sizeof(*mlx5_shared_data),
138 /* Lookup allocated shared memory. */
139 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
142 rte_panic("Cannot allocate mlx5 shared data\n");
143 mlx5_shared_data = mz->addr;
144 /* Initialize shared data. */
145 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
146 LIST_INIT(&mlx5_shared_data->mem_event_cb_list);
147 rte_rwlock_init(&mlx5_shared_data->mem_event_rwlock);
149 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
150 mlx5_mr_mem_event_cb, NULL);
152 rte_spinlock_unlock(&mlx5_shared_data_lock);
156 * Retrieve integer value from environment variable.
159 * Environment variable name.
162 * Integer value, 0 if the variable is not set.
165 mlx5_getenv_int(const char *name)
167 const char *val = getenv(name);
175 * Verbs callback to allocate a memory. This function should allocate the space
176 * according to the size provided residing inside a huge page.
177 * Please note that all allocation must respect the alignment from libmlx5
178 * (i.e. currently sysconf(_SC_PAGESIZE)).
181 * The size in bytes of the memory to allocate.
183 * A pointer to the callback data.
186 * Allocated buffer, NULL otherwise and rte_errno is set.
189 mlx5_alloc_verbs_buf(size_t size, void *data)
191 struct priv *priv = data;
193 size_t alignment = sysconf(_SC_PAGESIZE);
194 unsigned int socket = SOCKET_ID_ANY;
196 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
197 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
199 socket = ctrl->socket;
200 } else if (priv->verbs_alloc_ctx.type ==
201 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
202 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
204 socket = ctrl->socket;
206 assert(data != NULL);
207 ret = rte_malloc_socket(__func__, size, alignment, socket);
214 * Verbs callback to free a memory.
217 * A pointer to the memory to free.
219 * A pointer to the callback data.
222 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
224 assert(data != NULL);
229 * DPDK callback to close the device.
231 * Destroy all queues and objects, free memory.
234 * Pointer to Ethernet device structure.
237 mlx5_dev_close(struct rte_eth_dev *dev)
239 struct priv *priv = dev->data->dev_private;
243 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
245 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
246 /* In case mlx5_dev_stop() has not been called. */
247 mlx5_dev_interrupt_handler_uninstall(dev);
248 mlx5_traffic_disable(dev);
249 mlx5_flow_flush(dev, NULL);
250 /* Prevent crashes when queues are still in use. */
251 dev->rx_pkt_burst = removed_rx_burst;
252 dev->tx_pkt_burst = removed_tx_burst;
253 if (priv->rxqs != NULL) {
254 /* XXX race condition if mlx5_rx_burst() is still running. */
256 for (i = 0; (i != priv->rxqs_n); ++i)
257 mlx5_rxq_release(dev, i);
261 if (priv->txqs != NULL) {
262 /* XXX race condition if mlx5_tx_burst() is still running. */
264 for (i = 0; (i != priv->txqs_n); ++i)
265 mlx5_txq_release(dev, i);
269 mlx5_mprq_free_mp(dev);
270 mlx5_mr_release(dev);
271 if (priv->pd != NULL) {
272 assert(priv->ctx != NULL);
273 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
274 claim_zero(mlx5_glue->close_device(priv->ctx));
276 assert(priv->ctx == NULL);
277 if (priv->rss_conf.rss_key != NULL)
278 rte_free(priv->rss_conf.rss_key);
279 if (priv->reta_idx != NULL)
280 rte_free(priv->reta_idx);
281 if (priv->primary_socket)
282 mlx5_socket_uninit(dev);
284 mlx5_nl_mac_addr_flush(dev);
285 if (priv->nl_socket_route >= 0)
286 close(priv->nl_socket_route);
287 if (priv->nl_socket_rdma >= 0)
288 close(priv->nl_socket_rdma);
289 if (priv->tcf_context)
290 mlx5_flow_tcf_context_destroy(priv->tcf_context);
291 ret = mlx5_hrxq_ibv_verify(dev);
293 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
295 ret = mlx5_ind_table_ibv_verify(dev);
297 DRV_LOG(WARNING, "port %u some indirection table still remain",
299 ret = mlx5_rxq_ibv_verify(dev);
301 DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain",
303 ret = mlx5_rxq_verify(dev);
305 DRV_LOG(WARNING, "port %u some Rx queues still remain",
307 ret = mlx5_txq_ibv_verify(dev);
309 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
311 ret = mlx5_txq_verify(dev);
313 DRV_LOG(WARNING, "port %u some Tx queues still remain",
315 ret = mlx5_flow_verify(dev);
317 DRV_LOG(WARNING, "port %u some flows still remain",
319 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
321 unsigned int i = mlx5_dev_to_port_id(dev->device, NULL, 0);
324 i = RTE_MIN(mlx5_dev_to_port_id(dev->device, port_id, i), i);
327 rte_eth_devices[port_id[i]].data->dev_private;
330 opriv->domain_id != priv->domain_id ||
331 &rte_eth_devices[port_id[i]] == dev)
336 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
338 memset(priv, 0, sizeof(*priv));
339 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
342 const struct eth_dev_ops mlx5_dev_ops = {
343 .dev_configure = mlx5_dev_configure,
344 .dev_start = mlx5_dev_start,
345 .dev_stop = mlx5_dev_stop,
346 .dev_set_link_down = mlx5_set_link_down,
347 .dev_set_link_up = mlx5_set_link_up,
348 .dev_close = mlx5_dev_close,
349 .promiscuous_enable = mlx5_promiscuous_enable,
350 .promiscuous_disable = mlx5_promiscuous_disable,
351 .allmulticast_enable = mlx5_allmulticast_enable,
352 .allmulticast_disable = mlx5_allmulticast_disable,
353 .link_update = mlx5_link_update,
354 .stats_get = mlx5_stats_get,
355 .stats_reset = mlx5_stats_reset,
356 .xstats_get = mlx5_xstats_get,
357 .xstats_reset = mlx5_xstats_reset,
358 .xstats_get_names = mlx5_xstats_get_names,
359 .dev_infos_get = mlx5_dev_infos_get,
360 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
361 .vlan_filter_set = mlx5_vlan_filter_set,
362 .rx_queue_setup = mlx5_rx_queue_setup,
363 .tx_queue_setup = mlx5_tx_queue_setup,
364 .rx_queue_release = mlx5_rx_queue_release,
365 .tx_queue_release = mlx5_tx_queue_release,
366 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
367 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
368 .mac_addr_remove = mlx5_mac_addr_remove,
369 .mac_addr_add = mlx5_mac_addr_add,
370 .mac_addr_set = mlx5_mac_addr_set,
371 .set_mc_addr_list = mlx5_set_mc_addr_list,
372 .mtu_set = mlx5_dev_set_mtu,
373 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
374 .vlan_offload_set = mlx5_vlan_offload_set,
375 .reta_update = mlx5_dev_rss_reta_update,
376 .reta_query = mlx5_dev_rss_reta_query,
377 .rss_hash_update = mlx5_rss_hash_update,
378 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
379 .filter_ctrl = mlx5_dev_filter_ctrl,
380 .rx_descriptor_status = mlx5_rx_descriptor_status,
381 .tx_descriptor_status = mlx5_tx_descriptor_status,
382 .rx_queue_intr_enable = mlx5_rx_intr_enable,
383 .rx_queue_intr_disable = mlx5_rx_intr_disable,
384 .is_removed = mlx5_is_removed,
387 static const struct eth_dev_ops mlx5_dev_sec_ops = {
388 .stats_get = mlx5_stats_get,
389 .stats_reset = mlx5_stats_reset,
390 .xstats_get = mlx5_xstats_get,
391 .xstats_reset = mlx5_xstats_reset,
392 .xstats_get_names = mlx5_xstats_get_names,
393 .dev_infos_get = mlx5_dev_infos_get,
394 .rx_descriptor_status = mlx5_rx_descriptor_status,
395 .tx_descriptor_status = mlx5_tx_descriptor_status,
398 /* Available operators in flow isolated mode. */
399 const struct eth_dev_ops mlx5_dev_ops_isolate = {
400 .dev_configure = mlx5_dev_configure,
401 .dev_start = mlx5_dev_start,
402 .dev_stop = mlx5_dev_stop,
403 .dev_set_link_down = mlx5_set_link_down,
404 .dev_set_link_up = mlx5_set_link_up,
405 .dev_close = mlx5_dev_close,
406 .promiscuous_enable = mlx5_promiscuous_enable,
407 .promiscuous_disable = mlx5_promiscuous_disable,
408 .allmulticast_enable = mlx5_allmulticast_enable,
409 .allmulticast_disable = mlx5_allmulticast_disable,
410 .link_update = mlx5_link_update,
411 .stats_get = mlx5_stats_get,
412 .stats_reset = mlx5_stats_reset,
413 .xstats_get = mlx5_xstats_get,
414 .xstats_reset = mlx5_xstats_reset,
415 .xstats_get_names = mlx5_xstats_get_names,
416 .dev_infos_get = mlx5_dev_infos_get,
417 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
418 .vlan_filter_set = mlx5_vlan_filter_set,
419 .rx_queue_setup = mlx5_rx_queue_setup,
420 .tx_queue_setup = mlx5_tx_queue_setup,
421 .rx_queue_release = mlx5_rx_queue_release,
422 .tx_queue_release = mlx5_tx_queue_release,
423 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
424 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
425 .mac_addr_remove = mlx5_mac_addr_remove,
426 .mac_addr_add = mlx5_mac_addr_add,
427 .mac_addr_set = mlx5_mac_addr_set,
428 .set_mc_addr_list = mlx5_set_mc_addr_list,
429 .mtu_set = mlx5_dev_set_mtu,
430 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
431 .vlan_offload_set = mlx5_vlan_offload_set,
432 .filter_ctrl = mlx5_dev_filter_ctrl,
433 .rx_descriptor_status = mlx5_rx_descriptor_status,
434 .tx_descriptor_status = mlx5_tx_descriptor_status,
435 .rx_queue_intr_enable = mlx5_rx_intr_enable,
436 .rx_queue_intr_disable = mlx5_rx_intr_disable,
437 .is_removed = mlx5_is_removed,
441 * Verify and store value for device argument.
444 * Key argument to verify.
446 * Value associated with key.
451 * 0 on success, a negative errno value otherwise and rte_errno is set.
454 mlx5_args_check(const char *key, const char *val, void *opaque)
456 struct mlx5_dev_config *config = opaque;
459 /* No-op, port representors are processed in mlx5_dev_spawn(). */
460 if (!strcmp(MLX5_REPRESENTOR, key))
463 tmp = strtoul(val, NULL, 0);
466 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
469 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
470 config->cqe_comp = !!tmp;
471 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
472 config->mprq.enabled = !!tmp;
473 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
474 config->mprq.stride_num_n = tmp;
475 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
476 config->mprq.max_memcpy_len = tmp;
477 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
478 config->mprq.min_rxqs_num = tmp;
479 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
480 config->txq_inline = tmp;
481 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
482 config->txqs_inline = tmp;
483 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
485 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
486 config->mpw_hdr_dseg = !!tmp;
487 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
488 config->inline_max_packet_sz = tmp;
489 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
490 config->tx_vec_en = !!tmp;
491 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
492 config->rx_vec_en = !!tmp;
493 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
494 config->l3_vxlan_en = !!tmp;
495 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
496 config->vf_nl_en = !!tmp;
497 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
498 config->dv_flow_en = !!tmp;
500 DRV_LOG(WARNING, "%s: unknown parameter", key);
508 * Parse device parameters.
511 * Pointer to device configuration structure.
513 * Device arguments structure.
516 * 0 on success, a negative errno value otherwise and rte_errno is set.
519 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
521 const char **params = (const char *[]){
522 MLX5_RXQ_CQE_COMP_EN,
524 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
525 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
528 MLX5_TXQS_MIN_INLINE,
530 MLX5_TXQ_MPW_HDR_DSEG_EN,
531 MLX5_TXQ_MAX_INLINE_LEN,
540 struct rte_kvargs *kvlist;
546 /* Following UGLY cast is done to pass checkpatch. */
547 kvlist = rte_kvargs_parse(devargs->args, params);
550 /* Process parameters. */
551 for (i = 0; (params[i] != NULL); ++i) {
552 if (rte_kvargs_count(kvlist, params[i])) {
553 ret = rte_kvargs_process(kvlist, params[i],
554 mlx5_args_check, config);
557 rte_kvargs_free(kvlist);
562 rte_kvargs_free(kvlist);
566 static struct rte_pci_driver mlx5_driver;
569 * Reserved UAR address space for TXQ UAR(hw doorbell) mapping, process
570 * local resource used by both primary and secondary to avoid duplicate
572 * The space has to be available on both primary and secondary process,
573 * TXQ UAR maps to this area using fixed mmap w/o double check.
575 static void *uar_base;
578 find_lower_va_bound(const struct rte_memseg_list *msl,
579 const struct rte_memseg *ms, void *arg)
588 *addr = RTE_MIN(*addr, ms->addr);
594 * Reserve UAR address space for primary process.
597 * Pointer to Ethernet device.
600 * 0 on success, a negative errno value otherwise and rte_errno is set.
603 mlx5_uar_init_primary(struct rte_eth_dev *dev)
605 struct priv *priv = dev->data->dev_private;
606 void *addr = (void *)0;
608 if (uar_base) { /* UAR address space mapped. */
609 priv->uar_base = uar_base;
612 /* find out lower bound of hugepage segments */
613 rte_memseg_walk(find_lower_va_bound, &addr);
615 /* keep distance to hugepages to minimize potential conflicts. */
616 addr = RTE_PTR_SUB(addr, (uintptr_t)(MLX5_UAR_OFFSET + MLX5_UAR_SIZE));
617 /* anonymous mmap, no real memory consumption. */
618 addr = mmap(addr, MLX5_UAR_SIZE,
619 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
620 if (addr == MAP_FAILED) {
622 "port %u failed to reserve UAR address space, please"
623 " adjust MLX5_UAR_SIZE or try --base-virtaddr",
628 /* Accept either same addr or a new addr returned from mmap if target
631 DRV_LOG(INFO, "port %u reserved UAR address space: %p",
632 dev->data->port_id, addr);
633 priv->uar_base = addr; /* for primary and secondary UAR re-mmap. */
634 uar_base = addr; /* process local, don't reserve again. */
639 * Reserve UAR address space for secondary process, align with
643 * Pointer to Ethernet device.
646 * 0 on success, a negative errno value otherwise and rte_errno is set.
649 mlx5_uar_init_secondary(struct rte_eth_dev *dev)
651 struct priv *priv = dev->data->dev_private;
654 assert(priv->uar_base);
655 if (uar_base) { /* already reserved. */
656 assert(uar_base == priv->uar_base);
659 /* anonymous mmap, no real memory consumption. */
660 addr = mmap(priv->uar_base, MLX5_UAR_SIZE,
661 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
662 if (addr == MAP_FAILED) {
663 DRV_LOG(ERR, "port %u UAR mmap failed: %p size: %llu",
664 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
668 if (priv->uar_base != addr) {
670 "port %u UAR address %p size %llu occupied, please"
671 " adjust MLX5_UAR_OFFSET or try EAL parameter"
673 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
677 uar_base = addr; /* process local, don't reserve again */
678 DRV_LOG(INFO, "port %u reserved UAR address space: %p",
679 dev->data->port_id, addr);
684 * Spawn an Ethernet device from Verbs information.
687 * Backing DPDK device.
691 * If nonzero, enable VF-specific features.
692 * @param[in] switch_info
693 * Switch properties of Ethernet device.
696 * A valid Ethernet device object on success, NULL otherwise and rte_errno
697 * is set. The following errors are defined:
699 * EBUSY: device is not supposed to be spawned.
700 * EEXIST: device is already spawned
702 static struct rte_eth_dev *
703 mlx5_dev_spawn(struct rte_device *dpdk_dev,
704 struct ibv_device *ibv_dev,
706 const struct mlx5_switch_info *switch_info)
708 struct ibv_context *ctx;
709 struct ibv_device_attr_ex attr;
710 struct ibv_port_attr port_attr;
711 struct ibv_pd *pd = NULL;
712 struct mlx5dv_context dv_attr = { .comp_mask = 0 };
713 struct mlx5_dev_config config = {
715 .mps = MLX5_ARG_UNSET,
719 .txq_inline = MLX5_ARG_UNSET,
720 .txqs_inline = MLX5_ARG_UNSET,
721 .inline_max_packet_sz = MLX5_ARG_UNSET,
725 .stride_num_n = MLX5_MPRQ_STRIDE_NUM_N,
726 .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
727 .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
730 struct rte_eth_dev *eth_dev = NULL;
731 struct priv *priv = NULL;
734 unsigned int cqe_comp;
735 unsigned int tunnel_en = 0;
736 unsigned int mpls_en = 0;
737 unsigned int swp = 0;
738 unsigned int mprq = 0;
739 unsigned int mprq_min_stride_size_n = 0;
740 unsigned int mprq_max_stride_size_n = 0;
741 unsigned int mprq_min_stride_num_n = 0;
742 unsigned int mprq_max_stride_num_n = 0;
743 struct ether_addr mac;
744 char name[RTE_ETH_NAME_MAX_LEN];
745 int own_domain_id = 0;
749 /* Determine if this port representor is supposed to be spawned. */
750 if (switch_info->representor && dpdk_dev->devargs) {
751 struct rte_eth_devargs eth_da;
753 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, ð_da);
756 DRV_LOG(ERR, "failed to process device arguments: %s",
757 strerror(rte_errno));
760 for (i = 0; i < eth_da.nb_representor_ports; ++i)
761 if (eth_da.representor_ports[i] ==
762 (uint16_t)switch_info->port_name)
764 if (i == eth_da.nb_representor_ports) {
769 /* Build device name. */
770 if (!switch_info->representor)
771 rte_strlcpy(name, dpdk_dev->name, sizeof(name));
773 snprintf(name, sizeof(name), "%s_representor_%u",
774 dpdk_dev->name, switch_info->port_name);
775 /* check if the device is already spawned */
776 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
780 /* Prepare shared data between primary and secondary process. */
781 mlx5_prepare_shared_data();
783 ctx = mlx5_glue->open_device(ibv_dev);
785 rte_errno = errno ? errno : ENODEV;
788 #ifdef HAVE_IBV_MLX5_MOD_SWP
789 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
792 * Multi-packet send is supported by ConnectX-4 Lx PF as well
793 * as all ConnectX-5 devices.
795 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
796 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
798 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
799 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
801 mlx5_glue->dv_query_device(ctx, &dv_attr);
802 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
803 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
804 DRV_LOG(DEBUG, "enhanced MPW is supported");
805 mps = MLX5_MPW_ENHANCED;
807 DRV_LOG(DEBUG, "MPW is supported");
811 DRV_LOG(DEBUG, "MPW isn't supported");
812 mps = MLX5_MPW_DISABLED;
814 #ifdef HAVE_IBV_MLX5_MOD_SWP
815 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
816 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
817 DRV_LOG(DEBUG, "SWP support: %u", swp);
820 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
821 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
822 struct mlx5dv_striding_rq_caps mprq_caps =
823 dv_attr.striding_rq_caps;
825 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
826 mprq_caps.min_single_stride_log_num_of_bytes);
827 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
828 mprq_caps.max_single_stride_log_num_of_bytes);
829 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
830 mprq_caps.min_single_wqe_log_num_of_strides);
831 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
832 mprq_caps.max_single_wqe_log_num_of_strides);
833 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
834 mprq_caps.supported_qpts);
835 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
837 mprq_min_stride_size_n =
838 mprq_caps.min_single_stride_log_num_of_bytes;
839 mprq_max_stride_size_n =
840 mprq_caps.max_single_stride_log_num_of_bytes;
841 mprq_min_stride_num_n =
842 mprq_caps.min_single_wqe_log_num_of_strides;
843 mprq_max_stride_num_n =
844 mprq_caps.max_single_wqe_log_num_of_strides;
845 config.mprq.stride_num_n = RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
846 mprq_min_stride_num_n);
849 if (RTE_CACHE_LINE_SIZE == 128 &&
850 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
854 config.cqe_comp = cqe_comp;
855 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
856 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
857 tunnel_en = ((dv_attr.tunnel_offloads_caps &
858 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
859 (dv_attr.tunnel_offloads_caps &
860 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE));
862 DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
863 tunnel_en ? "" : "not ");
866 "tunnel offloading disabled due to old OFED/rdma-core version");
868 config.tunnel_en = tunnel_en;
869 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
870 mpls_en = ((dv_attr.tunnel_offloads_caps &
871 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
872 (dv_attr.tunnel_offloads_caps &
873 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
874 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
875 mpls_en ? "" : "not ");
877 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
878 " old OFED/rdma-core version or firmware configuration");
880 config.mpls_en = mpls_en;
881 err = mlx5_glue->query_device_ex(ctx, NULL, &attr);
883 DEBUG("ibv_query_device_ex() failed");
886 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
887 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
888 eth_dev = rte_eth_dev_attach_secondary(name);
889 if (eth_dev == NULL) {
890 DRV_LOG(ERR, "can not attach rte ethdev");
895 eth_dev->device = dpdk_dev;
896 eth_dev->dev_ops = &mlx5_dev_sec_ops;
897 err = mlx5_uar_init_secondary(eth_dev);
902 /* Receive command fd from primary process */
903 err = mlx5_socket_connect(eth_dev);
908 /* Remap UAR for Tx queues. */
909 err = mlx5_tx_uar_remap(eth_dev, err);
915 * Ethdev pointer is still required as input since
916 * the primary device is not accessible from the
919 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev);
920 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev);
921 claim_zero(mlx5_glue->close_device(ctx));
924 /* Check port status. */
925 err = mlx5_glue->query_port(ctx, 1, &port_attr);
927 DRV_LOG(ERR, "port query failed: %s", strerror(err));
930 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
931 DRV_LOG(ERR, "port is not configured in Ethernet mode");
935 if (port_attr.state != IBV_PORT_ACTIVE)
936 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)",
937 mlx5_glue->port_state_str(port_attr.state),
939 /* Allocate protection domain. */
940 pd = mlx5_glue->alloc_pd(ctx);
942 DRV_LOG(ERR, "PD allocation failure");
946 priv = rte_zmalloc("ethdev private structure",
948 RTE_CACHE_LINE_SIZE);
950 DRV_LOG(ERR, "priv allocation failure");
955 strncpy(priv->ibdev_name, priv->ctx->device->name,
956 sizeof(priv->ibdev_name));
957 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path,
958 sizeof(priv->ibdev_path));
959 priv->device_attr = attr;
961 priv->mtu = ETHER_MTU;
963 /* Initialize UAR access locks for 32bit implementations. */
964 rte_spinlock_init(&priv->uar_lock_cq);
965 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
966 rte_spinlock_init(&priv->uar_lock[i]);
968 /* Some internal functions rely on Netlink sockets, open them now. */
969 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA);
970 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE);
972 priv->representor = !!switch_info->representor;
973 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
974 priv->representor_id =
975 switch_info->representor ? switch_info->port_name : -1;
977 * Look for sibling devices in order to reuse their switch domain
978 * if any, otherwise allocate one.
980 i = mlx5_dev_to_port_id(dpdk_dev, NULL, 0);
984 i = RTE_MIN(mlx5_dev_to_port_id(dpdk_dev, port_id, i), i);
986 const struct priv *opriv =
987 rte_eth_devices[port_id[i]].data->dev_private;
991 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
993 priv->domain_id = opriv->domain_id;
997 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
998 err = rte_eth_switch_domain_alloc(&priv->domain_id);
1001 DRV_LOG(ERR, "unable to allocate switch domain: %s",
1002 strerror(rte_errno));
1007 err = mlx5_args(&config, dpdk_dev->devargs);
1010 DRV_LOG(ERR, "failed to process device arguments: %s",
1011 strerror(rte_errno));
1014 config.hw_csum = !!(attr.device_cap_flags_ex & IBV_DEVICE_RAW_IP_CSUM);
1015 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
1016 (config.hw_csum ? "" : "not "));
1017 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \
1018 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
1019 DRV_LOG(DEBUG, "counters are not supported");
1021 #ifndef HAVE_IBV_FLOW_DV_SUPPORT
1022 if (config.dv_flow_en) {
1023 DRV_LOG(WARNING, "DV flow is not supported");
1024 config.dv_flow_en = 0;
1027 config.ind_table_max_size =
1028 attr.rss_caps.max_rwq_indirection_table_size;
1030 * Remove this check once DPDK supports larger/variable
1031 * indirection tables.
1033 if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
1034 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
1035 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
1036 config.ind_table_max_size);
1037 config.hw_vlan_strip = !!(attr.raw_packet_caps &
1038 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
1039 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
1040 (config.hw_vlan_strip ? "" : "not "));
1041 config.hw_fcs_strip = !!(attr.raw_packet_caps &
1042 IBV_RAW_PACKET_CAP_SCATTER_FCS);
1043 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
1044 (config.hw_fcs_strip ? "" : "not "));
1045 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
1046 config.hw_padding = !!attr.rx_pad_end_addr_align;
1048 DRV_LOG(DEBUG, "hardware Rx end alignment padding is %ssupported",
1049 (config.hw_padding ? "" : "not "));
1050 config.tso = (attr.tso_caps.max_tso > 0 &&
1051 (attr.tso_caps.supported_qpts &
1052 (1 << IBV_QPT_RAW_PACKET)));
1054 config.tso_max_payload_sz = attr.tso_caps.max_tso;
1056 * MPW is disabled by default, while the Enhanced MPW is enabled
1059 if (config.mps == MLX5_ARG_UNSET)
1060 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED :
1063 config.mps = config.mps ? mps : MLX5_MPW_DISABLED;
1064 DRV_LOG(INFO, "%sMPS is %s",
1065 config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "",
1066 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
1067 if (config.cqe_comp && !cqe_comp) {
1068 DRV_LOG(WARNING, "Rx CQE compression isn't supported");
1069 config.cqe_comp = 0;
1071 if (config.mprq.enabled && mprq) {
1072 if (config.mprq.stride_num_n > mprq_max_stride_num_n ||
1073 config.mprq.stride_num_n < mprq_min_stride_num_n) {
1074 config.mprq.stride_num_n =
1075 RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
1076 mprq_min_stride_num_n);
1078 "the number of strides"
1079 " for Multi-Packet RQ is out of range,"
1080 " setting default value (%u)",
1081 1 << config.mprq.stride_num_n);
1083 config.mprq.min_stride_size_n = mprq_min_stride_size_n;
1084 config.mprq.max_stride_size_n = mprq_max_stride_size_n;
1085 } else if (config.mprq.enabled && !mprq) {
1086 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
1087 config.mprq.enabled = 0;
1089 eth_dev = rte_eth_dev_allocate(name);
1090 if (eth_dev == NULL) {
1091 DRV_LOG(ERR, "can not allocate rte ethdev");
1095 if (priv->representor) {
1096 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
1097 eth_dev->data->representor_id = priv->representor_id;
1099 eth_dev->data->dev_private = priv;
1100 priv->dev_data = eth_dev->data;
1101 eth_dev->data->mac_addrs = priv->mac;
1102 eth_dev->device = dpdk_dev;
1103 err = mlx5_uar_init_primary(eth_dev);
1108 /* Configure the first MAC address by default. */
1109 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
1111 "port %u cannot get MAC address, is mlx5_en"
1112 " loaded? (errno: %s)",
1113 eth_dev->data->port_id, strerror(rte_errno));
1118 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
1119 eth_dev->data->port_id,
1120 mac.addr_bytes[0], mac.addr_bytes[1],
1121 mac.addr_bytes[2], mac.addr_bytes[3],
1122 mac.addr_bytes[4], mac.addr_bytes[5]);
1125 char ifname[IF_NAMESIZE];
1127 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
1128 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
1129 eth_dev->data->port_id, ifname);
1131 DRV_LOG(DEBUG, "port %u ifname is unknown",
1132 eth_dev->data->port_id);
1135 /* Get actual MTU if possible. */
1136 err = mlx5_get_mtu(eth_dev, &priv->mtu);
1141 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
1143 /* Initialize burst functions to prevent crashes before link-up. */
1144 eth_dev->rx_pkt_burst = removed_rx_burst;
1145 eth_dev->tx_pkt_burst = removed_tx_burst;
1146 eth_dev->dev_ops = &mlx5_dev_ops;
1147 /* Register MAC address. */
1148 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
1149 if (vf && config.vf_nl_en)
1150 mlx5_nl_mac_addr_sync(eth_dev);
1151 priv->tcf_context = mlx5_flow_tcf_context_create();
1152 if (!priv->tcf_context) {
1155 "flow rules relying on switch offloads will not be"
1156 " supported: cannot open libmnl socket: %s",
1157 strerror(rte_errno));
1159 struct rte_flow_error error;
1160 unsigned int ifindex = mlx5_ifindex(eth_dev);
1165 "cannot retrieve network interface index";
1167 err = mlx5_flow_tcf_init(priv->tcf_context,
1172 "flow rules relying on switch offloads will"
1173 " not be supported: %s: %s",
1174 error.message, strerror(rte_errno));
1175 mlx5_flow_tcf_context_destroy(priv->tcf_context);
1176 priv->tcf_context = NULL;
1179 TAILQ_INIT(&priv->flows);
1180 TAILQ_INIT(&priv->ctrl_flows);
1181 /* Hint libmlx5 to use PMD allocator for data plane resources */
1182 struct mlx5dv_ctx_allocators alctr = {
1183 .alloc = &mlx5_alloc_verbs_buf,
1184 .free = &mlx5_free_verbs_buf,
1187 mlx5_glue->dv_set_context_attr(ctx, MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
1188 (void *)((uintptr_t)&alctr));
1189 /* Bring Ethernet device up. */
1190 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
1191 eth_dev->data->port_id);
1192 mlx5_set_link_up(eth_dev);
1194 * Even though the interrupt handler is not installed yet,
1195 * interrupts will still trigger on the asyn_fd from
1196 * Verbs context returned by ibv_open_device().
1198 mlx5_link_update(eth_dev, 0);
1199 /* Store device configuration on private structure. */
1200 priv->config = config;
1201 /* Supported Verbs flow priority number detection. */
1202 err = mlx5_flow_discover_priorities(eth_dev);
1205 priv->config.flow_prio = err;
1207 * Once the device is added to the list of memory event
1208 * callback, its global MR cache table cannot be expanded
1209 * on the fly because of deadlock. If it overflows, lookup
1210 * should be done by searching MR list linearly, which is slow.
1212 err = mlx5_mr_btree_init(&priv->mr.cache,
1213 MLX5_MR_BTREE_CACHE_N * 2,
1214 eth_dev->device->numa_node);
1219 /* Add device to memory callback list. */
1220 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1221 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1222 priv, mem_event_cb);
1223 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1227 if (priv->nl_socket_route >= 0)
1228 close(priv->nl_socket_route);
1229 if (priv->nl_socket_rdma >= 0)
1230 close(priv->nl_socket_rdma);
1231 if (priv->tcf_context)
1232 mlx5_flow_tcf_context_destroy(priv->tcf_context);
1234 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1236 if (eth_dev != NULL)
1237 eth_dev->data->dev_private = NULL;
1240 claim_zero(mlx5_glue->dealloc_pd(pd));
1241 if (eth_dev != NULL) {
1242 /* mac_addrs must not be freed alone because part of dev_private */
1243 eth_dev->data->mac_addrs = NULL;
1244 rte_eth_dev_release_port(eth_dev);
1247 claim_zero(mlx5_glue->close_device(ctx));
1253 /** Data associated with devices to spawn. */
1254 struct mlx5_dev_spawn_data {
1255 unsigned int ifindex; /**< Network interface index. */
1256 struct mlx5_switch_info info; /**< Switch information. */
1257 struct ibv_device *ibv_dev; /**< Associated IB device. */
1258 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
1262 * Comparison callback to sort device data.
1264 * This is meant to be used with qsort().
1267 * Pointer to pointer to first data object.
1269 * Pointer to pointer to second data object.
1272 * 0 if both objects are equal, less than 0 if the first argument is less
1273 * than the second, greater than 0 otherwise.
1276 mlx5_dev_spawn_data_cmp(const void *a, const void *b)
1278 const struct mlx5_switch_info *si_a =
1279 &((const struct mlx5_dev_spawn_data *)a)->info;
1280 const struct mlx5_switch_info *si_b =
1281 &((const struct mlx5_dev_spawn_data *)b)->info;
1284 /* Master device first. */
1285 ret = si_b->master - si_a->master;
1288 /* Then representor devices. */
1289 ret = si_b->representor - si_a->representor;
1292 /* Unidentified devices come last in no specific order. */
1293 if (!si_a->representor)
1295 /* Order representors by name. */
1296 return si_a->port_name - si_b->port_name;
1300 * DPDK callback to register a PCI device.
1302 * This function spawns Ethernet devices out of a given PCI device.
1304 * @param[in] pci_drv
1305 * PCI driver structure (mlx5_driver).
1306 * @param[in] pci_dev
1307 * PCI device information.
1310 * 0 on success, a negative errno value otherwise and rte_errno is set.
1313 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1314 struct rte_pci_device *pci_dev)
1316 struct ibv_device **ibv_list;
1321 assert(pci_drv == &mlx5_driver);
1323 ibv_list = mlx5_glue->get_device_list(&ret);
1325 rte_errno = errno ? errno : ENOSYS;
1326 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?");
1330 struct ibv_device *ibv_match[ret + 1];
1333 struct rte_pci_addr pci_addr;
1335 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name);
1336 if (mlx5_ibv_device_to_pci_addr(ibv_list[ret], &pci_addr))
1338 if (pci_dev->addr.domain != pci_addr.domain ||
1339 pci_dev->addr.bus != pci_addr.bus ||
1340 pci_dev->addr.devid != pci_addr.devid ||
1341 pci_dev->addr.function != pci_addr.function)
1343 DRV_LOG(INFO, "PCI information matches for device \"%s\"",
1344 ibv_list[ret]->name);
1345 ibv_match[n++] = ibv_list[ret];
1347 ibv_match[n] = NULL;
1349 struct mlx5_dev_spawn_data list[n];
1350 int nl_route = n ? mlx5_nl_init(NETLINK_ROUTE) : -1;
1351 int nl_rdma = n ? mlx5_nl_init(NETLINK_RDMA) : -1;
1356 * The existence of several matching entries (n > 1) means port
1357 * representors have been instantiated. No existing Verbs call nor
1358 * /sys entries can tell them apart, this can only be done through
1359 * Netlink calls assuming kernel drivers are recent enough to
1362 * In the event of identification failure through Netlink, try again
1363 * through sysfs, then either:
1365 * 1. No device matches (n == 0), complain and bail out.
1366 * 2. A single IB device matches (n == 1) and is not a representor,
1367 * assume no switch support.
1368 * 3. Otherwise no safe assumptions can be made; complain louder and
1371 for (i = 0; i != n; ++i) {
1372 list[i].ibv_dev = ibv_match[i];
1373 list[i].eth_dev = NULL;
1375 list[i].ifindex = 0;
1377 list[i].ifindex = mlx5_nl_ifindex
1378 (nl_rdma, list[i].ibv_dev->name);
1381 mlx5_nl_switch_info(nl_route, list[i].ifindex,
1383 ((!list[i].info.representor && !list[i].info.master) &&
1384 mlx5_sysfs_switch_info(list[i].ifindex, &list[i].info))) {
1385 list[i].ifindex = 0;
1386 memset(&list[i].info, 0, sizeof(list[i].info));
1394 /* Count unidentified devices. */
1395 for (u = 0, i = 0; i != n; ++i)
1396 if (!list[i].info.master && !list[i].info.representor)
1399 if (n == 1 && u == 1) {
1401 DRV_LOG(INFO, "no switch support detected");
1405 "unable to tell which of the matching devices"
1406 " is the master (lack of kernel support?)");
1411 * Sort list to probe devices in natural order for users convenience
1412 * (i.e. master first, then representors from lowest to highest ID).
1415 qsort(list, n, sizeof(*list), mlx5_dev_spawn_data_cmp);
1416 switch (pci_dev->id.device_id) {
1417 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1418 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1419 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1420 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1426 for (i = 0; i != n; ++i) {
1429 list[i].eth_dev = mlx5_dev_spawn
1430 (&pci_dev->device, list[i].ibv_dev, vf, &list[i].info);
1431 if (!list[i].eth_dev) {
1432 if (rte_errno != EBUSY && rte_errno != EEXIST)
1434 /* Device is disabled or already spawned. Ignore it. */
1437 restore = list[i].eth_dev->data->dev_flags;
1438 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev);
1439 /* Restore non-PCI flags cleared by the above call. */
1440 list[i].eth_dev->data->dev_flags |= restore;
1441 rte_eth_dev_probing_finish(list[i].eth_dev);
1443 mlx5_glue->free_device_list(ibv_list);
1446 "no Verbs device matches PCI device " PCI_PRI_FMT ","
1447 " are kernel drivers loaded?",
1448 pci_dev->addr.domain, pci_dev->addr.bus,
1449 pci_dev->addr.devid, pci_dev->addr.function);
1452 } else if (i != n) {
1454 "probe of PCI device " PCI_PRI_FMT " aborted after"
1455 " encountering an error: %s",
1456 pci_dev->addr.domain, pci_dev->addr.bus,
1457 pci_dev->addr.devid, pci_dev->addr.function,
1458 strerror(rte_errno));
1462 if (!list[i].eth_dev)
1464 mlx5_dev_close(list[i].eth_dev);
1465 /* mac_addrs must not be freed because in dev_private */
1466 list[i].eth_dev->data->mac_addrs = NULL;
1467 claim_zero(rte_eth_dev_release_port(list[i].eth_dev));
1469 /* Restore original error. */
1477 static const struct rte_pci_id mlx5_pci_id_map[] = {
1479 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1480 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1483 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1484 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1487 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1488 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1491 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1492 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1495 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1496 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1499 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1500 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1503 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1504 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1507 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1508 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1511 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1512 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
1515 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1516 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
1523 static struct rte_pci_driver mlx5_driver = {
1525 .name = MLX5_DRIVER_NAME
1527 .id_table = mlx5_pci_id_map,
1528 .probe = mlx5_pci_probe,
1529 .drv_flags = (RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV |
1530 RTE_PCI_DRV_PROBE_AGAIN),
1533 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1536 * Suffix RTE_EAL_PMD_PATH with "-glue".
1538 * This function performs a sanity check on RTE_EAL_PMD_PATH before
1539 * suffixing its last component.
1542 * Output buffer, should be large enough otherwise NULL is returned.
1547 * Pointer to @p buf or @p NULL in case suffix cannot be appended.
1550 mlx5_glue_path(char *buf, size_t size)
1552 static const char *const bad[] = { "/", ".", "..", NULL };
1553 const char *path = RTE_EAL_PMD_PATH;
1554 size_t len = strlen(path);
1558 while (len && path[len - 1] == '/')
1560 for (off = len; off && path[off - 1] != '/'; --off)
1562 for (i = 0; bad[i]; ++i)
1563 if (!strncmp(path + off, bad[i], (int)(len - off)))
1565 i = snprintf(buf, size, "%.*s-glue", (int)len, path);
1566 if (i == -1 || (size_t)i >= size)
1571 "unable to append \"-glue\" to last component of"
1572 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\"),"
1573 " please re-configure DPDK");
1578 * Initialization routine for run-time dependency on rdma-core.
1581 mlx5_glue_init(void)
1583 char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")];
1584 const char *path[] = {
1586 * A basic security check is necessary before trusting
1587 * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH.
1589 (geteuid() == getuid() && getegid() == getgid() ?
1590 getenv("MLX5_GLUE_PATH") : NULL),
1592 * When RTE_EAL_PMD_PATH is set, use its glue-suffixed
1593 * variant, otherwise let dlopen() look up libraries on its
1596 (*RTE_EAL_PMD_PATH ?
1597 mlx5_glue_path(glue_path, sizeof(glue_path)) : ""),
1600 void *handle = NULL;
1604 while (!handle && i != RTE_DIM(path)) {
1613 end = strpbrk(path[i], ":;");
1615 end = path[i] + strlen(path[i]);
1616 len = end - path[i];
1621 ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE,
1623 (!len || *(end - 1) == '/') ? "" : "/");
1626 if (sizeof(name) != (size_t)ret + 1)
1628 DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"",
1630 handle = dlopen(name, RTLD_LAZY);
1641 DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg);
1644 sym = dlsym(handle, "mlx5_glue");
1645 if (!sym || !*sym) {
1649 DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg);
1658 "cannot initialize PMD due to missing run-time dependency on"
1659 " rdma-core libraries (libibverbs, libmlx5)");
1666 * Driver initialization routine.
1668 RTE_INIT(rte_mlx5_pmd_init)
1670 /* Initialize driver log type. */
1671 mlx5_logtype = rte_log_register("pmd.net.mlx5");
1672 if (mlx5_logtype >= 0)
1673 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
1675 /* Build the static tables for Verbs conversion. */
1676 mlx5_set_ptype_table();
1677 mlx5_set_cksum_table();
1678 mlx5_set_swp_types_table();
1680 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
1681 * huge pages. Calling ibv_fork_init() during init allows
1682 * applications to use fork() safely for purposes other than
1683 * using this PMD, which is not supported in forked processes.
1685 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
1686 /* Match the size of Rx completion entry to the size of a cacheline. */
1687 if (RTE_CACHE_LINE_SIZE == 128)
1688 setenv("MLX5_CQE_SIZE", "128", 0);
1690 * MLX5_DEVICE_FATAL_CLEANUP tells ibv_destroy functions to
1691 * cleanup all the Verbs resources even when the device was removed.
1693 setenv("MLX5_DEVICE_FATAL_CLEANUP", "1", 1);
1694 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1695 if (mlx5_glue_init())
1700 /* Glue structure must not contain any NULL pointers. */
1704 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i)
1705 assert(((const void *const *)mlx5_glue)[i]);
1708 if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) {
1710 "rdma-core glue \"%s\" mismatch: \"%s\" is required",
1711 mlx5_glue->version, MLX5_GLUE_VERSION);
1714 mlx5_glue->fork_init();
1715 rte_pci_register(&mlx5_driver);
1718 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1719 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1720 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");