drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12 #include <net/if.h>
  13 #include <sys/mman.h>
  14 #include <linux/rtnetlink.h>
  15
  16 #include <rte_malloc.h>
  17 #include <rte_ethdev_driver.h>
  18 #include <rte_ethdev_pci.h>
  19 #include <rte_pci.h>
  20 #include <rte_bus_pci.h>
  21 #include <rte_common.h>
  22 #include <rte_kvargs.h>
  23 #include <rte_rwlock.h>
  24 #include <rte_spinlock.h>
  25 #include <rte_string_fns.h>
  26 #include <rte_alarm.h>
  27
  28 #include <mlx5_glue.h>
  29 #include <mlx5_devx_cmds.h>
  30 #include <mlx5_common.h>
  31 #include <mlx5_common_os.h>
  32 #include <mlx5_common_mp.h>
  33 #include <mlx5_common_pci.h>
  34 #include <mlx5_malloc.h>
  35
  36 #include "mlx5_defs.h"
  37 #include "mlx5.h"
  38 #include "mlx5_utils.h"
  39 #include "mlx5_rxtx.h"
  40 #include "mlx5_autoconf.h"
  41 #include "mlx5_mr.h"
  42 #include "mlx5_flow.h"
  43 #include "rte_pmd_mlx5.h"
  44
  45 /* Device parameter to enable RX completion queue compression. */
  46 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  47
  48 /* Device parameter to enable RX completion entry padding to 128B. */
  49 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
  50
  51 /* Device parameter to enable padding Rx packet to cacheline size. */
  52 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  53
  54 /* Device parameter to enable Multi-Packet Rx queue. */
  55 #define MLX5_RX_MPRQ_EN "mprq_en"
  56
  57 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  58 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  59
  60 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  61 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  62
  63 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  64 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  65
  66 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  67 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  68
  69 /* Device parameter to configure inline send. Deprecated, ignored.*/
  70 #define MLX5_TXQ_INLINE "txq_inline"
  71
  72 /* Device parameter to limit packet size to inline with ordinary SEND. */
  73 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  74
  75 /* Device parameter to configure minimal data size to inline. */
  76 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  77
  78 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  79 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  80
  81 /*
  82  * Device parameter to configure the number of TX queues threshold for
  83  * enabling inline send.
  84  */
  85 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  86
  87 /*
  88  * Device parameter to configure the number of TX queues threshold for
  89  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  90  */
  91 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  92
  93 /* Device parameter to enable multi-packet send WQEs. */
  94 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  95
  96 /*
  97  * Device parameter to force doorbell register mapping
  98  * to non-cahed region eliminating the extra write memory barrier.
  99  */
 100 #define MLX5_TX_DB_NC "tx_db_nc"
 101
 102 /*
 103  * Device parameter to include 2 dsegs in the title WQEBB.
 104  * Deprecated, ignored.
 105  */
 106 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 107
 108 /*
 109  * Device parameter to limit the size of inlining packet.
 110  * Deprecated, ignored.
 111  */
 112 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 113
 114 /*
 115  * Device parameter to enable Tx scheduling on timestamps
 116  * and specify the packet pacing granularity in nanoseconds.
 117  */
 118 #define MLX5_TX_PP "tx_pp"
 119
 120 /*
 121  * Device parameter to specify skew in nanoseconds on Tx datapath,
 122  * it represents the time between SQ start WQE processing and
 123  * appearing actual packet data on the wire.
 124  */
 125 #define MLX5_TX_SKEW "tx_skew"
 126
 127 /*
 128  * Device parameter to enable hardware Tx vector.
 129  * Deprecated, ignored (no vectorized Tx routines anymore).
 130  */
 131 #define MLX5_TX_VEC_EN "tx_vec_en"
 132
 133 /* Device parameter to enable hardware Rx vector. */
 134 #define MLX5_RX_VEC_EN "rx_vec_en"
 135
 136 /* Allow L3 VXLAN flow creation. */
 137 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 138
 139 /* Activate DV E-Switch flow steering. */
 140 #define MLX5_DV_ESW_EN "dv_esw_en"
 141
 142 /* Activate DV flow steering. */
 143 #define MLX5_DV_FLOW_EN "dv_flow_en"
 144
 145 /* Enable extensive flow metadata support. */
 146 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 147
 148 /* Device parameter to let the user manage the lacp traffic of bonded device */
 149 #define MLX5_LACP_BY_USER "lacp_by_user"
 150
 151 /* Activate Netlink support in VF mode. */
 152 #define MLX5_VF_NL_EN "vf_nl_en"
 153
 154 /* Enable extending memsegs when creating a MR. */
 155 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 156
 157 /* Select port representors to instantiate. */
 158 #define MLX5_REPRESENTOR "representor"
 159
 160 /* Device parameter to configure the maximum number of dump files per queue. */
 161 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 162
 163 /* Configure timeout of LRO session (in microseconds). */
 164 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 165
 166 /*
 167  * Device parameter to configure the total data buffer size for a single
 168  * hairpin queue (logarithm value).
 169  */
 170 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 171
 172 /* Flow memory reclaim mode. */
 173 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 174
 175 /* The default memory allocator used in PMD. */
 176 #define MLX5_SYS_MEM_EN "sys_mem_en"
 177 /* Decap will be used or not. */
 178 #define MLX5_DECAP_EN "decap_en"
 179
 180 /* Shared memory between primary and secondary processes. */
 181 struct mlx5_shared_data *mlx5_shared_data;
 182
 183 /** Driver-specific log messages type. */
 184 int mlx5_logtype;
 185
 186 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 187                                                 LIST_HEAD_INITIALIZER();
 188 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
 189
 190 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 191 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 192         {
 193                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 194                 .trunk_size = 64,
 195                 .grow_trunk = 3,
 196                 .grow_shift = 2,
 197                 .need_lock = 0,
 198                 .release_mem_en = 1,
 199                 .malloc = mlx5_malloc,
 200                 .free = mlx5_free,
 201                 .type = "mlx5_encap_decap_ipool",
 202         },
 203         {
 204                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 205                 .trunk_size = 64,
 206                 .grow_trunk = 3,
 207                 .grow_shift = 2,
 208                 .need_lock = 0,
 209                 .release_mem_en = 1,
 210                 .malloc = mlx5_malloc,
 211                 .free = mlx5_free,
 212                 .type = "mlx5_push_vlan_ipool",
 213         },
 214         {
 215                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 216                 .trunk_size = 64,
 217                 .grow_trunk = 3,
 218                 .grow_shift = 2,
 219                 .need_lock = 0,
 220                 .release_mem_en = 1,
 221                 .malloc = mlx5_malloc,
 222                 .free = mlx5_free,
 223                 .type = "mlx5_tag_ipool",
 224         },
 225         {
 226                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 227                 .trunk_size = 64,
 228                 .grow_trunk = 3,
 229                 .grow_shift = 2,
 230                 .need_lock = 0,
 231                 .release_mem_en = 1,
 232                 .malloc = mlx5_malloc,
 233                 .free = mlx5_free,
 234                 .type = "mlx5_port_id_ipool",
 235         },
 236         {
 237                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 238                 .trunk_size = 64,
 239                 .grow_trunk = 3,
 240                 .grow_shift = 2,
 241                 .need_lock = 0,
 242                 .release_mem_en = 1,
 243                 .malloc = mlx5_malloc,
 244                 .free = mlx5_free,
 245                 .type = "mlx5_jump_ipool",
 246         },
 247 #endif
 248         {
 249                 .size = sizeof(struct mlx5_flow_meter),
 250                 .trunk_size = 64,
 251                 .grow_trunk = 3,
 252                 .grow_shift = 2,
 253                 .need_lock = 0,
 254                 .release_mem_en = 1,
 255                 .malloc = mlx5_malloc,
 256                 .free = mlx5_free,
 257                 .type = "mlx5_meter_ipool",
 258         },
 259         {
 260                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 261                 .trunk_size = 64,
 262                 .grow_trunk = 3,
 263                 .grow_shift = 2,
 264                 .need_lock = 0,
 265                 .release_mem_en = 1,
 266                 .malloc = mlx5_malloc,
 267                 .free = mlx5_free,
 268                 .type = "mlx5_mcp_ipool",
 269         },
 270         {
 271                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 272                 .trunk_size = 64,
 273                 .grow_trunk = 3,
 274                 .grow_shift = 2,
 275                 .need_lock = 0,
 276                 .release_mem_en = 1,
 277                 .malloc = mlx5_malloc,
 278                 .free = mlx5_free,
 279                 .type = "mlx5_hrxq_ipool",
 280         },
 281         {
 282                 /*
 283                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 284                  * It set in run time according to PCI function configuration.
 285                  */
 286                 .size = 0,
 287                 .trunk_size = 64,
 288                 .grow_trunk = 3,
 289                 .grow_shift = 2,
 290                 .need_lock = 0,
 291                 .release_mem_en = 1,
 292                 .malloc = mlx5_malloc,
 293                 .free = mlx5_free,
 294                 .type = "mlx5_flow_handle_ipool",
 295         },
 296         {
 297                 .size = sizeof(struct rte_flow),
 298                 .trunk_size = 4096,
 299                 .need_lock = 1,
 300                 .release_mem_en = 1,
 301                 .malloc = mlx5_malloc,
 302                 .free = mlx5_free,
 303                 .type = "rte_flow_ipool",
 304         },
 305 };
 306
 307
 308 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 309 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 310
 311 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 312
 313 /**
 314  * Allocate ID pool structure.
 315  *
 316  * @param[in] max_id
 317  *   The maximum id can be allocated from the pool.
 318  *
 319  * @return
 320  *   Pointer to pool object, NULL value otherwise.
 321  */
 322 struct mlx5_flow_id_pool *
 323 mlx5_flow_id_pool_alloc(uint32_t max_id)
 324 {
 325         struct mlx5_flow_id_pool *pool;
 326         void *mem;
 327
 328         pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool),
 329                            RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 330         if (!pool) {
 331                 DRV_LOG(ERR, "can't allocate id pool");
 332                 rte_errno  = ENOMEM;
 333                 return NULL;
 334         }
 335         mem = mlx5_malloc(MLX5_MEM_ZERO,
 336                           MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
 337                           RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 338         if (!mem) {
 339                 DRV_LOG(ERR, "can't allocate mem for id pool");
 340                 rte_errno  = ENOMEM;
 341                 goto error;
 342         }
 343         pool->free_arr = mem;
 344         pool->curr = pool->free_arr;
 345         pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
 346         pool->base_index = 0;
 347         pool->max_id = max_id;
 348         return pool;
 349 error:
 350         mlx5_free(pool);
 351         return NULL;
 352 }
 353
 354 /**
 355  * Release ID pool structure.
 356  *
 357  * @param[in] pool
 358  *   Pointer to flow id pool object to free.
 359  */
 360 void
 361 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
 362 {
 363         mlx5_free(pool->free_arr);
 364         mlx5_free(pool);
 365 }
 366
 367 /**
 368  * Generate ID.
 369  *
 370  * @param[in] pool
 371  *   Pointer to flow id pool.
 372  * @param[out] id
 373  *   The generated ID.
 374  *
 375  * @return
 376  *   0 on success, error value otherwise.
 377  */
 378 uint32_t
 379 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
 380 {
 381         if (pool->curr == pool->free_arr) {
 382                 if (pool->base_index == pool->max_id) {
 383                         rte_errno  = ENOMEM;
 384                         DRV_LOG(ERR, "no free id");
 385                         return -rte_errno;
 386                 }
 387                 *id = ++pool->base_index;
 388                 return 0;
 389         }
 390         *id = *(--pool->curr);
 391         return 0;
 392 }
 393
 394 /**
 395  * Release ID.
 396  *
 397  * @param[in] pool
 398  *   Pointer to flow id pool.
 399  * @param[out] id
 400  *   The generated ID.
 401  *
 402  * @return
 403  *   0 on success, error value otherwise.
 404  */
 405 uint32_t
 406 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
 407 {
 408         uint32_t size;
 409         uint32_t size2;
 410         void *mem;
 411
 412         if (pool->curr == pool->last) {
 413                 size = pool->curr - pool->free_arr;
 414                 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
 415                 MLX5_ASSERT(size2 > size);
 416                 mem = mlx5_malloc(0, size2 * sizeof(uint32_t), 0,
 417                                   SOCKET_ID_ANY);
 418                 if (!mem) {
 419                         DRV_LOG(ERR, "can't allocate mem for id pool");
 420                         rte_errno  = ENOMEM;
 421                         return -rte_errno;
 422                 }
 423                 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
 424                 mlx5_free(pool->free_arr);
 425                 pool->free_arr = mem;
 426                 pool->curr = pool->free_arr + size;
 427                 pool->last = pool->free_arr + size2;
 428         }
 429         *pool->curr = id;
 430         pool->curr++;
 431         return 0;
 432 }
 433
 434 /**
 435  * Initialize the shared aging list information per port.
 436  *
 437  * @param[in] sh
 438  *   Pointer to mlx5_dev_ctx_shared object.
 439  */
 440 static void
 441 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 442 {
 443         uint32_t i;
 444         struct mlx5_age_info *age_info;
 445
 446         for (i = 0; i < sh->max_port; i++) {
 447                 age_info = &sh->port[i].age_info;
 448                 age_info->flags = 0;
 449                 TAILQ_INIT(&age_info->aged_counters);
 450                 rte_spinlock_init(&age_info->aged_sl);
 451                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 452         }
 453 }
 454
 455 /**
 456  * Initialize the counters management structure.
 457  *
 458  * @param[in] sh
 459  *   Pointer to mlx5_dev_ctx_shared object to free
 460  */
 461 static void
 462 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 463 {
 464         int i;
 465
 466         memset(&sh->cmng, 0, sizeof(sh->cmng));
 467         TAILQ_INIT(&sh->cmng.flow_counters);
 468         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 469                 sh->cmng.ccont[i].min_id = MLX5_CNT_BATCH_OFFSET;
 470                 sh->cmng.ccont[i].max_id = -1;
 471                 sh->cmng.ccont[i].last_pool_idx = POOL_IDX_INVALID;
 472                 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
 473                 rte_spinlock_init(&sh->cmng.ccont[i].resize_sl);
 474                 TAILQ_INIT(&sh->cmng.ccont[i].counters);
 475                 rte_spinlock_init(&sh->cmng.ccont[i].csl);
 476         }
 477 }
 478
 479 /**
 480  * Destroy all the resources allocated for a counter memory management.
 481  *
 482  * @param[in] mng
 483  *   Pointer to the memory management structure.
 484  */
 485 static void
 486 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 487 {
 488         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 489
 490         LIST_REMOVE(mng, next);
 491         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 492         claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
 493         mlx5_free(mem);
 494 }
 495
 496 /**
 497  * Close and release all the resources of the counters management.
 498  *
 499  * @param[in] sh
 500  *   Pointer to mlx5_dev_ctx_shared object to free.
 501  */
 502 static void
 503 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 504 {
 505         struct mlx5_counter_stats_mem_mng *mng;
 506         int i;
 507         int j;
 508         int retries = 1024;
 509
 510         rte_errno = 0;
 511         while (--retries) {
 512                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 513                 if (rte_errno != EINPROGRESS)
 514                         break;
 515                 rte_pause();
 516         }
 517         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 518                 struct mlx5_flow_counter_pool *pool;
 519                 uint32_t batch = !!(i > 1);
 520
 521                 if (!sh->cmng.ccont[i].pools)
 522                         continue;
 523                 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 524                 while (pool) {
 525                         if (batch && pool->min_dcs)
 526                                 claim_zero(mlx5_devx_cmd_destroy
 527                                                                (pool->min_dcs));
 528                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 529                                 if (MLX5_POOL_GET_CNT(pool, j)->action)
 530                                         claim_zero
 531                                          (mlx5_glue->destroy_flow_action
 532                                           (MLX5_POOL_GET_CNT
 533                                           (pool, j)->action));
 534                                 if (!batch && MLX5_GET_POOL_CNT_EXT
 535                                     (pool, j)->dcs)
 536                                         claim_zero(mlx5_devx_cmd_destroy
 537                                                    (MLX5_GET_POOL_CNT_EXT
 538                                                     (pool, j)->dcs));
 539                         }
 540                         TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, next);
 541                         mlx5_free(pool);
 542                         pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 543                 }
 544                 mlx5_free(sh->cmng.ccont[i].pools);
 545         }
 546         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 547         while (mng) {
 548                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 549                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 550         }
 551         memset(&sh->cmng, 0, sizeof(sh->cmng));
 552 }
 553
 554 /**
 555  * Initialize the flow resources' indexed mempool.
 556  *
 557  * @param[in] sh
 558  *   Pointer to mlx5_dev_ctx_shared object.
 559  * @param[in] sh
 560  *   Pointer to user dev config.
 561  */
 562 static void
 563 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 564                        const struct mlx5_dev_config *config)
 565 {
 566         uint8_t i;
 567         struct mlx5_indexed_pool_config cfg;
 568
 569         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 570                 cfg = mlx5_ipool_cfg[i];
 571                 switch (i) {
 572                 default:
 573                         break;
 574                 /*
 575                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 576                  * according to PCI function flow configuration.
 577                  */
 578                 case MLX5_IPOOL_MLX5_FLOW:
 579                         cfg.size = config->dv_flow_en ?
 580                                 sizeof(struct mlx5_flow_handle) :
 581                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 582                         break;
 583                 }
 584                 if (config->reclaim_mode)
 585                         cfg.release_mem_en = 1;
 586                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 587         }
 588 }
 589
 590 /**
 591  * Release the flow resources' indexed mempool.
 592  *
 593  * @param[in] sh
 594  *   Pointer to mlx5_dev_ctx_shared object.
 595  */
 596 static void
 597 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 598 {
 599         uint8_t i;
 600
 601         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 602                 mlx5_ipool_destroy(sh->ipool[i]);
 603 }
 604
 605 /*
 606  * Check if dynamic flex parser for eCPRI already exists.
 607  *
 608  * @param dev
 609  *   Pointer to Ethernet device structure.
 610  *
 611  * @return
 612  *   true on exists, false on not.
 613  */
 614 bool
 615 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
 616 {
 617         struct mlx5_priv *priv = dev->data->dev_private;
 618         struct mlx5_flex_parser_profiles *prf =
 619                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 620
 621         return !!prf->obj;
 622 }
 623
 624 /*
 625  * Allocation of a flex parser for eCPRI. Once created, this parser related
 626  * resources will be held until the device is closed.
 627  *
 628  * @param dev
 629  *   Pointer to Ethernet device structure.
 630  *
 631  * @return
 632  *   0 on success, a negative errno value otherwise and rte_errno is set.
 633  */
 634 int
 635 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
 636 {
 637         struct mlx5_priv *priv = dev->data->dev_private;
 638         struct mlx5_flex_parser_profiles *prf =
 639                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 640         struct mlx5_devx_graph_node_attr node = {
 641                 .modify_field_select = 0,
 642         };
 643         uint32_t ids[8];
 644         int ret;
 645
 646         if (!priv->config.hca_attr.parse_graph_flex_node) {
 647                 DRV_LOG(ERR, "Dynamic flex parser is not supported "
 648                         "for device %s.", priv->dev_data->name);
 649                 return -ENOTSUP;
 650         }
 651         node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
 652         /* 8 bytes now: 4B common header + 4B message body header. */
 653         node.header_length_base_value = 0x8;
 654         /* After MAC layer: Ether / VLAN. */
 655         node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
 656         /* Type of compared condition should be 0xAEFE in the L2 layer. */
 657         node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
 658         /* Sample #0: type in common header. */
 659         node.sample[0].flow_match_sample_en = 1;
 660         /* Fixed offset. */
 661         node.sample[0].flow_match_sample_offset_mode = 0x0;
 662         /* Only the 2nd byte will be used. */
 663         node.sample[0].flow_match_sample_field_base_offset = 0x0;
 664         /* Sample #1: message payload. */
 665         node.sample[1].flow_match_sample_en = 1;
 666         /* Fixed offset. */
 667         node.sample[1].flow_match_sample_offset_mode = 0x0;
 668         /*
 669          * Only the first two bytes will be used right now, and its offset will
 670          * start after the common header that with the length of a DW(u32).
 671          */
 672         node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
 673         prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
 674         if (!prf->obj) {
 675                 DRV_LOG(ERR, "Failed to create flex parser node object.");
 676                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 677         }
 678         prf->num = 2;
 679         ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
 680         if (ret) {
 681                 DRV_LOG(ERR, "Failed to query sample IDs.");
 682                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 683         }
 684         prf->offset[0] = 0x0;
 685         prf->offset[1] = sizeof(uint32_t);
 686         prf->ids[0] = ids[0];
 687         prf->ids[1] = ids[1];
 688         return 0;
 689 }
 690
 691 /*
 692  * Destroy the flex parser node, including the parser itself, input / output
 693  * arcs and DW samples. Resources could be reused then.
 694  *
 695  * @param dev
 696  *   Pointer to Ethernet device structure.
 697  */
 698 static void
 699 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
 700 {
 701         struct mlx5_priv *priv = dev->data->dev_private;
 702         struct mlx5_flex_parser_profiles *prf =
 703                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 704
 705         if (prf->obj)
 706                 mlx5_devx_cmd_destroy(prf->obj);
 707         prf->obj = NULL;
 708 }
 709
 710 /**
 711  * Allocate shared device context. If there is multiport device the
 712  * master and representors will share this context, if there is single
 713  * port dedicated device, the context will be used by only given
 714  * port due to unification.
 715  *
 716  * Routine first searches the context for the specified device name,
 717  * if found the shared context assumed and reference counter is incremented.
 718  * If no context found the new one is created and initialized with specified
 719  * device context and parameters.
 720  *
 721  * @param[in] spawn
 722  *   Pointer to the device attributes (name, port, etc).
 723  * @param[in] config
 724  *   Pointer to device configuration structure.
 725  *
 726  * @return
 727  *   Pointer to mlx5_dev_ctx_shared object on success,
 728  *   otherwise NULL and rte_errno is set.
 729  */
 730 struct mlx5_dev_ctx_shared *
 731 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
 732                            const struct mlx5_dev_config *config)
 733 {
 734         struct mlx5_dev_ctx_shared *sh;
 735         int err = 0;
 736         uint32_t i;
 737         struct mlx5_devx_tis_attr tis_attr = { 0 };
 738
 739         MLX5_ASSERT(spawn);
 740         /* Secondary process should not create the shared context. */
 741         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 742         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 743         /* Search for IB context by device name. */
 744         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
 745                 if (!strcmp(sh->ibdev_name,
 746                         mlx5_os_get_dev_device_name(spawn->phys_dev))) {
 747                         sh->refcnt++;
 748                         goto exit;
 749                 }
 750         }
 751         /* No device found, we have to create new shared context. */
 752         MLX5_ASSERT(spawn->max_port);
 753         sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
 754                          sizeof(struct mlx5_dev_ctx_shared) +
 755                          spawn->max_port *
 756                          sizeof(struct mlx5_dev_shared_port),
 757                          RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 758         if (!sh) {
 759                 DRV_LOG(ERR, "shared context allocation failure");
 760                 rte_errno  = ENOMEM;
 761                 goto exit;
 762         }
 763         err = mlx5_os_open_device(spawn, config, sh);
 764         if (!sh->ctx)
 765                 goto error;
 766         err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
 767         if (err) {
 768                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
 769                 goto error;
 770         }
 771         sh->refcnt = 1;
 772         sh->max_port = spawn->max_port;
 773         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
 774                 sizeof(sh->ibdev_name) - 1);
 775         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
 776                 sizeof(sh->ibdev_path) - 1);
 777         /*
 778          * Setting port_id to max unallowed value means
 779          * there is no interrupt subhandler installed for
 780          * the given port index i.
 781          */
 782         for (i = 0; i < sh->max_port; i++) {
 783                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 784                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
 785         }
 786         sh->pd = mlx5_glue->alloc_pd(sh->ctx);
 787         if (sh->pd == NULL) {
 788                 DRV_LOG(ERR, "PD allocation failure");
 789                 err = ENOMEM;
 790                 goto error;
 791         }
 792         if (sh->devx) {
 793                 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
 794                 if (err) {
 795                         DRV_LOG(ERR, "Fail to extract pdn from PD");
 796                         goto error;
 797                 }
 798                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
 799                 if (!sh->td) {
 800                         DRV_LOG(ERR, "TD allocation failure");
 801                         err = ENOMEM;
 802                         goto error;
 803                 }
 804                 tis_attr.transport_domain = sh->td->id;
 805                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
 806                 if (!sh->tis) {
 807                         DRV_LOG(ERR, "TIS allocation failure");
 808                         err = ENOMEM;
 809                         goto error;
 810                 }
 811                 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, 0);
 812                 if (!sh->tx_uar) {
 813                         DRV_LOG(ERR, "Failed to allocate DevX UAR.");
 814                         err = ENOMEM;
 815                         goto error;
 816                 }
 817                 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, 0);
 818                 if (!sh->devx_rx_uar) {
 819                         DRV_LOG(ERR, "Failed to allocate Rx DevX UAR.");
 820                         err = ENOMEM;
 821                         goto error;
 822                 }
 823         }
 824         sh->flow_id_pool = mlx5_flow_id_pool_alloc
 825                                         ((1 << HAIRPIN_FLOW_ID_BITS) - 1);
 826         if (!sh->flow_id_pool) {
 827                 DRV_LOG(ERR, "can't create flow id pool");
 828                 err = ENOMEM;
 829                 goto error;
 830         }
 831 #ifndef RTE_ARCH_64
 832         /* Initialize UAR access locks for 32bit implementations. */
 833         rte_spinlock_init(&sh->uar_lock_cq);
 834         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
 835                 rte_spinlock_init(&sh->uar_lock[i]);
 836 #endif
 837         /*
 838          * Once the device is added to the list of memory event
 839          * callback, its global MR cache table cannot be expanded
 840          * on the fly because of deadlock. If it overflows, lookup
 841          * should be done by searching MR list linearly, which is slow.
 842          *
 843          * At this point the device is not added to the memory
 844          * event list yet, context is just being created.
 845          */
 846         err = mlx5_mr_btree_init(&sh->share_cache.cache,
 847                                  MLX5_MR_BTREE_CACHE_N * 2,
 848                                  spawn->pci_dev->device.numa_node);
 849         if (err) {
 850                 err = rte_errno;
 851                 goto error;
 852         }
 853         mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
 854                               &sh->share_cache.dereg_mr_cb);
 855         mlx5_os_dev_shared_handler_install(sh);
 856         sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
 857         if (!sh->cnt_id_tbl) {
 858                 err = rte_errno;
 859                 goto error;
 860         }
 861         mlx5_flow_aging_init(sh);
 862         mlx5_flow_counters_mng_init(sh);
 863         mlx5_flow_ipool_create(sh, config);
 864         /* Add device to memory callback list. */
 865         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 866         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
 867                          sh, mem_event_cb);
 868         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 869         /* Add context to the global device list. */
 870         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
 871 exit:
 872         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 873         return sh;
 874 error:
 875         pthread_mutex_destroy(&sh->txpp.mutex);
 876         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 877         MLX5_ASSERT(sh);
 878         if (sh->cnt_id_tbl) {
 879                 mlx5_l3t_destroy(sh->cnt_id_tbl);
 880                 sh->cnt_id_tbl = NULL;
 881         }
 882         if (sh->tx_uar) {
 883                 mlx5_glue->devx_free_uar(sh->tx_uar);
 884                 sh->tx_uar = NULL;
 885         }
 886         if (sh->tis)
 887                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 888         if (sh->td)
 889                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 890         if (sh->devx_rx_uar)
 891                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
 892         if (sh->pd)
 893                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 894         if (sh->ctx)
 895                 claim_zero(mlx5_glue->close_device(sh->ctx));
 896         if (sh->flow_id_pool)
 897                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 898         mlx5_free(sh);
 899         MLX5_ASSERT(err > 0);
 900         rte_errno = err;
 901         return NULL;
 902 }
 903
 904 /**
 905  * Free shared IB device context. Decrement counter and if zero free
 906  * all allocated resources and close handles.
 907  *
 908  * @param[in] sh
 909  *   Pointer to mlx5_dev_ctx_shared object to free
 910  */
 911 void
 912 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
 913 {
 914         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 915 #ifdef RTE_LIBRTE_MLX5_DEBUG
 916         /* Check the object presence in the list. */
 917         struct mlx5_dev_ctx_shared *lctx;
 918
 919         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
 920                 if (lctx == sh)
 921                         break;
 922         MLX5_ASSERT(lctx);
 923         if (lctx != sh) {
 924                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
 925                 goto exit;
 926         }
 927 #endif
 928         MLX5_ASSERT(sh);
 929         MLX5_ASSERT(sh->refcnt);
 930         /* Secondary process should not free the shared context. */
 931         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 932         if (--sh->refcnt)
 933                 goto exit;
 934         /* Remove from memory callback device list. */
 935         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 936         LIST_REMOVE(sh, mem_event_cb);
 937         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 938         /* Release created Memory Regions. */
 939         mlx5_mr_release_cache(&sh->share_cache);
 940         /* Remove context from the global device list. */
 941         LIST_REMOVE(sh, next);
 942         /*
 943          *  Ensure there is no async event handler installed.
 944          *  Only primary process handles async device events.
 945          **/
 946         mlx5_flow_counters_mng_close(sh);
 947         mlx5_flow_ipool_destroy(sh);
 948         mlx5_os_dev_shared_handler_uninstall(sh);
 949         if (sh->cnt_id_tbl) {
 950                 mlx5_l3t_destroy(sh->cnt_id_tbl);
 951                 sh->cnt_id_tbl = NULL;
 952         }
 953         if (sh->tx_uar) {
 954                 mlx5_glue->devx_free_uar(sh->tx_uar);
 955                 sh->tx_uar = NULL;
 956         }
 957         if (sh->pd)
 958                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 959         if (sh->tis)
 960                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 961         if (sh->td)
 962                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 963         if (sh->devx_rx_uar)
 964                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
 965         if (sh->ctx)
 966                 claim_zero(mlx5_glue->close_device(sh->ctx));
 967         if (sh->flow_id_pool)
 968                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 969         pthread_mutex_destroy(&sh->txpp.mutex);
 970         mlx5_free(sh);
 971 exit:
 972         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 973 }
 974
 975 /**
 976  * Destroy table hash list and all the root entries per domain.
 977  *
 978  * @param[in] priv
 979  *   Pointer to the private device data structure.
 980  */
 981 void
 982 mlx5_free_table_hash_list(struct mlx5_priv *priv)
 983 {
 984         struct mlx5_dev_ctx_shared *sh = priv->sh;
 985         struct mlx5_flow_tbl_data_entry *tbl_data;
 986         union mlx5_flow_tbl_key table_key = {
 987                 {
 988                         .table_id = 0,
 989                         .reserved = 0,
 990                         .domain = 0,
 991                         .direction = 0,
 992                 }
 993         };
 994         struct mlx5_hlist_entry *pos;
 995
 996         if (!sh->flow_tbls)
 997                 return;
 998         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 999         if (pos) {
1000                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1001                                         entry);
1002                 MLX5_ASSERT(tbl_data);
1003                 mlx5_hlist_remove(sh->flow_tbls, pos);
1004                 mlx5_free(tbl_data);
1005         }
1006         table_key.direction = 1;
1007         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1008         if (pos) {
1009                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1010                                         entry);
1011                 MLX5_ASSERT(tbl_data);
1012                 mlx5_hlist_remove(sh->flow_tbls, pos);
1013                 mlx5_free(tbl_data);
1014         }
1015         table_key.direction = 0;
1016         table_key.domain = 1;
1017         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1018         if (pos) {
1019                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1020                                         entry);
1021                 MLX5_ASSERT(tbl_data);
1022                 mlx5_hlist_remove(sh->flow_tbls, pos);
1023                 mlx5_free(tbl_data);
1024         }
1025         mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
1026 }
1027
1028 /**
1029  * Initialize flow table hash list and create the root tables entry
1030  * for each domain.
1031  *
1032  * @param[in] priv
1033  *   Pointer to the private device data structure.
1034  *
1035  * @return
1036  *   Zero on success, positive error code otherwise.
1037  */
1038 int
1039 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
1040 {
1041         struct mlx5_dev_ctx_shared *sh = priv->sh;
1042         char s[MLX5_HLIST_NAMESIZE];
1043         int err = 0;
1044
1045         MLX5_ASSERT(sh);
1046         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1047         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
1048         if (!sh->flow_tbls) {
1049                 DRV_LOG(ERR, "flow tables with hash creation failed.");
1050                 err = ENOMEM;
1051                 return err;
1052         }
1053 #ifndef HAVE_MLX5DV_DR
1054         /*
1055          * In case we have not DR support, the zero tables should be created
1056          * because DV expect to see them even if they cannot be created by
1057          * RDMA-CORE.
1058          */
1059         union mlx5_flow_tbl_key table_key = {
1060                 {
1061                         .table_id = 0,
1062                         .reserved = 0,
1063                         .domain = 0,
1064                         .direction = 0,
1065                 }
1066         };
1067         struct mlx5_flow_tbl_data_entry *tbl_data = mlx5_malloc(MLX5_MEM_ZERO,
1068                                                           sizeof(*tbl_data), 0,
1069                                                           SOCKET_ID_ANY);
1070
1071         if (!tbl_data) {
1072                 err = ENOMEM;
1073                 goto error;
1074         }
1075         tbl_data->entry.key = table_key.v64;
1076         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1077         if (err)
1078                 goto error;
1079         rte_atomic32_init(&tbl_data->tbl.refcnt);
1080         rte_atomic32_inc(&tbl_data->tbl.refcnt);
1081         table_key.direction = 1;
1082         tbl_data = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tbl_data), 0,
1083                                SOCKET_ID_ANY);
1084         if (!tbl_data) {
1085                 err = ENOMEM;
1086                 goto error;
1087         }
1088         tbl_data->entry.key = table_key.v64;
1089         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1090         if (err)
1091                 goto error;
1092         rte_atomic32_init(&tbl_data->tbl.refcnt);
1093         rte_atomic32_inc(&tbl_data->tbl.refcnt);
1094         table_key.direction = 0;
1095         table_key.domain = 1;
1096         tbl_data = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tbl_data), 0,
1097                                SOCKET_ID_ANY);
1098         if (!tbl_data) {
1099                 err = ENOMEM;
1100                 goto error;
1101         }
1102         tbl_data->entry.key = table_key.v64;
1103         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1104         if (err)
1105                 goto error;
1106         rte_atomic32_init(&tbl_data->tbl.refcnt);
1107         rte_atomic32_inc(&tbl_data->tbl.refcnt);
1108         return err;
1109 error:
1110         mlx5_free_table_hash_list(priv);
1111 #endif /* HAVE_MLX5DV_DR */
1112         return err;
1113 }
1114
1115 /**
1116  * Retrieve integer value from environment variable.
1117  *
1118  * @param[in] name
1119  *   Environment variable name.
1120  *
1121  * @return
1122  *   Integer value, 0 if the variable is not set.
1123  */
1124 int
1125 mlx5_getenv_int(const char *name)
1126 {
1127         const char *val = getenv(name);
1128
1129         if (val == NULL)
1130                 return 0;
1131         return atoi(val);
1132 }
1133
1134 /**
1135  * DPDK callback to add udp tunnel port
1136  *
1137  * @param[in] dev
1138  *   A pointer to eth_dev
1139  * @param[in] udp_tunnel
1140  *   A pointer to udp tunnel
1141  *
1142  * @return
1143  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1144  */
1145 int
1146 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1147                          struct rte_eth_udp_tunnel *udp_tunnel)
1148 {
1149         MLX5_ASSERT(udp_tunnel != NULL);
1150         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1151             udp_tunnel->udp_port == 4789)
1152                 return 0;
1153         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1154             udp_tunnel->udp_port == 4790)
1155                 return 0;
1156         return -ENOTSUP;
1157 }
1158
1159 /**
1160  * Initialize process private data structure.
1161  *
1162  * @param dev
1163  *   Pointer to Ethernet device structure.
1164  *
1165  * @return
1166  *   0 on success, a negative errno value otherwise and rte_errno is set.
1167  */
1168 int
1169 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1170 {
1171         struct mlx5_priv *priv = dev->data->dev_private;
1172         struct mlx5_proc_priv *ppriv;
1173         size_t ppriv_size;
1174
1175         /*
1176          * UAR register table follows the process private structure. BlueFlame
1177          * registers for Tx queues are stored in the table.
1178          */
1179         ppriv_size =
1180                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1181         ppriv = mlx5_malloc(MLX5_MEM_RTE, ppriv_size, RTE_CACHE_LINE_SIZE,
1182                             dev->device->numa_node);
1183         if (!ppriv) {
1184                 rte_errno = ENOMEM;
1185                 return -rte_errno;
1186         }
1187         ppriv->uar_table_sz = ppriv_size;
1188         dev->process_private = ppriv;
1189         return 0;
1190 }
1191
1192 /**
1193  * Un-initialize process private data structure.
1194  *
1195  * @param dev
1196  *   Pointer to Ethernet device structure.
1197  */
1198 static void
1199 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1200 {
1201         if (!dev->process_private)
1202                 return;
1203         mlx5_free(dev->process_private);
1204         dev->process_private = NULL;
1205 }
1206
1207 /**
1208  * DPDK callback to close the device.
1209  *
1210  * Destroy all queues and objects, free memory.
1211  *
1212  * @param dev
1213  *   Pointer to Ethernet device structure.
1214  */
1215 void
1216 mlx5_dev_close(struct rte_eth_dev *dev)
1217 {
1218         struct mlx5_priv *priv = dev->data->dev_private;
1219         unsigned int i;
1220         int ret;
1221
1222         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1223                 /* Check if process_private released. */
1224                 if (!dev->process_private)
1225                         return;
1226                 mlx5_tx_uar_uninit_secondary(dev);
1227                 mlx5_proc_priv_uninit(dev);
1228                 rte_eth_dev_release_port(dev);
1229                 return;
1230         }
1231         if (!priv->sh)
1232                 return;
1233         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1234                 dev->data->port_id,
1235                 ((priv->sh->ctx != NULL) ?
1236                 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1237         /*
1238          * If default mreg copy action is removed at the stop stage,
1239          * the search will return none and nothing will be done anymore.
1240          */
1241         mlx5_flow_stop_default(dev);
1242         mlx5_traffic_disable(dev);
1243         /*
1244          * If all the flows are already flushed in the device stop stage,
1245          * then this will return directly without any action.
1246          */
1247         mlx5_flow_list_flush(dev, &priv->flows, true);
1248         mlx5_flow_meter_flush(dev, NULL);
1249         /* Free the intermediate buffers for flow creation. */
1250         mlx5_flow_free_intermediate(dev);
1251         /* Prevent crashes when queues are still in use. */
1252         dev->rx_pkt_burst = removed_rx_burst;
1253         dev->tx_pkt_burst = removed_tx_burst;
1254         rte_wmb();
1255         /* Disable datapath on secondary process. */
1256         mlx5_mp_os_req_stop_rxtx(dev);
1257         /* Free the eCPRI flex parser resource. */
1258         mlx5_flex_parser_ecpri_release(dev);
1259         if (priv->rxqs != NULL) {
1260                 /* XXX race condition if mlx5_rx_burst() is still running. */
1261                 usleep(1000);
1262                 for (i = 0; (i != priv->rxqs_n); ++i)
1263                         mlx5_rxq_release(dev, i);
1264                 priv->rxqs_n = 0;
1265                 priv->rxqs = NULL;
1266         }
1267         if (priv->txqs != NULL) {
1268                 /* XXX race condition if mlx5_tx_burst() is still running. */
1269                 usleep(1000);
1270                 for (i = 0; (i != priv->txqs_n); ++i)
1271                         mlx5_txq_release(dev, i);
1272                 priv->txqs_n = 0;
1273                 priv->txqs = NULL;
1274         }
1275         mlx5_proc_priv_uninit(dev);
1276         if (priv->mreg_cp_tbl)
1277                 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1278         mlx5_mprq_free_mp(dev);
1279         mlx5_os_free_shared_dr(priv);
1280         if (priv->rss_conf.rss_key != NULL)
1281                 mlx5_free(priv->rss_conf.rss_key);
1282         if (priv->reta_idx != NULL)
1283                 mlx5_free(priv->reta_idx);
1284         if (priv->config.vf)
1285                 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1286                                        dev->data->mac_addrs,
1287                                        MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1288         if (priv->nl_socket_route >= 0)
1289                 close(priv->nl_socket_route);
1290         if (priv->nl_socket_rdma >= 0)
1291                 close(priv->nl_socket_rdma);
1292         if (priv->vmwa_context)
1293                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1294         ret = mlx5_hrxq_verify(dev);
1295         if (ret)
1296                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1297                         dev->data->port_id);
1298         ret = mlx5_ind_table_obj_verify(dev);
1299         if (ret)
1300                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1301                         dev->data->port_id);
1302         ret = mlx5_rxq_obj_verify(dev);
1303         if (ret)
1304                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1305                         dev->data->port_id);
1306         ret = mlx5_rxq_verify(dev);
1307         if (ret)
1308                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1309                         dev->data->port_id);
1310         ret = mlx5_txq_obj_verify(dev);
1311         if (ret)
1312                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1313                         dev->data->port_id);
1314         ret = mlx5_txq_verify(dev);
1315         if (ret)
1316                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1317                         dev->data->port_id);
1318         ret = mlx5_flow_verify(dev);
1319         if (ret)
1320                 DRV_LOG(WARNING, "port %u some flows still remain",
1321                         dev->data->port_id);
1322         /*
1323          * Free the shared context in last turn, because the cleanup
1324          * routines above may use some shared fields, like
1325          * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1326          * ifindex if Netlink fails.
1327          */
1328         mlx5_free_shared_dev_ctx(priv->sh);
1329         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1330                 unsigned int c = 0;
1331                 uint16_t port_id;
1332
1333                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1334                         struct mlx5_priv *opriv =
1335                                 rte_eth_devices[port_id].data->dev_private;
1336
1337                         if (!opriv ||
1338                             opriv->domain_id != priv->domain_id ||
1339                             &rte_eth_devices[port_id] == dev)
1340                                 continue;
1341                         ++c;
1342                         break;
1343                 }
1344                 if (!c)
1345                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1346         }
1347         memset(priv, 0, sizeof(*priv));
1348         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1349         /*
1350          * Reset mac_addrs to NULL such that it is not freed as part of
1351          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1352          * it is freed when dev_private is freed.
1353          */
1354         dev->data->mac_addrs = NULL;
1355 }
1356
1357 /**
1358  * Verify and store value for device argument.
1359  *
1360  * @param[in] key
1361  *   Key argument to verify.
1362  * @param[in] val
1363  *   Value associated with key.
1364  * @param opaque
1365  *   User data.
1366  *
1367  * @return
1368  *   0 on success, a negative errno value otherwise and rte_errno is set.
1369  */
1370 static int
1371 mlx5_args_check(const char *key, const char *val, void *opaque)
1372 {
1373         struct mlx5_dev_config *config = opaque;
1374         unsigned long mod;
1375         signed long tmp;
1376
1377         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1378         if (!strcmp(MLX5_REPRESENTOR, key))
1379                 return 0;
1380         errno = 0;
1381         tmp = strtol(val, NULL, 0);
1382         if (errno) {
1383                 rte_errno = errno;
1384                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1385                 return -rte_errno;
1386         }
1387         if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1388                 /* Negative values are acceptable for some keys only. */
1389                 rte_errno = EINVAL;
1390                 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1391                 return -rte_errno;
1392         }
1393         mod = tmp >= 0 ? tmp : -tmp;
1394         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1395                 config->cqe_comp = !!tmp;
1396         } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1397                 config->cqe_pad = !!tmp;
1398         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1399                 config->hw_padding = !!tmp;
1400         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1401                 config->mprq.enabled = !!tmp;
1402         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1403                 config->mprq.stride_num_n = tmp;
1404         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1405                 config->mprq.stride_size_n = tmp;
1406         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1407                 config->mprq.max_memcpy_len = tmp;
1408         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1409                 config->mprq.min_rxqs_num = tmp;
1410         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1411                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1412                                  " converted to txq_inline_max", key);
1413                 config->txq_inline_max = tmp;
1414         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1415                 config->txq_inline_max = tmp;
1416         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1417                 config->txq_inline_min = tmp;
1418         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1419                 config->txq_inline_mpw = tmp;
1420         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1421                 config->txqs_inline = tmp;
1422         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1423                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1424         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1425                 config->mps = !!tmp;
1426         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1427                 if (tmp != MLX5_TXDB_CACHED &&
1428                     tmp != MLX5_TXDB_NCACHED &&
1429                     tmp != MLX5_TXDB_HEURISTIC) {
1430                         DRV_LOG(ERR, "invalid Tx doorbell "
1431                                      "mapping parameter");
1432                         rte_errno = EINVAL;
1433                         return -rte_errno;
1434                 }
1435                 config->dbnc = tmp;
1436         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1437                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1438         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1439                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1440                                  " converted to txq_inline_mpw", key);
1441                 config->txq_inline_mpw = tmp;
1442         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1443                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1444         } else if (strcmp(MLX5_TX_PP, key) == 0) {
1445                 if (!mod) {
1446                         DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1447                         rte_errno = EINVAL;
1448                         return -rte_errno;
1449                 }
1450                 config->tx_pp = tmp;
1451         } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1452                 config->tx_skew = tmp;
1453         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1454                 config->rx_vec_en = !!tmp;
1455         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1456                 config->l3_vxlan_en = !!tmp;
1457         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1458                 config->vf_nl_en = !!tmp;
1459         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1460                 config->dv_esw_en = !!tmp;
1461         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1462                 config->dv_flow_en = !!tmp;
1463         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1464                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1465                     tmp != MLX5_XMETA_MODE_META16 &&
1466                     tmp != MLX5_XMETA_MODE_META32) {
1467                         DRV_LOG(ERR, "invalid extensive "
1468                                      "metadata parameter");
1469                         rte_errno = EINVAL;
1470                         return -rte_errno;
1471                 }
1472                 config->dv_xmeta_en = tmp;
1473         } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1474                 config->lacp_by_user = !!tmp;
1475         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1476                 config->mr_ext_memseg_en = !!tmp;
1477         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1478                 config->max_dump_files_num = tmp;
1479         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1480                 config->lro.timeout = tmp;
1481         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1482                 DRV_LOG(DEBUG, "class argument is %s.", val);
1483         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1484                 config->log_hp_size = tmp;
1485         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1486                 if (tmp != MLX5_RCM_NONE &&
1487                     tmp != MLX5_RCM_LIGHT &&
1488                     tmp != MLX5_RCM_AGGR) {
1489                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1490                         rte_errno = EINVAL;
1491                         return -rte_errno;
1492                 }
1493                 config->reclaim_mode = tmp;
1494         } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1495                 config->sys_mem_en = !!tmp;
1496         } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1497                 config->decap_en = !!tmp;
1498         } else {
1499                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1500                 rte_errno = EINVAL;
1501                 return -rte_errno;
1502         }
1503         return 0;
1504 }
1505
1506 /**
1507  * Parse device parameters.
1508  *
1509  * @param config
1510  *   Pointer to device configuration structure.
1511  * @param devargs
1512  *   Device arguments structure.
1513  *
1514  * @return
1515  *   0 on success, a negative errno value otherwise and rte_errno is set.
1516  */
1517 int
1518 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1519 {
1520         const char **params = (const char *[]){
1521                 MLX5_RXQ_CQE_COMP_EN,
1522                 MLX5_RXQ_CQE_PAD_EN,
1523                 MLX5_RXQ_PKT_PAD_EN,
1524                 MLX5_RX_MPRQ_EN,
1525                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1526                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1527                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1528                 MLX5_RXQS_MIN_MPRQ,
1529                 MLX5_TXQ_INLINE,
1530                 MLX5_TXQ_INLINE_MIN,
1531                 MLX5_TXQ_INLINE_MAX,
1532                 MLX5_TXQ_INLINE_MPW,
1533                 MLX5_TXQS_MIN_INLINE,
1534                 MLX5_TXQS_MAX_VEC,
1535                 MLX5_TXQ_MPW_EN,
1536                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1537                 MLX5_TXQ_MAX_INLINE_LEN,
1538                 MLX5_TX_DB_NC,
1539                 MLX5_TX_PP,
1540                 MLX5_TX_SKEW,
1541                 MLX5_TX_VEC_EN,
1542                 MLX5_RX_VEC_EN,
1543                 MLX5_L3_VXLAN_EN,
1544                 MLX5_VF_NL_EN,
1545                 MLX5_DV_ESW_EN,
1546                 MLX5_DV_FLOW_EN,
1547                 MLX5_DV_XMETA_EN,
1548                 MLX5_LACP_BY_USER,
1549                 MLX5_MR_EXT_MEMSEG_EN,
1550                 MLX5_REPRESENTOR,
1551                 MLX5_MAX_DUMP_FILES_NUM,
1552                 MLX5_LRO_TIMEOUT_USEC,
1553                 MLX5_CLASS_ARG_NAME,
1554                 MLX5_HP_BUF_SIZE,
1555                 MLX5_RECLAIM_MEM,
1556                 MLX5_SYS_MEM_EN,
1557                 MLX5_DECAP_EN,
1558                 NULL,
1559         };
1560         struct rte_kvargs *kvlist;
1561         int ret = 0;
1562         int i;
1563
1564         if (devargs == NULL)
1565                 return 0;
1566         /* Following UGLY cast is done to pass checkpatch. */
1567         kvlist = rte_kvargs_parse(devargs->args, params);
1568         if (kvlist == NULL) {
1569                 rte_errno = EINVAL;
1570                 return -rte_errno;
1571         }
1572         /* Process parameters. */
1573         for (i = 0; (params[i] != NULL); ++i) {
1574                 if (rte_kvargs_count(kvlist, params[i])) {
1575                         ret = rte_kvargs_process(kvlist, params[i],
1576                                                  mlx5_args_check, config);
1577                         if (ret) {
1578                                 rte_errno = EINVAL;
1579                                 rte_kvargs_free(kvlist);
1580                                 return -rte_errno;
1581                         }
1582                 }
1583         }
1584         rte_kvargs_free(kvlist);
1585         return 0;
1586 }
1587
1588 /**
1589  * Configures the minimal amount of data to inline into WQE
1590  * while sending packets.
1591  *
1592  * - the txq_inline_min has the maximal priority, if this
1593  *   key is specified in devargs
1594  * - if DevX is enabled the inline mode is queried from the
1595  *   device (HCA attributes and NIC vport context if needed).
1596  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1597  *   and none (0 bytes) for other NICs
1598  *
1599  * @param spawn
1600  *   Verbs device parameters (name, port, switch_info) to spawn.
1601  * @param config
1602  *   Device configuration parameters.
1603  */
1604 void
1605 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1606                     struct mlx5_dev_config *config)
1607 {
1608         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1609                 /* Application defines size of inlined data explicitly. */
1610                 switch (spawn->pci_dev->id.device_id) {
1611                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1612                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1613                         if (config->txq_inline_min <
1614                                        (int)MLX5_INLINE_HSIZE_L2) {
1615                                 DRV_LOG(DEBUG,
1616                                         "txq_inline_mix aligned to minimal"
1617                                         " ConnectX-4 required value %d",
1618                                         (int)MLX5_INLINE_HSIZE_L2);
1619                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1620                         }
1621                         break;
1622                 }
1623                 goto exit;
1624         }
1625         if (config->hca_attr.eth_net_offloads) {
1626                 /* We have DevX enabled, inline mode queried successfully. */
1627                 switch (config->hca_attr.wqe_inline_mode) {
1628                 case MLX5_CAP_INLINE_MODE_L2:
1629                         /* outer L2 header must be inlined. */
1630                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1631                         goto exit;
1632                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1633                         /* No inline data are required by NIC. */
1634                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1635                         config->hw_vlan_insert =
1636                                 config->hca_attr.wqe_vlan_insert;
1637                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1638                         goto exit;
1639                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1640                         /* inline mode is defined by NIC vport context. */
1641                         if (!config->hca_attr.eth_virt)
1642                                 break;
1643                         switch (config->hca_attr.vport_inline_mode) {
1644                         case MLX5_INLINE_MODE_NONE:
1645                                 config->txq_inline_min =
1646                                         MLX5_INLINE_HSIZE_NONE;
1647                                 goto exit;
1648                         case MLX5_INLINE_MODE_L2:
1649                                 config->txq_inline_min =
1650                                         MLX5_INLINE_HSIZE_L2;
1651                                 goto exit;
1652                         case MLX5_INLINE_MODE_IP:
1653                                 config->txq_inline_min =
1654                                         MLX5_INLINE_HSIZE_L3;
1655                                 goto exit;
1656                         case MLX5_INLINE_MODE_TCP_UDP:
1657                                 config->txq_inline_min =
1658                                         MLX5_INLINE_HSIZE_L4;
1659                                 goto exit;
1660                         case MLX5_INLINE_MODE_INNER_L2:
1661                                 config->txq_inline_min =
1662                                         MLX5_INLINE_HSIZE_INNER_L2;
1663                                 goto exit;
1664                         case MLX5_INLINE_MODE_INNER_IP:
1665                                 config->txq_inline_min =
1666                                         MLX5_INLINE_HSIZE_INNER_L3;
1667                                 goto exit;
1668                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
1669                                 config->txq_inline_min =
1670                                         MLX5_INLINE_HSIZE_INNER_L4;
1671                                 goto exit;
1672                         }
1673                 }
1674         }
1675         /*
1676          * We get here if we are unable to deduce
1677          * inline data size with DevX. Try PCI ID
1678          * to determine old NICs.
1679          */
1680         switch (spawn->pci_dev->id.device_id) {
1681         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1682         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1683         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1684         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1685                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1686                 config->hw_vlan_insert = 0;
1687                 break;
1688         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1689         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1690         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1691         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1692                 /*
1693                  * These NICs support VLAN insertion from WQE and
1694                  * report the wqe_vlan_insert flag. But there is the bug
1695                  * and PFC control may be broken, so disable feature.
1696                  */
1697                 config->hw_vlan_insert = 0;
1698                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1699                 break;
1700         default:
1701                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1702                 break;
1703         }
1704 exit:
1705         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1706 }
1707
1708 /**
1709  * Configures the metadata mask fields in the shared context.
1710  *
1711  * @param [in] dev
1712  *   Pointer to Ethernet device.
1713  */
1714 void
1715 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1716 {
1717         struct mlx5_priv *priv = dev->data->dev_private;
1718         struct mlx5_dev_ctx_shared *sh = priv->sh;
1719         uint32_t meta, mark, reg_c0;
1720
1721         reg_c0 = ~priv->vport_meta_mask;
1722         switch (priv->config.dv_xmeta_en) {
1723         case MLX5_XMETA_MODE_LEGACY:
1724                 meta = UINT32_MAX;
1725                 mark = MLX5_FLOW_MARK_MASK;
1726                 break;
1727         case MLX5_XMETA_MODE_META16:
1728                 meta = reg_c0 >> rte_bsf32(reg_c0);
1729                 mark = MLX5_FLOW_MARK_MASK;
1730                 break;
1731         case MLX5_XMETA_MODE_META32:
1732                 meta = UINT32_MAX;
1733                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1734                 break;
1735         default:
1736                 meta = 0;
1737                 mark = 0;
1738                 MLX5_ASSERT(false);
1739                 break;
1740         }
1741         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1742                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1743                                  sh->dv_mark_mask, mark);
1744         else
1745                 sh->dv_mark_mask = mark;
1746         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1747                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1748                                  sh->dv_meta_mask, meta);
1749         else
1750                 sh->dv_meta_mask = meta;
1751         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1752                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1753                                  sh->dv_meta_mask, reg_c0);
1754         else
1755                 sh->dv_regc0_mask = reg_c0;
1756         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1757         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1758         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1759         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1760 }
1761
1762 int
1763 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1764 {
1765         static const char *const dynf_names[] = {
1766                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1767                 RTE_MBUF_DYNFLAG_METADATA_NAME,
1768                 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
1769         };
1770         unsigned int i;
1771
1772         if (n < RTE_DIM(dynf_names))
1773                 return -ENOMEM;
1774         for (i = 0; i < RTE_DIM(dynf_names); i++) {
1775                 if (names[i] == NULL)
1776                         return -EINVAL;
1777                 strcpy(names[i], dynf_names[i]);
1778         }
1779         return RTE_DIM(dynf_names);
1780 }
1781
1782 /**
1783  * Comparison callback to sort device data.
1784  *
1785  * This is meant to be used with qsort().
1786  *
1787  * @param a[in]
1788  *   Pointer to pointer to first data object.
1789  * @param b[in]
1790  *   Pointer to pointer to second data object.
1791  *
1792  * @return
1793  *   0 if both objects are equal, less than 0 if the first argument is less
1794  *   than the second, greater than 0 otherwise.
1795  */
1796 int
1797 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1798                               struct mlx5_dev_config *config)
1799 {
1800         struct mlx5_dev_ctx_shared *sh = priv->sh;
1801         struct mlx5_dev_config *sh_conf = NULL;
1802         uint16_t port_id;
1803
1804         MLX5_ASSERT(sh);
1805         /* Nothing to compare for the single/first device. */
1806         if (sh->refcnt == 1)
1807                 return 0;
1808         /* Find the device with shared context. */
1809         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1810                 struct mlx5_priv *opriv =
1811                         rte_eth_devices[port_id].data->dev_private;
1812
1813                 if (opriv && opriv != priv && opriv->sh == sh) {
1814                         sh_conf = &opriv->config;
1815                         break;
1816                 }
1817         }
1818         if (!sh_conf)
1819                 return 0;
1820         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1821                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1822                              " for shared %s context", sh->ibdev_name);
1823                 rte_errno = EINVAL;
1824                 return rte_errno;
1825         }
1826         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1827                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1828                              " for shared %s context", sh->ibdev_name);
1829                 rte_errno = EINVAL;
1830                 return rte_errno;
1831         }
1832         return 0;
1833 }
1834
1835 /**
1836  * Look for the ethernet device belonging to mlx5 driver.
1837  *
1838  * @param[in] port_id
1839  *   port_id to start looking for device.
1840  * @param[in] pci_dev
1841  *   Pointer to the hint PCI device. When device is being probed
1842  *   the its siblings (master and preceding representors might
1843  *   not have assigned driver yet (because the mlx5_os_pci_probe()
1844  *   is not completed yet, for this case match on hint PCI
1845  *   device may be used to detect sibling device.
1846  *
1847  * @return
1848  *   port_id of found device, RTE_MAX_ETHPORT if not found.
1849  */
1850 uint16_t
1851 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
1852 {
1853         while (port_id < RTE_MAX_ETHPORTS) {
1854                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
1855
1856                 if (dev->state != RTE_ETH_DEV_UNUSED &&
1857                     dev->device &&
1858                     (dev->device == &pci_dev->device ||
1859                      (dev->device->driver &&
1860                      dev->device->driver->name &&
1861                      !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
1862                         break;
1863                 port_id++;
1864         }
1865         if (port_id >= RTE_MAX_ETHPORTS)
1866                 return RTE_MAX_ETHPORTS;
1867         return port_id;
1868 }
1869
1870 /**
1871  * DPDK callback to remove a PCI device.
1872  *
1873  * This function removes all Ethernet devices belong to a given PCI device.
1874  *
1875  * @param[in] pci_dev
1876  *   Pointer to the PCI device.
1877  *
1878  * @return
1879  *   0 on success, the function cannot fail.
1880  */
1881 static int
1882 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1883 {
1884         uint16_t port_id;
1885
1886         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
1887                 /*
1888                  * mlx5_dev_close() is not registered to secondary process,
1889                  * call the close function explicitly for secondary process.
1890                  */
1891                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
1892                         mlx5_dev_close(&rte_eth_devices[port_id]);
1893                 else
1894                         rte_eth_dev_close(port_id);
1895         }
1896         return 0;
1897 }
1898
1899 static const struct rte_pci_id mlx5_pci_id_map[] = {
1900         {
1901                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1902                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1903         },
1904         {
1905                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1906                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1907         },
1908         {
1909                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1910                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1911         },
1912         {
1913                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1914                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1915         },
1916         {
1917                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1918                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1919         },
1920         {
1921                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1922                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1923         },
1924         {
1925                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1926                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1927         },
1928         {
1929                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1930                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1931         },
1932         {
1933                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1934                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
1935         },
1936         {
1937                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1938                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
1939         },
1940         {
1941                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1942                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
1943         },
1944         {
1945                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1946                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
1947         },
1948         {
1949                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1950                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
1951         },
1952         {
1953                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1954                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
1955         },
1956         {
1957                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1958                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
1959         },
1960         {
1961                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1962                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
1963         },
1964         {
1965                 .vendor_id = 0
1966         }
1967 };
1968
1969 static struct mlx5_pci_driver mlx5_driver = {
1970         .driver_class = MLX5_CLASS_NET,
1971         .pci_driver = {
1972                 .driver = {
1973                         .name = MLX5_DRIVER_NAME,
1974                 },
1975                 .id_table = mlx5_pci_id_map,
1976                 .probe = mlx5_os_pci_probe,
1977                 .remove = mlx5_pci_remove,
1978                 .dma_map = mlx5_dma_map,
1979                 .dma_unmap = mlx5_dma_unmap,
1980                 .drv_flags = PCI_DRV_FLAGS,
1981         },
1982 };
1983
1984 /* Initialize driver log type. */
1985 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
1986
1987 /**
1988  * Driver initialization routine.
1989  */
1990 RTE_INIT(rte_mlx5_pmd_init)
1991 {
1992         mlx5_common_init();
1993         /* Build the static tables for Verbs conversion. */
1994         mlx5_set_ptype_table();
1995         mlx5_set_cksum_table();
1996         mlx5_set_swp_types_table();
1997         if (mlx5_glue)
1998                 mlx5_pci_driver_register(&mlx5_driver);
1999 }
2000
2001 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2002 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2003 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");