drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <assert.h>
  10 #include <dlfcn.h>
  11 #include <stdint.h>
  12 #include <stdlib.h>
  13 #include <errno.h>
  14 #include <net/if.h>
  15 #include <sys/mman.h>
  16 #include <linux/rtnetlink.h>
  17
  18 /* Verbs header. */
  19 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  20 #ifdef PEDANTIC
  21 #pragma GCC diagnostic ignored "-Wpedantic"
  22 #endif
  23 #include <infiniband/verbs.h>
  24 #ifdef PEDANTIC
  25 #pragma GCC diagnostic error "-Wpedantic"
  26 #endif
  27
  28 #include <rte_malloc.h>
  29 #include <rte_ethdev_driver.h>
  30 #include <rte_ethdev_pci.h>
  31 #include <rte_pci.h>
  32 #include <rte_bus_pci.h>
  33 #include <rte_common.h>
  34 #include <rte_config.h>
  35 #include <rte_eal_memconfig.h>
  36 #include <rte_kvargs.h>
  37 #include <rte_rwlock.h>
  38 #include <rte_spinlock.h>
  39 #include <rte_string_fns.h>
  40
  41 #include "mlx5.h"
  42 #include "mlx5_utils.h"
  43 #include "mlx5_rxtx.h"
  44 #include "mlx5_autoconf.h"
  45 #include "mlx5_defs.h"
  46 #include "mlx5_glue.h"
  47 #include "mlx5_mr.h"
  48 #include "mlx5_flow.h"
  49
  50 /* Device parameter to enable RX completion queue compression. */
  51 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  52
  53 /* Device parameter to enable RX completion entry padding to 128B. */
  54 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
  55
  56 /* Device parameter to enable padding Rx packet to cacheline size. */
  57 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  58
  59 /* Device parameter to enable Multi-Packet Rx queue. */
  60 #define MLX5_RX_MPRQ_EN "mprq_en"
  61
  62 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  63 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  64
  65 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  66 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  67
  68 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  69 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  70
  71 /* Device parameter to configure inline send. */
  72 #define MLX5_TXQ_INLINE "txq_inline"
  73
  74 /*
  75  * Device parameter to configure the number of TX queues threshold for
  76  * enabling inline send.
  77  */
  78 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  79
  80 /*
  81  * Device parameter to configure the number of TX queues threshold for
  82  * enabling vectorized Tx.
  83  */
  84 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  85
  86 /* Device parameter to enable multi-packet send WQEs. */
  87 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  88
  89 /* Device parameter to include 2 dsegs in the title WQEBB. */
  90 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
  91
  92 /* Device parameter to limit the size of inlining packet. */
  93 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
  94
  95 /* Device parameter to enable hardware Tx vector. */
  96 #define MLX5_TX_VEC_EN "tx_vec_en"
  97
  98 /* Device parameter to enable hardware Rx vector. */
  99 #define MLX5_RX_VEC_EN "rx_vec_en"
 100
 101 /* Allow L3 VXLAN flow creation. */
 102 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 103
 104 /* Activate DV flow steering. */
 105 #define MLX5_DV_FLOW_EN "dv_flow_en"
 106
 107 /* Activate Netlink support in VF mode. */
 108 #define MLX5_VF_NL_EN "vf_nl_en"
 109
 110 /* Select port representors to instantiate. */
 111 #define MLX5_REPRESENTOR "representor"
 112
 113 #ifndef HAVE_IBV_MLX5_MOD_MPW
 114 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
 115 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
 116 #endif
 117
 118 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
 119 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
 120 #endif
 121
 122 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
 123
 124 /* Shared memory between primary and secondary processes. */
 125 struct mlx5_shared_data *mlx5_shared_data;
 126
 127 /* Spinlock for mlx5_shared_data allocation. */
 128 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
 129
 130 /** Driver-specific log messages type. */
 131 int mlx5_logtype;
 132
 133 /** Data associated with devices to spawn. */
 134 struct mlx5_dev_spawn_data {
 135         uint32_t ifindex; /**< Network interface index. */
 136         uint32_t max_port; /**< IB device maximal port index. */
 137         uint32_t ibv_port; /**< IB device physical port index. */
 138         struct mlx5_switch_info info; /**< Switch information. */
 139         struct ibv_device *ibv_dev; /**< Associated IB device. */
 140         struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
 141 };
 142
 143 static LIST_HEAD(, mlx5_ibv_shared) mlx5_ibv_list = LIST_HEAD_INITIALIZER();
 144 static pthread_mutex_t mlx5_ibv_list_mutex = PTHREAD_MUTEX_INITIALIZER;
 145
 146 /**
 147  * Allocate shared IB device context. If there is multiport device the
 148  * master and representors will share this context, if there is single
 149  * port dedicated IB device, the context will be used by only given
 150  * port due to unification.
 151  *
 152  * Routine first searches the context for the spesified IB device name,
 153  * if found the shared context assumed and reference counter is incremented.
 154  * If no context found the new one is created and initialized with specified
 155  * IB device context and parameters.
 156  *
 157  * @param[in] spawn
 158  *   Pointer to the IB device attributes (name, port, etc).
 159  *
 160  * @return
 161  *   Pointer to mlx5_ibv_shared object on success,
 162  *   otherwise NULL and rte_errno is set.
 163  */
 164 static struct mlx5_ibv_shared *
 165 mlx5_alloc_shared_ibctx(const struct mlx5_dev_spawn_data *spawn)
 166 {
 167         struct mlx5_ibv_shared *sh;
 168         int err = 0;
 169         uint32_t i;
 170
 171         assert(spawn);
 172         /* Secondary process should not create the shared context. */
 173         assert(rte_eal_process_type() == RTE_PROC_PRIMARY);
 174         pthread_mutex_lock(&mlx5_ibv_list_mutex);
 175         /* Search for IB context by device name. */
 176         LIST_FOREACH(sh, &mlx5_ibv_list, next) {
 177                 if (!strcmp(sh->ibdev_name, spawn->ibv_dev->name)) {
 178                         sh->refcnt++;
 179                         goto exit;
 180                 }
 181         }
 182         /* No device found, we have to create new sharted context. */
 183         assert(spawn->max_port);
 184         sh = rte_zmalloc("ethdev shared ib context",
 185                          sizeof(struct mlx5_ibv_shared) +
 186                          spawn->max_port *
 187                          sizeof(struct mlx5_ibv_shared_port),
 188                          RTE_CACHE_LINE_SIZE);
 189         if (!sh) {
 190                 DRV_LOG(ERR, "shared context allocation failure");
 191                 rte_errno  = ENOMEM;
 192                 goto exit;
 193         }
 194         /* Try to open IB device with DV first, then usual Verbs. */
 195         errno = 0;
 196         sh->ctx = mlx5_glue->dv_open_device(spawn->ibv_dev);
 197         if (sh->ctx) {
 198                 sh->devx = 1;
 199                 DRV_LOG(DEBUG, "DevX is supported");
 200         } else {
 201                 sh->ctx = mlx5_glue->open_device(spawn->ibv_dev);
 202                 if (!sh->ctx) {
 203                         err = errno ? errno : ENODEV;
 204                         goto error;
 205                 }
 206                 DRV_LOG(DEBUG, "DevX is NOT supported");
 207         }
 208         err = mlx5_glue->query_device_ex(sh->ctx, NULL, &sh->device_attr);
 209         if (err) {
 210                 DRV_LOG(DEBUG, "ibv_query_device_ex() failed");
 211                 goto error;
 212         }
 213         sh->refcnt = 1;
 214         sh->max_port = spawn->max_port;
 215         strncpy(sh->ibdev_name, sh->ctx->device->name,
 216                 sizeof(sh->ibdev_name));
 217         strncpy(sh->ibdev_path, sh->ctx->device->ibdev_path,
 218                 sizeof(sh->ibdev_path));
 219         pthread_mutex_init(&sh->intr_mutex, NULL);
 220         /*
 221          * Setting port_id to max unallowed value means
 222          * there is no interrupt subhandler installed for
 223          * the given port index i.
 224          */
 225         for (i = 0; i < sh->max_port; i++)
 226                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 227         sh->pd = mlx5_glue->alloc_pd(sh->ctx);
 228         if (sh->pd == NULL) {
 229                 DRV_LOG(ERR, "PD allocation failure");
 230                 err = ENOMEM;
 231                 goto error;
 232         }
 233         LIST_INSERT_HEAD(&mlx5_ibv_list, sh, next);
 234 exit:
 235         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 236         return sh;
 237 error:
 238         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 239         assert(sh);
 240         if (sh->pd)
 241                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 242         if (sh->ctx)
 243                 claim_zero(mlx5_glue->close_device(sh->ctx));
 244         rte_free(sh);
 245         assert(err > 0);
 246         rte_errno = err;
 247         return NULL;
 248 }
 249
 250 /**
 251  * Free shared IB device context. Decrement counter and if zero free
 252  * all allocated resources and close handles.
 253  *
 254  * @param[in] sh
 255  *   Pointer to mlx5_ibv_shared object to free
 256  */
 257 static void
 258 mlx5_free_shared_ibctx(struct mlx5_ibv_shared *sh)
 259 {
 260         pthread_mutex_lock(&mlx5_ibv_list_mutex);
 261 #ifndef NDEBUG
 262         /* Check the object presence in the list. */
 263         struct mlx5_ibv_shared *lctx;
 264
 265         LIST_FOREACH(lctx, &mlx5_ibv_list, next)
 266                 if (lctx == sh)
 267                         break;
 268         assert(lctx);
 269         if (lctx != sh) {
 270                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
 271                 goto exit;
 272         }
 273 #endif
 274         assert(sh);
 275         assert(sh->refcnt);
 276         /* Secondary process should not free the shared context. */
 277         assert(rte_eal_process_type() == RTE_PROC_PRIMARY);
 278         if (--sh->refcnt)
 279                 goto exit;
 280         LIST_REMOVE(sh, next);
 281         /*
 282          *  Ensure there is no async event handler installed.
 283          *  Only primary process handles async device events.
 284          **/
 285         assert(!sh->intr_cnt);
 286         if (sh->intr_cnt)
 287                 rte_intr_callback_unregister
 288                         (&sh->intr_handle, mlx5_dev_interrupt_handler, sh);
 289         pthread_mutex_destroy(&sh->intr_mutex);
 290         if (sh->pd)
 291                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 292         if (sh->ctx)
 293                 claim_zero(mlx5_glue->close_device(sh->ctx));
 294         rte_free(sh);
 295 exit:
 296         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 297 }
 298
 299 /**
 300  * Prepare shared data between primary and secondary process.
 301  */
 302 static void
 303 mlx5_prepare_shared_data(void)
 304 {
 305         const struct rte_memzone *mz;
 306
 307         rte_spinlock_lock(&mlx5_shared_data_lock);
 308         if (mlx5_shared_data == NULL) {
 309                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
 310                         /* Allocate shared memory. */
 311                         mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
 312                                                  sizeof(*mlx5_shared_data),
 313                                                  SOCKET_ID_ANY, 0);
 314                 } else {
 315                         /* Lookup allocated shared memory. */
 316                         mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
 317                 }
 318                 if (mz == NULL)
 319                         rte_panic("Cannot allocate mlx5 shared data\n");
 320                 mlx5_shared_data = mz->addr;
 321                 /* Initialize shared data. */
 322                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
 323                         LIST_INIT(&mlx5_shared_data->mem_event_cb_list);
 324                         rte_rwlock_init(&mlx5_shared_data->mem_event_rwlock);
 325                         rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
 326                                                         mlx5_mr_mem_event_cb,
 327                                                         NULL);
 328                 }
 329         }
 330         rte_spinlock_unlock(&mlx5_shared_data_lock);
 331 }
 332
 333 /**
 334  * Retrieve integer value from environment variable.
 335  *
 336  * @param[in] name
 337  *   Environment variable name.
 338  *
 339  * @return
 340  *   Integer value, 0 if the variable is not set.
 341  */
 342 int
 343 mlx5_getenv_int(const char *name)
 344 {
 345         const char *val = getenv(name);
 346
 347         if (val == NULL)
 348                 return 0;
 349         return atoi(val);
 350 }
 351
 352 /**
 353  * Verbs callback to allocate a memory. This function should allocate the space
 354  * according to the size provided residing inside a huge page.
 355  * Please note that all allocation must respect the alignment from libmlx5
 356  * (i.e. currently sysconf(_SC_PAGESIZE)).
 357  *
 358  * @param[in] size
 359  *   The size in bytes of the memory to allocate.
 360  * @param[in] data
 361  *   A pointer to the callback data.
 362  *
 363  * @return
 364  *   Allocated buffer, NULL otherwise and rte_errno is set.
 365  */
 366 static void *
 367 mlx5_alloc_verbs_buf(size_t size, void *data)
 368 {
 369         struct mlx5_priv *priv = data;
 370         void *ret;
 371         size_t alignment = sysconf(_SC_PAGESIZE);
 372         unsigned int socket = SOCKET_ID_ANY;
 373
 374         if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
 375                 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
 376
 377                 socket = ctrl->socket;
 378         } else if (priv->verbs_alloc_ctx.type ==
 379                    MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
 380                 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
 381
 382                 socket = ctrl->socket;
 383         }
 384         assert(data != NULL);
 385         ret = rte_malloc_socket(__func__, size, alignment, socket);
 386         if (!ret && size)
 387                 rte_errno = ENOMEM;
 388         return ret;
 389 }
 390
 391 /**
 392  * Verbs callback to free a memory.
 393  *
 394  * @param[in] ptr
 395  *   A pointer to the memory to free.
 396  * @param[in] data
 397  *   A pointer to the callback data.
 398  */
 399 static void
 400 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
 401 {
 402         assert(data != NULL);
 403         rte_free(ptr);
 404 }
 405
 406 /**
 407  * DPDK callback to close the device.
 408  *
 409  * Destroy all queues and objects, free memory.
 410  *
 411  * @param dev
 412  *   Pointer to Ethernet device structure.
 413  */
 414 static void
 415 mlx5_dev_close(struct rte_eth_dev *dev)
 416 {
 417         struct mlx5_priv *priv = dev->data->dev_private;
 418         unsigned int i;
 419         int ret;
 420
 421         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
 422                 dev->data->port_id,
 423                 ((priv->sh->ctx != NULL) ? priv->sh->ctx->device->name : ""));
 424         /* In case mlx5_dev_stop() has not been called. */
 425         mlx5_dev_interrupt_handler_uninstall(dev);
 426         mlx5_traffic_disable(dev);
 427         mlx5_flow_flush(dev, NULL);
 428         /* Prevent crashes when queues are still in use. */
 429         dev->rx_pkt_burst = removed_rx_burst;
 430         dev->tx_pkt_burst = removed_tx_burst;
 431         if (priv->rxqs != NULL) {
 432                 /* XXX race condition if mlx5_rx_burst() is still running. */
 433                 usleep(1000);
 434                 for (i = 0; (i != priv->rxqs_n); ++i)
 435                         mlx5_rxq_release(dev, i);
 436                 priv->rxqs_n = 0;
 437                 priv->rxqs = NULL;
 438         }
 439         if (priv->txqs != NULL) {
 440                 /* XXX race condition if mlx5_tx_burst() is still running. */
 441                 usleep(1000);
 442                 for (i = 0; (i != priv->txqs_n); ++i)
 443                         mlx5_txq_release(dev, i);
 444                 priv->txqs_n = 0;
 445                 priv->txqs = NULL;
 446         }
 447         mlx5_mprq_free_mp(dev);
 448         mlx5_mr_release(dev);
 449         assert(priv->sh);
 450         if (priv->sh)
 451                 mlx5_free_shared_ibctx(priv->sh);
 452         priv->sh = NULL;
 453         if (priv->rss_conf.rss_key != NULL)
 454                 rte_free(priv->rss_conf.rss_key);
 455         if (priv->reta_idx != NULL)
 456                 rte_free(priv->reta_idx);
 457         if (priv->primary_socket)
 458                 mlx5_socket_uninit(dev);
 459         if (priv->config.vf)
 460                 mlx5_nl_mac_addr_flush(dev);
 461         if (priv->nl_socket_route >= 0)
 462                 close(priv->nl_socket_route);
 463         if (priv->nl_socket_rdma >= 0)
 464                 close(priv->nl_socket_rdma);
 465         if (priv->tcf_context)
 466                 mlx5_flow_tcf_context_destroy(priv->tcf_context);
 467         ret = mlx5_hrxq_ibv_verify(dev);
 468         if (ret)
 469                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
 470                         dev->data->port_id);
 471         ret = mlx5_ind_table_ibv_verify(dev);
 472         if (ret)
 473                 DRV_LOG(WARNING, "port %u some indirection table still remain",
 474                         dev->data->port_id);
 475         ret = mlx5_rxq_ibv_verify(dev);
 476         if (ret)
 477                 DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain",
 478                         dev->data->port_id);
 479         ret = mlx5_rxq_verify(dev);
 480         if (ret)
 481                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
 482                         dev->data->port_id);
 483         ret = mlx5_txq_ibv_verify(dev);
 484         if (ret)
 485                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
 486                         dev->data->port_id);
 487         ret = mlx5_txq_verify(dev);
 488         if (ret)
 489                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
 490                         dev->data->port_id);
 491         ret = mlx5_flow_verify(dev);
 492         if (ret)
 493                 DRV_LOG(WARNING, "port %u some flows still remain",
 494                         dev->data->port_id);
 495         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
 496                 unsigned int c = 0;
 497                 unsigned int i = mlx5_dev_to_port_id(dev->device, NULL, 0);
 498                 uint16_t port_id[i];
 499
 500                 i = RTE_MIN(mlx5_dev_to_port_id(dev->device, port_id, i), i);
 501                 while (i--) {
 502                         struct mlx5_priv *opriv =
 503                                 rte_eth_devices[port_id[i]].data->dev_private;
 504
 505                         if (!opriv ||
 506                             opriv->domain_id != priv->domain_id ||
 507                             &rte_eth_devices[port_id[i]] == dev)
 508                                 continue;
 509                         ++c;
 510                 }
 511                 if (!c)
 512                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
 513         }
 514         memset(priv, 0, sizeof(*priv));
 515         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
 516         /*
 517          * Reset mac_addrs to NULL such that it is not freed as part of
 518          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
 519          * it is freed when dev_private is freed.
 520          */
 521         dev->data->mac_addrs = NULL;
 522 }
 523
 524 const struct eth_dev_ops mlx5_dev_ops = {
 525         .dev_configure = mlx5_dev_configure,
 526         .dev_start = mlx5_dev_start,
 527         .dev_stop = mlx5_dev_stop,
 528         .dev_set_link_down = mlx5_set_link_down,
 529         .dev_set_link_up = mlx5_set_link_up,
 530         .dev_close = mlx5_dev_close,
 531         .promiscuous_enable = mlx5_promiscuous_enable,
 532         .promiscuous_disable = mlx5_promiscuous_disable,
 533         .allmulticast_enable = mlx5_allmulticast_enable,
 534         .allmulticast_disable = mlx5_allmulticast_disable,
 535         .link_update = mlx5_link_update,
 536         .stats_get = mlx5_stats_get,
 537         .stats_reset = mlx5_stats_reset,
 538         .xstats_get = mlx5_xstats_get,
 539         .xstats_reset = mlx5_xstats_reset,
 540         .xstats_get_names = mlx5_xstats_get_names,
 541         .fw_version_get = mlx5_fw_version_get,
 542         .dev_infos_get = mlx5_dev_infos_get,
 543         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
 544         .vlan_filter_set = mlx5_vlan_filter_set,
 545         .rx_queue_setup = mlx5_rx_queue_setup,
 546         .tx_queue_setup = mlx5_tx_queue_setup,
 547         .rx_queue_release = mlx5_rx_queue_release,
 548         .tx_queue_release = mlx5_tx_queue_release,
 549         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
 550         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
 551         .mac_addr_remove = mlx5_mac_addr_remove,
 552         .mac_addr_add = mlx5_mac_addr_add,
 553         .mac_addr_set = mlx5_mac_addr_set,
 554         .set_mc_addr_list = mlx5_set_mc_addr_list,
 555         .mtu_set = mlx5_dev_set_mtu,
 556         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
 557         .vlan_offload_set = mlx5_vlan_offload_set,
 558         .reta_update = mlx5_dev_rss_reta_update,
 559         .reta_query = mlx5_dev_rss_reta_query,
 560         .rss_hash_update = mlx5_rss_hash_update,
 561         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
 562         .filter_ctrl = mlx5_dev_filter_ctrl,
 563         .rx_descriptor_status = mlx5_rx_descriptor_status,
 564         .tx_descriptor_status = mlx5_tx_descriptor_status,
 565         .rx_queue_count = mlx5_rx_queue_count,
 566         .rx_queue_intr_enable = mlx5_rx_intr_enable,
 567         .rx_queue_intr_disable = mlx5_rx_intr_disable,
 568         .is_removed = mlx5_is_removed,
 569 };
 570
 571 /* Available operations from secondary process. */
 572 static const struct eth_dev_ops mlx5_dev_sec_ops = {
 573         .stats_get = mlx5_stats_get,
 574         .stats_reset = mlx5_stats_reset,
 575         .xstats_get = mlx5_xstats_get,
 576         .xstats_reset = mlx5_xstats_reset,
 577         .xstats_get_names = mlx5_xstats_get_names,
 578         .fw_version_get = mlx5_fw_version_get,
 579         .dev_infos_get = mlx5_dev_infos_get,
 580         .rx_descriptor_status = mlx5_rx_descriptor_status,
 581         .tx_descriptor_status = mlx5_tx_descriptor_status,
 582 };
 583
 584 /* Available operations in flow isolated mode. */
 585 const struct eth_dev_ops mlx5_dev_ops_isolate = {
 586         .dev_configure = mlx5_dev_configure,
 587         .dev_start = mlx5_dev_start,
 588         .dev_stop = mlx5_dev_stop,
 589         .dev_set_link_down = mlx5_set_link_down,
 590         .dev_set_link_up = mlx5_set_link_up,
 591         .dev_close = mlx5_dev_close,
 592         .promiscuous_enable = mlx5_promiscuous_enable,
 593         .promiscuous_disable = mlx5_promiscuous_disable,
 594         .allmulticast_enable = mlx5_allmulticast_enable,
 595         .allmulticast_disable = mlx5_allmulticast_disable,
 596         .link_update = mlx5_link_update,
 597         .stats_get = mlx5_stats_get,
 598         .stats_reset = mlx5_stats_reset,
 599         .xstats_get = mlx5_xstats_get,
 600         .xstats_reset = mlx5_xstats_reset,
 601         .xstats_get_names = mlx5_xstats_get_names,
 602         .fw_version_get = mlx5_fw_version_get,
 603         .dev_infos_get = mlx5_dev_infos_get,
 604         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
 605         .vlan_filter_set = mlx5_vlan_filter_set,
 606         .rx_queue_setup = mlx5_rx_queue_setup,
 607         .tx_queue_setup = mlx5_tx_queue_setup,
 608         .rx_queue_release = mlx5_rx_queue_release,
 609         .tx_queue_release = mlx5_tx_queue_release,
 610         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
 611         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
 612         .mac_addr_remove = mlx5_mac_addr_remove,
 613         .mac_addr_add = mlx5_mac_addr_add,
 614         .mac_addr_set = mlx5_mac_addr_set,
 615         .set_mc_addr_list = mlx5_set_mc_addr_list,
 616         .mtu_set = mlx5_dev_set_mtu,
 617         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
 618         .vlan_offload_set = mlx5_vlan_offload_set,
 619         .filter_ctrl = mlx5_dev_filter_ctrl,
 620         .rx_descriptor_status = mlx5_rx_descriptor_status,
 621         .tx_descriptor_status = mlx5_tx_descriptor_status,
 622         .rx_queue_intr_enable = mlx5_rx_intr_enable,
 623         .rx_queue_intr_disable = mlx5_rx_intr_disable,
 624         .is_removed = mlx5_is_removed,
 625 };
 626
 627 /**
 628  * Verify and store value for device argument.
 629  *
 630  * @param[in] key
 631  *   Key argument to verify.
 632  * @param[in] val
 633  *   Value associated with key.
 634  * @param opaque
 635  *   User data.
 636  *
 637  * @return
 638  *   0 on success, a negative errno value otherwise and rte_errno is set.
 639  */
 640 static int
 641 mlx5_args_check(const char *key, const char *val, void *opaque)
 642 {
 643         struct mlx5_dev_config *config = opaque;
 644         unsigned long tmp;
 645
 646         /* No-op, port representors are processed in mlx5_dev_spawn(). */
 647         if (!strcmp(MLX5_REPRESENTOR, key))
 648                 return 0;
 649         errno = 0;
 650         tmp = strtoul(val, NULL, 0);
 651         if (errno) {
 652                 rte_errno = errno;
 653                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
 654                 return -rte_errno;
 655         }
 656         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
 657                 config->cqe_comp = !!tmp;
 658         } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
 659                 config->cqe_pad = !!tmp;
 660         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
 661                 config->hw_padding = !!tmp;
 662         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
 663                 config->mprq.enabled = !!tmp;
 664         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
 665                 config->mprq.stride_num_n = tmp;
 666         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
 667                 config->mprq.max_memcpy_len = tmp;
 668         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
 669                 config->mprq.min_rxqs_num = tmp;
 670         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
 671                 config->txq_inline = tmp;
 672         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
 673                 config->txqs_inline = tmp;
 674         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
 675                 config->txqs_vec = tmp;
 676         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
 677                 config->mps = !!tmp;
 678         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
 679                 config->mpw_hdr_dseg = !!tmp;
 680         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
 681                 config->inline_max_packet_sz = tmp;
 682         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
 683                 config->tx_vec_en = !!tmp;
 684         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
 685                 config->rx_vec_en = !!tmp;
 686         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
 687                 config->l3_vxlan_en = !!tmp;
 688         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
 689                 config->vf_nl_en = !!tmp;
 690         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
 691                 config->dv_flow_en = !!tmp;
 692         } else {
 693                 DRV_LOG(WARNING, "%s: unknown parameter", key);
 694                 rte_errno = EINVAL;
 695                 return -rte_errno;
 696         }
 697         return 0;
 698 }
 699
 700 /**
 701  * Parse device parameters.
 702  *
 703  * @param config
 704  *   Pointer to device configuration structure.
 705  * @param devargs
 706  *   Device arguments structure.
 707  *
 708  * @return
 709  *   0 on success, a negative errno value otherwise and rte_errno is set.
 710  */
 711 static int
 712 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
 713 {
 714         const char **params = (const char *[]){
 715                 MLX5_RXQ_CQE_COMP_EN,
 716                 MLX5_RXQ_CQE_PAD_EN,
 717                 MLX5_RXQ_PKT_PAD_EN,
 718                 MLX5_RX_MPRQ_EN,
 719                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
 720                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
 721                 MLX5_RXQS_MIN_MPRQ,
 722                 MLX5_TXQ_INLINE,
 723                 MLX5_TXQS_MIN_INLINE,
 724                 MLX5_TXQS_MAX_VEC,
 725                 MLX5_TXQ_MPW_EN,
 726                 MLX5_TXQ_MPW_HDR_DSEG_EN,
 727                 MLX5_TXQ_MAX_INLINE_LEN,
 728                 MLX5_TX_VEC_EN,
 729                 MLX5_RX_VEC_EN,
 730                 MLX5_L3_VXLAN_EN,
 731                 MLX5_VF_NL_EN,
 732                 MLX5_DV_FLOW_EN,
 733                 MLX5_REPRESENTOR,
 734                 NULL,
 735         };
 736         struct rte_kvargs *kvlist;
 737         int ret = 0;
 738         int i;
 739
 740         if (devargs == NULL)
 741                 return 0;
 742         /* Following UGLY cast is done to pass checkpatch. */
 743         kvlist = rte_kvargs_parse(devargs->args, params);
 744         if (kvlist == NULL)
 745                 return 0;
 746         /* Process parameters. */
 747         for (i = 0; (params[i] != NULL); ++i) {
 748                 if (rte_kvargs_count(kvlist, params[i])) {
 749                         ret = rte_kvargs_process(kvlist, params[i],
 750                                                  mlx5_args_check, config);
 751                         if (ret) {
 752                                 rte_errno = EINVAL;
 753                                 rte_kvargs_free(kvlist);
 754                                 return -rte_errno;
 755                         }
 756                 }
 757         }
 758         rte_kvargs_free(kvlist);
 759         return 0;
 760 }
 761
 762 static struct rte_pci_driver mlx5_driver;
 763
 764 /*
 765  * Reserved UAR address space for TXQ UAR(hw doorbell) mapping, process
 766  * local resource used by both primary and secondary to avoid duplicate
 767  * reservation.
 768  * The space has to be available on both primary and secondary process,
 769  * TXQ UAR maps to this area using fixed mmap w/o double check.
 770  */
 771 static void *uar_base;
 772
 773 static int
 774 find_lower_va_bound(const struct rte_memseg_list *msl,
 775                 const struct rte_memseg *ms, void *arg)
 776 {
 777         void **addr = arg;
 778
 779         if (msl->external)
 780                 return 0;
 781         if (*addr == NULL)
 782                 *addr = ms->addr;
 783         else
 784                 *addr = RTE_MIN(*addr, ms->addr);
 785
 786         return 0;
 787 }
 788
 789 /**
 790  * Reserve UAR address space for primary process.
 791  *
 792  * @param[in] dev
 793  *   Pointer to Ethernet device.
 794  *
 795  * @return
 796  *   0 on success, a negative errno value otherwise and rte_errno is set.
 797  */
 798 static int
 799 mlx5_uar_init_primary(struct rte_eth_dev *dev)
 800 {
 801         struct mlx5_priv *priv = dev->data->dev_private;
 802         void *addr = (void *)0;
 803
 804         if (uar_base) { /* UAR address space mapped. */
 805                 priv->uar_base = uar_base;
 806                 return 0;
 807         }
 808         /* find out lower bound of hugepage segments */
 809         rte_memseg_walk(find_lower_va_bound, &addr);
 810
 811         /* keep distance to hugepages to minimize potential conflicts. */
 812         addr = RTE_PTR_SUB(addr, (uintptr_t)(MLX5_UAR_OFFSET + MLX5_UAR_SIZE));
 813         /* anonymous mmap, no real memory consumption. */
 814         addr = mmap(addr, MLX5_UAR_SIZE,
 815                     PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
 816         if (addr == MAP_FAILED) {
 817                 DRV_LOG(ERR,
 818                         "port %u failed to reserve UAR address space, please"
 819                         " adjust MLX5_UAR_SIZE or try --base-virtaddr",
 820                         dev->data->port_id);
 821                 rte_errno = ENOMEM;
 822                 return -rte_errno;
 823         }
 824         /* Accept either same addr or a new addr returned from mmap if target
 825          * range occupied.
 826          */
 827         DRV_LOG(INFO, "port %u reserved UAR address space: %p",
 828                 dev->data->port_id, addr);
 829         priv->uar_base = addr; /* for primary and secondary UAR re-mmap. */
 830         uar_base = addr; /* process local, don't reserve again. */
 831         return 0;
 832 }
 833
 834 /**
 835  * Reserve UAR address space for secondary process, align with
 836  * primary process.
 837  *
 838  * @param[in] dev
 839  *   Pointer to Ethernet device.
 840  *
 841  * @return
 842  *   0 on success, a negative errno value otherwise and rte_errno is set.
 843  */
 844 static int
 845 mlx5_uar_init_secondary(struct rte_eth_dev *dev)
 846 {
 847         struct mlx5_priv *priv = dev->data->dev_private;
 848         void *addr;
 849
 850         assert(priv->uar_base);
 851         if (uar_base) { /* already reserved. */
 852                 assert(uar_base == priv->uar_base);
 853                 return 0;
 854         }
 855         /* anonymous mmap, no real memory consumption. */
 856         addr = mmap(priv->uar_base, MLX5_UAR_SIZE,
 857                     PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
 858         if (addr == MAP_FAILED) {
 859                 DRV_LOG(ERR, "port %u UAR mmap failed: %p size: %llu",
 860                         dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
 861                 rte_errno = ENXIO;
 862                 return -rte_errno;
 863         }
 864         if (priv->uar_base != addr) {
 865                 DRV_LOG(ERR,
 866                         "port %u UAR address %p size %llu occupied, please"
 867                         " adjust MLX5_UAR_OFFSET or try EAL parameter"
 868                         " --base-virtaddr",
 869                         dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
 870                 rte_errno = ENXIO;
 871                 return -rte_errno;
 872         }
 873         uar_base = addr; /* process local, don't reserve again */
 874         DRV_LOG(INFO, "port %u reserved UAR address space: %p",
 875                 dev->data->port_id, addr);
 876         return 0;
 877 }
 878
 879 /**
 880  * Spawn an Ethernet device from Verbs information.
 881  *
 882  * @param dpdk_dev
 883  *   Backing DPDK device.
 884  * @param spawn
 885  *   Verbs device parameters (name, port, switch_info) to spawn.
 886  * @param config
 887  *   Device configuration parameters.
 888  *
 889  * @return
 890  *   A valid Ethernet device object on success, NULL otherwise and rte_errno
 891  *   is set. The following errors are defined:
 892  *
 893  *   EBUSY: device is not supposed to be spawned.
 894  *   EEXIST: device is already spawned
 895  */
 896 static struct rte_eth_dev *
 897 mlx5_dev_spawn(struct rte_device *dpdk_dev,
 898                struct mlx5_dev_spawn_data *spawn,
 899                struct mlx5_dev_config config)
 900 {
 901         const struct mlx5_switch_info *switch_info = &spawn->info;
 902         struct mlx5_ibv_shared *sh = NULL;
 903         struct ibv_port_attr port_attr;
 904         struct mlx5dv_context dv_attr = { .comp_mask = 0 };
 905         struct rte_eth_dev *eth_dev = NULL;
 906         struct mlx5_priv *priv = NULL;
 907         int err = 0;
 908         unsigned int hw_padding = 0;
 909         unsigned int mps;
 910         unsigned int cqe_comp;
 911         unsigned int cqe_pad = 0;
 912         unsigned int tunnel_en = 0;
 913         unsigned int mpls_en = 0;
 914         unsigned int swp = 0;
 915         unsigned int mprq = 0;
 916         unsigned int mprq_min_stride_size_n = 0;
 917         unsigned int mprq_max_stride_size_n = 0;
 918         unsigned int mprq_min_stride_num_n = 0;
 919         unsigned int mprq_max_stride_num_n = 0;
 920         struct ether_addr mac;
 921         char name[RTE_ETH_NAME_MAX_LEN];
 922         int own_domain_id = 0;
 923         uint16_t port_id;
 924         unsigned int i;
 925
 926         /* Determine if this port representor is supposed to be spawned. */
 927         if (switch_info->representor && dpdk_dev->devargs) {
 928                 struct rte_eth_devargs eth_da;
 929
 930                 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, &eth_da);
 931                 if (err) {
 932                         rte_errno = -err;
 933                         DRV_LOG(ERR, "failed to process device arguments: %s",
 934                                 strerror(rte_errno));
 935                         return NULL;
 936                 }
 937                 for (i = 0; i < eth_da.nb_representor_ports; ++i)
 938                         if (eth_da.representor_ports[i] ==
 939                             (uint16_t)switch_info->port_name)
 940                                 break;
 941                 if (i == eth_da.nb_representor_ports) {
 942                         rte_errno = EBUSY;
 943                         return NULL;
 944                 }
 945         }
 946         /* Build device name. */
 947         if (!switch_info->representor)
 948                 strlcpy(name, dpdk_dev->name, sizeof(name));
 949         else
 950                 snprintf(name, sizeof(name), "%s_representor_%u",
 951                          dpdk_dev->name, switch_info->port_name);
 952         /* check if the device is already spawned */
 953         if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
 954                 rte_errno = EEXIST;
 955                 return NULL;
 956         }
 957         /* Prepare shared data between primary and secondary process. */
 958         mlx5_prepare_shared_data();
 959         DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
 960         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
 961                 eth_dev = rte_eth_dev_attach_secondary(name);
 962                 if (eth_dev == NULL) {
 963                         DRV_LOG(ERR, "can not attach rte ethdev");
 964                         rte_errno = ENOMEM;
 965                         return NULL;
 966                 }
 967                 eth_dev->device = dpdk_dev;
 968                 eth_dev->dev_ops = &mlx5_dev_sec_ops;
 969                 err = mlx5_uar_init_secondary(eth_dev);
 970                 if (err)
 971                         return NULL;
 972                 /* Receive command fd from primary process */
 973                 err = mlx5_socket_connect(eth_dev);
 974                 if (err < 0)
 975                         return NULL;
 976                 /* Remap UAR for Tx queues. */
 977                 err = mlx5_tx_uar_remap(eth_dev, err);
 978                 if (err)
 979                         return NULL;
 980                 /*
 981                  * Ethdev pointer is still required as input since
 982                  * the primary device is not accessible from the
 983                  * secondary process.
 984                  */
 985                 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev);
 986                 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev);
 987                 return eth_dev;
 988         }
 989         sh = mlx5_alloc_shared_ibctx(spawn);
 990         if (!sh)
 991                 return NULL;
 992         config.devx = sh->devx;
 993 #ifdef HAVE_IBV_MLX5_MOD_SWP
 994         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
 995 #endif
 996         /*
 997          * Multi-packet send is supported by ConnectX-4 Lx PF as well
 998          * as all ConnectX-5 devices.
 999          */
1000 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
1001         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
1002 #endif
1003 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1004         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
1005 #endif
1006         mlx5_glue->dv_query_device(sh->ctx, &dv_attr);
1007         if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
1008                 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
1009                         DRV_LOG(DEBUG, "enhanced MPW is supported");
1010                         mps = MLX5_MPW_ENHANCED;
1011                 } else {
1012                         DRV_LOG(DEBUG, "MPW is supported");
1013                         mps = MLX5_MPW;
1014                 }
1015         } else {
1016                 DRV_LOG(DEBUG, "MPW isn't supported");
1017                 mps = MLX5_MPW_DISABLED;
1018         }
1019 #ifdef HAVE_IBV_MLX5_MOD_SWP
1020         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
1021                 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
1022         DRV_LOG(DEBUG, "SWP support: %u", swp);
1023 #endif
1024         config.swp = !!swp;
1025 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1026         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
1027                 struct mlx5dv_striding_rq_caps mprq_caps =
1028                         dv_attr.striding_rq_caps;
1029
1030                 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
1031                         mprq_caps.min_single_stride_log_num_of_bytes);
1032                 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
1033                         mprq_caps.max_single_stride_log_num_of_bytes);
1034                 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
1035                         mprq_caps.min_single_wqe_log_num_of_strides);
1036                 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
1037                         mprq_caps.max_single_wqe_log_num_of_strides);
1038                 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
1039                         mprq_caps.supported_qpts);
1040                 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
1041                 mprq = 1;
1042                 mprq_min_stride_size_n =
1043                         mprq_caps.min_single_stride_log_num_of_bytes;
1044                 mprq_max_stride_size_n =
1045                         mprq_caps.max_single_stride_log_num_of_bytes;
1046                 mprq_min_stride_num_n =
1047                         mprq_caps.min_single_wqe_log_num_of_strides;
1048                 mprq_max_stride_num_n =
1049                         mprq_caps.max_single_wqe_log_num_of_strides;
1050                 config.mprq.stride_num_n = RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
1051                                                    mprq_min_stride_num_n);
1052         }
1053 #endif
1054         if (RTE_CACHE_LINE_SIZE == 128 &&
1055             !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
1056                 cqe_comp = 0;
1057         else
1058                 cqe_comp = 1;
1059         config.cqe_comp = cqe_comp;
1060 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
1061         /* Whether device supports 128B Rx CQE padding. */
1062         cqe_pad = RTE_CACHE_LINE_SIZE == 128 &&
1063                   (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD);
1064 #endif
1065 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
1066         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
1067                 tunnel_en = ((dv_attr.tunnel_offloads_caps &
1068                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
1069                              (dv_attr.tunnel_offloads_caps &
1070                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE));
1071         }
1072         DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
1073                 tunnel_en ? "" : "not ");
1074 #else
1075         DRV_LOG(WARNING,
1076                 "tunnel offloading disabled due to old OFED/rdma-core version");
1077 #endif
1078         config.tunnel_en = tunnel_en;
1079 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
1080         mpls_en = ((dv_attr.tunnel_offloads_caps &
1081                     MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
1082                    (dv_attr.tunnel_offloads_caps &
1083                     MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
1084         DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
1085                 mpls_en ? "" : "not ");
1086 #else
1087         DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
1088                 " old OFED/rdma-core version or firmware configuration");
1089 #endif
1090         config.mpls_en = mpls_en;
1091         /* Check port status. */
1092         err = mlx5_glue->query_port(sh->ctx, spawn->ibv_port, &port_attr);
1093         if (err) {
1094                 DRV_LOG(ERR, "port query failed: %s", strerror(err));
1095                 goto error;
1096         }
1097         if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
1098                 DRV_LOG(ERR, "port is not configured in Ethernet mode");
1099                 err = EINVAL;
1100                 goto error;
1101         }
1102         if (port_attr.state != IBV_PORT_ACTIVE)
1103                 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)",
1104                         mlx5_glue->port_state_str(port_attr.state),
1105                         port_attr.state);
1106         /* Allocate private eth device data. */
1107         priv = rte_zmalloc("ethdev private structure",
1108                            sizeof(*priv),
1109                            RTE_CACHE_LINE_SIZE);
1110         if (priv == NULL) {
1111                 DRV_LOG(ERR, "priv allocation failure");
1112                 err = ENOMEM;
1113                 goto error;
1114         }
1115         priv->sh = sh;
1116         priv->ibv_port = spawn->ibv_port;
1117         priv->mtu = ETHER_MTU;
1118 #ifndef RTE_ARCH_64
1119         /* Initialize UAR access locks for 32bit implementations. */
1120         rte_spinlock_init(&priv->uar_lock_cq);
1121         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
1122                 rte_spinlock_init(&priv->uar_lock[i]);
1123 #endif
1124         /* Some internal functions rely on Netlink sockets, open them now. */
1125         priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA);
1126         priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE);
1127         priv->nl_sn = 0;
1128         priv->representor = !!switch_info->representor;
1129         priv->master = !!switch_info->master;
1130         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1131         /*
1132          * Currently we support single E-Switch per PF configurations
1133          * only and vport_id field contains the vport index for
1134          * associated VF, which is deduced from representor port name.
1135          * For exapmple, let's have the IB device port 10, it has
1136          * attached network device eth0, which has port name attribute
1137          * pf0vf2, we can deduce the VF number as 2, and set vport index
1138          * as 3 (2+1). This assigning schema should be changed if the
1139          * multiple E-Switch instances per PF configurations or/and PCI
1140          * subfunctions are added.
1141          */
1142         priv->vport_id = switch_info->representor ?
1143                          switch_info->port_name + 1 : -1;
1144         /* representor_id field keeps the unmodified port/VF index. */
1145         priv->representor_id = switch_info->representor ?
1146                                switch_info->port_name : -1;
1147         /*
1148          * Look for sibling devices in order to reuse their switch domain
1149          * if any, otherwise allocate one.
1150          */
1151         i = mlx5_dev_to_port_id(dpdk_dev, NULL, 0);
1152         if (i > 0) {
1153                 uint16_t port_id[i];
1154
1155                 i = RTE_MIN(mlx5_dev_to_port_id(dpdk_dev, port_id, i), i);
1156                 while (i--) {
1157                         const struct mlx5_priv *opriv =
1158                                 rte_eth_devices[port_id[i]].data->dev_private;
1159
1160                         if (!opriv ||
1161                             opriv->domain_id ==
1162                             RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
1163                                 continue;
1164                         priv->domain_id = opriv->domain_id;
1165                         break;
1166                 }
1167         }
1168         if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1169                 err = rte_eth_switch_domain_alloc(&priv->domain_id);
1170                 if (err) {
1171                         err = rte_errno;
1172                         DRV_LOG(ERR, "unable to allocate switch domain: %s",
1173                                 strerror(rte_errno));
1174                         goto error;
1175                 }
1176                 own_domain_id = 1;
1177         }
1178         err = mlx5_args(&config, dpdk_dev->devargs);
1179         if (err) {
1180                 err = rte_errno;
1181                 DRV_LOG(ERR, "failed to process device arguments: %s",
1182                         strerror(rte_errno));
1183                 goto error;
1184         }
1185         config.hw_csum = !!(sh->device_attr.device_cap_flags_ex &
1186                             IBV_DEVICE_RAW_IP_CSUM);
1187         DRV_LOG(DEBUG, "checksum offloading is %ssupported",
1188                 (config.hw_csum ? "" : "not "));
1189 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \
1190         !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
1191         DRV_LOG(DEBUG, "counters are not supported");
1192 #endif
1193 #ifndef HAVE_IBV_FLOW_DV_SUPPORT
1194         if (config.dv_flow_en) {
1195                 DRV_LOG(WARNING, "DV flow is not supported");
1196                 config.dv_flow_en = 0;
1197         }
1198 #endif
1199         config.ind_table_max_size =
1200                 sh->device_attr.rss_caps.max_rwq_indirection_table_size;
1201         /*
1202          * Remove this check once DPDK supports larger/variable
1203          * indirection tables.
1204          */
1205         if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
1206                 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
1207         DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
1208                 config.ind_table_max_size);
1209         config.hw_vlan_strip = !!(sh->device_attr.raw_packet_caps &
1210                                   IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
1211         DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
1212                 (config.hw_vlan_strip ? "" : "not "));
1213         config.hw_fcs_strip = !!(sh->device_attr.raw_packet_caps &
1214                                  IBV_RAW_PACKET_CAP_SCATTER_FCS);
1215         DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
1216                 (config.hw_fcs_strip ? "" : "not "));
1217 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
1218         hw_padding = !!sh->device_attr.rx_pad_end_addr_align;
1219 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
1220         hw_padding = !!(sh->device_attr.device_cap_flags_ex &
1221                         IBV_DEVICE_PCI_WRITE_END_PADDING);
1222 #endif
1223         if (config.hw_padding && !hw_padding) {
1224                 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
1225                 config.hw_padding = 0;
1226         } else if (config.hw_padding) {
1227                 DRV_LOG(DEBUG, "Rx end alignment padding is enabled");
1228         }
1229         config.tso = (sh->device_attr.tso_caps.max_tso > 0 &&
1230                       (sh->device_attr.tso_caps.supported_qpts &
1231                        (1 << IBV_QPT_RAW_PACKET)));
1232         if (config.tso)
1233                 config.tso_max_payload_sz = sh->device_attr.tso_caps.max_tso;
1234         /*
1235          * MPW is disabled by default, while the Enhanced MPW is enabled
1236          * by default.
1237          */
1238         if (config.mps == MLX5_ARG_UNSET)
1239                 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED :
1240                                                           MLX5_MPW_DISABLED;
1241         else
1242                 config.mps = config.mps ? mps : MLX5_MPW_DISABLED;
1243         DRV_LOG(INFO, "%sMPS is %s",
1244                 config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "",
1245                 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
1246         if (config.cqe_comp && !cqe_comp) {
1247                 DRV_LOG(WARNING, "Rx CQE compression isn't supported");
1248                 config.cqe_comp = 0;
1249         }
1250         if (config.cqe_pad && !cqe_pad) {
1251                 DRV_LOG(WARNING, "Rx CQE padding isn't supported");
1252                 config.cqe_pad = 0;
1253         } else if (config.cqe_pad) {
1254                 DRV_LOG(INFO, "Rx CQE padding is enabled");
1255         }
1256         if (config.mprq.enabled && mprq) {
1257                 if (config.mprq.stride_num_n > mprq_max_stride_num_n ||
1258                     config.mprq.stride_num_n < mprq_min_stride_num_n) {
1259                         config.mprq.stride_num_n =
1260                                 RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
1261                                         mprq_min_stride_num_n);
1262                         DRV_LOG(WARNING,
1263                                 "the number of strides"
1264                                 " for Multi-Packet RQ is out of range,"
1265                                 " setting default value (%u)",
1266                                 1 << config.mprq.stride_num_n);
1267                 }
1268                 config.mprq.min_stride_size_n = mprq_min_stride_size_n;
1269                 config.mprq.max_stride_size_n = mprq_max_stride_size_n;
1270         } else if (config.mprq.enabled && !mprq) {
1271                 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
1272                 config.mprq.enabled = 0;
1273         }
1274         eth_dev = rte_eth_dev_allocate(name);
1275         if (eth_dev == NULL) {
1276                 DRV_LOG(ERR, "can not allocate rte ethdev");
1277                 err = ENOMEM;
1278                 goto error;
1279         }
1280         /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */
1281         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1282         if (priv->representor) {
1283                 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
1284                 eth_dev->data->representor_id = priv->representor_id;
1285         }
1286         eth_dev->data->dev_private = priv;
1287         priv->dev_data = eth_dev->data;
1288         eth_dev->data->mac_addrs = priv->mac;
1289         eth_dev->device = dpdk_dev;
1290         err = mlx5_uar_init_primary(eth_dev);
1291         if (err) {
1292                 err = rte_errno;
1293                 goto error;
1294         }
1295         /* Configure the first MAC address by default. */
1296         if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
1297                 DRV_LOG(ERR,
1298                         "port %u cannot get MAC address, is mlx5_en"
1299                         " loaded? (errno: %s)",
1300                         eth_dev->data->port_id, strerror(rte_errno));
1301                 err = ENODEV;
1302                 goto error;
1303         }
1304         DRV_LOG(INFO,
1305                 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
1306                 eth_dev->data->port_id,
1307                 mac.addr_bytes[0], mac.addr_bytes[1],
1308                 mac.addr_bytes[2], mac.addr_bytes[3],
1309                 mac.addr_bytes[4], mac.addr_bytes[5]);
1310 #ifndef NDEBUG
1311         {
1312                 char ifname[IF_NAMESIZE];
1313
1314                 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
1315                         DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
1316                                 eth_dev->data->port_id, ifname);
1317                 else
1318                         DRV_LOG(DEBUG, "port %u ifname is unknown",
1319                                 eth_dev->data->port_id);
1320         }
1321 #endif
1322         /* Get actual MTU if possible. */
1323         err = mlx5_get_mtu(eth_dev, &priv->mtu);
1324         if (err) {
1325                 err = rte_errno;
1326                 goto error;
1327         }
1328         DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
1329                 priv->mtu);
1330         /* Initialize burst functions to prevent crashes before link-up. */
1331         eth_dev->rx_pkt_burst = removed_rx_burst;
1332         eth_dev->tx_pkt_burst = removed_tx_burst;
1333         eth_dev->dev_ops = &mlx5_dev_ops;
1334         /* Register MAC address. */
1335         claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
1336         if (config.vf && config.vf_nl_en)
1337                 mlx5_nl_mac_addr_sync(eth_dev);
1338         priv->tcf_context = mlx5_flow_tcf_context_create();
1339         if (!priv->tcf_context) {
1340                 err = -rte_errno;
1341                 DRV_LOG(WARNING,
1342                         "flow rules relying on switch offloads will not be"
1343                         " supported: cannot open libmnl socket: %s",
1344                         strerror(rte_errno));
1345         } else {
1346                 struct rte_flow_error error;
1347                 unsigned int ifindex = mlx5_ifindex(eth_dev);
1348
1349                 if (!ifindex) {
1350                         err = -rte_errno;
1351                         error.message =
1352                                 "cannot retrieve network interface index";
1353                 } else {
1354                         err = mlx5_flow_tcf_init(priv->tcf_context,
1355                                                  ifindex, &error);
1356                 }
1357                 if (err) {
1358                         DRV_LOG(WARNING,
1359                                 "flow rules relying on switch offloads will"
1360                                 " not be supported: %s: %s",
1361                                 error.message, strerror(rte_errno));
1362                         mlx5_flow_tcf_context_destroy(priv->tcf_context);
1363                         priv->tcf_context = NULL;
1364                 }
1365         }
1366         TAILQ_INIT(&priv->flows);
1367         TAILQ_INIT(&priv->ctrl_flows);
1368         /* Hint libmlx5 to use PMD allocator for data plane resources */
1369         struct mlx5dv_ctx_allocators alctr = {
1370                 .alloc = &mlx5_alloc_verbs_buf,
1371                 .free = &mlx5_free_verbs_buf,
1372                 .data = priv,
1373         };
1374         mlx5_glue->dv_set_context_attr(sh->ctx,
1375                                        MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
1376                                        (void *)((uintptr_t)&alctr));
1377         /* Bring Ethernet device up. */
1378         DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
1379                 eth_dev->data->port_id);
1380         mlx5_set_link_up(eth_dev);
1381         /*
1382          * Even though the interrupt handler is not installed yet,
1383          * interrupts will still trigger on the asyn_fd from
1384          * Verbs context returned by ibv_open_device().
1385          */
1386         mlx5_link_update(eth_dev, 0);
1387         /* Store device configuration on private structure. */
1388         priv->config = config;
1389         /* Supported Verbs flow priority number detection. */
1390         err = mlx5_flow_discover_priorities(eth_dev);
1391         if (err < 0) {
1392                 err = -err;
1393                 goto error;
1394         }
1395         priv->config.flow_prio = err;
1396         /*
1397          * Once the device is added to the list of memory event
1398          * callback, its global MR cache table cannot be expanded
1399          * on the fly because of deadlock. If it overflows, lookup
1400          * should be done by searching MR list linearly, which is slow.
1401          */
1402         err = mlx5_mr_btree_init(&priv->mr.cache,
1403                                  MLX5_MR_BTREE_CACHE_N * 2,
1404                                  eth_dev->device->numa_node);
1405         if (err) {
1406                 err = rte_errno;
1407                 goto error;
1408         }
1409         /* Add device to memory callback list. */
1410         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1411         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1412                          priv, mem_event_cb);
1413         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1414         return eth_dev;
1415 error:
1416         if (priv) {
1417                 if (priv->nl_socket_route >= 0)
1418                         close(priv->nl_socket_route);
1419                 if (priv->nl_socket_rdma >= 0)
1420                         close(priv->nl_socket_rdma);
1421                 if (priv->tcf_context)
1422                         mlx5_flow_tcf_context_destroy(priv->tcf_context);
1423                 if (own_domain_id)
1424                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1425                 rte_free(priv);
1426                 if (eth_dev != NULL)
1427                         eth_dev->data->dev_private = NULL;
1428         }
1429         if (eth_dev != NULL) {
1430                 /* mac_addrs must not be freed alone because part of dev_private */
1431                 eth_dev->data->mac_addrs = NULL;
1432                 rte_eth_dev_release_port(eth_dev);
1433         }
1434         if (sh)
1435                 mlx5_free_shared_ibctx(sh);
1436         assert(err > 0);
1437         rte_errno = err;
1438         return NULL;
1439 }
1440
1441 /**
1442  * Comparison callback to sort device data.
1443  *
1444  * This is meant to be used with qsort().
1445  *
1446  * @param a[in]
1447  *   Pointer to pointer to first data object.
1448  * @param b[in]
1449  *   Pointer to pointer to second data object.
1450  *
1451  * @return
1452  *   0 if both objects are equal, less than 0 if the first argument is less
1453  *   than the second, greater than 0 otherwise.
1454  */
1455 static int
1456 mlx5_dev_spawn_data_cmp(const void *a, const void *b)
1457 {
1458         const struct mlx5_switch_info *si_a =
1459                 &((const struct mlx5_dev_spawn_data *)a)->info;
1460         const struct mlx5_switch_info *si_b =
1461                 &((const struct mlx5_dev_spawn_data *)b)->info;
1462         int ret;
1463
1464         /* Master device first. */
1465         ret = si_b->master - si_a->master;
1466         if (ret)
1467                 return ret;
1468         /* Then representor devices. */
1469         ret = si_b->representor - si_a->representor;
1470         if (ret)
1471                 return ret;
1472         /* Unidentified devices come last in no specific order. */
1473         if (!si_a->representor)
1474                 return 0;
1475         /* Order representors by name. */
1476         return si_a->port_name - si_b->port_name;
1477 }
1478
1479 /**
1480  * DPDK callback to register a PCI device.
1481  *
1482  * This function spawns Ethernet devices out of a given PCI device.
1483  *
1484  * @param[in] pci_drv
1485  *   PCI driver structure (mlx5_driver).
1486  * @param[in] pci_dev
1487  *   PCI device information.
1488  *
1489  * @return
1490  *   0 on success, a negative errno value otherwise and rte_errno is set.
1491  */
1492 static int
1493 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1494                struct rte_pci_device *pci_dev)
1495 {
1496         struct ibv_device **ibv_list;
1497         /*
1498          * Number of found IB Devices matching with requested PCI BDF.
1499          * nd != 1 means there are multiple IB devices over the same
1500          * PCI device and we have representors and master.
1501          */
1502         unsigned int nd = 0;
1503         /*
1504          * Number of found IB device Ports. nd = 1 and np = 1..n means
1505          * we have the single multiport IB device, and there may be
1506          * representors attached to some of found ports.
1507          */
1508         unsigned int np = 0;
1509         /*
1510          * Number of DPDK ethernet devices to Spawn - either over
1511          * multiple IB devices or multiple ports of single IB device.
1512          * Actually this is the number of iterations to spawn.
1513          */
1514         unsigned int ns = 0;
1515         struct mlx5_dev_config dev_config;
1516         int ret;
1517
1518         assert(pci_drv == &mlx5_driver);
1519         errno = 0;
1520         ibv_list = mlx5_glue->get_device_list(&ret);
1521         if (!ibv_list) {
1522                 rte_errno = errno ? errno : ENOSYS;
1523                 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?");
1524                 return -rte_errno;
1525         }
1526         /*
1527          * First scan the list of all Infiniband devices to find
1528          * matching ones, gathering into the list.
1529          */
1530         struct ibv_device *ibv_match[ret + 1];
1531         int nl_route = -1;
1532         int nl_rdma = -1;
1533         unsigned int i;
1534
1535         while (ret-- > 0) {
1536                 struct rte_pci_addr pci_addr;
1537
1538                 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name);
1539                 if (mlx5_ibv_device_to_pci_addr(ibv_list[ret], &pci_addr))
1540                         continue;
1541                 if (pci_dev->addr.domain != pci_addr.domain ||
1542                     pci_dev->addr.bus != pci_addr.bus ||
1543                     pci_dev->addr.devid != pci_addr.devid ||
1544                     pci_dev->addr.function != pci_addr.function)
1545                         continue;
1546                 DRV_LOG(INFO, "PCI information matches for device \"%s\"",
1547                         ibv_list[ret]->name);
1548                 ibv_match[nd++] = ibv_list[ret];
1549         }
1550         ibv_match[nd] = NULL;
1551         if (!nd) {
1552                 /* No device macthes, just complain and bail out. */
1553                 mlx5_glue->free_device_list(ibv_list);
1554                 DRV_LOG(WARNING,
1555                         "no Verbs device matches PCI device " PCI_PRI_FMT ","
1556                         " are kernel drivers loaded?",
1557                         pci_dev->addr.domain, pci_dev->addr.bus,
1558                         pci_dev->addr.devid, pci_dev->addr.function);
1559                 rte_errno = ENOENT;
1560                 ret = -rte_errno;
1561                 return ret;
1562         }
1563         nl_route = mlx5_nl_init(NETLINK_ROUTE);
1564         nl_rdma = mlx5_nl_init(NETLINK_RDMA);
1565         if (nd == 1) {
1566                 /*
1567                  * Found single matching device may have multiple ports.
1568                  * Each port may be representor, we have to check the port
1569                  * number and check the representors existence.
1570                  */
1571                 if (nl_rdma >= 0)
1572                         np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name);
1573                 if (!np)
1574                         DRV_LOG(WARNING, "can not get IB device \"%s\""
1575                                          " ports number", ibv_match[0]->name);
1576         }
1577         /*
1578          * Now we can determine the maximal
1579          * amount of devices to be spawned.
1580          */
1581         struct mlx5_dev_spawn_data list[np ? np : nd];
1582
1583         if (np > 1) {
1584                 /*
1585                  * Signle IB device with multiple ports found,
1586                  * it may be E-Switch master device and representors.
1587                  * We have to perform identification trough the ports.
1588                  */
1589                 assert(nl_rdma >= 0);
1590                 assert(ns == 0);
1591                 assert(nd == 1);
1592                 for (i = 1; i <= np; ++i) {
1593                         list[ns].max_port = np;
1594                         list[ns].ibv_port = i;
1595                         list[ns].ibv_dev = ibv_match[0];
1596                         list[ns].eth_dev = NULL;
1597                         list[ns].ifindex = mlx5_nl_ifindex
1598                                         (nl_rdma, list[ns].ibv_dev->name, i);
1599                         if (!list[ns].ifindex) {
1600                                 /*
1601                                  * No network interface index found for the
1602                                  * specified port, it means there is no
1603                                  * representor on this port. It's OK,
1604                                  * there can be disabled ports, for example
1605                                  * if sriov_numvfs < sriov_totalvfs.
1606                                  */
1607                                 continue;
1608                         }
1609                         ret = -1;
1610                         if (nl_route >= 0)
1611                                 ret = mlx5_nl_switch_info
1612                                                (nl_route,
1613                                                 list[ns].ifindex,
1614                                                 &list[ns].info);
1615                         if (ret || (!list[ns].info.representor &&
1616                                     !list[ns].info.master)) {
1617                                 /*
1618                                  * We failed to recognize representors with
1619                                  * Netlink, let's try to perform the task
1620                                  * with sysfs.
1621                                  */
1622                                 ret =  mlx5_sysfs_switch_info
1623                                                 (list[ns].ifindex,
1624                                                  &list[ns].info);
1625                         }
1626                         if (!ret && (list[ns].info.representor ^
1627                                      list[ns].info.master))
1628                                 ns++;
1629                 }
1630                 if (!ns) {
1631                         DRV_LOG(ERR,
1632                                 "unable to recognize master/representors"
1633                                 " on the IB device with multiple ports");
1634                         rte_errno = ENOENT;
1635                         ret = -rte_errno;
1636                         goto exit;
1637                 }
1638         } else {
1639                 /*
1640                  * The existence of several matching entries (nd > 1) means
1641                  * port representors have been instantiated. No existing Verbs
1642                  * call nor sysfs entries can tell them apart, this can only
1643                  * be done through Netlink calls assuming kernel drivers are
1644                  * recent enough to support them.
1645                  *
1646                  * In the event of identification failure through Netlink,
1647                  * try again through sysfs, then:
1648                  *
1649                  * 1. A single IB device matches (nd == 1) with single
1650                  *    port (np=0/1) and is not a representor, assume
1651                  *    no switch support.
1652                  *
1653                  * 2. Otherwise no safe assumptions can be made;
1654                  *    complain louder and bail out.
1655                  */
1656                 np = 1;
1657                 for (i = 0; i != nd; ++i) {
1658                         memset(&list[ns].info, 0, sizeof(list[ns].info));
1659                         list[ns].max_port = 1;
1660                         list[ns].ibv_port = 1;
1661                         list[ns].ibv_dev = ibv_match[i];
1662                         list[ns].eth_dev = NULL;
1663                         list[ns].ifindex = 0;
1664                         if (nl_rdma >= 0)
1665                                 list[ns].ifindex = mlx5_nl_ifindex
1666                                         (nl_rdma, list[ns].ibv_dev->name, 1);
1667                         if (!list[ns].ifindex) {
1668                                 /*
1669                                  * No network interface index found for the
1670                                  * specified device, it means there it is not
1671                                  * a representor/master.
1672                                  */
1673                                 continue;
1674                         }
1675                         ret = -1;
1676                         if (nl_route >= 0)
1677                                 ret = mlx5_nl_switch_info
1678                                                (nl_route,
1679                                                 list[ns].ifindex,
1680                                                 &list[ns].info);
1681                         if (ret || (!list[ns].info.representor &&
1682                                     !list[ns].info.master)) {
1683                                 /*
1684                                  * We failed to recognize representors with
1685                                  * Netlink, let's try to perform the task
1686                                  * with sysfs.
1687                                  */
1688                                 ret =  mlx5_sysfs_switch_info
1689                                                 (list[ns].ifindex,
1690                                                  &list[ns].info);
1691                         }
1692                         if (!ret && (list[ns].info.representor ^
1693                                      list[ns].info.master)) {
1694                                 ns++;
1695                         } else if ((nd == 1) &&
1696                                    !list[ns].info.representor &&
1697                                    !list[ns].info.master) {
1698                                 /*
1699                                  * Single IB device with
1700                                  * one physical port and
1701                                  * attached network device.
1702                                  * May be SRIOV is not enabled
1703                                  * or there is no representors.
1704                                  */
1705                                 DRV_LOG(INFO, "no E-Switch support detected");
1706                                 ns++;
1707                                 break;
1708                         }
1709                 }
1710                 if (!ns) {
1711                         DRV_LOG(ERR,
1712                                 "unable to recognize master/representors"
1713                                 " on the multiple IB devices");
1714                         rte_errno = ENOENT;
1715                         ret = -rte_errno;
1716                         goto exit;
1717                 }
1718         }
1719         assert(ns);
1720         /*
1721          * Sort list to probe devices in natural order for users convenience
1722          * (i.e. master first, then representors from lowest to highest ID).
1723          */
1724         qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp);
1725         /* Default configuration. */
1726         dev_config = (struct mlx5_dev_config){
1727                 .hw_padding = 0,
1728                 .mps = MLX5_ARG_UNSET,
1729                 .tx_vec_en = 1,
1730                 .rx_vec_en = 1,
1731                 .txq_inline = MLX5_ARG_UNSET,
1732                 .txqs_inline = MLX5_ARG_UNSET,
1733                 .txqs_vec = MLX5_ARG_UNSET,
1734                 .inline_max_packet_sz = MLX5_ARG_UNSET,
1735                 .vf_nl_en = 1,
1736                 .mprq = {
1737                         .enabled = 0, /* Disabled by default. */
1738                         .stride_num_n = MLX5_MPRQ_STRIDE_NUM_N,
1739                         .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
1740                         .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
1741                 },
1742         };
1743         /* Device specific configuration. */
1744         switch (pci_dev->id.device_id) {
1745         case PCI_DEVICE_ID_MELLANOX_CONNECTX5BF:
1746                 dev_config.txqs_vec = MLX5_VPMD_MAX_TXQS_BLUEFIELD;
1747                 break;
1748         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1749         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1750         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1751         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1752                 dev_config.vf = 1;
1753                 break;
1754         default:
1755                 break;
1756         }
1757         /* Set architecture-dependent default value if unset. */
1758         if (dev_config.txqs_vec == MLX5_ARG_UNSET)
1759                 dev_config.txqs_vec = MLX5_VPMD_MAX_TXQS;
1760         for (i = 0; i != ns; ++i) {
1761                 uint32_t restore;
1762
1763                 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device,
1764                                                  &list[i],
1765                                                  dev_config);
1766                 if (!list[i].eth_dev) {
1767                         if (rte_errno != EBUSY && rte_errno != EEXIST)
1768                                 break;
1769                         /* Device is disabled or already spawned. Ignore it. */
1770                         continue;
1771                 }
1772                 restore = list[i].eth_dev->data->dev_flags;
1773                 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev);
1774                 /* Restore non-PCI flags cleared by the above call. */
1775                 list[i].eth_dev->data->dev_flags |= restore;
1776                 rte_eth_dev_probing_finish(list[i].eth_dev);
1777         }
1778         if (i != ns) {
1779                 DRV_LOG(ERR,
1780                         "probe of PCI device " PCI_PRI_FMT " aborted after"
1781                         " encountering an error: %s",
1782                         pci_dev->addr.domain, pci_dev->addr.bus,
1783                         pci_dev->addr.devid, pci_dev->addr.function,
1784                         strerror(rte_errno));
1785                 ret = -rte_errno;
1786                 /* Roll back. */
1787                 while (i--) {
1788                         if (!list[i].eth_dev)
1789                                 continue;
1790                         mlx5_dev_close(list[i].eth_dev);
1791                         /* mac_addrs must not be freed because in dev_private */
1792                         list[i].eth_dev->data->mac_addrs = NULL;
1793                         claim_zero(rte_eth_dev_release_port(list[i].eth_dev));
1794                 }
1795                 /* Restore original error. */
1796                 rte_errno = -ret;
1797         } else {
1798                 ret = 0;
1799         }
1800 exit:
1801         /*
1802          * Do the routine cleanup:
1803          * - close opened Netlink sockets
1804          * - free the Infiniband device list
1805          */
1806         if (nl_rdma >= 0)
1807                 close(nl_rdma);
1808         if (nl_route >= 0)
1809                 close(nl_route);
1810         assert(ibv_list);
1811         mlx5_glue->free_device_list(ibv_list);
1812         return ret;
1813 }
1814
1815 /**
1816  * DPDK callback to remove a PCI device.
1817  *
1818  * This function removes all Ethernet devices belong to a given PCI device.
1819  *
1820  * @param[in] pci_dev
1821  *   Pointer to the PCI device.
1822  *
1823  * @return
1824  *   0 on success, the function cannot fail.
1825  */
1826 static int
1827 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1828 {
1829         uint16_t port_id;
1830         struct rte_eth_dev *port;
1831
1832         for (port_id = 0; port_id < RTE_MAX_ETHPORTS; port_id++) {
1833                 port = &rte_eth_devices[port_id];
1834                 if (port->state != RTE_ETH_DEV_UNUSED &&
1835                                 port->device == &pci_dev->device)
1836                         rte_eth_dev_close(port_id);
1837         }
1838         return 0;
1839 }
1840
1841 static const struct rte_pci_id mlx5_pci_id_map[] = {
1842         {
1843                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1844                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1845         },
1846         {
1847                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1848                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1849         },
1850         {
1851                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1852                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1853         },
1854         {
1855                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1856                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1857         },
1858         {
1859                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1860                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1861         },
1862         {
1863                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1864                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1865         },
1866         {
1867                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1868                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1869         },
1870         {
1871                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1872                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1873         },
1874         {
1875                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1876                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
1877         },
1878         {
1879                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1880                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
1881         },
1882         {
1883                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1884                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
1885         },
1886         {
1887                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1888                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
1889         },
1890         {
1891                 .vendor_id = 0
1892         }
1893 };
1894
1895 static struct rte_pci_driver mlx5_driver = {
1896         .driver = {
1897                 .name = MLX5_DRIVER_NAME
1898         },
1899         .id_table = mlx5_pci_id_map,
1900         .probe = mlx5_pci_probe,
1901         .remove = mlx5_pci_remove,
1902         .dma_map = mlx5_dma_map,
1903         .dma_unmap = mlx5_dma_unmap,
1904         .drv_flags = (RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV |
1905                       RTE_PCI_DRV_PROBE_AGAIN),
1906 };
1907
1908 #ifdef RTE_IBVERBS_LINK_DLOPEN
1909
1910 /**
1911  * Suffix RTE_EAL_PMD_PATH with "-glue".
1912  *
1913  * This function performs a sanity check on RTE_EAL_PMD_PATH before
1914  * suffixing its last component.
1915  *
1916  * @param buf[out]
1917  *   Output buffer, should be large enough otherwise NULL is returned.
1918  * @param size
1919  *   Size of @p out.
1920  *
1921  * @return
1922  *   Pointer to @p buf or @p NULL in case suffix cannot be appended.
1923  */
1924 static char *
1925 mlx5_glue_path(char *buf, size_t size)
1926 {
1927         static const char *const bad[] = { "/", ".", "..", NULL };
1928         const char *path = RTE_EAL_PMD_PATH;
1929         size_t len = strlen(path);
1930         size_t off;
1931         int i;
1932
1933         while (len && path[len - 1] == '/')
1934                 --len;
1935         for (off = len; off && path[off - 1] != '/'; --off)
1936                 ;
1937         for (i = 0; bad[i]; ++i)
1938                 if (!strncmp(path + off, bad[i], (int)(len - off)))
1939                         goto error;
1940         i = snprintf(buf, size, "%.*s-glue", (int)len, path);
1941         if (i == -1 || (size_t)i >= size)
1942                 goto error;
1943         return buf;
1944 error:
1945         DRV_LOG(ERR,
1946                 "unable to append \"-glue\" to last component of"
1947                 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\"),"
1948                 " please re-configure DPDK");
1949         return NULL;
1950 }
1951
1952 /**
1953  * Initialization routine for run-time dependency on rdma-core.
1954  */
1955 static int
1956 mlx5_glue_init(void)
1957 {
1958         char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")];
1959         const char *path[] = {
1960                 /*
1961                  * A basic security check is necessary before trusting
1962                  * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH.
1963                  */
1964                 (geteuid() == getuid() && getegid() == getgid() ?
1965                  getenv("MLX5_GLUE_PATH") : NULL),
1966                 /*
1967                  * When RTE_EAL_PMD_PATH is set, use its glue-suffixed
1968                  * variant, otherwise let dlopen() look up libraries on its
1969                  * own.
1970                  */
1971                 (*RTE_EAL_PMD_PATH ?
1972                  mlx5_glue_path(glue_path, sizeof(glue_path)) : ""),
1973         };
1974         unsigned int i = 0;
1975         void *handle = NULL;
1976         void **sym;
1977         const char *dlmsg;
1978
1979         while (!handle && i != RTE_DIM(path)) {
1980                 const char *end;
1981                 size_t len;
1982                 int ret;
1983
1984                 if (!path[i]) {
1985                         ++i;
1986                         continue;
1987                 }
1988                 end = strpbrk(path[i], ":;");
1989                 if (!end)
1990                         end = path[i] + strlen(path[i]);
1991                 len = end - path[i];
1992                 ret = 0;
1993                 do {
1994                         char name[ret + 1];
1995
1996                         ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE,
1997                                        (int)len, path[i],
1998                                        (!len || *(end - 1) == '/') ? "" : "/");
1999                         if (ret == -1)
2000                                 break;
2001                         if (sizeof(name) != (size_t)ret + 1)
2002                                 continue;
2003                         DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"",
2004                                 name);
2005                         handle = dlopen(name, RTLD_LAZY);
2006                         break;
2007                 } while (1);
2008                 path[i] = end + 1;
2009                 if (!*end)
2010                         ++i;
2011         }
2012         if (!handle) {
2013                 rte_errno = EINVAL;
2014                 dlmsg = dlerror();
2015                 if (dlmsg)
2016                         DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg);
2017                 goto glue_error;
2018         }
2019         sym = dlsym(handle, "mlx5_glue");
2020         if (!sym || !*sym) {
2021                 rte_errno = EINVAL;
2022                 dlmsg = dlerror();
2023                 if (dlmsg)
2024                         DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg);
2025                 goto glue_error;
2026         }
2027         mlx5_glue = *sym;
2028         return 0;
2029 glue_error:
2030         if (handle)
2031                 dlclose(handle);
2032         DRV_LOG(WARNING,
2033                 "cannot initialize PMD due to missing run-time dependency on"
2034                 " rdma-core libraries (libibverbs, libmlx5)");
2035         return -rte_errno;
2036 }
2037
2038 #endif
2039
2040 /**
2041  * Driver initialization routine.
2042  */
2043 RTE_INIT(rte_mlx5_pmd_init)
2044 {
2045         /* Initialize driver log type. */
2046         mlx5_logtype = rte_log_register("pmd.net.mlx5");
2047         if (mlx5_logtype >= 0)
2048                 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
2049
2050         /* Build the static tables for Verbs conversion. */
2051         mlx5_set_ptype_table();
2052         mlx5_set_cksum_table();
2053         mlx5_set_swp_types_table();
2054         /*
2055          * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
2056          * huge pages. Calling ibv_fork_init() during init allows
2057          * applications to use fork() safely for purposes other than
2058          * using this PMD, which is not supported in forked processes.
2059          */
2060         setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
2061         /* Match the size of Rx completion entry to the size of a cacheline. */
2062         if (RTE_CACHE_LINE_SIZE == 128)
2063                 setenv("MLX5_CQE_SIZE", "128", 0);
2064         /*
2065          * MLX5_DEVICE_FATAL_CLEANUP tells ibv_destroy functions to
2066          * cleanup all the Verbs resources even when the device was removed.
2067          */
2068         setenv("MLX5_DEVICE_FATAL_CLEANUP", "1", 1);
2069 #ifdef RTE_IBVERBS_LINK_DLOPEN
2070         if (mlx5_glue_init())
2071                 return;
2072         assert(mlx5_glue);
2073 #endif
2074 #ifndef NDEBUG
2075         /* Glue structure must not contain any NULL pointers. */
2076         {
2077                 unsigned int i;
2078
2079                 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i)
2080                         assert(((const void *const *)mlx5_glue)[i]);
2081         }
2082 #endif
2083         if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) {
2084                 DRV_LOG(ERR,
2085                         "rdma-core glue \"%s\" mismatch: \"%s\" is required",
2086                         mlx5_glue->version, MLX5_GLUE_VERSION);
2087                 return;
2088         }
2089         mlx5_glue->fork_init();
2090         rte_pci_register(&mlx5_driver);
2091 }
2092
2093 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2094 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2095 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");