1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
16 #include <linux/netlink.h>
17 #include <linux/rtnetlink.h>
20 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
22 #pragma GCC diagnostic ignored "-Wpedantic"
24 #include <infiniband/verbs.h>
26 #pragma GCC diagnostic error "-Wpedantic"
29 #include <rte_malloc.h>
30 #include <rte_ethdev_driver.h>
31 #include <rte_ethdev_pci.h>
33 #include <rte_bus_pci.h>
34 #include <rte_common.h>
35 #include <rte_config.h>
36 #include <rte_eal_memconfig.h>
37 #include <rte_kvargs.h>
38 #include <rte_rwlock.h>
39 #include <rte_spinlock.h>
40 #include <rte_string_fns.h>
43 #include "mlx5_utils.h"
44 #include "mlx5_rxtx.h"
45 #include "mlx5_autoconf.h"
46 #include "mlx5_defs.h"
47 #include "mlx5_glue.h"
49 #include "mlx5_flow.h"
51 /* Device parameter to enable RX completion queue compression. */
52 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
54 /* Device parameter to enable Multi-Packet Rx queue. */
55 #define MLX5_RX_MPRQ_EN "mprq_en"
57 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
58 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
60 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
61 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
63 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
64 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
66 /* Device parameter to configure inline send. */
67 #define MLX5_TXQ_INLINE "txq_inline"
70 * Device parameter to configure the number of TX queues threshold for
71 * enabling inline send.
73 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
75 /* Device parameter to enable multi-packet send WQEs. */
76 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
78 /* Device parameter to include 2 dsegs in the title WQEBB. */
79 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
81 /* Device parameter to limit the size of inlining packet. */
82 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
84 /* Device parameter to enable hardware Tx vector. */
85 #define MLX5_TX_VEC_EN "tx_vec_en"
87 /* Device parameter to enable hardware Rx vector. */
88 #define MLX5_RX_VEC_EN "rx_vec_en"
90 /* Allow L3 VXLAN flow creation. */
91 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
93 /* Activate DV flow steering. */
94 #define MLX5_DV_FLOW_EN "dv_flow_en"
96 /* Activate Netlink support in VF mode. */
97 #define MLX5_VF_NL_EN "vf_nl_en"
99 /* Select port representors to instantiate. */
100 #define MLX5_REPRESENTOR "representor"
102 #ifndef HAVE_IBV_MLX5_MOD_MPW
103 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
104 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
107 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
108 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
111 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
113 /* Shared memory between primary and secondary processes. */
114 struct mlx5_shared_data *mlx5_shared_data;
116 /* Spinlock for mlx5_shared_data allocation. */
117 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
119 /** Driver-specific log messages type. */
123 * Prepare shared data between primary and secondary process.
126 mlx5_prepare_shared_data(void)
128 const struct rte_memzone *mz;
130 rte_spinlock_lock(&mlx5_shared_data_lock);
131 if (mlx5_shared_data == NULL) {
132 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
133 /* Allocate shared memory. */
134 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
135 sizeof(*mlx5_shared_data),
138 /* Lookup allocated shared memory. */
139 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
142 rte_panic("Cannot allocate mlx5 shared data\n");
143 mlx5_shared_data = mz->addr;
144 /* Initialize shared data. */
145 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
146 LIST_INIT(&mlx5_shared_data->mem_event_cb_list);
147 rte_rwlock_init(&mlx5_shared_data->mem_event_rwlock);
149 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
150 mlx5_mr_mem_event_cb, NULL);
152 rte_spinlock_unlock(&mlx5_shared_data_lock);
156 * Retrieve integer value from environment variable.
159 * Environment variable name.
162 * Integer value, 0 if the variable is not set.
165 mlx5_getenv_int(const char *name)
167 const char *val = getenv(name);
175 * Verbs callback to allocate a memory. This function should allocate the space
176 * according to the size provided residing inside a huge page.
177 * Please note that all allocation must respect the alignment from libmlx5
178 * (i.e. currently sysconf(_SC_PAGESIZE)).
181 * The size in bytes of the memory to allocate.
183 * A pointer to the callback data.
186 * Allocated buffer, NULL otherwise and rte_errno is set.
189 mlx5_alloc_verbs_buf(size_t size, void *data)
191 struct priv *priv = data;
193 size_t alignment = sysconf(_SC_PAGESIZE);
194 unsigned int socket = SOCKET_ID_ANY;
196 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
197 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
199 socket = ctrl->socket;
200 } else if (priv->verbs_alloc_ctx.type ==
201 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
202 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
204 socket = ctrl->socket;
206 assert(data != NULL);
207 ret = rte_malloc_socket(__func__, size, alignment, socket);
214 * Verbs callback to free a memory.
217 * A pointer to the memory to free.
219 * A pointer to the callback data.
222 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
224 assert(data != NULL);
229 * DPDK callback to close the device.
231 * Destroy all queues and objects, free memory.
234 * Pointer to Ethernet device structure.
237 mlx5_dev_close(struct rte_eth_dev *dev)
239 struct priv *priv = dev->data->dev_private;
243 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
245 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
246 /* In case mlx5_dev_stop() has not been called. */
247 mlx5_dev_interrupt_handler_uninstall(dev);
248 mlx5_traffic_disable(dev);
249 mlx5_flow_flush(dev, NULL);
250 /* Prevent crashes when queues are still in use. */
251 dev->rx_pkt_burst = removed_rx_burst;
252 dev->tx_pkt_burst = removed_tx_burst;
253 if (priv->rxqs != NULL) {
254 /* XXX race condition if mlx5_rx_burst() is still running. */
256 for (i = 0; (i != priv->rxqs_n); ++i)
257 mlx5_rxq_release(dev, i);
261 if (priv->txqs != NULL) {
262 /* XXX race condition if mlx5_tx_burst() is still running. */
264 for (i = 0; (i != priv->txqs_n); ++i)
265 mlx5_txq_release(dev, i);
269 mlx5_mprq_free_mp(dev);
270 mlx5_mr_release(dev);
271 if (priv->pd != NULL) {
272 assert(priv->ctx != NULL);
273 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
274 claim_zero(mlx5_glue->close_device(priv->ctx));
276 assert(priv->ctx == NULL);
277 if (priv->rss_conf.rss_key != NULL)
278 rte_free(priv->rss_conf.rss_key);
279 if (priv->reta_idx != NULL)
280 rte_free(priv->reta_idx);
281 if (priv->primary_socket)
282 mlx5_socket_uninit(dev);
284 mlx5_nl_mac_addr_flush(dev);
285 if (priv->nl_socket_route >= 0)
286 close(priv->nl_socket_route);
287 if (priv->nl_socket_rdma >= 0)
288 close(priv->nl_socket_rdma);
289 ret = mlx5_hrxq_ibv_verify(dev);
291 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
293 ret = mlx5_ind_table_ibv_verify(dev);
295 DRV_LOG(WARNING, "port %u some indirection table still remain",
297 ret = mlx5_rxq_ibv_verify(dev);
299 DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain",
301 ret = mlx5_rxq_verify(dev);
303 DRV_LOG(WARNING, "port %u some Rx queues still remain",
305 ret = mlx5_txq_ibv_verify(dev);
307 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
309 ret = mlx5_txq_verify(dev);
311 DRV_LOG(WARNING, "port %u some Tx queues still remain",
313 ret = mlx5_flow_verify(dev);
315 DRV_LOG(WARNING, "port %u some flows still remain",
317 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
319 unsigned int i = mlx5_dev_to_port_id(dev->device, NULL, 0);
322 i = RTE_MIN(mlx5_dev_to_port_id(dev->device, port_id, i), i);
325 rte_eth_devices[port_id[i]].data->dev_private;
328 opriv->domain_id != priv->domain_id ||
329 &rte_eth_devices[port_id[i]] == dev)
334 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
336 memset(priv, 0, sizeof(*priv));
337 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
340 const struct eth_dev_ops mlx5_dev_ops = {
341 .dev_configure = mlx5_dev_configure,
342 .dev_start = mlx5_dev_start,
343 .dev_stop = mlx5_dev_stop,
344 .dev_set_link_down = mlx5_set_link_down,
345 .dev_set_link_up = mlx5_set_link_up,
346 .dev_close = mlx5_dev_close,
347 .promiscuous_enable = mlx5_promiscuous_enable,
348 .promiscuous_disable = mlx5_promiscuous_disable,
349 .allmulticast_enable = mlx5_allmulticast_enable,
350 .allmulticast_disable = mlx5_allmulticast_disable,
351 .link_update = mlx5_link_update,
352 .stats_get = mlx5_stats_get,
353 .stats_reset = mlx5_stats_reset,
354 .xstats_get = mlx5_xstats_get,
355 .xstats_reset = mlx5_xstats_reset,
356 .xstats_get_names = mlx5_xstats_get_names,
357 .dev_infos_get = mlx5_dev_infos_get,
358 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
359 .vlan_filter_set = mlx5_vlan_filter_set,
360 .rx_queue_setup = mlx5_rx_queue_setup,
361 .tx_queue_setup = mlx5_tx_queue_setup,
362 .rx_queue_release = mlx5_rx_queue_release,
363 .tx_queue_release = mlx5_tx_queue_release,
364 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
365 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
366 .mac_addr_remove = mlx5_mac_addr_remove,
367 .mac_addr_add = mlx5_mac_addr_add,
368 .mac_addr_set = mlx5_mac_addr_set,
369 .set_mc_addr_list = mlx5_set_mc_addr_list,
370 .mtu_set = mlx5_dev_set_mtu,
371 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
372 .vlan_offload_set = mlx5_vlan_offload_set,
373 .reta_update = mlx5_dev_rss_reta_update,
374 .reta_query = mlx5_dev_rss_reta_query,
375 .rss_hash_update = mlx5_rss_hash_update,
376 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
377 .filter_ctrl = mlx5_dev_filter_ctrl,
378 .rx_descriptor_status = mlx5_rx_descriptor_status,
379 .tx_descriptor_status = mlx5_tx_descriptor_status,
380 .rx_queue_intr_enable = mlx5_rx_intr_enable,
381 .rx_queue_intr_disable = mlx5_rx_intr_disable,
382 .is_removed = mlx5_is_removed,
385 static const struct eth_dev_ops mlx5_dev_sec_ops = {
386 .stats_get = mlx5_stats_get,
387 .stats_reset = mlx5_stats_reset,
388 .xstats_get = mlx5_xstats_get,
389 .xstats_reset = mlx5_xstats_reset,
390 .xstats_get_names = mlx5_xstats_get_names,
391 .dev_infos_get = mlx5_dev_infos_get,
392 .rx_descriptor_status = mlx5_rx_descriptor_status,
393 .tx_descriptor_status = mlx5_tx_descriptor_status,
396 /* Available operators in flow isolated mode. */
397 const struct eth_dev_ops mlx5_dev_ops_isolate = {
398 .dev_configure = mlx5_dev_configure,
399 .dev_start = mlx5_dev_start,
400 .dev_stop = mlx5_dev_stop,
401 .dev_set_link_down = mlx5_set_link_down,
402 .dev_set_link_up = mlx5_set_link_up,
403 .dev_close = mlx5_dev_close,
404 .promiscuous_enable = mlx5_promiscuous_enable,
405 .promiscuous_disable = mlx5_promiscuous_disable,
406 .allmulticast_enable = mlx5_allmulticast_enable,
407 .allmulticast_disable = mlx5_allmulticast_disable,
408 .link_update = mlx5_link_update,
409 .stats_get = mlx5_stats_get,
410 .stats_reset = mlx5_stats_reset,
411 .xstats_get = mlx5_xstats_get,
412 .xstats_reset = mlx5_xstats_reset,
413 .xstats_get_names = mlx5_xstats_get_names,
414 .dev_infos_get = mlx5_dev_infos_get,
415 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
416 .vlan_filter_set = mlx5_vlan_filter_set,
417 .rx_queue_setup = mlx5_rx_queue_setup,
418 .tx_queue_setup = mlx5_tx_queue_setup,
419 .rx_queue_release = mlx5_rx_queue_release,
420 .tx_queue_release = mlx5_tx_queue_release,
421 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
422 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
423 .mac_addr_remove = mlx5_mac_addr_remove,
424 .mac_addr_add = mlx5_mac_addr_add,
425 .mac_addr_set = mlx5_mac_addr_set,
426 .set_mc_addr_list = mlx5_set_mc_addr_list,
427 .mtu_set = mlx5_dev_set_mtu,
428 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
429 .vlan_offload_set = mlx5_vlan_offload_set,
430 .filter_ctrl = mlx5_dev_filter_ctrl,
431 .rx_descriptor_status = mlx5_rx_descriptor_status,
432 .tx_descriptor_status = mlx5_tx_descriptor_status,
433 .rx_queue_intr_enable = mlx5_rx_intr_enable,
434 .rx_queue_intr_disable = mlx5_rx_intr_disable,
435 .is_removed = mlx5_is_removed,
439 * Verify and store value for device argument.
442 * Key argument to verify.
444 * Value associated with key.
449 * 0 on success, a negative errno value otherwise and rte_errno is set.
452 mlx5_args_check(const char *key, const char *val, void *opaque)
454 struct mlx5_dev_config *config = opaque;
457 /* No-op, port representors are processed in mlx5_dev_spawn(). */
458 if (!strcmp(MLX5_REPRESENTOR, key))
461 tmp = strtoul(val, NULL, 0);
464 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
467 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
468 config->cqe_comp = !!tmp;
469 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
470 config->mprq.enabled = !!tmp;
471 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
472 config->mprq.stride_num_n = tmp;
473 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
474 config->mprq.max_memcpy_len = tmp;
475 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
476 config->mprq.min_rxqs_num = tmp;
477 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
478 config->txq_inline = tmp;
479 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
480 config->txqs_inline = tmp;
481 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
483 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
484 config->mpw_hdr_dseg = !!tmp;
485 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
486 config->inline_max_packet_sz = tmp;
487 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
488 config->tx_vec_en = !!tmp;
489 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
490 config->rx_vec_en = !!tmp;
491 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
492 config->l3_vxlan_en = !!tmp;
493 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
494 config->vf_nl_en = !!tmp;
495 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
496 config->dv_flow_en = !!tmp;
498 DRV_LOG(WARNING, "%s: unknown parameter", key);
506 * Parse device parameters.
509 * Pointer to device configuration structure.
511 * Device arguments structure.
514 * 0 on success, a negative errno value otherwise and rte_errno is set.
517 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
519 const char **params = (const char *[]){
520 MLX5_RXQ_CQE_COMP_EN,
522 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
523 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
526 MLX5_TXQS_MIN_INLINE,
528 MLX5_TXQ_MPW_HDR_DSEG_EN,
529 MLX5_TXQ_MAX_INLINE_LEN,
538 struct rte_kvargs *kvlist;
544 /* Following UGLY cast is done to pass checkpatch. */
545 kvlist = rte_kvargs_parse(devargs->args, params);
548 /* Process parameters. */
549 for (i = 0; (params[i] != NULL); ++i) {
550 if (rte_kvargs_count(kvlist, params[i])) {
551 ret = rte_kvargs_process(kvlist, params[i],
552 mlx5_args_check, config);
555 rte_kvargs_free(kvlist);
560 rte_kvargs_free(kvlist);
564 static struct rte_pci_driver mlx5_driver;
567 * Reserved UAR address space for TXQ UAR(hw doorbell) mapping, process
568 * local resource used by both primary and secondary to avoid duplicate
570 * The space has to be available on both primary and secondary process,
571 * TXQ UAR maps to this area using fixed mmap w/o double check.
573 static void *uar_base;
576 find_lower_va_bound(const struct rte_memseg_list *msl,
577 const struct rte_memseg *ms, void *arg)
586 *addr = RTE_MIN(*addr, ms->addr);
592 * Reserve UAR address space for primary process.
595 * Pointer to Ethernet device.
598 * 0 on success, a negative errno value otherwise and rte_errno is set.
601 mlx5_uar_init_primary(struct rte_eth_dev *dev)
603 struct priv *priv = dev->data->dev_private;
604 void *addr = (void *)0;
606 if (uar_base) { /* UAR address space mapped. */
607 priv->uar_base = uar_base;
610 /* find out lower bound of hugepage segments */
611 rte_memseg_walk(find_lower_va_bound, &addr);
613 /* keep distance to hugepages to minimize potential conflicts. */
614 addr = RTE_PTR_SUB(addr, (uintptr_t)(MLX5_UAR_OFFSET + MLX5_UAR_SIZE));
615 /* anonymous mmap, no real memory consumption. */
616 addr = mmap(addr, MLX5_UAR_SIZE,
617 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
618 if (addr == MAP_FAILED) {
620 "port %u failed to reserve UAR address space, please"
621 " adjust MLX5_UAR_SIZE or try --base-virtaddr",
626 /* Accept either same addr or a new addr returned from mmap if target
629 DRV_LOG(INFO, "port %u reserved UAR address space: %p",
630 dev->data->port_id, addr);
631 priv->uar_base = addr; /* for primary and secondary UAR re-mmap. */
632 uar_base = addr; /* process local, don't reserve again. */
637 * Reserve UAR address space for secondary process, align with
641 * Pointer to Ethernet device.
644 * 0 on success, a negative errno value otherwise and rte_errno is set.
647 mlx5_uar_init_secondary(struct rte_eth_dev *dev)
649 struct priv *priv = dev->data->dev_private;
652 assert(priv->uar_base);
653 if (uar_base) { /* already reserved. */
654 assert(uar_base == priv->uar_base);
657 /* anonymous mmap, no real memory consumption. */
658 addr = mmap(priv->uar_base, MLX5_UAR_SIZE,
659 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
660 if (addr == MAP_FAILED) {
661 DRV_LOG(ERR, "port %u UAR mmap failed: %p size: %llu",
662 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
666 if (priv->uar_base != addr) {
668 "port %u UAR address %p size %llu occupied, please"
669 " adjust MLX5_UAR_OFFSET or try EAL parameter"
671 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
675 uar_base = addr; /* process local, don't reserve again */
676 DRV_LOG(INFO, "port %u reserved UAR address space: %p",
677 dev->data->port_id, addr);
682 * Spawn an Ethernet device from Verbs information.
685 * Backing DPDK device.
689 * If nonzero, enable VF-specific features.
690 * @param[in] switch_info
691 * Switch properties of Ethernet device.
694 * A valid Ethernet device object on success, NULL otherwise and rte_errno
695 * is set. The following error is defined:
697 * EBUSY: device is not supposed to be spawned.
699 static struct rte_eth_dev *
700 mlx5_dev_spawn(struct rte_device *dpdk_dev,
701 struct ibv_device *ibv_dev,
703 const struct mlx5_switch_info *switch_info)
705 struct ibv_context *ctx;
706 struct ibv_device_attr_ex attr;
707 struct ibv_port_attr port_attr;
708 struct ibv_pd *pd = NULL;
709 struct mlx5dv_context dv_attr = { .comp_mask = 0 };
710 struct mlx5_dev_config config = {
712 .mps = MLX5_ARG_UNSET,
716 .txq_inline = MLX5_ARG_UNSET,
717 .txqs_inline = MLX5_ARG_UNSET,
718 .inline_max_packet_sz = MLX5_ARG_UNSET,
722 .stride_num_n = MLX5_MPRQ_STRIDE_NUM_N,
723 .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
724 .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
727 struct rte_eth_dev *eth_dev = NULL;
728 struct priv *priv = NULL;
731 unsigned int cqe_comp;
732 unsigned int tunnel_en = 0;
733 unsigned int mpls_en = 0;
734 unsigned int swp = 0;
735 unsigned int mprq = 0;
736 unsigned int mprq_min_stride_size_n = 0;
737 unsigned int mprq_max_stride_size_n = 0;
738 unsigned int mprq_min_stride_num_n = 0;
739 unsigned int mprq_max_stride_num_n = 0;
740 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
741 struct ibv_counter_set_description cs_desc = { .counter_type = 0 };
743 struct ether_addr mac;
744 char name[RTE_ETH_NAME_MAX_LEN];
745 int own_domain_id = 0;
748 /* Determine if this port representor is supposed to be spawned. */
749 if (switch_info->representor && dpdk_dev->devargs) {
750 struct rte_eth_devargs eth_da;
752 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, ð_da);
755 DRV_LOG(ERR, "failed to process device arguments: %s",
756 strerror(rte_errno));
759 for (i = 0; i < eth_da.nb_representor_ports; ++i)
760 if (eth_da.representor_ports[i] ==
761 (uint16_t)switch_info->port_name)
763 if (i == eth_da.nb_representor_ports) {
768 /* Prepare shared data between primary and secondary process. */
769 mlx5_prepare_shared_data();
771 ctx = mlx5_glue->open_device(ibv_dev);
773 rte_errno = errno ? errno : ENODEV;
776 #ifdef HAVE_IBV_MLX5_MOD_SWP
777 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
780 * Multi-packet send is supported by ConnectX-4 Lx PF as well
781 * as all ConnectX-5 devices.
783 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
784 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
786 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
787 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
789 mlx5_glue->dv_query_device(ctx, &dv_attr);
790 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
791 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
792 DRV_LOG(DEBUG, "enhanced MPW is supported");
793 mps = MLX5_MPW_ENHANCED;
795 DRV_LOG(DEBUG, "MPW is supported");
799 DRV_LOG(DEBUG, "MPW isn't supported");
800 mps = MLX5_MPW_DISABLED;
802 #ifdef HAVE_IBV_MLX5_MOD_SWP
803 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
804 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
805 DRV_LOG(DEBUG, "SWP support: %u", swp);
808 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
809 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
810 struct mlx5dv_striding_rq_caps mprq_caps =
811 dv_attr.striding_rq_caps;
813 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
814 mprq_caps.min_single_stride_log_num_of_bytes);
815 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
816 mprq_caps.max_single_stride_log_num_of_bytes);
817 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
818 mprq_caps.min_single_wqe_log_num_of_strides);
819 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
820 mprq_caps.max_single_wqe_log_num_of_strides);
821 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
822 mprq_caps.supported_qpts);
823 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
825 mprq_min_stride_size_n =
826 mprq_caps.min_single_stride_log_num_of_bytes;
827 mprq_max_stride_size_n =
828 mprq_caps.max_single_stride_log_num_of_bytes;
829 mprq_min_stride_num_n =
830 mprq_caps.min_single_wqe_log_num_of_strides;
831 mprq_max_stride_num_n =
832 mprq_caps.max_single_wqe_log_num_of_strides;
833 config.mprq.stride_num_n = RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
834 mprq_min_stride_num_n);
837 if (RTE_CACHE_LINE_SIZE == 128 &&
838 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
842 config.cqe_comp = cqe_comp;
843 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
844 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
845 tunnel_en = ((dv_attr.tunnel_offloads_caps &
846 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
847 (dv_attr.tunnel_offloads_caps &
848 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE));
850 DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
851 tunnel_en ? "" : "not ");
854 "tunnel offloading disabled due to old OFED/rdma-core version");
856 config.tunnel_en = tunnel_en;
857 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
858 mpls_en = ((dv_attr.tunnel_offloads_caps &
859 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
860 (dv_attr.tunnel_offloads_caps &
861 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
862 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
863 mpls_en ? "" : "not ");
865 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
866 " old OFED/rdma-core version or firmware configuration");
868 config.mpls_en = mpls_en;
869 err = mlx5_glue->query_device_ex(ctx, NULL, &attr);
871 DEBUG("ibv_query_device_ex() failed");
874 if (!switch_info->representor)
875 rte_strlcpy(name, dpdk_dev->name, sizeof(name));
877 snprintf(name, sizeof(name), "%s_representor_%u",
878 dpdk_dev->name, switch_info->port_name);
879 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
880 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
881 eth_dev = rte_eth_dev_attach_secondary(name);
882 if (eth_dev == NULL) {
883 DRV_LOG(ERR, "can not attach rte ethdev");
888 eth_dev->device = dpdk_dev;
889 eth_dev->dev_ops = &mlx5_dev_sec_ops;
890 err = mlx5_uar_init_secondary(eth_dev);
895 /* Receive command fd from primary process */
896 err = mlx5_socket_connect(eth_dev);
901 /* Remap UAR for Tx queues. */
902 err = mlx5_tx_uar_remap(eth_dev, err);
908 * Ethdev pointer is still required as input since
909 * the primary device is not accessible from the
912 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev);
913 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev);
914 claim_zero(mlx5_glue->close_device(ctx));
917 /* Check port status. */
918 err = mlx5_glue->query_port(ctx, 1, &port_attr);
920 DRV_LOG(ERR, "port query failed: %s", strerror(err));
923 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
924 DRV_LOG(ERR, "port is not configured in Ethernet mode");
928 if (port_attr.state != IBV_PORT_ACTIVE)
929 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)",
930 mlx5_glue->port_state_str(port_attr.state),
932 /* Allocate protection domain. */
933 pd = mlx5_glue->alloc_pd(ctx);
935 DRV_LOG(ERR, "PD allocation failure");
939 priv = rte_zmalloc("ethdev private structure",
941 RTE_CACHE_LINE_SIZE);
943 DRV_LOG(ERR, "priv allocation failure");
948 strncpy(priv->ibdev_name, priv->ctx->device->name,
949 sizeof(priv->ibdev_name));
950 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path,
951 sizeof(priv->ibdev_path));
952 priv->device_attr = attr;
954 priv->mtu = ETHER_MTU;
956 /* Initialize UAR access locks for 32bit implementations. */
957 rte_spinlock_init(&priv->uar_lock_cq);
958 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
959 rte_spinlock_init(&priv->uar_lock[i]);
961 /* Some internal functions rely on Netlink sockets, open them now. */
962 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA);
963 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE);
965 priv->representor = !!switch_info->representor;
966 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
967 priv->representor_id =
968 switch_info->representor ? switch_info->port_name : -1;
970 * Look for sibling devices in order to reuse their switch domain
971 * if any, otherwise allocate one.
973 i = mlx5_dev_to_port_id(dpdk_dev, NULL, 0);
977 i = RTE_MIN(mlx5_dev_to_port_id(dpdk_dev, port_id, i), i);
979 const struct priv *opriv =
980 rte_eth_devices[port_id[i]].data->dev_private;
984 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
986 priv->domain_id = opriv->domain_id;
990 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
991 err = rte_eth_switch_domain_alloc(&priv->domain_id);
994 DRV_LOG(ERR, "unable to allocate switch domain: %s",
995 strerror(rte_errno));
1000 err = mlx5_args(&config, dpdk_dev->devargs);
1003 DRV_LOG(ERR, "failed to process device arguments: %s",
1004 strerror(rte_errno));
1007 config.hw_csum = !!(attr.device_cap_flags_ex & IBV_DEVICE_RAW_IP_CSUM);
1008 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
1009 (config.hw_csum ? "" : "not "));
1010 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
1011 config.flow_counter_en = !!attr.max_counter_sets;
1012 mlx5_glue->describe_counter_set(ctx, 0, &cs_desc);
1013 DRV_LOG(DEBUG, "counter type = %d, num of cs = %ld, attributes = %d",
1014 cs_desc.counter_type, cs_desc.num_of_cs,
1015 cs_desc.attributes);
1017 config.ind_table_max_size =
1018 attr.rss_caps.max_rwq_indirection_table_size;
1020 * Remove this check once DPDK supports larger/variable
1021 * indirection tables.
1023 if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
1024 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
1025 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
1026 config.ind_table_max_size);
1027 config.hw_vlan_strip = !!(attr.raw_packet_caps &
1028 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
1029 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
1030 (config.hw_vlan_strip ? "" : "not "));
1031 config.hw_fcs_strip = !!(attr.raw_packet_caps &
1032 IBV_RAW_PACKET_CAP_SCATTER_FCS);
1033 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
1034 (config.hw_fcs_strip ? "" : "not "));
1035 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
1036 config.hw_padding = !!attr.rx_pad_end_addr_align;
1038 DRV_LOG(DEBUG, "hardware Rx end alignment padding is %ssupported",
1039 (config.hw_padding ? "" : "not "));
1040 config.tso = (attr.tso_caps.max_tso > 0 &&
1041 (attr.tso_caps.supported_qpts &
1042 (1 << IBV_QPT_RAW_PACKET)));
1044 config.tso_max_payload_sz = attr.tso_caps.max_tso;
1046 * MPW is disabled by default, while the Enhanced MPW is enabled
1049 if (config.mps == MLX5_ARG_UNSET)
1050 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED :
1053 config.mps = config.mps ? mps : MLX5_MPW_DISABLED;
1054 DRV_LOG(INFO, "%sMPS is %s",
1055 config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "",
1056 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
1057 if (config.cqe_comp && !cqe_comp) {
1058 DRV_LOG(WARNING, "Rx CQE compression isn't supported");
1059 config.cqe_comp = 0;
1061 if (config.mprq.enabled && mprq) {
1062 if (config.mprq.stride_num_n > mprq_max_stride_num_n ||
1063 config.mprq.stride_num_n < mprq_min_stride_num_n) {
1064 config.mprq.stride_num_n =
1065 RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
1066 mprq_min_stride_num_n);
1068 "the number of strides"
1069 " for Multi-Packet RQ is out of range,"
1070 " setting default value (%u)",
1071 1 << config.mprq.stride_num_n);
1073 config.mprq.min_stride_size_n = mprq_min_stride_size_n;
1074 config.mprq.max_stride_size_n = mprq_max_stride_size_n;
1075 } else if (config.mprq.enabled && !mprq) {
1076 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
1077 config.mprq.enabled = 0;
1079 eth_dev = rte_eth_dev_allocate(name);
1080 if (eth_dev == NULL) {
1081 DRV_LOG(ERR, "can not allocate rte ethdev");
1085 if (priv->representor)
1086 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
1087 eth_dev->data->dev_private = priv;
1088 priv->dev_data = eth_dev->data;
1089 eth_dev->data->mac_addrs = priv->mac;
1090 eth_dev->device = dpdk_dev;
1091 eth_dev->device->driver = &mlx5_driver.driver;
1092 err = mlx5_uar_init_primary(eth_dev);
1097 /* Configure the first MAC address by default. */
1098 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
1100 "port %u cannot get MAC address, is mlx5_en"
1101 " loaded? (errno: %s)",
1102 eth_dev->data->port_id, strerror(rte_errno));
1107 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
1108 eth_dev->data->port_id,
1109 mac.addr_bytes[0], mac.addr_bytes[1],
1110 mac.addr_bytes[2], mac.addr_bytes[3],
1111 mac.addr_bytes[4], mac.addr_bytes[5]);
1114 char ifname[IF_NAMESIZE];
1116 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
1117 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
1118 eth_dev->data->port_id, ifname);
1120 DRV_LOG(DEBUG, "port %u ifname is unknown",
1121 eth_dev->data->port_id);
1124 /* Get actual MTU if possible. */
1125 err = mlx5_get_mtu(eth_dev, &priv->mtu);
1130 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
1132 /* Initialize burst functions to prevent crashes before link-up. */
1133 eth_dev->rx_pkt_burst = removed_rx_burst;
1134 eth_dev->tx_pkt_burst = removed_tx_burst;
1135 eth_dev->dev_ops = &mlx5_dev_ops;
1136 /* Register MAC address. */
1137 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
1138 if (vf && config.vf_nl_en)
1139 mlx5_nl_mac_addr_sync(eth_dev);
1140 TAILQ_INIT(&priv->flows);
1141 TAILQ_INIT(&priv->ctrl_flows);
1142 /* Hint libmlx5 to use PMD allocator for data plane resources */
1143 struct mlx5dv_ctx_allocators alctr = {
1144 .alloc = &mlx5_alloc_verbs_buf,
1145 .free = &mlx5_free_verbs_buf,
1148 mlx5_glue->dv_set_context_attr(ctx, MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
1149 (void *)((uintptr_t)&alctr));
1150 /* Bring Ethernet device up. */
1151 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
1152 eth_dev->data->port_id);
1153 mlx5_set_link_up(eth_dev);
1155 * Even though the interrupt handler is not installed yet,
1156 * interrupts will still trigger on the asyn_fd from
1157 * Verbs context returned by ibv_open_device().
1159 mlx5_link_update(eth_dev, 0);
1160 /* Store device configuration on private structure. */
1161 priv->config = config;
1162 /* Supported Verbs flow priority number detection. */
1163 err = mlx5_flow_discover_priorities(eth_dev);
1166 priv->config.flow_prio = err;
1168 * Once the device is added to the list of memory event
1169 * callback, its global MR cache table cannot be expanded
1170 * on the fly because of deadlock. If it overflows, lookup
1171 * should be done by searching MR list linearly, which is slow.
1173 err = mlx5_mr_btree_init(&priv->mr.cache,
1174 MLX5_MR_BTREE_CACHE_N * 2,
1175 eth_dev->device->numa_node);
1180 /* Add device to memory callback list. */
1181 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1182 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1183 priv, mem_event_cb);
1184 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1188 if (priv->nl_socket_route >= 0)
1189 close(priv->nl_socket_route);
1190 if (priv->nl_socket_rdma >= 0)
1191 close(priv->nl_socket_rdma);
1193 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1197 claim_zero(mlx5_glue->dealloc_pd(pd));
1199 rte_eth_dev_release_port(eth_dev);
1201 claim_zero(mlx5_glue->close_device(ctx));
1207 /** Data associated with devices to spawn. */
1208 struct mlx5_dev_spawn_data {
1209 unsigned int ifindex; /**< Network interface index. */
1210 struct mlx5_switch_info info; /**< Switch information. */
1211 struct ibv_device *ibv_dev; /**< Associated IB device. */
1212 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
1216 * Comparison callback to sort device data.
1218 * This is meant to be used with qsort().
1221 * Pointer to pointer to first data object.
1223 * Pointer to pointer to second data object.
1226 * 0 if both objects are equal, less than 0 if the first argument is less
1227 * than the second, greater than 0 otherwise.
1230 mlx5_dev_spawn_data_cmp(const void *a, const void *b)
1232 const struct mlx5_switch_info *si_a =
1233 &((const struct mlx5_dev_spawn_data *)a)->info;
1234 const struct mlx5_switch_info *si_b =
1235 &((const struct mlx5_dev_spawn_data *)b)->info;
1238 /* Master device first. */
1239 ret = si_b->master - si_a->master;
1242 /* Then representor devices. */
1243 ret = si_b->representor - si_a->representor;
1246 /* Unidentified devices come last in no specific order. */
1247 if (!si_a->representor)
1249 /* Order representors by name. */
1250 return si_a->port_name - si_b->port_name;
1254 * DPDK callback to register a PCI device.
1256 * This function spawns Ethernet devices out of a given PCI device.
1258 * @param[in] pci_drv
1259 * PCI driver structure (mlx5_driver).
1260 * @param[in] pci_dev
1261 * PCI device information.
1264 * 0 on success, a negative errno value otherwise and rte_errno is set.
1267 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1268 struct rte_pci_device *pci_dev)
1270 struct ibv_device **ibv_list;
1275 assert(pci_drv == &mlx5_driver);
1277 ibv_list = mlx5_glue->get_device_list(&ret);
1279 rte_errno = errno ? errno : ENOSYS;
1280 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?");
1284 struct ibv_device *ibv_match[ret + 1];
1287 struct rte_pci_addr pci_addr;
1289 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name);
1290 if (mlx5_ibv_device_to_pci_addr(ibv_list[ret], &pci_addr))
1292 if (pci_dev->addr.domain != pci_addr.domain ||
1293 pci_dev->addr.bus != pci_addr.bus ||
1294 pci_dev->addr.devid != pci_addr.devid ||
1295 pci_dev->addr.function != pci_addr.function)
1297 DRV_LOG(INFO, "PCI information matches for device \"%s\"",
1298 ibv_list[ret]->name);
1299 ibv_match[n++] = ibv_list[ret];
1301 ibv_match[n] = NULL;
1303 struct mlx5_dev_spawn_data list[n];
1304 int nl_route = n ? mlx5_nl_init(NETLINK_ROUTE) : -1;
1305 int nl_rdma = n ? mlx5_nl_init(NETLINK_RDMA) : -1;
1310 * The existence of several matching entries (n > 1) means port
1311 * representors have been instantiated. No existing Verbs call nor
1312 * /sys entries can tell them apart, this can only be done through
1313 * Netlink calls assuming kernel drivers are recent enough to
1316 * In the event of identification failure through Netlink, try again
1317 * through sysfs, then either:
1319 * 1. No device matches (n == 0), complain and bail out.
1320 * 2. A single IB device matches (n == 1) and is not a representor,
1321 * assume no switch support.
1322 * 3. Otherwise no safe assumptions can be made; complain louder and
1325 for (i = 0; i != n; ++i) {
1326 list[i].ibv_dev = ibv_match[i];
1327 list[i].eth_dev = NULL;
1329 list[i].ifindex = 0;
1331 list[i].ifindex = mlx5_nl_ifindex
1332 (nl_rdma, list[i].ibv_dev->name);
1335 mlx5_nl_switch_info(nl_route, list[i].ifindex,
1337 ((!list[i].info.representor && !list[i].info.master) &&
1338 mlx5_sysfs_switch_info(list[i].ifindex, &list[i].info))) {
1339 list[i].ifindex = 0;
1340 memset(&list[i].info, 0, sizeof(list[i].info));
1348 /* Count unidentified devices. */
1349 for (u = 0, i = 0; i != n; ++i)
1350 if (!list[i].info.master && !list[i].info.representor)
1353 if (n == 1 && u == 1) {
1355 DRV_LOG(INFO, "no switch support detected");
1359 "unable to tell which of the matching devices"
1360 " is the master (lack of kernel support?)");
1365 * Sort list to probe devices in natural order for users convenience
1366 * (i.e. master first, then representors from lowest to highest ID).
1369 qsort(list, n, sizeof(*list), mlx5_dev_spawn_data_cmp);
1370 switch (pci_dev->id.device_id) {
1371 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1372 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1373 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1374 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1380 for (i = 0; i != n; ++i) {
1383 list[i].eth_dev = mlx5_dev_spawn
1384 (&pci_dev->device, list[i].ibv_dev, vf, &list[i].info);
1385 if (!list[i].eth_dev) {
1386 if (rte_errno != EBUSY)
1388 /* Device is disabled, ignore it. */
1391 restore = list[i].eth_dev->data->dev_flags;
1392 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev);
1393 /* Restore non-PCI flags cleared by the above call. */
1394 list[i].eth_dev->data->dev_flags |= restore;
1395 rte_eth_dev_probing_finish(list[i].eth_dev);
1397 mlx5_glue->free_device_list(ibv_list);
1400 "no Verbs device matches PCI device " PCI_PRI_FMT ","
1401 " are kernel drivers loaded?",
1402 pci_dev->addr.domain, pci_dev->addr.bus,
1403 pci_dev->addr.devid, pci_dev->addr.function);
1406 } else if (i != n) {
1408 "probe of PCI device " PCI_PRI_FMT " aborted after"
1409 " encountering an error: %s",
1410 pci_dev->addr.domain, pci_dev->addr.bus,
1411 pci_dev->addr.devid, pci_dev->addr.function,
1412 strerror(rte_errno));
1416 if (!list[i].eth_dev)
1418 mlx5_dev_close(list[i].eth_dev);
1419 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
1420 rte_free(list[i].eth_dev->data->dev_private);
1421 claim_zero(rte_eth_dev_release_port(list[i].eth_dev));
1423 /* Restore original error. */
1431 static const struct rte_pci_id mlx5_pci_id_map[] = {
1433 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1434 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1437 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1438 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1441 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1442 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1445 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1446 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1449 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1450 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1453 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1454 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1457 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1458 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1461 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1462 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1465 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1466 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
1469 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1470 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
1477 static struct rte_pci_driver mlx5_driver = {
1479 .name = MLX5_DRIVER_NAME
1481 .id_table = mlx5_pci_id_map,
1482 .probe = mlx5_pci_probe,
1483 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV,
1486 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1489 * Suffix RTE_EAL_PMD_PATH with "-glue".
1491 * This function performs a sanity check on RTE_EAL_PMD_PATH before
1492 * suffixing its last component.
1495 * Output buffer, should be large enough otherwise NULL is returned.
1500 * Pointer to @p buf or @p NULL in case suffix cannot be appended.
1503 mlx5_glue_path(char *buf, size_t size)
1505 static const char *const bad[] = { "/", ".", "..", NULL };
1506 const char *path = RTE_EAL_PMD_PATH;
1507 size_t len = strlen(path);
1511 while (len && path[len - 1] == '/')
1513 for (off = len; off && path[off - 1] != '/'; --off)
1515 for (i = 0; bad[i]; ++i)
1516 if (!strncmp(path + off, bad[i], (int)(len - off)))
1518 i = snprintf(buf, size, "%.*s-glue", (int)len, path);
1519 if (i == -1 || (size_t)i >= size)
1524 "unable to append \"-glue\" to last component of"
1525 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\"),"
1526 " please re-configure DPDK");
1531 * Initialization routine for run-time dependency on rdma-core.
1534 mlx5_glue_init(void)
1536 char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")];
1537 const char *path[] = {
1539 * A basic security check is necessary before trusting
1540 * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH.
1542 (geteuid() == getuid() && getegid() == getgid() ?
1543 getenv("MLX5_GLUE_PATH") : NULL),
1545 * When RTE_EAL_PMD_PATH is set, use its glue-suffixed
1546 * variant, otherwise let dlopen() look up libraries on its
1549 (*RTE_EAL_PMD_PATH ?
1550 mlx5_glue_path(glue_path, sizeof(glue_path)) : ""),
1553 void *handle = NULL;
1557 while (!handle && i != RTE_DIM(path)) {
1566 end = strpbrk(path[i], ":;");
1568 end = path[i] + strlen(path[i]);
1569 len = end - path[i];
1574 ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE,
1576 (!len || *(end - 1) == '/') ? "" : "/");
1579 if (sizeof(name) != (size_t)ret + 1)
1581 DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"",
1583 handle = dlopen(name, RTLD_LAZY);
1594 DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg);
1597 sym = dlsym(handle, "mlx5_glue");
1598 if (!sym || !*sym) {
1602 DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg);
1611 "cannot initialize PMD due to missing run-time dependency on"
1612 " rdma-core libraries (libibverbs, libmlx5)");
1619 * Driver initialization routine.
1621 RTE_INIT(rte_mlx5_pmd_init)
1623 /* Initialize driver log type. */
1624 mlx5_logtype = rte_log_register("pmd.net.mlx5");
1625 if (mlx5_logtype >= 0)
1626 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
1628 /* Build the static tables for Verbs conversion. */
1629 mlx5_set_ptype_table();
1630 mlx5_set_cksum_table();
1631 mlx5_set_swp_types_table();
1633 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
1634 * huge pages. Calling ibv_fork_init() during init allows
1635 * applications to use fork() safely for purposes other than
1636 * using this PMD, which is not supported in forked processes.
1638 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
1639 /* Match the size of Rx completion entry to the size of a cacheline. */
1640 if (RTE_CACHE_LINE_SIZE == 128)
1641 setenv("MLX5_CQE_SIZE", "128", 0);
1643 * MLX5_DEVICE_FATAL_CLEANUP tells ibv_destroy functions to
1644 * cleanup all the Verbs resources even when the device was removed.
1646 setenv("MLX5_DEVICE_FATAL_CLEANUP", "1", 1);
1647 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1648 if (mlx5_glue_init())
1653 /* Glue structure must not contain any NULL pointers. */
1657 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i)
1658 assert(((const void *const *)mlx5_glue)[i]);
1661 if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) {
1663 "rdma-core glue \"%s\" mismatch: \"%s\" is required",
1664 mlx5_glue->version, MLX5_GLUE_VERSION);
1667 mlx5_glue->fork_init();
1668 rte_pci_register(&mlx5_driver);
1671 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1672 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1673 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");