drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12 #include <net/if.h>
  13 #include <sys/mman.h>
  14 #include <linux/rtnetlink.h>
  15
  16 /* Verbs header. */
  17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  18 #ifdef PEDANTIC
  19 #pragma GCC diagnostic ignored "-Wpedantic"
  20 #endif
  21 #include <infiniband/verbs.h>
  22 #ifdef PEDANTIC
  23 #pragma GCC diagnostic error "-Wpedantic"
  24 #endif
  25
  26 #include <rte_malloc.h>
  27 #include <rte_ethdev_driver.h>
  28 #include <rte_ethdev_pci.h>
  29 #include <rte_pci.h>
  30 #include <rte_bus_pci.h>
  31 #include <rte_common.h>
  32 #include <rte_kvargs.h>
  33 #include <rte_rwlock.h>
  34 #include <rte_spinlock.h>
  35 #include <rte_string_fns.h>
  36 #include <rte_alarm.h>
  37
  38 #include <mlx5_glue.h>
  39 #include <mlx5_devx_cmds.h>
  40 #include <mlx5_common.h>
  41 #include <mlx5_common_mp.h>
  42
  43 #include "mlx5_defs.h"
  44 #include "mlx5.h"
  45 #include "mlx5_utils.h"
  46 #include "mlx5_rxtx.h"
  47 #include "mlx5_autoconf.h"
  48 #include "mlx5_mr.h"
  49 #include "mlx5_flow.h"
  50 #include "rte_pmd_mlx5.h"
  51
  52 /* Device parameter to enable RX completion queue compression. */
  53 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  54
  55 /* Device parameter to enable RX completion entry padding to 128B. */
  56 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
  57
  58 /* Device parameter to enable padding Rx packet to cacheline size. */
  59 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  60
  61 /* Device parameter to enable Multi-Packet Rx queue. */
  62 #define MLX5_RX_MPRQ_EN "mprq_en"
  63
  64 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  65 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  66
  67 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  68 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  69
  70 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  71 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  72
  73 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  74 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  75
  76 /* Device parameter to configure inline send. Deprecated, ignored.*/
  77 #define MLX5_TXQ_INLINE "txq_inline"
  78
  79 /* Device parameter to limit packet size to inline with ordinary SEND. */
  80 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  81
  82 /* Device parameter to configure minimal data size to inline. */
  83 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  84
  85 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  86 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  87
  88 /*
  89  * Device parameter to configure the number of TX queues threshold for
  90  * enabling inline send.
  91  */
  92 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  93
  94 /*
  95  * Device parameter to configure the number of TX queues threshold for
  96  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  97  */
  98 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  99
 100 /* Device parameter to enable multi-packet send WQEs. */
 101 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
 102
 103 /*
 104  * Device parameter to force doorbell register mapping
 105  * to non-cahed region eliminating the extra write memory barrier.
 106  */
 107 #define MLX5_TX_DB_NC "tx_db_nc"
 108
 109 /*
 110  * Device parameter to include 2 dsegs in the title WQEBB.
 111  * Deprecated, ignored.
 112  */
 113 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 114
 115 /*
 116  * Device parameter to limit the size of inlining packet.
 117  * Deprecated, ignored.
 118  */
 119 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 120
 121 /*
 122  * Device parameter to enable hardware Tx vector.
 123  * Deprecated, ignored (no vectorized Tx routines anymore).
 124  */
 125 #define MLX5_TX_VEC_EN "tx_vec_en"
 126
 127 /* Device parameter to enable hardware Rx vector. */
 128 #define MLX5_RX_VEC_EN "rx_vec_en"
 129
 130 /* Allow L3 VXLAN flow creation. */
 131 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 132
 133 /* Activate DV E-Switch flow steering. */
 134 #define MLX5_DV_ESW_EN "dv_esw_en"
 135
 136 /* Activate DV flow steering. */
 137 #define MLX5_DV_FLOW_EN "dv_flow_en"
 138
 139 /* Enable extensive flow metadata support. */
 140 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 141
 142 /* Activate Netlink support in VF mode. */
 143 #define MLX5_VF_NL_EN "vf_nl_en"
 144
 145 /* Enable extending memsegs when creating a MR. */
 146 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 147
 148 /* Select port representors to instantiate. */
 149 #define MLX5_REPRESENTOR "representor"
 150
 151 /* Device parameter to configure the maximum number of dump files per queue. */
 152 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 153
 154 /* Configure timeout of LRO session (in microseconds). */
 155 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 156
 157 /*
 158  * Device parameter to configure the total data buffer size for a single
 159  * hairpin queue (logarithm value).
 160  */
 161 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 162
 163 /* Flow memory reclaim mode. */
 164 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 165
 166 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
 167
 168 /* Shared memory between primary and secondary processes. */
 169 struct mlx5_shared_data *mlx5_shared_data;
 170
 171 /* Spinlock for mlx5_shared_data allocation. */
 172 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
 173
 174 /* Process local data for secondary processes. */
 175 static struct mlx5_local_data mlx5_local_data;
 176 /** Driver-specific log messages type. */
 177 int mlx5_logtype;
 178
 179 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_ibv_list = LIST_HEAD_INITIALIZER();
 180 static pthread_mutex_t mlx5_ibv_list_mutex = PTHREAD_MUTEX_INITIALIZER;
 181
 182 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 183 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 184         {
 185                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 186                 .trunk_size = 64,
 187                 .grow_trunk = 3,
 188                 .grow_shift = 2,
 189                 .need_lock = 0,
 190                 .release_mem_en = 1,
 191                 .malloc = rte_malloc_socket,
 192                 .free = rte_free,
 193                 .type = "mlx5_encap_decap_ipool",
 194         },
 195         {
 196                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 197                 .trunk_size = 64,
 198                 .grow_trunk = 3,
 199                 .grow_shift = 2,
 200                 .need_lock = 0,
 201                 .release_mem_en = 1,
 202                 .malloc = rte_malloc_socket,
 203                 .free = rte_free,
 204                 .type = "mlx5_push_vlan_ipool",
 205         },
 206         {
 207                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 208                 .trunk_size = 64,
 209                 .grow_trunk = 3,
 210                 .grow_shift = 2,
 211                 .need_lock = 0,
 212                 .release_mem_en = 1,
 213                 .malloc = rte_malloc_socket,
 214                 .free = rte_free,
 215                 .type = "mlx5_tag_ipool",
 216         },
 217         {
 218                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 219                 .trunk_size = 64,
 220                 .grow_trunk = 3,
 221                 .grow_shift = 2,
 222                 .need_lock = 0,
 223                 .release_mem_en = 1,
 224                 .malloc = rte_malloc_socket,
 225                 .free = rte_free,
 226                 .type = "mlx5_port_id_ipool",
 227         },
 228         {
 229                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 230                 .trunk_size = 64,
 231                 .grow_trunk = 3,
 232                 .grow_shift = 2,
 233                 .need_lock = 0,
 234                 .release_mem_en = 1,
 235                 .malloc = rte_malloc_socket,
 236                 .free = rte_free,
 237                 .type = "mlx5_jump_ipool",
 238         },
 239 #endif
 240         {
 241                 .size = sizeof(struct mlx5_flow_meter),
 242                 .trunk_size = 64,
 243                 .grow_trunk = 3,
 244                 .grow_shift = 2,
 245                 .need_lock = 0,
 246                 .release_mem_en = 1,
 247                 .malloc = rte_malloc_socket,
 248                 .free = rte_free,
 249                 .type = "mlx5_meter_ipool",
 250         },
 251         {
 252                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 253                 .trunk_size = 64,
 254                 .grow_trunk = 3,
 255                 .grow_shift = 2,
 256                 .need_lock = 0,
 257                 .release_mem_en = 1,
 258                 .malloc = rte_malloc_socket,
 259                 .free = rte_free,
 260                 .type = "mlx5_mcp_ipool",
 261         },
 262         {
 263                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 264                 .trunk_size = 64,
 265                 .grow_trunk = 3,
 266                 .grow_shift = 2,
 267                 .need_lock = 0,
 268                 .release_mem_en = 1,
 269                 .malloc = rte_malloc_socket,
 270                 .free = rte_free,
 271                 .type = "mlx5_hrxq_ipool",
 272         },
 273         {
 274                 /*
 275                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 276                  * It set in run time according to PCI function configuration.
 277                  */
 278                 .size = 0,
 279                 .trunk_size = 64,
 280                 .grow_trunk = 3,
 281                 .grow_shift = 2,
 282                 .need_lock = 0,
 283                 .release_mem_en = 1,
 284                 .malloc = rte_malloc_socket,
 285                 .free = rte_free,
 286                 .type = "mlx5_flow_handle_ipool",
 287         },
 288         {
 289                 .size = sizeof(struct rte_flow),
 290                 .trunk_size = 4096,
 291                 .need_lock = 1,
 292                 .release_mem_en = 1,
 293                 .malloc = rte_malloc_socket,
 294                 .free = rte_free,
 295                 .type = "rte_flow_ipool",
 296         },
 297 };
 298
 299
 300 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 301 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 302
 303 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 304
 305 /**
 306  * Allocate ID pool structure.
 307  *
 308  * @param[in] max_id
 309  *   The maximum id can be allocated from the pool.
 310  *
 311  * @return
 312  *   Pointer to pool object, NULL value otherwise.
 313  */
 314 struct mlx5_flow_id_pool *
 315 mlx5_flow_id_pool_alloc(uint32_t max_id)
 316 {
 317         struct mlx5_flow_id_pool *pool;
 318         void *mem;
 319
 320         pool = rte_zmalloc("id pool allocation", sizeof(*pool),
 321                            RTE_CACHE_LINE_SIZE);
 322         if (!pool) {
 323                 DRV_LOG(ERR, "can't allocate id pool");
 324                 rte_errno  = ENOMEM;
 325                 return NULL;
 326         }
 327         mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
 328                           RTE_CACHE_LINE_SIZE);
 329         if (!mem) {
 330                 DRV_LOG(ERR, "can't allocate mem for id pool");
 331                 rte_errno  = ENOMEM;
 332                 goto error;
 333         }
 334         pool->free_arr = mem;
 335         pool->curr = pool->free_arr;
 336         pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
 337         pool->base_index = 0;
 338         pool->max_id = max_id;
 339         return pool;
 340 error:
 341         rte_free(pool);
 342         return NULL;
 343 }
 344
 345 /**
 346  * Release ID pool structure.
 347  *
 348  * @param[in] pool
 349  *   Pointer to flow id pool object to free.
 350  */
 351 void
 352 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
 353 {
 354         rte_free(pool->free_arr);
 355         rte_free(pool);
 356 }
 357
 358 /**
 359  * Generate ID.
 360  *
 361  * @param[in] pool
 362  *   Pointer to flow id pool.
 363  * @param[out] id
 364  *   The generated ID.
 365  *
 366  * @return
 367  *   0 on success, error value otherwise.
 368  */
 369 uint32_t
 370 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
 371 {
 372         if (pool->curr == pool->free_arr) {
 373                 if (pool->base_index == pool->max_id) {
 374                         rte_errno  = ENOMEM;
 375                         DRV_LOG(ERR, "no free id");
 376                         return -rte_errno;
 377                 }
 378                 *id = ++pool->base_index;
 379                 return 0;
 380         }
 381         *id = *(--pool->curr);
 382         return 0;
 383 }
 384
 385 /**
 386  * Release ID.
 387  *
 388  * @param[in] pool
 389  *   Pointer to flow id pool.
 390  * @param[out] id
 391  *   The generated ID.
 392  *
 393  * @return
 394  *   0 on success, error value otherwise.
 395  */
 396 uint32_t
 397 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
 398 {
 399         uint32_t size;
 400         uint32_t size2;
 401         void *mem;
 402
 403         if (pool->curr == pool->last) {
 404                 size = pool->curr - pool->free_arr;
 405                 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
 406                 MLX5_ASSERT(size2 > size);
 407                 mem = rte_malloc("", size2 * sizeof(uint32_t), 0);
 408                 if (!mem) {
 409                         DRV_LOG(ERR, "can't allocate mem for id pool");
 410                         rte_errno  = ENOMEM;
 411                         return -rte_errno;
 412                 }
 413                 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
 414                 rte_free(pool->free_arr);
 415                 pool->free_arr = mem;
 416                 pool->curr = pool->free_arr + size;
 417                 pool->last = pool->free_arr + size2;
 418         }
 419         *pool->curr = id;
 420         pool->curr++;
 421         return 0;
 422 }
 423
 424 /**
 425  * Initialize the shared aging list information per port.
 426  *
 427  * @param[in] sh
 428  *   Pointer to mlx5_dev_ctx_shared object.
 429  */
 430 static void
 431 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 432 {
 433         uint32_t i;
 434         struct mlx5_age_info *age_info;
 435
 436         for (i = 0; i < sh->max_port; i++) {
 437                 age_info = &sh->port[i].age_info;
 438                 age_info->flags = 0;
 439                 TAILQ_INIT(&age_info->aged_counters);
 440                 rte_spinlock_init(&age_info->aged_sl);
 441                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 442         }
 443 }
 444
 445 /**
 446  * Initialize the counters management structure.
 447  *
 448  * @param[in] sh
 449  *   Pointer to mlx5_dev_ctx_shared object to free
 450  */
 451 static void
 452 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 453 {
 454         int i;
 455
 456         memset(&sh->cmng, 0, sizeof(sh->cmng));
 457         TAILQ_INIT(&sh->cmng.flow_counters);
 458         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 459                 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
 460                 rte_spinlock_init(&sh->cmng.ccont[i].resize_sl);
 461         }
 462 }
 463
 464 /**
 465  * Destroy all the resources allocated for a counter memory management.
 466  *
 467  * @param[in] mng
 468  *   Pointer to the memory management structure.
 469  */
 470 static void
 471 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 472 {
 473         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 474
 475         LIST_REMOVE(mng, next);
 476         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 477         claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
 478         rte_free(mem);
 479 }
 480
 481 /**
 482  * Close and release all the resources of the counters management.
 483  *
 484  * @param[in] sh
 485  *   Pointer to mlx5_dev_ctx_shared object to free.
 486  */
 487 static void
 488 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 489 {
 490         struct mlx5_counter_stats_mem_mng *mng;
 491         int i;
 492         int j;
 493         int retries = 1024;
 494
 495         rte_errno = 0;
 496         while (--retries) {
 497                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 498                 if (rte_errno != EINPROGRESS)
 499                         break;
 500                 rte_pause();
 501         }
 502         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 503                 struct mlx5_flow_counter_pool *pool;
 504                 uint32_t batch = !!(i > 1);
 505
 506                 if (!sh->cmng.ccont[i].pools)
 507                         continue;
 508                 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 509                 while (pool) {
 510                         if (batch && pool->min_dcs)
 511                                 claim_zero(mlx5_devx_cmd_destroy
 512                                                                (pool->min_dcs));
 513                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 514                                 if (MLX5_POOL_GET_CNT(pool, j)->action)
 515                                         claim_zero
 516                                          (mlx5_glue->destroy_flow_action
 517                                           (MLX5_POOL_GET_CNT
 518                                           (pool, j)->action));
 519                                 if (!batch && MLX5_GET_POOL_CNT_EXT
 520                                     (pool, j)->dcs)
 521                                         claim_zero(mlx5_devx_cmd_destroy
 522                                                    (MLX5_GET_POOL_CNT_EXT
 523                                                     (pool, j)->dcs));
 524                         }
 525                         TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, next);
 526                         rte_free(pool);
 527                         pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 528                 }
 529                 rte_free(sh->cmng.ccont[i].pools);
 530         }
 531         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 532         while (mng) {
 533                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 534                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 535         }
 536         memset(&sh->cmng, 0, sizeof(sh->cmng));
 537 }
 538
 539 /**
 540  * Initialize the flow resources' indexed mempool.
 541  *
 542  * @param[in] sh
 543  *   Pointer to mlx5_dev_ctx_shared object.
 544  * @param[in] sh
 545  *   Pointer to user dev config.
 546  */
 547 static void
 548 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 549                        const struct mlx5_dev_config *config)
 550 {
 551         uint8_t i;
 552         struct mlx5_indexed_pool_config cfg;
 553
 554         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 555                 cfg = mlx5_ipool_cfg[i];
 556                 switch (i) {
 557                 default:
 558                         break;
 559                 /*
 560                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 561                  * according to PCI function flow configuration.
 562                  */
 563                 case MLX5_IPOOL_MLX5_FLOW:
 564                         cfg.size = config->dv_flow_en ?
 565                                 sizeof(struct mlx5_flow_handle) :
 566                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 567                         break;
 568                 }
 569                 if (config->reclaim_mode)
 570                         cfg.release_mem_en = 1;
 571                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 572         }
 573 }
 574
 575 /**
 576  * Release the flow resources' indexed mempool.
 577  *
 578  * @param[in] sh
 579  *   Pointer to mlx5_dev_ctx_shared object.
 580  */
 581 static void
 582 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 583 {
 584         uint8_t i;
 585
 586         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 587                 mlx5_ipool_destroy(sh->ipool[i]);
 588 }
 589
 590 /**
 591  * Allocate shared IB device context. If there is multiport device the
 592  * master and representors will share this context, if there is single
 593  * port dedicated IB device, the context will be used by only given
 594  * port due to unification.
 595  *
 596  * Routine first searches the context for the specified IB device name,
 597  * if found the shared context assumed and reference counter is incremented.
 598  * If no context found the new one is created and initialized with specified
 599  * IB device context and parameters.
 600  *
 601  * @param[in] spawn
 602  *   Pointer to the IB device attributes (name, port, etc).
 603  * @param[in] config
 604  *   Pointer to device configuration structure.
 605  *
 606  * @return
 607  *   Pointer to mlx5_dev_ctx_shared object on success,
 608  *   otherwise NULL and rte_errno is set.
 609  */
 610 struct mlx5_dev_ctx_shared *
 611 mlx5_alloc_shared_ibctx(const struct mlx5_dev_spawn_data *spawn,
 612                         const struct mlx5_dev_config *config)
 613 {
 614         struct mlx5_dev_ctx_shared *sh;
 615         int err = 0;
 616         uint32_t i;
 617         struct mlx5_devx_tis_attr tis_attr = { 0 };
 618
 619         MLX5_ASSERT(spawn);
 620         /* Secondary process should not create the shared context. */
 621         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 622         pthread_mutex_lock(&mlx5_ibv_list_mutex);
 623         /* Search for IB context by device name. */
 624         LIST_FOREACH(sh, &mlx5_ibv_list, next) {
 625                 if (!strcmp(sh->ibdev_name,
 626                         mlx5_os_get_dev_device_name(spawn->phys_dev))) {
 627                         sh->refcnt++;
 628                         goto exit;
 629                 }
 630         }
 631         /* No device found, we have to create new shared context. */
 632         MLX5_ASSERT(spawn->max_port);
 633         sh = rte_zmalloc("ethdev shared ib context",
 634                          sizeof(struct mlx5_dev_ctx_shared) +
 635                          spawn->max_port *
 636                          sizeof(struct mlx5_ibv_shared_port),
 637                          RTE_CACHE_LINE_SIZE);
 638         if (!sh) {
 639                 DRV_LOG(ERR, "shared context allocation failure");
 640                 rte_errno  = ENOMEM;
 641                 goto exit;
 642         }
 643         err = mlx5_os_open_device(spawn, config, sh);
 644         if (!sh->ctx)
 645                 goto error;
 646         err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
 647         if (err) {
 648                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
 649                 goto error;
 650         }
 651         sh->refcnt = 1;
 652         sh->max_port = spawn->max_port;
 653         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
 654                 sizeof(sh->ibdev_name) - 1);
 655         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
 656                 sizeof(sh->ibdev_path) - 1);
 657         /*
 658          * Setting port_id to max unallowed value means
 659          * there is no interrupt subhandler installed for
 660          * the given port index i.
 661          */
 662         for (i = 0; i < sh->max_port; i++) {
 663                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 664                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
 665         }
 666         sh->pd = mlx5_glue->alloc_pd(sh->ctx);
 667         if (sh->pd == NULL) {
 668                 DRV_LOG(ERR, "PD allocation failure");
 669                 err = ENOMEM;
 670                 goto error;
 671         }
 672         if (sh->devx) {
 673                 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
 674                 if (err) {
 675                         DRV_LOG(ERR, "Fail to extract pdn from PD");
 676                         goto error;
 677                 }
 678                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
 679                 if (!sh->td) {
 680                         DRV_LOG(ERR, "TD allocation failure");
 681                         err = ENOMEM;
 682                         goto error;
 683                 }
 684                 tis_attr.transport_domain = sh->td->id;
 685                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
 686                 if (!sh->tis) {
 687                         DRV_LOG(ERR, "TIS allocation failure");
 688                         err = ENOMEM;
 689                         goto error;
 690                 }
 691         }
 692         sh->flow_id_pool = mlx5_flow_id_pool_alloc
 693                                         ((1 << HAIRPIN_FLOW_ID_BITS) - 1);
 694         if (!sh->flow_id_pool) {
 695                 DRV_LOG(ERR, "can't create flow id pool");
 696                 err = ENOMEM;
 697                 goto error;
 698         }
 699         /*
 700          * Once the device is added to the list of memory event
 701          * callback, its global MR cache table cannot be expanded
 702          * on the fly because of deadlock. If it overflows, lookup
 703          * should be done by searching MR list linearly, which is slow.
 704          *
 705          * At this point the device is not added to the memory
 706          * event list yet, context is just being created.
 707          */
 708         err = mlx5_mr_btree_init(&sh->share_cache.cache,
 709                                  MLX5_MR_BTREE_CACHE_N * 2,
 710                                  spawn->pci_dev->device.numa_node);
 711         if (err) {
 712                 err = rte_errno;
 713                 goto error;
 714         }
 715         mlx5_os_dev_shared_handler_install(sh);
 716         mlx5_flow_aging_init(sh);
 717         mlx5_flow_counters_mng_init(sh);
 718         mlx5_flow_ipool_create(sh, config);
 719         /* Add device to memory callback list. */
 720         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 721         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
 722                          sh, mem_event_cb);
 723         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 724         /* Add context to the global device list. */
 725         LIST_INSERT_HEAD(&mlx5_ibv_list, sh, next);
 726 exit:
 727         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 728         return sh;
 729 error:
 730         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 731         MLX5_ASSERT(sh);
 732         if (sh->tis)
 733                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 734         if (sh->td)
 735                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 736         if (sh->pd)
 737                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 738         if (sh->ctx)
 739                 claim_zero(mlx5_glue->close_device(sh->ctx));
 740         if (sh->flow_id_pool)
 741                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 742         rte_free(sh);
 743         MLX5_ASSERT(err > 0);
 744         rte_errno = err;
 745         return NULL;
 746 }
 747
 748 /**
 749  * Free shared IB device context. Decrement counter and if zero free
 750  * all allocated resources and close handles.
 751  *
 752  * @param[in] sh
 753  *   Pointer to mlx5_dev_ctx_shared object to free
 754  */
 755 void
 756 mlx5_free_shared_ibctx(struct mlx5_dev_ctx_shared *sh)
 757 {
 758         pthread_mutex_lock(&mlx5_ibv_list_mutex);
 759 #ifdef RTE_LIBRTE_MLX5_DEBUG
 760         /* Check the object presence in the list. */
 761         struct mlx5_dev_ctx_shared *lctx;
 762
 763         LIST_FOREACH(lctx, &mlx5_ibv_list, next)
 764                 if (lctx == sh)
 765                         break;
 766         MLX5_ASSERT(lctx);
 767         if (lctx != sh) {
 768                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
 769                 goto exit;
 770         }
 771 #endif
 772         MLX5_ASSERT(sh);
 773         MLX5_ASSERT(sh->refcnt);
 774         /* Secondary process should not free the shared context. */
 775         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 776         if (--sh->refcnt)
 777                 goto exit;
 778         /* Remove from memory callback device list. */
 779         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 780         LIST_REMOVE(sh, mem_event_cb);
 781         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 782         /* Release created Memory Regions. */
 783         mlx5_mr_release_cache(&sh->share_cache);
 784         /* Remove context from the global device list. */
 785         LIST_REMOVE(sh, next);
 786         /*
 787          *  Ensure there is no async event handler installed.
 788          *  Only primary process handles async device events.
 789          **/
 790         mlx5_flow_counters_mng_close(sh);
 791         mlx5_flow_ipool_destroy(sh);
 792         mlx5_os_dev_shared_handler_uninstall(sh);
 793         if (sh->pd)
 794                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 795         if (sh->tis)
 796                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 797         if (sh->td)
 798                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 799         if (sh->ctx)
 800                 claim_zero(mlx5_glue->close_device(sh->ctx));
 801         if (sh->flow_id_pool)
 802                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 803         rte_free(sh);
 804 exit:
 805         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 806 }
 807
 808 /**
 809  * Destroy table hash list and all the root entries per domain.
 810  *
 811  * @param[in] priv
 812  *   Pointer to the private device data structure.
 813  */
 814 void
 815 mlx5_free_table_hash_list(struct mlx5_priv *priv)
 816 {
 817         struct mlx5_dev_ctx_shared *sh = priv->sh;
 818         struct mlx5_flow_tbl_data_entry *tbl_data;
 819         union mlx5_flow_tbl_key table_key = {
 820                 {
 821                         .table_id = 0,
 822                         .reserved = 0,
 823                         .domain = 0,
 824                         .direction = 0,
 825                 }
 826         };
 827         struct mlx5_hlist_entry *pos;
 828
 829         if (!sh->flow_tbls)
 830                 return;
 831         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 832         if (pos) {
 833                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 834                                         entry);
 835                 MLX5_ASSERT(tbl_data);
 836                 mlx5_hlist_remove(sh->flow_tbls, pos);
 837                 rte_free(tbl_data);
 838         }
 839         table_key.direction = 1;
 840         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 841         if (pos) {
 842                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 843                                         entry);
 844                 MLX5_ASSERT(tbl_data);
 845                 mlx5_hlist_remove(sh->flow_tbls, pos);
 846                 rte_free(tbl_data);
 847         }
 848         table_key.direction = 0;
 849         table_key.domain = 1;
 850         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 851         if (pos) {
 852                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 853                                         entry);
 854                 MLX5_ASSERT(tbl_data);
 855                 mlx5_hlist_remove(sh->flow_tbls, pos);
 856                 rte_free(tbl_data);
 857         }
 858         mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
 859 }
 860
 861 /**
 862  * Initialize flow table hash list and create the root tables entry
 863  * for each domain.
 864  *
 865  * @param[in] priv
 866  *   Pointer to the private device data structure.
 867  *
 868  * @return
 869  *   Zero on success, positive error code otherwise.
 870  */
 871 int
 872 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
 873 {
 874         struct mlx5_dev_ctx_shared *sh = priv->sh;
 875         char s[MLX5_HLIST_NAMESIZE];
 876         int err = 0;
 877
 878         MLX5_ASSERT(sh);
 879         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
 880         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
 881         if (!sh->flow_tbls) {
 882                 DRV_LOG(ERR, "flow tables with hash creation failed.\n");
 883                 err = ENOMEM;
 884                 return err;
 885         }
 886 #ifndef HAVE_MLX5DV_DR
 887         /*
 888          * In case we have not DR support, the zero tables should be created
 889          * because DV expect to see them even if they cannot be created by
 890          * RDMA-CORE.
 891          */
 892         union mlx5_flow_tbl_key table_key = {
 893                 {
 894                         .table_id = 0,
 895                         .reserved = 0,
 896                         .domain = 0,
 897                         .direction = 0,
 898                 }
 899         };
 900         struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL,
 901                                                           sizeof(*tbl_data), 0);
 902
 903         if (!tbl_data) {
 904                 err = ENOMEM;
 905                 goto error;
 906         }
 907         tbl_data->entry.key = table_key.v64;
 908         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 909         if (err)
 910                 goto error;
 911         rte_atomic32_init(&tbl_data->tbl.refcnt);
 912         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 913         table_key.direction = 1;
 914         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 915         if (!tbl_data) {
 916                 err = ENOMEM;
 917                 goto error;
 918         }
 919         tbl_data->entry.key = table_key.v64;
 920         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 921         if (err)
 922                 goto error;
 923         rte_atomic32_init(&tbl_data->tbl.refcnt);
 924         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 925         table_key.direction = 0;
 926         table_key.domain = 1;
 927         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 928         if (!tbl_data) {
 929                 err = ENOMEM;
 930                 goto error;
 931         }
 932         tbl_data->entry.key = table_key.v64;
 933         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 934         if (err)
 935                 goto error;
 936         rte_atomic32_init(&tbl_data->tbl.refcnt);
 937         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 938         return err;
 939 error:
 940         mlx5_free_table_hash_list(priv);
 941 #endif /* HAVE_MLX5DV_DR */
 942         return err;
 943 }
 944
 945 /**
 946  * Initialize shared data between primary and secondary process.
 947  *
 948  * A memzone is reserved by primary process and secondary processes attach to
 949  * the memzone.
 950  *
 951  * @return
 952  *   0 on success, a negative errno value otherwise and rte_errno is set.
 953  */
 954 static int
 955 mlx5_init_shared_data(void)
 956 {
 957         const struct rte_memzone *mz;
 958         int ret = 0;
 959
 960         rte_spinlock_lock(&mlx5_shared_data_lock);
 961         if (mlx5_shared_data == NULL) {
 962                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
 963                         /* Allocate shared memory. */
 964                         mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
 965                                                  sizeof(*mlx5_shared_data),
 966                                                  SOCKET_ID_ANY, 0);
 967                         if (mz == NULL) {
 968                                 DRV_LOG(ERR,
 969                                         "Cannot allocate mlx5 shared data");
 970                                 ret = -rte_errno;
 971                                 goto error;
 972                         }
 973                         mlx5_shared_data = mz->addr;
 974                         memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
 975                         rte_spinlock_init(&mlx5_shared_data->lock);
 976                 } else {
 977                         /* Lookup allocated shared memory. */
 978                         mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
 979                         if (mz == NULL) {
 980                                 DRV_LOG(ERR,
 981                                         "Cannot attach mlx5 shared data");
 982                                 ret = -rte_errno;
 983                                 goto error;
 984                         }
 985                         mlx5_shared_data = mz->addr;
 986                         memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
 987                 }
 988         }
 989 error:
 990         rte_spinlock_unlock(&mlx5_shared_data_lock);
 991         return ret;
 992 }
 993
 994 /**
 995  * Retrieve integer value from environment variable.
 996  *
 997  * @param[in] name
 998  *   Environment variable name.
 999  *
1000  * @return
1001  *   Integer value, 0 if the variable is not set.
1002  */
1003 int
1004 mlx5_getenv_int(const char *name)
1005 {
1006         const char *val = getenv(name);
1007
1008         if (val == NULL)
1009                 return 0;
1010         return atoi(val);
1011 }
1012
1013 /**
1014  * DPDK callback to add udp tunnel port
1015  *
1016  * @param[in] dev
1017  *   A pointer to eth_dev
1018  * @param[in] udp_tunnel
1019  *   A pointer to udp tunnel
1020  *
1021  * @return
1022  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1023  */
1024 int
1025 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1026                          struct rte_eth_udp_tunnel *udp_tunnel)
1027 {
1028         MLX5_ASSERT(udp_tunnel != NULL);
1029         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1030             udp_tunnel->udp_port == 4789)
1031                 return 0;
1032         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1033             udp_tunnel->udp_port == 4790)
1034                 return 0;
1035         return -ENOTSUP;
1036 }
1037
1038 /**
1039  * Initialize process private data structure.
1040  *
1041  * @param dev
1042  *   Pointer to Ethernet device structure.
1043  *
1044  * @return
1045  *   0 on success, a negative errno value otherwise and rte_errno is set.
1046  */
1047 int
1048 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1049 {
1050         struct mlx5_priv *priv = dev->data->dev_private;
1051         struct mlx5_proc_priv *ppriv;
1052         size_t ppriv_size;
1053
1054         /*
1055          * UAR register table follows the process private structure. BlueFlame
1056          * registers for Tx queues are stored in the table.
1057          */
1058         ppriv_size =
1059                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1060         ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
1061                                   RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1062         if (!ppriv) {
1063                 rte_errno = ENOMEM;
1064                 return -rte_errno;
1065         }
1066         ppriv->uar_table_sz = ppriv_size;
1067         dev->process_private = ppriv;
1068         return 0;
1069 }
1070
1071 /**
1072  * Un-initialize process private data structure.
1073  *
1074  * @param dev
1075  *   Pointer to Ethernet device structure.
1076  */
1077 static void
1078 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1079 {
1080         if (!dev->process_private)
1081                 return;
1082         rte_free(dev->process_private);
1083         dev->process_private = NULL;
1084 }
1085
1086 /**
1087  * DPDK callback to close the device.
1088  *
1089  * Destroy all queues and objects, free memory.
1090  *
1091  * @param dev
1092  *   Pointer to Ethernet device structure.
1093  */
1094 void
1095 mlx5_dev_close(struct rte_eth_dev *dev)
1096 {
1097         struct mlx5_priv *priv = dev->data->dev_private;
1098         unsigned int i;
1099         int ret;
1100
1101         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1102                 /* Check if process_private released. */
1103                 if (!dev->process_private)
1104                         return;
1105                 mlx5_tx_uar_uninit_secondary(dev);
1106                 mlx5_proc_priv_uninit(dev);
1107                 rte_eth_dev_release_port(dev);
1108                 return;
1109         }
1110         if (!priv->sh)
1111                 return;
1112         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1113                 dev->data->port_id,
1114                 ((priv->sh->ctx != NULL) ?
1115                 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1116         /*
1117          * If default mreg copy action is removed at the stop stage,
1118          * the search will return none and nothing will be done anymore.
1119          */
1120         mlx5_flow_stop_default(dev);
1121         mlx5_traffic_disable(dev);
1122         /*
1123          * If all the flows are already flushed in the device stop stage,
1124          * then this will return directly without any action.
1125          */
1126         mlx5_flow_list_flush(dev, &priv->flows, true);
1127         mlx5_flow_meter_flush(dev, NULL);
1128         /* Free the intermediate buffers for flow creation. */
1129         mlx5_flow_free_intermediate(dev);
1130         /* Prevent crashes when queues are still in use. */
1131         dev->rx_pkt_burst = removed_rx_burst;
1132         dev->tx_pkt_burst = removed_tx_burst;
1133         rte_wmb();
1134         /* Disable datapath on secondary process. */
1135         mlx5_mp_req_stop_rxtx(dev);
1136         if (priv->rxqs != NULL) {
1137                 /* XXX race condition if mlx5_rx_burst() is still running. */
1138                 usleep(1000);
1139                 for (i = 0; (i != priv->rxqs_n); ++i)
1140                         mlx5_rxq_release(dev, i);
1141                 priv->rxqs_n = 0;
1142                 priv->rxqs = NULL;
1143         }
1144         if (priv->txqs != NULL) {
1145                 /* XXX race condition if mlx5_tx_burst() is still running. */
1146                 usleep(1000);
1147                 for (i = 0; (i != priv->txqs_n); ++i)
1148                         mlx5_txq_release(dev, i);
1149                 priv->txqs_n = 0;
1150                 priv->txqs = NULL;
1151         }
1152         mlx5_proc_priv_uninit(dev);
1153         if (priv->mreg_cp_tbl)
1154                 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1155         mlx5_mprq_free_mp(dev);
1156         mlx5_os_free_shared_dr(priv);
1157         if (priv->rss_conf.rss_key != NULL)
1158                 rte_free(priv->rss_conf.rss_key);
1159         if (priv->reta_idx != NULL)
1160                 rte_free(priv->reta_idx);
1161         if (priv->config.vf)
1162                 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1163                                        dev->data->mac_addrs,
1164                                        MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1165         if (priv->nl_socket_route >= 0)
1166                 close(priv->nl_socket_route);
1167         if (priv->nl_socket_rdma >= 0)
1168                 close(priv->nl_socket_rdma);
1169         if (priv->vmwa_context)
1170                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1171         ret = mlx5_hrxq_verify(dev);
1172         if (ret)
1173                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1174                         dev->data->port_id);
1175         ret = mlx5_ind_table_obj_verify(dev);
1176         if (ret)
1177                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1178                         dev->data->port_id);
1179         ret = mlx5_rxq_obj_verify(dev);
1180         if (ret)
1181                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1182                         dev->data->port_id);
1183         ret = mlx5_rxq_verify(dev);
1184         if (ret)
1185                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1186                         dev->data->port_id);
1187         ret = mlx5_txq_obj_verify(dev);
1188         if (ret)
1189                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1190                         dev->data->port_id);
1191         ret = mlx5_txq_verify(dev);
1192         if (ret)
1193                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1194                         dev->data->port_id);
1195         ret = mlx5_flow_verify(dev);
1196         if (ret)
1197                 DRV_LOG(WARNING, "port %u some flows still remain",
1198                         dev->data->port_id);
1199         /*
1200          * Free the shared context in last turn, because the cleanup
1201          * routines above may use some shared fields, like
1202          * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1203          * ifindex if Netlink fails.
1204          */
1205         mlx5_free_shared_ibctx(priv->sh);
1206         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1207                 unsigned int c = 0;
1208                 uint16_t port_id;
1209
1210                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1211                         struct mlx5_priv *opriv =
1212                                 rte_eth_devices[port_id].data->dev_private;
1213
1214                         if (!opriv ||
1215                             opriv->domain_id != priv->domain_id ||
1216                             &rte_eth_devices[port_id] == dev)
1217                                 continue;
1218                         ++c;
1219                         break;
1220                 }
1221                 if (!c)
1222                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1223         }
1224         memset(priv, 0, sizeof(*priv));
1225         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1226         /*
1227          * Reset mac_addrs to NULL such that it is not freed as part of
1228          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1229          * it is freed when dev_private is freed.
1230          */
1231         dev->data->mac_addrs = NULL;
1232 }
1233
1234 const struct eth_dev_ops mlx5_dev_ops = {
1235         .dev_configure = mlx5_dev_configure,
1236         .dev_start = mlx5_dev_start,
1237         .dev_stop = mlx5_dev_stop,
1238         .dev_set_link_down = mlx5_set_link_down,
1239         .dev_set_link_up = mlx5_set_link_up,
1240         .dev_close = mlx5_dev_close,
1241         .promiscuous_enable = mlx5_promiscuous_enable,
1242         .promiscuous_disable = mlx5_promiscuous_disable,
1243         .allmulticast_enable = mlx5_allmulticast_enable,
1244         .allmulticast_disable = mlx5_allmulticast_disable,
1245         .link_update = mlx5_link_update,
1246         .stats_get = mlx5_stats_get,
1247         .stats_reset = mlx5_stats_reset,
1248         .xstats_get = mlx5_xstats_get,
1249         .xstats_reset = mlx5_xstats_reset,
1250         .xstats_get_names = mlx5_xstats_get_names,
1251         .fw_version_get = mlx5_fw_version_get,
1252         .dev_infos_get = mlx5_dev_infos_get,
1253         .read_clock = mlx5_read_clock,
1254         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1255         .vlan_filter_set = mlx5_vlan_filter_set,
1256         .rx_queue_setup = mlx5_rx_queue_setup,
1257         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1258         .tx_queue_setup = mlx5_tx_queue_setup,
1259         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1260         .rx_queue_release = mlx5_rx_queue_release,
1261         .tx_queue_release = mlx5_tx_queue_release,
1262         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1263         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1264         .mac_addr_remove = mlx5_mac_addr_remove,
1265         .mac_addr_add = mlx5_mac_addr_add,
1266         .mac_addr_set = mlx5_mac_addr_set,
1267         .set_mc_addr_list = mlx5_set_mc_addr_list,
1268         .mtu_set = mlx5_dev_set_mtu,
1269         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1270         .vlan_offload_set = mlx5_vlan_offload_set,
1271         .reta_update = mlx5_dev_rss_reta_update,
1272         .reta_query = mlx5_dev_rss_reta_query,
1273         .rss_hash_update = mlx5_rss_hash_update,
1274         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1275         .filter_ctrl = mlx5_dev_filter_ctrl,
1276         .rx_descriptor_status = mlx5_rx_descriptor_status,
1277         .tx_descriptor_status = mlx5_tx_descriptor_status,
1278         .rxq_info_get = mlx5_rxq_info_get,
1279         .txq_info_get = mlx5_txq_info_get,
1280         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1281         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1282         .rx_queue_count = mlx5_rx_queue_count,
1283         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1284         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1285         .is_removed = mlx5_is_removed,
1286         .udp_tunnel_port_add  = mlx5_udp_tunnel_port_add,
1287         .get_module_info = mlx5_get_module_info,
1288         .get_module_eeprom = mlx5_get_module_eeprom,
1289         .hairpin_cap_get = mlx5_hairpin_cap_get,
1290         .mtr_ops_get = mlx5_flow_meter_ops_get,
1291 };
1292
1293 /* Available operations from secondary process. */
1294 const struct eth_dev_ops mlx5_dev_sec_ops = {
1295         .stats_get = mlx5_stats_get,
1296         .stats_reset = mlx5_stats_reset,
1297         .xstats_get = mlx5_xstats_get,
1298         .xstats_reset = mlx5_xstats_reset,
1299         .xstats_get_names = mlx5_xstats_get_names,
1300         .fw_version_get = mlx5_fw_version_get,
1301         .dev_infos_get = mlx5_dev_infos_get,
1302         .rx_descriptor_status = mlx5_rx_descriptor_status,
1303         .tx_descriptor_status = mlx5_tx_descriptor_status,
1304         .rxq_info_get = mlx5_rxq_info_get,
1305         .txq_info_get = mlx5_txq_info_get,
1306         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1307         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1308         .get_module_info = mlx5_get_module_info,
1309         .get_module_eeprom = mlx5_get_module_eeprom,
1310 };
1311
1312 /* Available operations in flow isolated mode. */
1313 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1314         .dev_configure = mlx5_dev_configure,
1315         .dev_start = mlx5_dev_start,
1316         .dev_stop = mlx5_dev_stop,
1317         .dev_set_link_down = mlx5_set_link_down,
1318         .dev_set_link_up = mlx5_set_link_up,
1319         .dev_close = mlx5_dev_close,
1320         .promiscuous_enable = mlx5_promiscuous_enable,
1321         .promiscuous_disable = mlx5_promiscuous_disable,
1322         .allmulticast_enable = mlx5_allmulticast_enable,
1323         .allmulticast_disable = mlx5_allmulticast_disable,
1324         .link_update = mlx5_link_update,
1325         .stats_get = mlx5_stats_get,
1326         .stats_reset = mlx5_stats_reset,
1327         .xstats_get = mlx5_xstats_get,
1328         .xstats_reset = mlx5_xstats_reset,
1329         .xstats_get_names = mlx5_xstats_get_names,
1330         .fw_version_get = mlx5_fw_version_get,
1331         .dev_infos_get = mlx5_dev_infos_get,
1332         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1333         .vlan_filter_set = mlx5_vlan_filter_set,
1334         .rx_queue_setup = mlx5_rx_queue_setup,
1335         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1336         .tx_queue_setup = mlx5_tx_queue_setup,
1337         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1338         .rx_queue_release = mlx5_rx_queue_release,
1339         .tx_queue_release = mlx5_tx_queue_release,
1340         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1341         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1342         .mac_addr_remove = mlx5_mac_addr_remove,
1343         .mac_addr_add = mlx5_mac_addr_add,
1344         .mac_addr_set = mlx5_mac_addr_set,
1345         .set_mc_addr_list = mlx5_set_mc_addr_list,
1346         .mtu_set = mlx5_dev_set_mtu,
1347         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1348         .vlan_offload_set = mlx5_vlan_offload_set,
1349         .filter_ctrl = mlx5_dev_filter_ctrl,
1350         .rx_descriptor_status = mlx5_rx_descriptor_status,
1351         .tx_descriptor_status = mlx5_tx_descriptor_status,
1352         .rxq_info_get = mlx5_rxq_info_get,
1353         .txq_info_get = mlx5_txq_info_get,
1354         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1355         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1356         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1357         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1358         .is_removed = mlx5_is_removed,
1359         .get_module_info = mlx5_get_module_info,
1360         .get_module_eeprom = mlx5_get_module_eeprom,
1361         .hairpin_cap_get = mlx5_hairpin_cap_get,
1362         .mtr_ops_get = mlx5_flow_meter_ops_get,
1363 };
1364
1365 /**
1366  * Verify and store value for device argument.
1367  *
1368  * @param[in] key
1369  *   Key argument to verify.
1370  * @param[in] val
1371  *   Value associated with key.
1372  * @param opaque
1373  *   User data.
1374  *
1375  * @return
1376  *   0 on success, a negative errno value otherwise and rte_errno is set.
1377  */
1378 static int
1379 mlx5_args_check(const char *key, const char *val, void *opaque)
1380 {
1381         struct mlx5_dev_config *config = opaque;
1382         unsigned long tmp;
1383
1384         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1385         if (!strcmp(MLX5_REPRESENTOR, key))
1386                 return 0;
1387         errno = 0;
1388         tmp = strtoul(val, NULL, 0);
1389         if (errno) {
1390                 rte_errno = errno;
1391                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1392                 return -rte_errno;
1393         }
1394         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1395                 config->cqe_comp = !!tmp;
1396         } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1397                 config->cqe_pad = !!tmp;
1398         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1399                 config->hw_padding = !!tmp;
1400         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1401                 config->mprq.enabled = !!tmp;
1402         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1403                 config->mprq.stride_num_n = tmp;
1404         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1405                 config->mprq.stride_size_n = tmp;
1406         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1407                 config->mprq.max_memcpy_len = tmp;
1408         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1409                 config->mprq.min_rxqs_num = tmp;
1410         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1411                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1412                                  " converted to txq_inline_max", key);
1413                 config->txq_inline_max = tmp;
1414         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1415                 config->txq_inline_max = tmp;
1416         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1417                 config->txq_inline_min = tmp;
1418         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1419                 config->txq_inline_mpw = tmp;
1420         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1421                 config->txqs_inline = tmp;
1422         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1423                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1424         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1425                 config->mps = !!tmp;
1426         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1427                 if (tmp != MLX5_TXDB_CACHED &&
1428                     tmp != MLX5_TXDB_NCACHED &&
1429                     tmp != MLX5_TXDB_HEURISTIC) {
1430                         DRV_LOG(ERR, "invalid Tx doorbell "
1431                                      "mapping parameter");
1432                         rte_errno = EINVAL;
1433                         return -rte_errno;
1434                 }
1435                 config->dbnc = tmp;
1436         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1437                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1438         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1439                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1440                                  " converted to txq_inline_mpw", key);
1441                 config->txq_inline_mpw = tmp;
1442         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1443                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1444         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1445                 config->rx_vec_en = !!tmp;
1446         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1447                 config->l3_vxlan_en = !!tmp;
1448         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1449                 config->vf_nl_en = !!tmp;
1450         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1451                 config->dv_esw_en = !!tmp;
1452         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1453                 config->dv_flow_en = !!tmp;
1454         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1455                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1456                     tmp != MLX5_XMETA_MODE_META16 &&
1457                     tmp != MLX5_XMETA_MODE_META32) {
1458                         DRV_LOG(ERR, "invalid extensive "
1459                                      "metadata parameter");
1460                         rte_errno = EINVAL;
1461                         return -rte_errno;
1462                 }
1463                 config->dv_xmeta_en = tmp;
1464         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1465                 config->mr_ext_memseg_en = !!tmp;
1466         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1467                 config->max_dump_files_num = tmp;
1468         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1469                 config->lro.timeout = tmp;
1470         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1471                 DRV_LOG(DEBUG, "class argument is %s.", val);
1472         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1473                 config->log_hp_size = tmp;
1474         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1475                 if (tmp != MLX5_RCM_NONE &&
1476                     tmp != MLX5_RCM_LIGHT &&
1477                     tmp != MLX5_RCM_AGGR) {
1478                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1479                         rte_errno = EINVAL;
1480                         return -rte_errno;
1481                 }
1482                 config->reclaim_mode = tmp;
1483         } else {
1484                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1485                 rte_errno = EINVAL;
1486                 return -rte_errno;
1487         }
1488         return 0;
1489 }
1490
1491 /**
1492  * Parse device parameters.
1493  *
1494  * @param config
1495  *   Pointer to device configuration structure.
1496  * @param devargs
1497  *   Device arguments structure.
1498  *
1499  * @return
1500  *   0 on success, a negative errno value otherwise and rte_errno is set.
1501  */
1502 int
1503 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1504 {
1505         const char **params = (const char *[]){
1506                 MLX5_RXQ_CQE_COMP_EN,
1507                 MLX5_RXQ_CQE_PAD_EN,
1508                 MLX5_RXQ_PKT_PAD_EN,
1509                 MLX5_RX_MPRQ_EN,
1510                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1511                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1512                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1513                 MLX5_RXQS_MIN_MPRQ,
1514                 MLX5_TXQ_INLINE,
1515                 MLX5_TXQ_INLINE_MIN,
1516                 MLX5_TXQ_INLINE_MAX,
1517                 MLX5_TXQ_INLINE_MPW,
1518                 MLX5_TXQS_MIN_INLINE,
1519                 MLX5_TXQS_MAX_VEC,
1520                 MLX5_TXQ_MPW_EN,
1521                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1522                 MLX5_TXQ_MAX_INLINE_LEN,
1523                 MLX5_TX_DB_NC,
1524                 MLX5_TX_VEC_EN,
1525                 MLX5_RX_VEC_EN,
1526                 MLX5_L3_VXLAN_EN,
1527                 MLX5_VF_NL_EN,
1528                 MLX5_DV_ESW_EN,
1529                 MLX5_DV_FLOW_EN,
1530                 MLX5_DV_XMETA_EN,
1531                 MLX5_MR_EXT_MEMSEG_EN,
1532                 MLX5_REPRESENTOR,
1533                 MLX5_MAX_DUMP_FILES_NUM,
1534                 MLX5_LRO_TIMEOUT_USEC,
1535                 MLX5_CLASS_ARG_NAME,
1536                 MLX5_HP_BUF_SIZE,
1537                 MLX5_RECLAIM_MEM,
1538                 NULL,
1539         };
1540         struct rte_kvargs *kvlist;
1541         int ret = 0;
1542         int i;
1543
1544         if (devargs == NULL)
1545                 return 0;
1546         /* Following UGLY cast is done to pass checkpatch. */
1547         kvlist = rte_kvargs_parse(devargs->args, params);
1548         if (kvlist == NULL) {
1549                 rte_errno = EINVAL;
1550                 return -rte_errno;
1551         }
1552         /* Process parameters. */
1553         for (i = 0; (params[i] != NULL); ++i) {
1554                 if (rte_kvargs_count(kvlist, params[i])) {
1555                         ret = rte_kvargs_process(kvlist, params[i],
1556                                                  mlx5_args_check, config);
1557                         if (ret) {
1558                                 rte_errno = EINVAL;
1559                                 rte_kvargs_free(kvlist);
1560                                 return -rte_errno;
1561                         }
1562                 }
1563         }
1564         rte_kvargs_free(kvlist);
1565         return 0;
1566 }
1567
1568 /**
1569  * PMD global initialization.
1570  *
1571  * Independent from individual device, this function initializes global
1572  * per-PMD data structures distinguishing primary and secondary processes.
1573  * Hence, each initialization is called once per a process.
1574  *
1575  * @return
1576  *   0 on success, a negative errno value otherwise and rte_errno is set.
1577  */
1578 int
1579 mlx5_init_once(void)
1580 {
1581         struct mlx5_shared_data *sd;
1582         struct mlx5_local_data *ld = &mlx5_local_data;
1583         int ret = 0;
1584
1585         if (mlx5_init_shared_data())
1586                 return -rte_errno;
1587         sd = mlx5_shared_data;
1588         MLX5_ASSERT(sd);
1589         rte_spinlock_lock(&sd->lock);
1590         switch (rte_eal_process_type()) {
1591         case RTE_PROC_PRIMARY:
1592                 if (sd->init_done)
1593                         break;
1594                 LIST_INIT(&sd->mem_event_cb_list);
1595                 rte_rwlock_init(&sd->mem_event_rwlock);
1596                 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1597                                                 mlx5_mr_mem_event_cb, NULL);
1598                 ret = mlx5_mp_init_primary(MLX5_MP_NAME,
1599                                            mlx5_mp_primary_handle);
1600                 if (ret)
1601                         goto out;
1602                 sd->init_done = true;
1603                 break;
1604         case RTE_PROC_SECONDARY:
1605                 if (ld->init_done)
1606                         break;
1607                 ret = mlx5_mp_init_secondary(MLX5_MP_NAME,
1608                                              mlx5_mp_secondary_handle);
1609                 if (ret)
1610                         goto out;
1611                 ++sd->secondary_cnt;
1612                 ld->init_done = true;
1613                 break;
1614         default:
1615                 break;
1616         }
1617 out:
1618         rte_spinlock_unlock(&sd->lock);
1619         return ret;
1620 }
1621
1622 /**
1623  * Configures the minimal amount of data to inline into WQE
1624  * while sending packets.
1625  *
1626  * - the txq_inline_min has the maximal priority, if this
1627  *   key is specified in devargs
1628  * - if DevX is enabled the inline mode is queried from the
1629  *   device (HCA attributes and NIC vport context if needed).
1630  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1631  *   and none (0 bytes) for other NICs
1632  *
1633  * @param spawn
1634  *   Verbs device parameters (name, port, switch_info) to spawn.
1635  * @param config
1636  *   Device configuration parameters.
1637  */
1638 void
1639 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1640                     struct mlx5_dev_config *config)
1641 {
1642         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1643                 /* Application defines size of inlined data explicitly. */
1644                 switch (spawn->pci_dev->id.device_id) {
1645                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1646                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1647                         if (config->txq_inline_min <
1648                                        (int)MLX5_INLINE_HSIZE_L2) {
1649                                 DRV_LOG(DEBUG,
1650                                         "txq_inline_mix aligned to minimal"
1651                                         " ConnectX-4 required value %d",
1652                                         (int)MLX5_INLINE_HSIZE_L2);
1653                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1654                         }
1655                         break;
1656                 }
1657                 goto exit;
1658         }
1659         if (config->hca_attr.eth_net_offloads) {
1660                 /* We have DevX enabled, inline mode queried successfully. */
1661                 switch (config->hca_attr.wqe_inline_mode) {
1662                 case MLX5_CAP_INLINE_MODE_L2:
1663                         /* outer L2 header must be inlined. */
1664                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1665                         goto exit;
1666                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1667                         /* No inline data are required by NIC. */
1668                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1669                         config->hw_vlan_insert =
1670                                 config->hca_attr.wqe_vlan_insert;
1671                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1672                         goto exit;
1673                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1674                         /* inline mode is defined by NIC vport context. */
1675                         if (!config->hca_attr.eth_virt)
1676                                 break;
1677                         switch (config->hca_attr.vport_inline_mode) {
1678                         case MLX5_INLINE_MODE_NONE:
1679                                 config->txq_inline_min =
1680                                         MLX5_INLINE_HSIZE_NONE;
1681                                 goto exit;
1682                         case MLX5_INLINE_MODE_L2:
1683                                 config->txq_inline_min =
1684                                         MLX5_INLINE_HSIZE_L2;
1685                                 goto exit;
1686                         case MLX5_INLINE_MODE_IP:
1687                                 config->txq_inline_min =
1688                                         MLX5_INLINE_HSIZE_L3;
1689                                 goto exit;
1690                         case MLX5_INLINE_MODE_TCP_UDP:
1691                                 config->txq_inline_min =
1692                                         MLX5_INLINE_HSIZE_L4;
1693                                 goto exit;
1694                         case MLX5_INLINE_MODE_INNER_L2:
1695                                 config->txq_inline_min =
1696                                         MLX5_INLINE_HSIZE_INNER_L2;
1697                                 goto exit;
1698                         case MLX5_INLINE_MODE_INNER_IP:
1699                                 config->txq_inline_min =
1700                                         MLX5_INLINE_HSIZE_INNER_L3;
1701                                 goto exit;
1702                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
1703                                 config->txq_inline_min =
1704                                         MLX5_INLINE_HSIZE_INNER_L4;
1705                                 goto exit;
1706                         }
1707                 }
1708         }
1709         /*
1710          * We get here if we are unable to deduce
1711          * inline data size with DevX. Try PCI ID
1712          * to determine old NICs.
1713          */
1714         switch (spawn->pci_dev->id.device_id) {
1715         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1716         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1717         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1718         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1719                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1720                 config->hw_vlan_insert = 0;
1721                 break;
1722         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1723         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1724         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1725         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1726                 /*
1727                  * These NICs support VLAN insertion from WQE and
1728                  * report the wqe_vlan_insert flag. But there is the bug
1729                  * and PFC control may be broken, so disable feature.
1730                  */
1731                 config->hw_vlan_insert = 0;
1732                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1733                 break;
1734         default:
1735                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1736                 break;
1737         }
1738 exit:
1739         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1740 }
1741
1742 /**
1743  * Configures the metadata mask fields in the shared context.
1744  *
1745  * @param [in] dev
1746  *   Pointer to Ethernet device.
1747  */
1748 void
1749 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1750 {
1751         struct mlx5_priv *priv = dev->data->dev_private;
1752         struct mlx5_dev_ctx_shared *sh = priv->sh;
1753         uint32_t meta, mark, reg_c0;
1754
1755         reg_c0 = ~priv->vport_meta_mask;
1756         switch (priv->config.dv_xmeta_en) {
1757         case MLX5_XMETA_MODE_LEGACY:
1758                 meta = UINT32_MAX;
1759                 mark = MLX5_FLOW_MARK_MASK;
1760                 break;
1761         case MLX5_XMETA_MODE_META16:
1762                 meta = reg_c0 >> rte_bsf32(reg_c0);
1763                 mark = MLX5_FLOW_MARK_MASK;
1764                 break;
1765         case MLX5_XMETA_MODE_META32:
1766                 meta = UINT32_MAX;
1767                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1768                 break;
1769         default:
1770                 meta = 0;
1771                 mark = 0;
1772                 MLX5_ASSERT(false);
1773                 break;
1774         }
1775         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1776                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1777                                  sh->dv_mark_mask, mark);
1778         else
1779                 sh->dv_mark_mask = mark;
1780         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1781                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1782                                  sh->dv_meta_mask, meta);
1783         else
1784                 sh->dv_meta_mask = meta;
1785         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1786                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1787                                  sh->dv_meta_mask, reg_c0);
1788         else
1789                 sh->dv_regc0_mask = reg_c0;
1790         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1791         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1792         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1793         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1794 }
1795
1796 /**
1797  * Allocate page of door-bells and register it using DevX API.
1798  *
1799  * @param [in] dev
1800  *   Pointer to Ethernet device.
1801  *
1802  * @return
1803  *   Pointer to new page on success, NULL otherwise.
1804  */
1805 static struct mlx5_devx_dbr_page *
1806 mlx5_alloc_dbr_page(struct rte_eth_dev *dev)
1807 {
1808         struct mlx5_priv *priv = dev->data->dev_private;
1809         struct mlx5_devx_dbr_page *page;
1810
1811         /* Allocate space for door-bell page and management data. */
1812         page = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_devx_dbr_page),
1813                                  RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1814         if (!page) {
1815                 DRV_LOG(ERR, "port %u cannot allocate dbr page",
1816                         dev->data->port_id);
1817                 return NULL;
1818         }
1819         /* Register allocated memory. */
1820         page->umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, page->dbrs,
1821                                               MLX5_DBR_PAGE_SIZE, 0);
1822         if (!page->umem) {
1823                 DRV_LOG(ERR, "port %u cannot umem reg dbr page",
1824                         dev->data->port_id);
1825                 rte_free(page);
1826                 return NULL;
1827         }
1828         return page;
1829 }
1830
1831 /**
1832  * Find the next available door-bell, allocate new page if needed.
1833  *
1834  * @param [in] dev
1835  *   Pointer to Ethernet device.
1836  * @param [out] dbr_page
1837  *   Door-bell page containing the page data.
1838  *
1839  * @return
1840  *   Door-bell address offset on success, a negative error value otherwise.
1841  */
1842 int64_t
1843 mlx5_get_dbr(struct rte_eth_dev *dev, struct mlx5_devx_dbr_page **dbr_page)
1844 {
1845         struct mlx5_priv *priv = dev->data->dev_private;
1846         struct mlx5_devx_dbr_page *page = NULL;
1847         uint32_t i, j;
1848
1849         LIST_FOREACH(page, &priv->dbrpgs, next)
1850                 if (page->dbr_count < MLX5_DBR_PER_PAGE)
1851                         break;
1852         if (!page) { /* No page with free door-bell exists. */
1853                 page = mlx5_alloc_dbr_page(dev);
1854                 if (!page) /* Failed to allocate new page. */
1855                         return (-1);
1856                 LIST_INSERT_HEAD(&priv->dbrpgs, page, next);
1857         }
1858         /* Loop to find bitmap part with clear bit. */
1859         for (i = 0;
1860              i < MLX5_DBR_BITMAP_SIZE && page->dbr_bitmap[i] == UINT64_MAX;
1861              i++)
1862                 ; /* Empty. */
1863         /* Find the first clear bit. */
1864         MLX5_ASSERT(i < MLX5_DBR_BITMAP_SIZE);
1865         j = rte_bsf64(~page->dbr_bitmap[i]);
1866         page->dbr_bitmap[i] |= (UINT64_C(1) << j);
1867         page->dbr_count++;
1868         *dbr_page = page;
1869         return (((i * 64) + j) * sizeof(uint64_t));
1870 }
1871
1872 /**
1873  * Release a door-bell record.
1874  *
1875  * @param [in] dev
1876  *   Pointer to Ethernet device.
1877  * @param [in] umem_id
1878  *   UMEM ID of page containing the door-bell record to release.
1879  * @param [in] offset
1880  *   Offset of door-bell record in page.
1881  *
1882  * @return
1883  *   0 on success, a negative error value otherwise.
1884  */
1885 int32_t
1886 mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id, uint64_t offset)
1887 {
1888         struct mlx5_priv *priv = dev->data->dev_private;
1889         struct mlx5_devx_dbr_page *page = NULL;
1890         int ret = 0;
1891
1892         LIST_FOREACH(page, &priv->dbrpgs, next)
1893                 /* Find the page this address belongs to. */
1894                 if (mlx5_os_get_umem_id(page->umem) == umem_id)
1895                         break;
1896         if (!page)
1897                 return -EINVAL;
1898         page->dbr_count--;
1899         if (!page->dbr_count) {
1900                 /* Page not used, free it and remove from list. */
1901                 LIST_REMOVE(page, next);
1902                 if (page->umem)
1903                         ret = -mlx5_glue->devx_umem_dereg(page->umem);
1904                 rte_free(page);
1905         } else {
1906                 /* Mark in bitmap that this door-bell is not in use. */
1907                 offset /= MLX5_DBR_SIZE;
1908                 int i = offset / 64;
1909                 int j = offset % 64;
1910
1911                 page->dbr_bitmap[i] &= ~(UINT64_C(1) << j);
1912         }
1913         return ret;
1914 }
1915
1916 int
1917 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1918 {
1919         static const char *const dynf_names[] = {
1920                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1921                 RTE_MBUF_DYNFLAG_METADATA_NAME
1922         };
1923         unsigned int i;
1924
1925         if (n < RTE_DIM(dynf_names))
1926                 return -ENOMEM;
1927         for (i = 0; i < RTE_DIM(dynf_names); i++) {
1928                 if (names[i] == NULL)
1929                         return -EINVAL;
1930                 strcpy(names[i], dynf_names[i]);
1931         }
1932         return RTE_DIM(dynf_names);
1933 }
1934
1935 /**
1936  * Comparison callback to sort device data.
1937  *
1938  * This is meant to be used with qsort().
1939  *
1940  * @param a[in]
1941  *   Pointer to pointer to first data object.
1942  * @param b[in]
1943  *   Pointer to pointer to second data object.
1944  *
1945  * @return
1946  *   0 if both objects are equal, less than 0 if the first argument is less
1947  *   than the second, greater than 0 otherwise.
1948  */
1949 int
1950 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1951                               struct mlx5_dev_config *config)
1952 {
1953         struct mlx5_dev_ctx_shared *sh = priv->sh;
1954         struct mlx5_dev_config *sh_conf = NULL;
1955         uint16_t port_id;
1956
1957         MLX5_ASSERT(sh);
1958         /* Nothing to compare for the single/first device. */
1959         if (sh->refcnt == 1)
1960                 return 0;
1961         /* Find the device with shared context. */
1962         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1963                 struct mlx5_priv *opriv =
1964                         rte_eth_devices[port_id].data->dev_private;
1965
1966                 if (opriv && opriv != priv && opriv->sh == sh) {
1967                         sh_conf = &opriv->config;
1968                         break;
1969                 }
1970         }
1971         if (!sh_conf)
1972                 return 0;
1973         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1974                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1975                              " for shared %s context", sh->ibdev_name);
1976                 rte_errno = EINVAL;
1977                 return rte_errno;
1978         }
1979         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1980                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1981                              " for shared %s context", sh->ibdev_name);
1982                 rte_errno = EINVAL;
1983                 return rte_errno;
1984         }
1985         return 0;
1986 }
1987
1988 /**
1989  * Look for the ethernet device belonging to mlx5 driver.
1990  *
1991  * @param[in] port_id
1992  *   port_id to start looking for device.
1993  * @param[in] pci_dev
1994  *   Pointer to the hint PCI device. When device is being probed
1995  *   the its siblings (master and preceding representors might
1996  *   not have assigned driver yet (because the mlx5_os_pci_probe()
1997  *   is not completed yet, for this case match on hint PCI
1998  *   device may be used to detect sibling device.
1999  *
2000  * @return
2001  *   port_id of found device, RTE_MAX_ETHPORT if not found.
2002  */
2003 uint16_t
2004 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
2005 {
2006         while (port_id < RTE_MAX_ETHPORTS) {
2007                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2008
2009                 if (dev->state != RTE_ETH_DEV_UNUSED &&
2010                     dev->device &&
2011                     (dev->device == &pci_dev->device ||
2012                      (dev->device->driver &&
2013                      dev->device->driver->name &&
2014                      !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
2015                         break;
2016                 port_id++;
2017         }
2018         if (port_id >= RTE_MAX_ETHPORTS)
2019                 return RTE_MAX_ETHPORTS;
2020         return port_id;
2021 }
2022
2023 /**
2024  * DPDK callback to remove a PCI device.
2025  *
2026  * This function removes all Ethernet devices belong to a given PCI device.
2027  *
2028  * @param[in] pci_dev
2029  *   Pointer to the PCI device.
2030  *
2031  * @return
2032  *   0 on success, the function cannot fail.
2033  */
2034 static int
2035 mlx5_pci_remove(struct rte_pci_device *pci_dev)
2036 {
2037         uint16_t port_id;
2038
2039         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
2040                 /*
2041                  * mlx5_dev_close() is not registered to secondary process,
2042                  * call the close function explicitly for secondary process.
2043                  */
2044                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2045                         mlx5_dev_close(&rte_eth_devices[port_id]);
2046                 else
2047                         rte_eth_dev_close(port_id);
2048         }
2049         return 0;
2050 }
2051
2052 static const struct rte_pci_id mlx5_pci_id_map[] = {
2053         {
2054                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2055                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2056         },
2057         {
2058                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2059                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2060         },
2061         {
2062                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2063                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2064         },
2065         {
2066                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2067                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2068         },
2069         {
2070                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2071                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2072         },
2073         {
2074                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2075                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2076         },
2077         {
2078                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2079                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2080         },
2081         {
2082                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2083                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2084         },
2085         {
2086                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2087                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2088         },
2089         {
2090                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2091                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2092         },
2093         {
2094                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2095                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2096         },
2097         {
2098                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2099                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2100         },
2101         {
2102                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2103                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2104         },
2105         {
2106                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2107                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
2108         },
2109         {
2110                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2111                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2112         },
2113         {
2114                 .vendor_id = 0
2115         }
2116 };
2117
2118 struct rte_pci_driver mlx5_driver = {
2119         .driver = {
2120                 .name = MLX5_DRIVER_NAME
2121         },
2122         .id_table = mlx5_pci_id_map,
2123         .probe = mlx5_os_pci_probe,
2124         .remove = mlx5_pci_remove,
2125         .dma_map = mlx5_dma_map,
2126         .dma_unmap = mlx5_dma_unmap,
2127         .drv_flags = PCI_DRV_FLAGS,
2128 };
2129
2130 /**
2131  * Driver initialization routine.
2132  */
2133 RTE_INIT(rte_mlx5_pmd_init)
2134 {
2135         /* Initialize driver log type. */
2136         mlx5_logtype = rte_log_register("pmd.net.mlx5");
2137         if (mlx5_logtype >= 0)
2138                 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
2139
2140         /* Build the static tables for Verbs conversion. */
2141         mlx5_set_ptype_table();
2142         mlx5_set_cksum_table();
2143         mlx5_set_swp_types_table();
2144         if (mlx5_glue)
2145                 rte_pci_register(&mlx5_driver);
2146 }
2147
2148 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2149 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2150 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");