drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12 #include <net/if.h>
  13 #include <sys/mman.h>
  14 #include <linux/rtnetlink.h>
  15
  16 /* Verbs header. */
  17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  18 #ifdef PEDANTIC
  19 #pragma GCC diagnostic ignored "-Wpedantic"
  20 #endif
  21 #include <infiniband/verbs.h>
  22 #ifdef PEDANTIC
  23 #pragma GCC diagnostic error "-Wpedantic"
  24 #endif
  25
  26 #include <rte_malloc.h>
  27 #include <rte_ethdev_driver.h>
  28 #include <rte_ethdev_pci.h>
  29 #include <rte_pci.h>
  30 #include <rte_bus_pci.h>
  31 #include <rte_common.h>
  32 #include <rte_kvargs.h>
  33 #include <rte_rwlock.h>
  34 #include <rte_spinlock.h>
  35 #include <rte_string_fns.h>
  36 #include <rte_alarm.h>
  37
  38 #include <mlx5_glue.h>
  39 #include <mlx5_devx_cmds.h>
  40 #include <mlx5_common.h>
  41 #include <mlx5_common_mp.h>
  42
  43 #include "mlx5_defs.h"
  44 #include "mlx5.h"
  45 #include "mlx5_utils.h"
  46 #include "mlx5_rxtx.h"
  47 #include "mlx5_autoconf.h"
  48 #include "mlx5_mr.h"
  49 #include "mlx5_flow.h"
  50 #include "rte_pmd_mlx5.h"
  51
  52 /* Device parameter to enable RX completion queue compression. */
  53 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  54
  55 /* Device parameter to enable RX completion entry padding to 128B. */
  56 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
  57
  58 /* Device parameter to enable padding Rx packet to cacheline size. */
  59 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  60
  61 /* Device parameter to enable Multi-Packet Rx queue. */
  62 #define MLX5_RX_MPRQ_EN "mprq_en"
  63
  64 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  65 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  66
  67 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  68 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  69
  70 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  71 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  72
  73 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  74 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  75
  76 /* Device parameter to configure inline send. Deprecated, ignored.*/
  77 #define MLX5_TXQ_INLINE "txq_inline"
  78
  79 /* Device parameter to limit packet size to inline with ordinary SEND. */
  80 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  81
  82 /* Device parameter to configure minimal data size to inline. */
  83 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  84
  85 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  86 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  87
  88 /*
  89  * Device parameter to configure the number of TX queues threshold for
  90  * enabling inline send.
  91  */
  92 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  93
  94 /*
  95  * Device parameter to configure the number of TX queues threshold for
  96  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  97  */
  98 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  99
 100 /* Device parameter to enable multi-packet send WQEs. */
 101 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
 102
 103 /*
 104  * Device parameter to force doorbell register mapping
 105  * to non-cahed region eliminating the extra write memory barrier.
 106  */
 107 #define MLX5_TX_DB_NC "tx_db_nc"
 108
 109 /*
 110  * Device parameter to include 2 dsegs in the title WQEBB.
 111  * Deprecated, ignored.
 112  */
 113 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 114
 115 /*
 116  * Device parameter to limit the size of inlining packet.
 117  * Deprecated, ignored.
 118  */
 119 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 120
 121 /*
 122  * Device parameter to enable hardware Tx vector.
 123  * Deprecated, ignored (no vectorized Tx routines anymore).
 124  */
 125 #define MLX5_TX_VEC_EN "tx_vec_en"
 126
 127 /* Device parameter to enable hardware Rx vector. */
 128 #define MLX5_RX_VEC_EN "rx_vec_en"
 129
 130 /* Allow L3 VXLAN flow creation. */
 131 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 132
 133 /* Activate DV E-Switch flow steering. */
 134 #define MLX5_DV_ESW_EN "dv_esw_en"
 135
 136 /* Activate DV flow steering. */
 137 #define MLX5_DV_FLOW_EN "dv_flow_en"
 138
 139 /* Enable extensive flow metadata support. */
 140 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 141
 142 /* Activate Netlink support in VF mode. */
 143 #define MLX5_VF_NL_EN "vf_nl_en"
 144
 145 /* Enable extending memsegs when creating a MR. */
 146 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 147
 148 /* Select port representors to instantiate. */
 149 #define MLX5_REPRESENTOR "representor"
 150
 151 /* Device parameter to configure the maximum number of dump files per queue. */
 152 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 153
 154 /* Configure timeout of LRO session (in microseconds). */
 155 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 156
 157 /*
 158  * Device parameter to configure the total data buffer size for a single
 159  * hairpin queue (logarithm value).
 160  */
 161 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 162
 163 #ifndef HAVE_IBV_MLX5_MOD_MPW
 164 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
 165 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
 166 #endif
 167
 168 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
 169 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
 170 #endif
 171
 172 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
 173
 174 /* Shared memory between primary and secondary processes. */
 175 struct mlx5_shared_data *mlx5_shared_data;
 176
 177 /* Spinlock for mlx5_shared_data allocation. */
 178 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
 179
 180 /* Process local data for secondary processes. */
 181 static struct mlx5_local_data mlx5_local_data;
 182
 183 /** Driver-specific log messages type. */
 184 int mlx5_logtype;
 185
 186 /** Data associated with devices to spawn. */
 187 struct mlx5_dev_spawn_data {
 188         uint32_t ifindex; /**< Network interface index. */
 189         uint32_t max_port; /**< IB device maximal port index. */
 190         uint32_t ibv_port; /**< IB device physical port index. */
 191         int pf_bond; /**< bonding device PF index. < 0 - no bonding */
 192         struct mlx5_switch_info info; /**< Switch information. */
 193         struct ibv_device *ibv_dev; /**< Associated IB device. */
 194         struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
 195         struct rte_pci_device *pci_dev; /**< Backend PCI device. */
 196 };
 197
 198 static LIST_HEAD(, mlx5_ibv_shared) mlx5_ibv_list = LIST_HEAD_INITIALIZER();
 199 static pthread_mutex_t mlx5_ibv_list_mutex = PTHREAD_MUTEX_INITIALIZER;
 200
 201 static struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 202         {
 203                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 204                 .trunk_size = 64,
 205                 .grow_trunk = 3,
 206                 .grow_shift = 2,
 207                 .need_lock = 0,
 208                 .release_mem_en = 1,
 209                 .malloc = rte_malloc_socket,
 210                 .free = rte_free,
 211                 .type = "mlx5_encap_decap_ipool",
 212         },
 213         {
 214                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 215                 .trunk_size = 64,
 216                 .grow_trunk = 3,
 217                 .grow_shift = 2,
 218                 .need_lock = 0,
 219                 .release_mem_en = 1,
 220                 .malloc = rte_malloc_socket,
 221                 .free = rte_free,
 222                 .type = "mlx5_push_vlan_ipool",
 223         },
 224         {
 225                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 226                 .trunk_size = 64,
 227                 .grow_trunk = 3,
 228                 .grow_shift = 2,
 229                 .need_lock = 0,
 230                 .release_mem_en = 1,
 231                 .malloc = rte_malloc_socket,
 232                 .free = rte_free,
 233                 .type = "mlx5_tag_ipool",
 234         },
 235 };
 236
 237
 238 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 239 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 240
 241 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 242 #define MLX5_TAGS_HLIST_ARRAY_SIZE 8192
 243
 244 /**
 245  * Allocate ID pool structure.
 246  *
 247  * @param[in] max_id
 248  *   The maximum id can be allocated from the pool.
 249  *
 250  * @return
 251  *   Pointer to pool object, NULL value otherwise.
 252  */
 253 struct mlx5_flow_id_pool *
 254 mlx5_flow_id_pool_alloc(uint32_t max_id)
 255 {
 256         struct mlx5_flow_id_pool *pool;
 257         void *mem;
 258
 259         pool = rte_zmalloc("id pool allocation", sizeof(*pool),
 260                            RTE_CACHE_LINE_SIZE);
 261         if (!pool) {
 262                 DRV_LOG(ERR, "can't allocate id pool");
 263                 rte_errno  = ENOMEM;
 264                 return NULL;
 265         }
 266         mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
 267                           RTE_CACHE_LINE_SIZE);
 268         if (!mem) {
 269                 DRV_LOG(ERR, "can't allocate mem for id pool");
 270                 rte_errno  = ENOMEM;
 271                 goto error;
 272         }
 273         pool->free_arr = mem;
 274         pool->curr = pool->free_arr;
 275         pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
 276         pool->base_index = 0;
 277         pool->max_id = max_id;
 278         return pool;
 279 error:
 280         rte_free(pool);
 281         return NULL;
 282 }
 283
 284 /**
 285  * Release ID pool structure.
 286  *
 287  * @param[in] pool
 288  *   Pointer to flow id pool object to free.
 289  */
 290 void
 291 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
 292 {
 293         rte_free(pool->free_arr);
 294         rte_free(pool);
 295 }
 296
 297 /**
 298  * Generate ID.
 299  *
 300  * @param[in] pool
 301  *   Pointer to flow id pool.
 302  * @param[out] id
 303  *   The generated ID.
 304  *
 305  * @return
 306  *   0 on success, error value otherwise.
 307  */
 308 uint32_t
 309 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
 310 {
 311         if (pool->curr == pool->free_arr) {
 312                 if (pool->base_index == pool->max_id) {
 313                         rte_errno  = ENOMEM;
 314                         DRV_LOG(ERR, "no free id");
 315                         return -rte_errno;
 316                 }
 317                 *id = ++pool->base_index;
 318                 return 0;
 319         }
 320         *id = *(--pool->curr);
 321         return 0;
 322 }
 323
 324 /**
 325  * Release ID.
 326  *
 327  * @param[in] pool
 328  *   Pointer to flow id pool.
 329  * @param[out] id
 330  *   The generated ID.
 331  *
 332  * @return
 333  *   0 on success, error value otherwise.
 334  */
 335 uint32_t
 336 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
 337 {
 338         uint32_t size;
 339         uint32_t size2;
 340         void *mem;
 341
 342         if (pool->curr == pool->last) {
 343                 size = pool->curr - pool->free_arr;
 344                 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
 345                 MLX5_ASSERT(size2 > size);
 346                 mem = rte_malloc("", size2 * sizeof(uint32_t), 0);
 347                 if (!mem) {
 348                         DRV_LOG(ERR, "can't allocate mem for id pool");
 349                         rte_errno  = ENOMEM;
 350                         return -rte_errno;
 351                 }
 352                 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
 353                 rte_free(pool->free_arr);
 354                 pool->free_arr = mem;
 355                 pool->curr = pool->free_arr + size;
 356                 pool->last = pool->free_arr + size2;
 357         }
 358         *pool->curr = id;
 359         pool->curr++;
 360         return 0;
 361 }
 362
 363 /**
 364  * Initialize the counters management structure.
 365  *
 366  * @param[in] sh
 367  *   Pointer to mlx5_ibv_shared object to free
 368  */
 369 static void
 370 mlx5_flow_counters_mng_init(struct mlx5_ibv_shared *sh)
 371 {
 372         uint8_t i;
 373
 374         TAILQ_INIT(&sh->cmng.flow_counters);
 375         for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i)
 376                 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
 377 }
 378
 379 /**
 380  * Destroy all the resources allocated for a counter memory management.
 381  *
 382  * @param[in] mng
 383  *   Pointer to the memory management structure.
 384  */
 385 static void
 386 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 387 {
 388         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 389
 390         LIST_REMOVE(mng, next);
 391         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 392         claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
 393         rte_free(mem);
 394 }
 395
 396 /**
 397  * Close and release all the resources of the counters management.
 398  *
 399  * @param[in] sh
 400  *   Pointer to mlx5_ibv_shared object to free.
 401  */
 402 static void
 403 mlx5_flow_counters_mng_close(struct mlx5_ibv_shared *sh)
 404 {
 405         struct mlx5_counter_stats_mem_mng *mng;
 406         uint8_t i;
 407         int j;
 408         int retries = 1024;
 409
 410         rte_errno = 0;
 411         while (--retries) {
 412                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 413                 if (rte_errno != EINPROGRESS)
 414                         break;
 415                 rte_pause();
 416         }
 417         for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i) {
 418                 struct mlx5_flow_counter_pool *pool;
 419                 uint32_t batch = !!(i % 2);
 420
 421                 if (!sh->cmng.ccont[i].pools)
 422                         continue;
 423                 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 424                 while (pool) {
 425                         if (batch) {
 426                                 if (pool->min_dcs)
 427                                         claim_zero
 428                                         (mlx5_devx_cmd_destroy(pool->min_dcs));
 429                         }
 430                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 431                                 if (pool->counters_raw[j].action)
 432                                         claim_zero
 433                                         (mlx5_glue->destroy_flow_action
 434                                                (pool->counters_raw[j].action));
 435                                 if (!batch && MLX5_GET_POOL_CNT_EXT
 436                                     (pool, j)->dcs)
 437                                         claim_zero(mlx5_devx_cmd_destroy
 438                                                   (MLX5_GET_POOL_CNT_EXT
 439                                                   (pool, j)->dcs));
 440                         }
 441                         TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool,
 442                                      next);
 443                         rte_free(pool);
 444                         pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 445                 }
 446                 rte_free(sh->cmng.ccont[i].pools);
 447         }
 448         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 449         while (mng) {
 450                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 451                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 452         }
 453         memset(&sh->cmng, 0, sizeof(sh->cmng));
 454 }
 455
 456 /**
 457  * Initialize the flow resources' indexed mempool.
 458  *
 459  * @param[in] sh
 460  *   Pointer to mlx5_ibv_shared object.
 461  */
 462 static void
 463 mlx5_flow_ipool_create(struct mlx5_ibv_shared *sh)
 464 {
 465         uint8_t i;
 466
 467         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 468                 sh->ipool[i] = mlx5_ipool_create(&mlx5_ipool_cfg[i]);
 469 }
 470
 471 /**
 472  * Release the flow resources' indexed mempool.
 473  *
 474  * @param[in] sh
 475  *   Pointer to mlx5_ibv_shared object.
 476  */
 477 static void
 478 mlx5_flow_ipool_destroy(struct mlx5_ibv_shared *sh)
 479 {
 480         uint8_t i;
 481
 482         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 483                 mlx5_ipool_destroy(sh->ipool[i]);
 484 }
 485
 486 /**
 487  * Extract pdn of PD object using DV API.
 488  *
 489  * @param[in] pd
 490  *   Pointer to the verbs PD object.
 491  * @param[out] pdn
 492  *   Pointer to the PD object number variable.
 493  *
 494  * @return
 495  *   0 on success, error value otherwise.
 496  */
 497 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 498 static int
 499 mlx5_get_pdn(struct ibv_pd *pd __rte_unused, uint32_t *pdn __rte_unused)
 500 {
 501         struct mlx5dv_obj obj;
 502         struct mlx5dv_pd pd_info;
 503         int ret = 0;
 504
 505         obj.pd.in = pd;
 506         obj.pd.out = &pd_info;
 507         ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);
 508         if (ret) {
 509                 DRV_LOG(DEBUG, "Fail to get PD object info");
 510                 return ret;
 511         }
 512         *pdn = pd_info.pdn;
 513         return 0;
 514 }
 515 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
 516
 517 static int
 518 mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config)
 519 {
 520         char *env;
 521         int value;
 522
 523         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 524         /* Get environment variable to store. */
 525         env = getenv(MLX5_SHUT_UP_BF);
 526         value = env ? !!strcmp(env, "0") : MLX5_ARG_UNSET;
 527         if (config->dbnc == MLX5_ARG_UNSET)
 528                 setenv(MLX5_SHUT_UP_BF, MLX5_SHUT_UP_BF_DEFAULT, 1);
 529         else
 530                 setenv(MLX5_SHUT_UP_BF,
 531                        config->dbnc == MLX5_TXDB_NCACHED ? "1" : "0", 1);
 532         return value;
 533 }
 534
 535 static void
 536 mlx5_restore_doorbell_mapping_env(int value)
 537 {
 538         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 539         /* Restore the original environment variable state. */
 540         if (value == MLX5_ARG_UNSET)
 541                 unsetenv(MLX5_SHUT_UP_BF);
 542         else
 543                 setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1);
 544 }
 545
 546 /**
 547  * Allocate shared IB device context. If there is multiport device the
 548  * master and representors will share this context, if there is single
 549  * port dedicated IB device, the context will be used by only given
 550  * port due to unification.
 551  *
 552  * Routine first searches the context for the specified IB device name,
 553  * if found the shared context assumed and reference counter is incremented.
 554  * If no context found the new one is created and initialized with specified
 555  * IB device context and parameters.
 556  *
 557  * @param[in] spawn
 558  *   Pointer to the IB device attributes (name, port, etc).
 559  * @param[in] config
 560  *   Pointer to device configuration structure.
 561  *
 562  * @return
 563  *   Pointer to mlx5_ibv_shared object on success,
 564  *   otherwise NULL and rte_errno is set.
 565  */
 566 static struct mlx5_ibv_shared *
 567 mlx5_alloc_shared_ibctx(const struct mlx5_dev_spawn_data *spawn,
 568                         const struct mlx5_dev_config *config)
 569 {
 570         struct mlx5_ibv_shared *sh;
 571         int dbmap_env;
 572         int err = 0;
 573         uint32_t i;
 574 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 575         struct mlx5_devx_tis_attr tis_attr = { 0 };
 576 #endif
 577
 578         MLX5_ASSERT(spawn);
 579         /* Secondary process should not create the shared context. */
 580         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 581         pthread_mutex_lock(&mlx5_ibv_list_mutex);
 582         /* Search for IB context by device name. */
 583         LIST_FOREACH(sh, &mlx5_ibv_list, next) {
 584                 if (!strcmp(sh->ibdev_name, spawn->ibv_dev->name)) {
 585                         sh->refcnt++;
 586                         goto exit;
 587                 }
 588         }
 589         /* No device found, we have to create new shared context. */
 590         MLX5_ASSERT(spawn->max_port);
 591         sh = rte_zmalloc("ethdev shared ib context",
 592                          sizeof(struct mlx5_ibv_shared) +
 593                          spawn->max_port *
 594                          sizeof(struct mlx5_ibv_shared_port),
 595                          RTE_CACHE_LINE_SIZE);
 596         if (!sh) {
 597                 DRV_LOG(ERR, "shared context allocation failure");
 598                 rte_errno  = ENOMEM;
 599                 goto exit;
 600         }
 601         /*
 602          * Configure environment variable "MLX5_BF_SHUT_UP"
 603          * before the device creation. The rdma_core library
 604          * checks the variable at device creation and
 605          * stores the result internally.
 606          */
 607         dbmap_env = mlx5_config_doorbell_mapping_env(config);
 608         /* Try to open IB device with DV first, then usual Verbs. */
 609         errno = 0;
 610         sh->ctx = mlx5_glue->dv_open_device(spawn->ibv_dev);
 611         if (sh->ctx) {
 612                 sh->devx = 1;
 613                 DRV_LOG(DEBUG, "DevX is supported");
 614                 /* The device is created, no need for environment. */
 615                 mlx5_restore_doorbell_mapping_env(dbmap_env);
 616         } else {
 617                 /* The environment variable is still configured. */
 618                 sh->ctx = mlx5_glue->open_device(spawn->ibv_dev);
 619                 err = errno ? errno : ENODEV;
 620                 /*
 621                  * The environment variable is not needed anymore,
 622                  * all device creation attempts are completed.
 623                  */
 624                 mlx5_restore_doorbell_mapping_env(dbmap_env);
 625                 if (!sh->ctx)
 626                         goto error;
 627                 DRV_LOG(DEBUG, "DevX is NOT supported");
 628         }
 629         err = mlx5_glue->query_device_ex(sh->ctx, NULL, &sh->device_attr);
 630         if (err) {
 631                 DRV_LOG(DEBUG, "ibv_query_device_ex() failed");
 632                 goto error;
 633         }
 634         sh->refcnt = 1;
 635         sh->max_port = spawn->max_port;
 636         strncpy(sh->ibdev_name, sh->ctx->device->name,
 637                 sizeof(sh->ibdev_name));
 638         strncpy(sh->ibdev_path, sh->ctx->device->ibdev_path,
 639                 sizeof(sh->ibdev_path));
 640         pthread_mutex_init(&sh->intr_mutex, NULL);
 641         /*
 642          * Setting port_id to max unallowed value means
 643          * there is no interrupt subhandler installed for
 644          * the given port index i.
 645          */
 646         for (i = 0; i < sh->max_port; i++) {
 647                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 648                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
 649         }
 650         sh->pd = mlx5_glue->alloc_pd(sh->ctx);
 651         if (sh->pd == NULL) {
 652                 DRV_LOG(ERR, "PD allocation failure");
 653                 err = ENOMEM;
 654                 goto error;
 655         }
 656 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 657         if (sh->devx) {
 658                 err = mlx5_get_pdn(sh->pd, &sh->pdn);
 659                 if (err) {
 660                         DRV_LOG(ERR, "Fail to extract pdn from PD");
 661                         goto error;
 662                 }
 663                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
 664                 if (!sh->td) {
 665                         DRV_LOG(ERR, "TD allocation failure");
 666                         err = ENOMEM;
 667                         goto error;
 668                 }
 669                 tis_attr.transport_domain = sh->td->id;
 670                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
 671                 if (!sh->tis) {
 672                         DRV_LOG(ERR, "TIS allocation failure");
 673                         err = ENOMEM;
 674                         goto error;
 675                 }
 676         }
 677         sh->flow_id_pool = mlx5_flow_id_pool_alloc(UINT32_MAX);
 678         if (!sh->flow_id_pool) {
 679                 DRV_LOG(ERR, "can't create flow id pool");
 680                 err = ENOMEM;
 681                 goto error;
 682         }
 683 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
 684         /*
 685          * Once the device is added to the list of memory event
 686          * callback, its global MR cache table cannot be expanded
 687          * on the fly because of deadlock. If it overflows, lookup
 688          * should be done by searching MR list linearly, which is slow.
 689          *
 690          * At this point the device is not added to the memory
 691          * event list yet, context is just being created.
 692          */
 693         err = mlx5_mr_btree_init(&sh->share_cache.cache,
 694                                  MLX5_MR_BTREE_CACHE_N * 2,
 695                                  spawn->pci_dev->device.numa_node);
 696         if (err) {
 697                 err = rte_errno;
 698                 goto error;
 699         }
 700         mlx5_flow_counters_mng_init(sh);
 701         mlx5_flow_ipool_create(sh);
 702         /* Add device to memory callback list. */
 703         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 704         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
 705                          sh, mem_event_cb);
 706         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 707         /* Add context to the global device list. */
 708         LIST_INSERT_HEAD(&mlx5_ibv_list, sh, next);
 709 exit:
 710         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 711         return sh;
 712 error:
 713         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 714         MLX5_ASSERT(sh);
 715         if (sh->tis)
 716                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 717         if (sh->td)
 718                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 719         if (sh->pd)
 720                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 721         if (sh->ctx)
 722                 claim_zero(mlx5_glue->close_device(sh->ctx));
 723         if (sh->flow_id_pool)
 724                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 725         rte_free(sh);
 726         MLX5_ASSERT(err > 0);
 727         rte_errno = err;
 728         return NULL;
 729 }
 730
 731 /**
 732  * Free shared IB device context. Decrement counter and if zero free
 733  * all allocated resources and close handles.
 734  *
 735  * @param[in] sh
 736  *   Pointer to mlx5_ibv_shared object to free
 737  */
 738 static void
 739 mlx5_free_shared_ibctx(struct mlx5_ibv_shared *sh)
 740 {
 741         pthread_mutex_lock(&mlx5_ibv_list_mutex);
 742 #ifdef RTE_LIBRTE_MLX5_DEBUG
 743         /* Check the object presence in the list. */
 744         struct mlx5_ibv_shared *lctx;
 745
 746         LIST_FOREACH(lctx, &mlx5_ibv_list, next)
 747                 if (lctx == sh)
 748                         break;
 749         MLX5_ASSERT(lctx);
 750         if (lctx != sh) {
 751                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
 752                 goto exit;
 753         }
 754 #endif
 755         MLX5_ASSERT(sh);
 756         MLX5_ASSERT(sh->refcnt);
 757         /* Secondary process should not free the shared context. */
 758         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 759         if (--sh->refcnt)
 760                 goto exit;
 761         /* Remove from memory callback device list. */
 762         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 763         LIST_REMOVE(sh, mem_event_cb);
 764         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 765         /* Release created Memory Regions. */
 766         mlx5_mr_release_cache(&sh->share_cache);
 767         /* Remove context from the global device list. */
 768         LIST_REMOVE(sh, next);
 769         /*
 770          *  Ensure there is no async event handler installed.
 771          *  Only primary process handles async device events.
 772          **/
 773         mlx5_flow_counters_mng_close(sh);
 774         mlx5_flow_ipool_destroy(sh);
 775         MLX5_ASSERT(!sh->intr_cnt);
 776         if (sh->intr_cnt)
 777                 mlx5_intr_callback_unregister
 778                         (&sh->intr_handle, mlx5_dev_interrupt_handler, sh);
 779 #ifdef HAVE_MLX5_DEVX_ASYNC_SUPPORT
 780         if (sh->devx_intr_cnt) {
 781                 if (sh->intr_handle_devx.fd)
 782                         rte_intr_callback_unregister(&sh->intr_handle_devx,
 783                                           mlx5_dev_interrupt_handler_devx, sh);
 784                 if (sh->devx_comp)
 785                         mlx5dv_devx_destroy_cmd_comp(sh->devx_comp);
 786         }
 787 #endif
 788         pthread_mutex_destroy(&sh->intr_mutex);
 789         if (sh->pd)
 790                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 791         if (sh->tis)
 792                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 793         if (sh->td)
 794                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 795         if (sh->ctx)
 796                 claim_zero(mlx5_glue->close_device(sh->ctx));
 797         if (sh->flow_id_pool)
 798                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 799         rte_free(sh);
 800 exit:
 801         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 802 }
 803
 804 /**
 805  * Destroy table hash list and all the root entries per domain.
 806  *
 807  * @param[in] priv
 808  *   Pointer to the private device data structure.
 809  */
 810 static void
 811 mlx5_free_table_hash_list(struct mlx5_priv *priv)
 812 {
 813         struct mlx5_ibv_shared *sh = priv->sh;
 814         struct mlx5_flow_tbl_data_entry *tbl_data;
 815         union mlx5_flow_tbl_key table_key = {
 816                 {
 817                         .table_id = 0,
 818                         .reserved = 0,
 819                         .domain = 0,
 820                         .direction = 0,
 821                 }
 822         };
 823         struct mlx5_hlist_entry *pos;
 824
 825         if (!sh->flow_tbls)
 826                 return;
 827         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 828         if (pos) {
 829                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 830                                         entry);
 831                 MLX5_ASSERT(tbl_data);
 832                 mlx5_hlist_remove(sh->flow_tbls, pos);
 833                 rte_free(tbl_data);
 834         }
 835         table_key.direction = 1;
 836         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 837         if (pos) {
 838                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 839                                         entry);
 840                 MLX5_ASSERT(tbl_data);
 841                 mlx5_hlist_remove(sh->flow_tbls, pos);
 842                 rte_free(tbl_data);
 843         }
 844         table_key.direction = 0;
 845         table_key.domain = 1;
 846         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 847         if (pos) {
 848                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 849                                         entry);
 850                 MLX5_ASSERT(tbl_data);
 851                 mlx5_hlist_remove(sh->flow_tbls, pos);
 852                 rte_free(tbl_data);
 853         }
 854         mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
 855 }
 856
 857 /**
 858  * Initialize flow table hash list and create the root tables entry
 859  * for each domain.
 860  *
 861  * @param[in] priv
 862  *   Pointer to the private device data structure.
 863  *
 864  * @return
 865  *   Zero on success, positive error code otherwise.
 866  */
 867 static int
 868 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
 869 {
 870         struct mlx5_ibv_shared *sh = priv->sh;
 871         char s[MLX5_HLIST_NAMESIZE];
 872         int err = 0;
 873
 874         MLX5_ASSERT(sh);
 875         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
 876         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
 877         if (!sh->flow_tbls) {
 878                 DRV_LOG(ERR, "flow tables with hash creation failed.\n");
 879                 err = ENOMEM;
 880                 return err;
 881         }
 882 #ifndef HAVE_MLX5DV_DR
 883         /*
 884          * In case we have not DR support, the zero tables should be created
 885          * because DV expect to see them even if they cannot be created by
 886          * RDMA-CORE.
 887          */
 888         union mlx5_flow_tbl_key table_key = {
 889                 {
 890                         .table_id = 0,
 891                         .reserved = 0,
 892                         .domain = 0,
 893                         .direction = 0,
 894                 }
 895         };
 896         struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL,
 897                                                           sizeof(*tbl_data), 0);
 898
 899         if (!tbl_data) {
 900                 err = ENOMEM;
 901                 goto error;
 902         }
 903         tbl_data->entry.key = table_key.v64;
 904         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 905         if (err)
 906                 goto error;
 907         rte_atomic32_init(&tbl_data->tbl.refcnt);
 908         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 909         table_key.direction = 1;
 910         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 911         if (!tbl_data) {
 912                 err = ENOMEM;
 913                 goto error;
 914         }
 915         tbl_data->entry.key = table_key.v64;
 916         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 917         if (err)
 918                 goto error;
 919         rte_atomic32_init(&tbl_data->tbl.refcnt);
 920         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 921         table_key.direction = 0;
 922         table_key.domain = 1;
 923         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 924         if (!tbl_data) {
 925                 err = ENOMEM;
 926                 goto error;
 927         }
 928         tbl_data->entry.key = table_key.v64;
 929         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 930         if (err)
 931                 goto error;
 932         rte_atomic32_init(&tbl_data->tbl.refcnt);
 933         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 934         return err;
 935 error:
 936         mlx5_free_table_hash_list(priv);
 937 #endif /* HAVE_MLX5DV_DR */
 938         return err;
 939 }
 940
 941 /**
 942  * Initialize DR related data within private structure.
 943  * Routine checks the reference counter and does actual
 944  * resources creation/initialization only if counter is zero.
 945  *
 946  * @param[in] priv
 947  *   Pointer to the private device data structure.
 948  *
 949  * @return
 950  *   Zero on success, positive error code otherwise.
 951  */
 952 static int
 953 mlx5_alloc_shared_dr(struct mlx5_priv *priv)
 954 {
 955         struct mlx5_ibv_shared *sh = priv->sh;
 956         char s[MLX5_HLIST_NAMESIZE];
 957         int err = 0;
 958
 959         if (!sh->flow_tbls)
 960                 err = mlx5_alloc_table_hash_list(priv);
 961         else
 962                 DRV_LOG(DEBUG, "sh->flow_tbls[%p] already created, reuse\n",
 963                         (void *)sh->flow_tbls);
 964         if (err)
 965                 return err;
 966         /* Create tags hash list table. */
 967         snprintf(s, sizeof(s), "%s_tags", sh->ibdev_name);
 968         sh->tag_table = mlx5_hlist_create(s, MLX5_TAGS_HLIST_ARRAY_SIZE);
 969         if (!sh->tag_table) {
 970                 DRV_LOG(ERR, "tags with hash creation failed.\n");
 971                 err = ENOMEM;
 972                 goto error;
 973         }
 974 #ifdef HAVE_MLX5DV_DR
 975         void *domain;
 976
 977         if (sh->dv_refcnt) {
 978                 /* Shared DV/DR structures is already initialized. */
 979                 sh->dv_refcnt++;
 980                 priv->dr_shared = 1;
 981                 return 0;
 982         }
 983         /* Reference counter is zero, we should initialize structures. */
 984         domain = mlx5_glue->dr_create_domain(sh->ctx,
 985                                              MLX5DV_DR_DOMAIN_TYPE_NIC_RX);
 986         if (!domain) {
 987                 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed");
 988                 err = errno;
 989                 goto error;
 990         }
 991         sh->rx_domain = domain;
 992         domain = mlx5_glue->dr_create_domain(sh->ctx,
 993                                              MLX5DV_DR_DOMAIN_TYPE_NIC_TX);
 994         if (!domain) {
 995                 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed");
 996                 err = errno;
 997                 goto error;
 998         }
 999         pthread_mutex_init(&sh->dv_mutex, NULL);
1000         sh->tx_domain = domain;
1001 #ifdef HAVE_MLX5DV_DR_ESWITCH
1002         if (priv->config.dv_esw_en) {
1003                 domain  = mlx5_glue->dr_create_domain
1004                         (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB);
1005                 if (!domain) {
1006                         DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed");
1007                         err = errno;
1008                         goto error;
1009                 }
1010                 sh->fdb_domain = domain;
1011                 sh->esw_drop_action = mlx5_glue->dr_create_flow_action_drop();
1012         }
1013 #endif
1014         sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan();
1015 #endif /* HAVE_MLX5DV_DR */
1016         sh->dv_refcnt++;
1017         priv->dr_shared = 1;
1018         return 0;
1019 error:
1020         /* Rollback the created objects. */
1021         if (sh->rx_domain) {
1022                 mlx5_glue->dr_destroy_domain(sh->rx_domain);
1023                 sh->rx_domain = NULL;
1024         }
1025         if (sh->tx_domain) {
1026                 mlx5_glue->dr_destroy_domain(sh->tx_domain);
1027                 sh->tx_domain = NULL;
1028         }
1029         if (sh->fdb_domain) {
1030                 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
1031                 sh->fdb_domain = NULL;
1032         }
1033         if (sh->esw_drop_action) {
1034                 mlx5_glue->destroy_flow_action(sh->esw_drop_action);
1035                 sh->esw_drop_action = NULL;
1036         }
1037         if (sh->pop_vlan_action) {
1038                 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
1039                 sh->pop_vlan_action = NULL;
1040         }
1041         if (sh->tag_table) {
1042                 /* tags should be destroyed with flow before. */
1043                 mlx5_hlist_destroy(sh->tag_table, NULL, NULL);
1044                 sh->tag_table = NULL;
1045         }
1046         mlx5_free_table_hash_list(priv);
1047         return err;
1048 }
1049
1050 /**
1051  * Destroy DR related data within private structure.
1052  *
1053  * @param[in] priv
1054  *   Pointer to the private device data structure.
1055  */
1056 static void
1057 mlx5_free_shared_dr(struct mlx5_priv *priv)
1058 {
1059         struct mlx5_ibv_shared *sh;
1060
1061         if (!priv->dr_shared)
1062                 return;
1063         priv->dr_shared = 0;
1064         sh = priv->sh;
1065         MLX5_ASSERT(sh);
1066 #ifdef HAVE_MLX5DV_DR
1067         MLX5_ASSERT(sh->dv_refcnt);
1068         if (sh->dv_refcnt && --sh->dv_refcnt)
1069                 return;
1070         if (sh->rx_domain) {
1071                 mlx5_glue->dr_destroy_domain(sh->rx_domain);
1072                 sh->rx_domain = NULL;
1073         }
1074         if (sh->tx_domain) {
1075                 mlx5_glue->dr_destroy_domain(sh->tx_domain);
1076                 sh->tx_domain = NULL;
1077         }
1078 #ifdef HAVE_MLX5DV_DR_ESWITCH
1079         if (sh->fdb_domain) {
1080                 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
1081                 sh->fdb_domain = NULL;
1082         }
1083         if (sh->esw_drop_action) {
1084                 mlx5_glue->destroy_flow_action(sh->esw_drop_action);
1085                 sh->esw_drop_action = NULL;
1086         }
1087 #endif
1088         if (sh->pop_vlan_action) {
1089                 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
1090                 sh->pop_vlan_action = NULL;
1091         }
1092         pthread_mutex_destroy(&sh->dv_mutex);
1093 #endif /* HAVE_MLX5DV_DR */
1094         if (sh->tag_table) {
1095                 /* tags should be destroyed with flow before. */
1096                 mlx5_hlist_destroy(sh->tag_table, NULL, NULL);
1097                 sh->tag_table = NULL;
1098         }
1099         mlx5_free_table_hash_list(priv);
1100 }
1101
1102 /**
1103  * Initialize shared data between primary and secondary process.
1104  *
1105  * A memzone is reserved by primary process and secondary processes attach to
1106  * the memzone.
1107  *
1108  * @return
1109  *   0 on success, a negative errno value otherwise and rte_errno is set.
1110  */
1111 static int
1112 mlx5_init_shared_data(void)
1113 {
1114         const struct rte_memzone *mz;
1115         int ret = 0;
1116
1117         rte_spinlock_lock(&mlx5_shared_data_lock);
1118         if (mlx5_shared_data == NULL) {
1119                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
1120                         /* Allocate shared memory. */
1121                         mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
1122                                                  sizeof(*mlx5_shared_data),
1123                                                  SOCKET_ID_ANY, 0);
1124                         if (mz == NULL) {
1125                                 DRV_LOG(ERR,
1126                                         "Cannot allocate mlx5 shared data");
1127                                 ret = -rte_errno;
1128                                 goto error;
1129                         }
1130                         mlx5_shared_data = mz->addr;
1131                         memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
1132                         rte_spinlock_init(&mlx5_shared_data->lock);
1133                 } else {
1134                         /* Lookup allocated shared memory. */
1135                         mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
1136                         if (mz == NULL) {
1137                                 DRV_LOG(ERR,
1138                                         "Cannot attach mlx5 shared data");
1139                                 ret = -rte_errno;
1140                                 goto error;
1141                         }
1142                         mlx5_shared_data = mz->addr;
1143                         memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
1144                 }
1145         }
1146 error:
1147         rte_spinlock_unlock(&mlx5_shared_data_lock);
1148         return ret;
1149 }
1150
1151 /**
1152  * Retrieve integer value from environment variable.
1153  *
1154  * @param[in] name
1155  *   Environment variable name.
1156  *
1157  * @return
1158  *   Integer value, 0 if the variable is not set.
1159  */
1160 int
1161 mlx5_getenv_int(const char *name)
1162 {
1163         const char *val = getenv(name);
1164
1165         if (val == NULL)
1166                 return 0;
1167         return atoi(val);
1168 }
1169
1170 /**
1171  * Verbs callback to allocate a memory. This function should allocate the space
1172  * according to the size provided residing inside a huge page.
1173  * Please note that all allocation must respect the alignment from libmlx5
1174  * (i.e. currently sysconf(_SC_PAGESIZE)).
1175  *
1176  * @param[in] size
1177  *   The size in bytes of the memory to allocate.
1178  * @param[in] data
1179  *   A pointer to the callback data.
1180  *
1181  * @return
1182  *   Allocated buffer, NULL otherwise and rte_errno is set.
1183  */
1184 static void *
1185 mlx5_alloc_verbs_buf(size_t size, void *data)
1186 {
1187         struct mlx5_priv *priv = data;
1188         void *ret;
1189         size_t alignment = sysconf(_SC_PAGESIZE);
1190         unsigned int socket = SOCKET_ID_ANY;
1191
1192         if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
1193                 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
1194
1195                 socket = ctrl->socket;
1196         } else if (priv->verbs_alloc_ctx.type ==
1197                    MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
1198                 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
1199
1200                 socket = ctrl->socket;
1201         }
1202         MLX5_ASSERT(data != NULL);
1203         ret = rte_malloc_socket(__func__, size, alignment, socket);
1204         if (!ret && size)
1205                 rte_errno = ENOMEM;
1206         return ret;
1207 }
1208
1209 /**
1210  * Verbs callback to free a memory.
1211  *
1212  * @param[in] ptr
1213  *   A pointer to the memory to free.
1214  * @param[in] data
1215  *   A pointer to the callback data.
1216  */
1217 static void
1218 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
1219 {
1220         MLX5_ASSERT(data != NULL);
1221         rte_free(ptr);
1222 }
1223
1224 /**
1225  * DPDK callback to add udp tunnel port
1226  *
1227  * @param[in] dev
1228  *   A pointer to eth_dev
1229  * @param[in] udp_tunnel
1230  *   A pointer to udp tunnel
1231  *
1232  * @return
1233  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1234  */
1235 int
1236 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1237                          struct rte_eth_udp_tunnel *udp_tunnel)
1238 {
1239         MLX5_ASSERT(udp_tunnel != NULL);
1240         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1241             udp_tunnel->udp_port == 4789)
1242                 return 0;
1243         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1244             udp_tunnel->udp_port == 4790)
1245                 return 0;
1246         return -ENOTSUP;
1247 }
1248
1249 /**
1250  * Initialize process private data structure.
1251  *
1252  * @param dev
1253  *   Pointer to Ethernet device structure.
1254  *
1255  * @return
1256  *   0 on success, a negative errno value otherwise and rte_errno is set.
1257  */
1258 int
1259 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1260 {
1261         struct mlx5_priv *priv = dev->data->dev_private;
1262         struct mlx5_proc_priv *ppriv;
1263         size_t ppriv_size;
1264
1265         /*
1266          * UAR register table follows the process private structure. BlueFlame
1267          * registers for Tx queues are stored in the table.
1268          */
1269         ppriv_size =
1270                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1271         ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
1272                                   RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1273         if (!ppriv) {
1274                 rte_errno = ENOMEM;
1275                 return -rte_errno;
1276         }
1277         ppriv->uar_table_sz = ppriv_size;
1278         dev->process_private = ppriv;
1279         return 0;
1280 }
1281
1282 /**
1283  * Un-initialize process private data structure.
1284  *
1285  * @param dev
1286  *   Pointer to Ethernet device structure.
1287  */
1288 static void
1289 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1290 {
1291         if (!dev->process_private)
1292                 return;
1293         rte_free(dev->process_private);
1294         dev->process_private = NULL;
1295 }
1296
1297 /**
1298  * DPDK callback to close the device.
1299  *
1300  * Destroy all queues and objects, free memory.
1301  *
1302  * @param dev
1303  *   Pointer to Ethernet device structure.
1304  */
1305 static void
1306 mlx5_dev_close(struct rte_eth_dev *dev)
1307 {
1308         struct mlx5_priv *priv = dev->data->dev_private;
1309         unsigned int i;
1310         int ret;
1311
1312         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1313                 dev->data->port_id,
1314                 ((priv->sh->ctx != NULL) ? priv->sh->ctx->device->name : ""));
1315         /* In case mlx5_dev_stop() has not been called. */
1316         mlx5_dev_interrupt_handler_uninstall(dev);
1317         mlx5_dev_interrupt_handler_devx_uninstall(dev);
1318         /*
1319          * If default mreg copy action is removed at the stop stage,
1320          * the search will return none and nothing will be done anymore.
1321          */
1322         mlx5_flow_stop_default(dev);
1323         mlx5_traffic_disable(dev);
1324         /*
1325          * If all the flows are already flushed in the device stop stage,
1326          * then this will return directly without any action.
1327          */
1328         mlx5_flow_list_flush(dev, &priv->flows, true);
1329         mlx5_flow_meter_flush(dev, NULL);
1330         /* Free the intermediate buffers for flow creation. */
1331         mlx5_flow_free_intermediate(dev);
1332         /* Prevent crashes when queues are still in use. */
1333         dev->rx_pkt_burst = removed_rx_burst;
1334         dev->tx_pkt_burst = removed_tx_burst;
1335         rte_wmb();
1336         /* Disable datapath on secondary process. */
1337         mlx5_mp_req_stop_rxtx(dev);
1338         if (priv->rxqs != NULL) {
1339                 /* XXX race condition if mlx5_rx_burst() is still running. */
1340                 usleep(1000);
1341                 for (i = 0; (i != priv->rxqs_n); ++i)
1342                         mlx5_rxq_release(dev, i);
1343                 priv->rxqs_n = 0;
1344                 priv->rxqs = NULL;
1345         }
1346         if (priv->txqs != NULL) {
1347                 /* XXX race condition if mlx5_tx_burst() is still running. */
1348                 usleep(1000);
1349                 for (i = 0; (i != priv->txqs_n); ++i)
1350                         mlx5_txq_release(dev, i);
1351                 priv->txqs_n = 0;
1352                 priv->txqs = NULL;
1353         }
1354         mlx5_proc_priv_uninit(dev);
1355         if (priv->mreg_cp_tbl)
1356                 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1357         mlx5_mprq_free_mp(dev);
1358         mlx5_free_shared_dr(priv);
1359         if (priv->rss_conf.rss_key != NULL)
1360                 rte_free(priv->rss_conf.rss_key);
1361         if (priv->reta_idx != NULL)
1362                 rte_free(priv->reta_idx);
1363         if (priv->config.vf)
1364                 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1365                                        dev->data->mac_addrs,
1366                                        MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1367         if (priv->nl_socket_route >= 0)
1368                 close(priv->nl_socket_route);
1369         if (priv->nl_socket_rdma >= 0)
1370                 close(priv->nl_socket_rdma);
1371         if (priv->vmwa_context)
1372                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1373         if (priv->sh) {
1374                 /*
1375                  * Free the shared context in last turn, because the cleanup
1376                  * routines above may use some shared fields, like
1377                  * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1378                  * ifindex if Netlink fails.
1379                  */
1380                 mlx5_free_shared_ibctx(priv->sh);
1381                 priv->sh = NULL;
1382         }
1383         ret = mlx5_hrxq_verify(dev);
1384         if (ret)
1385                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1386                         dev->data->port_id);
1387         ret = mlx5_ind_table_obj_verify(dev);
1388         if (ret)
1389                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1390                         dev->data->port_id);
1391         ret = mlx5_rxq_obj_verify(dev);
1392         if (ret)
1393                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1394                         dev->data->port_id);
1395         ret = mlx5_rxq_verify(dev);
1396         if (ret)
1397                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1398                         dev->data->port_id);
1399         ret = mlx5_txq_obj_verify(dev);
1400         if (ret)
1401                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1402                         dev->data->port_id);
1403         ret = mlx5_txq_verify(dev);
1404         if (ret)
1405                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1406                         dev->data->port_id);
1407         ret = mlx5_flow_verify(dev);
1408         if (ret)
1409                 DRV_LOG(WARNING, "port %u some flows still remain",
1410                         dev->data->port_id);
1411         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1412                 unsigned int c = 0;
1413                 uint16_t port_id;
1414
1415                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1416                         struct mlx5_priv *opriv =
1417                                 rte_eth_devices[port_id].data->dev_private;
1418
1419                         if (!opriv ||
1420                             opriv->domain_id != priv->domain_id ||
1421                             &rte_eth_devices[port_id] == dev)
1422                                 continue;
1423                         ++c;
1424                         break;
1425                 }
1426                 if (!c)
1427                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1428         }
1429         memset(priv, 0, sizeof(*priv));
1430         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1431         /*
1432          * Reset mac_addrs to NULL such that it is not freed as part of
1433          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1434          * it is freed when dev_private is freed.
1435          */
1436         dev->data->mac_addrs = NULL;
1437 }
1438
1439 const struct eth_dev_ops mlx5_dev_ops = {
1440         .dev_configure = mlx5_dev_configure,
1441         .dev_start = mlx5_dev_start,
1442         .dev_stop = mlx5_dev_stop,
1443         .dev_set_link_down = mlx5_set_link_down,
1444         .dev_set_link_up = mlx5_set_link_up,
1445         .dev_close = mlx5_dev_close,
1446         .promiscuous_enable = mlx5_promiscuous_enable,
1447         .promiscuous_disable = mlx5_promiscuous_disable,
1448         .allmulticast_enable = mlx5_allmulticast_enable,
1449         .allmulticast_disable = mlx5_allmulticast_disable,
1450         .link_update = mlx5_link_update,
1451         .stats_get = mlx5_stats_get,
1452         .stats_reset = mlx5_stats_reset,
1453         .xstats_get = mlx5_xstats_get,
1454         .xstats_reset = mlx5_xstats_reset,
1455         .xstats_get_names = mlx5_xstats_get_names,
1456         .fw_version_get = mlx5_fw_version_get,
1457         .dev_infos_get = mlx5_dev_infos_get,
1458         .read_clock = mlx5_read_clock,
1459         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1460         .vlan_filter_set = mlx5_vlan_filter_set,
1461         .rx_queue_setup = mlx5_rx_queue_setup,
1462         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1463         .tx_queue_setup = mlx5_tx_queue_setup,
1464         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1465         .rx_queue_release = mlx5_rx_queue_release,
1466         .tx_queue_release = mlx5_tx_queue_release,
1467         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1468         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1469         .mac_addr_remove = mlx5_mac_addr_remove,
1470         .mac_addr_add = mlx5_mac_addr_add,
1471         .mac_addr_set = mlx5_mac_addr_set,
1472         .set_mc_addr_list = mlx5_set_mc_addr_list,
1473         .mtu_set = mlx5_dev_set_mtu,
1474         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1475         .vlan_offload_set = mlx5_vlan_offload_set,
1476         .reta_update = mlx5_dev_rss_reta_update,
1477         .reta_query = mlx5_dev_rss_reta_query,
1478         .rss_hash_update = mlx5_rss_hash_update,
1479         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1480         .filter_ctrl = mlx5_dev_filter_ctrl,
1481         .rx_descriptor_status = mlx5_rx_descriptor_status,
1482         .tx_descriptor_status = mlx5_tx_descriptor_status,
1483         .rxq_info_get = mlx5_rxq_info_get,
1484         .txq_info_get = mlx5_txq_info_get,
1485         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1486         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1487         .rx_queue_count = mlx5_rx_queue_count,
1488         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1489         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1490         .is_removed = mlx5_is_removed,
1491         .udp_tunnel_port_add  = mlx5_udp_tunnel_port_add,
1492         .get_module_info = mlx5_get_module_info,
1493         .get_module_eeprom = mlx5_get_module_eeprom,
1494         .hairpin_cap_get = mlx5_hairpin_cap_get,
1495         .mtr_ops_get = mlx5_flow_meter_ops_get,
1496 };
1497
1498 /* Available operations from secondary process. */
1499 static const struct eth_dev_ops mlx5_dev_sec_ops = {
1500         .stats_get = mlx5_stats_get,
1501         .stats_reset = mlx5_stats_reset,
1502         .xstats_get = mlx5_xstats_get,
1503         .xstats_reset = mlx5_xstats_reset,
1504         .xstats_get_names = mlx5_xstats_get_names,
1505         .fw_version_get = mlx5_fw_version_get,
1506         .dev_infos_get = mlx5_dev_infos_get,
1507         .rx_descriptor_status = mlx5_rx_descriptor_status,
1508         .tx_descriptor_status = mlx5_tx_descriptor_status,
1509         .rxq_info_get = mlx5_rxq_info_get,
1510         .txq_info_get = mlx5_txq_info_get,
1511         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1512         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1513         .get_module_info = mlx5_get_module_info,
1514         .get_module_eeprom = mlx5_get_module_eeprom,
1515 };
1516
1517 /* Available operations in flow isolated mode. */
1518 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1519         .dev_configure = mlx5_dev_configure,
1520         .dev_start = mlx5_dev_start,
1521         .dev_stop = mlx5_dev_stop,
1522         .dev_set_link_down = mlx5_set_link_down,
1523         .dev_set_link_up = mlx5_set_link_up,
1524         .dev_close = mlx5_dev_close,
1525         .promiscuous_enable = mlx5_promiscuous_enable,
1526         .promiscuous_disable = mlx5_promiscuous_disable,
1527         .allmulticast_enable = mlx5_allmulticast_enable,
1528         .allmulticast_disable = mlx5_allmulticast_disable,
1529         .link_update = mlx5_link_update,
1530         .stats_get = mlx5_stats_get,
1531         .stats_reset = mlx5_stats_reset,
1532         .xstats_get = mlx5_xstats_get,
1533         .xstats_reset = mlx5_xstats_reset,
1534         .xstats_get_names = mlx5_xstats_get_names,
1535         .fw_version_get = mlx5_fw_version_get,
1536         .dev_infos_get = mlx5_dev_infos_get,
1537         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1538         .vlan_filter_set = mlx5_vlan_filter_set,
1539         .rx_queue_setup = mlx5_rx_queue_setup,
1540         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1541         .tx_queue_setup = mlx5_tx_queue_setup,
1542         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1543         .rx_queue_release = mlx5_rx_queue_release,
1544         .tx_queue_release = mlx5_tx_queue_release,
1545         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1546         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1547         .mac_addr_remove = mlx5_mac_addr_remove,
1548         .mac_addr_add = mlx5_mac_addr_add,
1549         .mac_addr_set = mlx5_mac_addr_set,
1550         .set_mc_addr_list = mlx5_set_mc_addr_list,
1551         .mtu_set = mlx5_dev_set_mtu,
1552         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1553         .vlan_offload_set = mlx5_vlan_offload_set,
1554         .filter_ctrl = mlx5_dev_filter_ctrl,
1555         .rx_descriptor_status = mlx5_rx_descriptor_status,
1556         .tx_descriptor_status = mlx5_tx_descriptor_status,
1557         .rxq_info_get = mlx5_rxq_info_get,
1558         .txq_info_get = mlx5_txq_info_get,
1559         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1560         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1561         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1562         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1563         .is_removed = mlx5_is_removed,
1564         .get_module_info = mlx5_get_module_info,
1565         .get_module_eeprom = mlx5_get_module_eeprom,
1566         .hairpin_cap_get = mlx5_hairpin_cap_get,
1567         .mtr_ops_get = mlx5_flow_meter_ops_get,
1568 };
1569
1570 /**
1571  * Verify and store value for device argument.
1572  *
1573  * @param[in] key
1574  *   Key argument to verify.
1575  * @param[in] val
1576  *   Value associated with key.
1577  * @param opaque
1578  *   User data.
1579  *
1580  * @return
1581  *   0 on success, a negative errno value otherwise and rte_errno is set.
1582  */
1583 static int
1584 mlx5_args_check(const char *key, const char *val, void *opaque)
1585 {
1586         struct mlx5_dev_config *config = opaque;
1587         unsigned long tmp;
1588
1589         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1590         if (!strcmp(MLX5_REPRESENTOR, key))
1591                 return 0;
1592         errno = 0;
1593         tmp = strtoul(val, NULL, 0);
1594         if (errno) {
1595                 rte_errno = errno;
1596                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1597                 return -rte_errno;
1598         }
1599         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1600                 config->cqe_comp = !!tmp;
1601         } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1602                 config->cqe_pad = !!tmp;
1603         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1604                 config->hw_padding = !!tmp;
1605         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1606                 config->mprq.enabled = !!tmp;
1607         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1608                 config->mprq.stride_num_n = tmp;
1609         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1610                 config->mprq.stride_size_n = tmp;
1611         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1612                 config->mprq.max_memcpy_len = tmp;
1613         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1614                 config->mprq.min_rxqs_num = tmp;
1615         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1616                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1617                                  " converted to txq_inline_max", key);
1618                 config->txq_inline_max = tmp;
1619         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1620                 config->txq_inline_max = tmp;
1621         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1622                 config->txq_inline_min = tmp;
1623         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1624                 config->txq_inline_mpw = tmp;
1625         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1626                 config->txqs_inline = tmp;
1627         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1628                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1629         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1630                 config->mps = !!tmp;
1631         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1632                 if (tmp != MLX5_TXDB_CACHED &&
1633                     tmp != MLX5_TXDB_NCACHED &&
1634                     tmp != MLX5_TXDB_HEURISTIC) {
1635                         DRV_LOG(ERR, "invalid Tx doorbell "
1636                                      "mapping parameter");
1637                         rte_errno = EINVAL;
1638                         return -rte_errno;
1639                 }
1640                 config->dbnc = tmp;
1641         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1642                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1643         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1644                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1645                                  " converted to txq_inline_mpw", key);
1646                 config->txq_inline_mpw = tmp;
1647         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1648                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1649         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1650                 config->rx_vec_en = !!tmp;
1651         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1652                 config->l3_vxlan_en = !!tmp;
1653         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1654                 config->vf_nl_en = !!tmp;
1655         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1656                 config->dv_esw_en = !!tmp;
1657         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1658                 config->dv_flow_en = !!tmp;
1659         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1660                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1661                     tmp != MLX5_XMETA_MODE_META16 &&
1662                     tmp != MLX5_XMETA_MODE_META32) {
1663                         DRV_LOG(ERR, "invalid extensive "
1664                                      "metadata parameter");
1665                         rte_errno = EINVAL;
1666                         return -rte_errno;
1667                 }
1668                 config->dv_xmeta_en = tmp;
1669         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1670                 config->mr_ext_memseg_en = !!tmp;
1671         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1672                 config->max_dump_files_num = tmp;
1673         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1674                 config->lro.timeout = tmp;
1675         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1676                 DRV_LOG(DEBUG, "class argument is %s.", val);
1677         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1678                 config->log_hp_size = tmp;
1679         } else {
1680                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1681                 rte_errno = EINVAL;
1682                 return -rte_errno;
1683         }
1684         return 0;
1685 }
1686
1687 /**
1688  * Parse device parameters.
1689  *
1690  * @param config
1691  *   Pointer to device configuration structure.
1692  * @param devargs
1693  *   Device arguments structure.
1694  *
1695  * @return
1696  *   0 on success, a negative errno value otherwise and rte_errno is set.
1697  */
1698 static int
1699 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1700 {
1701         const char **params = (const char *[]){
1702                 MLX5_RXQ_CQE_COMP_EN,
1703                 MLX5_RXQ_CQE_PAD_EN,
1704                 MLX5_RXQ_PKT_PAD_EN,
1705                 MLX5_RX_MPRQ_EN,
1706                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1707                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1708                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1709                 MLX5_RXQS_MIN_MPRQ,
1710                 MLX5_TXQ_INLINE,
1711                 MLX5_TXQ_INLINE_MIN,
1712                 MLX5_TXQ_INLINE_MAX,
1713                 MLX5_TXQ_INLINE_MPW,
1714                 MLX5_TXQS_MIN_INLINE,
1715                 MLX5_TXQS_MAX_VEC,
1716                 MLX5_TXQ_MPW_EN,
1717                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1718                 MLX5_TXQ_MAX_INLINE_LEN,
1719                 MLX5_TX_DB_NC,
1720                 MLX5_TX_VEC_EN,
1721                 MLX5_RX_VEC_EN,
1722                 MLX5_L3_VXLAN_EN,
1723                 MLX5_VF_NL_EN,
1724                 MLX5_DV_ESW_EN,
1725                 MLX5_DV_FLOW_EN,
1726                 MLX5_DV_XMETA_EN,
1727                 MLX5_MR_EXT_MEMSEG_EN,
1728                 MLX5_REPRESENTOR,
1729                 MLX5_MAX_DUMP_FILES_NUM,
1730                 MLX5_LRO_TIMEOUT_USEC,
1731                 MLX5_CLASS_ARG_NAME,
1732                 MLX5_HP_BUF_SIZE,
1733                 NULL,
1734         };
1735         struct rte_kvargs *kvlist;
1736         int ret = 0;
1737         int i;
1738
1739         if (devargs == NULL)
1740                 return 0;
1741         /* Following UGLY cast is done to pass checkpatch. */
1742         kvlist = rte_kvargs_parse(devargs->args, params);
1743         if (kvlist == NULL) {
1744                 rte_errno = EINVAL;
1745                 return -rte_errno;
1746         }
1747         /* Process parameters. */
1748         for (i = 0; (params[i] != NULL); ++i) {
1749                 if (rte_kvargs_count(kvlist, params[i])) {
1750                         ret = rte_kvargs_process(kvlist, params[i],
1751                                                  mlx5_args_check, config);
1752                         if (ret) {
1753                                 rte_errno = EINVAL;
1754                                 rte_kvargs_free(kvlist);
1755                                 return -rte_errno;
1756                         }
1757                 }
1758         }
1759         rte_kvargs_free(kvlist);
1760         return 0;
1761 }
1762
1763 static struct rte_pci_driver mlx5_driver;
1764
1765 /**
1766  * PMD global initialization.
1767  *
1768  * Independent from individual device, this function initializes global
1769  * per-PMD data structures distinguishing primary and secondary processes.
1770  * Hence, each initialization is called once per a process.
1771  *
1772  * @return
1773  *   0 on success, a negative errno value otherwise and rte_errno is set.
1774  */
1775 static int
1776 mlx5_init_once(void)
1777 {
1778         struct mlx5_shared_data *sd;
1779         struct mlx5_local_data *ld = &mlx5_local_data;
1780         int ret = 0;
1781
1782         if (mlx5_init_shared_data())
1783                 return -rte_errno;
1784         sd = mlx5_shared_data;
1785         MLX5_ASSERT(sd);
1786         rte_spinlock_lock(&sd->lock);
1787         switch (rte_eal_process_type()) {
1788         case RTE_PROC_PRIMARY:
1789                 if (sd->init_done)
1790                         break;
1791                 LIST_INIT(&sd->mem_event_cb_list);
1792                 rte_rwlock_init(&sd->mem_event_rwlock);
1793                 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1794                                                 mlx5_mr_mem_event_cb, NULL);
1795                 ret = mlx5_mp_init_primary(MLX5_MP_NAME,
1796                                            mlx5_mp_primary_handle);
1797                 if (ret)
1798                         goto out;
1799                 sd->init_done = true;
1800                 break;
1801         case RTE_PROC_SECONDARY:
1802                 if (ld->init_done)
1803                         break;
1804                 ret = mlx5_mp_init_secondary(MLX5_MP_NAME,
1805                                              mlx5_mp_secondary_handle);
1806                 if (ret)
1807                         goto out;
1808                 ++sd->secondary_cnt;
1809                 ld->init_done = true;
1810                 break;
1811         default:
1812                 break;
1813         }
1814 out:
1815         rte_spinlock_unlock(&sd->lock);
1816         return ret;
1817 }
1818
1819 /**
1820  * Configures the minimal amount of data to inline into WQE
1821  * while sending packets.
1822  *
1823  * - the txq_inline_min has the maximal priority, if this
1824  *   key is specified in devargs
1825  * - if DevX is enabled the inline mode is queried from the
1826  *   device (HCA attributes and NIC vport context if needed).
1827  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1828  *   and none (0 bytes) for other NICs
1829  *
1830  * @param spawn
1831  *   Verbs device parameters (name, port, switch_info) to spawn.
1832  * @param config
1833  *   Device configuration parameters.
1834  */
1835 static void
1836 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1837                     struct mlx5_dev_config *config)
1838 {
1839         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1840                 /* Application defines size of inlined data explicitly. */
1841                 switch (spawn->pci_dev->id.device_id) {
1842                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1843                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1844                         if (config->txq_inline_min <
1845                                        (int)MLX5_INLINE_HSIZE_L2) {
1846                                 DRV_LOG(DEBUG,
1847                                         "txq_inline_mix aligned to minimal"
1848                                         " ConnectX-4 required value %d",
1849                                         (int)MLX5_INLINE_HSIZE_L2);
1850                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1851                         }
1852                         break;
1853                 }
1854                 goto exit;
1855         }
1856         if (config->hca_attr.eth_net_offloads) {
1857                 /* We have DevX enabled, inline mode queried successfully. */
1858                 switch (config->hca_attr.wqe_inline_mode) {
1859                 case MLX5_CAP_INLINE_MODE_L2:
1860                         /* outer L2 header must be inlined. */
1861                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1862                         goto exit;
1863                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1864                         /* No inline data are required by NIC. */
1865                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1866                         config->hw_vlan_insert =
1867                                 config->hca_attr.wqe_vlan_insert;
1868                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1869                         goto exit;
1870                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1871                         /* inline mode is defined by NIC vport context. */
1872                         if (!config->hca_attr.eth_virt)
1873                                 break;
1874                         switch (config->hca_attr.vport_inline_mode) {
1875                         case MLX5_INLINE_MODE_NONE:
1876                                 config->txq_inline_min =
1877                                         MLX5_INLINE_HSIZE_NONE;
1878                                 goto exit;
1879                         case MLX5_INLINE_MODE_L2:
1880                                 config->txq_inline_min =
1881                                         MLX5_INLINE_HSIZE_L2;
1882                                 goto exit;
1883                         case MLX5_INLINE_MODE_IP:
1884                                 config->txq_inline_min =
1885                                         MLX5_INLINE_HSIZE_L3;
1886                                 goto exit;
1887                         case MLX5_INLINE_MODE_TCP_UDP:
1888                                 config->txq_inline_min =
1889                                         MLX5_INLINE_HSIZE_L4;
1890                                 goto exit;
1891                         case MLX5_INLINE_MODE_INNER_L2:
1892                                 config->txq_inline_min =
1893                                         MLX5_INLINE_HSIZE_INNER_L2;
1894                                 goto exit;
1895                         case MLX5_INLINE_MODE_INNER_IP:
1896                                 config->txq_inline_min =
1897                                         MLX5_INLINE_HSIZE_INNER_L3;
1898                                 goto exit;
1899                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
1900                                 config->txq_inline_min =
1901                                         MLX5_INLINE_HSIZE_INNER_L4;
1902                                 goto exit;
1903                         }
1904                 }
1905         }
1906         /*
1907          * We get here if we are unable to deduce
1908          * inline data size with DevX. Try PCI ID
1909          * to determine old NICs.
1910          */
1911         switch (spawn->pci_dev->id.device_id) {
1912         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1913         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1914         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1915         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1916                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1917                 config->hw_vlan_insert = 0;
1918                 break;
1919         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1920         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1921         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1922         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1923                 /*
1924                  * These NICs support VLAN insertion from WQE and
1925                  * report the wqe_vlan_insert flag. But there is the bug
1926                  * and PFC control may be broken, so disable feature.
1927                  */
1928                 config->hw_vlan_insert = 0;
1929                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1930                 break;
1931         default:
1932                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1933                 break;
1934         }
1935 exit:
1936         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1937 }
1938
1939 /**
1940  * Configures the metadata mask fields in the shared context.
1941  *
1942  * @param [in] dev
1943  *   Pointer to Ethernet device.
1944  */
1945 static void
1946 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1947 {
1948         struct mlx5_priv *priv = dev->data->dev_private;
1949         struct mlx5_ibv_shared *sh = priv->sh;
1950         uint32_t meta, mark, reg_c0;
1951
1952         reg_c0 = ~priv->vport_meta_mask;
1953         switch (priv->config.dv_xmeta_en) {
1954         case MLX5_XMETA_MODE_LEGACY:
1955                 meta = UINT32_MAX;
1956                 mark = MLX5_FLOW_MARK_MASK;
1957                 break;
1958         case MLX5_XMETA_MODE_META16:
1959                 meta = reg_c0 >> rte_bsf32(reg_c0);
1960                 mark = MLX5_FLOW_MARK_MASK;
1961                 break;
1962         case MLX5_XMETA_MODE_META32:
1963                 meta = UINT32_MAX;
1964                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1965                 break;
1966         default:
1967                 meta = 0;
1968                 mark = 0;
1969                 MLX5_ASSERT(false);
1970                 break;
1971         }
1972         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1973                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1974                                  sh->dv_mark_mask, mark);
1975         else
1976                 sh->dv_mark_mask = mark;
1977         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1978                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1979                                  sh->dv_meta_mask, meta);
1980         else
1981                 sh->dv_meta_mask = meta;
1982         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1983                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1984                                  sh->dv_meta_mask, reg_c0);
1985         else
1986                 sh->dv_regc0_mask = reg_c0;
1987         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1988         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1989         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1990         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1991 }
1992
1993 /**
1994  * Allocate page of door-bells and register it using DevX API.
1995  *
1996  * @param [in] dev
1997  *   Pointer to Ethernet device.
1998  *
1999  * @return
2000  *   Pointer to new page on success, NULL otherwise.
2001  */
2002 static struct mlx5_devx_dbr_page *
2003 mlx5_alloc_dbr_page(struct rte_eth_dev *dev)
2004 {
2005         struct mlx5_priv *priv = dev->data->dev_private;
2006         struct mlx5_devx_dbr_page *page;
2007
2008         /* Allocate space for door-bell page and management data. */
2009         page = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_devx_dbr_page),
2010                                  RTE_CACHE_LINE_SIZE, dev->device->numa_node);
2011         if (!page) {
2012                 DRV_LOG(ERR, "port %u cannot allocate dbr page",
2013                         dev->data->port_id);
2014                 return NULL;
2015         }
2016         /* Register allocated memory. */
2017         page->umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, page->dbrs,
2018                                               MLX5_DBR_PAGE_SIZE, 0);
2019         if (!page->umem) {
2020                 DRV_LOG(ERR, "port %u cannot umem reg dbr page",
2021                         dev->data->port_id);
2022                 rte_free(page);
2023                 return NULL;
2024         }
2025         return page;
2026 }
2027
2028 /**
2029  * Find the next available door-bell, allocate new page if needed.
2030  *
2031  * @param [in] dev
2032  *   Pointer to Ethernet device.
2033  * @param [out] dbr_page
2034  *   Door-bell page containing the page data.
2035  *
2036  * @return
2037  *   Door-bell address offset on success, a negative error value otherwise.
2038  */
2039 int64_t
2040 mlx5_get_dbr(struct rte_eth_dev *dev, struct mlx5_devx_dbr_page **dbr_page)
2041 {
2042         struct mlx5_priv *priv = dev->data->dev_private;
2043         struct mlx5_devx_dbr_page *page = NULL;
2044         uint32_t i, j;
2045
2046         LIST_FOREACH(page, &priv->dbrpgs, next)
2047                 if (page->dbr_count < MLX5_DBR_PER_PAGE)
2048                         break;
2049         if (!page) { /* No page with free door-bell exists. */
2050                 page = mlx5_alloc_dbr_page(dev);
2051                 if (!page) /* Failed to allocate new page. */
2052                         return (-1);
2053                 LIST_INSERT_HEAD(&priv->dbrpgs, page, next);
2054         }
2055         /* Loop to find bitmap part with clear bit. */
2056         for (i = 0;
2057              i < MLX5_DBR_BITMAP_SIZE && page->dbr_bitmap[i] == UINT64_MAX;
2058              i++)
2059                 ; /* Empty. */
2060         /* Find the first clear bit. */
2061         j = rte_bsf64(~page->dbr_bitmap[i]);
2062         MLX5_ASSERT(i < (MLX5_DBR_PER_PAGE / 64));
2063         page->dbr_bitmap[i] |= (1 << j);
2064         page->dbr_count++;
2065         *dbr_page = page;
2066         return (((i * 64) + j) * sizeof(uint64_t));
2067 }
2068
2069 /**
2070  * Release a door-bell record.
2071  *
2072  * @param [in] dev
2073  *   Pointer to Ethernet device.
2074  * @param [in] umem_id
2075  *   UMEM ID of page containing the door-bell record to release.
2076  * @param [in] offset
2077  *   Offset of door-bell record in page.
2078  *
2079  * @return
2080  *   0 on success, a negative error value otherwise.
2081  */
2082 int32_t
2083 mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id, uint64_t offset)
2084 {
2085         struct mlx5_priv *priv = dev->data->dev_private;
2086         struct mlx5_devx_dbr_page *page = NULL;
2087         int ret = 0;
2088
2089         LIST_FOREACH(page, &priv->dbrpgs, next)
2090                 /* Find the page this address belongs to. */
2091                 if (page->umem->umem_id == umem_id)
2092                         break;
2093         if (!page)
2094                 return -EINVAL;
2095         page->dbr_count--;
2096         if (!page->dbr_count) {
2097                 /* Page not used, free it and remove from list. */
2098                 LIST_REMOVE(page, next);
2099                 if (page->umem)
2100                         ret = -mlx5_glue->devx_umem_dereg(page->umem);
2101                 rte_free(page);
2102         } else {
2103                 /* Mark in bitmap that this door-bell is not in use. */
2104                 offset /= MLX5_DBR_SIZE;
2105                 int i = offset / 64;
2106                 int j = offset % 64;
2107
2108                 page->dbr_bitmap[i] &= ~(1 << j);
2109         }
2110         return ret;
2111 }
2112
2113 int
2114 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2115 {
2116         static const char *const dynf_names[] = {
2117                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2118                 RTE_MBUF_DYNFLAG_METADATA_NAME
2119         };
2120         unsigned int i;
2121
2122         if (n < RTE_DIM(dynf_names))
2123                 return -ENOMEM;
2124         for (i = 0; i < RTE_DIM(dynf_names); i++) {
2125                 if (names[i] == NULL)
2126                         return -EINVAL;
2127                 strcpy(names[i], dynf_names[i]);
2128         }
2129         return RTE_DIM(dynf_names);
2130 }
2131
2132 /**
2133  * Check sibling device configurations.
2134  *
2135  * Sibling devices sharing the Infiniband device context
2136  * should have compatible configurations. This regards
2137  * representors and bonding slaves.
2138  *
2139  * @param priv
2140  *   Private device descriptor.
2141  * @param config
2142  *   Configuration of the device is going to be created.
2143  *
2144  * @return
2145  *   0 on success, EINVAL otherwise
2146  */
2147 static int
2148 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2149                               struct mlx5_dev_config *config)
2150 {
2151         struct mlx5_ibv_shared *sh = priv->sh;
2152         struct mlx5_dev_config *sh_conf = NULL;
2153         uint16_t port_id;
2154
2155         MLX5_ASSERT(sh);
2156         /* Nothing to compare for the single/first device. */
2157         if (sh->refcnt == 1)
2158                 return 0;
2159         /* Find the device with shared context. */
2160         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2161                 struct mlx5_priv *opriv =
2162                         rte_eth_devices[port_id].data->dev_private;
2163
2164                 if (opriv && opriv != priv && opriv->sh == sh) {
2165                         sh_conf = &opriv->config;
2166                         break;
2167                 }
2168         }
2169         if (!sh_conf)
2170                 return 0;
2171         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2172                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2173                              " for shared %s context", sh->ibdev_name);
2174                 rte_errno = EINVAL;
2175                 return rte_errno;
2176         }
2177         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2178                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2179                              " for shared %s context", sh->ibdev_name);
2180                 rte_errno = EINVAL;
2181                 return rte_errno;
2182         }
2183         return 0;
2184 }
2185 /**
2186  * Spawn an Ethernet device from Verbs information.
2187  *
2188  * @param dpdk_dev
2189  *   Backing DPDK device.
2190  * @param spawn
2191  *   Verbs device parameters (name, port, switch_info) to spawn.
2192  * @param config
2193  *   Device configuration parameters.
2194  *
2195  * @return
2196  *   A valid Ethernet device object on success, NULL otherwise and rte_errno
2197  *   is set. The following errors are defined:
2198  *
2199  *   EBUSY: device is not supposed to be spawned.
2200  *   EEXIST: device is already spawned
2201  */
2202 static struct rte_eth_dev *
2203 mlx5_dev_spawn(struct rte_device *dpdk_dev,
2204                struct mlx5_dev_spawn_data *spawn,
2205                struct mlx5_dev_config config)
2206 {
2207         const struct mlx5_switch_info *switch_info = &spawn->info;
2208         struct mlx5_ibv_shared *sh = NULL;
2209         struct ibv_port_attr port_attr;
2210         struct mlx5dv_context dv_attr = { .comp_mask = 0 };
2211         struct rte_eth_dev *eth_dev = NULL;
2212         struct mlx5_priv *priv = NULL;
2213         int err = 0;
2214         unsigned int hw_padding = 0;
2215         unsigned int mps;
2216         unsigned int cqe_comp;
2217         unsigned int cqe_pad = 0;
2218         unsigned int tunnel_en = 0;
2219         unsigned int mpls_en = 0;
2220         unsigned int swp = 0;
2221         unsigned int mprq = 0;
2222         unsigned int mprq_min_stride_size_n = 0;
2223         unsigned int mprq_max_stride_size_n = 0;
2224         unsigned int mprq_min_stride_num_n = 0;
2225         unsigned int mprq_max_stride_num_n = 0;
2226         struct rte_ether_addr mac;
2227         char name[RTE_ETH_NAME_MAX_LEN];
2228         int own_domain_id = 0;
2229         uint16_t port_id;
2230         unsigned int i;
2231 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
2232         struct mlx5dv_devx_port devx_port = { .comp_mask = 0 };
2233 #endif
2234
2235         /* Determine if this port representor is supposed to be spawned. */
2236         if (switch_info->representor && dpdk_dev->devargs) {
2237                 struct rte_eth_devargs eth_da;
2238
2239                 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, &eth_da);
2240                 if (err) {
2241                         rte_errno = -err;
2242                         DRV_LOG(ERR, "failed to process device arguments: %s",
2243                                 strerror(rte_errno));
2244                         return NULL;
2245                 }
2246                 for (i = 0; i < eth_da.nb_representor_ports; ++i)
2247                         if (eth_da.representor_ports[i] ==
2248                             (uint16_t)switch_info->port_name)
2249                                 break;
2250                 if (i == eth_da.nb_representor_ports) {
2251                         rte_errno = EBUSY;
2252                         return NULL;
2253                 }
2254         }
2255         /* Build device name. */
2256         if (spawn->pf_bond <  0) {
2257                 /* Single device. */
2258                 if (!switch_info->representor)
2259                         strlcpy(name, dpdk_dev->name, sizeof(name));
2260                 else
2261                         snprintf(name, sizeof(name), "%s_representor_%u",
2262                                  dpdk_dev->name, switch_info->port_name);
2263         } else {
2264                 /* Bonding device. */
2265                 if (!switch_info->representor)
2266                         snprintf(name, sizeof(name), "%s_%s",
2267                                  dpdk_dev->name, spawn->ibv_dev->name);
2268                 else
2269                         snprintf(name, sizeof(name), "%s_%s_representor_%u",
2270                                  dpdk_dev->name, spawn->ibv_dev->name,
2271                                  switch_info->port_name);
2272         }
2273         /* check if the device is already spawned */
2274         if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
2275                 rte_errno = EEXIST;
2276                 return NULL;
2277         }
2278         DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
2279         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
2280                 struct mlx5_mp_id mp_id;
2281
2282                 eth_dev = rte_eth_dev_attach_secondary(name);
2283                 if (eth_dev == NULL) {
2284                         DRV_LOG(ERR, "can not attach rte ethdev");
2285                         rte_errno = ENOMEM;
2286                         return NULL;
2287                 }
2288                 eth_dev->device = dpdk_dev;
2289                 eth_dev->dev_ops = &mlx5_dev_sec_ops;
2290                 err = mlx5_proc_priv_init(eth_dev);
2291                 if (err)
2292                         return NULL;
2293                 mp_id.port_id = eth_dev->data->port_id;
2294                 strlcpy(mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);
2295                 /* Receive command fd from primary process */
2296                 err = mlx5_mp_req_verbs_cmd_fd(&mp_id);
2297                 if (err < 0)
2298                         return NULL;
2299                 /* Remap UAR for Tx queues. */
2300                 err = mlx5_tx_uar_init_secondary(eth_dev, err);
2301                 if (err)
2302                         return NULL;
2303                 /*
2304                  * Ethdev pointer is still required as input since
2305                  * the primary device is not accessible from the
2306                  * secondary process.
2307                  */
2308                 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev);
2309                 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev);
2310                 return eth_dev;
2311         }
2312         /*
2313          * Some parameters ("tx_db_nc" in particularly) are needed in
2314          * advance to create dv/verbs device context. We proceed the
2315          * devargs here to get ones, and later proceed devargs again
2316          * to override some hardware settings.
2317          */
2318         err = mlx5_args(&config, dpdk_dev->devargs);
2319         if (err) {
2320                 err = rte_errno;
2321                 DRV_LOG(ERR, "failed to process device arguments: %s",
2322                         strerror(rte_errno));
2323                 goto error;
2324         }
2325         sh = mlx5_alloc_shared_ibctx(spawn, &config);
2326         if (!sh)
2327                 return NULL;
2328         config.devx = sh->devx;
2329 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR
2330         config.dest_tir = 1;
2331 #endif
2332 #ifdef HAVE_IBV_MLX5_MOD_SWP
2333         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
2334 #endif
2335         /*
2336          * Multi-packet send is supported by ConnectX-4 Lx PF as well
2337          * as all ConnectX-5 devices.
2338          */
2339 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2340         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
2341 #endif
2342 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
2343         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
2344 #endif
2345         mlx5_glue->dv_query_device(sh->ctx, &dv_attr);
2346         if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
2347                 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
2348                         DRV_LOG(DEBUG, "enhanced MPW is supported");
2349                         mps = MLX5_MPW_ENHANCED;
2350                 } else {
2351                         DRV_LOG(DEBUG, "MPW is supported");
2352                         mps = MLX5_MPW;
2353                 }
2354         } else {
2355                 DRV_LOG(DEBUG, "MPW isn't supported");
2356                 mps = MLX5_MPW_DISABLED;
2357         }
2358 #ifdef HAVE_IBV_MLX5_MOD_SWP
2359         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
2360                 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
2361         DRV_LOG(DEBUG, "SWP support: %u", swp);
2362 #endif
2363         config.swp = !!swp;
2364 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
2365         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
2366                 struct mlx5dv_striding_rq_caps mprq_caps =
2367                         dv_attr.striding_rq_caps;
2368
2369                 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
2370                         mprq_caps.min_single_stride_log_num_of_bytes);
2371                 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
2372                         mprq_caps.max_single_stride_log_num_of_bytes);
2373                 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
2374                         mprq_caps.min_single_wqe_log_num_of_strides);
2375                 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
2376                         mprq_caps.max_single_wqe_log_num_of_strides);
2377                 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
2378                         mprq_caps.supported_qpts);
2379                 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
2380                 mprq = 1;
2381                 mprq_min_stride_size_n =
2382                         mprq_caps.min_single_stride_log_num_of_bytes;
2383                 mprq_max_stride_size_n =
2384                         mprq_caps.max_single_stride_log_num_of_bytes;
2385                 mprq_min_stride_num_n =
2386                         mprq_caps.min_single_wqe_log_num_of_strides;
2387                 mprq_max_stride_num_n =
2388                         mprq_caps.max_single_wqe_log_num_of_strides;
2389         }
2390 #endif
2391         if (RTE_CACHE_LINE_SIZE == 128 &&
2392             !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
2393                 cqe_comp = 0;
2394         else
2395                 cqe_comp = 1;
2396         config.cqe_comp = cqe_comp;
2397 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
2398         /* Whether device supports 128B Rx CQE padding. */
2399         cqe_pad = RTE_CACHE_LINE_SIZE == 128 &&
2400                   (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD);
2401 #endif
2402 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2403         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
2404                 tunnel_en = ((dv_attr.tunnel_offloads_caps &
2405                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
2406                              (dv_attr.tunnel_offloads_caps &
2407                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) &&
2408                              (dv_attr.tunnel_offloads_caps &
2409                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE));
2410         }
2411         DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
2412                 tunnel_en ? "" : "not ");
2413 #else
2414         DRV_LOG(WARNING,
2415                 "tunnel offloading disabled due to old OFED/rdma-core version");
2416 #endif
2417         config.tunnel_en = tunnel_en;
2418 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
2419         mpls_en = ((dv_attr.tunnel_offloads_caps &
2420                     MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
2421                    (dv_attr.tunnel_offloads_caps &
2422                     MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
2423         DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
2424                 mpls_en ? "" : "not ");
2425 #else
2426         DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
2427                 " old OFED/rdma-core version or firmware configuration");
2428 #endif
2429         config.mpls_en = mpls_en;
2430         /* Check port status. */
2431         err = mlx5_glue->query_port(sh->ctx, spawn->ibv_port, &port_attr);
2432         if (err) {
2433                 DRV_LOG(ERR, "port query failed: %s", strerror(err));
2434                 goto error;
2435         }
2436         if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
2437                 DRV_LOG(ERR, "port is not configured in Ethernet mode");
2438                 err = EINVAL;
2439                 goto error;
2440         }
2441         if (port_attr.state != IBV_PORT_ACTIVE)
2442                 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)",
2443                         mlx5_glue->port_state_str(port_attr.state),
2444                         port_attr.state);
2445         /* Allocate private eth device data. */
2446         priv = rte_zmalloc("ethdev private structure",
2447                            sizeof(*priv),
2448                            RTE_CACHE_LINE_SIZE);
2449         if (priv == NULL) {
2450                 DRV_LOG(ERR, "priv allocation failure");
2451                 err = ENOMEM;
2452                 goto error;
2453         }
2454         priv->sh = sh;
2455         priv->ibv_port = spawn->ibv_port;
2456         priv->pci_dev = spawn->pci_dev;
2457         priv->mtu = RTE_ETHER_MTU;
2458         priv->mp_id.port_id = port_id;
2459         strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);
2460 #ifndef RTE_ARCH_64
2461         /* Initialize UAR access locks for 32bit implementations. */
2462         rte_spinlock_init(&priv->uar_lock_cq);
2463         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
2464                 rte_spinlock_init(&priv->uar_lock[i]);
2465 #endif
2466         /* Some internal functions rely on Netlink sockets, open them now. */
2467         priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA);
2468         priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE);
2469         priv->representor = !!switch_info->representor;
2470         priv->master = !!switch_info->master;
2471         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
2472         priv->vport_meta_tag = 0;
2473         priv->vport_meta_mask = 0;
2474         priv->pf_bond = spawn->pf_bond;
2475 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
2476         /*
2477          * The DevX port query API is implemented. E-Switch may use
2478          * either vport or reg_c[0] metadata register to match on
2479          * vport index. The engaged part of metadata register is
2480          * defined by mask.
2481          */
2482         if (switch_info->representor || switch_info->master) {
2483                 devx_port.comp_mask = MLX5DV_DEVX_PORT_VPORT |
2484                                       MLX5DV_DEVX_PORT_MATCH_REG_C_0;
2485                 err = mlx5_glue->devx_port_query(sh->ctx, spawn->ibv_port,
2486                                                  &devx_port);
2487                 if (err) {
2488                         DRV_LOG(WARNING,
2489                                 "can't query devx port %d on device %s",
2490                                 spawn->ibv_port, spawn->ibv_dev->name);
2491                         devx_port.comp_mask = 0;
2492                 }
2493         }
2494         if (devx_port.comp_mask & MLX5DV_DEVX_PORT_MATCH_REG_C_0) {
2495                 priv->vport_meta_tag = devx_port.reg_c_0.value;
2496                 priv->vport_meta_mask = devx_port.reg_c_0.mask;
2497                 if (!priv->vport_meta_mask) {
2498                         DRV_LOG(ERR, "vport zero mask for port %d"
2499                                      " on bonding device %s",
2500                                      spawn->ibv_port, spawn->ibv_dev->name);
2501                         err = ENOTSUP;
2502                         goto error;
2503                 }
2504                 if (priv->vport_meta_tag & ~priv->vport_meta_mask) {
2505                         DRV_LOG(ERR, "invalid vport tag for port %d"
2506                                      " on bonding device %s",
2507                                      spawn->ibv_port, spawn->ibv_dev->name);
2508                         err = ENOTSUP;
2509                         goto error;
2510                 }
2511         }
2512         if (devx_port.comp_mask & MLX5DV_DEVX_PORT_VPORT) {
2513                 priv->vport_id = devx_port.vport_num;
2514         } else if (spawn->pf_bond >= 0) {
2515                 DRV_LOG(ERR, "can't deduce vport index for port %d"
2516                              " on bonding device %s",
2517                              spawn->ibv_port, spawn->ibv_dev->name);
2518                 err = ENOTSUP;
2519                 goto error;
2520         } else {
2521                 /* Suppose vport index in compatible way. */
2522                 priv->vport_id = switch_info->representor ?
2523                                  switch_info->port_name + 1 : -1;
2524         }
2525 #else
2526         /*
2527          * Kernel/rdma_core support single E-Switch per PF configurations
2528          * only and vport_id field contains the vport index for
2529          * associated VF, which is deduced from representor port name.
2530          * For example, let's have the IB device port 10, it has
2531          * attached network device eth0, which has port name attribute
2532          * pf0vf2, we can deduce the VF number as 2, and set vport index
2533          * as 3 (2+1). This assigning schema should be changed if the
2534          * multiple E-Switch instances per PF configurations or/and PCI
2535          * subfunctions are added.
2536          */
2537         priv->vport_id = switch_info->representor ?
2538                          switch_info->port_name + 1 : -1;
2539 #endif
2540         /* representor_id field keeps the unmodified VF index. */
2541         priv->representor_id = switch_info->representor ?
2542                                switch_info->port_name : -1;
2543         /*
2544          * Look for sibling devices in order to reuse their switch domain
2545          * if any, otherwise allocate one.
2546          */
2547         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2548                 const struct mlx5_priv *opriv =
2549                         rte_eth_devices[port_id].data->dev_private;
2550
2551                 if (!opriv ||
2552                     opriv->sh != priv->sh ||
2553                         opriv->domain_id ==
2554                         RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
2555                         continue;
2556                 priv->domain_id = opriv->domain_id;
2557                 break;
2558         }
2559         if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
2560                 err = rte_eth_switch_domain_alloc(&priv->domain_id);
2561                 if (err) {
2562                         err = rte_errno;
2563                         DRV_LOG(ERR, "unable to allocate switch domain: %s",
2564                                 strerror(rte_errno));
2565                         goto error;
2566                 }
2567                 own_domain_id = 1;
2568         }
2569         /* Override some values set by hardware configuration. */
2570         mlx5_args(&config, dpdk_dev->devargs);
2571         err = mlx5_dev_check_sibling_config(priv, &config);
2572         if (err)
2573                 goto error;
2574         config.hw_csum = !!(sh->device_attr.device_cap_flags_ex &
2575                             IBV_DEVICE_RAW_IP_CSUM);
2576         DRV_LOG(DEBUG, "checksum offloading is %ssupported",
2577                 (config.hw_csum ? "" : "not "));
2578 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \
2579         !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
2580         DRV_LOG(DEBUG, "counters are not supported");
2581 #endif
2582 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR)
2583         if (config.dv_flow_en) {
2584                 DRV_LOG(WARNING, "DV flow is not supported");
2585                 config.dv_flow_en = 0;
2586         }
2587 #endif
2588         config.ind_table_max_size =
2589                 sh->device_attr.rss_caps.max_rwq_indirection_table_size;
2590         /*
2591          * Remove this check once DPDK supports larger/variable
2592          * indirection tables.
2593          */
2594         if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
2595                 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
2596         DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
2597                 config.ind_table_max_size);
2598         config.hw_vlan_strip = !!(sh->device_attr.raw_packet_caps &
2599                                   IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
2600         DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
2601                 (config.hw_vlan_strip ? "" : "not "));
2602         config.hw_fcs_strip = !!(sh->device_attr.raw_packet_caps &
2603                                  IBV_RAW_PACKET_CAP_SCATTER_FCS);
2604         DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
2605                 (config.hw_fcs_strip ? "" : "not "));
2606 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
2607         hw_padding = !!sh->device_attr.rx_pad_end_addr_align;
2608 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
2609         hw_padding = !!(sh->device_attr.device_cap_flags_ex &
2610                         IBV_DEVICE_PCI_WRITE_END_PADDING);
2611 #endif
2612         if (config.hw_padding && !hw_padding) {
2613                 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
2614                 config.hw_padding = 0;
2615         } else if (config.hw_padding) {
2616                 DRV_LOG(DEBUG, "Rx end alignment padding is enabled");
2617         }
2618         config.tso = (sh->device_attr.tso_caps.max_tso > 0 &&
2619                       (sh->device_attr.tso_caps.supported_qpts &
2620                        (1 << IBV_QPT_RAW_PACKET)));
2621         if (config.tso)
2622                 config.tso_max_payload_sz = sh->device_attr.tso_caps.max_tso;
2623         /*
2624          * MPW is disabled by default, while the Enhanced MPW is enabled
2625          * by default.
2626          */
2627         if (config.mps == MLX5_ARG_UNSET)
2628                 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED :
2629                                                           MLX5_MPW_DISABLED;
2630         else
2631                 config.mps = config.mps ? mps : MLX5_MPW_DISABLED;
2632         DRV_LOG(INFO, "%sMPS is %s",
2633                 config.mps == MLX5_MPW_ENHANCED ? "enhanced " :
2634                 config.mps == MLX5_MPW ? "legacy " : "",
2635                 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
2636         if (config.cqe_comp && !cqe_comp) {
2637                 DRV_LOG(WARNING, "Rx CQE compression isn't supported");
2638                 config.cqe_comp = 0;
2639         }
2640         if (config.cqe_pad && !cqe_pad) {
2641                 DRV_LOG(WARNING, "Rx CQE padding isn't supported");
2642                 config.cqe_pad = 0;
2643         } else if (config.cqe_pad) {
2644                 DRV_LOG(INFO, "Rx CQE padding is enabled");
2645         }
2646         if (config.devx) {
2647                 priv->counter_fallback = 0;
2648                 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config.hca_attr);
2649                 if (err) {
2650                         err = -err;
2651                         goto error;
2652                 }
2653                 if (!config.hca_attr.flow_counters_dump)
2654                         priv->counter_fallback = 1;
2655 #ifndef HAVE_IBV_DEVX_ASYNC
2656                 priv->counter_fallback = 1;
2657 #endif
2658                 if (priv->counter_fallback)
2659                         DRV_LOG(INFO, "Use fall-back DV counter management");
2660                 /* Check for LRO support. */
2661                 if (config.dest_tir && config.hca_attr.lro_cap &&
2662                     config.dv_flow_en) {
2663                         /* TBD check tunnel lro caps. */
2664                         config.lro.supported = config.hca_attr.lro_cap;
2665                         DRV_LOG(DEBUG, "Device supports LRO");
2666                         /*
2667                          * If LRO timeout is not configured by application,
2668                          * use the minimal supported value.
2669                          */
2670                         if (!config.lro.timeout)
2671                                 config.lro.timeout =
2672                                 config.hca_attr.lro_timer_supported_periods[0];
2673                         DRV_LOG(DEBUG, "LRO session timeout set to %d usec",
2674                                 config.lro.timeout);
2675                 }
2676 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER)
2677                 if (config.hca_attr.qos.sup && config.hca_attr.qos.srtcm_sup &&
2678                     config.dv_flow_en) {
2679                         uint8_t reg_c_mask =
2680                                 config.hca_attr.qos.flow_meter_reg_c_ids;
2681                         /*
2682                          * Meter needs two REG_C's for color match and pre-sfx
2683                          * flow match. Here get the REG_C for color match.
2684                          * REG_C_0 and REG_C_1 is reserved for metadata feature.
2685                          */
2686                         reg_c_mask &= 0xfc;
2687                         if (__builtin_popcount(reg_c_mask) < 1) {
2688                                 priv->mtr_en = 0;
2689                                 DRV_LOG(WARNING, "No available register for"
2690                                         " meter.");
2691                         } else {
2692                                 priv->mtr_color_reg = ffs(reg_c_mask) - 1 +
2693                                                       REG_C_0;
2694                                 priv->mtr_en = 1;
2695                                 priv->mtr_reg_share =
2696                                       config.hca_attr.qos.flow_meter_reg_share;
2697                                 DRV_LOG(DEBUG, "The REG_C meter uses is %d",
2698                                         priv->mtr_color_reg);
2699                         }
2700                 }
2701 #endif
2702         }
2703         if (config.mprq.enabled && mprq) {
2704                 if (config.mprq.stride_num_n &&
2705                     (config.mprq.stride_num_n > mprq_max_stride_num_n ||
2706                      config.mprq.stride_num_n < mprq_min_stride_num_n)) {
2707                         config.mprq.stride_num_n =
2708                                 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
2709                                                 mprq_min_stride_num_n),
2710                                         mprq_max_stride_num_n);
2711                         DRV_LOG(WARNING,
2712                                 "the number of strides"
2713                                 " for Multi-Packet RQ is out of range,"
2714                                 " setting default value (%u)",
2715                                 1 << config.mprq.stride_num_n);
2716                 }
2717                 if (config.mprq.stride_size_n &&
2718                     (config.mprq.stride_size_n > mprq_max_stride_size_n ||
2719                      config.mprq.stride_size_n < mprq_min_stride_size_n)) {
2720                         config.mprq.stride_size_n =
2721                                 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N,
2722                                                 mprq_min_stride_size_n),
2723                                         mprq_max_stride_size_n);
2724                         DRV_LOG(WARNING,
2725                                 "the size of a stride"
2726                                 " for Multi-Packet RQ is out of range,"
2727                                 " setting default value (%u)",
2728                                 1 << config.mprq.stride_size_n);
2729                 }
2730                 config.mprq.min_stride_size_n = mprq_min_stride_size_n;
2731                 config.mprq.max_stride_size_n = mprq_max_stride_size_n;
2732         } else if (config.mprq.enabled && !mprq) {
2733                 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
2734                 config.mprq.enabled = 0;
2735         }
2736         if (config.max_dump_files_num == 0)
2737                 config.max_dump_files_num = 128;
2738         eth_dev = rte_eth_dev_allocate(name);
2739         if (eth_dev == NULL) {
2740                 DRV_LOG(ERR, "can not allocate rte ethdev");
2741                 err = ENOMEM;
2742                 goto error;
2743         }
2744         /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */
2745         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2746         if (priv->representor) {
2747                 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
2748                 eth_dev->data->representor_id = priv->representor_id;
2749         }
2750         /*
2751          * Store associated network device interface index. This index
2752          * is permanent throughout the lifetime of device. So, we may store
2753          * the ifindex here and use the cached value further.
2754          */
2755         MLX5_ASSERT(spawn->ifindex);
2756         priv->if_index = spawn->ifindex;
2757         eth_dev->data->dev_private = priv;
2758         priv->dev_data = eth_dev->data;
2759         eth_dev->data->mac_addrs = priv->mac;
2760         eth_dev->device = dpdk_dev;
2761         /* Configure the first MAC address by default. */
2762         if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
2763                 DRV_LOG(ERR,
2764                         "port %u cannot get MAC address, is mlx5_en"
2765                         " loaded? (errno: %s)",
2766                         eth_dev->data->port_id, strerror(rte_errno));
2767                 err = ENODEV;
2768                 goto error;
2769         }
2770         DRV_LOG(INFO,
2771                 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
2772                 eth_dev->data->port_id,
2773                 mac.addr_bytes[0], mac.addr_bytes[1],
2774                 mac.addr_bytes[2], mac.addr_bytes[3],
2775                 mac.addr_bytes[4], mac.addr_bytes[5]);
2776 #ifdef RTE_LIBRTE_MLX5_DEBUG
2777         {
2778                 char ifname[IF_NAMESIZE];
2779
2780                 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
2781                         DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
2782                                 eth_dev->data->port_id, ifname);
2783                 else
2784                         DRV_LOG(DEBUG, "port %u ifname is unknown",
2785                                 eth_dev->data->port_id);
2786         }
2787 #endif
2788         /* Get actual MTU if possible. */
2789         err = mlx5_get_mtu(eth_dev, &priv->mtu);
2790         if (err) {
2791                 err = rte_errno;
2792                 goto error;
2793         }
2794         DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
2795                 priv->mtu);
2796         /* Initialize burst functions to prevent crashes before link-up. */
2797         eth_dev->rx_pkt_burst = removed_rx_burst;
2798         eth_dev->tx_pkt_burst = removed_tx_burst;
2799         eth_dev->dev_ops = &mlx5_dev_ops;
2800         /* Register MAC address. */
2801         claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
2802         if (config.vf && config.vf_nl_en)
2803                 mlx5_nl_mac_addr_sync(priv->nl_socket_route,
2804                                       mlx5_ifindex(eth_dev),
2805                                       eth_dev->data->mac_addrs,
2806                                       MLX5_MAX_MAC_ADDRESSES);
2807         TAILQ_INIT(&priv->flows);
2808         TAILQ_INIT(&priv->ctrl_flows);
2809         TAILQ_INIT(&priv->flow_meters);
2810         TAILQ_INIT(&priv->flow_meter_profiles);
2811         /* Hint libmlx5 to use PMD allocator for data plane resources */
2812         struct mlx5dv_ctx_allocators alctr = {
2813                 .alloc = &mlx5_alloc_verbs_buf,
2814                 .free = &mlx5_free_verbs_buf,
2815                 .data = priv,
2816         };
2817         mlx5_glue->dv_set_context_attr(sh->ctx,
2818                                        MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
2819                                        (void *)((uintptr_t)&alctr));
2820         /* Bring Ethernet device up. */
2821         DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
2822                 eth_dev->data->port_id);
2823         mlx5_set_link_up(eth_dev);
2824         /*
2825          * Even though the interrupt handler is not installed yet,
2826          * interrupts will still trigger on the async_fd from
2827          * Verbs context returned by ibv_open_device().
2828          */
2829         mlx5_link_update(eth_dev, 0);
2830 #ifdef HAVE_MLX5DV_DR_ESWITCH
2831         if (!(config.hca_attr.eswitch_manager && config.dv_flow_en &&
2832               (switch_info->representor || switch_info->master)))
2833                 config.dv_esw_en = 0;
2834 #else
2835         config.dv_esw_en = 0;
2836 #endif
2837         /* Detect minimal data bytes to inline. */
2838         mlx5_set_min_inline(spawn, &config);
2839         /* Store device configuration on private structure. */
2840         priv->config = config;
2841         /* Create context for virtual machine VLAN workaround. */
2842         priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex);
2843         if (config.dv_flow_en) {
2844                 err = mlx5_alloc_shared_dr(priv);
2845                 if (err)
2846                         goto error;
2847                 /*
2848                  * RSS id is shared with meter flow id. Meter flow id can only
2849                  * use the 24 MSB of the register.
2850                  */
2851                 priv->qrss_id_pool = mlx5_flow_id_pool_alloc(UINT32_MAX >>
2852                                      MLX5_MTR_COLOR_BITS);
2853                 if (!priv->qrss_id_pool) {
2854                         DRV_LOG(ERR, "can't create flow id pool");
2855                         err = ENOMEM;
2856                         goto error;
2857                 }
2858         }
2859         /* Supported Verbs flow priority number detection. */
2860         err = mlx5_flow_discover_priorities(eth_dev);
2861         if (err < 0) {
2862                 err = -err;
2863                 goto error;
2864         }
2865         priv->config.flow_prio = err;
2866         if (!priv->config.dv_esw_en &&
2867             priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2868                 DRV_LOG(WARNING, "metadata mode %u is not supported "
2869                                  "(no E-Switch)", priv->config.dv_xmeta_en);
2870                 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY;
2871         }
2872         mlx5_set_metadata_mask(eth_dev);
2873         if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
2874             !priv->sh->dv_regc0_mask) {
2875                 DRV_LOG(ERR, "metadata mode %u is not supported "
2876                              "(no metadata reg_c[0] is available)",
2877                              priv->config.dv_xmeta_en);
2878                         err = ENOTSUP;
2879                         goto error;
2880         }
2881         /*
2882          * Allocate the buffer for flow creating, just once.
2883          * The allocation must be done before any flow creating.
2884          */
2885         mlx5_flow_alloc_intermediate(eth_dev);
2886         /* Query availibility of metadata reg_c's. */
2887         err = mlx5_flow_discover_mreg_c(eth_dev);
2888         if (err < 0) {
2889                 err = -err;
2890                 goto error;
2891         }
2892         if (!mlx5_flow_ext_mreg_supported(eth_dev)) {
2893                 DRV_LOG(DEBUG,
2894                         "port %u extensive metadata register is not supported",
2895                         eth_dev->data->port_id);
2896                 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2897                         DRV_LOG(ERR, "metadata mode %u is not supported "
2898                                      "(no metadata registers available)",
2899                                      priv->config.dv_xmeta_en);
2900                         err = ENOTSUP;
2901                         goto error;
2902                 }
2903         }
2904         if (priv->config.dv_flow_en &&
2905             priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
2906             mlx5_flow_ext_mreg_supported(eth_dev) &&
2907             priv->sh->dv_regc0_mask) {
2908                 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME,
2909                                                       MLX5_FLOW_MREG_HTABLE_SZ);
2910                 if (!priv->mreg_cp_tbl) {
2911                         err = ENOMEM;
2912                         goto error;
2913                 }
2914         }
2915         return eth_dev;
2916 error:
2917         if (priv) {
2918                 if (priv->mreg_cp_tbl)
2919                         mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
2920                 if (priv->sh)
2921                         mlx5_free_shared_dr(priv);
2922                 if (priv->nl_socket_route >= 0)
2923                         close(priv->nl_socket_route);
2924                 if (priv->nl_socket_rdma >= 0)
2925                         close(priv->nl_socket_rdma);
2926                 if (priv->vmwa_context)
2927                         mlx5_vlan_vmwa_exit(priv->vmwa_context);
2928                 if (priv->qrss_id_pool)
2929                         mlx5_flow_id_pool_release(priv->qrss_id_pool);
2930                 if (own_domain_id)
2931                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
2932                 rte_free(priv);
2933                 if (eth_dev != NULL)
2934                         eth_dev->data->dev_private = NULL;
2935         }
2936         if (eth_dev != NULL) {
2937                 /* mac_addrs must not be freed alone because part of dev_private */
2938                 eth_dev->data->mac_addrs = NULL;
2939                 rte_eth_dev_release_port(eth_dev);
2940         }
2941         if (sh)
2942                 mlx5_free_shared_ibctx(sh);
2943         MLX5_ASSERT(err > 0);
2944         rte_errno = err;
2945         return NULL;
2946 }
2947
2948 /**
2949  * Comparison callback to sort device data.
2950  *
2951  * This is meant to be used with qsort().
2952  *
2953  * @param a[in]
2954  *   Pointer to pointer to first data object.
2955  * @param b[in]
2956  *   Pointer to pointer to second data object.
2957  *
2958  * @return
2959  *   0 if both objects are equal, less than 0 if the first argument is less
2960  *   than the second, greater than 0 otherwise.
2961  */
2962 static int
2963 mlx5_dev_spawn_data_cmp(const void *a, const void *b)
2964 {
2965         const struct mlx5_switch_info *si_a =
2966                 &((const struct mlx5_dev_spawn_data *)a)->info;
2967         const struct mlx5_switch_info *si_b =
2968                 &((const struct mlx5_dev_spawn_data *)b)->info;
2969         int ret;
2970
2971         /* Master device first. */
2972         ret = si_b->master - si_a->master;
2973         if (ret)
2974                 return ret;
2975         /* Then representor devices. */
2976         ret = si_b->representor - si_a->representor;
2977         if (ret)
2978                 return ret;
2979         /* Unidentified devices come last in no specific order. */
2980         if (!si_a->representor)
2981                 return 0;
2982         /* Order representors by name. */
2983         return si_a->port_name - si_b->port_name;
2984 }
2985
2986 /**
2987  * Match PCI information for possible slaves of bonding device.
2988  *
2989  * @param[in] ibv_dev
2990  *   Pointer to Infiniband device structure.
2991  * @param[in] pci_dev
2992  *   Pointer to PCI device structure to match PCI address.
2993  * @param[in] nl_rdma
2994  *   Netlink RDMA group socket handle.
2995  *
2996  * @return
2997  *   negative value if no bonding device found, otherwise
2998  *   positive index of slave PF in bonding.
2999  */
3000 static int
3001 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev,
3002                            const struct rte_pci_device *pci_dev,
3003                            int nl_rdma)
3004 {
3005         char ifname[IF_NAMESIZE + 1];
3006         unsigned int ifindex;
3007         unsigned int np, i;
3008         FILE *file = NULL;
3009         int pf = -1;
3010
3011         /*
3012          * Try to get master device name. If something goes
3013          * wrong suppose the lack of kernel support and no
3014          * bonding devices.
3015          */
3016         if (nl_rdma < 0)
3017                 return -1;
3018         if (!strstr(ibv_dev->name, "bond"))
3019                 return -1;
3020         np = mlx5_nl_portnum(nl_rdma, ibv_dev->name);
3021         if (!np)
3022                 return -1;
3023         /*
3024          * The Master device might not be on the predefined
3025          * port (not on port index 1, it is not garanted),
3026          * we have to scan all Infiniband device port and
3027          * find master.
3028          */
3029         for (i = 1; i <= np; ++i) {
3030                 /* Check whether Infiniband port is populated. */
3031                 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i);
3032                 if (!ifindex)
3033                         continue;
3034                 if (!if_indextoname(ifindex, ifname))
3035                         continue;
3036                 /* Try to read bonding slave names from sysfs. */
3037                 MKSTR(slaves,
3038                       "/sys/class/net/%s/master/bonding/slaves", ifname);
3039                 file = fopen(slaves, "r");
3040                 if (file)
3041                         break;
3042         }
3043         if (!file)
3044                 return -1;
3045         /* Use safe format to check maximal buffer length. */
3046         MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE);
3047         while (fscanf(file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) {
3048                 char tmp_str[IF_NAMESIZE + 32];
3049                 struct rte_pci_addr pci_addr;
3050                 struct mlx5_switch_info info;
3051
3052                 /* Process slave interface names in the loop. */
3053                 snprintf(tmp_str, sizeof(tmp_str),
3054                          "/sys/class/net/%s", ifname);
3055                 if (mlx5_dev_to_pci_addr(tmp_str, &pci_addr)) {
3056                         DRV_LOG(WARNING, "can not get PCI address"
3057                                          " for netdev \"%s\"", ifname);
3058                         continue;
3059                 }
3060                 if (pci_dev->addr.domain != pci_addr.domain ||
3061                     pci_dev->addr.bus != pci_addr.bus ||
3062                     pci_dev->addr.devid != pci_addr.devid ||
3063                     pci_dev->addr.function != pci_addr.function)
3064                         continue;
3065                 /* Slave interface PCI address match found. */
3066                 fclose(file);
3067                 snprintf(tmp_str, sizeof(tmp_str),
3068                          "/sys/class/net/%s/phys_port_name", ifname);
3069                 file = fopen(tmp_str, "rb");
3070                 if (!file)
3071                         break;
3072                 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET;
3073                 if (fscanf(file, "%32s", tmp_str) == 1)
3074                         mlx5_translate_port_name(tmp_str, &info);
3075                 if (info.name_type == MLX5_PHYS_PORT_NAME_TYPE_LEGACY ||
3076                     info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK)
3077                         pf = info.port_name;
3078                 break;
3079         }
3080         if (file)
3081                 fclose(file);
3082         return pf;
3083 }
3084
3085 /**
3086  * DPDK callback to register a PCI device.
3087  *
3088  * This function spawns Ethernet devices out of a given PCI device.
3089  *
3090  * @param[in] pci_drv
3091  *   PCI driver structure (mlx5_driver).
3092  * @param[in] pci_dev
3093  *   PCI device information.
3094  *
3095  * @return
3096  *   0 on success, a negative errno value otherwise and rte_errno is set.
3097  */
3098 static int
3099 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3100                struct rte_pci_device *pci_dev)
3101 {
3102         struct ibv_device **ibv_list;
3103         /*
3104          * Number of found IB Devices matching with requested PCI BDF.
3105          * nd != 1 means there are multiple IB devices over the same
3106          * PCI device and we have representors and master.
3107          */
3108         unsigned int nd = 0;
3109         /*
3110          * Number of found IB device Ports. nd = 1 and np = 1..n means
3111          * we have the single multiport IB device, and there may be
3112          * representors attached to some of found ports.
3113          */
3114         unsigned int np = 0;
3115         /*
3116          * Number of DPDK ethernet devices to Spawn - either over
3117          * multiple IB devices or multiple ports of single IB device.
3118          * Actually this is the number of iterations to spawn.
3119          */
3120         unsigned int ns = 0;
3121         /*
3122          * Bonding device
3123          *   < 0 - no bonding device (single one)
3124          *  >= 0 - bonding device (value is slave PF index)
3125          */
3126         int bd = -1;
3127         struct mlx5_dev_spawn_data *list = NULL;
3128         struct mlx5_dev_config dev_config;
3129         int ret;
3130
3131         if (mlx5_class_get(pci_dev->device.devargs) != MLX5_CLASS_NET) {
3132                 DRV_LOG(DEBUG, "Skip probing - should be probed by other mlx5"
3133                         " driver.");
3134                 return 1;
3135         }
3136         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
3137                 mlx5_pmd_socket_init();
3138         ret = mlx5_init_once();
3139         if (ret) {
3140                 DRV_LOG(ERR, "unable to init PMD global data: %s",
3141                         strerror(rte_errno));
3142                 return -rte_errno;
3143         }
3144         MLX5_ASSERT(pci_drv == &mlx5_driver);
3145         errno = 0;
3146         ibv_list = mlx5_glue->get_device_list(&ret);
3147         if (!ibv_list) {
3148                 rte_errno = errno ? errno : ENOSYS;
3149                 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?");
3150                 return -rte_errno;
3151         }
3152         /*
3153          * First scan the list of all Infiniband devices to find
3154          * matching ones, gathering into the list.
3155          */
3156         struct ibv_device *ibv_match[ret + 1];
3157         int nl_route = mlx5_nl_init(NETLINK_ROUTE);
3158         int nl_rdma = mlx5_nl_init(NETLINK_RDMA);
3159         unsigned int i;
3160
3161         while (ret-- > 0) {
3162                 struct rte_pci_addr pci_addr;
3163
3164                 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name);
3165                 bd = mlx5_device_bond_pci_match
3166                                 (ibv_list[ret], pci_dev, nl_rdma);
3167                 if (bd >= 0) {
3168                         /*
3169                          * Bonding device detected. Only one match is allowed,
3170                          * the bonding is supported over multi-port IB device,
3171                          * there should be no matches on representor PCI
3172                          * functions or non VF LAG bonding devices with
3173                          * specified address.
3174                          */
3175                         if (nd) {
3176                                 DRV_LOG(ERR,
3177                                         "multiple PCI match on bonding device"
3178                                         "\"%s\" found", ibv_list[ret]->name);
3179                                 rte_errno = ENOENT;
3180                                 ret = -rte_errno;
3181                                 goto exit;
3182                         }
3183                         DRV_LOG(INFO, "PCI information matches for"
3184                                       " slave %d bonding device \"%s\"",
3185                                       bd, ibv_list[ret]->name);
3186                         ibv_match[nd++] = ibv_list[ret];
3187                         break;
3188                 }
3189                 if (mlx5_dev_to_pci_addr
3190                         (ibv_list[ret]->ibdev_path, &pci_addr))
3191                         continue;
3192                 if (pci_dev->addr.domain != pci_addr.domain ||
3193                     pci_dev->addr.bus != pci_addr.bus ||
3194                     pci_dev->addr.devid != pci_addr.devid ||
3195                     pci_dev->addr.function != pci_addr.function)
3196                         continue;
3197                 DRV_LOG(INFO, "PCI information matches for device \"%s\"",
3198                         ibv_list[ret]->name);
3199                 ibv_match[nd++] = ibv_list[ret];
3200         }
3201         ibv_match[nd] = NULL;
3202         if (!nd) {
3203                 /* No device matches, just complain and bail out. */
3204                 DRV_LOG(WARNING,
3205                         "no Verbs device matches PCI device " PCI_PRI_FMT ","
3206                         " are kernel drivers loaded?",
3207                         pci_dev->addr.domain, pci_dev->addr.bus,
3208                         pci_dev->addr.devid, pci_dev->addr.function);
3209                 rte_errno = ENOENT;
3210                 ret = -rte_errno;
3211                 goto exit;
3212         }
3213         if (nd == 1) {
3214                 /*
3215                  * Found single matching device may have multiple ports.
3216                  * Each port may be representor, we have to check the port
3217                  * number and check the representors existence.
3218                  */
3219                 if (nl_rdma >= 0)
3220                         np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name);
3221                 if (!np)
3222                         DRV_LOG(WARNING, "can not get IB device \"%s\""
3223                                          " ports number", ibv_match[0]->name);
3224                 if (bd >= 0 && !np) {
3225                         DRV_LOG(ERR, "can not get ports"
3226                                      " for bonding device");
3227                         rte_errno = ENOENT;
3228                         ret = -rte_errno;
3229                         goto exit;
3230                 }
3231         }
3232 #ifndef HAVE_MLX5DV_DR_DEVX_PORT
3233         if (bd >= 0) {
3234                 /*
3235                  * This may happen if there is VF LAG kernel support and
3236                  * application is compiled with older rdma_core library.
3237                  */
3238                 DRV_LOG(ERR,
3239                         "No kernel/verbs support for VF LAG bonding found.");
3240                 rte_errno = ENOTSUP;
3241                 ret = -rte_errno;
3242                 goto exit;
3243         }
3244 #endif
3245         /*
3246          * Now we can determine the maximal
3247          * amount of devices to be spawned.
3248          */
3249         list = rte_zmalloc("device spawn data",
3250                          sizeof(struct mlx5_dev_spawn_data) *
3251                          (np ? np : nd),
3252                          RTE_CACHE_LINE_SIZE);
3253         if (!list) {
3254                 DRV_LOG(ERR, "spawn data array allocation failure");
3255                 rte_errno = ENOMEM;
3256                 ret = -rte_errno;
3257                 goto exit;
3258         }
3259         if (bd >= 0 || np > 1) {
3260                 /*
3261                  * Single IB device with multiple ports found,
3262                  * it may be E-Switch master device and representors.
3263                  * We have to perform identification trough the ports.
3264                  */
3265                 MLX5_ASSERT(nl_rdma >= 0);
3266                 MLX5_ASSERT(ns == 0);
3267                 MLX5_ASSERT(nd == 1);
3268                 MLX5_ASSERT(np);
3269                 for (i = 1; i <= np; ++i) {
3270                         list[ns].max_port = np;
3271                         list[ns].ibv_port = i;
3272                         list[ns].ibv_dev = ibv_match[0];
3273                         list[ns].eth_dev = NULL;
3274                         list[ns].pci_dev = pci_dev;
3275                         list[ns].pf_bond = bd;
3276                         list[ns].ifindex = mlx5_nl_ifindex
3277                                         (nl_rdma, list[ns].ibv_dev->name, i);
3278                         if (!list[ns].ifindex) {
3279                                 /*
3280                                  * No network interface index found for the
3281                                  * specified port, it means there is no
3282                                  * representor on this port. It's OK,
3283                                  * there can be disabled ports, for example
3284                                  * if sriov_numvfs < sriov_totalvfs.
3285                                  */
3286                                 continue;
3287                         }
3288                         ret = -1;
3289                         if (nl_route >= 0)
3290                                 ret = mlx5_nl_switch_info
3291                                                (nl_route,
3292                                                 list[ns].ifindex,
3293                                                 &list[ns].info);
3294                         if (ret || (!list[ns].info.representor &&
3295                                     !list[ns].info.master)) {
3296                                 /*
3297                                  * We failed to recognize representors with
3298                                  * Netlink, let's try to perform the task
3299                                  * with sysfs.
3300                                  */
3301                                 ret =  mlx5_sysfs_switch_info
3302                                                 (list[ns].ifindex,
3303                                                  &list[ns].info);
3304                         }
3305                         if (!ret && bd >= 0) {
3306                                 switch (list[ns].info.name_type) {
3307                                 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK:
3308                                         if (list[ns].info.port_name == bd)
3309                                                 ns++;
3310                                         break;
3311                                 case MLX5_PHYS_PORT_NAME_TYPE_PFVF:
3312                                         if (list[ns].info.pf_num == bd)
3313                                                 ns++;
3314                                         break;
3315                                 default:
3316                                         break;
3317                                 }
3318                                 continue;
3319                         }
3320                         if (!ret && (list[ns].info.representor ^
3321                                      list[ns].info.master))
3322                                 ns++;
3323                 }
3324                 if (!ns) {
3325                         DRV_LOG(ERR,
3326                                 "unable to recognize master/representors"
3327                                 " on the IB device with multiple ports");
3328                         rte_errno = ENOENT;
3329                         ret = -rte_errno;
3330                         goto exit;
3331                 }
3332         } else {
3333                 /*
3334                  * The existence of several matching entries (nd > 1) means
3335                  * port representors have been instantiated. No existing Verbs
3336                  * call nor sysfs entries can tell them apart, this can only
3337                  * be done through Netlink calls assuming kernel drivers are
3338                  * recent enough to support them.
3339                  *
3340                  * In the event of identification failure through Netlink,
3341                  * try again through sysfs, then:
3342                  *
3343                  * 1. A single IB device matches (nd == 1) with single
3344                  *    port (np=0/1) and is not a representor, assume
3345                  *    no switch support.
3346                  *
3347                  * 2. Otherwise no safe assumptions can be made;
3348                  *    complain louder and bail out.
3349                  */
3350                 np = 1;
3351                 for (i = 0; i != nd; ++i) {
3352                         memset(&list[ns].info, 0, sizeof(list[ns].info));
3353                         list[ns].max_port = 1;
3354                         list[ns].ibv_port = 1;
3355                         list[ns].ibv_dev = ibv_match[i];
3356                         list[ns].eth_dev = NULL;
3357                         list[ns].pci_dev = pci_dev;
3358                         list[ns].pf_bond = -1;
3359                         list[ns].ifindex = 0;
3360                         if (nl_rdma >= 0)
3361                                 list[ns].ifindex = mlx5_nl_ifindex
3362                                         (nl_rdma, list[ns].ibv_dev->name, 1);
3363                         if (!list[ns].ifindex) {
3364                                 char ifname[IF_NAMESIZE];
3365
3366                                 /*
3367                                  * Netlink failed, it may happen with old
3368                                  * ib_core kernel driver (before 4.16).
3369                                  * We can assume there is old driver because
3370                                  * here we are processing single ports IB
3371                                  * devices. Let's try sysfs to retrieve
3372                                  * the ifindex. The method works for
3373                                  * master device only.
3374                                  */
3375                                 if (nd > 1) {
3376                                         /*
3377                                          * Multiple devices found, assume
3378                                          * representors, can not distinguish
3379                                          * master/representor and retrieve
3380                                          * ifindex via sysfs.
3381                                          */
3382                                         continue;
3383                                 }
3384                                 ret = mlx5_get_master_ifname
3385                                         (ibv_match[i]->ibdev_path, &ifname);
3386                                 if (!ret)
3387                                         list[ns].ifindex =
3388                                                 if_nametoindex(ifname);
3389                                 if (!list[ns].ifindex) {
3390                                         /*
3391                                          * No network interface index found
3392                                          * for the specified device, it means
3393                                          * there it is neither representor
3394                                          * nor master.
3395                                          */
3396                                         continue;
3397                                 }
3398                         }
3399                         ret = -1;
3400                         if (nl_route >= 0)
3401                                 ret = mlx5_nl_switch_info
3402                                                (nl_route,
3403                                                 list[ns].ifindex,
3404                                                 &list[ns].info);
3405                         if (ret || (!list[ns].info.representor &&
3406                                     !list[ns].info.master)) {
3407                                 /*
3408                                  * We failed to recognize representors with
3409                                  * Netlink, let's try to perform the task
3410                                  * with sysfs.
3411                                  */
3412                                 ret =  mlx5_sysfs_switch_info
3413                                                 (list[ns].ifindex,
3414                                                  &list[ns].info);
3415                         }
3416                         if (!ret && (list[ns].info.representor ^
3417                                      list[ns].info.master)) {
3418                                 ns++;
3419                         } else if ((nd == 1) &&
3420                                    !list[ns].info.representor &&
3421                                    !list[ns].info.master) {
3422                                 /*
3423                                  * Single IB device with
3424                                  * one physical port and
3425                                  * attached network device.
3426                                  * May be SRIOV is not enabled
3427                                  * or there is no representors.
3428                                  */
3429                                 DRV_LOG(INFO, "no E-Switch support detected");
3430                                 ns++;
3431                                 break;
3432                         }
3433                 }
3434                 if (!ns) {
3435                         DRV_LOG(ERR,
3436                                 "unable to recognize master/representors"
3437                                 " on the multiple IB devices");
3438                         rte_errno = ENOENT;
3439                         ret = -rte_errno;
3440                         goto exit;
3441                 }
3442         }
3443         MLX5_ASSERT(ns);
3444         /*
3445          * Sort list to probe devices in natural order for users convenience
3446          * (i.e. master first, then representors from lowest to highest ID).
3447          */
3448         qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp);
3449         /* Default configuration. */
3450         dev_config = (struct mlx5_dev_config){
3451                 .hw_padding = 0,
3452                 .mps = MLX5_ARG_UNSET,
3453                 .dbnc = MLX5_ARG_UNSET,
3454                 .rx_vec_en = 1,
3455                 .txq_inline_max = MLX5_ARG_UNSET,
3456                 .txq_inline_min = MLX5_ARG_UNSET,
3457                 .txq_inline_mpw = MLX5_ARG_UNSET,
3458                 .txqs_inline = MLX5_ARG_UNSET,
3459                 .vf_nl_en = 1,
3460                 .mr_ext_memseg_en = 1,
3461                 .mprq = {
3462                         .enabled = 0, /* Disabled by default. */
3463                         .stride_num_n = 0,
3464                         .stride_size_n = 0,
3465                         .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
3466                         .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
3467                 },
3468                 .dv_esw_en = 1,
3469                 .dv_flow_en = 1,
3470                 .log_hp_size = MLX5_ARG_UNSET,
3471         };
3472         /* Device specific configuration. */
3473         switch (pci_dev->id.device_id) {
3474         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
3475         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
3476         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
3477         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
3478         case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF:
3479         case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF:
3480         case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF:
3481                 dev_config.vf = 1;
3482                 break;
3483         default:
3484                 break;
3485         }
3486         for (i = 0; i != ns; ++i) {
3487                 uint32_t restore;
3488
3489                 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device,
3490                                                  &list[i],
3491                                                  dev_config);
3492                 if (!list[i].eth_dev) {
3493                         if (rte_errno != EBUSY && rte_errno != EEXIST)
3494                                 break;
3495                         /* Device is disabled or already spawned. Ignore it. */
3496                         continue;
3497                 }
3498                 restore = list[i].eth_dev->data->dev_flags;
3499                 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev);
3500                 /* Restore non-PCI flags cleared by the above call. */
3501                 list[i].eth_dev->data->dev_flags |= restore;
3502                 mlx5_dev_interrupt_handler_devx_install(list[i].eth_dev);
3503                 rte_eth_dev_probing_finish(list[i].eth_dev);
3504         }
3505         if (i != ns) {
3506                 DRV_LOG(ERR,
3507                         "probe of PCI device " PCI_PRI_FMT " aborted after"
3508                         " encountering an error: %s",
3509                         pci_dev->addr.domain, pci_dev->addr.bus,
3510                         pci_dev->addr.devid, pci_dev->addr.function,
3511                         strerror(rte_errno));
3512                 ret = -rte_errno;
3513                 /* Roll back. */
3514                 while (i--) {
3515                         if (!list[i].eth_dev)
3516                                 continue;
3517                         mlx5_dev_close(list[i].eth_dev);
3518                         /* mac_addrs must not be freed because in dev_private */
3519                         list[i].eth_dev->data->mac_addrs = NULL;
3520                         claim_zero(rte_eth_dev_release_port(list[i].eth_dev));
3521                 }
3522                 /* Restore original error. */
3523                 rte_errno = -ret;
3524         } else {
3525                 ret = 0;
3526         }
3527 exit:
3528         /*
3529          * Do the routine cleanup:
3530          * - close opened Netlink sockets
3531          * - free allocated spawn data array
3532          * - free the Infiniband device list
3533          */
3534         if (nl_rdma >= 0)
3535                 close(nl_rdma);
3536         if (nl_route >= 0)
3537                 close(nl_route);
3538         if (list)
3539                 rte_free(list);
3540         MLX5_ASSERT(ibv_list);
3541         mlx5_glue->free_device_list(ibv_list);
3542         return ret;
3543 }
3544
3545 /**
3546  * Look for the ethernet device belonging to mlx5 driver.
3547  *
3548  * @param[in] port_id
3549  *   port_id to start looking for device.
3550  * @param[in] pci_dev
3551  *   Pointer to the hint PCI device. When device is being probed
3552  *   the its siblings (master and preceding representors might
3553  *   not have assigned driver yet (because the mlx5_pci_probe()
3554  *   is not completed yet, for this case match on hint PCI
3555  *   device may be used to detect sibling device.
3556  *
3557  * @return
3558  *   port_id of found device, RTE_MAX_ETHPORT if not found.
3559  */
3560 uint16_t
3561 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
3562 {
3563         while (port_id < RTE_MAX_ETHPORTS) {
3564                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
3565
3566                 if (dev->state != RTE_ETH_DEV_UNUSED &&
3567                     dev->device &&
3568                     (dev->device == &pci_dev->device ||
3569                      (dev->device->driver &&
3570                      dev->device->driver->name &&
3571                      !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
3572                         break;
3573                 port_id++;
3574         }
3575         if (port_id >= RTE_MAX_ETHPORTS)
3576                 return RTE_MAX_ETHPORTS;
3577         return port_id;
3578 }
3579
3580 /**
3581  * DPDK callback to remove a PCI device.
3582  *
3583  * This function removes all Ethernet devices belong to a given PCI device.
3584  *
3585  * @param[in] pci_dev
3586  *   Pointer to the PCI device.
3587  *
3588  * @return
3589  *   0 on success, the function cannot fail.
3590  */
3591 static int
3592 mlx5_pci_remove(struct rte_pci_device *pci_dev)
3593 {
3594         uint16_t port_id;
3595
3596         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device)
3597                 rte_eth_dev_close(port_id);
3598         return 0;
3599 }
3600
3601 static const struct rte_pci_id mlx5_pci_id_map[] = {
3602         {
3603                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3604                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
3605         },
3606         {
3607                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3608                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
3609         },
3610         {
3611                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3612                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
3613         },
3614         {
3615                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3616                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
3617         },
3618         {
3619                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3620                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
3621         },
3622         {
3623                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3624                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
3625         },
3626         {
3627                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3628                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
3629         },
3630         {
3631                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3632                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
3633         },
3634         {
3635                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3636                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
3637         },
3638         {
3639                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3640                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
3641         },
3642         {
3643                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3644                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
3645         },
3646         {
3647                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3648                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
3649         },
3650         {
3651                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3652                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
3653         },
3654         {
3655                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3656                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
3657         },
3658         {
3659                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3660                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
3661         },
3662         {
3663                 .vendor_id = 0
3664         }
3665 };
3666
3667 static struct rte_pci_driver mlx5_driver = {
3668         .driver = {
3669                 .name = MLX5_DRIVER_NAME
3670         },
3671         .id_table = mlx5_pci_id_map,
3672         .probe = mlx5_pci_probe,
3673         .remove = mlx5_pci_remove,
3674         .dma_map = mlx5_dma_map,
3675         .dma_unmap = mlx5_dma_unmap,
3676         .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV |
3677                      RTE_PCI_DRV_PROBE_AGAIN,
3678 };
3679
3680 /**
3681  * Driver initialization routine.
3682  */
3683 RTE_INIT(rte_mlx5_pmd_init)
3684 {
3685         /* Initialize driver log type. */
3686         mlx5_logtype = rte_log_register("pmd.net.mlx5");
3687         if (mlx5_logtype >= 0)
3688                 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
3689
3690         /* Build the static tables for Verbs conversion. */
3691         mlx5_set_ptype_table();
3692         mlx5_set_cksum_table();
3693         mlx5_set_swp_types_table();
3694         if (mlx5_glue)
3695                 rte_pci_register(&mlx5_driver);
3696 }
3697
3698 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
3699 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
3700 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");