drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12 #include <net/if.h>
  13 #include <fcntl.h>
  14 #include <sys/mman.h>
  15 #include <linux/rtnetlink.h>
  16
  17 /* Verbs header. */
  18 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  19 #ifdef PEDANTIC
  20 #pragma GCC diagnostic ignored "-Wpedantic"
  21 #endif
  22 #include <infiniband/verbs.h>
  23 #ifdef PEDANTIC
  24 #pragma GCC diagnostic error "-Wpedantic"
  25 #endif
  26
  27 #include <rte_malloc.h>
  28 #include <rte_ethdev_driver.h>
  29 #include <rte_ethdev_pci.h>
  30 #include <rte_pci.h>
  31 #include <rte_bus_pci.h>
  32 #include <rte_common.h>
  33 #include <rte_kvargs.h>
  34 #include <rte_rwlock.h>
  35 #include <rte_spinlock.h>
  36 #include <rte_string_fns.h>
  37 #include <rte_alarm.h>
  38
  39 #include <mlx5_glue.h>
  40 #include <mlx5_devx_cmds.h>
  41 #include <mlx5_common.h>
  42 #include <mlx5_common_mp.h>
  43
  44 #include "mlx5_defs.h"
  45 #include "mlx5.h"
  46 #include "mlx5_utils.h"
  47 #include "mlx5_rxtx.h"
  48 #include "mlx5_autoconf.h"
  49 #include "mlx5_mr.h"
  50 #include "mlx5_flow.h"
  51 #include "rte_pmd_mlx5.h"
  52
  53 /* Device parameter to enable RX completion queue compression. */
  54 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  55
  56 /* Device parameter to enable RX completion entry padding to 128B. */
  57 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
  58
  59 /* Device parameter to enable padding Rx packet to cacheline size. */
  60 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  61
  62 /* Device parameter to enable Multi-Packet Rx queue. */
  63 #define MLX5_RX_MPRQ_EN "mprq_en"
  64
  65 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  66 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  67
  68 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  69 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  70
  71 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  72 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  73
  74 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  75 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  76
  77 /* Device parameter to configure inline send. Deprecated, ignored.*/
  78 #define MLX5_TXQ_INLINE "txq_inline"
  79
  80 /* Device parameter to limit packet size to inline with ordinary SEND. */
  81 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  82
  83 /* Device parameter to configure minimal data size to inline. */
  84 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  85
  86 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  87 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  88
  89 /*
  90  * Device parameter to configure the number of TX queues threshold for
  91  * enabling inline send.
  92  */
  93 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  94
  95 /*
  96  * Device parameter to configure the number of TX queues threshold for
  97  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  98  */
  99 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
 100
 101 /* Device parameter to enable multi-packet send WQEs. */
 102 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
 103
 104 /*
 105  * Device parameter to force doorbell register mapping
 106  * to non-cahed region eliminating the extra write memory barrier.
 107  */
 108 #define MLX5_TX_DB_NC "tx_db_nc"
 109
 110 /*
 111  * Device parameter to include 2 dsegs in the title WQEBB.
 112  * Deprecated, ignored.
 113  */
 114 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 115
 116 /*
 117  * Device parameter to limit the size of inlining packet.
 118  * Deprecated, ignored.
 119  */
 120 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 121
 122 /*
 123  * Device parameter to enable hardware Tx vector.
 124  * Deprecated, ignored (no vectorized Tx routines anymore).
 125  */
 126 #define MLX5_TX_VEC_EN "tx_vec_en"
 127
 128 /* Device parameter to enable hardware Rx vector. */
 129 #define MLX5_RX_VEC_EN "rx_vec_en"
 130
 131 /* Allow L3 VXLAN flow creation. */
 132 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 133
 134 /* Activate DV E-Switch flow steering. */
 135 #define MLX5_DV_ESW_EN "dv_esw_en"
 136
 137 /* Activate DV flow steering. */
 138 #define MLX5_DV_FLOW_EN "dv_flow_en"
 139
 140 /* Enable extensive flow metadata support. */
 141 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 142
 143 /* Activate Netlink support in VF mode. */
 144 #define MLX5_VF_NL_EN "vf_nl_en"
 145
 146 /* Enable extending memsegs when creating a MR. */
 147 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 148
 149 /* Select port representors to instantiate. */
 150 #define MLX5_REPRESENTOR "representor"
 151
 152 /* Device parameter to configure the maximum number of dump files per queue. */
 153 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 154
 155 /* Configure timeout of LRO session (in microseconds). */
 156 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 157
 158 /*
 159  * Device parameter to configure the total data buffer size for a single
 160  * hairpin queue (logarithm value).
 161  */
 162 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 163
 164 /* Flow memory reclaim mode. */
 165 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 166
 167 #ifndef HAVE_IBV_MLX5_MOD_MPW
 168 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
 169 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
 170 #endif
 171
 172 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
 173 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
 174 #endif
 175
 176 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
 177
 178 /* Shared memory between primary and secondary processes. */
 179 struct mlx5_shared_data *mlx5_shared_data;
 180
 181 /* Spinlock for mlx5_shared_data allocation. */
 182 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
 183
 184 /* Process local data for secondary processes. */
 185 static struct mlx5_local_data mlx5_local_data;
 186
 187 /** Driver-specific log messages type. */
 188 int mlx5_logtype;
 189
 190 /** Data associated with devices to spawn. */
 191 struct mlx5_dev_spawn_data {
 192         uint32_t ifindex; /**< Network interface index. */
 193         uint32_t max_port; /**< IB device maximal port index. */
 194         uint32_t ibv_port; /**< IB device physical port index. */
 195         int pf_bond; /**< bonding device PF index. < 0 - no bonding */
 196         struct mlx5_switch_info info; /**< Switch information. */
 197         struct ibv_device *ibv_dev; /**< Associated IB device. */
 198         struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
 199         struct rte_pci_device *pci_dev; /**< Backend PCI device. */
 200 };
 201
 202 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_ibv_list = LIST_HEAD_INITIALIZER();
 203 static pthread_mutex_t mlx5_ibv_list_mutex = PTHREAD_MUTEX_INITIALIZER;
 204
 205 static struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 206 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 207         {
 208                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 209                 .trunk_size = 64,
 210                 .grow_trunk = 3,
 211                 .grow_shift = 2,
 212                 .need_lock = 0,
 213                 .release_mem_en = 1,
 214                 .malloc = rte_malloc_socket,
 215                 .free = rte_free,
 216                 .type = "mlx5_encap_decap_ipool",
 217         },
 218         {
 219                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 220                 .trunk_size = 64,
 221                 .grow_trunk = 3,
 222                 .grow_shift = 2,
 223                 .need_lock = 0,
 224                 .release_mem_en = 1,
 225                 .malloc = rte_malloc_socket,
 226                 .free = rte_free,
 227                 .type = "mlx5_push_vlan_ipool",
 228         },
 229         {
 230                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 231                 .trunk_size = 64,
 232                 .grow_trunk = 3,
 233                 .grow_shift = 2,
 234                 .need_lock = 0,
 235                 .release_mem_en = 1,
 236                 .malloc = rte_malloc_socket,
 237                 .free = rte_free,
 238                 .type = "mlx5_tag_ipool",
 239         },
 240         {
 241                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 242                 .trunk_size = 64,
 243                 .grow_trunk = 3,
 244                 .grow_shift = 2,
 245                 .need_lock = 0,
 246                 .release_mem_en = 1,
 247                 .malloc = rte_malloc_socket,
 248                 .free = rte_free,
 249                 .type = "mlx5_port_id_ipool",
 250         },
 251         {
 252                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 253                 .trunk_size = 64,
 254                 .grow_trunk = 3,
 255                 .grow_shift = 2,
 256                 .need_lock = 0,
 257                 .release_mem_en = 1,
 258                 .malloc = rte_malloc_socket,
 259                 .free = rte_free,
 260                 .type = "mlx5_jump_ipool",
 261         },
 262 #endif
 263         {
 264                 .size = sizeof(struct mlx5_flow_meter),
 265                 .trunk_size = 64,
 266                 .grow_trunk = 3,
 267                 .grow_shift = 2,
 268                 .need_lock = 0,
 269                 .release_mem_en = 1,
 270                 .malloc = rte_malloc_socket,
 271                 .free = rte_free,
 272                 .type = "mlx5_meter_ipool",
 273         },
 274         {
 275                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 276                 .trunk_size = 64,
 277                 .grow_trunk = 3,
 278                 .grow_shift = 2,
 279                 .need_lock = 0,
 280                 .release_mem_en = 1,
 281                 .malloc = rte_malloc_socket,
 282                 .free = rte_free,
 283                 .type = "mlx5_mcp_ipool",
 284         },
 285         {
 286                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 287                 .trunk_size = 64,
 288                 .grow_trunk = 3,
 289                 .grow_shift = 2,
 290                 .need_lock = 0,
 291                 .release_mem_en = 1,
 292                 .malloc = rte_malloc_socket,
 293                 .free = rte_free,
 294                 .type = "mlx5_hrxq_ipool",
 295         },
 296         {
 297                 .size = sizeof(struct mlx5_flow_handle),
 298                 .trunk_size = 64,
 299                 .grow_trunk = 3,
 300                 .grow_shift = 2,
 301                 .need_lock = 0,
 302                 .release_mem_en = 1,
 303                 .malloc = rte_malloc_socket,
 304                 .free = rte_free,
 305                 .type = "mlx5_flow_handle_ipool",
 306         },
 307         {
 308                 .size = sizeof(struct rte_flow),
 309                 .trunk_size = 4096,
 310                 .need_lock = 1,
 311                 .release_mem_en = 1,
 312                 .malloc = rte_malloc_socket,
 313                 .free = rte_free,
 314                 .type = "rte_flow_ipool",
 315         },
 316 };
 317
 318
 319 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 320 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 321
 322 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 323 #define MLX5_TAGS_HLIST_ARRAY_SIZE 8192
 324
 325 /**
 326  * Allocate ID pool structure.
 327  *
 328  * @param[in] max_id
 329  *   The maximum id can be allocated from the pool.
 330  *
 331  * @return
 332  *   Pointer to pool object, NULL value otherwise.
 333  */
 334 struct mlx5_flow_id_pool *
 335 mlx5_flow_id_pool_alloc(uint32_t max_id)
 336 {
 337         struct mlx5_flow_id_pool *pool;
 338         void *mem;
 339
 340         pool = rte_zmalloc("id pool allocation", sizeof(*pool),
 341                            RTE_CACHE_LINE_SIZE);
 342         if (!pool) {
 343                 DRV_LOG(ERR, "can't allocate id pool");
 344                 rte_errno  = ENOMEM;
 345                 return NULL;
 346         }
 347         mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
 348                           RTE_CACHE_LINE_SIZE);
 349         if (!mem) {
 350                 DRV_LOG(ERR, "can't allocate mem for id pool");
 351                 rte_errno  = ENOMEM;
 352                 goto error;
 353         }
 354         pool->free_arr = mem;
 355         pool->curr = pool->free_arr;
 356         pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
 357         pool->base_index = 0;
 358         pool->max_id = max_id;
 359         return pool;
 360 error:
 361         rte_free(pool);
 362         return NULL;
 363 }
 364
 365 /**
 366  * Release ID pool structure.
 367  *
 368  * @param[in] pool
 369  *   Pointer to flow id pool object to free.
 370  */
 371 void
 372 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
 373 {
 374         rte_free(pool->free_arr);
 375         rte_free(pool);
 376 }
 377
 378 /**
 379  * Generate ID.
 380  *
 381  * @param[in] pool
 382  *   Pointer to flow id pool.
 383  * @param[out] id
 384  *   The generated ID.
 385  *
 386  * @return
 387  *   0 on success, error value otherwise.
 388  */
 389 uint32_t
 390 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
 391 {
 392         if (pool->curr == pool->free_arr) {
 393                 if (pool->base_index == pool->max_id) {
 394                         rte_errno  = ENOMEM;
 395                         DRV_LOG(ERR, "no free id");
 396                         return -rte_errno;
 397                 }
 398                 *id = ++pool->base_index;
 399                 return 0;
 400         }
 401         *id = *(--pool->curr);
 402         return 0;
 403 }
 404
 405 /**
 406  * Release ID.
 407  *
 408  * @param[in] pool
 409  *   Pointer to flow id pool.
 410  * @param[out] id
 411  *   The generated ID.
 412  *
 413  * @return
 414  *   0 on success, error value otherwise.
 415  */
 416 uint32_t
 417 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
 418 {
 419         uint32_t size;
 420         uint32_t size2;
 421         void *mem;
 422
 423         if (pool->curr == pool->last) {
 424                 size = pool->curr - pool->free_arr;
 425                 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
 426                 MLX5_ASSERT(size2 > size);
 427                 mem = rte_malloc("", size2 * sizeof(uint32_t), 0);
 428                 if (!mem) {
 429                         DRV_LOG(ERR, "can't allocate mem for id pool");
 430                         rte_errno  = ENOMEM;
 431                         return -rte_errno;
 432                 }
 433                 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
 434                 rte_free(pool->free_arr);
 435                 pool->free_arr = mem;
 436                 pool->curr = pool->free_arr + size;
 437                 pool->last = pool->free_arr + size2;
 438         }
 439         *pool->curr = id;
 440         pool->curr++;
 441         return 0;
 442 }
 443
 444 /**
 445  * Initialize the shared aging list information per port.
 446  *
 447  * @param[in] sh
 448  *   Pointer to mlx5_dev_ctx_shared object.
 449  */
 450 static void
 451 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 452 {
 453         uint32_t i;
 454         struct mlx5_age_info *age_info;
 455
 456         for (i = 0; i < sh->max_port; i++) {
 457                 age_info = &sh->port[i].age_info;
 458                 age_info->flags = 0;
 459                 TAILQ_INIT(&age_info->aged_counters);
 460                 rte_spinlock_init(&age_info->aged_sl);
 461                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 462         }
 463 }
 464
 465 /**
 466  * Initialize the counters management structure.
 467  *
 468  * @param[in] sh
 469  *   Pointer to mlx5_dev_ctx_shared object to free
 470  */
 471 static void
 472 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 473 {
 474         int i;
 475
 476         memset(&sh->cmng, 0, sizeof(sh->cmng));
 477         TAILQ_INIT(&sh->cmng.flow_counters);
 478         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 479                 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
 480                 rte_spinlock_init(&sh->cmng.ccont[i].resize_sl);
 481         }
 482 }
 483
 484 /**
 485  * Destroy all the resources allocated for a counter memory management.
 486  *
 487  * @param[in] mng
 488  *   Pointer to the memory management structure.
 489  */
 490 static void
 491 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 492 {
 493         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 494
 495         LIST_REMOVE(mng, next);
 496         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 497         claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
 498         rte_free(mem);
 499 }
 500
 501 /**
 502  * Close and release all the resources of the counters management.
 503  *
 504  * @param[in] sh
 505  *   Pointer to mlx5_dev_ctx_shared object to free.
 506  */
 507 static void
 508 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 509 {
 510         struct mlx5_counter_stats_mem_mng *mng;
 511         int i;
 512         int j;
 513         int retries = 1024;
 514
 515         rte_errno = 0;
 516         while (--retries) {
 517                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 518                 if (rte_errno != EINPROGRESS)
 519                         break;
 520                 rte_pause();
 521         }
 522         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 523                 struct mlx5_flow_counter_pool *pool;
 524                 uint32_t batch = !!(i > 1);
 525
 526                 if (!sh->cmng.ccont[i].pools)
 527                         continue;
 528                 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 529                 while (pool) {
 530                         if (batch && pool->min_dcs)
 531                                 claim_zero(mlx5_devx_cmd_destroy
 532                                                                (pool->min_dcs));
 533                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 534                                 if (MLX5_POOL_GET_CNT(pool, j)->action)
 535                                         claim_zero
 536                                          (mlx5_glue->destroy_flow_action
 537                                           (MLX5_POOL_GET_CNT
 538                                           (pool, j)->action));
 539                                 if (!batch && MLX5_GET_POOL_CNT_EXT
 540                                     (pool, j)->dcs)
 541                                         claim_zero(mlx5_devx_cmd_destroy
 542                                                    (MLX5_GET_POOL_CNT_EXT
 543                                                     (pool, j)->dcs));
 544                         }
 545                         TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, next);
 546                         rte_free(pool);
 547                         pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 548                 }
 549                 rte_free(sh->cmng.ccont[i].pools);
 550         }
 551         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 552         while (mng) {
 553                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 554                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 555         }
 556         memset(&sh->cmng, 0, sizeof(sh->cmng));
 557 }
 558
 559 /**
 560  * Initialize the flow resources' indexed mempool.
 561  *
 562  * @param[in] sh
 563  *   Pointer to mlx5_dev_ctx_shared object.
 564  * @param[in] sh
 565  *   Pointer to user dev config.
 566  */
 567 static void
 568 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 569                        const struct mlx5_dev_config *config __rte_unused)
 570 {
 571         uint8_t i;
 572
 573 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 574         /*
 575          * While DV is supported, user chooses the verbs mode,
 576          * the mlx5 flow handle size is different with the
 577          * MLX5_FLOW_HANDLE_VERBS_SIZE.
 578          */
 579         if (!config->dv_flow_en)
 580                 mlx5_ipool_cfg[MLX5_IPOOL_MLX5_FLOW].size =
 581                                         MLX5_FLOW_HANDLE_VERBS_SIZE;
 582 #endif
 583         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 584                 if (config->reclaim_mode)
 585                         mlx5_ipool_cfg[i].release_mem_en = 1;
 586                 sh->ipool[i] = mlx5_ipool_create(&mlx5_ipool_cfg[i]);
 587         }
 588 }
 589
 590 /**
 591  * Release the flow resources' indexed mempool.
 592  *
 593  * @param[in] sh
 594  *   Pointer to mlx5_dev_ctx_shared object.
 595  */
 596 static void
 597 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 598 {
 599         uint8_t i;
 600
 601         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 602                 mlx5_ipool_destroy(sh->ipool[i]);
 603 }
 604
 605 /**
 606  * Extract pdn of PD object using DV API.
 607  *
 608  * @param[in] pd
 609  *   Pointer to the verbs PD object.
 610  * @param[out] pdn
 611  *   Pointer to the PD object number variable.
 612  *
 613  * @return
 614  *   0 on success, error value otherwise.
 615  */
 616 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 617 static int
 618 mlx5_get_pdn(struct ibv_pd *pd __rte_unused, uint32_t *pdn __rte_unused)
 619 {
 620         struct mlx5dv_obj obj;
 621         struct mlx5dv_pd pd_info;
 622         int ret = 0;
 623
 624         obj.pd.in = pd;
 625         obj.pd.out = &pd_info;
 626         ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);
 627         if (ret) {
 628                 DRV_LOG(DEBUG, "Fail to get PD object info");
 629                 return ret;
 630         }
 631         *pdn = pd_info.pdn;
 632         return 0;
 633 }
 634 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
 635
 636 static int
 637 mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config)
 638 {
 639         char *env;
 640         int value;
 641
 642         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 643         /* Get environment variable to store. */
 644         env = getenv(MLX5_SHUT_UP_BF);
 645         value = env ? !!strcmp(env, "0") : MLX5_ARG_UNSET;
 646         if (config->dbnc == MLX5_ARG_UNSET)
 647                 setenv(MLX5_SHUT_UP_BF, MLX5_SHUT_UP_BF_DEFAULT, 1);
 648         else
 649                 setenv(MLX5_SHUT_UP_BF,
 650                        config->dbnc == MLX5_TXDB_NCACHED ? "1" : "0", 1);
 651         return value;
 652 }
 653
 654 static void
 655 mlx5_restore_doorbell_mapping_env(int value)
 656 {
 657         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 658         /* Restore the original environment variable state. */
 659         if (value == MLX5_ARG_UNSET)
 660                 unsetenv(MLX5_SHUT_UP_BF);
 661         else
 662                 setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1);
 663 }
 664
 665 /**
 666  * Install shared asynchronous device events handler.
 667  * This function is implemented to support event sharing
 668  * between multiple ports of single IB device.
 669  *
 670  * @param sh
 671  *   Pointer to mlx5_dev_ctx_shared object.
 672  */
 673 static void
 674 mlx5_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh)
 675 {
 676         int ret;
 677         int flags;
 678
 679         sh->intr_handle.fd = -1;
 680         flags = fcntl(sh->ctx->async_fd, F_GETFL);
 681         ret = fcntl(sh->ctx->async_fd, F_SETFL, flags | O_NONBLOCK);
 682         if (ret) {
 683                 DRV_LOG(INFO, "failed to change file descriptor async event"
 684                         " queue");
 685         } else {
 686                 sh->intr_handle.fd = sh->ctx->async_fd;
 687                 sh->intr_handle.type = RTE_INTR_HANDLE_EXT;
 688                 if (rte_intr_callback_register(&sh->intr_handle,
 689                                         mlx5_dev_interrupt_handler, sh)) {
 690                         DRV_LOG(INFO, "Fail to install the shared interrupt.");
 691                         sh->intr_handle.fd = -1;
 692                 }
 693         }
 694         if (sh->devx) {
 695 #ifdef HAVE_IBV_DEVX_ASYNC
 696                 sh->intr_handle_devx.fd = -1;
 697                 sh->devx_comp = mlx5_glue->devx_create_cmd_comp(sh->ctx);
 698                 if (!sh->devx_comp) {
 699                         DRV_LOG(INFO, "failed to allocate devx_comp.");
 700                         return;
 701                 }
 702                 flags = fcntl(sh->devx_comp->fd, F_GETFL);
 703                 ret = fcntl(sh->devx_comp->fd, F_SETFL, flags | O_NONBLOCK);
 704                 if (ret) {
 705                         DRV_LOG(INFO, "failed to change file descriptor"
 706                                 " devx comp");
 707                         return;
 708                 }
 709                 sh->intr_handle_devx.fd = sh->devx_comp->fd;
 710                 sh->intr_handle_devx.type = RTE_INTR_HANDLE_EXT;
 711                 if (rte_intr_callback_register(&sh->intr_handle_devx,
 712                                         mlx5_dev_interrupt_handler_devx, sh)) {
 713                         DRV_LOG(INFO, "Fail to install the devx shared"
 714                                 " interrupt.");
 715                         sh->intr_handle_devx.fd = -1;
 716                 }
 717 #endif /* HAVE_IBV_DEVX_ASYNC */
 718         }
 719 }
 720
 721 /**
 722  * Uninstall shared asynchronous device events handler.
 723  * This function is implemented to support event sharing
 724  * between multiple ports of single IB device.
 725  *
 726  * @param dev
 727  *   Pointer to mlx5_dev_ctx_shared object.
 728  */
 729 static void
 730 mlx5_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh)
 731 {
 732         if (sh->intr_handle.fd >= 0)
 733                 mlx5_intr_callback_unregister(&sh->intr_handle,
 734                                               mlx5_dev_interrupt_handler, sh);
 735 #ifdef HAVE_IBV_DEVX_ASYNC
 736         if (sh->intr_handle_devx.fd >= 0)
 737                 rte_intr_callback_unregister(&sh->intr_handle_devx,
 738                                   mlx5_dev_interrupt_handler_devx, sh);
 739         if (sh->devx_comp)
 740                 mlx5_glue->devx_destroy_cmd_comp(sh->devx_comp);
 741 #endif
 742 }
 743
 744 /**
 745  * Allocate shared IB device context. If there is multiport device the
 746  * master and representors will share this context, if there is single
 747  * port dedicated IB device, the context will be used by only given
 748  * port due to unification.
 749  *
 750  * Routine first searches the context for the specified IB device name,
 751  * if found the shared context assumed and reference counter is incremented.
 752  * If no context found the new one is created and initialized with specified
 753  * IB device context and parameters.
 754  *
 755  * @param[in] spawn
 756  *   Pointer to the IB device attributes (name, port, etc).
 757  * @param[in] config
 758  *   Pointer to device configuration structure.
 759  *
 760  * @return
 761  *   Pointer to mlx5_dev_ctx_shared object on success,
 762  *   otherwise NULL and rte_errno is set.
 763  */
 764 static struct mlx5_dev_ctx_shared *
 765 mlx5_alloc_shared_ibctx(const struct mlx5_dev_spawn_data *spawn,
 766                         const struct mlx5_dev_config *config)
 767 {
 768         struct mlx5_dev_ctx_shared *sh;
 769         int dbmap_env;
 770         int err = 0;
 771         uint32_t i;
 772 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 773         struct mlx5_devx_tis_attr tis_attr = { 0 };
 774 #endif
 775
 776         MLX5_ASSERT(spawn);
 777         /* Secondary process should not create the shared context. */
 778         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 779         pthread_mutex_lock(&mlx5_ibv_list_mutex);
 780         /* Search for IB context by device name. */
 781         LIST_FOREACH(sh, &mlx5_ibv_list, next) {
 782                 if (!strcmp(sh->ibdev_name, spawn->ibv_dev->name)) {
 783                         sh->refcnt++;
 784                         goto exit;
 785                 }
 786         }
 787         /* No device found, we have to create new shared context. */
 788         MLX5_ASSERT(spawn->max_port);
 789         sh = rte_zmalloc("ethdev shared ib context",
 790                          sizeof(struct mlx5_dev_ctx_shared) +
 791                          spawn->max_port *
 792                          sizeof(struct mlx5_ibv_shared_port),
 793                          RTE_CACHE_LINE_SIZE);
 794         if (!sh) {
 795                 DRV_LOG(ERR, "shared context allocation failure");
 796                 rte_errno  = ENOMEM;
 797                 goto exit;
 798         }
 799         /*
 800          * Configure environment variable "MLX5_BF_SHUT_UP"
 801          * before the device creation. The rdma_core library
 802          * checks the variable at device creation and
 803          * stores the result internally.
 804          */
 805         dbmap_env = mlx5_config_doorbell_mapping_env(config);
 806         /* Try to open IB device with DV first, then usual Verbs. */
 807         errno = 0;
 808         sh->ctx = mlx5_glue->dv_open_device(spawn->ibv_dev);
 809         if (sh->ctx) {
 810                 sh->devx = 1;
 811                 DRV_LOG(DEBUG, "DevX is supported");
 812                 /* The device is created, no need for environment. */
 813                 mlx5_restore_doorbell_mapping_env(dbmap_env);
 814         } else {
 815                 /* The environment variable is still configured. */
 816                 sh->ctx = mlx5_glue->open_device(spawn->ibv_dev);
 817                 err = errno ? errno : ENODEV;
 818                 /*
 819                  * The environment variable is not needed anymore,
 820                  * all device creation attempts are completed.
 821                  */
 822                 mlx5_restore_doorbell_mapping_env(dbmap_env);
 823                 if (!sh->ctx)
 824                         goto error;
 825                 DRV_LOG(DEBUG, "DevX is NOT supported");
 826         }
 827         err = mlx5_glue->query_device_ex(sh->ctx, NULL, &sh->device_attr);
 828         if (err) {
 829                 DRV_LOG(DEBUG, "ibv_query_device_ex() failed");
 830                 goto error;
 831         }
 832         sh->refcnt = 1;
 833         sh->max_port = spawn->max_port;
 834         strncpy(sh->ibdev_name, sh->ctx->device->name,
 835                 sizeof(sh->ibdev_name));
 836         strncpy(sh->ibdev_path, sh->ctx->device->ibdev_path,
 837                 sizeof(sh->ibdev_path));
 838         /*
 839          * Setting port_id to max unallowed value means
 840          * there is no interrupt subhandler installed for
 841          * the given port index i.
 842          */
 843         for (i = 0; i < sh->max_port; i++) {
 844                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 845                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
 846         }
 847         sh->pd = mlx5_glue->alloc_pd(sh->ctx);
 848         if (sh->pd == NULL) {
 849                 DRV_LOG(ERR, "PD allocation failure");
 850                 err = ENOMEM;
 851                 goto error;
 852         }
 853 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 854         if (sh->devx) {
 855                 err = mlx5_get_pdn(sh->pd, &sh->pdn);
 856                 if (err) {
 857                         DRV_LOG(ERR, "Fail to extract pdn from PD");
 858                         goto error;
 859                 }
 860                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
 861                 if (!sh->td) {
 862                         DRV_LOG(ERR, "TD allocation failure");
 863                         err = ENOMEM;
 864                         goto error;
 865                 }
 866                 tis_attr.transport_domain = sh->td->id;
 867                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
 868                 if (!sh->tis) {
 869                         DRV_LOG(ERR, "TIS allocation failure");
 870                         err = ENOMEM;
 871                         goto error;
 872                 }
 873         }
 874         sh->flow_id_pool = mlx5_flow_id_pool_alloc
 875                                         ((1 << HAIRPIN_FLOW_ID_BITS) - 1);
 876         if (!sh->flow_id_pool) {
 877                 DRV_LOG(ERR, "can't create flow id pool");
 878                 err = ENOMEM;
 879                 goto error;
 880         }
 881 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
 882         /*
 883          * Once the device is added to the list of memory event
 884          * callback, its global MR cache table cannot be expanded
 885          * on the fly because of deadlock. If it overflows, lookup
 886          * should be done by searching MR list linearly, which is slow.
 887          *
 888          * At this point the device is not added to the memory
 889          * event list yet, context is just being created.
 890          */
 891         err = mlx5_mr_btree_init(&sh->share_cache.cache,
 892                                  MLX5_MR_BTREE_CACHE_N * 2,
 893                                  spawn->pci_dev->device.numa_node);
 894         if (err) {
 895                 err = rte_errno;
 896                 goto error;
 897         }
 898         mlx5_dev_shared_handler_install(sh);
 899         mlx5_flow_aging_init(sh);
 900         mlx5_flow_counters_mng_init(sh);
 901         mlx5_flow_ipool_create(sh, config);
 902         /* Add device to memory callback list. */
 903         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 904         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
 905                          sh, mem_event_cb);
 906         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 907         /* Add context to the global device list. */
 908         LIST_INSERT_HEAD(&mlx5_ibv_list, sh, next);
 909 exit:
 910         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 911         return sh;
 912 error:
 913         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 914         MLX5_ASSERT(sh);
 915         if (sh->tis)
 916                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 917         if (sh->td)
 918                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 919         if (sh->pd)
 920                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 921         if (sh->ctx)
 922                 claim_zero(mlx5_glue->close_device(sh->ctx));
 923         if (sh->flow_id_pool)
 924                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 925         rte_free(sh);
 926         MLX5_ASSERT(err > 0);
 927         rte_errno = err;
 928         return NULL;
 929 }
 930
 931 /**
 932  * Free shared IB device context. Decrement counter and if zero free
 933  * all allocated resources and close handles.
 934  *
 935  * @param[in] sh
 936  *   Pointer to mlx5_dev_ctx_shared object to free
 937  */
 938 static void
 939 mlx5_free_shared_ibctx(struct mlx5_dev_ctx_shared *sh)
 940 {
 941         pthread_mutex_lock(&mlx5_ibv_list_mutex);
 942 #ifdef RTE_LIBRTE_MLX5_DEBUG
 943         /* Check the object presence in the list. */
 944         struct mlx5_dev_ctx_shared *lctx;
 945
 946         LIST_FOREACH(lctx, &mlx5_ibv_list, next)
 947                 if (lctx == sh)
 948                         break;
 949         MLX5_ASSERT(lctx);
 950         if (lctx != sh) {
 951                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
 952                 goto exit;
 953         }
 954 #endif
 955         MLX5_ASSERT(sh);
 956         MLX5_ASSERT(sh->refcnt);
 957         /* Secondary process should not free the shared context. */
 958         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 959         if (--sh->refcnt)
 960                 goto exit;
 961         /* Remove from memory callback device list. */
 962         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 963         LIST_REMOVE(sh, mem_event_cb);
 964         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 965         /* Release created Memory Regions. */
 966         mlx5_mr_release_cache(&sh->share_cache);
 967         /* Remove context from the global device list. */
 968         LIST_REMOVE(sh, next);
 969         /*
 970          *  Ensure there is no async event handler installed.
 971          *  Only primary process handles async device events.
 972          **/
 973         mlx5_flow_counters_mng_close(sh);
 974         mlx5_flow_ipool_destroy(sh);
 975         mlx5_dev_shared_handler_uninstall(sh);
 976         if (sh->pd)
 977                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 978         if (sh->tis)
 979                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 980         if (sh->td)
 981                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 982         if (sh->ctx)
 983                 claim_zero(mlx5_glue->close_device(sh->ctx));
 984         if (sh->flow_id_pool)
 985                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 986         rte_free(sh);
 987 exit:
 988         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 989 }
 990
 991 /**
 992  * Destroy table hash list and all the root entries per domain.
 993  *
 994  * @param[in] priv
 995  *   Pointer to the private device data structure.
 996  */
 997 static void
 998 mlx5_free_table_hash_list(struct mlx5_priv *priv)
 999 {
1000         struct mlx5_dev_ctx_shared *sh = priv->sh;
1001         struct mlx5_flow_tbl_data_entry *tbl_data;
1002         union mlx5_flow_tbl_key table_key = {
1003                 {
1004                         .table_id = 0,
1005                         .reserved = 0,
1006                         .domain = 0,
1007                         .direction = 0,
1008                 }
1009         };
1010         struct mlx5_hlist_entry *pos;
1011
1012         if (!sh->flow_tbls)
1013                 return;
1014         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1015         if (pos) {
1016                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1017                                         entry);
1018                 MLX5_ASSERT(tbl_data);
1019                 mlx5_hlist_remove(sh->flow_tbls, pos);
1020                 rte_free(tbl_data);
1021         }
1022         table_key.direction = 1;
1023         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1024         if (pos) {
1025                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1026                                         entry);
1027                 MLX5_ASSERT(tbl_data);
1028                 mlx5_hlist_remove(sh->flow_tbls, pos);
1029                 rte_free(tbl_data);
1030         }
1031         table_key.direction = 0;
1032         table_key.domain = 1;
1033         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1034         if (pos) {
1035                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1036                                         entry);
1037                 MLX5_ASSERT(tbl_data);
1038                 mlx5_hlist_remove(sh->flow_tbls, pos);
1039                 rte_free(tbl_data);
1040         }
1041         mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
1042 }
1043
1044 /**
1045  * Initialize flow table hash list and create the root tables entry
1046  * for each domain.
1047  *
1048  * @param[in] priv
1049  *   Pointer to the private device data structure.
1050  *
1051  * @return
1052  *   Zero on success, positive error code otherwise.
1053  */
1054 static int
1055 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
1056 {
1057         struct mlx5_dev_ctx_shared *sh = priv->sh;
1058         char s[MLX5_HLIST_NAMESIZE];
1059         int err = 0;
1060
1061         MLX5_ASSERT(sh);
1062         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1063         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
1064         if (!sh->flow_tbls) {
1065                 DRV_LOG(ERR, "flow tables with hash creation failed.\n");
1066                 err = ENOMEM;
1067                 return err;
1068         }
1069 #ifndef HAVE_MLX5DV_DR
1070         /*
1071          * In case we have not DR support, the zero tables should be created
1072          * because DV expect to see them even if they cannot be created by
1073          * RDMA-CORE.
1074          */
1075         union mlx5_flow_tbl_key table_key = {
1076                 {
1077                         .table_id = 0,
1078                         .reserved = 0,
1079                         .domain = 0,
1080                         .direction = 0,
1081                 }
1082         };
1083         struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL,
1084                                                           sizeof(*tbl_data), 0);
1085
1086         if (!tbl_data) {
1087                 err = ENOMEM;
1088                 goto error;
1089         }
1090         tbl_data->entry.key = table_key.v64;
1091         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1092         if (err)
1093                 goto error;
1094         rte_atomic32_init(&tbl_data->tbl.refcnt);
1095         rte_atomic32_inc(&tbl_data->tbl.refcnt);
1096         table_key.direction = 1;
1097         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
1098         if (!tbl_data) {
1099                 err = ENOMEM;
1100                 goto error;
1101         }
1102         tbl_data->entry.key = table_key.v64;
1103         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1104         if (err)
1105                 goto error;
1106         rte_atomic32_init(&tbl_data->tbl.refcnt);
1107         rte_atomic32_inc(&tbl_data->tbl.refcnt);
1108         table_key.direction = 0;
1109         table_key.domain = 1;
1110         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
1111         if (!tbl_data) {
1112                 err = ENOMEM;
1113                 goto error;
1114         }
1115         tbl_data->entry.key = table_key.v64;
1116         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1117         if (err)
1118                 goto error;
1119         rte_atomic32_init(&tbl_data->tbl.refcnt);
1120         rte_atomic32_inc(&tbl_data->tbl.refcnt);
1121         return err;
1122 error:
1123         mlx5_free_table_hash_list(priv);
1124 #endif /* HAVE_MLX5DV_DR */
1125         return err;
1126 }
1127
1128 /**
1129  * Initialize DR related data within private structure.
1130  * Routine checks the reference counter and does actual
1131  * resources creation/initialization only if counter is zero.
1132  *
1133  * @param[in] priv
1134  *   Pointer to the private device data structure.
1135  *
1136  * @return
1137  *   Zero on success, positive error code otherwise.
1138  */
1139 static int
1140 mlx5_alloc_shared_dr(struct mlx5_priv *priv)
1141 {
1142         struct mlx5_dev_ctx_shared *sh = priv->sh;
1143         char s[MLX5_HLIST_NAMESIZE];
1144         int err = 0;
1145
1146         if (!sh->flow_tbls)
1147                 err = mlx5_alloc_table_hash_list(priv);
1148         else
1149                 DRV_LOG(DEBUG, "sh->flow_tbls[%p] already created, reuse\n",
1150                         (void *)sh->flow_tbls);
1151         if (err)
1152                 return err;
1153         /* Create tags hash list table. */
1154         snprintf(s, sizeof(s), "%s_tags", sh->ibdev_name);
1155         sh->tag_table = mlx5_hlist_create(s, MLX5_TAGS_HLIST_ARRAY_SIZE);
1156         if (!sh->tag_table) {
1157                 DRV_LOG(ERR, "tags with hash creation failed.\n");
1158                 err = ENOMEM;
1159                 goto error;
1160         }
1161 #ifdef HAVE_MLX5DV_DR
1162         void *domain;
1163
1164         if (sh->dv_refcnt) {
1165                 /* Shared DV/DR structures is already initialized. */
1166                 sh->dv_refcnt++;
1167                 priv->dr_shared = 1;
1168                 return 0;
1169         }
1170         /* Reference counter is zero, we should initialize structures. */
1171         domain = mlx5_glue->dr_create_domain(sh->ctx,
1172                                              MLX5DV_DR_DOMAIN_TYPE_NIC_RX);
1173         if (!domain) {
1174                 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed");
1175                 err = errno;
1176                 goto error;
1177         }
1178         sh->rx_domain = domain;
1179         domain = mlx5_glue->dr_create_domain(sh->ctx,
1180                                              MLX5DV_DR_DOMAIN_TYPE_NIC_TX);
1181         if (!domain) {
1182                 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed");
1183                 err = errno;
1184                 goto error;
1185         }
1186         pthread_mutex_init(&sh->dv_mutex, NULL);
1187         sh->tx_domain = domain;
1188 #ifdef HAVE_MLX5DV_DR_ESWITCH
1189         if (priv->config.dv_esw_en) {
1190                 domain  = mlx5_glue->dr_create_domain
1191                         (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB);
1192                 if (!domain) {
1193                         DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed");
1194                         err = errno;
1195                         goto error;
1196                 }
1197                 sh->fdb_domain = domain;
1198                 sh->esw_drop_action = mlx5_glue->dr_create_flow_action_drop();
1199         }
1200 #endif
1201         if (priv->config.reclaim_mode == MLX5_RCM_AGGR) {
1202                 mlx5_glue->dr_reclaim_domain_memory(sh->rx_domain, 1);
1203                 mlx5_glue->dr_reclaim_domain_memory(sh->tx_domain, 1);
1204                 if (sh->fdb_domain)
1205                         mlx5_glue->dr_reclaim_domain_memory(sh->fdb_domain, 1);
1206         }
1207         sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan();
1208 #endif /* HAVE_MLX5DV_DR */
1209         sh->dv_refcnt++;
1210         priv->dr_shared = 1;
1211         return 0;
1212 error:
1213         /* Rollback the created objects. */
1214         if (sh->rx_domain) {
1215                 mlx5_glue->dr_destroy_domain(sh->rx_domain);
1216                 sh->rx_domain = NULL;
1217         }
1218         if (sh->tx_domain) {
1219                 mlx5_glue->dr_destroy_domain(sh->tx_domain);
1220                 sh->tx_domain = NULL;
1221         }
1222         if (sh->fdb_domain) {
1223                 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
1224                 sh->fdb_domain = NULL;
1225         }
1226         if (sh->esw_drop_action) {
1227                 mlx5_glue->destroy_flow_action(sh->esw_drop_action);
1228                 sh->esw_drop_action = NULL;
1229         }
1230         if (sh->pop_vlan_action) {
1231                 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
1232                 sh->pop_vlan_action = NULL;
1233         }
1234         if (sh->tag_table) {
1235                 /* tags should be destroyed with flow before. */
1236                 mlx5_hlist_destroy(sh->tag_table, NULL, NULL);
1237                 sh->tag_table = NULL;
1238         }
1239         mlx5_free_table_hash_list(priv);
1240         return err;
1241 }
1242
1243 /**
1244  * Destroy DR related data within private structure.
1245  *
1246  * @param[in] priv
1247  *   Pointer to the private device data structure.
1248  */
1249 static void
1250 mlx5_free_shared_dr(struct mlx5_priv *priv)
1251 {
1252         struct mlx5_dev_ctx_shared *sh;
1253
1254         if (!priv->dr_shared)
1255                 return;
1256         priv->dr_shared = 0;
1257         sh = priv->sh;
1258         MLX5_ASSERT(sh);
1259 #ifdef HAVE_MLX5DV_DR
1260         MLX5_ASSERT(sh->dv_refcnt);
1261         if (sh->dv_refcnt && --sh->dv_refcnt)
1262                 return;
1263         if (sh->rx_domain) {
1264                 mlx5_glue->dr_destroy_domain(sh->rx_domain);
1265                 sh->rx_domain = NULL;
1266         }
1267         if (sh->tx_domain) {
1268                 mlx5_glue->dr_destroy_domain(sh->tx_domain);
1269                 sh->tx_domain = NULL;
1270         }
1271 #ifdef HAVE_MLX5DV_DR_ESWITCH
1272         if (sh->fdb_domain) {
1273                 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
1274                 sh->fdb_domain = NULL;
1275         }
1276         if (sh->esw_drop_action) {
1277                 mlx5_glue->destroy_flow_action(sh->esw_drop_action);
1278                 sh->esw_drop_action = NULL;
1279         }
1280 #endif
1281         if (sh->pop_vlan_action) {
1282                 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
1283                 sh->pop_vlan_action = NULL;
1284         }
1285         pthread_mutex_destroy(&sh->dv_mutex);
1286 #endif /* HAVE_MLX5DV_DR */
1287         if (sh->tag_table) {
1288                 /* tags should be destroyed with flow before. */
1289                 mlx5_hlist_destroy(sh->tag_table, NULL, NULL);
1290                 sh->tag_table = NULL;
1291         }
1292         mlx5_free_table_hash_list(priv);
1293 }
1294
1295 /**
1296  * Initialize shared data between primary and secondary process.
1297  *
1298  * A memzone is reserved by primary process and secondary processes attach to
1299  * the memzone.
1300  *
1301  * @return
1302  *   0 on success, a negative errno value otherwise and rte_errno is set.
1303  */
1304 static int
1305 mlx5_init_shared_data(void)
1306 {
1307         const struct rte_memzone *mz;
1308         int ret = 0;
1309
1310         rte_spinlock_lock(&mlx5_shared_data_lock);
1311         if (mlx5_shared_data == NULL) {
1312                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
1313                         /* Allocate shared memory. */
1314                         mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
1315                                                  sizeof(*mlx5_shared_data),
1316                                                  SOCKET_ID_ANY, 0);
1317                         if (mz == NULL) {
1318                                 DRV_LOG(ERR,
1319                                         "Cannot allocate mlx5 shared data");
1320                                 ret = -rte_errno;
1321                                 goto error;
1322                         }
1323                         mlx5_shared_data = mz->addr;
1324                         memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
1325                         rte_spinlock_init(&mlx5_shared_data->lock);
1326                 } else {
1327                         /* Lookup allocated shared memory. */
1328                         mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
1329                         if (mz == NULL) {
1330                                 DRV_LOG(ERR,
1331                                         "Cannot attach mlx5 shared data");
1332                                 ret = -rte_errno;
1333                                 goto error;
1334                         }
1335                         mlx5_shared_data = mz->addr;
1336                         memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
1337                 }
1338         }
1339 error:
1340         rte_spinlock_unlock(&mlx5_shared_data_lock);
1341         return ret;
1342 }
1343
1344 /**
1345  * Retrieve integer value from environment variable.
1346  *
1347  * @param[in] name
1348  *   Environment variable name.
1349  *
1350  * @return
1351  *   Integer value, 0 if the variable is not set.
1352  */
1353 int
1354 mlx5_getenv_int(const char *name)
1355 {
1356         const char *val = getenv(name);
1357
1358         if (val == NULL)
1359                 return 0;
1360         return atoi(val);
1361 }
1362
1363 /**
1364  * Verbs callback to allocate a memory. This function should allocate the space
1365  * according to the size provided residing inside a huge page.
1366  * Please note that all allocation must respect the alignment from libmlx5
1367  * (i.e. currently sysconf(_SC_PAGESIZE)).
1368  *
1369  * @param[in] size
1370  *   The size in bytes of the memory to allocate.
1371  * @param[in] data
1372  *   A pointer to the callback data.
1373  *
1374  * @return
1375  *   Allocated buffer, NULL otherwise and rte_errno is set.
1376  */
1377 static void *
1378 mlx5_alloc_verbs_buf(size_t size, void *data)
1379 {
1380         struct mlx5_priv *priv = data;
1381         void *ret;
1382         size_t alignment = sysconf(_SC_PAGESIZE);
1383         unsigned int socket = SOCKET_ID_ANY;
1384
1385         if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
1386                 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
1387
1388                 socket = ctrl->socket;
1389         } else if (priv->verbs_alloc_ctx.type ==
1390                    MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
1391                 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
1392
1393                 socket = ctrl->socket;
1394         }
1395         MLX5_ASSERT(data != NULL);
1396         ret = rte_malloc_socket(__func__, size, alignment, socket);
1397         if (!ret && size)
1398                 rte_errno = ENOMEM;
1399         return ret;
1400 }
1401
1402 /**
1403  * Verbs callback to free a memory.
1404  *
1405  * @param[in] ptr
1406  *   A pointer to the memory to free.
1407  * @param[in] data
1408  *   A pointer to the callback data.
1409  */
1410 static void
1411 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
1412 {
1413         MLX5_ASSERT(data != NULL);
1414         rte_free(ptr);
1415 }
1416
1417 /**
1418  * DPDK callback to add udp tunnel port
1419  *
1420  * @param[in] dev
1421  *   A pointer to eth_dev
1422  * @param[in] udp_tunnel
1423  *   A pointer to udp tunnel
1424  *
1425  * @return
1426  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1427  */
1428 int
1429 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1430                          struct rte_eth_udp_tunnel *udp_tunnel)
1431 {
1432         MLX5_ASSERT(udp_tunnel != NULL);
1433         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1434             udp_tunnel->udp_port == 4789)
1435                 return 0;
1436         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1437             udp_tunnel->udp_port == 4790)
1438                 return 0;
1439         return -ENOTSUP;
1440 }
1441
1442 /**
1443  * Initialize process private data structure.
1444  *
1445  * @param dev
1446  *   Pointer to Ethernet device structure.
1447  *
1448  * @return
1449  *   0 on success, a negative errno value otherwise and rte_errno is set.
1450  */
1451 int
1452 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1453 {
1454         struct mlx5_priv *priv = dev->data->dev_private;
1455         struct mlx5_proc_priv *ppriv;
1456         size_t ppriv_size;
1457
1458         /*
1459          * UAR register table follows the process private structure. BlueFlame
1460          * registers for Tx queues are stored in the table.
1461          */
1462         ppriv_size =
1463                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1464         ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
1465                                   RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1466         if (!ppriv) {
1467                 rte_errno = ENOMEM;
1468                 return -rte_errno;
1469         }
1470         ppriv->uar_table_sz = ppriv_size;
1471         dev->process_private = ppriv;
1472         return 0;
1473 }
1474
1475 /**
1476  * Un-initialize process private data structure.
1477  *
1478  * @param dev
1479  *   Pointer to Ethernet device structure.
1480  */
1481 static void
1482 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1483 {
1484         if (!dev->process_private)
1485                 return;
1486         rte_free(dev->process_private);
1487         dev->process_private = NULL;
1488 }
1489
1490 /**
1491  * DPDK callback to close the device.
1492  *
1493  * Destroy all queues and objects, free memory.
1494  *
1495  * @param dev
1496  *   Pointer to Ethernet device structure.
1497  */
1498 static void
1499 mlx5_dev_close(struct rte_eth_dev *dev)
1500 {
1501         struct mlx5_priv *priv = dev->data->dev_private;
1502         unsigned int i;
1503         int ret;
1504
1505         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1506                 /* Check if process_private released. */
1507                 if (!dev->process_private)
1508                         return;
1509                 mlx5_tx_uar_uninit_secondary(dev);
1510                 mlx5_proc_priv_uninit(dev);
1511                 rte_eth_dev_release_port(dev);
1512                 return;
1513         }
1514         if (!priv->sh)
1515                 return;
1516         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1517                 dev->data->port_id,
1518                 ((priv->sh->ctx != NULL) ? priv->sh->ctx->device->name : ""));
1519         /*
1520          * If default mreg copy action is removed at the stop stage,
1521          * the search will return none and nothing will be done anymore.
1522          */
1523         mlx5_flow_stop_default(dev);
1524         mlx5_traffic_disable(dev);
1525         /*
1526          * If all the flows are already flushed in the device stop stage,
1527          * then this will return directly without any action.
1528          */
1529         mlx5_flow_list_flush(dev, &priv->flows, true);
1530         mlx5_flow_meter_flush(dev, NULL);
1531         /* Free the intermediate buffers for flow creation. */
1532         mlx5_flow_free_intermediate(dev);
1533         /* Prevent crashes when queues are still in use. */
1534         dev->rx_pkt_burst = removed_rx_burst;
1535         dev->tx_pkt_burst = removed_tx_burst;
1536         rte_wmb();
1537         /* Disable datapath on secondary process. */
1538         mlx5_mp_req_stop_rxtx(dev);
1539         if (priv->rxqs != NULL) {
1540                 /* XXX race condition if mlx5_rx_burst() is still running. */
1541                 usleep(1000);
1542                 for (i = 0; (i != priv->rxqs_n); ++i)
1543                         mlx5_rxq_release(dev, i);
1544                 priv->rxqs_n = 0;
1545                 priv->rxqs = NULL;
1546         }
1547         if (priv->txqs != NULL) {
1548                 /* XXX race condition if mlx5_tx_burst() is still running. */
1549                 usleep(1000);
1550                 for (i = 0; (i != priv->txqs_n); ++i)
1551                         mlx5_txq_release(dev, i);
1552                 priv->txqs_n = 0;
1553                 priv->txqs = NULL;
1554         }
1555         mlx5_proc_priv_uninit(dev);
1556         if (priv->mreg_cp_tbl)
1557                 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1558         mlx5_mprq_free_mp(dev);
1559         mlx5_free_shared_dr(priv);
1560         if (priv->rss_conf.rss_key != NULL)
1561                 rte_free(priv->rss_conf.rss_key);
1562         if (priv->reta_idx != NULL)
1563                 rte_free(priv->reta_idx);
1564         if (priv->config.vf)
1565                 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1566                                        dev->data->mac_addrs,
1567                                        MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1568         if (priv->nl_socket_route >= 0)
1569                 close(priv->nl_socket_route);
1570         if (priv->nl_socket_rdma >= 0)
1571                 close(priv->nl_socket_rdma);
1572         if (priv->vmwa_context)
1573                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1574         ret = mlx5_hrxq_verify(dev);
1575         if (ret)
1576                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1577                         dev->data->port_id);
1578         ret = mlx5_ind_table_obj_verify(dev);
1579         if (ret)
1580                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1581                         dev->data->port_id);
1582         ret = mlx5_rxq_obj_verify(dev);
1583         if (ret)
1584                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1585                         dev->data->port_id);
1586         ret = mlx5_rxq_verify(dev);
1587         if (ret)
1588                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1589                         dev->data->port_id);
1590         ret = mlx5_txq_obj_verify(dev);
1591         if (ret)
1592                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1593                         dev->data->port_id);
1594         ret = mlx5_txq_verify(dev);
1595         if (ret)
1596                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1597                         dev->data->port_id);
1598         ret = mlx5_flow_verify(dev);
1599         if (ret)
1600                 DRV_LOG(WARNING, "port %u some flows still remain",
1601                         dev->data->port_id);
1602         /*
1603          * Free the shared context in last turn, because the cleanup
1604          * routines above may use some shared fields, like
1605          * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1606          * ifindex if Netlink fails.
1607          */
1608         mlx5_free_shared_ibctx(priv->sh);
1609         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1610                 unsigned int c = 0;
1611                 uint16_t port_id;
1612
1613                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1614                         struct mlx5_priv *opriv =
1615                                 rte_eth_devices[port_id].data->dev_private;
1616
1617                         if (!opriv ||
1618                             opriv->domain_id != priv->domain_id ||
1619                             &rte_eth_devices[port_id] == dev)
1620                                 continue;
1621                         ++c;
1622                         break;
1623                 }
1624                 if (!c)
1625                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1626         }
1627         memset(priv, 0, sizeof(*priv));
1628         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1629         /*
1630          * Reset mac_addrs to NULL such that it is not freed as part of
1631          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1632          * it is freed when dev_private is freed.
1633          */
1634         dev->data->mac_addrs = NULL;
1635 }
1636
1637 const struct eth_dev_ops mlx5_dev_ops = {
1638         .dev_configure = mlx5_dev_configure,
1639         .dev_start = mlx5_dev_start,
1640         .dev_stop = mlx5_dev_stop,
1641         .dev_set_link_down = mlx5_set_link_down,
1642         .dev_set_link_up = mlx5_set_link_up,
1643         .dev_close = mlx5_dev_close,
1644         .promiscuous_enable = mlx5_promiscuous_enable,
1645         .promiscuous_disable = mlx5_promiscuous_disable,
1646         .allmulticast_enable = mlx5_allmulticast_enable,
1647         .allmulticast_disable = mlx5_allmulticast_disable,
1648         .link_update = mlx5_link_update,
1649         .stats_get = mlx5_stats_get,
1650         .stats_reset = mlx5_stats_reset,
1651         .xstats_get = mlx5_xstats_get,
1652         .xstats_reset = mlx5_xstats_reset,
1653         .xstats_get_names = mlx5_xstats_get_names,
1654         .fw_version_get = mlx5_fw_version_get,
1655         .dev_infos_get = mlx5_dev_infos_get,
1656         .read_clock = mlx5_read_clock,
1657         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1658         .vlan_filter_set = mlx5_vlan_filter_set,
1659         .rx_queue_setup = mlx5_rx_queue_setup,
1660         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1661         .tx_queue_setup = mlx5_tx_queue_setup,
1662         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1663         .rx_queue_release = mlx5_rx_queue_release,
1664         .tx_queue_release = mlx5_tx_queue_release,
1665         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1666         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1667         .mac_addr_remove = mlx5_mac_addr_remove,
1668         .mac_addr_add = mlx5_mac_addr_add,
1669         .mac_addr_set = mlx5_mac_addr_set,
1670         .set_mc_addr_list = mlx5_set_mc_addr_list,
1671         .mtu_set = mlx5_dev_set_mtu,
1672         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1673         .vlan_offload_set = mlx5_vlan_offload_set,
1674         .reta_update = mlx5_dev_rss_reta_update,
1675         .reta_query = mlx5_dev_rss_reta_query,
1676         .rss_hash_update = mlx5_rss_hash_update,
1677         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1678         .filter_ctrl = mlx5_dev_filter_ctrl,
1679         .rx_descriptor_status = mlx5_rx_descriptor_status,
1680         .tx_descriptor_status = mlx5_tx_descriptor_status,
1681         .rxq_info_get = mlx5_rxq_info_get,
1682         .txq_info_get = mlx5_txq_info_get,
1683         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1684         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1685         .rx_queue_count = mlx5_rx_queue_count,
1686         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1687         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1688         .is_removed = mlx5_is_removed,
1689         .udp_tunnel_port_add  = mlx5_udp_tunnel_port_add,
1690         .get_module_info = mlx5_get_module_info,
1691         .get_module_eeprom = mlx5_get_module_eeprom,
1692         .hairpin_cap_get = mlx5_hairpin_cap_get,
1693         .mtr_ops_get = mlx5_flow_meter_ops_get,
1694 };
1695
1696 /* Available operations from secondary process. */
1697 static const struct eth_dev_ops mlx5_dev_sec_ops = {
1698         .stats_get = mlx5_stats_get,
1699         .stats_reset = mlx5_stats_reset,
1700         .xstats_get = mlx5_xstats_get,
1701         .xstats_reset = mlx5_xstats_reset,
1702         .xstats_get_names = mlx5_xstats_get_names,
1703         .fw_version_get = mlx5_fw_version_get,
1704         .dev_infos_get = mlx5_dev_infos_get,
1705         .rx_descriptor_status = mlx5_rx_descriptor_status,
1706         .tx_descriptor_status = mlx5_tx_descriptor_status,
1707         .rxq_info_get = mlx5_rxq_info_get,
1708         .txq_info_get = mlx5_txq_info_get,
1709         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1710         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1711         .get_module_info = mlx5_get_module_info,
1712         .get_module_eeprom = mlx5_get_module_eeprom,
1713 };
1714
1715 /* Available operations in flow isolated mode. */
1716 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1717         .dev_configure = mlx5_dev_configure,
1718         .dev_start = mlx5_dev_start,
1719         .dev_stop = mlx5_dev_stop,
1720         .dev_set_link_down = mlx5_set_link_down,
1721         .dev_set_link_up = mlx5_set_link_up,
1722         .dev_close = mlx5_dev_close,
1723         .promiscuous_enable = mlx5_promiscuous_enable,
1724         .promiscuous_disable = mlx5_promiscuous_disable,
1725         .allmulticast_enable = mlx5_allmulticast_enable,
1726         .allmulticast_disable = mlx5_allmulticast_disable,
1727         .link_update = mlx5_link_update,
1728         .stats_get = mlx5_stats_get,
1729         .stats_reset = mlx5_stats_reset,
1730         .xstats_get = mlx5_xstats_get,
1731         .xstats_reset = mlx5_xstats_reset,
1732         .xstats_get_names = mlx5_xstats_get_names,
1733         .fw_version_get = mlx5_fw_version_get,
1734         .dev_infos_get = mlx5_dev_infos_get,
1735         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1736         .vlan_filter_set = mlx5_vlan_filter_set,
1737         .rx_queue_setup = mlx5_rx_queue_setup,
1738         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1739         .tx_queue_setup = mlx5_tx_queue_setup,
1740         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1741         .rx_queue_release = mlx5_rx_queue_release,
1742         .tx_queue_release = mlx5_tx_queue_release,
1743         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1744         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1745         .mac_addr_remove = mlx5_mac_addr_remove,
1746         .mac_addr_add = mlx5_mac_addr_add,
1747         .mac_addr_set = mlx5_mac_addr_set,
1748         .set_mc_addr_list = mlx5_set_mc_addr_list,
1749         .mtu_set = mlx5_dev_set_mtu,
1750         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1751         .vlan_offload_set = mlx5_vlan_offload_set,
1752         .filter_ctrl = mlx5_dev_filter_ctrl,
1753         .rx_descriptor_status = mlx5_rx_descriptor_status,
1754         .tx_descriptor_status = mlx5_tx_descriptor_status,
1755         .rxq_info_get = mlx5_rxq_info_get,
1756         .txq_info_get = mlx5_txq_info_get,
1757         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1758         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1759         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1760         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1761         .is_removed = mlx5_is_removed,
1762         .get_module_info = mlx5_get_module_info,
1763         .get_module_eeprom = mlx5_get_module_eeprom,
1764         .hairpin_cap_get = mlx5_hairpin_cap_get,
1765         .mtr_ops_get = mlx5_flow_meter_ops_get,
1766 };
1767
1768 /**
1769  * Verify and store value for device argument.
1770  *
1771  * @param[in] key
1772  *   Key argument to verify.
1773  * @param[in] val
1774  *   Value associated with key.
1775  * @param opaque
1776  *   User data.
1777  *
1778  * @return
1779  *   0 on success, a negative errno value otherwise and rte_errno is set.
1780  */
1781 static int
1782 mlx5_args_check(const char *key, const char *val, void *opaque)
1783 {
1784         struct mlx5_dev_config *config = opaque;
1785         unsigned long tmp;
1786
1787         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1788         if (!strcmp(MLX5_REPRESENTOR, key))
1789                 return 0;
1790         errno = 0;
1791         tmp = strtoul(val, NULL, 0);
1792         if (errno) {
1793                 rte_errno = errno;
1794                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1795                 return -rte_errno;
1796         }
1797         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1798                 config->cqe_comp = !!tmp;
1799         } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1800                 config->cqe_pad = !!tmp;
1801         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1802                 config->hw_padding = !!tmp;
1803         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1804                 config->mprq.enabled = !!tmp;
1805         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1806                 config->mprq.stride_num_n = tmp;
1807         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1808                 config->mprq.stride_size_n = tmp;
1809         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1810                 config->mprq.max_memcpy_len = tmp;
1811         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1812                 config->mprq.min_rxqs_num = tmp;
1813         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1814                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1815                                  " converted to txq_inline_max", key);
1816                 config->txq_inline_max = tmp;
1817         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1818                 config->txq_inline_max = tmp;
1819         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1820                 config->txq_inline_min = tmp;
1821         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1822                 config->txq_inline_mpw = tmp;
1823         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1824                 config->txqs_inline = tmp;
1825         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1826                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1827         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1828                 config->mps = !!tmp;
1829         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1830                 if (tmp != MLX5_TXDB_CACHED &&
1831                     tmp != MLX5_TXDB_NCACHED &&
1832                     tmp != MLX5_TXDB_HEURISTIC) {
1833                         DRV_LOG(ERR, "invalid Tx doorbell "
1834                                      "mapping parameter");
1835                         rte_errno = EINVAL;
1836                         return -rte_errno;
1837                 }
1838                 config->dbnc = tmp;
1839         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1840                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1841         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1842                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1843                                  " converted to txq_inline_mpw", key);
1844                 config->txq_inline_mpw = tmp;
1845         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1846                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1847         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1848                 config->rx_vec_en = !!tmp;
1849         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1850                 config->l3_vxlan_en = !!tmp;
1851         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1852                 config->vf_nl_en = !!tmp;
1853         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1854                 config->dv_esw_en = !!tmp;
1855         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1856                 config->dv_flow_en = !!tmp;
1857         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1858                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1859                     tmp != MLX5_XMETA_MODE_META16 &&
1860                     tmp != MLX5_XMETA_MODE_META32) {
1861                         DRV_LOG(ERR, "invalid extensive "
1862                                      "metadata parameter");
1863                         rte_errno = EINVAL;
1864                         return -rte_errno;
1865                 }
1866                 config->dv_xmeta_en = tmp;
1867         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1868                 config->mr_ext_memseg_en = !!tmp;
1869         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1870                 config->max_dump_files_num = tmp;
1871         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1872                 config->lro.timeout = tmp;
1873         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1874                 DRV_LOG(DEBUG, "class argument is %s.", val);
1875         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1876                 config->log_hp_size = tmp;
1877         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1878                 if (tmp != MLX5_RCM_NONE &&
1879                     tmp != MLX5_RCM_LIGHT &&
1880                     tmp != MLX5_RCM_AGGR) {
1881                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1882                         rte_errno = EINVAL;
1883                         return -rte_errno;
1884                 }
1885                 config->reclaim_mode = tmp;
1886         } else {
1887                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1888                 rte_errno = EINVAL;
1889                 return -rte_errno;
1890         }
1891         return 0;
1892 }
1893
1894 /**
1895  * Parse device parameters.
1896  *
1897  * @param config
1898  *   Pointer to device configuration structure.
1899  * @param devargs
1900  *   Device arguments structure.
1901  *
1902  * @return
1903  *   0 on success, a negative errno value otherwise and rte_errno is set.
1904  */
1905 static int
1906 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1907 {
1908         const char **params = (const char *[]){
1909                 MLX5_RXQ_CQE_COMP_EN,
1910                 MLX5_RXQ_CQE_PAD_EN,
1911                 MLX5_RXQ_PKT_PAD_EN,
1912                 MLX5_RX_MPRQ_EN,
1913                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1914                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1915                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1916                 MLX5_RXQS_MIN_MPRQ,
1917                 MLX5_TXQ_INLINE,
1918                 MLX5_TXQ_INLINE_MIN,
1919                 MLX5_TXQ_INLINE_MAX,
1920                 MLX5_TXQ_INLINE_MPW,
1921                 MLX5_TXQS_MIN_INLINE,
1922                 MLX5_TXQS_MAX_VEC,
1923                 MLX5_TXQ_MPW_EN,
1924                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1925                 MLX5_TXQ_MAX_INLINE_LEN,
1926                 MLX5_TX_DB_NC,
1927                 MLX5_TX_VEC_EN,
1928                 MLX5_RX_VEC_EN,
1929                 MLX5_L3_VXLAN_EN,
1930                 MLX5_VF_NL_EN,
1931                 MLX5_DV_ESW_EN,
1932                 MLX5_DV_FLOW_EN,
1933                 MLX5_DV_XMETA_EN,
1934                 MLX5_MR_EXT_MEMSEG_EN,
1935                 MLX5_REPRESENTOR,
1936                 MLX5_MAX_DUMP_FILES_NUM,
1937                 MLX5_LRO_TIMEOUT_USEC,
1938                 MLX5_CLASS_ARG_NAME,
1939                 MLX5_HP_BUF_SIZE,
1940                 MLX5_RECLAIM_MEM,
1941                 NULL,
1942         };
1943         struct rte_kvargs *kvlist;
1944         int ret = 0;
1945         int i;
1946
1947         if (devargs == NULL)
1948                 return 0;
1949         /* Following UGLY cast is done to pass checkpatch. */
1950         kvlist = rte_kvargs_parse(devargs->args, params);
1951         if (kvlist == NULL) {
1952                 rte_errno = EINVAL;
1953                 return -rte_errno;
1954         }
1955         /* Process parameters. */
1956         for (i = 0; (params[i] != NULL); ++i) {
1957                 if (rte_kvargs_count(kvlist, params[i])) {
1958                         ret = rte_kvargs_process(kvlist, params[i],
1959                                                  mlx5_args_check, config);
1960                         if (ret) {
1961                                 rte_errno = EINVAL;
1962                                 rte_kvargs_free(kvlist);
1963                                 return -rte_errno;
1964                         }
1965                 }
1966         }
1967         rte_kvargs_free(kvlist);
1968         return 0;
1969 }
1970
1971 static struct rte_pci_driver mlx5_driver;
1972
1973 /**
1974  * PMD global initialization.
1975  *
1976  * Independent from individual device, this function initializes global
1977  * per-PMD data structures distinguishing primary and secondary processes.
1978  * Hence, each initialization is called once per a process.
1979  *
1980  * @return
1981  *   0 on success, a negative errno value otherwise and rte_errno is set.
1982  */
1983 static int
1984 mlx5_init_once(void)
1985 {
1986         struct mlx5_shared_data *sd;
1987         struct mlx5_local_data *ld = &mlx5_local_data;
1988         int ret = 0;
1989
1990         if (mlx5_init_shared_data())
1991                 return -rte_errno;
1992         sd = mlx5_shared_data;
1993         MLX5_ASSERT(sd);
1994         rte_spinlock_lock(&sd->lock);
1995         switch (rte_eal_process_type()) {
1996         case RTE_PROC_PRIMARY:
1997                 if (sd->init_done)
1998                         break;
1999                 LIST_INIT(&sd->mem_event_cb_list);
2000                 rte_rwlock_init(&sd->mem_event_rwlock);
2001                 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
2002                                                 mlx5_mr_mem_event_cb, NULL);
2003                 ret = mlx5_mp_init_primary(MLX5_MP_NAME,
2004                                            mlx5_mp_primary_handle);
2005                 if (ret)
2006                         goto out;
2007                 sd->init_done = true;
2008                 break;
2009         case RTE_PROC_SECONDARY:
2010                 if (ld->init_done)
2011                         break;
2012                 ret = mlx5_mp_init_secondary(MLX5_MP_NAME,
2013                                              mlx5_mp_secondary_handle);
2014                 if (ret)
2015                         goto out;
2016                 ++sd->secondary_cnt;
2017                 ld->init_done = true;
2018                 break;
2019         default:
2020                 break;
2021         }
2022 out:
2023         rte_spinlock_unlock(&sd->lock);
2024         return ret;
2025 }
2026
2027 /**
2028  * Configures the minimal amount of data to inline into WQE
2029  * while sending packets.
2030  *
2031  * - the txq_inline_min has the maximal priority, if this
2032  *   key is specified in devargs
2033  * - if DevX is enabled the inline mode is queried from the
2034  *   device (HCA attributes and NIC vport context if needed).
2035  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
2036  *   and none (0 bytes) for other NICs
2037  *
2038  * @param spawn
2039  *   Verbs device parameters (name, port, switch_info) to spawn.
2040  * @param config
2041  *   Device configuration parameters.
2042  */
2043 static void
2044 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
2045                     struct mlx5_dev_config *config)
2046 {
2047         if (config->txq_inline_min != MLX5_ARG_UNSET) {
2048                 /* Application defines size of inlined data explicitly. */
2049                 switch (spawn->pci_dev->id.device_id) {
2050                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2051                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2052                         if (config->txq_inline_min <
2053                                        (int)MLX5_INLINE_HSIZE_L2) {
2054                                 DRV_LOG(DEBUG,
2055                                         "txq_inline_mix aligned to minimal"
2056                                         " ConnectX-4 required value %d",
2057                                         (int)MLX5_INLINE_HSIZE_L2);
2058                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2059                         }
2060                         break;
2061                 }
2062                 goto exit;
2063         }
2064         if (config->hca_attr.eth_net_offloads) {
2065                 /* We have DevX enabled, inline mode queried successfully. */
2066                 switch (config->hca_attr.wqe_inline_mode) {
2067                 case MLX5_CAP_INLINE_MODE_L2:
2068                         /* outer L2 header must be inlined. */
2069                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2070                         goto exit;
2071                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2072                         /* No inline data are required by NIC. */
2073                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2074                         config->hw_vlan_insert =
2075                                 config->hca_attr.wqe_vlan_insert;
2076                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
2077                         goto exit;
2078                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2079                         /* inline mode is defined by NIC vport context. */
2080                         if (!config->hca_attr.eth_virt)
2081                                 break;
2082                         switch (config->hca_attr.vport_inline_mode) {
2083                         case MLX5_INLINE_MODE_NONE:
2084                                 config->txq_inline_min =
2085                                         MLX5_INLINE_HSIZE_NONE;
2086                                 goto exit;
2087                         case MLX5_INLINE_MODE_L2:
2088                                 config->txq_inline_min =
2089                                         MLX5_INLINE_HSIZE_L2;
2090                                 goto exit;
2091                         case MLX5_INLINE_MODE_IP:
2092                                 config->txq_inline_min =
2093                                         MLX5_INLINE_HSIZE_L3;
2094                                 goto exit;
2095                         case MLX5_INLINE_MODE_TCP_UDP:
2096                                 config->txq_inline_min =
2097                                         MLX5_INLINE_HSIZE_L4;
2098                                 goto exit;
2099                         case MLX5_INLINE_MODE_INNER_L2:
2100                                 config->txq_inline_min =
2101                                         MLX5_INLINE_HSIZE_INNER_L2;
2102                                 goto exit;
2103                         case MLX5_INLINE_MODE_INNER_IP:
2104                                 config->txq_inline_min =
2105                                         MLX5_INLINE_HSIZE_INNER_L3;
2106                                 goto exit;
2107                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
2108                                 config->txq_inline_min =
2109                                         MLX5_INLINE_HSIZE_INNER_L4;
2110                                 goto exit;
2111                         }
2112                 }
2113         }
2114         /*
2115          * We get here if we are unable to deduce
2116          * inline data size with DevX. Try PCI ID
2117          * to determine old NICs.
2118          */
2119         switch (spawn->pci_dev->id.device_id) {
2120         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2121         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2122         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
2123         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
2124                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2125                 config->hw_vlan_insert = 0;
2126                 break;
2127         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
2128         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
2129         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
2130         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
2131                 /*
2132                  * These NICs support VLAN insertion from WQE and
2133                  * report the wqe_vlan_insert flag. But there is the bug
2134                  * and PFC control may be broken, so disable feature.
2135                  */
2136                 config->hw_vlan_insert = 0;
2137                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2138                 break;
2139         default:
2140                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2141                 break;
2142         }
2143 exit:
2144         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
2145 }
2146
2147 /**
2148  * Configures the metadata mask fields in the shared context.
2149  *
2150  * @param [in] dev
2151  *   Pointer to Ethernet device.
2152  */
2153 static void
2154 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
2155 {
2156         struct mlx5_priv *priv = dev->data->dev_private;
2157         struct mlx5_dev_ctx_shared *sh = priv->sh;
2158         uint32_t meta, mark, reg_c0;
2159
2160         reg_c0 = ~priv->vport_meta_mask;
2161         switch (priv->config.dv_xmeta_en) {
2162         case MLX5_XMETA_MODE_LEGACY:
2163                 meta = UINT32_MAX;
2164                 mark = MLX5_FLOW_MARK_MASK;
2165                 break;
2166         case MLX5_XMETA_MODE_META16:
2167                 meta = reg_c0 >> rte_bsf32(reg_c0);
2168                 mark = MLX5_FLOW_MARK_MASK;
2169                 break;
2170         case MLX5_XMETA_MODE_META32:
2171                 meta = UINT32_MAX;
2172                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2173                 break;
2174         default:
2175                 meta = 0;
2176                 mark = 0;
2177                 MLX5_ASSERT(false);
2178                 break;
2179         }
2180         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2181                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
2182                                  sh->dv_mark_mask, mark);
2183         else
2184                 sh->dv_mark_mask = mark;
2185         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2186                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
2187                                  sh->dv_meta_mask, meta);
2188         else
2189                 sh->dv_meta_mask = meta;
2190         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2191                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
2192                                  sh->dv_meta_mask, reg_c0);
2193         else
2194                 sh->dv_regc0_mask = reg_c0;
2195         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2196         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2197         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2198         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2199 }
2200
2201 /**
2202  * Allocate page of door-bells and register it using DevX API.
2203  *
2204  * @param [in] dev
2205  *   Pointer to Ethernet device.
2206  *
2207  * @return
2208  *   Pointer to new page on success, NULL otherwise.
2209  */
2210 static struct mlx5_devx_dbr_page *
2211 mlx5_alloc_dbr_page(struct rte_eth_dev *dev)
2212 {
2213         struct mlx5_priv *priv = dev->data->dev_private;
2214         struct mlx5_devx_dbr_page *page;
2215
2216         /* Allocate space for door-bell page and management data. */
2217         page = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_devx_dbr_page),
2218                                  RTE_CACHE_LINE_SIZE, dev->device->numa_node);
2219         if (!page) {
2220                 DRV_LOG(ERR, "port %u cannot allocate dbr page",
2221                         dev->data->port_id);
2222                 return NULL;
2223         }
2224         /* Register allocated memory. */
2225         page->umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, page->dbrs,
2226                                               MLX5_DBR_PAGE_SIZE, 0);
2227         if (!page->umem) {
2228                 DRV_LOG(ERR, "port %u cannot umem reg dbr page",
2229                         dev->data->port_id);
2230                 rte_free(page);
2231                 return NULL;
2232         }
2233         return page;
2234 }
2235
2236 /**
2237  * Find the next available door-bell, allocate new page if needed.
2238  *
2239  * @param [in] dev
2240  *   Pointer to Ethernet device.
2241  * @param [out] dbr_page
2242  *   Door-bell page containing the page data.
2243  *
2244  * @return
2245  *   Door-bell address offset on success, a negative error value otherwise.
2246  */
2247 int64_t
2248 mlx5_get_dbr(struct rte_eth_dev *dev, struct mlx5_devx_dbr_page **dbr_page)
2249 {
2250         struct mlx5_priv *priv = dev->data->dev_private;
2251         struct mlx5_devx_dbr_page *page = NULL;
2252         uint32_t i, j;
2253
2254         LIST_FOREACH(page, &priv->dbrpgs, next)
2255                 if (page->dbr_count < MLX5_DBR_PER_PAGE)
2256                         break;
2257         if (!page) { /* No page with free door-bell exists. */
2258                 page = mlx5_alloc_dbr_page(dev);
2259                 if (!page) /* Failed to allocate new page. */
2260                         return (-1);
2261                 LIST_INSERT_HEAD(&priv->dbrpgs, page, next);
2262         }
2263         /* Loop to find bitmap part with clear bit. */
2264         for (i = 0;
2265              i < MLX5_DBR_BITMAP_SIZE && page->dbr_bitmap[i] == UINT64_MAX;
2266              i++)
2267                 ; /* Empty. */
2268         /* Find the first clear bit. */
2269         MLX5_ASSERT(i < MLX5_DBR_BITMAP_SIZE);
2270         j = rte_bsf64(~page->dbr_bitmap[i]);
2271         page->dbr_bitmap[i] |= (UINT64_C(1) << j);
2272         page->dbr_count++;
2273         *dbr_page = page;
2274         return (((i * 64) + j) * sizeof(uint64_t));
2275 }
2276
2277 /**
2278  * Release a door-bell record.
2279  *
2280  * @param [in] dev
2281  *   Pointer to Ethernet device.
2282  * @param [in] umem_id
2283  *   UMEM ID of page containing the door-bell record to release.
2284  * @param [in] offset
2285  *   Offset of door-bell record in page.
2286  *
2287  * @return
2288  *   0 on success, a negative error value otherwise.
2289  */
2290 int32_t
2291 mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id, uint64_t offset)
2292 {
2293         struct mlx5_priv *priv = dev->data->dev_private;
2294         struct mlx5_devx_dbr_page *page = NULL;
2295         int ret = 0;
2296
2297         LIST_FOREACH(page, &priv->dbrpgs, next)
2298                 /* Find the page this address belongs to. */
2299                 if (page->umem->umem_id == umem_id)
2300                         break;
2301         if (!page)
2302                 return -EINVAL;
2303         page->dbr_count--;
2304         if (!page->dbr_count) {
2305                 /* Page not used, free it and remove from list. */
2306                 LIST_REMOVE(page, next);
2307                 if (page->umem)
2308                         ret = -mlx5_glue->devx_umem_dereg(page->umem);
2309                 rte_free(page);
2310         } else {
2311                 /* Mark in bitmap that this door-bell is not in use. */
2312                 offset /= MLX5_DBR_SIZE;
2313                 int i = offset / 64;
2314                 int j = offset % 64;
2315
2316                 page->dbr_bitmap[i] &= ~(UINT64_C(1) << j);
2317         }
2318         return ret;
2319 }
2320
2321 int
2322 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2323 {
2324         static const char *const dynf_names[] = {
2325                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2326                 RTE_MBUF_DYNFLAG_METADATA_NAME
2327         };
2328         unsigned int i;
2329
2330         if (n < RTE_DIM(dynf_names))
2331                 return -ENOMEM;
2332         for (i = 0; i < RTE_DIM(dynf_names); i++) {
2333                 if (names[i] == NULL)
2334                         return -EINVAL;
2335                 strcpy(names[i], dynf_names[i]);
2336         }
2337         return RTE_DIM(dynf_names);
2338 }
2339
2340 /**
2341  * Check sibling device configurations.
2342  *
2343  * Sibling devices sharing the Infiniband device context
2344  * should have compatible configurations. This regards
2345  * representors and bonding slaves.
2346  *
2347  * @param priv
2348  *   Private device descriptor.
2349  * @param config
2350  *   Configuration of the device is going to be created.
2351  *
2352  * @return
2353  *   0 on success, EINVAL otherwise
2354  */
2355 static int
2356 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2357                               struct mlx5_dev_config *config)
2358 {
2359         struct mlx5_dev_ctx_shared *sh = priv->sh;
2360         struct mlx5_dev_config *sh_conf = NULL;
2361         uint16_t port_id;
2362
2363         MLX5_ASSERT(sh);
2364         /* Nothing to compare for the single/first device. */
2365         if (sh->refcnt == 1)
2366                 return 0;
2367         /* Find the device with shared context. */
2368         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2369                 struct mlx5_priv *opriv =
2370                         rte_eth_devices[port_id].data->dev_private;
2371
2372                 if (opriv && opriv != priv && opriv->sh == sh) {
2373                         sh_conf = &opriv->config;
2374                         break;
2375                 }
2376         }
2377         if (!sh_conf)
2378                 return 0;
2379         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2380                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2381                              " for shared %s context", sh->ibdev_name);
2382                 rte_errno = EINVAL;
2383                 return rte_errno;
2384         }
2385         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2386                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2387                              " for shared %s context", sh->ibdev_name);
2388                 rte_errno = EINVAL;
2389                 return rte_errno;
2390         }
2391         return 0;
2392 }
2393 /**
2394  * Spawn an Ethernet device from Verbs information.
2395  *
2396  * @param dpdk_dev
2397  *   Backing DPDK device.
2398  * @param spawn
2399  *   Verbs device parameters (name, port, switch_info) to spawn.
2400  * @param config
2401  *   Device configuration parameters.
2402  *
2403  * @return
2404  *   A valid Ethernet device object on success, NULL otherwise and rte_errno
2405  *   is set. The following errors are defined:
2406  *
2407  *   EBUSY: device is not supposed to be spawned.
2408  *   EEXIST: device is already spawned
2409  */
2410 static struct rte_eth_dev *
2411 mlx5_dev_spawn(struct rte_device *dpdk_dev,
2412                struct mlx5_dev_spawn_data *spawn,
2413                struct mlx5_dev_config config)
2414 {
2415         const struct mlx5_switch_info *switch_info = &spawn->info;
2416         struct mlx5_dev_ctx_shared *sh = NULL;
2417         struct ibv_port_attr port_attr;
2418         struct mlx5dv_context dv_attr = { .comp_mask = 0 };
2419         struct rte_eth_dev *eth_dev = NULL;
2420         struct mlx5_priv *priv = NULL;
2421         int err = 0;
2422         unsigned int hw_padding = 0;
2423         unsigned int mps;
2424         unsigned int cqe_comp;
2425         unsigned int cqe_pad = 0;
2426         unsigned int tunnel_en = 0;
2427         unsigned int mpls_en = 0;
2428         unsigned int swp = 0;
2429         unsigned int mprq = 0;
2430         unsigned int mprq_min_stride_size_n = 0;
2431         unsigned int mprq_max_stride_size_n = 0;
2432         unsigned int mprq_min_stride_num_n = 0;
2433         unsigned int mprq_max_stride_num_n = 0;
2434         struct rte_ether_addr mac;
2435         char name[RTE_ETH_NAME_MAX_LEN];
2436         int own_domain_id = 0;
2437         uint16_t port_id;
2438         unsigned int i;
2439 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
2440         struct mlx5dv_devx_port devx_port = { .comp_mask = 0 };
2441 #endif
2442
2443         /* Determine if this port representor is supposed to be spawned. */
2444         if (switch_info->representor && dpdk_dev->devargs) {
2445                 struct rte_eth_devargs eth_da;
2446
2447                 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, &eth_da);
2448                 if (err) {
2449                         rte_errno = -err;
2450                         DRV_LOG(ERR, "failed to process device arguments: %s",
2451                                 strerror(rte_errno));
2452                         return NULL;
2453                 }
2454                 for (i = 0; i < eth_da.nb_representor_ports; ++i)
2455                         if (eth_da.representor_ports[i] ==
2456                             (uint16_t)switch_info->port_name)
2457                                 break;
2458                 if (i == eth_da.nb_representor_ports) {
2459                         rte_errno = EBUSY;
2460                         return NULL;
2461                 }
2462         }
2463         /* Build device name. */
2464         if (spawn->pf_bond <  0) {
2465                 /* Single device. */
2466                 if (!switch_info->representor)
2467                         strlcpy(name, dpdk_dev->name, sizeof(name));
2468                 else
2469                         snprintf(name, sizeof(name), "%s_representor_%u",
2470                                  dpdk_dev->name, switch_info->port_name);
2471         } else {
2472                 /* Bonding device. */
2473                 if (!switch_info->representor)
2474                         snprintf(name, sizeof(name), "%s_%s",
2475                                  dpdk_dev->name, spawn->ibv_dev->name);
2476                 else
2477                         snprintf(name, sizeof(name), "%s_%s_representor_%u",
2478                                  dpdk_dev->name, spawn->ibv_dev->name,
2479                                  switch_info->port_name);
2480         }
2481         /* check if the device is already spawned */
2482         if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
2483                 rte_errno = EEXIST;
2484                 return NULL;
2485         }
2486         DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
2487         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
2488                 struct mlx5_mp_id mp_id;
2489
2490                 eth_dev = rte_eth_dev_attach_secondary(name);
2491                 if (eth_dev == NULL) {
2492                         DRV_LOG(ERR, "can not attach rte ethdev");
2493                         rte_errno = ENOMEM;
2494                         return NULL;
2495                 }
2496                 eth_dev->device = dpdk_dev;
2497                 eth_dev->dev_ops = &mlx5_dev_sec_ops;
2498                 err = mlx5_proc_priv_init(eth_dev);
2499                 if (err)
2500                         return NULL;
2501                 mp_id.port_id = eth_dev->data->port_id;
2502                 strlcpy(mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);
2503                 /* Receive command fd from primary process */
2504                 err = mlx5_mp_req_verbs_cmd_fd(&mp_id);
2505                 if (err < 0)
2506                         goto err_secondary;
2507                 /* Remap UAR for Tx queues. */
2508                 err = mlx5_tx_uar_init_secondary(eth_dev, err);
2509                 if (err)
2510                         goto err_secondary;
2511                 /*
2512                  * Ethdev pointer is still required as input since
2513                  * the primary device is not accessible from the
2514                  * secondary process.
2515                  */
2516                 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev);
2517                 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev);
2518                 return eth_dev;
2519 err_secondary:
2520                 mlx5_dev_close(eth_dev);
2521                 return NULL;
2522         }
2523         /*
2524          * Some parameters ("tx_db_nc" in particularly) are needed in
2525          * advance to create dv/verbs device context. We proceed the
2526          * devargs here to get ones, and later proceed devargs again
2527          * to override some hardware settings.
2528          */
2529         err = mlx5_args(&config, dpdk_dev->devargs);
2530         if (err) {
2531                 err = rte_errno;
2532                 DRV_LOG(ERR, "failed to process device arguments: %s",
2533                         strerror(rte_errno));
2534                 goto error;
2535         }
2536         sh = mlx5_alloc_shared_ibctx(spawn, &config);
2537         if (!sh)
2538                 return NULL;
2539         config.devx = sh->devx;
2540 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR
2541         config.dest_tir = 1;
2542 #endif
2543 #ifdef HAVE_IBV_MLX5_MOD_SWP
2544         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
2545 #endif
2546         /*
2547          * Multi-packet send is supported by ConnectX-4 Lx PF as well
2548          * as all ConnectX-5 devices.
2549          */
2550 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2551         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
2552 #endif
2553 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
2554         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
2555 #endif
2556         mlx5_glue->dv_query_device(sh->ctx, &dv_attr);
2557         if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
2558                 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
2559                         DRV_LOG(DEBUG, "enhanced MPW is supported");
2560                         mps = MLX5_MPW_ENHANCED;
2561                 } else {
2562                         DRV_LOG(DEBUG, "MPW is supported");
2563                         mps = MLX5_MPW;
2564                 }
2565         } else {
2566                 DRV_LOG(DEBUG, "MPW isn't supported");
2567                 mps = MLX5_MPW_DISABLED;
2568         }
2569 #ifdef HAVE_IBV_MLX5_MOD_SWP
2570         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
2571                 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
2572         DRV_LOG(DEBUG, "SWP support: %u", swp);
2573 #endif
2574         config.swp = !!swp;
2575 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
2576         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
2577                 struct mlx5dv_striding_rq_caps mprq_caps =
2578                         dv_attr.striding_rq_caps;
2579
2580                 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
2581                         mprq_caps.min_single_stride_log_num_of_bytes);
2582                 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
2583                         mprq_caps.max_single_stride_log_num_of_bytes);
2584                 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
2585                         mprq_caps.min_single_wqe_log_num_of_strides);
2586                 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
2587                         mprq_caps.max_single_wqe_log_num_of_strides);
2588                 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
2589                         mprq_caps.supported_qpts);
2590                 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
2591                 mprq = 1;
2592                 mprq_min_stride_size_n =
2593                         mprq_caps.min_single_stride_log_num_of_bytes;
2594                 mprq_max_stride_size_n =
2595                         mprq_caps.max_single_stride_log_num_of_bytes;
2596                 mprq_min_stride_num_n =
2597                         mprq_caps.min_single_wqe_log_num_of_strides;
2598                 mprq_max_stride_num_n =
2599                         mprq_caps.max_single_wqe_log_num_of_strides;
2600         }
2601 #endif
2602         if (RTE_CACHE_LINE_SIZE == 128 &&
2603             !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
2604                 cqe_comp = 0;
2605         else
2606                 cqe_comp = 1;
2607         config.cqe_comp = cqe_comp;
2608 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
2609         /* Whether device supports 128B Rx CQE padding. */
2610         cqe_pad = RTE_CACHE_LINE_SIZE == 128 &&
2611                   (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD);
2612 #endif
2613 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2614         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
2615                 tunnel_en = ((dv_attr.tunnel_offloads_caps &
2616                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
2617                              (dv_attr.tunnel_offloads_caps &
2618                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) &&
2619                              (dv_attr.tunnel_offloads_caps &
2620                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE));
2621         }
2622         DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
2623                 tunnel_en ? "" : "not ");
2624 #else
2625         DRV_LOG(WARNING,
2626                 "tunnel offloading disabled due to old OFED/rdma-core version");
2627 #endif
2628         config.tunnel_en = tunnel_en;
2629 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
2630         mpls_en = ((dv_attr.tunnel_offloads_caps &
2631                     MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
2632                    (dv_attr.tunnel_offloads_caps &
2633                     MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
2634         DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
2635                 mpls_en ? "" : "not ");
2636 #else
2637         DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
2638                 " old OFED/rdma-core version or firmware configuration");
2639 #endif
2640         config.mpls_en = mpls_en;
2641         /* Check port status. */
2642         err = mlx5_glue->query_port(sh->ctx, spawn->ibv_port, &port_attr);
2643         if (err) {
2644                 DRV_LOG(ERR, "port query failed: %s", strerror(err));
2645                 goto error;
2646         }
2647         if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
2648                 DRV_LOG(ERR, "port is not configured in Ethernet mode");
2649                 err = EINVAL;
2650                 goto error;
2651         }
2652         if (port_attr.state != IBV_PORT_ACTIVE)
2653                 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)",
2654                         mlx5_glue->port_state_str(port_attr.state),
2655                         port_attr.state);
2656         /* Allocate private eth device data. */
2657         priv = rte_zmalloc("ethdev private structure",
2658                            sizeof(*priv),
2659                            RTE_CACHE_LINE_SIZE);
2660         if (priv == NULL) {
2661                 DRV_LOG(ERR, "priv allocation failure");
2662                 err = ENOMEM;
2663                 goto error;
2664         }
2665         priv->sh = sh;
2666         priv->ibv_port = spawn->ibv_port;
2667         priv->pci_dev = spawn->pci_dev;
2668         priv->mtu = RTE_ETHER_MTU;
2669         priv->mp_id.port_id = port_id;
2670         strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);
2671 #ifndef RTE_ARCH_64
2672         /* Initialize UAR access locks for 32bit implementations. */
2673         rte_spinlock_init(&priv->uar_lock_cq);
2674         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
2675                 rte_spinlock_init(&priv->uar_lock[i]);
2676 #endif
2677         /* Some internal functions rely on Netlink sockets, open them now. */
2678         priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA);
2679         priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE);
2680         priv->representor = !!switch_info->representor;
2681         priv->master = !!switch_info->master;
2682         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
2683         priv->vport_meta_tag = 0;
2684         priv->vport_meta_mask = 0;
2685         priv->pf_bond = spawn->pf_bond;
2686 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
2687         /*
2688          * The DevX port query API is implemented. E-Switch may use
2689          * either vport or reg_c[0] metadata register to match on
2690          * vport index. The engaged part of metadata register is
2691          * defined by mask.
2692          */
2693         if (switch_info->representor || switch_info->master) {
2694                 devx_port.comp_mask = MLX5DV_DEVX_PORT_VPORT |
2695                                       MLX5DV_DEVX_PORT_MATCH_REG_C_0;
2696                 err = mlx5_glue->devx_port_query(sh->ctx, spawn->ibv_port,
2697                                                  &devx_port);
2698                 if (err) {
2699                         DRV_LOG(WARNING,
2700                                 "can't query devx port %d on device %s",
2701                                 spawn->ibv_port, spawn->ibv_dev->name);
2702                         devx_port.comp_mask = 0;
2703                 }
2704         }
2705         if (devx_port.comp_mask & MLX5DV_DEVX_PORT_MATCH_REG_C_0) {
2706                 priv->vport_meta_tag = devx_port.reg_c_0.value;
2707                 priv->vport_meta_mask = devx_port.reg_c_0.mask;
2708                 if (!priv->vport_meta_mask) {
2709                         DRV_LOG(ERR, "vport zero mask for port %d"
2710                                      " on bonding device %s",
2711                                      spawn->ibv_port, spawn->ibv_dev->name);
2712                         err = ENOTSUP;
2713                         goto error;
2714                 }
2715                 if (priv->vport_meta_tag & ~priv->vport_meta_mask) {
2716                         DRV_LOG(ERR, "invalid vport tag for port %d"
2717                                      " on bonding device %s",
2718                                      spawn->ibv_port, spawn->ibv_dev->name);
2719                         err = ENOTSUP;
2720                         goto error;
2721                 }
2722         }
2723         if (devx_port.comp_mask & MLX5DV_DEVX_PORT_VPORT) {
2724                 priv->vport_id = devx_port.vport_num;
2725         } else if (spawn->pf_bond >= 0) {
2726                 DRV_LOG(ERR, "can't deduce vport index for port %d"
2727                              " on bonding device %s",
2728                              spawn->ibv_port, spawn->ibv_dev->name);
2729                 err = ENOTSUP;
2730                 goto error;
2731         } else {
2732                 /* Suppose vport index in compatible way. */
2733                 priv->vport_id = switch_info->representor ?
2734                                  switch_info->port_name + 1 : -1;
2735         }
2736 #else
2737         /*
2738          * Kernel/rdma_core support single E-Switch per PF configurations
2739          * only and vport_id field contains the vport index for
2740          * associated VF, which is deduced from representor port name.
2741          * For example, let's have the IB device port 10, it has
2742          * attached network device eth0, which has port name attribute
2743          * pf0vf2, we can deduce the VF number as 2, and set vport index
2744          * as 3 (2+1). This assigning schema should be changed if the
2745          * multiple E-Switch instances per PF configurations or/and PCI
2746          * subfunctions are added.
2747          */
2748         priv->vport_id = switch_info->representor ?
2749                          switch_info->port_name + 1 : -1;
2750 #endif
2751         /* representor_id field keeps the unmodified VF index. */
2752         priv->representor_id = switch_info->representor ?
2753                                switch_info->port_name : -1;
2754         /*
2755          * Look for sibling devices in order to reuse their switch domain
2756          * if any, otherwise allocate one.
2757          */
2758         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2759                 const struct mlx5_priv *opriv =
2760                         rte_eth_devices[port_id].data->dev_private;
2761
2762                 if (!opriv ||
2763                     opriv->sh != priv->sh ||
2764                         opriv->domain_id ==
2765                         RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
2766                         continue;
2767                 priv->domain_id = opriv->domain_id;
2768                 break;
2769         }
2770         if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
2771                 err = rte_eth_switch_domain_alloc(&priv->domain_id);
2772                 if (err) {
2773                         err = rte_errno;
2774                         DRV_LOG(ERR, "unable to allocate switch domain: %s",
2775                                 strerror(rte_errno));
2776                         goto error;
2777                 }
2778                 own_domain_id = 1;
2779         }
2780         /* Override some values set by hardware configuration. */
2781         mlx5_args(&config, dpdk_dev->devargs);
2782         err = mlx5_dev_check_sibling_config(priv, &config);
2783         if (err)
2784                 goto error;
2785         config.hw_csum = !!(sh->device_attr.device_cap_flags_ex &
2786                             IBV_DEVICE_RAW_IP_CSUM);
2787         DRV_LOG(DEBUG, "checksum offloading is %ssupported",
2788                 (config.hw_csum ? "" : "not "));
2789 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \
2790         !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
2791         DRV_LOG(DEBUG, "counters are not supported");
2792 #endif
2793 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR)
2794         if (config.dv_flow_en) {
2795                 DRV_LOG(WARNING, "DV flow is not supported");
2796                 config.dv_flow_en = 0;
2797         }
2798 #endif
2799         config.ind_table_max_size =
2800                 sh->device_attr.rss_caps.max_rwq_indirection_table_size;
2801         /*
2802          * Remove this check once DPDK supports larger/variable
2803          * indirection tables.
2804          */
2805         if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
2806                 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
2807         DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
2808                 config.ind_table_max_size);
2809         config.hw_vlan_strip = !!(sh->device_attr.raw_packet_caps &
2810                                   IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
2811         DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
2812                 (config.hw_vlan_strip ? "" : "not "));
2813         config.hw_fcs_strip = !!(sh->device_attr.raw_packet_caps &
2814                                  IBV_RAW_PACKET_CAP_SCATTER_FCS);
2815         DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
2816                 (config.hw_fcs_strip ? "" : "not "));
2817 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
2818         hw_padding = !!sh->device_attr.rx_pad_end_addr_align;
2819 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
2820         hw_padding = !!(sh->device_attr.device_cap_flags_ex &
2821                         IBV_DEVICE_PCI_WRITE_END_PADDING);
2822 #endif
2823         if (config.hw_padding && !hw_padding) {
2824                 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
2825                 config.hw_padding = 0;
2826         } else if (config.hw_padding) {
2827                 DRV_LOG(DEBUG, "Rx end alignment padding is enabled");
2828         }
2829         config.tso = (sh->device_attr.tso_caps.max_tso > 0 &&
2830                       (sh->device_attr.tso_caps.supported_qpts &
2831                        (1 << IBV_QPT_RAW_PACKET)));
2832         if (config.tso)
2833                 config.tso_max_payload_sz = sh->device_attr.tso_caps.max_tso;
2834         /*
2835          * MPW is disabled by default, while the Enhanced MPW is enabled
2836          * by default.
2837          */
2838         if (config.mps == MLX5_ARG_UNSET)
2839                 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED :
2840                                                           MLX5_MPW_DISABLED;
2841         else
2842                 config.mps = config.mps ? mps : MLX5_MPW_DISABLED;
2843         DRV_LOG(INFO, "%sMPS is %s",
2844                 config.mps == MLX5_MPW_ENHANCED ? "enhanced " :
2845                 config.mps == MLX5_MPW ? "legacy " : "",
2846                 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
2847         if (config.cqe_comp && !cqe_comp) {
2848                 DRV_LOG(WARNING, "Rx CQE compression isn't supported");
2849                 config.cqe_comp = 0;
2850         }
2851         if (config.cqe_pad && !cqe_pad) {
2852                 DRV_LOG(WARNING, "Rx CQE padding isn't supported");
2853                 config.cqe_pad = 0;
2854         } else if (config.cqe_pad) {
2855                 DRV_LOG(INFO, "Rx CQE padding is enabled");
2856         }
2857         if (config.devx) {
2858                 priv->counter_fallback = 0;
2859                 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config.hca_attr);
2860                 if (err) {
2861                         err = -err;
2862                         goto error;
2863                 }
2864                 if (!config.hca_attr.flow_counters_dump)
2865                         priv->counter_fallback = 1;
2866 #ifndef HAVE_IBV_DEVX_ASYNC
2867                 priv->counter_fallback = 1;
2868 #endif
2869                 if (priv->counter_fallback)
2870                         DRV_LOG(INFO, "Use fall-back DV counter management");
2871                 /* Check for LRO support. */
2872                 if (config.dest_tir && config.hca_attr.lro_cap &&
2873                     config.dv_flow_en) {
2874                         /* TBD check tunnel lro caps. */
2875                         config.lro.supported = config.hca_attr.lro_cap;
2876                         DRV_LOG(DEBUG, "Device supports LRO");
2877                         /*
2878                          * If LRO timeout is not configured by application,
2879                          * use the minimal supported value.
2880                          */
2881                         if (!config.lro.timeout)
2882                                 config.lro.timeout =
2883                                 config.hca_attr.lro_timer_supported_periods[0];
2884                         DRV_LOG(DEBUG, "LRO session timeout set to %d usec",
2885                                 config.lro.timeout);
2886                 }
2887 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER)
2888                 if (config.hca_attr.qos.sup && config.hca_attr.qos.srtcm_sup &&
2889                     config.dv_flow_en) {
2890                         uint8_t reg_c_mask =
2891                                 config.hca_attr.qos.flow_meter_reg_c_ids;
2892                         /*
2893                          * Meter needs two REG_C's for color match and pre-sfx
2894                          * flow match. Here get the REG_C for color match.
2895                          * REG_C_0 and REG_C_1 is reserved for metadata feature.
2896                          */
2897                         reg_c_mask &= 0xfc;
2898                         if (__builtin_popcount(reg_c_mask) < 1) {
2899                                 priv->mtr_en = 0;
2900                                 DRV_LOG(WARNING, "No available register for"
2901                                         " meter.");
2902                         } else {
2903                                 priv->mtr_color_reg = ffs(reg_c_mask) - 1 +
2904                                                       REG_C_0;
2905                                 priv->mtr_en = 1;
2906                                 priv->mtr_reg_share =
2907                                       config.hca_attr.qos.flow_meter_reg_share;
2908                                 DRV_LOG(DEBUG, "The REG_C meter uses is %d",
2909                                         priv->mtr_color_reg);
2910                         }
2911                 }
2912 #endif
2913         }
2914         if (config.mprq.enabled && mprq) {
2915                 if (config.mprq.stride_num_n &&
2916                     (config.mprq.stride_num_n > mprq_max_stride_num_n ||
2917                      config.mprq.stride_num_n < mprq_min_stride_num_n)) {
2918                         config.mprq.stride_num_n =
2919                                 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
2920                                                 mprq_min_stride_num_n),
2921                                         mprq_max_stride_num_n);
2922                         DRV_LOG(WARNING,
2923                                 "the number of strides"
2924                                 " for Multi-Packet RQ is out of range,"
2925                                 " setting default value (%u)",
2926                                 1 << config.mprq.stride_num_n);
2927                 }
2928                 if (config.mprq.stride_size_n &&
2929                     (config.mprq.stride_size_n > mprq_max_stride_size_n ||
2930                      config.mprq.stride_size_n < mprq_min_stride_size_n)) {
2931                         config.mprq.stride_size_n =
2932                                 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N,
2933                                                 mprq_min_stride_size_n),
2934                                         mprq_max_stride_size_n);
2935                         DRV_LOG(WARNING,
2936                                 "the size of a stride"
2937                                 " for Multi-Packet RQ is out of range,"
2938                                 " setting default value (%u)",
2939                                 1 << config.mprq.stride_size_n);
2940                 }
2941                 config.mprq.min_stride_size_n = mprq_min_stride_size_n;
2942                 config.mprq.max_stride_size_n = mprq_max_stride_size_n;
2943         } else if (config.mprq.enabled && !mprq) {
2944                 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
2945                 config.mprq.enabled = 0;
2946         }
2947         if (config.max_dump_files_num == 0)
2948                 config.max_dump_files_num = 128;
2949         eth_dev = rte_eth_dev_allocate(name);
2950         if (eth_dev == NULL) {
2951                 DRV_LOG(ERR, "can not allocate rte ethdev");
2952                 err = ENOMEM;
2953                 goto error;
2954         }
2955         /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */
2956         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2957         if (priv->representor) {
2958                 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
2959                 eth_dev->data->representor_id = priv->representor_id;
2960         }
2961         /*
2962          * Store associated network device interface index. This index
2963          * is permanent throughout the lifetime of device. So, we may store
2964          * the ifindex here and use the cached value further.
2965          */
2966         MLX5_ASSERT(spawn->ifindex);
2967         priv->if_index = spawn->ifindex;
2968         eth_dev->data->dev_private = priv;
2969         priv->dev_data = eth_dev->data;
2970         eth_dev->data->mac_addrs = priv->mac;
2971         eth_dev->device = dpdk_dev;
2972         /* Configure the first MAC address by default. */
2973         if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
2974                 DRV_LOG(ERR,
2975                         "port %u cannot get MAC address, is mlx5_en"
2976                         " loaded? (errno: %s)",
2977                         eth_dev->data->port_id, strerror(rte_errno));
2978                 err = ENODEV;
2979                 goto error;
2980         }
2981         DRV_LOG(INFO,
2982                 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
2983                 eth_dev->data->port_id,
2984                 mac.addr_bytes[0], mac.addr_bytes[1],
2985                 mac.addr_bytes[2], mac.addr_bytes[3],
2986                 mac.addr_bytes[4], mac.addr_bytes[5]);
2987 #ifdef RTE_LIBRTE_MLX5_DEBUG
2988         {
2989                 char ifname[IF_NAMESIZE];
2990
2991                 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
2992                         DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
2993                                 eth_dev->data->port_id, ifname);
2994                 else
2995                         DRV_LOG(DEBUG, "port %u ifname is unknown",
2996                                 eth_dev->data->port_id);
2997         }
2998 #endif
2999         /* Get actual MTU if possible. */
3000         err = mlx5_get_mtu(eth_dev, &priv->mtu);
3001         if (err) {
3002                 err = rte_errno;
3003                 goto error;
3004         }
3005         DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
3006                 priv->mtu);
3007         /* Initialize burst functions to prevent crashes before link-up. */
3008         eth_dev->rx_pkt_burst = removed_rx_burst;
3009         eth_dev->tx_pkt_burst = removed_tx_burst;
3010         eth_dev->dev_ops = &mlx5_dev_ops;
3011         /* Register MAC address. */
3012         claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
3013         if (config.vf && config.vf_nl_en)
3014                 mlx5_nl_mac_addr_sync(priv->nl_socket_route,
3015                                       mlx5_ifindex(eth_dev),
3016                                       eth_dev->data->mac_addrs,
3017                                       MLX5_MAX_MAC_ADDRESSES);
3018         priv->flows = 0;
3019         priv->ctrl_flows = 0;
3020         TAILQ_INIT(&priv->flow_meters);
3021         TAILQ_INIT(&priv->flow_meter_profiles);
3022         /* Hint libmlx5 to use PMD allocator for data plane resources */
3023         struct mlx5dv_ctx_allocators alctr = {
3024                 .alloc = &mlx5_alloc_verbs_buf,
3025                 .free = &mlx5_free_verbs_buf,
3026                 .data = priv,
3027         };
3028         mlx5_glue->dv_set_context_attr(sh->ctx,
3029                                        MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
3030                                        (void *)((uintptr_t)&alctr));
3031         /* Bring Ethernet device up. */
3032         DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
3033                 eth_dev->data->port_id);
3034         mlx5_set_link_up(eth_dev);
3035         /*
3036          * Even though the interrupt handler is not installed yet,
3037          * interrupts will still trigger on the async_fd from
3038          * Verbs context returned by ibv_open_device().
3039          */
3040         mlx5_link_update(eth_dev, 0);
3041 #ifdef HAVE_MLX5DV_DR_ESWITCH
3042         if (!(config.hca_attr.eswitch_manager && config.dv_flow_en &&
3043               (switch_info->representor || switch_info->master)))
3044                 config.dv_esw_en = 0;
3045 #else
3046         config.dv_esw_en = 0;
3047 #endif
3048         /* Detect minimal data bytes to inline. */
3049         mlx5_set_min_inline(spawn, &config);
3050         /* Store device configuration on private structure. */
3051         priv->config = config;
3052         /* Create context for virtual machine VLAN workaround. */
3053         priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex);
3054         if (config.dv_flow_en) {
3055                 err = mlx5_alloc_shared_dr(priv);
3056                 if (err)
3057                         goto error;
3058                 /*
3059                  * RSS id is shared with meter flow id. Meter flow id can only
3060                  * use the 24 MSB of the register.
3061                  */
3062                 priv->qrss_id_pool = mlx5_flow_id_pool_alloc(UINT32_MAX >>
3063                                      MLX5_MTR_COLOR_BITS);
3064                 if (!priv->qrss_id_pool) {
3065                         DRV_LOG(ERR, "can't create flow id pool");
3066                         err = ENOMEM;
3067                         goto error;
3068                 }
3069         }
3070         /* Supported Verbs flow priority number detection. */
3071         err = mlx5_flow_discover_priorities(eth_dev);
3072         if (err < 0) {
3073                 err = -err;
3074                 goto error;
3075         }
3076         priv->config.flow_prio = err;
3077         if (!priv->config.dv_esw_en &&
3078             priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
3079                 DRV_LOG(WARNING, "metadata mode %u is not supported "
3080                                  "(no E-Switch)", priv->config.dv_xmeta_en);
3081                 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY;
3082         }
3083         mlx5_set_metadata_mask(eth_dev);
3084         if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
3085             !priv->sh->dv_regc0_mask) {
3086                 DRV_LOG(ERR, "metadata mode %u is not supported "
3087                              "(no metadata reg_c[0] is available)",
3088                              priv->config.dv_xmeta_en);
3089                         err = ENOTSUP;
3090                         goto error;
3091         }
3092         /*
3093          * Allocate the buffer for flow creating, just once.
3094          * The allocation must be done before any flow creating.
3095          */
3096         mlx5_flow_alloc_intermediate(eth_dev);
3097         /* Query availibility of metadata reg_c's. */
3098         err = mlx5_flow_discover_mreg_c(eth_dev);
3099         if (err < 0) {
3100                 err = -err;
3101                 goto error;
3102         }
3103         if (!mlx5_flow_ext_mreg_supported(eth_dev)) {
3104                 DRV_LOG(DEBUG,
3105                         "port %u extensive metadata register is not supported",
3106                         eth_dev->data->port_id);
3107                 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
3108                         DRV_LOG(ERR, "metadata mode %u is not supported "
3109                                      "(no metadata registers available)",
3110                                      priv->config.dv_xmeta_en);
3111                         err = ENOTSUP;
3112                         goto error;
3113                 }
3114         }
3115         if (priv->config.dv_flow_en &&
3116             priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
3117             mlx5_flow_ext_mreg_supported(eth_dev) &&
3118             priv->sh->dv_regc0_mask) {
3119                 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME,
3120                                                       MLX5_FLOW_MREG_HTABLE_SZ);
3121                 if (!priv->mreg_cp_tbl) {
3122                         err = ENOMEM;
3123                         goto error;
3124                 }
3125         }
3126         return eth_dev;
3127 error:
3128         if (priv) {
3129                 if (priv->mreg_cp_tbl)
3130                         mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
3131                 if (priv->sh)
3132                         mlx5_free_shared_dr(priv);
3133                 if (priv->nl_socket_route >= 0)
3134                         close(priv->nl_socket_route);
3135                 if (priv->nl_socket_rdma >= 0)
3136                         close(priv->nl_socket_rdma);
3137                 if (priv->vmwa_context)
3138                         mlx5_vlan_vmwa_exit(priv->vmwa_context);
3139                 if (priv->qrss_id_pool)
3140                         mlx5_flow_id_pool_release(priv->qrss_id_pool);
3141                 if (own_domain_id)
3142                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
3143                 rte_free(priv);
3144                 if (eth_dev != NULL)
3145                         eth_dev->data->dev_private = NULL;
3146         }
3147         if (eth_dev != NULL) {
3148                 /* mac_addrs must not be freed alone because part of dev_private */
3149                 eth_dev->data->mac_addrs = NULL;
3150                 rte_eth_dev_release_port(eth_dev);
3151         }
3152         if (sh)
3153                 mlx5_free_shared_ibctx(sh);
3154         MLX5_ASSERT(err > 0);
3155         rte_errno = err;
3156         return NULL;
3157 }
3158
3159 /**
3160  * Comparison callback to sort device data.
3161  *
3162  * This is meant to be used with qsort().
3163  *
3164  * @param a[in]
3165  *   Pointer to pointer to first data object.
3166  * @param b[in]
3167  *   Pointer to pointer to second data object.
3168  *
3169  * @return
3170  *   0 if both objects are equal, less than 0 if the first argument is less
3171  *   than the second, greater than 0 otherwise.
3172  */
3173 static int
3174 mlx5_dev_spawn_data_cmp(const void *a, const void *b)
3175 {
3176         const struct mlx5_switch_info *si_a =
3177                 &((const struct mlx5_dev_spawn_data *)a)->info;
3178         const struct mlx5_switch_info *si_b =
3179                 &((const struct mlx5_dev_spawn_data *)b)->info;
3180         int ret;
3181
3182         /* Master device first. */
3183         ret = si_b->master - si_a->master;
3184         if (ret)
3185                 return ret;
3186         /* Then representor devices. */
3187         ret = si_b->representor - si_a->representor;
3188         if (ret)
3189                 return ret;
3190         /* Unidentified devices come last in no specific order. */
3191         if (!si_a->representor)
3192                 return 0;
3193         /* Order representors by name. */
3194         return si_a->port_name - si_b->port_name;
3195 }
3196
3197 /**
3198  * Match PCI information for possible slaves of bonding device.
3199  *
3200  * @param[in] ibv_dev
3201  *   Pointer to Infiniband device structure.
3202  * @param[in] pci_dev
3203  *   Pointer to PCI device structure to match PCI address.
3204  * @param[in] nl_rdma
3205  *   Netlink RDMA group socket handle.
3206  *
3207  * @return
3208  *   negative value if no bonding device found, otherwise
3209  *   positive index of slave PF in bonding.
3210  */
3211 static int
3212 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev,
3213                            const struct rte_pci_device *pci_dev,
3214                            int nl_rdma)
3215 {
3216         char ifname[IF_NAMESIZE + 1];
3217         unsigned int ifindex;
3218         unsigned int np, i;
3219         FILE *file = NULL;
3220         int pf = -1;
3221
3222         /*
3223          * Try to get master device name. If something goes
3224          * wrong suppose the lack of kernel support and no
3225          * bonding devices.
3226          */
3227         if (nl_rdma < 0)
3228                 return -1;
3229         if (!strstr(ibv_dev->name, "bond"))
3230                 return -1;
3231         np = mlx5_nl_portnum(nl_rdma, ibv_dev->name);
3232         if (!np)
3233                 return -1;
3234         /*
3235          * The Master device might not be on the predefined
3236          * port (not on port index 1, it is not garanted),
3237          * we have to scan all Infiniband device port and
3238          * find master.
3239          */
3240         for (i = 1; i <= np; ++i) {
3241                 /* Check whether Infiniband port is populated. */
3242                 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i);
3243                 if (!ifindex)
3244                         continue;
3245                 if (!if_indextoname(ifindex, ifname))
3246                         continue;
3247                 /* Try to read bonding slave names from sysfs. */
3248                 MKSTR(slaves,
3249                       "/sys/class/net/%s/master/bonding/slaves", ifname);
3250                 file = fopen(slaves, "r");
3251                 if (file)
3252                         break;
3253         }
3254         if (!file)
3255                 return -1;
3256         /* Use safe format to check maximal buffer length. */
3257         MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE);
3258         while (fscanf(file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) {
3259                 char tmp_str[IF_NAMESIZE + 32];
3260                 struct rte_pci_addr pci_addr;
3261                 struct mlx5_switch_info info;
3262
3263                 /* Process slave interface names in the loop. */
3264                 snprintf(tmp_str, sizeof(tmp_str),
3265                          "/sys/class/net/%s", ifname);
3266                 if (mlx5_dev_to_pci_addr(tmp_str, &pci_addr)) {
3267                         DRV_LOG(WARNING, "can not get PCI address"
3268                                          " for netdev \"%s\"", ifname);
3269                         continue;
3270                 }
3271                 if (pci_dev->addr.domain != pci_addr.domain ||
3272                     pci_dev->addr.bus != pci_addr.bus ||
3273                     pci_dev->addr.devid != pci_addr.devid ||
3274                     pci_dev->addr.function != pci_addr.function)
3275                         continue;
3276                 /* Slave interface PCI address match found. */
3277                 fclose(file);
3278                 snprintf(tmp_str, sizeof(tmp_str),
3279                          "/sys/class/net/%s/phys_port_name", ifname);
3280                 file = fopen(tmp_str, "rb");
3281                 if (!file)
3282                         break;
3283                 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET;
3284                 if (fscanf(file, "%32s", tmp_str) == 1)
3285                         mlx5_translate_port_name(tmp_str, &info);
3286                 if (info.name_type == MLX5_PHYS_PORT_NAME_TYPE_LEGACY ||
3287                     info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK)
3288                         pf = info.port_name;
3289                 break;
3290         }
3291         if (file)
3292                 fclose(file);
3293         return pf;
3294 }
3295
3296 /**
3297  * DPDK callback to register a PCI device.
3298  *
3299  * This function spawns Ethernet devices out of a given PCI device.
3300  *
3301  * @param[in] pci_drv
3302  *   PCI driver structure (mlx5_driver).
3303  * @param[in] pci_dev
3304  *   PCI device information.
3305  *
3306  * @return
3307  *   0 on success, a negative errno value otherwise and rte_errno is set.
3308  */
3309 static int
3310 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3311                struct rte_pci_device *pci_dev)
3312 {
3313         struct ibv_device **ibv_list;
3314         /*
3315          * Number of found IB Devices matching with requested PCI BDF.
3316          * nd != 1 means there are multiple IB devices over the same
3317          * PCI device and we have representors and master.
3318          */
3319         unsigned int nd = 0;
3320         /*
3321          * Number of found IB device Ports. nd = 1 and np = 1..n means
3322          * we have the single multiport IB device, and there may be
3323          * representors attached to some of found ports.
3324          */
3325         unsigned int np = 0;
3326         /*
3327          * Number of DPDK ethernet devices to Spawn - either over
3328          * multiple IB devices or multiple ports of single IB device.
3329          * Actually this is the number of iterations to spawn.
3330          */
3331         unsigned int ns = 0;
3332         /*
3333          * Bonding device
3334          *   < 0 - no bonding device (single one)
3335          *  >= 0 - bonding device (value is slave PF index)
3336          */
3337         int bd = -1;
3338         struct mlx5_dev_spawn_data *list = NULL;
3339         struct mlx5_dev_config dev_config;
3340         int ret;
3341
3342         if (mlx5_class_get(pci_dev->device.devargs) != MLX5_CLASS_NET) {
3343                 DRV_LOG(DEBUG, "Skip probing - should be probed by other mlx5"
3344                         " driver.");
3345                 return 1;
3346         }
3347         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
3348                 mlx5_pmd_socket_init();
3349         ret = mlx5_init_once();
3350         if (ret) {
3351                 DRV_LOG(ERR, "unable to init PMD global data: %s",
3352                         strerror(rte_errno));
3353                 return -rte_errno;
3354         }
3355         MLX5_ASSERT(pci_drv == &mlx5_driver);
3356         errno = 0;
3357         ibv_list = mlx5_glue->get_device_list(&ret);
3358         if (!ibv_list) {
3359                 rte_errno = errno ? errno : ENOSYS;
3360                 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?");
3361                 return -rte_errno;
3362         }
3363         /*
3364          * First scan the list of all Infiniband devices to find
3365          * matching ones, gathering into the list.
3366          */
3367         struct ibv_device *ibv_match[ret + 1];
3368         int nl_route = mlx5_nl_init(NETLINK_ROUTE);
3369         int nl_rdma = mlx5_nl_init(NETLINK_RDMA);
3370         unsigned int i;
3371
3372         while (ret-- > 0) {
3373                 struct rte_pci_addr pci_addr;
3374
3375                 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name);
3376                 bd = mlx5_device_bond_pci_match
3377                                 (ibv_list[ret], pci_dev, nl_rdma);
3378                 if (bd >= 0) {
3379                         /*
3380                          * Bonding device detected. Only one match is allowed,
3381                          * the bonding is supported over multi-port IB device,
3382                          * there should be no matches on representor PCI
3383                          * functions or non VF LAG bonding devices with
3384                          * specified address.
3385                          */
3386                         if (nd) {
3387                                 DRV_LOG(ERR,
3388                                         "multiple PCI match on bonding device"
3389                                         "\"%s\" found", ibv_list[ret]->name);
3390                                 rte_errno = ENOENT;
3391                                 ret = -rte_errno;
3392                                 goto exit;
3393                         }
3394                         DRV_LOG(INFO, "PCI information matches for"
3395                                       " slave %d bonding device \"%s\"",
3396                                       bd, ibv_list[ret]->name);
3397                         ibv_match[nd++] = ibv_list[ret];
3398                         break;
3399                 }
3400                 if (mlx5_dev_to_pci_addr
3401                         (ibv_list[ret]->ibdev_path, &pci_addr))
3402                         continue;
3403                 if (pci_dev->addr.domain != pci_addr.domain ||
3404                     pci_dev->addr.bus != pci_addr.bus ||
3405                     pci_dev->addr.devid != pci_addr.devid ||
3406                     pci_dev->addr.function != pci_addr.function)
3407                         continue;
3408                 DRV_LOG(INFO, "PCI information matches for device \"%s\"",
3409                         ibv_list[ret]->name);
3410                 ibv_match[nd++] = ibv_list[ret];
3411         }
3412         ibv_match[nd] = NULL;
3413         if (!nd) {
3414                 /* No device matches, just complain and bail out. */
3415                 DRV_LOG(WARNING,
3416                         "no Verbs device matches PCI device " PCI_PRI_FMT ","
3417                         " are kernel drivers loaded?",
3418                         pci_dev->addr.domain, pci_dev->addr.bus,
3419                         pci_dev->addr.devid, pci_dev->addr.function);
3420                 rte_errno = ENOENT;
3421                 ret = -rte_errno;
3422                 goto exit;
3423         }
3424         if (nd == 1) {
3425                 /*
3426                  * Found single matching device may have multiple ports.
3427                  * Each port may be representor, we have to check the port
3428                  * number and check the representors existence.
3429                  */
3430                 if (nl_rdma >= 0)
3431                         np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name);
3432                 if (!np)
3433                         DRV_LOG(WARNING, "can not get IB device \"%s\""
3434                                          " ports number", ibv_match[0]->name);
3435                 if (bd >= 0 && !np) {
3436                         DRV_LOG(ERR, "can not get ports"
3437                                      " for bonding device");
3438                         rte_errno = ENOENT;
3439                         ret = -rte_errno;
3440                         goto exit;
3441                 }
3442         }
3443 #ifndef HAVE_MLX5DV_DR_DEVX_PORT
3444         if (bd >= 0) {
3445                 /*
3446                  * This may happen if there is VF LAG kernel support and
3447                  * application is compiled with older rdma_core library.
3448                  */
3449                 DRV_LOG(ERR,
3450                         "No kernel/verbs support for VF LAG bonding found.");
3451                 rte_errno = ENOTSUP;
3452                 ret = -rte_errno;
3453                 goto exit;
3454         }
3455 #endif
3456         /*
3457          * Now we can determine the maximal
3458          * amount of devices to be spawned.
3459          */
3460         list = rte_zmalloc("device spawn data",
3461                          sizeof(struct mlx5_dev_spawn_data) *
3462                          (np ? np : nd),
3463                          RTE_CACHE_LINE_SIZE);
3464         if (!list) {
3465                 DRV_LOG(ERR, "spawn data array allocation failure");
3466                 rte_errno = ENOMEM;
3467                 ret = -rte_errno;
3468                 goto exit;
3469         }
3470         if (bd >= 0 || np > 1) {
3471                 /*
3472                  * Single IB device with multiple ports found,
3473                  * it may be E-Switch master device and representors.
3474                  * We have to perform identification through the ports.
3475                  */
3476                 MLX5_ASSERT(nl_rdma >= 0);
3477                 MLX5_ASSERT(ns == 0);
3478                 MLX5_ASSERT(nd == 1);
3479                 MLX5_ASSERT(np);
3480                 for (i = 1; i <= np; ++i) {
3481                         list[ns].max_port = np;
3482                         list[ns].ibv_port = i;
3483                         list[ns].ibv_dev = ibv_match[0];
3484                         list[ns].eth_dev = NULL;
3485                         list[ns].pci_dev = pci_dev;
3486                         list[ns].pf_bond = bd;
3487                         list[ns].ifindex = mlx5_nl_ifindex
3488                                         (nl_rdma, list[ns].ibv_dev->name, i);
3489                         if (!list[ns].ifindex) {
3490                                 /*
3491                                  * No network interface index found for the
3492                                  * specified port, it means there is no
3493                                  * representor on this port. It's OK,
3494                                  * there can be disabled ports, for example
3495                                  * if sriov_numvfs < sriov_totalvfs.
3496                                  */
3497                                 continue;
3498                         }
3499                         ret = -1;
3500                         if (nl_route >= 0)
3501                                 ret = mlx5_nl_switch_info
3502                                                (nl_route,
3503                                                 list[ns].ifindex,
3504                                                 &list[ns].info);
3505                         if (ret || (!list[ns].info.representor &&
3506                                     !list[ns].info.master)) {
3507                                 /*
3508                                  * We failed to recognize representors with
3509                                  * Netlink, let's try to perform the task
3510                                  * with sysfs.
3511                                  */
3512                                 ret =  mlx5_sysfs_switch_info
3513                                                 (list[ns].ifindex,
3514                                                  &list[ns].info);
3515                         }
3516                         if (!ret && bd >= 0) {
3517                                 switch (list[ns].info.name_type) {
3518                                 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK:
3519                                         if (list[ns].info.port_name == bd)
3520                                                 ns++;
3521                                         break;
3522                                 case MLX5_PHYS_PORT_NAME_TYPE_PFVF:
3523                                         if (list[ns].info.pf_num == bd)
3524                                                 ns++;
3525                                         break;
3526                                 default:
3527                                         break;
3528                                 }
3529                                 continue;
3530                         }
3531                         if (!ret && (list[ns].info.representor ^
3532                                      list[ns].info.master))
3533                                 ns++;
3534                 }
3535                 if (!ns) {
3536                         DRV_LOG(ERR,
3537                                 "unable to recognize master/representors"
3538                                 " on the IB device with multiple ports");
3539                         rte_errno = ENOENT;
3540                         ret = -rte_errno;
3541                         goto exit;
3542                 }
3543         } else {
3544                 /*
3545                  * The existence of several matching entries (nd > 1) means
3546                  * port representors have been instantiated. No existing Verbs
3547                  * call nor sysfs entries can tell them apart, this can only
3548                  * be done through Netlink calls assuming kernel drivers are
3549                  * recent enough to support them.
3550                  *
3551                  * In the event of identification failure through Netlink,
3552                  * try again through sysfs, then:
3553                  *
3554                  * 1. A single IB device matches (nd == 1) with single
3555                  *    port (np=0/1) and is not a representor, assume
3556                  *    no switch support.
3557                  *
3558                  * 2. Otherwise no safe assumptions can be made;
3559                  *    complain louder and bail out.
3560                  */
3561                 np = 1;
3562                 for (i = 0; i != nd; ++i) {
3563                         memset(&list[ns].info, 0, sizeof(list[ns].info));
3564                         list[ns].max_port = 1;
3565                         list[ns].ibv_port = 1;
3566                         list[ns].ibv_dev = ibv_match[i];
3567                         list[ns].eth_dev = NULL;
3568                         list[ns].pci_dev = pci_dev;
3569                         list[ns].pf_bond = -1;
3570                         list[ns].ifindex = 0;
3571                         if (nl_rdma >= 0)
3572                                 list[ns].ifindex = mlx5_nl_ifindex
3573                                         (nl_rdma, list[ns].ibv_dev->name, 1);
3574                         if (!list[ns].ifindex) {
3575                                 char ifname[IF_NAMESIZE];
3576
3577                                 /*
3578                                  * Netlink failed, it may happen with old
3579                                  * ib_core kernel driver (before 4.16).
3580                                  * We can assume there is old driver because
3581                                  * here we are processing single ports IB
3582                                  * devices. Let's try sysfs to retrieve
3583                                  * the ifindex. The method works for
3584                                  * master device only.
3585                                  */
3586                                 if (nd > 1) {
3587                                         /*
3588                                          * Multiple devices found, assume
3589                                          * representors, can not distinguish
3590                                          * master/representor and retrieve
3591                                          * ifindex via sysfs.
3592                                          */
3593                                         continue;
3594                                 }
3595                                 ret = mlx5_get_master_ifname
3596                                         (ibv_match[i]->ibdev_path, &ifname);
3597                                 if (!ret)
3598                                         list[ns].ifindex =
3599                                                 if_nametoindex(ifname);
3600                                 if (!list[ns].ifindex) {
3601                                         /*
3602                                          * No network interface index found
3603                                          * for the specified device, it means
3604                                          * there it is neither representor
3605                                          * nor master.
3606                                          */
3607                                         continue;
3608                                 }
3609                         }
3610                         ret = -1;
3611                         if (nl_route >= 0)
3612                                 ret = mlx5_nl_switch_info
3613                                                (nl_route,
3614                                                 list[ns].ifindex,
3615                                                 &list[ns].info);
3616                         if (ret || (!list[ns].info.representor &&
3617                                     !list[ns].info.master)) {
3618                                 /*
3619                                  * We failed to recognize representors with
3620                                  * Netlink, let's try to perform the task
3621                                  * with sysfs.
3622                                  */
3623                                 ret =  mlx5_sysfs_switch_info
3624                                                 (list[ns].ifindex,
3625                                                  &list[ns].info);
3626                         }
3627                         if (!ret && (list[ns].info.representor ^
3628                                      list[ns].info.master)) {
3629                                 ns++;
3630                         } else if ((nd == 1) &&
3631                                    !list[ns].info.representor &&
3632                                    !list[ns].info.master) {
3633                                 /*
3634                                  * Single IB device with
3635                                  * one physical port and
3636                                  * attached network device.
3637                                  * May be SRIOV is not enabled
3638                                  * or there is no representors.
3639                                  */
3640                                 DRV_LOG(INFO, "no E-Switch support detected");
3641                                 ns++;
3642                                 break;
3643                         }
3644                 }
3645                 if (!ns) {
3646                         DRV_LOG(ERR,
3647                                 "unable to recognize master/representors"
3648                                 " on the multiple IB devices");
3649                         rte_errno = ENOENT;
3650                         ret = -rte_errno;
3651                         goto exit;
3652                 }
3653         }
3654         MLX5_ASSERT(ns);
3655         /*
3656          * Sort list to probe devices in natural order for users convenience
3657          * (i.e. master first, then representors from lowest to highest ID).
3658          */
3659         qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp);
3660         /* Default configuration. */
3661         dev_config = (struct mlx5_dev_config){
3662                 .hw_padding = 0,
3663                 .mps = MLX5_ARG_UNSET,
3664                 .dbnc = MLX5_ARG_UNSET,
3665                 .rx_vec_en = 1,
3666                 .txq_inline_max = MLX5_ARG_UNSET,
3667                 .txq_inline_min = MLX5_ARG_UNSET,
3668                 .txq_inline_mpw = MLX5_ARG_UNSET,
3669                 .txqs_inline = MLX5_ARG_UNSET,
3670                 .vf_nl_en = 1,
3671                 .mr_ext_memseg_en = 1,
3672                 .mprq = {
3673                         .enabled = 0, /* Disabled by default. */
3674                         .stride_num_n = 0,
3675                         .stride_size_n = 0,
3676                         .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
3677                         .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
3678                 },
3679                 .dv_esw_en = 1,
3680                 .dv_flow_en = 1,
3681                 .log_hp_size = MLX5_ARG_UNSET,
3682         };
3683         /* Device specific configuration. */
3684         switch (pci_dev->id.device_id) {
3685         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
3686         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
3687         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
3688         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
3689         case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF:
3690         case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF:
3691         case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF:
3692                 dev_config.vf = 1;
3693                 break;
3694         default:
3695                 break;
3696         }
3697         for (i = 0; i != ns; ++i) {
3698                 uint32_t restore;
3699
3700                 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device,
3701                                                  &list[i],
3702                                                  dev_config);
3703                 if (!list[i].eth_dev) {
3704                         if (rte_errno != EBUSY && rte_errno != EEXIST)
3705                                 break;
3706                         /* Device is disabled or already spawned. Ignore it. */
3707                         continue;
3708                 }
3709                 restore = list[i].eth_dev->data->dev_flags;
3710                 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev);
3711                 /* Restore non-PCI flags cleared by the above call. */
3712                 list[i].eth_dev->data->dev_flags |= restore;
3713                 rte_eth_dev_probing_finish(list[i].eth_dev);
3714         }
3715         if (i != ns) {
3716                 DRV_LOG(ERR,
3717                         "probe of PCI device " PCI_PRI_FMT " aborted after"
3718                         " encountering an error: %s",
3719                         pci_dev->addr.domain, pci_dev->addr.bus,
3720                         pci_dev->addr.devid, pci_dev->addr.function,
3721                         strerror(rte_errno));
3722                 ret = -rte_errno;
3723                 /* Roll back. */
3724                 while (i--) {
3725                         if (!list[i].eth_dev)
3726                                 continue;
3727                         mlx5_dev_close(list[i].eth_dev);
3728                         /* mac_addrs must not be freed because in dev_private */
3729                         list[i].eth_dev->data->mac_addrs = NULL;
3730                         claim_zero(rte_eth_dev_release_port(list[i].eth_dev));
3731                 }
3732                 /* Restore original error. */
3733                 rte_errno = -ret;
3734         } else {
3735                 ret = 0;
3736         }
3737 exit:
3738         /*
3739          * Do the routine cleanup:
3740          * - close opened Netlink sockets
3741          * - free allocated spawn data array
3742          * - free the Infiniband device list
3743          */
3744         if (nl_rdma >= 0)
3745                 close(nl_rdma);
3746         if (nl_route >= 0)
3747                 close(nl_route);
3748         if (list)
3749                 rte_free(list);
3750         MLX5_ASSERT(ibv_list);
3751         mlx5_glue->free_device_list(ibv_list);
3752         return ret;
3753 }
3754
3755 /**
3756  * Look for the ethernet device belonging to mlx5 driver.
3757  *
3758  * @param[in] port_id
3759  *   port_id to start looking for device.
3760  * @param[in] pci_dev
3761  *   Pointer to the hint PCI device. When device is being probed
3762  *   the its siblings (master and preceding representors might
3763  *   not have assigned driver yet (because the mlx5_pci_probe()
3764  *   is not completed yet, for this case match on hint PCI
3765  *   device may be used to detect sibling device.
3766  *
3767  * @return
3768  *   port_id of found device, RTE_MAX_ETHPORT if not found.
3769  */
3770 uint16_t
3771 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
3772 {
3773         while (port_id < RTE_MAX_ETHPORTS) {
3774                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
3775
3776                 if (dev->state != RTE_ETH_DEV_UNUSED &&
3777                     dev->device &&
3778                     (dev->device == &pci_dev->device ||
3779                      (dev->device->driver &&
3780                      dev->device->driver->name &&
3781                      !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
3782                         break;
3783                 port_id++;
3784         }
3785         if (port_id >= RTE_MAX_ETHPORTS)
3786                 return RTE_MAX_ETHPORTS;
3787         return port_id;
3788 }
3789
3790 /**
3791  * DPDK callback to remove a PCI device.
3792  *
3793  * This function removes all Ethernet devices belong to a given PCI device.
3794  *
3795  * @param[in] pci_dev
3796  *   Pointer to the PCI device.
3797  *
3798  * @return
3799  *   0 on success, the function cannot fail.
3800  */
3801 static int
3802 mlx5_pci_remove(struct rte_pci_device *pci_dev)
3803 {
3804         uint16_t port_id;
3805
3806         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
3807                 /*
3808                  * mlx5_dev_close() is not registered to secondary process,
3809                  * call the close function explicitly for secondary process.
3810                  */
3811                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
3812                         mlx5_dev_close(&rte_eth_devices[port_id]);
3813                 else
3814                         rte_eth_dev_close(port_id);
3815         }
3816         return 0;
3817 }
3818
3819 static const struct rte_pci_id mlx5_pci_id_map[] = {
3820         {
3821                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3822                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
3823         },
3824         {
3825                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3826                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
3827         },
3828         {
3829                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3830                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
3831         },
3832         {
3833                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3834                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
3835         },
3836         {
3837                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3838                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
3839         },
3840         {
3841                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3842                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
3843         },
3844         {
3845                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3846                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
3847         },
3848         {
3849                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3850                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
3851         },
3852         {
3853                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3854                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
3855         },
3856         {
3857                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3858                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
3859         },
3860         {
3861                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3862                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
3863         },
3864         {
3865                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3866                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
3867         },
3868         {
3869                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3870                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
3871         },
3872         {
3873                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3874                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
3875         },
3876         {
3877                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3878                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
3879         },
3880         {
3881                 .vendor_id = 0
3882         }
3883 };
3884
3885 static struct rte_pci_driver mlx5_driver = {
3886         .driver = {
3887                 .name = MLX5_DRIVER_NAME
3888         },
3889         .id_table = mlx5_pci_id_map,
3890         .probe = mlx5_pci_probe,
3891         .remove = mlx5_pci_remove,
3892         .dma_map = mlx5_dma_map,
3893         .dma_unmap = mlx5_dma_unmap,
3894         .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV |
3895                      RTE_PCI_DRV_PROBE_AGAIN,
3896 };
3897
3898 /**
3899  * Driver initialization routine.
3900  */
3901 RTE_INIT(rte_mlx5_pmd_init)
3902 {
3903         /* Initialize driver log type. */
3904         mlx5_logtype = rte_log_register("pmd.net.mlx5");
3905         if (mlx5_logtype >= 0)
3906                 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
3907
3908         /* Build the static tables for Verbs conversion. */
3909         mlx5_set_ptype_table();
3910         mlx5_set_cksum_table();
3911         mlx5_set_swp_types_table();
3912         if (mlx5_glue)
3913                 rte_pci_register(&mlx5_driver);
3914 }
3915
3916 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
3917 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
3918 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");