1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
14 #include <linux/rtnetlink.h>
17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
19 #pragma GCC diagnostic ignored "-Wpedantic"
21 #include <infiniband/verbs.h>
23 #pragma GCC diagnostic error "-Wpedantic"
26 #include <rte_malloc.h>
27 #include <rte_ethdev_driver.h>
28 #include <rte_ethdev_pci.h>
30 #include <rte_bus_pci.h>
31 #include <rte_common.h>
32 #include <rte_kvargs.h>
33 #include <rte_rwlock.h>
34 #include <rte_spinlock.h>
35 #include <rte_string_fns.h>
36 #include <rte_alarm.h>
38 #include <mlx5_glue.h>
39 #include <mlx5_devx_cmds.h>
40 #include <mlx5_common.h>
41 #include <mlx5_common_mp.h>
43 #include "mlx5_defs.h"
45 #include "mlx5_utils.h"
46 #include "mlx5_rxtx.h"
47 #include "mlx5_autoconf.h"
49 #include "mlx5_flow.h"
50 #include "rte_pmd_mlx5.h"
52 /* Device parameter to enable RX completion queue compression. */
53 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
55 /* Device parameter to enable RX completion entry padding to 128B. */
56 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
58 /* Device parameter to enable padding Rx packet to cacheline size. */
59 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
61 /* Device parameter to enable Multi-Packet Rx queue. */
62 #define MLX5_RX_MPRQ_EN "mprq_en"
64 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
65 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
67 /* Device parameter to configure log 2 of the stride size for MPRQ. */
68 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
70 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
71 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
73 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
74 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
76 /* Device parameter to configure inline send. Deprecated, ignored.*/
77 #define MLX5_TXQ_INLINE "txq_inline"
79 /* Device parameter to limit packet size to inline with ordinary SEND. */
80 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
82 /* Device parameter to configure minimal data size to inline. */
83 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
85 /* Device parameter to limit packet size to inline with Enhanced MPW. */
86 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
89 * Device parameter to configure the number of TX queues threshold for
90 * enabling inline send.
92 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
95 * Device parameter to configure the number of TX queues threshold for
96 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
98 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
100 /* Device parameter to enable multi-packet send WQEs. */
101 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
104 * Device parameter to force doorbell register mapping
105 * to non-cahed region eliminating the extra write memory barrier.
107 #define MLX5_TX_DB_NC "tx_db_nc"
110 * Device parameter to include 2 dsegs in the title WQEBB.
111 * Deprecated, ignored.
113 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
116 * Device parameter to limit the size of inlining packet.
117 * Deprecated, ignored.
119 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
122 * Device parameter to enable hardware Tx vector.
123 * Deprecated, ignored (no vectorized Tx routines anymore).
125 #define MLX5_TX_VEC_EN "tx_vec_en"
127 /* Device parameter to enable hardware Rx vector. */
128 #define MLX5_RX_VEC_EN "rx_vec_en"
130 /* Allow L3 VXLAN flow creation. */
131 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
133 /* Activate DV E-Switch flow steering. */
134 #define MLX5_DV_ESW_EN "dv_esw_en"
136 /* Activate DV flow steering. */
137 #define MLX5_DV_FLOW_EN "dv_flow_en"
139 /* Enable extensive flow metadata support. */
140 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
142 /* Activate Netlink support in VF mode. */
143 #define MLX5_VF_NL_EN "vf_nl_en"
145 /* Enable extending memsegs when creating a MR. */
146 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
148 /* Select port representors to instantiate. */
149 #define MLX5_REPRESENTOR "representor"
151 /* Device parameter to configure the maximum number of dump files per queue. */
152 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
154 /* Configure timeout of LRO session (in microseconds). */
155 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
158 * Device parameter to configure the total data buffer size for a single
159 * hairpin queue (logarithm value).
161 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
163 #ifndef HAVE_IBV_MLX5_MOD_MPW
164 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
165 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
168 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
169 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
172 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
174 /* Shared memory between primary and secondary processes. */
175 struct mlx5_shared_data *mlx5_shared_data;
177 /* Spinlock for mlx5_shared_data allocation. */
178 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
180 /* Process local data for secondary processes. */
181 static struct mlx5_local_data mlx5_local_data;
183 /** Driver-specific log messages type. */
186 /** Data associated with devices to spawn. */
187 struct mlx5_dev_spawn_data {
188 uint32_t ifindex; /**< Network interface index. */
189 uint32_t max_port; /**< IB device maximal port index. */
190 uint32_t ibv_port; /**< IB device physical port index. */
191 int pf_bond; /**< bonding device PF index. < 0 - no bonding */
192 struct mlx5_switch_info info; /**< Switch information. */
193 struct ibv_device *ibv_dev; /**< Associated IB device. */
194 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
195 struct rte_pci_device *pci_dev; /**< Backend PCI device. */
198 static LIST_HEAD(, mlx5_ibv_shared) mlx5_ibv_list = LIST_HEAD_INITIALIZER();
199 static pthread_mutex_t mlx5_ibv_list_mutex = PTHREAD_MUTEX_INITIALIZER;
201 static struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
203 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
209 .malloc = rte_malloc_socket,
211 .type = "mlx5_encap_decap_ipool",
214 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
220 .malloc = rte_malloc_socket,
222 .type = "mlx5_push_vlan_ipool",
225 .size = sizeof(struct mlx5_flow_dv_tag_resource),
231 .malloc = rte_malloc_socket,
233 .type = "mlx5_tag_ipool",
236 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
242 .malloc = rte_malloc_socket,
244 .type = "mlx5_port_id_ipool",
247 .size = sizeof(struct mlx5_flow_tbl_data_entry),
253 .malloc = rte_malloc_socket,
255 .type = "mlx5_jump_ipool",
258 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
264 .malloc = rte_malloc_socket,
266 .type = "mlx5_hrxq_ipool",
271 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
272 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
274 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
275 #define MLX5_TAGS_HLIST_ARRAY_SIZE 8192
278 * Allocate ID pool structure.
281 * The maximum id can be allocated from the pool.
284 * Pointer to pool object, NULL value otherwise.
286 struct mlx5_flow_id_pool *
287 mlx5_flow_id_pool_alloc(uint32_t max_id)
289 struct mlx5_flow_id_pool *pool;
292 pool = rte_zmalloc("id pool allocation", sizeof(*pool),
293 RTE_CACHE_LINE_SIZE);
295 DRV_LOG(ERR, "can't allocate id pool");
299 mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
300 RTE_CACHE_LINE_SIZE);
302 DRV_LOG(ERR, "can't allocate mem for id pool");
306 pool->free_arr = mem;
307 pool->curr = pool->free_arr;
308 pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
309 pool->base_index = 0;
310 pool->max_id = max_id;
318 * Release ID pool structure.
321 * Pointer to flow id pool object to free.
324 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
326 rte_free(pool->free_arr);
334 * Pointer to flow id pool.
339 * 0 on success, error value otherwise.
342 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
344 if (pool->curr == pool->free_arr) {
345 if (pool->base_index == pool->max_id) {
347 DRV_LOG(ERR, "no free id");
350 *id = ++pool->base_index;
353 *id = *(--pool->curr);
361 * Pointer to flow id pool.
366 * 0 on success, error value otherwise.
369 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
375 if (pool->curr == pool->last) {
376 size = pool->curr - pool->free_arr;
377 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
378 MLX5_ASSERT(size2 > size);
379 mem = rte_malloc("", size2 * sizeof(uint32_t), 0);
381 DRV_LOG(ERR, "can't allocate mem for id pool");
385 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
386 rte_free(pool->free_arr);
387 pool->free_arr = mem;
388 pool->curr = pool->free_arr + size;
389 pool->last = pool->free_arr + size2;
397 * Initialize the counters management structure.
400 * Pointer to mlx5_ibv_shared object to free
403 mlx5_flow_counters_mng_init(struct mlx5_ibv_shared *sh)
407 TAILQ_INIT(&sh->cmng.flow_counters);
408 for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i)
409 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
413 * Destroy all the resources allocated for a counter memory management.
416 * Pointer to the memory management structure.
419 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
421 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
423 LIST_REMOVE(mng, next);
424 claim_zero(mlx5_devx_cmd_destroy(mng->dm));
425 claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
430 * Close and release all the resources of the counters management.
433 * Pointer to mlx5_ibv_shared object to free.
436 mlx5_flow_counters_mng_close(struct mlx5_ibv_shared *sh)
438 struct mlx5_counter_stats_mem_mng *mng;
445 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
446 if (rte_errno != EINPROGRESS)
450 for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i) {
451 struct mlx5_flow_counter_pool *pool;
452 uint32_t batch = !!(i % 2);
454 if (!sh->cmng.ccont[i].pools)
456 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
461 (mlx5_devx_cmd_destroy(pool->min_dcs));
463 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
464 if (pool->counters_raw[j].action)
466 (mlx5_glue->destroy_flow_action
467 (pool->counters_raw[j].action));
468 if (!batch && MLX5_GET_POOL_CNT_EXT
470 claim_zero(mlx5_devx_cmd_destroy
471 (MLX5_GET_POOL_CNT_EXT
474 TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool,
477 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
479 rte_free(sh->cmng.ccont[i].pools);
481 mng = LIST_FIRST(&sh->cmng.mem_mngs);
483 mlx5_flow_destroy_counter_stat_mem_mng(mng);
484 mng = LIST_FIRST(&sh->cmng.mem_mngs);
486 memset(&sh->cmng, 0, sizeof(sh->cmng));
490 * Initialize the flow resources' indexed mempool.
493 * Pointer to mlx5_ibv_shared object.
496 mlx5_flow_ipool_create(struct mlx5_ibv_shared *sh)
500 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
501 sh->ipool[i] = mlx5_ipool_create(&mlx5_ipool_cfg[i]);
505 * Release the flow resources' indexed mempool.
508 * Pointer to mlx5_ibv_shared object.
511 mlx5_flow_ipool_destroy(struct mlx5_ibv_shared *sh)
515 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
516 mlx5_ipool_destroy(sh->ipool[i]);
520 * Extract pdn of PD object using DV API.
523 * Pointer to the verbs PD object.
525 * Pointer to the PD object number variable.
528 * 0 on success, error value otherwise.
530 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
532 mlx5_get_pdn(struct ibv_pd *pd __rte_unused, uint32_t *pdn __rte_unused)
534 struct mlx5dv_obj obj;
535 struct mlx5dv_pd pd_info;
539 obj.pd.out = &pd_info;
540 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);
542 DRV_LOG(DEBUG, "Fail to get PD object info");
548 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
551 mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config)
556 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
557 /* Get environment variable to store. */
558 env = getenv(MLX5_SHUT_UP_BF);
559 value = env ? !!strcmp(env, "0") : MLX5_ARG_UNSET;
560 if (config->dbnc == MLX5_ARG_UNSET)
561 setenv(MLX5_SHUT_UP_BF, MLX5_SHUT_UP_BF_DEFAULT, 1);
563 setenv(MLX5_SHUT_UP_BF,
564 config->dbnc == MLX5_TXDB_NCACHED ? "1" : "0", 1);
569 mlx5_restore_doorbell_mapping_env(int value)
571 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
572 /* Restore the original environment variable state. */
573 if (value == MLX5_ARG_UNSET)
574 unsetenv(MLX5_SHUT_UP_BF);
576 setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1);
580 * Allocate shared IB device context. If there is multiport device the
581 * master and representors will share this context, if there is single
582 * port dedicated IB device, the context will be used by only given
583 * port due to unification.
585 * Routine first searches the context for the specified IB device name,
586 * if found the shared context assumed and reference counter is incremented.
587 * If no context found the new one is created and initialized with specified
588 * IB device context and parameters.
591 * Pointer to the IB device attributes (name, port, etc).
593 * Pointer to device configuration structure.
596 * Pointer to mlx5_ibv_shared object on success,
597 * otherwise NULL and rte_errno is set.
599 static struct mlx5_ibv_shared *
600 mlx5_alloc_shared_ibctx(const struct mlx5_dev_spawn_data *spawn,
601 const struct mlx5_dev_config *config)
603 struct mlx5_ibv_shared *sh;
607 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
608 struct mlx5_devx_tis_attr tis_attr = { 0 };
612 /* Secondary process should not create the shared context. */
613 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
614 pthread_mutex_lock(&mlx5_ibv_list_mutex);
615 /* Search for IB context by device name. */
616 LIST_FOREACH(sh, &mlx5_ibv_list, next) {
617 if (!strcmp(sh->ibdev_name, spawn->ibv_dev->name)) {
622 /* No device found, we have to create new shared context. */
623 MLX5_ASSERT(spawn->max_port);
624 sh = rte_zmalloc("ethdev shared ib context",
625 sizeof(struct mlx5_ibv_shared) +
627 sizeof(struct mlx5_ibv_shared_port),
628 RTE_CACHE_LINE_SIZE);
630 DRV_LOG(ERR, "shared context allocation failure");
635 * Configure environment variable "MLX5_BF_SHUT_UP"
636 * before the device creation. The rdma_core library
637 * checks the variable at device creation and
638 * stores the result internally.
640 dbmap_env = mlx5_config_doorbell_mapping_env(config);
641 /* Try to open IB device with DV first, then usual Verbs. */
643 sh->ctx = mlx5_glue->dv_open_device(spawn->ibv_dev);
646 DRV_LOG(DEBUG, "DevX is supported");
647 /* The device is created, no need for environment. */
648 mlx5_restore_doorbell_mapping_env(dbmap_env);
650 /* The environment variable is still configured. */
651 sh->ctx = mlx5_glue->open_device(spawn->ibv_dev);
652 err = errno ? errno : ENODEV;
654 * The environment variable is not needed anymore,
655 * all device creation attempts are completed.
657 mlx5_restore_doorbell_mapping_env(dbmap_env);
660 DRV_LOG(DEBUG, "DevX is NOT supported");
662 err = mlx5_glue->query_device_ex(sh->ctx, NULL, &sh->device_attr);
664 DRV_LOG(DEBUG, "ibv_query_device_ex() failed");
668 sh->max_port = spawn->max_port;
669 strncpy(sh->ibdev_name, sh->ctx->device->name,
670 sizeof(sh->ibdev_name));
671 strncpy(sh->ibdev_path, sh->ctx->device->ibdev_path,
672 sizeof(sh->ibdev_path));
673 pthread_mutex_init(&sh->intr_mutex, NULL);
675 * Setting port_id to max unallowed value means
676 * there is no interrupt subhandler installed for
677 * the given port index i.
679 for (i = 0; i < sh->max_port; i++) {
680 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
681 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
683 sh->pd = mlx5_glue->alloc_pd(sh->ctx);
684 if (sh->pd == NULL) {
685 DRV_LOG(ERR, "PD allocation failure");
689 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
691 err = mlx5_get_pdn(sh->pd, &sh->pdn);
693 DRV_LOG(ERR, "Fail to extract pdn from PD");
696 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
698 DRV_LOG(ERR, "TD allocation failure");
702 tis_attr.transport_domain = sh->td->id;
703 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
705 DRV_LOG(ERR, "TIS allocation failure");
710 sh->flow_id_pool = mlx5_flow_id_pool_alloc(UINT32_MAX);
711 if (!sh->flow_id_pool) {
712 DRV_LOG(ERR, "can't create flow id pool");
716 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
718 * Once the device is added to the list of memory event
719 * callback, its global MR cache table cannot be expanded
720 * on the fly because of deadlock. If it overflows, lookup
721 * should be done by searching MR list linearly, which is slow.
723 * At this point the device is not added to the memory
724 * event list yet, context is just being created.
726 err = mlx5_mr_btree_init(&sh->share_cache.cache,
727 MLX5_MR_BTREE_CACHE_N * 2,
728 spawn->pci_dev->device.numa_node);
733 mlx5_flow_counters_mng_init(sh);
734 mlx5_flow_ipool_create(sh);
735 /* Add device to memory callback list. */
736 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
737 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
739 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
740 /* Add context to the global device list. */
741 LIST_INSERT_HEAD(&mlx5_ibv_list, sh, next);
743 pthread_mutex_unlock(&mlx5_ibv_list_mutex);
746 pthread_mutex_unlock(&mlx5_ibv_list_mutex);
749 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
751 claim_zero(mlx5_devx_cmd_destroy(sh->td));
753 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
755 claim_zero(mlx5_glue->close_device(sh->ctx));
756 if (sh->flow_id_pool)
757 mlx5_flow_id_pool_release(sh->flow_id_pool);
759 MLX5_ASSERT(err > 0);
765 * Free shared IB device context. Decrement counter and if zero free
766 * all allocated resources and close handles.
769 * Pointer to mlx5_ibv_shared object to free
772 mlx5_free_shared_ibctx(struct mlx5_ibv_shared *sh)
774 pthread_mutex_lock(&mlx5_ibv_list_mutex);
775 #ifdef RTE_LIBRTE_MLX5_DEBUG
776 /* Check the object presence in the list. */
777 struct mlx5_ibv_shared *lctx;
779 LIST_FOREACH(lctx, &mlx5_ibv_list, next)
784 DRV_LOG(ERR, "Freeing non-existing shared IB context");
789 MLX5_ASSERT(sh->refcnt);
790 /* Secondary process should not free the shared context. */
791 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
794 /* Remove from memory callback device list. */
795 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
796 LIST_REMOVE(sh, mem_event_cb);
797 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
798 /* Release created Memory Regions. */
799 mlx5_mr_release_cache(&sh->share_cache);
800 /* Remove context from the global device list. */
801 LIST_REMOVE(sh, next);
803 * Ensure there is no async event handler installed.
804 * Only primary process handles async device events.
806 mlx5_flow_counters_mng_close(sh);
807 mlx5_flow_ipool_destroy(sh);
808 MLX5_ASSERT(!sh->intr_cnt);
810 mlx5_intr_callback_unregister
811 (&sh->intr_handle, mlx5_dev_interrupt_handler, sh);
812 #ifdef HAVE_MLX5_DEVX_ASYNC_SUPPORT
813 if (sh->devx_intr_cnt) {
814 if (sh->intr_handle_devx.fd)
815 rte_intr_callback_unregister(&sh->intr_handle_devx,
816 mlx5_dev_interrupt_handler_devx, sh);
818 mlx5dv_devx_destroy_cmd_comp(sh->devx_comp);
821 pthread_mutex_destroy(&sh->intr_mutex);
823 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
825 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
827 claim_zero(mlx5_devx_cmd_destroy(sh->td));
829 claim_zero(mlx5_glue->close_device(sh->ctx));
830 if (sh->flow_id_pool)
831 mlx5_flow_id_pool_release(sh->flow_id_pool);
834 pthread_mutex_unlock(&mlx5_ibv_list_mutex);
838 * Destroy table hash list and all the root entries per domain.
841 * Pointer to the private device data structure.
844 mlx5_free_table_hash_list(struct mlx5_priv *priv)
846 struct mlx5_ibv_shared *sh = priv->sh;
847 struct mlx5_flow_tbl_data_entry *tbl_data;
848 union mlx5_flow_tbl_key table_key = {
856 struct mlx5_hlist_entry *pos;
860 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
862 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
864 MLX5_ASSERT(tbl_data);
865 mlx5_hlist_remove(sh->flow_tbls, pos);
868 table_key.direction = 1;
869 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
871 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
873 MLX5_ASSERT(tbl_data);
874 mlx5_hlist_remove(sh->flow_tbls, pos);
877 table_key.direction = 0;
878 table_key.domain = 1;
879 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
881 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
883 MLX5_ASSERT(tbl_data);
884 mlx5_hlist_remove(sh->flow_tbls, pos);
887 mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
891 * Initialize flow table hash list and create the root tables entry
895 * Pointer to the private device data structure.
898 * Zero on success, positive error code otherwise.
901 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
903 struct mlx5_ibv_shared *sh = priv->sh;
904 char s[MLX5_HLIST_NAMESIZE];
908 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
909 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
910 if (!sh->flow_tbls) {
911 DRV_LOG(ERR, "flow tables with hash creation failed.\n");
915 #ifndef HAVE_MLX5DV_DR
917 * In case we have not DR support, the zero tables should be created
918 * because DV expect to see them even if they cannot be created by
921 union mlx5_flow_tbl_key table_key = {
929 struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL,
930 sizeof(*tbl_data), 0);
936 tbl_data->entry.key = table_key.v64;
937 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
940 rte_atomic32_init(&tbl_data->tbl.refcnt);
941 rte_atomic32_inc(&tbl_data->tbl.refcnt);
942 table_key.direction = 1;
943 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
948 tbl_data->entry.key = table_key.v64;
949 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
952 rte_atomic32_init(&tbl_data->tbl.refcnt);
953 rte_atomic32_inc(&tbl_data->tbl.refcnt);
954 table_key.direction = 0;
955 table_key.domain = 1;
956 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
961 tbl_data->entry.key = table_key.v64;
962 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
965 rte_atomic32_init(&tbl_data->tbl.refcnt);
966 rte_atomic32_inc(&tbl_data->tbl.refcnt);
969 mlx5_free_table_hash_list(priv);
970 #endif /* HAVE_MLX5DV_DR */
975 * Initialize DR related data within private structure.
976 * Routine checks the reference counter and does actual
977 * resources creation/initialization only if counter is zero.
980 * Pointer to the private device data structure.
983 * Zero on success, positive error code otherwise.
986 mlx5_alloc_shared_dr(struct mlx5_priv *priv)
988 struct mlx5_ibv_shared *sh = priv->sh;
989 char s[MLX5_HLIST_NAMESIZE];
993 err = mlx5_alloc_table_hash_list(priv);
995 DRV_LOG(DEBUG, "sh->flow_tbls[%p] already created, reuse\n",
996 (void *)sh->flow_tbls);
999 /* Create tags hash list table. */
1000 snprintf(s, sizeof(s), "%s_tags", sh->ibdev_name);
1001 sh->tag_table = mlx5_hlist_create(s, MLX5_TAGS_HLIST_ARRAY_SIZE);
1002 if (!sh->tag_table) {
1003 DRV_LOG(ERR, "tags with hash creation failed.\n");
1007 #ifdef HAVE_MLX5DV_DR
1010 if (sh->dv_refcnt) {
1011 /* Shared DV/DR structures is already initialized. */
1013 priv->dr_shared = 1;
1016 /* Reference counter is zero, we should initialize structures. */
1017 domain = mlx5_glue->dr_create_domain(sh->ctx,
1018 MLX5DV_DR_DOMAIN_TYPE_NIC_RX);
1020 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed");
1024 sh->rx_domain = domain;
1025 domain = mlx5_glue->dr_create_domain(sh->ctx,
1026 MLX5DV_DR_DOMAIN_TYPE_NIC_TX);
1028 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed");
1032 pthread_mutex_init(&sh->dv_mutex, NULL);
1033 sh->tx_domain = domain;
1034 #ifdef HAVE_MLX5DV_DR_ESWITCH
1035 if (priv->config.dv_esw_en) {
1036 domain = mlx5_glue->dr_create_domain
1037 (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB);
1039 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed");
1043 sh->fdb_domain = domain;
1044 sh->esw_drop_action = mlx5_glue->dr_create_flow_action_drop();
1047 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan();
1048 #endif /* HAVE_MLX5DV_DR */
1050 priv->dr_shared = 1;
1053 /* Rollback the created objects. */
1054 if (sh->rx_domain) {
1055 mlx5_glue->dr_destroy_domain(sh->rx_domain);
1056 sh->rx_domain = NULL;
1058 if (sh->tx_domain) {
1059 mlx5_glue->dr_destroy_domain(sh->tx_domain);
1060 sh->tx_domain = NULL;
1062 if (sh->fdb_domain) {
1063 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
1064 sh->fdb_domain = NULL;
1066 if (sh->esw_drop_action) {
1067 mlx5_glue->destroy_flow_action(sh->esw_drop_action);
1068 sh->esw_drop_action = NULL;
1070 if (sh->pop_vlan_action) {
1071 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
1072 sh->pop_vlan_action = NULL;
1074 if (sh->tag_table) {
1075 /* tags should be destroyed with flow before. */
1076 mlx5_hlist_destroy(sh->tag_table, NULL, NULL);
1077 sh->tag_table = NULL;
1079 mlx5_free_table_hash_list(priv);
1084 * Destroy DR related data within private structure.
1087 * Pointer to the private device data structure.
1090 mlx5_free_shared_dr(struct mlx5_priv *priv)
1092 struct mlx5_ibv_shared *sh;
1094 if (!priv->dr_shared)
1096 priv->dr_shared = 0;
1099 #ifdef HAVE_MLX5DV_DR
1100 MLX5_ASSERT(sh->dv_refcnt);
1101 if (sh->dv_refcnt && --sh->dv_refcnt)
1103 if (sh->rx_domain) {
1104 mlx5_glue->dr_destroy_domain(sh->rx_domain);
1105 sh->rx_domain = NULL;
1107 if (sh->tx_domain) {
1108 mlx5_glue->dr_destroy_domain(sh->tx_domain);
1109 sh->tx_domain = NULL;
1111 #ifdef HAVE_MLX5DV_DR_ESWITCH
1112 if (sh->fdb_domain) {
1113 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
1114 sh->fdb_domain = NULL;
1116 if (sh->esw_drop_action) {
1117 mlx5_glue->destroy_flow_action(sh->esw_drop_action);
1118 sh->esw_drop_action = NULL;
1121 if (sh->pop_vlan_action) {
1122 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
1123 sh->pop_vlan_action = NULL;
1125 pthread_mutex_destroy(&sh->dv_mutex);
1126 #endif /* HAVE_MLX5DV_DR */
1127 if (sh->tag_table) {
1128 /* tags should be destroyed with flow before. */
1129 mlx5_hlist_destroy(sh->tag_table, NULL, NULL);
1130 sh->tag_table = NULL;
1132 mlx5_free_table_hash_list(priv);
1136 * Initialize shared data between primary and secondary process.
1138 * A memzone is reserved by primary process and secondary processes attach to
1142 * 0 on success, a negative errno value otherwise and rte_errno is set.
1145 mlx5_init_shared_data(void)
1147 const struct rte_memzone *mz;
1150 rte_spinlock_lock(&mlx5_shared_data_lock);
1151 if (mlx5_shared_data == NULL) {
1152 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
1153 /* Allocate shared memory. */
1154 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
1155 sizeof(*mlx5_shared_data),
1159 "Cannot allocate mlx5 shared data");
1163 mlx5_shared_data = mz->addr;
1164 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
1165 rte_spinlock_init(&mlx5_shared_data->lock);
1167 /* Lookup allocated shared memory. */
1168 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
1171 "Cannot attach mlx5 shared data");
1175 mlx5_shared_data = mz->addr;
1176 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
1180 rte_spinlock_unlock(&mlx5_shared_data_lock);
1185 * Retrieve integer value from environment variable.
1188 * Environment variable name.
1191 * Integer value, 0 if the variable is not set.
1194 mlx5_getenv_int(const char *name)
1196 const char *val = getenv(name);
1204 * Verbs callback to allocate a memory. This function should allocate the space
1205 * according to the size provided residing inside a huge page.
1206 * Please note that all allocation must respect the alignment from libmlx5
1207 * (i.e. currently sysconf(_SC_PAGESIZE)).
1210 * The size in bytes of the memory to allocate.
1212 * A pointer to the callback data.
1215 * Allocated buffer, NULL otherwise and rte_errno is set.
1218 mlx5_alloc_verbs_buf(size_t size, void *data)
1220 struct mlx5_priv *priv = data;
1222 size_t alignment = sysconf(_SC_PAGESIZE);
1223 unsigned int socket = SOCKET_ID_ANY;
1225 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
1226 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
1228 socket = ctrl->socket;
1229 } else if (priv->verbs_alloc_ctx.type ==
1230 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
1231 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
1233 socket = ctrl->socket;
1235 MLX5_ASSERT(data != NULL);
1236 ret = rte_malloc_socket(__func__, size, alignment, socket);
1243 * Verbs callback to free a memory.
1246 * A pointer to the memory to free.
1248 * A pointer to the callback data.
1251 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
1253 MLX5_ASSERT(data != NULL);
1258 * DPDK callback to add udp tunnel port
1261 * A pointer to eth_dev
1262 * @param[in] udp_tunnel
1263 * A pointer to udp tunnel
1266 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1269 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1270 struct rte_eth_udp_tunnel *udp_tunnel)
1272 MLX5_ASSERT(udp_tunnel != NULL);
1273 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1274 udp_tunnel->udp_port == 4789)
1276 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1277 udp_tunnel->udp_port == 4790)
1283 * Initialize process private data structure.
1286 * Pointer to Ethernet device structure.
1289 * 0 on success, a negative errno value otherwise and rte_errno is set.
1292 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1294 struct mlx5_priv *priv = dev->data->dev_private;
1295 struct mlx5_proc_priv *ppriv;
1299 * UAR register table follows the process private structure. BlueFlame
1300 * registers for Tx queues are stored in the table.
1303 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1304 ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
1305 RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1310 ppriv->uar_table_sz = ppriv_size;
1311 dev->process_private = ppriv;
1316 * Un-initialize process private data structure.
1319 * Pointer to Ethernet device structure.
1322 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1324 if (!dev->process_private)
1326 rte_free(dev->process_private);
1327 dev->process_private = NULL;
1331 * DPDK callback to close the device.
1333 * Destroy all queues and objects, free memory.
1336 * Pointer to Ethernet device structure.
1339 mlx5_dev_close(struct rte_eth_dev *dev)
1341 struct mlx5_priv *priv = dev->data->dev_private;
1345 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1347 ((priv->sh->ctx != NULL) ? priv->sh->ctx->device->name : ""));
1348 /* In case mlx5_dev_stop() has not been called. */
1349 mlx5_dev_interrupt_handler_uninstall(dev);
1350 mlx5_dev_interrupt_handler_devx_uninstall(dev);
1352 * If default mreg copy action is removed at the stop stage,
1353 * the search will return none and nothing will be done anymore.
1355 mlx5_flow_stop_default(dev);
1356 mlx5_traffic_disable(dev);
1358 * If all the flows are already flushed in the device stop stage,
1359 * then this will return directly without any action.
1361 mlx5_flow_list_flush(dev, &priv->flows, true);
1362 mlx5_flow_meter_flush(dev, NULL);
1363 /* Free the intermediate buffers for flow creation. */
1364 mlx5_flow_free_intermediate(dev);
1365 /* Prevent crashes when queues are still in use. */
1366 dev->rx_pkt_burst = removed_rx_burst;
1367 dev->tx_pkt_burst = removed_tx_burst;
1369 /* Disable datapath on secondary process. */
1370 mlx5_mp_req_stop_rxtx(dev);
1371 if (priv->rxqs != NULL) {
1372 /* XXX race condition if mlx5_rx_burst() is still running. */
1374 for (i = 0; (i != priv->rxqs_n); ++i)
1375 mlx5_rxq_release(dev, i);
1379 if (priv->txqs != NULL) {
1380 /* XXX race condition if mlx5_tx_burst() is still running. */
1382 for (i = 0; (i != priv->txqs_n); ++i)
1383 mlx5_txq_release(dev, i);
1387 mlx5_proc_priv_uninit(dev);
1388 if (priv->mreg_cp_tbl)
1389 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1390 mlx5_mprq_free_mp(dev);
1391 mlx5_free_shared_dr(priv);
1392 if (priv->rss_conf.rss_key != NULL)
1393 rte_free(priv->rss_conf.rss_key);
1394 if (priv->reta_idx != NULL)
1395 rte_free(priv->reta_idx);
1396 if (priv->config.vf)
1397 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1398 dev->data->mac_addrs,
1399 MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1400 if (priv->nl_socket_route >= 0)
1401 close(priv->nl_socket_route);
1402 if (priv->nl_socket_rdma >= 0)
1403 close(priv->nl_socket_rdma);
1404 if (priv->vmwa_context)
1405 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1406 ret = mlx5_hrxq_verify(dev);
1408 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1409 dev->data->port_id);
1410 ret = mlx5_ind_table_obj_verify(dev);
1412 DRV_LOG(WARNING, "port %u some indirection table still remain",
1413 dev->data->port_id);
1414 ret = mlx5_rxq_obj_verify(dev);
1416 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1417 dev->data->port_id);
1418 ret = mlx5_rxq_verify(dev);
1420 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1421 dev->data->port_id);
1422 ret = mlx5_txq_obj_verify(dev);
1424 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1425 dev->data->port_id);
1426 ret = mlx5_txq_verify(dev);
1428 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1429 dev->data->port_id);
1430 ret = mlx5_flow_verify(dev);
1432 DRV_LOG(WARNING, "port %u some flows still remain",
1433 dev->data->port_id);
1436 * Free the shared context in last turn, because the cleanup
1437 * routines above may use some shared fields, like
1438 * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1439 * ifindex if Netlink fails.
1441 mlx5_free_shared_ibctx(priv->sh);
1444 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1448 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1449 struct mlx5_priv *opriv =
1450 rte_eth_devices[port_id].data->dev_private;
1453 opriv->domain_id != priv->domain_id ||
1454 &rte_eth_devices[port_id] == dev)
1460 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1462 memset(priv, 0, sizeof(*priv));
1463 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1465 * Reset mac_addrs to NULL such that it is not freed as part of
1466 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1467 * it is freed when dev_private is freed.
1469 dev->data->mac_addrs = NULL;
1472 const struct eth_dev_ops mlx5_dev_ops = {
1473 .dev_configure = mlx5_dev_configure,
1474 .dev_start = mlx5_dev_start,
1475 .dev_stop = mlx5_dev_stop,
1476 .dev_set_link_down = mlx5_set_link_down,
1477 .dev_set_link_up = mlx5_set_link_up,
1478 .dev_close = mlx5_dev_close,
1479 .promiscuous_enable = mlx5_promiscuous_enable,
1480 .promiscuous_disable = mlx5_promiscuous_disable,
1481 .allmulticast_enable = mlx5_allmulticast_enable,
1482 .allmulticast_disable = mlx5_allmulticast_disable,
1483 .link_update = mlx5_link_update,
1484 .stats_get = mlx5_stats_get,
1485 .stats_reset = mlx5_stats_reset,
1486 .xstats_get = mlx5_xstats_get,
1487 .xstats_reset = mlx5_xstats_reset,
1488 .xstats_get_names = mlx5_xstats_get_names,
1489 .fw_version_get = mlx5_fw_version_get,
1490 .dev_infos_get = mlx5_dev_infos_get,
1491 .read_clock = mlx5_read_clock,
1492 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1493 .vlan_filter_set = mlx5_vlan_filter_set,
1494 .rx_queue_setup = mlx5_rx_queue_setup,
1495 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1496 .tx_queue_setup = mlx5_tx_queue_setup,
1497 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1498 .rx_queue_release = mlx5_rx_queue_release,
1499 .tx_queue_release = mlx5_tx_queue_release,
1500 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1501 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1502 .mac_addr_remove = mlx5_mac_addr_remove,
1503 .mac_addr_add = mlx5_mac_addr_add,
1504 .mac_addr_set = mlx5_mac_addr_set,
1505 .set_mc_addr_list = mlx5_set_mc_addr_list,
1506 .mtu_set = mlx5_dev_set_mtu,
1507 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1508 .vlan_offload_set = mlx5_vlan_offload_set,
1509 .reta_update = mlx5_dev_rss_reta_update,
1510 .reta_query = mlx5_dev_rss_reta_query,
1511 .rss_hash_update = mlx5_rss_hash_update,
1512 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1513 .filter_ctrl = mlx5_dev_filter_ctrl,
1514 .rx_descriptor_status = mlx5_rx_descriptor_status,
1515 .tx_descriptor_status = mlx5_tx_descriptor_status,
1516 .rxq_info_get = mlx5_rxq_info_get,
1517 .txq_info_get = mlx5_txq_info_get,
1518 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1519 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1520 .rx_queue_count = mlx5_rx_queue_count,
1521 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1522 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1523 .is_removed = mlx5_is_removed,
1524 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add,
1525 .get_module_info = mlx5_get_module_info,
1526 .get_module_eeprom = mlx5_get_module_eeprom,
1527 .hairpin_cap_get = mlx5_hairpin_cap_get,
1528 .mtr_ops_get = mlx5_flow_meter_ops_get,
1531 /* Available operations from secondary process. */
1532 static const struct eth_dev_ops mlx5_dev_sec_ops = {
1533 .stats_get = mlx5_stats_get,
1534 .stats_reset = mlx5_stats_reset,
1535 .xstats_get = mlx5_xstats_get,
1536 .xstats_reset = mlx5_xstats_reset,
1537 .xstats_get_names = mlx5_xstats_get_names,
1538 .fw_version_get = mlx5_fw_version_get,
1539 .dev_infos_get = mlx5_dev_infos_get,
1540 .rx_descriptor_status = mlx5_rx_descriptor_status,
1541 .tx_descriptor_status = mlx5_tx_descriptor_status,
1542 .rxq_info_get = mlx5_rxq_info_get,
1543 .txq_info_get = mlx5_txq_info_get,
1544 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1545 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1546 .get_module_info = mlx5_get_module_info,
1547 .get_module_eeprom = mlx5_get_module_eeprom,
1550 /* Available operations in flow isolated mode. */
1551 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1552 .dev_configure = mlx5_dev_configure,
1553 .dev_start = mlx5_dev_start,
1554 .dev_stop = mlx5_dev_stop,
1555 .dev_set_link_down = mlx5_set_link_down,
1556 .dev_set_link_up = mlx5_set_link_up,
1557 .dev_close = mlx5_dev_close,
1558 .promiscuous_enable = mlx5_promiscuous_enable,
1559 .promiscuous_disable = mlx5_promiscuous_disable,
1560 .allmulticast_enable = mlx5_allmulticast_enable,
1561 .allmulticast_disable = mlx5_allmulticast_disable,
1562 .link_update = mlx5_link_update,
1563 .stats_get = mlx5_stats_get,
1564 .stats_reset = mlx5_stats_reset,
1565 .xstats_get = mlx5_xstats_get,
1566 .xstats_reset = mlx5_xstats_reset,
1567 .xstats_get_names = mlx5_xstats_get_names,
1568 .fw_version_get = mlx5_fw_version_get,
1569 .dev_infos_get = mlx5_dev_infos_get,
1570 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1571 .vlan_filter_set = mlx5_vlan_filter_set,
1572 .rx_queue_setup = mlx5_rx_queue_setup,
1573 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1574 .tx_queue_setup = mlx5_tx_queue_setup,
1575 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1576 .rx_queue_release = mlx5_rx_queue_release,
1577 .tx_queue_release = mlx5_tx_queue_release,
1578 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1579 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1580 .mac_addr_remove = mlx5_mac_addr_remove,
1581 .mac_addr_add = mlx5_mac_addr_add,
1582 .mac_addr_set = mlx5_mac_addr_set,
1583 .set_mc_addr_list = mlx5_set_mc_addr_list,
1584 .mtu_set = mlx5_dev_set_mtu,
1585 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1586 .vlan_offload_set = mlx5_vlan_offload_set,
1587 .filter_ctrl = mlx5_dev_filter_ctrl,
1588 .rx_descriptor_status = mlx5_rx_descriptor_status,
1589 .tx_descriptor_status = mlx5_tx_descriptor_status,
1590 .rxq_info_get = mlx5_rxq_info_get,
1591 .txq_info_get = mlx5_txq_info_get,
1592 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1593 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1594 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1595 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1596 .is_removed = mlx5_is_removed,
1597 .get_module_info = mlx5_get_module_info,
1598 .get_module_eeprom = mlx5_get_module_eeprom,
1599 .hairpin_cap_get = mlx5_hairpin_cap_get,
1600 .mtr_ops_get = mlx5_flow_meter_ops_get,
1604 * Verify and store value for device argument.
1607 * Key argument to verify.
1609 * Value associated with key.
1614 * 0 on success, a negative errno value otherwise and rte_errno is set.
1617 mlx5_args_check(const char *key, const char *val, void *opaque)
1619 struct mlx5_dev_config *config = opaque;
1622 /* No-op, port representors are processed in mlx5_dev_spawn(). */
1623 if (!strcmp(MLX5_REPRESENTOR, key))
1626 tmp = strtoul(val, NULL, 0);
1629 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1632 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1633 config->cqe_comp = !!tmp;
1634 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1635 config->cqe_pad = !!tmp;
1636 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1637 config->hw_padding = !!tmp;
1638 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1639 config->mprq.enabled = !!tmp;
1640 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1641 config->mprq.stride_num_n = tmp;
1642 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1643 config->mprq.stride_size_n = tmp;
1644 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1645 config->mprq.max_memcpy_len = tmp;
1646 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1647 config->mprq.min_rxqs_num = tmp;
1648 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1649 DRV_LOG(WARNING, "%s: deprecated parameter,"
1650 " converted to txq_inline_max", key);
1651 config->txq_inline_max = tmp;
1652 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1653 config->txq_inline_max = tmp;
1654 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1655 config->txq_inline_min = tmp;
1656 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1657 config->txq_inline_mpw = tmp;
1658 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1659 config->txqs_inline = tmp;
1660 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1661 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1662 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1663 config->mps = !!tmp;
1664 } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1665 if (tmp != MLX5_TXDB_CACHED &&
1666 tmp != MLX5_TXDB_NCACHED &&
1667 tmp != MLX5_TXDB_HEURISTIC) {
1668 DRV_LOG(ERR, "invalid Tx doorbell "
1669 "mapping parameter");
1674 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1675 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1676 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1677 DRV_LOG(WARNING, "%s: deprecated parameter,"
1678 " converted to txq_inline_mpw", key);
1679 config->txq_inline_mpw = tmp;
1680 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1681 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1682 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1683 config->rx_vec_en = !!tmp;
1684 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1685 config->l3_vxlan_en = !!tmp;
1686 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1687 config->vf_nl_en = !!tmp;
1688 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1689 config->dv_esw_en = !!tmp;
1690 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1691 config->dv_flow_en = !!tmp;
1692 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1693 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1694 tmp != MLX5_XMETA_MODE_META16 &&
1695 tmp != MLX5_XMETA_MODE_META32) {
1696 DRV_LOG(ERR, "invalid extensive "
1697 "metadata parameter");
1701 config->dv_xmeta_en = tmp;
1702 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1703 config->mr_ext_memseg_en = !!tmp;
1704 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1705 config->max_dump_files_num = tmp;
1706 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1707 config->lro.timeout = tmp;
1708 } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1709 DRV_LOG(DEBUG, "class argument is %s.", val);
1710 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1711 config->log_hp_size = tmp;
1713 DRV_LOG(WARNING, "%s: unknown parameter", key);
1721 * Parse device parameters.
1724 * Pointer to device configuration structure.
1726 * Device arguments structure.
1729 * 0 on success, a negative errno value otherwise and rte_errno is set.
1732 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1734 const char **params = (const char *[]){
1735 MLX5_RXQ_CQE_COMP_EN,
1736 MLX5_RXQ_CQE_PAD_EN,
1737 MLX5_RXQ_PKT_PAD_EN,
1739 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1740 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1741 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1744 MLX5_TXQ_INLINE_MIN,
1745 MLX5_TXQ_INLINE_MAX,
1746 MLX5_TXQ_INLINE_MPW,
1747 MLX5_TXQS_MIN_INLINE,
1750 MLX5_TXQ_MPW_HDR_DSEG_EN,
1751 MLX5_TXQ_MAX_INLINE_LEN,
1760 MLX5_MR_EXT_MEMSEG_EN,
1762 MLX5_MAX_DUMP_FILES_NUM,
1763 MLX5_LRO_TIMEOUT_USEC,
1764 MLX5_CLASS_ARG_NAME,
1768 struct rte_kvargs *kvlist;
1772 if (devargs == NULL)
1774 /* Following UGLY cast is done to pass checkpatch. */
1775 kvlist = rte_kvargs_parse(devargs->args, params);
1776 if (kvlist == NULL) {
1780 /* Process parameters. */
1781 for (i = 0; (params[i] != NULL); ++i) {
1782 if (rte_kvargs_count(kvlist, params[i])) {
1783 ret = rte_kvargs_process(kvlist, params[i],
1784 mlx5_args_check, config);
1787 rte_kvargs_free(kvlist);
1792 rte_kvargs_free(kvlist);
1796 static struct rte_pci_driver mlx5_driver;
1799 * PMD global initialization.
1801 * Independent from individual device, this function initializes global
1802 * per-PMD data structures distinguishing primary and secondary processes.
1803 * Hence, each initialization is called once per a process.
1806 * 0 on success, a negative errno value otherwise and rte_errno is set.
1809 mlx5_init_once(void)
1811 struct mlx5_shared_data *sd;
1812 struct mlx5_local_data *ld = &mlx5_local_data;
1815 if (mlx5_init_shared_data())
1817 sd = mlx5_shared_data;
1819 rte_spinlock_lock(&sd->lock);
1820 switch (rte_eal_process_type()) {
1821 case RTE_PROC_PRIMARY:
1824 LIST_INIT(&sd->mem_event_cb_list);
1825 rte_rwlock_init(&sd->mem_event_rwlock);
1826 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1827 mlx5_mr_mem_event_cb, NULL);
1828 ret = mlx5_mp_init_primary(MLX5_MP_NAME,
1829 mlx5_mp_primary_handle);
1832 sd->init_done = true;
1834 case RTE_PROC_SECONDARY:
1837 ret = mlx5_mp_init_secondary(MLX5_MP_NAME,
1838 mlx5_mp_secondary_handle);
1841 ++sd->secondary_cnt;
1842 ld->init_done = true;
1848 rte_spinlock_unlock(&sd->lock);
1853 * Configures the minimal amount of data to inline into WQE
1854 * while sending packets.
1856 * - the txq_inline_min has the maximal priority, if this
1857 * key is specified in devargs
1858 * - if DevX is enabled the inline mode is queried from the
1859 * device (HCA attributes and NIC vport context if needed).
1860 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1861 * and none (0 bytes) for other NICs
1864 * Verbs device parameters (name, port, switch_info) to spawn.
1866 * Device configuration parameters.
1869 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1870 struct mlx5_dev_config *config)
1872 if (config->txq_inline_min != MLX5_ARG_UNSET) {
1873 /* Application defines size of inlined data explicitly. */
1874 switch (spawn->pci_dev->id.device_id) {
1875 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1876 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1877 if (config->txq_inline_min <
1878 (int)MLX5_INLINE_HSIZE_L2) {
1880 "txq_inline_mix aligned to minimal"
1881 " ConnectX-4 required value %d",
1882 (int)MLX5_INLINE_HSIZE_L2);
1883 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1889 if (config->hca_attr.eth_net_offloads) {
1890 /* We have DevX enabled, inline mode queried successfully. */
1891 switch (config->hca_attr.wqe_inline_mode) {
1892 case MLX5_CAP_INLINE_MODE_L2:
1893 /* outer L2 header must be inlined. */
1894 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1896 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1897 /* No inline data are required by NIC. */
1898 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1899 config->hw_vlan_insert =
1900 config->hca_attr.wqe_vlan_insert;
1901 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1903 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1904 /* inline mode is defined by NIC vport context. */
1905 if (!config->hca_attr.eth_virt)
1907 switch (config->hca_attr.vport_inline_mode) {
1908 case MLX5_INLINE_MODE_NONE:
1909 config->txq_inline_min =
1910 MLX5_INLINE_HSIZE_NONE;
1912 case MLX5_INLINE_MODE_L2:
1913 config->txq_inline_min =
1914 MLX5_INLINE_HSIZE_L2;
1916 case MLX5_INLINE_MODE_IP:
1917 config->txq_inline_min =
1918 MLX5_INLINE_HSIZE_L3;
1920 case MLX5_INLINE_MODE_TCP_UDP:
1921 config->txq_inline_min =
1922 MLX5_INLINE_HSIZE_L4;
1924 case MLX5_INLINE_MODE_INNER_L2:
1925 config->txq_inline_min =
1926 MLX5_INLINE_HSIZE_INNER_L2;
1928 case MLX5_INLINE_MODE_INNER_IP:
1929 config->txq_inline_min =
1930 MLX5_INLINE_HSIZE_INNER_L3;
1932 case MLX5_INLINE_MODE_INNER_TCP_UDP:
1933 config->txq_inline_min =
1934 MLX5_INLINE_HSIZE_INNER_L4;
1940 * We get here if we are unable to deduce
1941 * inline data size with DevX. Try PCI ID
1942 * to determine old NICs.
1944 switch (spawn->pci_dev->id.device_id) {
1945 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1946 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1947 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1948 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1949 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1950 config->hw_vlan_insert = 0;
1952 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1953 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1954 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1955 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1957 * These NICs support VLAN insertion from WQE and
1958 * report the wqe_vlan_insert flag. But there is the bug
1959 * and PFC control may be broken, so disable feature.
1961 config->hw_vlan_insert = 0;
1962 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1965 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1969 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1973 * Configures the metadata mask fields in the shared context.
1976 * Pointer to Ethernet device.
1979 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1981 struct mlx5_priv *priv = dev->data->dev_private;
1982 struct mlx5_ibv_shared *sh = priv->sh;
1983 uint32_t meta, mark, reg_c0;
1985 reg_c0 = ~priv->vport_meta_mask;
1986 switch (priv->config.dv_xmeta_en) {
1987 case MLX5_XMETA_MODE_LEGACY:
1989 mark = MLX5_FLOW_MARK_MASK;
1991 case MLX5_XMETA_MODE_META16:
1992 meta = reg_c0 >> rte_bsf32(reg_c0);
1993 mark = MLX5_FLOW_MARK_MASK;
1995 case MLX5_XMETA_MODE_META32:
1997 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2005 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2006 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
2007 sh->dv_mark_mask, mark);
2009 sh->dv_mark_mask = mark;
2010 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2011 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
2012 sh->dv_meta_mask, meta);
2014 sh->dv_meta_mask = meta;
2015 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2016 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
2017 sh->dv_meta_mask, reg_c0);
2019 sh->dv_regc0_mask = reg_c0;
2020 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2021 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2022 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2023 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2027 * Allocate page of door-bells and register it using DevX API.
2030 * Pointer to Ethernet device.
2033 * Pointer to new page on success, NULL otherwise.
2035 static struct mlx5_devx_dbr_page *
2036 mlx5_alloc_dbr_page(struct rte_eth_dev *dev)
2038 struct mlx5_priv *priv = dev->data->dev_private;
2039 struct mlx5_devx_dbr_page *page;
2041 /* Allocate space for door-bell page and management data. */
2042 page = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_devx_dbr_page),
2043 RTE_CACHE_LINE_SIZE, dev->device->numa_node);
2045 DRV_LOG(ERR, "port %u cannot allocate dbr page",
2046 dev->data->port_id);
2049 /* Register allocated memory. */
2050 page->umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, page->dbrs,
2051 MLX5_DBR_PAGE_SIZE, 0);
2053 DRV_LOG(ERR, "port %u cannot umem reg dbr page",
2054 dev->data->port_id);
2062 * Find the next available door-bell, allocate new page if needed.
2065 * Pointer to Ethernet device.
2066 * @param [out] dbr_page
2067 * Door-bell page containing the page data.
2070 * Door-bell address offset on success, a negative error value otherwise.
2073 mlx5_get_dbr(struct rte_eth_dev *dev, struct mlx5_devx_dbr_page **dbr_page)
2075 struct mlx5_priv *priv = dev->data->dev_private;
2076 struct mlx5_devx_dbr_page *page = NULL;
2079 LIST_FOREACH(page, &priv->dbrpgs, next)
2080 if (page->dbr_count < MLX5_DBR_PER_PAGE)
2082 if (!page) { /* No page with free door-bell exists. */
2083 page = mlx5_alloc_dbr_page(dev);
2084 if (!page) /* Failed to allocate new page. */
2086 LIST_INSERT_HEAD(&priv->dbrpgs, page, next);
2088 /* Loop to find bitmap part with clear bit. */
2090 i < MLX5_DBR_BITMAP_SIZE && page->dbr_bitmap[i] == UINT64_MAX;
2093 /* Find the first clear bit. */
2094 j = rte_bsf64(~page->dbr_bitmap[i]);
2095 MLX5_ASSERT(i < (MLX5_DBR_PER_PAGE / 64));
2096 page->dbr_bitmap[i] |= (1 << j);
2099 return (((i * 64) + j) * sizeof(uint64_t));
2103 * Release a door-bell record.
2106 * Pointer to Ethernet device.
2107 * @param [in] umem_id
2108 * UMEM ID of page containing the door-bell record to release.
2109 * @param [in] offset
2110 * Offset of door-bell record in page.
2113 * 0 on success, a negative error value otherwise.
2116 mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id, uint64_t offset)
2118 struct mlx5_priv *priv = dev->data->dev_private;
2119 struct mlx5_devx_dbr_page *page = NULL;
2122 LIST_FOREACH(page, &priv->dbrpgs, next)
2123 /* Find the page this address belongs to. */
2124 if (page->umem->umem_id == umem_id)
2129 if (!page->dbr_count) {
2130 /* Page not used, free it and remove from list. */
2131 LIST_REMOVE(page, next);
2133 ret = -mlx5_glue->devx_umem_dereg(page->umem);
2136 /* Mark in bitmap that this door-bell is not in use. */
2137 offset /= MLX5_DBR_SIZE;
2138 int i = offset / 64;
2139 int j = offset % 64;
2141 page->dbr_bitmap[i] &= ~(1 << j);
2147 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2149 static const char *const dynf_names[] = {
2150 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2151 RTE_MBUF_DYNFLAG_METADATA_NAME
2155 if (n < RTE_DIM(dynf_names))
2157 for (i = 0; i < RTE_DIM(dynf_names); i++) {
2158 if (names[i] == NULL)
2160 strcpy(names[i], dynf_names[i]);
2162 return RTE_DIM(dynf_names);
2166 * Check sibling device configurations.
2168 * Sibling devices sharing the Infiniband device context
2169 * should have compatible configurations. This regards
2170 * representors and bonding slaves.
2173 * Private device descriptor.
2175 * Configuration of the device is going to be created.
2178 * 0 on success, EINVAL otherwise
2181 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2182 struct mlx5_dev_config *config)
2184 struct mlx5_ibv_shared *sh = priv->sh;
2185 struct mlx5_dev_config *sh_conf = NULL;
2189 /* Nothing to compare for the single/first device. */
2190 if (sh->refcnt == 1)
2192 /* Find the device with shared context. */
2193 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2194 struct mlx5_priv *opriv =
2195 rte_eth_devices[port_id].data->dev_private;
2197 if (opriv && opriv != priv && opriv->sh == sh) {
2198 sh_conf = &opriv->config;
2204 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2205 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2206 " for shared %s context", sh->ibdev_name);
2210 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2211 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2212 " for shared %s context", sh->ibdev_name);
2219 * Spawn an Ethernet device from Verbs information.
2222 * Backing DPDK device.
2224 * Verbs device parameters (name, port, switch_info) to spawn.
2226 * Device configuration parameters.
2229 * A valid Ethernet device object on success, NULL otherwise and rte_errno
2230 * is set. The following errors are defined:
2232 * EBUSY: device is not supposed to be spawned.
2233 * EEXIST: device is already spawned
2235 static struct rte_eth_dev *
2236 mlx5_dev_spawn(struct rte_device *dpdk_dev,
2237 struct mlx5_dev_spawn_data *spawn,
2238 struct mlx5_dev_config config)
2240 const struct mlx5_switch_info *switch_info = &spawn->info;
2241 struct mlx5_ibv_shared *sh = NULL;
2242 struct ibv_port_attr port_attr;
2243 struct mlx5dv_context dv_attr = { .comp_mask = 0 };
2244 struct rte_eth_dev *eth_dev = NULL;
2245 struct mlx5_priv *priv = NULL;
2247 unsigned int hw_padding = 0;
2249 unsigned int cqe_comp;
2250 unsigned int cqe_pad = 0;
2251 unsigned int tunnel_en = 0;
2252 unsigned int mpls_en = 0;
2253 unsigned int swp = 0;
2254 unsigned int mprq = 0;
2255 unsigned int mprq_min_stride_size_n = 0;
2256 unsigned int mprq_max_stride_size_n = 0;
2257 unsigned int mprq_min_stride_num_n = 0;
2258 unsigned int mprq_max_stride_num_n = 0;
2259 struct rte_ether_addr mac;
2260 char name[RTE_ETH_NAME_MAX_LEN];
2261 int own_domain_id = 0;
2264 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
2265 struct mlx5dv_devx_port devx_port = { .comp_mask = 0 };
2268 /* Determine if this port representor is supposed to be spawned. */
2269 if (switch_info->representor && dpdk_dev->devargs) {
2270 struct rte_eth_devargs eth_da;
2272 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, ð_da);
2275 DRV_LOG(ERR, "failed to process device arguments: %s",
2276 strerror(rte_errno));
2279 for (i = 0; i < eth_da.nb_representor_ports; ++i)
2280 if (eth_da.representor_ports[i] ==
2281 (uint16_t)switch_info->port_name)
2283 if (i == eth_da.nb_representor_ports) {
2288 /* Build device name. */
2289 if (spawn->pf_bond < 0) {
2290 /* Single device. */
2291 if (!switch_info->representor)
2292 strlcpy(name, dpdk_dev->name, sizeof(name));
2294 snprintf(name, sizeof(name), "%s_representor_%u",
2295 dpdk_dev->name, switch_info->port_name);
2297 /* Bonding device. */
2298 if (!switch_info->representor)
2299 snprintf(name, sizeof(name), "%s_%s",
2300 dpdk_dev->name, spawn->ibv_dev->name);
2302 snprintf(name, sizeof(name), "%s_%s_representor_%u",
2303 dpdk_dev->name, spawn->ibv_dev->name,
2304 switch_info->port_name);
2306 /* check if the device is already spawned */
2307 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
2311 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
2312 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
2313 struct mlx5_mp_id mp_id;
2315 eth_dev = rte_eth_dev_attach_secondary(name);
2316 if (eth_dev == NULL) {
2317 DRV_LOG(ERR, "can not attach rte ethdev");
2321 eth_dev->device = dpdk_dev;
2322 eth_dev->dev_ops = &mlx5_dev_sec_ops;
2323 err = mlx5_proc_priv_init(eth_dev);
2326 mp_id.port_id = eth_dev->data->port_id;
2327 strlcpy(mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);
2328 /* Receive command fd from primary process */
2329 err = mlx5_mp_req_verbs_cmd_fd(&mp_id);
2332 /* Remap UAR for Tx queues. */
2333 err = mlx5_tx_uar_init_secondary(eth_dev, err);
2337 * Ethdev pointer is still required as input since
2338 * the primary device is not accessible from the
2339 * secondary process.
2341 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev);
2342 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev);
2346 * Some parameters ("tx_db_nc" in particularly) are needed in
2347 * advance to create dv/verbs device context. We proceed the
2348 * devargs here to get ones, and later proceed devargs again
2349 * to override some hardware settings.
2351 err = mlx5_args(&config, dpdk_dev->devargs);
2354 DRV_LOG(ERR, "failed to process device arguments: %s",
2355 strerror(rte_errno));
2358 sh = mlx5_alloc_shared_ibctx(spawn, &config);
2361 config.devx = sh->devx;
2362 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR
2363 config.dest_tir = 1;
2365 #ifdef HAVE_IBV_MLX5_MOD_SWP
2366 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
2369 * Multi-packet send is supported by ConnectX-4 Lx PF as well
2370 * as all ConnectX-5 devices.
2372 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2373 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
2375 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
2376 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
2378 mlx5_glue->dv_query_device(sh->ctx, &dv_attr);
2379 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
2380 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
2381 DRV_LOG(DEBUG, "enhanced MPW is supported");
2382 mps = MLX5_MPW_ENHANCED;
2384 DRV_LOG(DEBUG, "MPW is supported");
2388 DRV_LOG(DEBUG, "MPW isn't supported");
2389 mps = MLX5_MPW_DISABLED;
2391 #ifdef HAVE_IBV_MLX5_MOD_SWP
2392 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
2393 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
2394 DRV_LOG(DEBUG, "SWP support: %u", swp);
2397 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
2398 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
2399 struct mlx5dv_striding_rq_caps mprq_caps =
2400 dv_attr.striding_rq_caps;
2402 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
2403 mprq_caps.min_single_stride_log_num_of_bytes);
2404 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
2405 mprq_caps.max_single_stride_log_num_of_bytes);
2406 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
2407 mprq_caps.min_single_wqe_log_num_of_strides);
2408 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
2409 mprq_caps.max_single_wqe_log_num_of_strides);
2410 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
2411 mprq_caps.supported_qpts);
2412 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
2414 mprq_min_stride_size_n =
2415 mprq_caps.min_single_stride_log_num_of_bytes;
2416 mprq_max_stride_size_n =
2417 mprq_caps.max_single_stride_log_num_of_bytes;
2418 mprq_min_stride_num_n =
2419 mprq_caps.min_single_wqe_log_num_of_strides;
2420 mprq_max_stride_num_n =
2421 mprq_caps.max_single_wqe_log_num_of_strides;
2424 if (RTE_CACHE_LINE_SIZE == 128 &&
2425 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
2429 config.cqe_comp = cqe_comp;
2430 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
2431 /* Whether device supports 128B Rx CQE padding. */
2432 cqe_pad = RTE_CACHE_LINE_SIZE == 128 &&
2433 (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD);
2435 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2436 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
2437 tunnel_en = ((dv_attr.tunnel_offloads_caps &
2438 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
2439 (dv_attr.tunnel_offloads_caps &
2440 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) &&
2441 (dv_attr.tunnel_offloads_caps &
2442 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE));
2444 DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
2445 tunnel_en ? "" : "not ");
2448 "tunnel offloading disabled due to old OFED/rdma-core version");
2450 config.tunnel_en = tunnel_en;
2451 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
2452 mpls_en = ((dv_attr.tunnel_offloads_caps &
2453 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
2454 (dv_attr.tunnel_offloads_caps &
2455 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
2456 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
2457 mpls_en ? "" : "not ");
2459 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
2460 " old OFED/rdma-core version or firmware configuration");
2462 config.mpls_en = mpls_en;
2463 /* Check port status. */
2464 err = mlx5_glue->query_port(sh->ctx, spawn->ibv_port, &port_attr);
2466 DRV_LOG(ERR, "port query failed: %s", strerror(err));
2469 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
2470 DRV_LOG(ERR, "port is not configured in Ethernet mode");
2474 if (port_attr.state != IBV_PORT_ACTIVE)
2475 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)",
2476 mlx5_glue->port_state_str(port_attr.state),
2478 /* Allocate private eth device data. */
2479 priv = rte_zmalloc("ethdev private structure",
2481 RTE_CACHE_LINE_SIZE);
2483 DRV_LOG(ERR, "priv allocation failure");
2488 priv->ibv_port = spawn->ibv_port;
2489 priv->pci_dev = spawn->pci_dev;
2490 priv->mtu = RTE_ETHER_MTU;
2491 priv->mp_id.port_id = port_id;
2492 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);
2494 /* Initialize UAR access locks for 32bit implementations. */
2495 rte_spinlock_init(&priv->uar_lock_cq);
2496 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
2497 rte_spinlock_init(&priv->uar_lock[i]);
2499 /* Some internal functions rely on Netlink sockets, open them now. */
2500 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA);
2501 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE);
2502 priv->representor = !!switch_info->representor;
2503 priv->master = !!switch_info->master;
2504 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
2505 priv->vport_meta_tag = 0;
2506 priv->vport_meta_mask = 0;
2507 priv->pf_bond = spawn->pf_bond;
2508 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
2510 * The DevX port query API is implemented. E-Switch may use
2511 * either vport or reg_c[0] metadata register to match on
2512 * vport index. The engaged part of metadata register is
2515 if (switch_info->representor || switch_info->master) {
2516 devx_port.comp_mask = MLX5DV_DEVX_PORT_VPORT |
2517 MLX5DV_DEVX_PORT_MATCH_REG_C_0;
2518 err = mlx5_glue->devx_port_query(sh->ctx, spawn->ibv_port,
2522 "can't query devx port %d on device %s",
2523 spawn->ibv_port, spawn->ibv_dev->name);
2524 devx_port.comp_mask = 0;
2527 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_MATCH_REG_C_0) {
2528 priv->vport_meta_tag = devx_port.reg_c_0.value;
2529 priv->vport_meta_mask = devx_port.reg_c_0.mask;
2530 if (!priv->vport_meta_mask) {
2531 DRV_LOG(ERR, "vport zero mask for port %d"
2532 " on bonding device %s",
2533 spawn->ibv_port, spawn->ibv_dev->name);
2537 if (priv->vport_meta_tag & ~priv->vport_meta_mask) {
2538 DRV_LOG(ERR, "invalid vport tag for port %d"
2539 " on bonding device %s",
2540 spawn->ibv_port, spawn->ibv_dev->name);
2545 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_VPORT) {
2546 priv->vport_id = devx_port.vport_num;
2547 } else if (spawn->pf_bond >= 0) {
2548 DRV_LOG(ERR, "can't deduce vport index for port %d"
2549 " on bonding device %s",
2550 spawn->ibv_port, spawn->ibv_dev->name);
2554 /* Suppose vport index in compatible way. */
2555 priv->vport_id = switch_info->representor ?
2556 switch_info->port_name + 1 : -1;
2560 * Kernel/rdma_core support single E-Switch per PF configurations
2561 * only and vport_id field contains the vport index for
2562 * associated VF, which is deduced from representor port name.
2563 * For example, let's have the IB device port 10, it has
2564 * attached network device eth0, which has port name attribute
2565 * pf0vf2, we can deduce the VF number as 2, and set vport index
2566 * as 3 (2+1). This assigning schema should be changed if the
2567 * multiple E-Switch instances per PF configurations or/and PCI
2568 * subfunctions are added.
2570 priv->vport_id = switch_info->representor ?
2571 switch_info->port_name + 1 : -1;
2573 /* representor_id field keeps the unmodified VF index. */
2574 priv->representor_id = switch_info->representor ?
2575 switch_info->port_name : -1;
2577 * Look for sibling devices in order to reuse their switch domain
2578 * if any, otherwise allocate one.
2580 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2581 const struct mlx5_priv *opriv =
2582 rte_eth_devices[port_id].data->dev_private;
2585 opriv->sh != priv->sh ||
2587 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
2589 priv->domain_id = opriv->domain_id;
2592 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
2593 err = rte_eth_switch_domain_alloc(&priv->domain_id);
2596 DRV_LOG(ERR, "unable to allocate switch domain: %s",
2597 strerror(rte_errno));
2602 /* Override some values set by hardware configuration. */
2603 mlx5_args(&config, dpdk_dev->devargs);
2604 err = mlx5_dev_check_sibling_config(priv, &config);
2607 config.hw_csum = !!(sh->device_attr.device_cap_flags_ex &
2608 IBV_DEVICE_RAW_IP_CSUM);
2609 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
2610 (config.hw_csum ? "" : "not "));
2611 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \
2612 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
2613 DRV_LOG(DEBUG, "counters are not supported");
2615 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR)
2616 if (config.dv_flow_en) {
2617 DRV_LOG(WARNING, "DV flow is not supported");
2618 config.dv_flow_en = 0;
2621 config.ind_table_max_size =
2622 sh->device_attr.rss_caps.max_rwq_indirection_table_size;
2624 * Remove this check once DPDK supports larger/variable
2625 * indirection tables.
2627 if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
2628 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
2629 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
2630 config.ind_table_max_size);
2631 config.hw_vlan_strip = !!(sh->device_attr.raw_packet_caps &
2632 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
2633 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
2634 (config.hw_vlan_strip ? "" : "not "));
2635 config.hw_fcs_strip = !!(sh->device_attr.raw_packet_caps &
2636 IBV_RAW_PACKET_CAP_SCATTER_FCS);
2637 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
2638 (config.hw_fcs_strip ? "" : "not "));
2639 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
2640 hw_padding = !!sh->device_attr.rx_pad_end_addr_align;
2641 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
2642 hw_padding = !!(sh->device_attr.device_cap_flags_ex &
2643 IBV_DEVICE_PCI_WRITE_END_PADDING);
2645 if (config.hw_padding && !hw_padding) {
2646 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
2647 config.hw_padding = 0;
2648 } else if (config.hw_padding) {
2649 DRV_LOG(DEBUG, "Rx end alignment padding is enabled");
2651 config.tso = (sh->device_attr.tso_caps.max_tso > 0 &&
2652 (sh->device_attr.tso_caps.supported_qpts &
2653 (1 << IBV_QPT_RAW_PACKET)));
2655 config.tso_max_payload_sz = sh->device_attr.tso_caps.max_tso;
2657 * MPW is disabled by default, while the Enhanced MPW is enabled
2660 if (config.mps == MLX5_ARG_UNSET)
2661 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED :
2664 config.mps = config.mps ? mps : MLX5_MPW_DISABLED;
2665 DRV_LOG(INFO, "%sMPS is %s",
2666 config.mps == MLX5_MPW_ENHANCED ? "enhanced " :
2667 config.mps == MLX5_MPW ? "legacy " : "",
2668 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
2669 if (config.cqe_comp && !cqe_comp) {
2670 DRV_LOG(WARNING, "Rx CQE compression isn't supported");
2671 config.cqe_comp = 0;
2673 if (config.cqe_pad && !cqe_pad) {
2674 DRV_LOG(WARNING, "Rx CQE padding isn't supported");
2676 } else if (config.cqe_pad) {
2677 DRV_LOG(INFO, "Rx CQE padding is enabled");
2680 priv->counter_fallback = 0;
2681 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config.hca_attr);
2686 if (!config.hca_attr.flow_counters_dump)
2687 priv->counter_fallback = 1;
2688 #ifndef HAVE_IBV_DEVX_ASYNC
2689 priv->counter_fallback = 1;
2691 if (priv->counter_fallback)
2692 DRV_LOG(INFO, "Use fall-back DV counter management");
2693 /* Check for LRO support. */
2694 if (config.dest_tir && config.hca_attr.lro_cap &&
2695 config.dv_flow_en) {
2696 /* TBD check tunnel lro caps. */
2697 config.lro.supported = config.hca_attr.lro_cap;
2698 DRV_LOG(DEBUG, "Device supports LRO");
2700 * If LRO timeout is not configured by application,
2701 * use the minimal supported value.
2703 if (!config.lro.timeout)
2704 config.lro.timeout =
2705 config.hca_attr.lro_timer_supported_periods[0];
2706 DRV_LOG(DEBUG, "LRO session timeout set to %d usec",
2707 config.lro.timeout);
2709 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER)
2710 if (config.hca_attr.qos.sup && config.hca_attr.qos.srtcm_sup &&
2711 config.dv_flow_en) {
2712 uint8_t reg_c_mask =
2713 config.hca_attr.qos.flow_meter_reg_c_ids;
2715 * Meter needs two REG_C's for color match and pre-sfx
2716 * flow match. Here get the REG_C for color match.
2717 * REG_C_0 and REG_C_1 is reserved for metadata feature.
2720 if (__builtin_popcount(reg_c_mask) < 1) {
2722 DRV_LOG(WARNING, "No available register for"
2725 priv->mtr_color_reg = ffs(reg_c_mask) - 1 +
2728 priv->mtr_reg_share =
2729 config.hca_attr.qos.flow_meter_reg_share;
2730 DRV_LOG(DEBUG, "The REG_C meter uses is %d",
2731 priv->mtr_color_reg);
2736 if (config.mprq.enabled && mprq) {
2737 if (config.mprq.stride_num_n &&
2738 (config.mprq.stride_num_n > mprq_max_stride_num_n ||
2739 config.mprq.stride_num_n < mprq_min_stride_num_n)) {
2740 config.mprq.stride_num_n =
2741 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
2742 mprq_min_stride_num_n),
2743 mprq_max_stride_num_n);
2745 "the number of strides"
2746 " for Multi-Packet RQ is out of range,"
2747 " setting default value (%u)",
2748 1 << config.mprq.stride_num_n);
2750 if (config.mprq.stride_size_n &&
2751 (config.mprq.stride_size_n > mprq_max_stride_size_n ||
2752 config.mprq.stride_size_n < mprq_min_stride_size_n)) {
2753 config.mprq.stride_size_n =
2754 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N,
2755 mprq_min_stride_size_n),
2756 mprq_max_stride_size_n);
2758 "the size of a stride"
2759 " for Multi-Packet RQ is out of range,"
2760 " setting default value (%u)",
2761 1 << config.mprq.stride_size_n);
2763 config.mprq.min_stride_size_n = mprq_min_stride_size_n;
2764 config.mprq.max_stride_size_n = mprq_max_stride_size_n;
2765 } else if (config.mprq.enabled && !mprq) {
2766 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
2767 config.mprq.enabled = 0;
2769 if (config.max_dump_files_num == 0)
2770 config.max_dump_files_num = 128;
2771 eth_dev = rte_eth_dev_allocate(name);
2772 if (eth_dev == NULL) {
2773 DRV_LOG(ERR, "can not allocate rte ethdev");
2777 /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */
2778 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2779 if (priv->representor) {
2780 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
2781 eth_dev->data->representor_id = priv->representor_id;
2784 * Store associated network device interface index. This index
2785 * is permanent throughout the lifetime of device. So, we may store
2786 * the ifindex here and use the cached value further.
2788 MLX5_ASSERT(spawn->ifindex);
2789 priv->if_index = spawn->ifindex;
2790 eth_dev->data->dev_private = priv;
2791 priv->dev_data = eth_dev->data;
2792 eth_dev->data->mac_addrs = priv->mac;
2793 eth_dev->device = dpdk_dev;
2794 /* Configure the first MAC address by default. */
2795 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
2797 "port %u cannot get MAC address, is mlx5_en"
2798 " loaded? (errno: %s)",
2799 eth_dev->data->port_id, strerror(rte_errno));
2804 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
2805 eth_dev->data->port_id,
2806 mac.addr_bytes[0], mac.addr_bytes[1],
2807 mac.addr_bytes[2], mac.addr_bytes[3],
2808 mac.addr_bytes[4], mac.addr_bytes[5]);
2809 #ifdef RTE_LIBRTE_MLX5_DEBUG
2811 char ifname[IF_NAMESIZE];
2813 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
2814 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
2815 eth_dev->data->port_id, ifname);
2817 DRV_LOG(DEBUG, "port %u ifname is unknown",
2818 eth_dev->data->port_id);
2821 /* Get actual MTU if possible. */
2822 err = mlx5_get_mtu(eth_dev, &priv->mtu);
2827 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
2829 /* Initialize burst functions to prevent crashes before link-up. */
2830 eth_dev->rx_pkt_burst = removed_rx_burst;
2831 eth_dev->tx_pkt_burst = removed_tx_burst;
2832 eth_dev->dev_ops = &mlx5_dev_ops;
2833 /* Register MAC address. */
2834 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
2835 if (config.vf && config.vf_nl_en)
2836 mlx5_nl_mac_addr_sync(priv->nl_socket_route,
2837 mlx5_ifindex(eth_dev),
2838 eth_dev->data->mac_addrs,
2839 MLX5_MAX_MAC_ADDRESSES);
2840 TAILQ_INIT(&priv->flows);
2841 TAILQ_INIT(&priv->ctrl_flows);
2842 TAILQ_INIT(&priv->flow_meters);
2843 TAILQ_INIT(&priv->flow_meter_profiles);
2844 /* Hint libmlx5 to use PMD allocator for data plane resources */
2845 struct mlx5dv_ctx_allocators alctr = {
2846 .alloc = &mlx5_alloc_verbs_buf,
2847 .free = &mlx5_free_verbs_buf,
2850 mlx5_glue->dv_set_context_attr(sh->ctx,
2851 MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
2852 (void *)((uintptr_t)&alctr));
2853 /* Bring Ethernet device up. */
2854 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
2855 eth_dev->data->port_id);
2856 mlx5_set_link_up(eth_dev);
2858 * Even though the interrupt handler is not installed yet,
2859 * interrupts will still trigger on the async_fd from
2860 * Verbs context returned by ibv_open_device().
2862 mlx5_link_update(eth_dev, 0);
2863 #ifdef HAVE_MLX5DV_DR_ESWITCH
2864 if (!(config.hca_attr.eswitch_manager && config.dv_flow_en &&
2865 (switch_info->representor || switch_info->master)))
2866 config.dv_esw_en = 0;
2868 config.dv_esw_en = 0;
2870 /* Detect minimal data bytes to inline. */
2871 mlx5_set_min_inline(spawn, &config);
2872 /* Store device configuration on private structure. */
2873 priv->config = config;
2874 /* Create context for virtual machine VLAN workaround. */
2875 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex);
2876 if (config.dv_flow_en) {
2877 err = mlx5_alloc_shared_dr(priv);
2881 * RSS id is shared with meter flow id. Meter flow id can only
2882 * use the 24 MSB of the register.
2884 priv->qrss_id_pool = mlx5_flow_id_pool_alloc(UINT32_MAX >>
2885 MLX5_MTR_COLOR_BITS);
2886 if (!priv->qrss_id_pool) {
2887 DRV_LOG(ERR, "can't create flow id pool");
2892 /* Supported Verbs flow priority number detection. */
2893 err = mlx5_flow_discover_priorities(eth_dev);
2898 priv->config.flow_prio = err;
2899 if (!priv->config.dv_esw_en &&
2900 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2901 DRV_LOG(WARNING, "metadata mode %u is not supported "
2902 "(no E-Switch)", priv->config.dv_xmeta_en);
2903 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY;
2905 mlx5_set_metadata_mask(eth_dev);
2906 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
2907 !priv->sh->dv_regc0_mask) {
2908 DRV_LOG(ERR, "metadata mode %u is not supported "
2909 "(no metadata reg_c[0] is available)",
2910 priv->config.dv_xmeta_en);
2915 * Allocate the buffer for flow creating, just once.
2916 * The allocation must be done before any flow creating.
2918 mlx5_flow_alloc_intermediate(eth_dev);
2919 /* Query availibility of metadata reg_c's. */
2920 err = mlx5_flow_discover_mreg_c(eth_dev);
2925 if (!mlx5_flow_ext_mreg_supported(eth_dev)) {
2927 "port %u extensive metadata register is not supported",
2928 eth_dev->data->port_id);
2929 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2930 DRV_LOG(ERR, "metadata mode %u is not supported "
2931 "(no metadata registers available)",
2932 priv->config.dv_xmeta_en);
2937 if (priv->config.dv_flow_en &&
2938 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
2939 mlx5_flow_ext_mreg_supported(eth_dev) &&
2940 priv->sh->dv_regc0_mask) {
2941 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME,
2942 MLX5_FLOW_MREG_HTABLE_SZ);
2943 if (!priv->mreg_cp_tbl) {
2951 if (priv->mreg_cp_tbl)
2952 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
2954 mlx5_free_shared_dr(priv);
2955 if (priv->nl_socket_route >= 0)
2956 close(priv->nl_socket_route);
2957 if (priv->nl_socket_rdma >= 0)
2958 close(priv->nl_socket_rdma);
2959 if (priv->vmwa_context)
2960 mlx5_vlan_vmwa_exit(priv->vmwa_context);
2961 if (priv->qrss_id_pool)
2962 mlx5_flow_id_pool_release(priv->qrss_id_pool);
2964 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
2966 if (eth_dev != NULL)
2967 eth_dev->data->dev_private = NULL;
2969 if (eth_dev != NULL) {
2970 /* mac_addrs must not be freed alone because part of dev_private */
2971 eth_dev->data->mac_addrs = NULL;
2972 rte_eth_dev_release_port(eth_dev);
2975 mlx5_free_shared_ibctx(sh);
2976 MLX5_ASSERT(err > 0);
2982 * Comparison callback to sort device data.
2984 * This is meant to be used with qsort().
2987 * Pointer to pointer to first data object.
2989 * Pointer to pointer to second data object.
2992 * 0 if both objects are equal, less than 0 if the first argument is less
2993 * than the second, greater than 0 otherwise.
2996 mlx5_dev_spawn_data_cmp(const void *a, const void *b)
2998 const struct mlx5_switch_info *si_a =
2999 &((const struct mlx5_dev_spawn_data *)a)->info;
3000 const struct mlx5_switch_info *si_b =
3001 &((const struct mlx5_dev_spawn_data *)b)->info;
3004 /* Master device first. */
3005 ret = si_b->master - si_a->master;
3008 /* Then representor devices. */
3009 ret = si_b->representor - si_a->representor;
3012 /* Unidentified devices come last in no specific order. */
3013 if (!si_a->representor)
3015 /* Order representors by name. */
3016 return si_a->port_name - si_b->port_name;
3020 * Match PCI information for possible slaves of bonding device.
3022 * @param[in] ibv_dev
3023 * Pointer to Infiniband device structure.
3024 * @param[in] pci_dev
3025 * Pointer to PCI device structure to match PCI address.
3026 * @param[in] nl_rdma
3027 * Netlink RDMA group socket handle.
3030 * negative value if no bonding device found, otherwise
3031 * positive index of slave PF in bonding.
3034 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev,
3035 const struct rte_pci_device *pci_dev,
3038 char ifname[IF_NAMESIZE + 1];
3039 unsigned int ifindex;
3045 * Try to get master device name. If something goes
3046 * wrong suppose the lack of kernel support and no
3051 if (!strstr(ibv_dev->name, "bond"))
3053 np = mlx5_nl_portnum(nl_rdma, ibv_dev->name);
3057 * The Master device might not be on the predefined
3058 * port (not on port index 1, it is not garanted),
3059 * we have to scan all Infiniband device port and
3062 for (i = 1; i <= np; ++i) {
3063 /* Check whether Infiniband port is populated. */
3064 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i);
3067 if (!if_indextoname(ifindex, ifname))
3069 /* Try to read bonding slave names from sysfs. */
3071 "/sys/class/net/%s/master/bonding/slaves", ifname);
3072 file = fopen(slaves, "r");
3078 /* Use safe format to check maximal buffer length. */
3079 MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE);
3080 while (fscanf(file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) {
3081 char tmp_str[IF_NAMESIZE + 32];
3082 struct rte_pci_addr pci_addr;
3083 struct mlx5_switch_info info;
3085 /* Process slave interface names in the loop. */
3086 snprintf(tmp_str, sizeof(tmp_str),
3087 "/sys/class/net/%s", ifname);
3088 if (mlx5_dev_to_pci_addr(tmp_str, &pci_addr)) {
3089 DRV_LOG(WARNING, "can not get PCI address"
3090 " for netdev \"%s\"", ifname);
3093 if (pci_dev->addr.domain != pci_addr.domain ||
3094 pci_dev->addr.bus != pci_addr.bus ||
3095 pci_dev->addr.devid != pci_addr.devid ||
3096 pci_dev->addr.function != pci_addr.function)
3098 /* Slave interface PCI address match found. */
3100 snprintf(tmp_str, sizeof(tmp_str),
3101 "/sys/class/net/%s/phys_port_name", ifname);
3102 file = fopen(tmp_str, "rb");
3105 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET;
3106 if (fscanf(file, "%32s", tmp_str) == 1)
3107 mlx5_translate_port_name(tmp_str, &info);
3108 if (info.name_type == MLX5_PHYS_PORT_NAME_TYPE_LEGACY ||
3109 info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK)
3110 pf = info.port_name;
3119 * DPDK callback to register a PCI device.
3121 * This function spawns Ethernet devices out of a given PCI device.
3123 * @param[in] pci_drv
3124 * PCI driver structure (mlx5_driver).
3125 * @param[in] pci_dev
3126 * PCI device information.
3129 * 0 on success, a negative errno value otherwise and rte_errno is set.
3132 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3133 struct rte_pci_device *pci_dev)
3135 struct ibv_device **ibv_list;
3137 * Number of found IB Devices matching with requested PCI BDF.
3138 * nd != 1 means there are multiple IB devices over the same
3139 * PCI device and we have representors and master.
3141 unsigned int nd = 0;
3143 * Number of found IB device Ports. nd = 1 and np = 1..n means
3144 * we have the single multiport IB device, and there may be
3145 * representors attached to some of found ports.
3147 unsigned int np = 0;
3149 * Number of DPDK ethernet devices to Spawn - either over
3150 * multiple IB devices or multiple ports of single IB device.
3151 * Actually this is the number of iterations to spawn.
3153 unsigned int ns = 0;
3156 * < 0 - no bonding device (single one)
3157 * >= 0 - bonding device (value is slave PF index)
3160 struct mlx5_dev_spawn_data *list = NULL;
3161 struct mlx5_dev_config dev_config;
3164 if (mlx5_class_get(pci_dev->device.devargs) != MLX5_CLASS_NET) {
3165 DRV_LOG(DEBUG, "Skip probing - should be probed by other mlx5"
3169 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
3170 mlx5_pmd_socket_init();
3171 ret = mlx5_init_once();
3173 DRV_LOG(ERR, "unable to init PMD global data: %s",
3174 strerror(rte_errno));
3177 MLX5_ASSERT(pci_drv == &mlx5_driver);
3179 ibv_list = mlx5_glue->get_device_list(&ret);
3181 rte_errno = errno ? errno : ENOSYS;
3182 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?");
3186 * First scan the list of all Infiniband devices to find
3187 * matching ones, gathering into the list.
3189 struct ibv_device *ibv_match[ret + 1];
3190 int nl_route = mlx5_nl_init(NETLINK_ROUTE);
3191 int nl_rdma = mlx5_nl_init(NETLINK_RDMA);
3195 struct rte_pci_addr pci_addr;
3197 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name);
3198 bd = mlx5_device_bond_pci_match
3199 (ibv_list[ret], pci_dev, nl_rdma);
3202 * Bonding device detected. Only one match is allowed,
3203 * the bonding is supported over multi-port IB device,
3204 * there should be no matches on representor PCI
3205 * functions or non VF LAG bonding devices with
3206 * specified address.
3210 "multiple PCI match on bonding device"
3211 "\"%s\" found", ibv_list[ret]->name);
3216 DRV_LOG(INFO, "PCI information matches for"
3217 " slave %d bonding device \"%s\"",
3218 bd, ibv_list[ret]->name);
3219 ibv_match[nd++] = ibv_list[ret];
3222 if (mlx5_dev_to_pci_addr
3223 (ibv_list[ret]->ibdev_path, &pci_addr))
3225 if (pci_dev->addr.domain != pci_addr.domain ||
3226 pci_dev->addr.bus != pci_addr.bus ||
3227 pci_dev->addr.devid != pci_addr.devid ||
3228 pci_dev->addr.function != pci_addr.function)
3230 DRV_LOG(INFO, "PCI information matches for device \"%s\"",
3231 ibv_list[ret]->name);
3232 ibv_match[nd++] = ibv_list[ret];
3234 ibv_match[nd] = NULL;
3236 /* No device matches, just complain and bail out. */
3238 "no Verbs device matches PCI device " PCI_PRI_FMT ","
3239 " are kernel drivers loaded?",
3240 pci_dev->addr.domain, pci_dev->addr.bus,
3241 pci_dev->addr.devid, pci_dev->addr.function);
3248 * Found single matching device may have multiple ports.
3249 * Each port may be representor, we have to check the port
3250 * number and check the representors existence.
3253 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name);
3255 DRV_LOG(WARNING, "can not get IB device \"%s\""
3256 " ports number", ibv_match[0]->name);
3257 if (bd >= 0 && !np) {
3258 DRV_LOG(ERR, "can not get ports"
3259 " for bonding device");
3265 #ifndef HAVE_MLX5DV_DR_DEVX_PORT
3268 * This may happen if there is VF LAG kernel support and
3269 * application is compiled with older rdma_core library.
3272 "No kernel/verbs support for VF LAG bonding found.");
3273 rte_errno = ENOTSUP;
3279 * Now we can determine the maximal
3280 * amount of devices to be spawned.
3282 list = rte_zmalloc("device spawn data",
3283 sizeof(struct mlx5_dev_spawn_data) *
3285 RTE_CACHE_LINE_SIZE);
3287 DRV_LOG(ERR, "spawn data array allocation failure");
3292 if (bd >= 0 || np > 1) {
3294 * Single IB device with multiple ports found,
3295 * it may be E-Switch master device and representors.
3296 * We have to perform identification trough the ports.
3298 MLX5_ASSERT(nl_rdma >= 0);
3299 MLX5_ASSERT(ns == 0);
3300 MLX5_ASSERT(nd == 1);
3302 for (i = 1; i <= np; ++i) {
3303 list[ns].max_port = np;
3304 list[ns].ibv_port = i;
3305 list[ns].ibv_dev = ibv_match[0];
3306 list[ns].eth_dev = NULL;
3307 list[ns].pci_dev = pci_dev;
3308 list[ns].pf_bond = bd;
3309 list[ns].ifindex = mlx5_nl_ifindex
3310 (nl_rdma, list[ns].ibv_dev->name, i);
3311 if (!list[ns].ifindex) {
3313 * No network interface index found for the
3314 * specified port, it means there is no
3315 * representor on this port. It's OK,
3316 * there can be disabled ports, for example
3317 * if sriov_numvfs < sriov_totalvfs.
3323 ret = mlx5_nl_switch_info
3327 if (ret || (!list[ns].info.representor &&
3328 !list[ns].info.master)) {
3330 * We failed to recognize representors with
3331 * Netlink, let's try to perform the task
3334 ret = mlx5_sysfs_switch_info
3338 if (!ret && bd >= 0) {
3339 switch (list[ns].info.name_type) {
3340 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK:
3341 if (list[ns].info.port_name == bd)
3344 case MLX5_PHYS_PORT_NAME_TYPE_PFVF:
3345 if (list[ns].info.pf_num == bd)
3353 if (!ret && (list[ns].info.representor ^
3354 list[ns].info.master))
3359 "unable to recognize master/representors"
3360 " on the IB device with multiple ports");
3367 * The existence of several matching entries (nd > 1) means
3368 * port representors have been instantiated. No existing Verbs
3369 * call nor sysfs entries can tell them apart, this can only
3370 * be done through Netlink calls assuming kernel drivers are
3371 * recent enough to support them.
3373 * In the event of identification failure through Netlink,
3374 * try again through sysfs, then:
3376 * 1. A single IB device matches (nd == 1) with single
3377 * port (np=0/1) and is not a representor, assume
3378 * no switch support.
3380 * 2. Otherwise no safe assumptions can be made;
3381 * complain louder and bail out.
3384 for (i = 0; i != nd; ++i) {
3385 memset(&list[ns].info, 0, sizeof(list[ns].info));
3386 list[ns].max_port = 1;
3387 list[ns].ibv_port = 1;
3388 list[ns].ibv_dev = ibv_match[i];
3389 list[ns].eth_dev = NULL;
3390 list[ns].pci_dev = pci_dev;
3391 list[ns].pf_bond = -1;
3392 list[ns].ifindex = 0;
3394 list[ns].ifindex = mlx5_nl_ifindex
3395 (nl_rdma, list[ns].ibv_dev->name, 1);
3396 if (!list[ns].ifindex) {
3397 char ifname[IF_NAMESIZE];
3400 * Netlink failed, it may happen with old
3401 * ib_core kernel driver (before 4.16).
3402 * We can assume there is old driver because
3403 * here we are processing single ports IB
3404 * devices. Let's try sysfs to retrieve
3405 * the ifindex. The method works for
3406 * master device only.
3410 * Multiple devices found, assume
3411 * representors, can not distinguish
3412 * master/representor and retrieve
3413 * ifindex via sysfs.
3417 ret = mlx5_get_master_ifname
3418 (ibv_match[i]->ibdev_path, &ifname);
3421 if_nametoindex(ifname);
3422 if (!list[ns].ifindex) {
3424 * No network interface index found
3425 * for the specified device, it means
3426 * there it is neither representor
3434 ret = mlx5_nl_switch_info
3438 if (ret || (!list[ns].info.representor &&
3439 !list[ns].info.master)) {
3441 * We failed to recognize representors with
3442 * Netlink, let's try to perform the task
3445 ret = mlx5_sysfs_switch_info
3449 if (!ret && (list[ns].info.representor ^
3450 list[ns].info.master)) {
3452 } else if ((nd == 1) &&
3453 !list[ns].info.representor &&
3454 !list[ns].info.master) {
3456 * Single IB device with
3457 * one physical port and
3458 * attached network device.
3459 * May be SRIOV is not enabled
3460 * or there is no representors.
3462 DRV_LOG(INFO, "no E-Switch support detected");
3469 "unable to recognize master/representors"
3470 " on the multiple IB devices");
3478 * Sort list to probe devices in natural order for users convenience
3479 * (i.e. master first, then representors from lowest to highest ID).
3481 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp);
3482 /* Default configuration. */
3483 dev_config = (struct mlx5_dev_config){
3485 .mps = MLX5_ARG_UNSET,
3486 .dbnc = MLX5_ARG_UNSET,
3488 .txq_inline_max = MLX5_ARG_UNSET,
3489 .txq_inline_min = MLX5_ARG_UNSET,
3490 .txq_inline_mpw = MLX5_ARG_UNSET,
3491 .txqs_inline = MLX5_ARG_UNSET,
3493 .mr_ext_memseg_en = 1,
3495 .enabled = 0, /* Disabled by default. */
3498 .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
3499 .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
3503 .log_hp_size = MLX5_ARG_UNSET,
3505 /* Device specific configuration. */
3506 switch (pci_dev->id.device_id) {
3507 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
3508 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
3509 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
3510 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
3511 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF:
3512 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF:
3513 case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF:
3519 for (i = 0; i != ns; ++i) {
3522 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device,
3525 if (!list[i].eth_dev) {
3526 if (rte_errno != EBUSY && rte_errno != EEXIST)
3528 /* Device is disabled or already spawned. Ignore it. */
3531 restore = list[i].eth_dev->data->dev_flags;
3532 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev);
3533 /* Restore non-PCI flags cleared by the above call. */
3534 list[i].eth_dev->data->dev_flags |= restore;
3535 mlx5_dev_interrupt_handler_devx_install(list[i].eth_dev);
3536 rte_eth_dev_probing_finish(list[i].eth_dev);
3540 "probe of PCI device " PCI_PRI_FMT " aborted after"
3541 " encountering an error: %s",
3542 pci_dev->addr.domain, pci_dev->addr.bus,
3543 pci_dev->addr.devid, pci_dev->addr.function,
3544 strerror(rte_errno));
3548 if (!list[i].eth_dev)
3550 mlx5_dev_close(list[i].eth_dev);
3551 /* mac_addrs must not be freed because in dev_private */
3552 list[i].eth_dev->data->mac_addrs = NULL;
3553 claim_zero(rte_eth_dev_release_port(list[i].eth_dev));
3555 /* Restore original error. */
3562 * Do the routine cleanup:
3563 * - close opened Netlink sockets
3564 * - free allocated spawn data array
3565 * - free the Infiniband device list
3573 MLX5_ASSERT(ibv_list);
3574 mlx5_glue->free_device_list(ibv_list);
3579 * Look for the ethernet device belonging to mlx5 driver.
3581 * @param[in] port_id
3582 * port_id to start looking for device.
3583 * @param[in] pci_dev
3584 * Pointer to the hint PCI device. When device is being probed
3585 * the its siblings (master and preceding representors might
3586 * not have assigned driver yet (because the mlx5_pci_probe()
3587 * is not completed yet, for this case match on hint PCI
3588 * device may be used to detect sibling device.
3591 * port_id of found device, RTE_MAX_ETHPORT if not found.
3594 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
3596 while (port_id < RTE_MAX_ETHPORTS) {
3597 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
3599 if (dev->state != RTE_ETH_DEV_UNUSED &&
3601 (dev->device == &pci_dev->device ||
3602 (dev->device->driver &&
3603 dev->device->driver->name &&
3604 !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
3608 if (port_id >= RTE_MAX_ETHPORTS)
3609 return RTE_MAX_ETHPORTS;
3614 * DPDK callback to remove a PCI device.
3616 * This function removes all Ethernet devices belong to a given PCI device.
3618 * @param[in] pci_dev
3619 * Pointer to the PCI device.
3622 * 0 on success, the function cannot fail.
3625 mlx5_pci_remove(struct rte_pci_device *pci_dev)
3629 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device)
3630 rte_eth_dev_close(port_id);
3634 static const struct rte_pci_id mlx5_pci_id_map[] = {
3636 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3637 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
3640 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3641 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
3644 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3645 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
3648 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3649 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
3652 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3653 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
3656 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3657 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
3660 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3661 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
3664 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3665 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
3668 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3669 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
3672 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3673 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
3676 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3677 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
3680 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3681 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
3684 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3685 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
3688 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3689 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
3692 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3693 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
3700 static struct rte_pci_driver mlx5_driver = {
3702 .name = MLX5_DRIVER_NAME
3704 .id_table = mlx5_pci_id_map,
3705 .probe = mlx5_pci_probe,
3706 .remove = mlx5_pci_remove,
3707 .dma_map = mlx5_dma_map,
3708 .dma_unmap = mlx5_dma_unmap,
3709 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV |
3710 RTE_PCI_DRV_PROBE_AGAIN,
3714 * Driver initialization routine.
3716 RTE_INIT(rte_mlx5_pmd_init)
3718 /* Initialize driver log type. */
3719 mlx5_logtype = rte_log_register("pmd.net.mlx5");
3720 if (mlx5_logtype >= 0)
3721 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
3723 /* Build the static tables for Verbs conversion. */
3724 mlx5_set_ptype_table();
3725 mlx5_set_cksum_table();
3726 mlx5_set_swp_types_table();
3728 rte_pci_register(&mlx5_driver);
3731 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
3732 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
3733 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");