drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12 #include <net/if.h>
  13 #include <sys/mman.h>
  14 #include <linux/rtnetlink.h>
  15
  16 /* Verbs header. */
  17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  18 #ifdef PEDANTIC
  19 #pragma GCC diagnostic ignored "-Wpedantic"
  20 #endif
  21 #include <infiniband/verbs.h>
  22 #ifdef PEDANTIC
  23 #pragma GCC diagnostic error "-Wpedantic"
  24 #endif
  25
  26 #include <rte_malloc.h>
  27 #include <rte_ethdev_driver.h>
  28 #include <rte_ethdev_pci.h>
  29 #include <rte_pci.h>
  30 #include <rte_bus_pci.h>
  31 #include <rte_common.h>
  32 #include <rte_kvargs.h>
  33 #include <rte_rwlock.h>
  34 #include <rte_spinlock.h>
  35 #include <rte_string_fns.h>
  36 #include <rte_alarm.h>
  37
  38 #include <mlx5_glue.h>
  39 #include <mlx5_devx_cmds.h>
  40 #include <mlx5_common.h>
  41 #include <mlx5_common_mp.h>
  42
  43 #include "mlx5_defs.h"
  44 #include "mlx5.h"
  45 #include "mlx5_utils.h"
  46 #include "mlx5_rxtx.h"
  47 #include "mlx5_autoconf.h"
  48 #include "mlx5_mr.h"
  49 #include "mlx5_flow.h"
  50 #include "rte_pmd_mlx5.h"
  51
  52 /* Device parameter to enable RX completion queue compression. */
  53 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  54
  55 /* Device parameter to enable RX completion entry padding to 128B. */
  56 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
  57
  58 /* Device parameter to enable padding Rx packet to cacheline size. */
  59 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  60
  61 /* Device parameter to enable Multi-Packet Rx queue. */
  62 #define MLX5_RX_MPRQ_EN "mprq_en"
  63
  64 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  65 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  66
  67 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  68 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  69
  70 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  71 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  72
  73 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  74 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  75
  76 /* Device parameter to configure inline send. Deprecated, ignored.*/
  77 #define MLX5_TXQ_INLINE "txq_inline"
  78
  79 /* Device parameter to limit packet size to inline with ordinary SEND. */
  80 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  81
  82 /* Device parameter to configure minimal data size to inline. */
  83 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  84
  85 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  86 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  87
  88 /*
  89  * Device parameter to configure the number of TX queues threshold for
  90  * enabling inline send.
  91  */
  92 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  93
  94 /*
  95  * Device parameter to configure the number of TX queues threshold for
  96  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  97  */
  98 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  99
 100 /* Device parameter to enable multi-packet send WQEs. */
 101 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
 102
 103 /*
 104  * Device parameter to force doorbell register mapping
 105  * to non-cahed region eliminating the extra write memory barrier.
 106  */
 107 #define MLX5_TX_DB_NC "tx_db_nc"
 108
 109 /*
 110  * Device parameter to include 2 dsegs in the title WQEBB.
 111  * Deprecated, ignored.
 112  */
 113 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 114
 115 /*
 116  * Device parameter to limit the size of inlining packet.
 117  * Deprecated, ignored.
 118  */
 119 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 120
 121 /*
 122  * Device parameter to enable hardware Tx vector.
 123  * Deprecated, ignored (no vectorized Tx routines anymore).
 124  */
 125 #define MLX5_TX_VEC_EN "tx_vec_en"
 126
 127 /* Device parameter to enable hardware Rx vector. */
 128 #define MLX5_RX_VEC_EN "rx_vec_en"
 129
 130 /* Allow L3 VXLAN flow creation. */
 131 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 132
 133 /* Activate DV E-Switch flow steering. */
 134 #define MLX5_DV_ESW_EN "dv_esw_en"
 135
 136 /* Activate DV flow steering. */
 137 #define MLX5_DV_FLOW_EN "dv_flow_en"
 138
 139 /* Enable extensive flow metadata support. */
 140 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 141
 142 /* Activate Netlink support in VF mode. */
 143 #define MLX5_VF_NL_EN "vf_nl_en"
 144
 145 /* Enable extending memsegs when creating a MR. */
 146 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 147
 148 /* Select port representors to instantiate. */
 149 #define MLX5_REPRESENTOR "representor"
 150
 151 /* Device parameter to configure the maximum number of dump files per queue. */
 152 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 153
 154 /* Configure timeout of LRO session (in microseconds). */
 155 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 156
 157 /*
 158  * Device parameter to configure the total data buffer size for a single
 159  * hairpin queue (logarithm value).
 160  */
 161 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 162
 163 /* Flow memory reclaim mode. */
 164 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 165
 166 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
 167
 168 /* Shared memory between primary and secondary processes. */
 169 struct mlx5_shared_data *mlx5_shared_data;
 170
 171 /* Spinlock for mlx5_shared_data allocation. */
 172 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
 173
 174 /* Process local data for secondary processes. */
 175 static struct mlx5_local_data mlx5_local_data;
 176 /** Driver-specific log messages type. */
 177 int mlx5_logtype;
 178
 179 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_ibv_list = LIST_HEAD_INITIALIZER();
 180 static pthread_mutex_t mlx5_ibv_list_mutex = PTHREAD_MUTEX_INITIALIZER;
 181
 182 static struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 183 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 184         {
 185                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 186                 .trunk_size = 64,
 187                 .grow_trunk = 3,
 188                 .grow_shift = 2,
 189                 .need_lock = 0,
 190                 .release_mem_en = 1,
 191                 .malloc = rte_malloc_socket,
 192                 .free = rte_free,
 193                 .type = "mlx5_encap_decap_ipool",
 194         },
 195         {
 196                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 197                 .trunk_size = 64,
 198                 .grow_trunk = 3,
 199                 .grow_shift = 2,
 200                 .need_lock = 0,
 201                 .release_mem_en = 1,
 202                 .malloc = rte_malloc_socket,
 203                 .free = rte_free,
 204                 .type = "mlx5_push_vlan_ipool",
 205         },
 206         {
 207                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 208                 .trunk_size = 64,
 209                 .grow_trunk = 3,
 210                 .grow_shift = 2,
 211                 .need_lock = 0,
 212                 .release_mem_en = 1,
 213                 .malloc = rte_malloc_socket,
 214                 .free = rte_free,
 215                 .type = "mlx5_tag_ipool",
 216         },
 217         {
 218                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 219                 .trunk_size = 64,
 220                 .grow_trunk = 3,
 221                 .grow_shift = 2,
 222                 .need_lock = 0,
 223                 .release_mem_en = 1,
 224                 .malloc = rte_malloc_socket,
 225                 .free = rte_free,
 226                 .type = "mlx5_port_id_ipool",
 227         },
 228         {
 229                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 230                 .trunk_size = 64,
 231                 .grow_trunk = 3,
 232                 .grow_shift = 2,
 233                 .need_lock = 0,
 234                 .release_mem_en = 1,
 235                 .malloc = rte_malloc_socket,
 236                 .free = rte_free,
 237                 .type = "mlx5_jump_ipool",
 238         },
 239 #endif
 240         {
 241                 .size = sizeof(struct mlx5_flow_meter),
 242                 .trunk_size = 64,
 243                 .grow_trunk = 3,
 244                 .grow_shift = 2,
 245                 .need_lock = 0,
 246                 .release_mem_en = 1,
 247                 .malloc = rte_malloc_socket,
 248                 .free = rte_free,
 249                 .type = "mlx5_meter_ipool",
 250         },
 251         {
 252                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 253                 .trunk_size = 64,
 254                 .grow_trunk = 3,
 255                 .grow_shift = 2,
 256                 .need_lock = 0,
 257                 .release_mem_en = 1,
 258                 .malloc = rte_malloc_socket,
 259                 .free = rte_free,
 260                 .type = "mlx5_mcp_ipool",
 261         },
 262         {
 263                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 264                 .trunk_size = 64,
 265                 .grow_trunk = 3,
 266                 .grow_shift = 2,
 267                 .need_lock = 0,
 268                 .release_mem_en = 1,
 269                 .malloc = rte_malloc_socket,
 270                 .free = rte_free,
 271                 .type = "mlx5_hrxq_ipool",
 272         },
 273         {
 274                 .size = sizeof(struct mlx5_flow_handle),
 275                 .trunk_size = 64,
 276                 .grow_trunk = 3,
 277                 .grow_shift = 2,
 278                 .need_lock = 0,
 279                 .release_mem_en = 1,
 280                 .malloc = rte_malloc_socket,
 281                 .free = rte_free,
 282                 .type = "mlx5_flow_handle_ipool",
 283         },
 284         {
 285                 .size = sizeof(struct rte_flow),
 286                 .trunk_size = 4096,
 287                 .need_lock = 1,
 288                 .release_mem_en = 1,
 289                 .malloc = rte_malloc_socket,
 290                 .free = rte_free,
 291                 .type = "rte_flow_ipool",
 292         },
 293 };
 294
 295
 296 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 297 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 298
 299 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 300
 301 /**
 302  * Allocate ID pool structure.
 303  *
 304  * @param[in] max_id
 305  *   The maximum id can be allocated from the pool.
 306  *
 307  * @return
 308  *   Pointer to pool object, NULL value otherwise.
 309  */
 310 struct mlx5_flow_id_pool *
 311 mlx5_flow_id_pool_alloc(uint32_t max_id)
 312 {
 313         struct mlx5_flow_id_pool *pool;
 314         void *mem;
 315
 316         pool = rte_zmalloc("id pool allocation", sizeof(*pool),
 317                            RTE_CACHE_LINE_SIZE);
 318         if (!pool) {
 319                 DRV_LOG(ERR, "can't allocate id pool");
 320                 rte_errno  = ENOMEM;
 321                 return NULL;
 322         }
 323         mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
 324                           RTE_CACHE_LINE_SIZE);
 325         if (!mem) {
 326                 DRV_LOG(ERR, "can't allocate mem for id pool");
 327                 rte_errno  = ENOMEM;
 328                 goto error;
 329         }
 330         pool->free_arr = mem;
 331         pool->curr = pool->free_arr;
 332         pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
 333         pool->base_index = 0;
 334         pool->max_id = max_id;
 335         return pool;
 336 error:
 337         rte_free(pool);
 338         return NULL;
 339 }
 340
 341 /**
 342  * Release ID pool structure.
 343  *
 344  * @param[in] pool
 345  *   Pointer to flow id pool object to free.
 346  */
 347 void
 348 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
 349 {
 350         rte_free(pool->free_arr);
 351         rte_free(pool);
 352 }
 353
 354 /**
 355  * Generate ID.
 356  *
 357  * @param[in] pool
 358  *   Pointer to flow id pool.
 359  * @param[out] id
 360  *   The generated ID.
 361  *
 362  * @return
 363  *   0 on success, error value otherwise.
 364  */
 365 uint32_t
 366 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
 367 {
 368         if (pool->curr == pool->free_arr) {
 369                 if (pool->base_index == pool->max_id) {
 370                         rte_errno  = ENOMEM;
 371                         DRV_LOG(ERR, "no free id");
 372                         return -rte_errno;
 373                 }
 374                 *id = ++pool->base_index;
 375                 return 0;
 376         }
 377         *id = *(--pool->curr);
 378         return 0;
 379 }
 380
 381 /**
 382  * Release ID.
 383  *
 384  * @param[in] pool
 385  *   Pointer to flow id pool.
 386  * @param[out] id
 387  *   The generated ID.
 388  *
 389  * @return
 390  *   0 on success, error value otherwise.
 391  */
 392 uint32_t
 393 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
 394 {
 395         uint32_t size;
 396         uint32_t size2;
 397         void *mem;
 398
 399         if (pool->curr == pool->last) {
 400                 size = pool->curr - pool->free_arr;
 401                 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
 402                 MLX5_ASSERT(size2 > size);
 403                 mem = rte_malloc("", size2 * sizeof(uint32_t), 0);
 404                 if (!mem) {
 405                         DRV_LOG(ERR, "can't allocate mem for id pool");
 406                         rte_errno  = ENOMEM;
 407                         return -rte_errno;
 408                 }
 409                 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
 410                 rte_free(pool->free_arr);
 411                 pool->free_arr = mem;
 412                 pool->curr = pool->free_arr + size;
 413                 pool->last = pool->free_arr + size2;
 414         }
 415         *pool->curr = id;
 416         pool->curr++;
 417         return 0;
 418 }
 419
 420 /**
 421  * Initialize the shared aging list information per port.
 422  *
 423  * @param[in] sh
 424  *   Pointer to mlx5_dev_ctx_shared object.
 425  */
 426 static void
 427 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 428 {
 429         uint32_t i;
 430         struct mlx5_age_info *age_info;
 431
 432         for (i = 0; i < sh->max_port; i++) {
 433                 age_info = &sh->port[i].age_info;
 434                 age_info->flags = 0;
 435                 TAILQ_INIT(&age_info->aged_counters);
 436                 rte_spinlock_init(&age_info->aged_sl);
 437                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 438         }
 439 }
 440
 441 /**
 442  * Initialize the counters management structure.
 443  *
 444  * @param[in] sh
 445  *   Pointer to mlx5_dev_ctx_shared object to free
 446  */
 447 static void
 448 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 449 {
 450         int i;
 451
 452         memset(&sh->cmng, 0, sizeof(sh->cmng));
 453         TAILQ_INIT(&sh->cmng.flow_counters);
 454         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 455                 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
 456                 rte_spinlock_init(&sh->cmng.ccont[i].resize_sl);
 457         }
 458 }
 459
 460 /**
 461  * Destroy all the resources allocated for a counter memory management.
 462  *
 463  * @param[in] mng
 464  *   Pointer to the memory management structure.
 465  */
 466 static void
 467 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 468 {
 469         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 470
 471         LIST_REMOVE(mng, next);
 472         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 473         claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
 474         rte_free(mem);
 475 }
 476
 477 /**
 478  * Close and release all the resources of the counters management.
 479  *
 480  * @param[in] sh
 481  *   Pointer to mlx5_dev_ctx_shared object to free.
 482  */
 483 static void
 484 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 485 {
 486         struct mlx5_counter_stats_mem_mng *mng;
 487         int i;
 488         int j;
 489         int retries = 1024;
 490
 491         rte_errno = 0;
 492         while (--retries) {
 493                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 494                 if (rte_errno != EINPROGRESS)
 495                         break;
 496                 rte_pause();
 497         }
 498         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 499                 struct mlx5_flow_counter_pool *pool;
 500                 uint32_t batch = !!(i > 1);
 501
 502                 if (!sh->cmng.ccont[i].pools)
 503                         continue;
 504                 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 505                 while (pool) {
 506                         if (batch && pool->min_dcs)
 507                                 claim_zero(mlx5_devx_cmd_destroy
 508                                                                (pool->min_dcs));
 509                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 510                                 if (MLX5_POOL_GET_CNT(pool, j)->action)
 511                                         claim_zero
 512                                          (mlx5_glue->destroy_flow_action
 513                                           (MLX5_POOL_GET_CNT
 514                                           (pool, j)->action));
 515                                 if (!batch && MLX5_GET_POOL_CNT_EXT
 516                                     (pool, j)->dcs)
 517                                         claim_zero(mlx5_devx_cmd_destroy
 518                                                    (MLX5_GET_POOL_CNT_EXT
 519                                                     (pool, j)->dcs));
 520                         }
 521                         TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, next);
 522                         rte_free(pool);
 523                         pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 524                 }
 525                 rte_free(sh->cmng.ccont[i].pools);
 526         }
 527         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 528         while (mng) {
 529                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 530                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 531         }
 532         memset(&sh->cmng, 0, sizeof(sh->cmng));
 533 }
 534
 535 /**
 536  * Initialize the flow resources' indexed mempool.
 537  *
 538  * @param[in] sh
 539  *   Pointer to mlx5_dev_ctx_shared object.
 540  * @param[in] sh
 541  *   Pointer to user dev config.
 542  */
 543 static void
 544 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 545                        const struct mlx5_dev_config *config __rte_unused)
 546 {
 547         uint8_t i;
 548
 549 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 550         /*
 551          * While DV is supported, user chooses the verbs mode,
 552          * the mlx5 flow handle size is different with the
 553          * MLX5_FLOW_HANDLE_VERBS_SIZE.
 554          */
 555         if (!config->dv_flow_en)
 556                 mlx5_ipool_cfg[MLX5_IPOOL_MLX5_FLOW].size =
 557                                         MLX5_FLOW_HANDLE_VERBS_SIZE;
 558 #endif
 559         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 560                 if (config->reclaim_mode)
 561                         mlx5_ipool_cfg[i].release_mem_en = 1;
 562                 sh->ipool[i] = mlx5_ipool_create(&mlx5_ipool_cfg[i]);
 563         }
 564 }
 565
 566 /**
 567  * Release the flow resources' indexed mempool.
 568  *
 569  * @param[in] sh
 570  *   Pointer to mlx5_dev_ctx_shared object.
 571  */
 572 static void
 573 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 574 {
 575         uint8_t i;
 576
 577         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 578                 mlx5_ipool_destroy(sh->ipool[i]);
 579 }
 580
 581 /**
 582  * Allocate shared IB device context. If there is multiport device the
 583  * master and representors will share this context, if there is single
 584  * port dedicated IB device, the context will be used by only given
 585  * port due to unification.
 586  *
 587  * Routine first searches the context for the specified IB device name,
 588  * if found the shared context assumed and reference counter is incremented.
 589  * If no context found the new one is created and initialized with specified
 590  * IB device context and parameters.
 591  *
 592  * @param[in] spawn
 593  *   Pointer to the IB device attributes (name, port, etc).
 594  * @param[in] config
 595  *   Pointer to device configuration structure.
 596  *
 597  * @return
 598  *   Pointer to mlx5_dev_ctx_shared object on success,
 599  *   otherwise NULL and rte_errno is set.
 600  */
 601 struct mlx5_dev_ctx_shared *
 602 mlx5_alloc_shared_ibctx(const struct mlx5_dev_spawn_data *spawn,
 603                         const struct mlx5_dev_config *config)
 604 {
 605         struct mlx5_dev_ctx_shared *sh;
 606         int err = 0;
 607         uint32_t i;
 608         struct mlx5_devx_tis_attr tis_attr = { 0 };
 609
 610         MLX5_ASSERT(spawn);
 611         /* Secondary process should not create the shared context. */
 612         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 613         pthread_mutex_lock(&mlx5_ibv_list_mutex);
 614         /* Search for IB context by device name. */
 615         LIST_FOREACH(sh, &mlx5_ibv_list, next) {
 616                 if (!strcmp(sh->ibdev_name,
 617                         mlx5_os_get_dev_device_name(spawn->phys_dev))) {
 618                         sh->refcnt++;
 619                         goto exit;
 620                 }
 621         }
 622         /* No device found, we have to create new shared context. */
 623         MLX5_ASSERT(spawn->max_port);
 624         sh = rte_zmalloc("ethdev shared ib context",
 625                          sizeof(struct mlx5_dev_ctx_shared) +
 626                          spawn->max_port *
 627                          sizeof(struct mlx5_ibv_shared_port),
 628                          RTE_CACHE_LINE_SIZE);
 629         if (!sh) {
 630                 DRV_LOG(ERR, "shared context allocation failure");
 631                 rte_errno  = ENOMEM;
 632                 goto exit;
 633         }
 634         err = mlx5_os_open_device(spawn, config, sh);
 635         if (!sh->ctx)
 636                 goto error;
 637         err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
 638         if (err) {
 639                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
 640                 goto error;
 641         }
 642         sh->refcnt = 1;
 643         sh->max_port = spawn->max_port;
 644         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
 645                 sizeof(sh->ibdev_name) - 1);
 646         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
 647                 sizeof(sh->ibdev_path) - 1);
 648         /*
 649          * Setting port_id to max unallowed value means
 650          * there is no interrupt subhandler installed for
 651          * the given port index i.
 652          */
 653         for (i = 0; i < sh->max_port; i++) {
 654                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 655                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
 656         }
 657         sh->pd = mlx5_glue->alloc_pd(sh->ctx);
 658         if (sh->pd == NULL) {
 659                 DRV_LOG(ERR, "PD allocation failure");
 660                 err = ENOMEM;
 661                 goto error;
 662         }
 663         if (sh->devx) {
 664                 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
 665                 if (err) {
 666                         DRV_LOG(ERR, "Fail to extract pdn from PD");
 667                         goto error;
 668                 }
 669                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
 670                 if (!sh->td) {
 671                         DRV_LOG(ERR, "TD allocation failure");
 672                         err = ENOMEM;
 673                         goto error;
 674                 }
 675                 tis_attr.transport_domain = sh->td->id;
 676                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
 677                 if (!sh->tis) {
 678                         DRV_LOG(ERR, "TIS allocation failure");
 679                         err = ENOMEM;
 680                         goto error;
 681                 }
 682         }
 683         sh->flow_id_pool = mlx5_flow_id_pool_alloc
 684                                         ((1 << HAIRPIN_FLOW_ID_BITS) - 1);
 685         if (!sh->flow_id_pool) {
 686                 DRV_LOG(ERR, "can't create flow id pool");
 687                 err = ENOMEM;
 688                 goto error;
 689         }
 690         /*
 691          * Once the device is added to the list of memory event
 692          * callback, its global MR cache table cannot be expanded
 693          * on the fly because of deadlock. If it overflows, lookup
 694          * should be done by searching MR list linearly, which is slow.
 695          *
 696          * At this point the device is not added to the memory
 697          * event list yet, context is just being created.
 698          */
 699         err = mlx5_mr_btree_init(&sh->share_cache.cache,
 700                                  MLX5_MR_BTREE_CACHE_N * 2,
 701                                  spawn->pci_dev->device.numa_node);
 702         if (err) {
 703                 err = rte_errno;
 704                 goto error;
 705         }
 706         mlx5_os_dev_shared_handler_install(sh);
 707         mlx5_flow_aging_init(sh);
 708         mlx5_flow_counters_mng_init(sh);
 709         mlx5_flow_ipool_create(sh, config);
 710         /* Add device to memory callback list. */
 711         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 712         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
 713                          sh, mem_event_cb);
 714         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 715         /* Add context to the global device list. */
 716         LIST_INSERT_HEAD(&mlx5_ibv_list, sh, next);
 717 exit:
 718         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 719         return sh;
 720 error:
 721         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 722         MLX5_ASSERT(sh);
 723         if (sh->tis)
 724                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 725         if (sh->td)
 726                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 727         if (sh->pd)
 728                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 729         if (sh->ctx)
 730                 claim_zero(mlx5_glue->close_device(sh->ctx));
 731         if (sh->flow_id_pool)
 732                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 733         rte_free(sh);
 734         MLX5_ASSERT(err > 0);
 735         rte_errno = err;
 736         return NULL;
 737 }
 738
 739 /**
 740  * Free shared IB device context. Decrement counter and if zero free
 741  * all allocated resources and close handles.
 742  *
 743  * @param[in] sh
 744  *   Pointer to mlx5_dev_ctx_shared object to free
 745  */
 746 void
 747 mlx5_free_shared_ibctx(struct mlx5_dev_ctx_shared *sh)
 748 {
 749         pthread_mutex_lock(&mlx5_ibv_list_mutex);
 750 #ifdef RTE_LIBRTE_MLX5_DEBUG
 751         /* Check the object presence in the list. */
 752         struct mlx5_dev_ctx_shared *lctx;
 753
 754         LIST_FOREACH(lctx, &mlx5_ibv_list, next)
 755                 if (lctx == sh)
 756                         break;
 757         MLX5_ASSERT(lctx);
 758         if (lctx != sh) {
 759                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
 760                 goto exit;
 761         }
 762 #endif
 763         MLX5_ASSERT(sh);
 764         MLX5_ASSERT(sh->refcnt);
 765         /* Secondary process should not free the shared context. */
 766         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 767         if (--sh->refcnt)
 768                 goto exit;
 769         /* Remove from memory callback device list. */
 770         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 771         LIST_REMOVE(sh, mem_event_cb);
 772         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 773         /* Release created Memory Regions. */
 774         mlx5_mr_release_cache(&sh->share_cache);
 775         /* Remove context from the global device list. */
 776         LIST_REMOVE(sh, next);
 777         /*
 778          *  Ensure there is no async event handler installed.
 779          *  Only primary process handles async device events.
 780          **/
 781         mlx5_flow_counters_mng_close(sh);
 782         mlx5_flow_ipool_destroy(sh);
 783         mlx5_os_dev_shared_handler_uninstall(sh);
 784         if (sh->pd)
 785                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 786         if (sh->tis)
 787                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 788         if (sh->td)
 789                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 790         if (sh->ctx)
 791                 claim_zero(mlx5_glue->close_device(sh->ctx));
 792         if (sh->flow_id_pool)
 793                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 794         rte_free(sh);
 795 exit:
 796         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 797 }
 798
 799 /**
 800  * Destroy table hash list and all the root entries per domain.
 801  *
 802  * @param[in] priv
 803  *   Pointer to the private device data structure.
 804  */
 805 void
 806 mlx5_free_table_hash_list(struct mlx5_priv *priv)
 807 {
 808         struct mlx5_dev_ctx_shared *sh = priv->sh;
 809         struct mlx5_flow_tbl_data_entry *tbl_data;
 810         union mlx5_flow_tbl_key table_key = {
 811                 {
 812                         .table_id = 0,
 813                         .reserved = 0,
 814                         .domain = 0,
 815                         .direction = 0,
 816                 }
 817         };
 818         struct mlx5_hlist_entry *pos;
 819
 820         if (!sh->flow_tbls)
 821                 return;
 822         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 823         if (pos) {
 824                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 825                                         entry);
 826                 MLX5_ASSERT(tbl_data);
 827                 mlx5_hlist_remove(sh->flow_tbls, pos);
 828                 rte_free(tbl_data);
 829         }
 830         table_key.direction = 1;
 831         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 832         if (pos) {
 833                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 834                                         entry);
 835                 MLX5_ASSERT(tbl_data);
 836                 mlx5_hlist_remove(sh->flow_tbls, pos);
 837                 rte_free(tbl_data);
 838         }
 839         table_key.direction = 0;
 840         table_key.domain = 1;
 841         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 842         if (pos) {
 843                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 844                                         entry);
 845                 MLX5_ASSERT(tbl_data);
 846                 mlx5_hlist_remove(sh->flow_tbls, pos);
 847                 rte_free(tbl_data);
 848         }
 849         mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
 850 }
 851
 852 /**
 853  * Initialize flow table hash list and create the root tables entry
 854  * for each domain.
 855  *
 856  * @param[in] priv
 857  *   Pointer to the private device data structure.
 858  *
 859  * @return
 860  *   Zero on success, positive error code otherwise.
 861  */
 862 int
 863 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
 864 {
 865         struct mlx5_dev_ctx_shared *sh = priv->sh;
 866         char s[MLX5_HLIST_NAMESIZE];
 867         int err = 0;
 868
 869         MLX5_ASSERT(sh);
 870         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
 871         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
 872         if (!sh->flow_tbls) {
 873                 DRV_LOG(ERR, "flow tables with hash creation failed.\n");
 874                 err = ENOMEM;
 875                 return err;
 876         }
 877 #ifndef HAVE_MLX5DV_DR
 878         /*
 879          * In case we have not DR support, the zero tables should be created
 880          * because DV expect to see them even if they cannot be created by
 881          * RDMA-CORE.
 882          */
 883         union mlx5_flow_tbl_key table_key = {
 884                 {
 885                         .table_id = 0,
 886                         .reserved = 0,
 887                         .domain = 0,
 888                         .direction = 0,
 889                 }
 890         };
 891         struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL,
 892                                                           sizeof(*tbl_data), 0);
 893
 894         if (!tbl_data) {
 895                 err = ENOMEM;
 896                 goto error;
 897         }
 898         tbl_data->entry.key = table_key.v64;
 899         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 900         if (err)
 901                 goto error;
 902         rte_atomic32_init(&tbl_data->tbl.refcnt);
 903         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 904         table_key.direction = 1;
 905         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 906         if (!tbl_data) {
 907                 err = ENOMEM;
 908                 goto error;
 909         }
 910         tbl_data->entry.key = table_key.v64;
 911         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 912         if (err)
 913                 goto error;
 914         rte_atomic32_init(&tbl_data->tbl.refcnt);
 915         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 916         table_key.direction = 0;
 917         table_key.domain = 1;
 918         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 919         if (!tbl_data) {
 920                 err = ENOMEM;
 921                 goto error;
 922         }
 923         tbl_data->entry.key = table_key.v64;
 924         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 925         if (err)
 926                 goto error;
 927         rte_atomic32_init(&tbl_data->tbl.refcnt);
 928         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 929         return err;
 930 error:
 931         mlx5_free_table_hash_list(priv);
 932 #endif /* HAVE_MLX5DV_DR */
 933         return err;
 934 }
 935
 936 /**
 937  * Initialize shared data between primary and secondary process.
 938  *
 939  * A memzone is reserved by primary process and secondary processes attach to
 940  * the memzone.
 941  *
 942  * @return
 943  *   0 on success, a negative errno value otherwise and rte_errno is set.
 944  */
 945 static int
 946 mlx5_init_shared_data(void)
 947 {
 948         const struct rte_memzone *mz;
 949         int ret = 0;
 950
 951         rte_spinlock_lock(&mlx5_shared_data_lock);
 952         if (mlx5_shared_data == NULL) {
 953                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
 954                         /* Allocate shared memory. */
 955                         mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
 956                                                  sizeof(*mlx5_shared_data),
 957                                                  SOCKET_ID_ANY, 0);
 958                         if (mz == NULL) {
 959                                 DRV_LOG(ERR,
 960                                         "Cannot allocate mlx5 shared data");
 961                                 ret = -rte_errno;
 962                                 goto error;
 963                         }
 964                         mlx5_shared_data = mz->addr;
 965                         memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
 966                         rte_spinlock_init(&mlx5_shared_data->lock);
 967                 } else {
 968                         /* Lookup allocated shared memory. */
 969                         mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
 970                         if (mz == NULL) {
 971                                 DRV_LOG(ERR,
 972                                         "Cannot attach mlx5 shared data");
 973                                 ret = -rte_errno;
 974                                 goto error;
 975                         }
 976                         mlx5_shared_data = mz->addr;
 977                         memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
 978                 }
 979         }
 980 error:
 981         rte_spinlock_unlock(&mlx5_shared_data_lock);
 982         return ret;
 983 }
 984
 985 /**
 986  * Retrieve integer value from environment variable.
 987  *
 988  * @param[in] name
 989  *   Environment variable name.
 990  *
 991  * @return
 992  *   Integer value, 0 if the variable is not set.
 993  */
 994 int
 995 mlx5_getenv_int(const char *name)
 996 {
 997         const char *val = getenv(name);
 998
 999         if (val == NULL)
1000                 return 0;
1001         return atoi(val);
1002 }
1003
1004 /**
1005  * DPDK callback to add udp tunnel port
1006  *
1007  * @param[in] dev
1008  *   A pointer to eth_dev
1009  * @param[in] udp_tunnel
1010  *   A pointer to udp tunnel
1011  *
1012  * @return
1013  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1014  */
1015 int
1016 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1017                          struct rte_eth_udp_tunnel *udp_tunnel)
1018 {
1019         MLX5_ASSERT(udp_tunnel != NULL);
1020         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1021             udp_tunnel->udp_port == 4789)
1022                 return 0;
1023         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1024             udp_tunnel->udp_port == 4790)
1025                 return 0;
1026         return -ENOTSUP;
1027 }
1028
1029 /**
1030  * Initialize process private data structure.
1031  *
1032  * @param dev
1033  *   Pointer to Ethernet device structure.
1034  *
1035  * @return
1036  *   0 on success, a negative errno value otherwise and rte_errno is set.
1037  */
1038 int
1039 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1040 {
1041         struct mlx5_priv *priv = dev->data->dev_private;
1042         struct mlx5_proc_priv *ppriv;
1043         size_t ppriv_size;
1044
1045         /*
1046          * UAR register table follows the process private structure. BlueFlame
1047          * registers for Tx queues are stored in the table.
1048          */
1049         ppriv_size =
1050                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1051         ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
1052                                   RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1053         if (!ppriv) {
1054                 rte_errno = ENOMEM;
1055                 return -rte_errno;
1056         }
1057         ppriv->uar_table_sz = ppriv_size;
1058         dev->process_private = ppriv;
1059         return 0;
1060 }
1061
1062 /**
1063  * Un-initialize process private data structure.
1064  *
1065  * @param dev
1066  *   Pointer to Ethernet device structure.
1067  */
1068 static void
1069 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1070 {
1071         if (!dev->process_private)
1072                 return;
1073         rte_free(dev->process_private);
1074         dev->process_private = NULL;
1075 }
1076
1077 /**
1078  * DPDK callback to close the device.
1079  *
1080  * Destroy all queues and objects, free memory.
1081  *
1082  * @param dev
1083  *   Pointer to Ethernet device structure.
1084  */
1085 void
1086 mlx5_dev_close(struct rte_eth_dev *dev)
1087 {
1088         struct mlx5_priv *priv = dev->data->dev_private;
1089         unsigned int i;
1090         int ret;
1091
1092         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1093                 /* Check if process_private released. */
1094                 if (!dev->process_private)
1095                         return;
1096                 mlx5_tx_uar_uninit_secondary(dev);
1097                 mlx5_proc_priv_uninit(dev);
1098                 rte_eth_dev_release_port(dev);
1099                 return;
1100         }
1101         if (!priv->sh)
1102                 return;
1103         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1104                 dev->data->port_id,
1105                 ((priv->sh->ctx != NULL) ?
1106                 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1107         /*
1108          * If default mreg copy action is removed at the stop stage,
1109          * the search will return none and nothing will be done anymore.
1110          */
1111         mlx5_flow_stop_default(dev);
1112         mlx5_traffic_disable(dev);
1113         /*
1114          * If all the flows are already flushed in the device stop stage,
1115          * then this will return directly without any action.
1116          */
1117         mlx5_flow_list_flush(dev, &priv->flows, true);
1118         mlx5_flow_meter_flush(dev, NULL);
1119         /* Free the intermediate buffers for flow creation. */
1120         mlx5_flow_free_intermediate(dev);
1121         /* Prevent crashes when queues are still in use. */
1122         dev->rx_pkt_burst = removed_rx_burst;
1123         dev->tx_pkt_burst = removed_tx_burst;
1124         rte_wmb();
1125         /* Disable datapath on secondary process. */
1126         mlx5_mp_req_stop_rxtx(dev);
1127         if (priv->rxqs != NULL) {
1128                 /* XXX race condition if mlx5_rx_burst() is still running. */
1129                 usleep(1000);
1130                 for (i = 0; (i != priv->rxqs_n); ++i)
1131                         mlx5_rxq_release(dev, i);
1132                 priv->rxqs_n = 0;
1133                 priv->rxqs = NULL;
1134         }
1135         if (priv->txqs != NULL) {
1136                 /* XXX race condition if mlx5_tx_burst() is still running. */
1137                 usleep(1000);
1138                 for (i = 0; (i != priv->txqs_n); ++i)
1139                         mlx5_txq_release(dev, i);
1140                 priv->txqs_n = 0;
1141                 priv->txqs = NULL;
1142         }
1143         mlx5_proc_priv_uninit(dev);
1144         if (priv->mreg_cp_tbl)
1145                 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1146         mlx5_mprq_free_mp(dev);
1147         mlx5_os_free_shared_dr(priv);
1148         if (priv->rss_conf.rss_key != NULL)
1149                 rte_free(priv->rss_conf.rss_key);
1150         if (priv->reta_idx != NULL)
1151                 rte_free(priv->reta_idx);
1152         if (priv->config.vf)
1153                 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1154                                        dev->data->mac_addrs,
1155                                        MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1156         if (priv->nl_socket_route >= 0)
1157                 close(priv->nl_socket_route);
1158         if (priv->nl_socket_rdma >= 0)
1159                 close(priv->nl_socket_rdma);
1160         if (priv->vmwa_context)
1161                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1162         ret = mlx5_hrxq_verify(dev);
1163         if (ret)
1164                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1165                         dev->data->port_id);
1166         ret = mlx5_ind_table_obj_verify(dev);
1167         if (ret)
1168                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1169                         dev->data->port_id);
1170         ret = mlx5_rxq_obj_verify(dev);
1171         if (ret)
1172                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1173                         dev->data->port_id);
1174         ret = mlx5_rxq_verify(dev);
1175         if (ret)
1176                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1177                         dev->data->port_id);
1178         ret = mlx5_txq_obj_verify(dev);
1179         if (ret)
1180                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1181                         dev->data->port_id);
1182         ret = mlx5_txq_verify(dev);
1183         if (ret)
1184                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1185                         dev->data->port_id);
1186         ret = mlx5_flow_verify(dev);
1187         if (ret)
1188                 DRV_LOG(WARNING, "port %u some flows still remain",
1189                         dev->data->port_id);
1190         /*
1191          * Free the shared context in last turn, because the cleanup
1192          * routines above may use some shared fields, like
1193          * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1194          * ifindex if Netlink fails.
1195          */
1196         mlx5_free_shared_ibctx(priv->sh);
1197         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1198                 unsigned int c = 0;
1199                 uint16_t port_id;
1200
1201                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1202                         struct mlx5_priv *opriv =
1203                                 rte_eth_devices[port_id].data->dev_private;
1204
1205                         if (!opriv ||
1206                             opriv->domain_id != priv->domain_id ||
1207                             &rte_eth_devices[port_id] == dev)
1208                                 continue;
1209                         ++c;
1210                         break;
1211                 }
1212                 if (!c)
1213                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1214         }
1215         memset(priv, 0, sizeof(*priv));
1216         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1217         /*
1218          * Reset mac_addrs to NULL such that it is not freed as part of
1219          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1220          * it is freed when dev_private is freed.
1221          */
1222         dev->data->mac_addrs = NULL;
1223 }
1224
1225 const struct eth_dev_ops mlx5_dev_ops = {
1226         .dev_configure = mlx5_dev_configure,
1227         .dev_start = mlx5_dev_start,
1228         .dev_stop = mlx5_dev_stop,
1229         .dev_set_link_down = mlx5_set_link_down,
1230         .dev_set_link_up = mlx5_set_link_up,
1231         .dev_close = mlx5_dev_close,
1232         .promiscuous_enable = mlx5_promiscuous_enable,
1233         .promiscuous_disable = mlx5_promiscuous_disable,
1234         .allmulticast_enable = mlx5_allmulticast_enable,
1235         .allmulticast_disable = mlx5_allmulticast_disable,
1236         .link_update = mlx5_link_update,
1237         .stats_get = mlx5_stats_get,
1238         .stats_reset = mlx5_stats_reset,
1239         .xstats_get = mlx5_xstats_get,
1240         .xstats_reset = mlx5_xstats_reset,
1241         .xstats_get_names = mlx5_xstats_get_names,
1242         .fw_version_get = mlx5_fw_version_get,
1243         .dev_infos_get = mlx5_dev_infos_get,
1244         .read_clock = mlx5_read_clock,
1245         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1246         .vlan_filter_set = mlx5_vlan_filter_set,
1247         .rx_queue_setup = mlx5_rx_queue_setup,
1248         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1249         .tx_queue_setup = mlx5_tx_queue_setup,
1250         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1251         .rx_queue_release = mlx5_rx_queue_release,
1252         .tx_queue_release = mlx5_tx_queue_release,
1253         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1254         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1255         .mac_addr_remove = mlx5_mac_addr_remove,
1256         .mac_addr_add = mlx5_mac_addr_add,
1257         .mac_addr_set = mlx5_mac_addr_set,
1258         .set_mc_addr_list = mlx5_set_mc_addr_list,
1259         .mtu_set = mlx5_dev_set_mtu,
1260         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1261         .vlan_offload_set = mlx5_vlan_offload_set,
1262         .reta_update = mlx5_dev_rss_reta_update,
1263         .reta_query = mlx5_dev_rss_reta_query,
1264         .rss_hash_update = mlx5_rss_hash_update,
1265         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1266         .filter_ctrl = mlx5_dev_filter_ctrl,
1267         .rx_descriptor_status = mlx5_rx_descriptor_status,
1268         .tx_descriptor_status = mlx5_tx_descriptor_status,
1269         .rxq_info_get = mlx5_rxq_info_get,
1270         .txq_info_get = mlx5_txq_info_get,
1271         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1272         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1273         .rx_queue_count = mlx5_rx_queue_count,
1274         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1275         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1276         .is_removed = mlx5_is_removed,
1277         .udp_tunnel_port_add  = mlx5_udp_tunnel_port_add,
1278         .get_module_info = mlx5_get_module_info,
1279         .get_module_eeprom = mlx5_get_module_eeprom,
1280         .hairpin_cap_get = mlx5_hairpin_cap_get,
1281         .mtr_ops_get = mlx5_flow_meter_ops_get,
1282 };
1283
1284 /* Available operations from secondary process. */
1285 const struct eth_dev_ops mlx5_dev_sec_ops = {
1286         .stats_get = mlx5_stats_get,
1287         .stats_reset = mlx5_stats_reset,
1288         .xstats_get = mlx5_xstats_get,
1289         .xstats_reset = mlx5_xstats_reset,
1290         .xstats_get_names = mlx5_xstats_get_names,
1291         .fw_version_get = mlx5_fw_version_get,
1292         .dev_infos_get = mlx5_dev_infos_get,
1293         .rx_descriptor_status = mlx5_rx_descriptor_status,
1294         .tx_descriptor_status = mlx5_tx_descriptor_status,
1295         .rxq_info_get = mlx5_rxq_info_get,
1296         .txq_info_get = mlx5_txq_info_get,
1297         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1298         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1299         .get_module_info = mlx5_get_module_info,
1300         .get_module_eeprom = mlx5_get_module_eeprom,
1301 };
1302
1303 /* Available operations in flow isolated mode. */
1304 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1305         .dev_configure = mlx5_dev_configure,
1306         .dev_start = mlx5_dev_start,
1307         .dev_stop = mlx5_dev_stop,
1308         .dev_set_link_down = mlx5_set_link_down,
1309         .dev_set_link_up = mlx5_set_link_up,
1310         .dev_close = mlx5_dev_close,
1311         .promiscuous_enable = mlx5_promiscuous_enable,
1312         .promiscuous_disable = mlx5_promiscuous_disable,
1313         .allmulticast_enable = mlx5_allmulticast_enable,
1314         .allmulticast_disable = mlx5_allmulticast_disable,
1315         .link_update = mlx5_link_update,
1316         .stats_get = mlx5_stats_get,
1317         .stats_reset = mlx5_stats_reset,
1318         .xstats_get = mlx5_xstats_get,
1319         .xstats_reset = mlx5_xstats_reset,
1320         .xstats_get_names = mlx5_xstats_get_names,
1321         .fw_version_get = mlx5_fw_version_get,
1322         .dev_infos_get = mlx5_dev_infos_get,
1323         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1324         .vlan_filter_set = mlx5_vlan_filter_set,
1325         .rx_queue_setup = mlx5_rx_queue_setup,
1326         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1327         .tx_queue_setup = mlx5_tx_queue_setup,
1328         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1329         .rx_queue_release = mlx5_rx_queue_release,
1330         .tx_queue_release = mlx5_tx_queue_release,
1331         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1332         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1333         .mac_addr_remove = mlx5_mac_addr_remove,
1334         .mac_addr_add = mlx5_mac_addr_add,
1335         .mac_addr_set = mlx5_mac_addr_set,
1336         .set_mc_addr_list = mlx5_set_mc_addr_list,
1337         .mtu_set = mlx5_dev_set_mtu,
1338         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1339         .vlan_offload_set = mlx5_vlan_offload_set,
1340         .filter_ctrl = mlx5_dev_filter_ctrl,
1341         .rx_descriptor_status = mlx5_rx_descriptor_status,
1342         .tx_descriptor_status = mlx5_tx_descriptor_status,
1343         .rxq_info_get = mlx5_rxq_info_get,
1344         .txq_info_get = mlx5_txq_info_get,
1345         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1346         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1347         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1348         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1349         .is_removed = mlx5_is_removed,
1350         .get_module_info = mlx5_get_module_info,
1351         .get_module_eeprom = mlx5_get_module_eeprom,
1352         .hairpin_cap_get = mlx5_hairpin_cap_get,
1353         .mtr_ops_get = mlx5_flow_meter_ops_get,
1354 };
1355
1356 /**
1357  * Verify and store value for device argument.
1358  *
1359  * @param[in] key
1360  *   Key argument to verify.
1361  * @param[in] val
1362  *   Value associated with key.
1363  * @param opaque
1364  *   User data.
1365  *
1366  * @return
1367  *   0 on success, a negative errno value otherwise and rte_errno is set.
1368  */
1369 static int
1370 mlx5_args_check(const char *key, const char *val, void *opaque)
1371 {
1372         struct mlx5_dev_config *config = opaque;
1373         unsigned long tmp;
1374
1375         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1376         if (!strcmp(MLX5_REPRESENTOR, key))
1377                 return 0;
1378         errno = 0;
1379         tmp = strtoul(val, NULL, 0);
1380         if (errno) {
1381                 rte_errno = errno;
1382                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1383                 return -rte_errno;
1384         }
1385         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1386                 config->cqe_comp = !!tmp;
1387         } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1388                 config->cqe_pad = !!tmp;
1389         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1390                 config->hw_padding = !!tmp;
1391         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1392                 config->mprq.enabled = !!tmp;
1393         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1394                 config->mprq.stride_num_n = tmp;
1395         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1396                 config->mprq.stride_size_n = tmp;
1397         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1398                 config->mprq.max_memcpy_len = tmp;
1399         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1400                 config->mprq.min_rxqs_num = tmp;
1401         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1402                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1403                                  " converted to txq_inline_max", key);
1404                 config->txq_inline_max = tmp;
1405         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1406                 config->txq_inline_max = tmp;
1407         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1408                 config->txq_inline_min = tmp;
1409         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1410                 config->txq_inline_mpw = tmp;
1411         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1412                 config->txqs_inline = tmp;
1413         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1414                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1415         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1416                 config->mps = !!tmp;
1417         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1418                 if (tmp != MLX5_TXDB_CACHED &&
1419                     tmp != MLX5_TXDB_NCACHED &&
1420                     tmp != MLX5_TXDB_HEURISTIC) {
1421                         DRV_LOG(ERR, "invalid Tx doorbell "
1422                                      "mapping parameter");
1423                         rte_errno = EINVAL;
1424                         return -rte_errno;
1425                 }
1426                 config->dbnc = tmp;
1427         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1428                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1429         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1430                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1431                                  " converted to txq_inline_mpw", key);
1432                 config->txq_inline_mpw = tmp;
1433         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1434                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1435         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1436                 config->rx_vec_en = !!tmp;
1437         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1438                 config->l3_vxlan_en = !!tmp;
1439         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1440                 config->vf_nl_en = !!tmp;
1441         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1442                 config->dv_esw_en = !!tmp;
1443         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1444                 config->dv_flow_en = !!tmp;
1445         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1446                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1447                     tmp != MLX5_XMETA_MODE_META16 &&
1448                     tmp != MLX5_XMETA_MODE_META32) {
1449                         DRV_LOG(ERR, "invalid extensive "
1450                                      "metadata parameter");
1451                         rte_errno = EINVAL;
1452                         return -rte_errno;
1453                 }
1454                 config->dv_xmeta_en = tmp;
1455         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1456                 config->mr_ext_memseg_en = !!tmp;
1457         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1458                 config->max_dump_files_num = tmp;
1459         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1460                 config->lro.timeout = tmp;
1461         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1462                 DRV_LOG(DEBUG, "class argument is %s.", val);
1463         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1464                 config->log_hp_size = tmp;
1465         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1466                 if (tmp != MLX5_RCM_NONE &&
1467                     tmp != MLX5_RCM_LIGHT &&
1468                     tmp != MLX5_RCM_AGGR) {
1469                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1470                         rte_errno = EINVAL;
1471                         return -rte_errno;
1472                 }
1473                 config->reclaim_mode = tmp;
1474         } else {
1475                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1476                 rte_errno = EINVAL;
1477                 return -rte_errno;
1478         }
1479         return 0;
1480 }
1481
1482 /**
1483  * Parse device parameters.
1484  *
1485  * @param config
1486  *   Pointer to device configuration structure.
1487  * @param devargs
1488  *   Device arguments structure.
1489  *
1490  * @return
1491  *   0 on success, a negative errno value otherwise and rte_errno is set.
1492  */
1493 int
1494 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1495 {
1496         const char **params = (const char *[]){
1497                 MLX5_RXQ_CQE_COMP_EN,
1498                 MLX5_RXQ_CQE_PAD_EN,
1499                 MLX5_RXQ_PKT_PAD_EN,
1500                 MLX5_RX_MPRQ_EN,
1501                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1502                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1503                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1504                 MLX5_RXQS_MIN_MPRQ,
1505                 MLX5_TXQ_INLINE,
1506                 MLX5_TXQ_INLINE_MIN,
1507                 MLX5_TXQ_INLINE_MAX,
1508                 MLX5_TXQ_INLINE_MPW,
1509                 MLX5_TXQS_MIN_INLINE,
1510                 MLX5_TXQS_MAX_VEC,
1511                 MLX5_TXQ_MPW_EN,
1512                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1513                 MLX5_TXQ_MAX_INLINE_LEN,
1514                 MLX5_TX_DB_NC,
1515                 MLX5_TX_VEC_EN,
1516                 MLX5_RX_VEC_EN,
1517                 MLX5_L3_VXLAN_EN,
1518                 MLX5_VF_NL_EN,
1519                 MLX5_DV_ESW_EN,
1520                 MLX5_DV_FLOW_EN,
1521                 MLX5_DV_XMETA_EN,
1522                 MLX5_MR_EXT_MEMSEG_EN,
1523                 MLX5_REPRESENTOR,
1524                 MLX5_MAX_DUMP_FILES_NUM,
1525                 MLX5_LRO_TIMEOUT_USEC,
1526                 MLX5_CLASS_ARG_NAME,
1527                 MLX5_HP_BUF_SIZE,
1528                 MLX5_RECLAIM_MEM,
1529                 NULL,
1530         };
1531         struct rte_kvargs *kvlist;
1532         int ret = 0;
1533         int i;
1534
1535         if (devargs == NULL)
1536                 return 0;
1537         /* Following UGLY cast is done to pass checkpatch. */
1538         kvlist = rte_kvargs_parse(devargs->args, params);
1539         if (kvlist == NULL) {
1540                 rte_errno = EINVAL;
1541                 return -rte_errno;
1542         }
1543         /* Process parameters. */
1544         for (i = 0; (params[i] != NULL); ++i) {
1545                 if (rte_kvargs_count(kvlist, params[i])) {
1546                         ret = rte_kvargs_process(kvlist, params[i],
1547                                                  mlx5_args_check, config);
1548                         if (ret) {
1549                                 rte_errno = EINVAL;
1550                                 rte_kvargs_free(kvlist);
1551                                 return -rte_errno;
1552                         }
1553                 }
1554         }
1555         rte_kvargs_free(kvlist);
1556         return 0;
1557 }
1558
1559 /**
1560  * PMD global initialization.
1561  *
1562  * Independent from individual device, this function initializes global
1563  * per-PMD data structures distinguishing primary and secondary processes.
1564  * Hence, each initialization is called once per a process.
1565  *
1566  * @return
1567  *   0 on success, a negative errno value otherwise and rte_errno is set.
1568  */
1569 int
1570 mlx5_init_once(void)
1571 {
1572         struct mlx5_shared_data *sd;
1573         struct mlx5_local_data *ld = &mlx5_local_data;
1574         int ret = 0;
1575
1576         if (mlx5_init_shared_data())
1577                 return -rte_errno;
1578         sd = mlx5_shared_data;
1579         MLX5_ASSERT(sd);
1580         rte_spinlock_lock(&sd->lock);
1581         switch (rte_eal_process_type()) {
1582         case RTE_PROC_PRIMARY:
1583                 if (sd->init_done)
1584                         break;
1585                 LIST_INIT(&sd->mem_event_cb_list);
1586                 rte_rwlock_init(&sd->mem_event_rwlock);
1587                 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1588                                                 mlx5_mr_mem_event_cb, NULL);
1589                 ret = mlx5_mp_init_primary(MLX5_MP_NAME,
1590                                            mlx5_mp_primary_handle);
1591                 if (ret)
1592                         goto out;
1593                 sd->init_done = true;
1594                 break;
1595         case RTE_PROC_SECONDARY:
1596                 if (ld->init_done)
1597                         break;
1598                 ret = mlx5_mp_init_secondary(MLX5_MP_NAME,
1599                                              mlx5_mp_secondary_handle);
1600                 if (ret)
1601                         goto out;
1602                 ++sd->secondary_cnt;
1603                 ld->init_done = true;
1604                 break;
1605         default:
1606                 break;
1607         }
1608 out:
1609         rte_spinlock_unlock(&sd->lock);
1610         return ret;
1611 }
1612
1613 /**
1614  * Configures the minimal amount of data to inline into WQE
1615  * while sending packets.
1616  *
1617  * - the txq_inline_min has the maximal priority, if this
1618  *   key is specified in devargs
1619  * - if DevX is enabled the inline mode is queried from the
1620  *   device (HCA attributes and NIC vport context if needed).
1621  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1622  *   and none (0 bytes) for other NICs
1623  *
1624  * @param spawn
1625  *   Verbs device parameters (name, port, switch_info) to spawn.
1626  * @param config
1627  *   Device configuration parameters.
1628  */
1629 void
1630 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1631                     struct mlx5_dev_config *config)
1632 {
1633         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1634                 /* Application defines size of inlined data explicitly. */
1635                 switch (spawn->pci_dev->id.device_id) {
1636                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1637                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1638                         if (config->txq_inline_min <
1639                                        (int)MLX5_INLINE_HSIZE_L2) {
1640                                 DRV_LOG(DEBUG,
1641                                         "txq_inline_mix aligned to minimal"
1642                                         " ConnectX-4 required value %d",
1643                                         (int)MLX5_INLINE_HSIZE_L2);
1644                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1645                         }
1646                         break;
1647                 }
1648                 goto exit;
1649         }
1650         if (config->hca_attr.eth_net_offloads) {
1651                 /* We have DevX enabled, inline mode queried successfully. */
1652                 switch (config->hca_attr.wqe_inline_mode) {
1653                 case MLX5_CAP_INLINE_MODE_L2:
1654                         /* outer L2 header must be inlined. */
1655                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1656                         goto exit;
1657                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1658                         /* No inline data are required by NIC. */
1659                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1660                         config->hw_vlan_insert =
1661                                 config->hca_attr.wqe_vlan_insert;
1662                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1663                         goto exit;
1664                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1665                         /* inline mode is defined by NIC vport context. */
1666                         if (!config->hca_attr.eth_virt)
1667                                 break;
1668                         switch (config->hca_attr.vport_inline_mode) {
1669                         case MLX5_INLINE_MODE_NONE:
1670                                 config->txq_inline_min =
1671                                         MLX5_INLINE_HSIZE_NONE;
1672                                 goto exit;
1673                         case MLX5_INLINE_MODE_L2:
1674                                 config->txq_inline_min =
1675                                         MLX5_INLINE_HSIZE_L2;
1676                                 goto exit;
1677                         case MLX5_INLINE_MODE_IP:
1678                                 config->txq_inline_min =
1679                                         MLX5_INLINE_HSIZE_L3;
1680                                 goto exit;
1681                         case MLX5_INLINE_MODE_TCP_UDP:
1682                                 config->txq_inline_min =
1683                                         MLX5_INLINE_HSIZE_L4;
1684                                 goto exit;
1685                         case MLX5_INLINE_MODE_INNER_L2:
1686                                 config->txq_inline_min =
1687                                         MLX5_INLINE_HSIZE_INNER_L2;
1688                                 goto exit;
1689                         case MLX5_INLINE_MODE_INNER_IP:
1690                                 config->txq_inline_min =
1691                                         MLX5_INLINE_HSIZE_INNER_L3;
1692                                 goto exit;
1693                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
1694                                 config->txq_inline_min =
1695                                         MLX5_INLINE_HSIZE_INNER_L4;
1696                                 goto exit;
1697                         }
1698                 }
1699         }
1700         /*
1701          * We get here if we are unable to deduce
1702          * inline data size with DevX. Try PCI ID
1703          * to determine old NICs.
1704          */
1705         switch (spawn->pci_dev->id.device_id) {
1706         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1707         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1708         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1709         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1710                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1711                 config->hw_vlan_insert = 0;
1712                 break;
1713         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1714         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1715         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1716         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1717                 /*
1718                  * These NICs support VLAN insertion from WQE and
1719                  * report the wqe_vlan_insert flag. But there is the bug
1720                  * and PFC control may be broken, so disable feature.
1721                  */
1722                 config->hw_vlan_insert = 0;
1723                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1724                 break;
1725         default:
1726                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1727                 break;
1728         }
1729 exit:
1730         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1731 }
1732
1733 /**
1734  * Configures the metadata mask fields in the shared context.
1735  *
1736  * @param [in] dev
1737  *   Pointer to Ethernet device.
1738  */
1739 void
1740 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1741 {
1742         struct mlx5_priv *priv = dev->data->dev_private;
1743         struct mlx5_dev_ctx_shared *sh = priv->sh;
1744         uint32_t meta, mark, reg_c0;
1745
1746         reg_c0 = ~priv->vport_meta_mask;
1747         switch (priv->config.dv_xmeta_en) {
1748         case MLX5_XMETA_MODE_LEGACY:
1749                 meta = UINT32_MAX;
1750                 mark = MLX5_FLOW_MARK_MASK;
1751                 break;
1752         case MLX5_XMETA_MODE_META16:
1753                 meta = reg_c0 >> rte_bsf32(reg_c0);
1754                 mark = MLX5_FLOW_MARK_MASK;
1755                 break;
1756         case MLX5_XMETA_MODE_META32:
1757                 meta = UINT32_MAX;
1758                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1759                 break;
1760         default:
1761                 meta = 0;
1762                 mark = 0;
1763                 MLX5_ASSERT(false);
1764                 break;
1765         }
1766         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1767                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1768                                  sh->dv_mark_mask, mark);
1769         else
1770                 sh->dv_mark_mask = mark;
1771         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1772                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1773                                  sh->dv_meta_mask, meta);
1774         else
1775                 sh->dv_meta_mask = meta;
1776         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1777                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1778                                  sh->dv_meta_mask, reg_c0);
1779         else
1780                 sh->dv_regc0_mask = reg_c0;
1781         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1782         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1783         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1784         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1785 }
1786
1787 /**
1788  * Allocate page of door-bells and register it using DevX API.
1789  *
1790  * @param [in] dev
1791  *   Pointer to Ethernet device.
1792  *
1793  * @return
1794  *   Pointer to new page on success, NULL otherwise.
1795  */
1796 static struct mlx5_devx_dbr_page *
1797 mlx5_alloc_dbr_page(struct rte_eth_dev *dev)
1798 {
1799         struct mlx5_priv *priv = dev->data->dev_private;
1800         struct mlx5_devx_dbr_page *page;
1801
1802         /* Allocate space for door-bell page and management data. */
1803         page = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_devx_dbr_page),
1804                                  RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1805         if (!page) {
1806                 DRV_LOG(ERR, "port %u cannot allocate dbr page",
1807                         dev->data->port_id);
1808                 return NULL;
1809         }
1810         /* Register allocated memory. */
1811         page->umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, page->dbrs,
1812                                               MLX5_DBR_PAGE_SIZE, 0);
1813         if (!page->umem) {
1814                 DRV_LOG(ERR, "port %u cannot umem reg dbr page",
1815                         dev->data->port_id);
1816                 rte_free(page);
1817                 return NULL;
1818         }
1819         return page;
1820 }
1821
1822 /**
1823  * Find the next available door-bell, allocate new page if needed.
1824  *
1825  * @param [in] dev
1826  *   Pointer to Ethernet device.
1827  * @param [out] dbr_page
1828  *   Door-bell page containing the page data.
1829  *
1830  * @return
1831  *   Door-bell address offset on success, a negative error value otherwise.
1832  */
1833 int64_t
1834 mlx5_get_dbr(struct rte_eth_dev *dev, struct mlx5_devx_dbr_page **dbr_page)
1835 {
1836         struct mlx5_priv *priv = dev->data->dev_private;
1837         struct mlx5_devx_dbr_page *page = NULL;
1838         uint32_t i, j;
1839
1840         LIST_FOREACH(page, &priv->dbrpgs, next)
1841                 if (page->dbr_count < MLX5_DBR_PER_PAGE)
1842                         break;
1843         if (!page) { /* No page with free door-bell exists. */
1844                 page = mlx5_alloc_dbr_page(dev);
1845                 if (!page) /* Failed to allocate new page. */
1846                         return (-1);
1847                 LIST_INSERT_HEAD(&priv->dbrpgs, page, next);
1848         }
1849         /* Loop to find bitmap part with clear bit. */
1850         for (i = 0;
1851              i < MLX5_DBR_BITMAP_SIZE && page->dbr_bitmap[i] == UINT64_MAX;
1852              i++)
1853                 ; /* Empty. */
1854         /* Find the first clear bit. */
1855         MLX5_ASSERT(i < MLX5_DBR_BITMAP_SIZE);
1856         j = rte_bsf64(~page->dbr_bitmap[i]);
1857         page->dbr_bitmap[i] |= (UINT64_C(1) << j);
1858         page->dbr_count++;
1859         *dbr_page = page;
1860         return (((i * 64) + j) * sizeof(uint64_t));
1861 }
1862
1863 /**
1864  * Release a door-bell record.
1865  *
1866  * @param [in] dev
1867  *   Pointer to Ethernet device.
1868  * @param [in] umem_id
1869  *   UMEM ID of page containing the door-bell record to release.
1870  * @param [in] offset
1871  *   Offset of door-bell record in page.
1872  *
1873  * @return
1874  *   0 on success, a negative error value otherwise.
1875  */
1876 int32_t
1877 mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id, uint64_t offset)
1878 {
1879         struct mlx5_priv *priv = dev->data->dev_private;
1880         struct mlx5_devx_dbr_page *page = NULL;
1881         int ret = 0;
1882
1883         LIST_FOREACH(page, &priv->dbrpgs, next)
1884                 /* Find the page this address belongs to. */
1885                 if (mlx5_os_get_umem_id(page->umem) == umem_id)
1886                         break;
1887         if (!page)
1888                 return -EINVAL;
1889         page->dbr_count--;
1890         if (!page->dbr_count) {
1891                 /* Page not used, free it and remove from list. */
1892                 LIST_REMOVE(page, next);
1893                 if (page->umem)
1894                         ret = -mlx5_glue->devx_umem_dereg(page->umem);
1895                 rte_free(page);
1896         } else {
1897                 /* Mark in bitmap that this door-bell is not in use. */
1898                 offset /= MLX5_DBR_SIZE;
1899                 int i = offset / 64;
1900                 int j = offset % 64;
1901
1902                 page->dbr_bitmap[i] &= ~(UINT64_C(1) << j);
1903         }
1904         return ret;
1905 }
1906
1907 int
1908 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1909 {
1910         static const char *const dynf_names[] = {
1911                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1912                 RTE_MBUF_DYNFLAG_METADATA_NAME
1913         };
1914         unsigned int i;
1915
1916         if (n < RTE_DIM(dynf_names))
1917                 return -ENOMEM;
1918         for (i = 0; i < RTE_DIM(dynf_names); i++) {
1919                 if (names[i] == NULL)
1920                         return -EINVAL;
1921                 strcpy(names[i], dynf_names[i]);
1922         }
1923         return RTE_DIM(dynf_names);
1924 }
1925
1926 /**
1927  * Comparison callback to sort device data.
1928  *
1929  * This is meant to be used with qsort().
1930  *
1931  * @param a[in]
1932  *   Pointer to pointer to first data object.
1933  * @param b[in]
1934  *   Pointer to pointer to second data object.
1935  *
1936  * @return
1937  *   0 if both objects are equal, less than 0 if the first argument is less
1938  *   than the second, greater than 0 otherwise.
1939  */
1940 int
1941 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1942                               struct mlx5_dev_config *config)
1943 {
1944         struct mlx5_dev_ctx_shared *sh = priv->sh;
1945         struct mlx5_dev_config *sh_conf = NULL;
1946         uint16_t port_id;
1947
1948         MLX5_ASSERT(sh);
1949         /* Nothing to compare for the single/first device. */
1950         if (sh->refcnt == 1)
1951                 return 0;
1952         /* Find the device with shared context. */
1953         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1954                 struct mlx5_priv *opriv =
1955                         rte_eth_devices[port_id].data->dev_private;
1956
1957                 if (opriv && opriv != priv && opriv->sh == sh) {
1958                         sh_conf = &opriv->config;
1959                         break;
1960                 }
1961         }
1962         if (!sh_conf)
1963                 return 0;
1964         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1965                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1966                              " for shared %s context", sh->ibdev_name);
1967                 rte_errno = EINVAL;
1968                 return rte_errno;
1969         }
1970         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1971                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1972                              " for shared %s context", sh->ibdev_name);
1973                 rte_errno = EINVAL;
1974                 return rte_errno;
1975         }
1976         return 0;
1977 }
1978
1979 /**
1980  * Look for the ethernet device belonging to mlx5 driver.
1981  *
1982  * @param[in] port_id
1983  *   port_id to start looking for device.
1984  * @param[in] pci_dev
1985  *   Pointer to the hint PCI device. When device is being probed
1986  *   the its siblings (master and preceding representors might
1987  *   not have assigned driver yet (because the mlx5_os_pci_probe()
1988  *   is not completed yet, for this case match on hint PCI
1989  *   device may be used to detect sibling device.
1990  *
1991  * @return
1992  *   port_id of found device, RTE_MAX_ETHPORT if not found.
1993  */
1994 uint16_t
1995 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
1996 {
1997         while (port_id < RTE_MAX_ETHPORTS) {
1998                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
1999
2000                 if (dev->state != RTE_ETH_DEV_UNUSED &&
2001                     dev->device &&
2002                     (dev->device == &pci_dev->device ||
2003                      (dev->device->driver &&
2004                      dev->device->driver->name &&
2005                      !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
2006                         break;
2007                 port_id++;
2008         }
2009         if (port_id >= RTE_MAX_ETHPORTS)
2010                 return RTE_MAX_ETHPORTS;
2011         return port_id;
2012 }
2013
2014 /**
2015  * DPDK callback to remove a PCI device.
2016  *
2017  * This function removes all Ethernet devices belong to a given PCI device.
2018  *
2019  * @param[in] pci_dev
2020  *   Pointer to the PCI device.
2021  *
2022  * @return
2023  *   0 on success, the function cannot fail.
2024  */
2025 static int
2026 mlx5_pci_remove(struct rte_pci_device *pci_dev)
2027 {
2028         uint16_t port_id;
2029
2030         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
2031                 /*
2032                  * mlx5_dev_close() is not registered to secondary process,
2033                  * call the close function explicitly for secondary process.
2034                  */
2035                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2036                         mlx5_dev_close(&rte_eth_devices[port_id]);
2037                 else
2038                         rte_eth_dev_close(port_id);
2039         }
2040         return 0;
2041 }
2042
2043 static const struct rte_pci_id mlx5_pci_id_map[] = {
2044         {
2045                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2046                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2047         },
2048         {
2049                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2050                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2051         },
2052         {
2053                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2054                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2055         },
2056         {
2057                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2058                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2059         },
2060         {
2061                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2062                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2063         },
2064         {
2065                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2066                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2067         },
2068         {
2069                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2070                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2071         },
2072         {
2073                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2074                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2075         },
2076         {
2077                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2078                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2079         },
2080         {
2081                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2082                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2083         },
2084         {
2085                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2086                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2087         },
2088         {
2089                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2090                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2091         },
2092         {
2093                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2094                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2095         },
2096         {
2097                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2098                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
2099         },
2100         {
2101                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2102                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2103         },
2104         {
2105                 .vendor_id = 0
2106         }
2107 };
2108
2109 struct rte_pci_driver mlx5_driver = {
2110         .driver = {
2111                 .name = MLX5_DRIVER_NAME
2112         },
2113         .id_table = mlx5_pci_id_map,
2114         .probe = mlx5_os_pci_probe,
2115         .remove = mlx5_pci_remove,
2116         .dma_map = mlx5_dma_map,
2117         .dma_unmap = mlx5_dma_unmap,
2118         .drv_flags = PCI_DRV_FLAGS,
2119 };
2120
2121 /**
2122  * Driver initialization routine.
2123  */
2124 RTE_INIT(rte_mlx5_pmd_init)
2125 {
2126         /* Initialize driver log type. */
2127         mlx5_logtype = rte_log_register("pmd.net.mlx5");
2128         if (mlx5_logtype >= 0)
2129                 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
2130
2131         /* Build the static tables for Verbs conversion. */
2132         mlx5_set_ptype_table();
2133         mlx5_set_cksum_table();
2134         mlx5_set_swp_types_table();
2135         if (mlx5_glue)
2136                 rte_pci_register(&mlx5_driver);
2137 }
2138
2139 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2140 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2141 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");