drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12 #include <net/if.h>
  13 #include <sys/mman.h>
  14 #include <linux/rtnetlink.h>
  15
  16 /* Verbs header. */
  17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  18 #ifdef PEDANTIC
  19 #pragma GCC diagnostic ignored "-Wpedantic"
  20 #endif
  21 #include <infiniband/verbs.h>
  22 #ifdef PEDANTIC
  23 #pragma GCC diagnostic error "-Wpedantic"
  24 #endif
  25
  26 #include <rte_malloc.h>
  27 #include <rte_ethdev_driver.h>
  28 #include <rte_ethdev_pci.h>
  29 #include <rte_pci.h>
  30 #include <rte_bus_pci.h>
  31 #include <rte_common.h>
  32 #include <rte_kvargs.h>
  33 #include <rte_rwlock.h>
  34 #include <rte_spinlock.h>
  35 #include <rte_string_fns.h>
  36 #include <rte_alarm.h>
  37
  38 #include <mlx5_glue.h>
  39 #include <mlx5_devx_cmds.h>
  40 #include <mlx5_common.h>
  41 #include <mlx5_common_mp.h>
  42
  43 #include "mlx5_defs.h"
  44 #include "mlx5.h"
  45 #include "mlx5_utils.h"
  46 #include "mlx5_rxtx.h"
  47 #include "mlx5_autoconf.h"
  48 #include "mlx5_mr.h"
  49 #include "mlx5_flow.h"
  50 #include "rte_pmd_mlx5.h"
  51
  52 /* Device parameter to enable RX completion queue compression. */
  53 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  54
  55 /* Device parameter to enable RX completion entry padding to 128B. */
  56 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
  57
  58 /* Device parameter to enable padding Rx packet to cacheline size. */
  59 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  60
  61 /* Device parameter to enable Multi-Packet Rx queue. */
  62 #define MLX5_RX_MPRQ_EN "mprq_en"
  63
  64 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  65 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  66
  67 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  68 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  69
  70 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  71 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  72
  73 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  74 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  75
  76 /* Device parameter to configure inline send. Deprecated, ignored.*/
  77 #define MLX5_TXQ_INLINE "txq_inline"
  78
  79 /* Device parameter to limit packet size to inline with ordinary SEND. */
  80 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  81
  82 /* Device parameter to configure minimal data size to inline. */
  83 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  84
  85 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  86 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  87
  88 /*
  89  * Device parameter to configure the number of TX queues threshold for
  90  * enabling inline send.
  91  */
  92 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  93
  94 /*
  95  * Device parameter to configure the number of TX queues threshold for
  96  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  97  */
  98 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  99
 100 /* Device parameter to enable multi-packet send WQEs. */
 101 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
 102
 103 /*
 104  * Device parameter to force doorbell register mapping
 105  * to non-cahed region eliminating the extra write memory barrier.
 106  */
 107 #define MLX5_TX_DB_NC "tx_db_nc"
 108
 109 /*
 110  * Device parameter to include 2 dsegs in the title WQEBB.
 111  * Deprecated, ignored.
 112  */
 113 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 114
 115 /*
 116  * Device parameter to limit the size of inlining packet.
 117  * Deprecated, ignored.
 118  */
 119 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 120
 121 /*
 122  * Device parameter to enable hardware Tx vector.
 123  * Deprecated, ignored (no vectorized Tx routines anymore).
 124  */
 125 #define MLX5_TX_VEC_EN "tx_vec_en"
 126
 127 /* Device parameter to enable hardware Rx vector. */
 128 #define MLX5_RX_VEC_EN "rx_vec_en"
 129
 130 /* Allow L3 VXLAN flow creation. */
 131 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 132
 133 /* Activate DV E-Switch flow steering. */
 134 #define MLX5_DV_ESW_EN "dv_esw_en"
 135
 136 /* Activate DV flow steering. */
 137 #define MLX5_DV_FLOW_EN "dv_flow_en"
 138
 139 /* Enable extensive flow metadata support. */
 140 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 141
 142 /* Activate Netlink support in VF mode. */
 143 #define MLX5_VF_NL_EN "vf_nl_en"
 144
 145 /* Enable extending memsegs when creating a MR. */
 146 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 147
 148 /* Select port representors to instantiate. */
 149 #define MLX5_REPRESENTOR "representor"
 150
 151 /* Device parameter to configure the maximum number of dump files per queue. */
 152 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 153
 154 /* Configure timeout of LRO session (in microseconds). */
 155 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 156
 157 /*
 158  * Device parameter to configure the total data buffer size for a single
 159  * hairpin queue (logarithm value).
 160  */
 161 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 162
 163 /* Flow memory reclaim mode. */
 164 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 165
 166 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
 167
 168 /* Shared memory between primary and secondary processes. */
 169 struct mlx5_shared_data *mlx5_shared_data;
 170
 171 /* Spinlock for mlx5_shared_data allocation. */
 172 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
 173
 174 /* Process local data for secondary processes. */
 175 static struct mlx5_local_data mlx5_local_data;
 176 /** Driver-specific log messages type. */
 177 int mlx5_logtype;
 178
 179 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 180                                                 LIST_HEAD_INITIALIZER();
 181 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
 182
 183 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 184 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 185         {
 186                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 187                 .trunk_size = 64,
 188                 .grow_trunk = 3,
 189                 .grow_shift = 2,
 190                 .need_lock = 0,
 191                 .release_mem_en = 1,
 192                 .malloc = rte_malloc_socket,
 193                 .free = rte_free,
 194                 .type = "mlx5_encap_decap_ipool",
 195         },
 196         {
 197                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 198                 .trunk_size = 64,
 199                 .grow_trunk = 3,
 200                 .grow_shift = 2,
 201                 .need_lock = 0,
 202                 .release_mem_en = 1,
 203                 .malloc = rte_malloc_socket,
 204                 .free = rte_free,
 205                 .type = "mlx5_push_vlan_ipool",
 206         },
 207         {
 208                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 209                 .trunk_size = 64,
 210                 .grow_trunk = 3,
 211                 .grow_shift = 2,
 212                 .need_lock = 0,
 213                 .release_mem_en = 1,
 214                 .malloc = rte_malloc_socket,
 215                 .free = rte_free,
 216                 .type = "mlx5_tag_ipool",
 217         },
 218         {
 219                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 220                 .trunk_size = 64,
 221                 .grow_trunk = 3,
 222                 .grow_shift = 2,
 223                 .need_lock = 0,
 224                 .release_mem_en = 1,
 225                 .malloc = rte_malloc_socket,
 226                 .free = rte_free,
 227                 .type = "mlx5_port_id_ipool",
 228         },
 229         {
 230                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 231                 .trunk_size = 64,
 232                 .grow_trunk = 3,
 233                 .grow_shift = 2,
 234                 .need_lock = 0,
 235                 .release_mem_en = 1,
 236                 .malloc = rte_malloc_socket,
 237                 .free = rte_free,
 238                 .type = "mlx5_jump_ipool",
 239         },
 240 #endif
 241         {
 242                 .size = sizeof(struct mlx5_flow_meter),
 243                 .trunk_size = 64,
 244                 .grow_trunk = 3,
 245                 .grow_shift = 2,
 246                 .need_lock = 0,
 247                 .release_mem_en = 1,
 248                 .malloc = rte_malloc_socket,
 249                 .free = rte_free,
 250                 .type = "mlx5_meter_ipool",
 251         },
 252         {
 253                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 254                 .trunk_size = 64,
 255                 .grow_trunk = 3,
 256                 .grow_shift = 2,
 257                 .need_lock = 0,
 258                 .release_mem_en = 1,
 259                 .malloc = rte_malloc_socket,
 260                 .free = rte_free,
 261                 .type = "mlx5_mcp_ipool",
 262         },
 263         {
 264                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 265                 .trunk_size = 64,
 266                 .grow_trunk = 3,
 267                 .grow_shift = 2,
 268                 .need_lock = 0,
 269                 .release_mem_en = 1,
 270                 .malloc = rte_malloc_socket,
 271                 .free = rte_free,
 272                 .type = "mlx5_hrxq_ipool",
 273         },
 274         {
 275                 /*
 276                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 277                  * It set in run time according to PCI function configuration.
 278                  */
 279                 .size = 0,
 280                 .trunk_size = 64,
 281                 .grow_trunk = 3,
 282                 .grow_shift = 2,
 283                 .need_lock = 0,
 284                 .release_mem_en = 1,
 285                 .malloc = rte_malloc_socket,
 286                 .free = rte_free,
 287                 .type = "mlx5_flow_handle_ipool",
 288         },
 289         {
 290                 .size = sizeof(struct rte_flow),
 291                 .trunk_size = 4096,
 292                 .need_lock = 1,
 293                 .release_mem_en = 1,
 294                 .malloc = rte_malloc_socket,
 295                 .free = rte_free,
 296                 .type = "rte_flow_ipool",
 297         },
 298 };
 299
 300
 301 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 302 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 303
 304 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 305
 306 /**
 307  * Allocate ID pool structure.
 308  *
 309  * @param[in] max_id
 310  *   The maximum id can be allocated from the pool.
 311  *
 312  * @return
 313  *   Pointer to pool object, NULL value otherwise.
 314  */
 315 struct mlx5_flow_id_pool *
 316 mlx5_flow_id_pool_alloc(uint32_t max_id)
 317 {
 318         struct mlx5_flow_id_pool *pool;
 319         void *mem;
 320
 321         pool = rte_zmalloc("id pool allocation", sizeof(*pool),
 322                            RTE_CACHE_LINE_SIZE);
 323         if (!pool) {
 324                 DRV_LOG(ERR, "can't allocate id pool");
 325                 rte_errno  = ENOMEM;
 326                 return NULL;
 327         }
 328         mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
 329                           RTE_CACHE_LINE_SIZE);
 330         if (!mem) {
 331                 DRV_LOG(ERR, "can't allocate mem for id pool");
 332                 rte_errno  = ENOMEM;
 333                 goto error;
 334         }
 335         pool->free_arr = mem;
 336         pool->curr = pool->free_arr;
 337         pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
 338         pool->base_index = 0;
 339         pool->max_id = max_id;
 340         return pool;
 341 error:
 342         rte_free(pool);
 343         return NULL;
 344 }
 345
 346 /**
 347  * Release ID pool structure.
 348  *
 349  * @param[in] pool
 350  *   Pointer to flow id pool object to free.
 351  */
 352 void
 353 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
 354 {
 355         rte_free(pool->free_arr);
 356         rte_free(pool);
 357 }
 358
 359 /**
 360  * Generate ID.
 361  *
 362  * @param[in] pool
 363  *   Pointer to flow id pool.
 364  * @param[out] id
 365  *   The generated ID.
 366  *
 367  * @return
 368  *   0 on success, error value otherwise.
 369  */
 370 uint32_t
 371 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
 372 {
 373         if (pool->curr == pool->free_arr) {
 374                 if (pool->base_index == pool->max_id) {
 375                         rte_errno  = ENOMEM;
 376                         DRV_LOG(ERR, "no free id");
 377                         return -rte_errno;
 378                 }
 379                 *id = ++pool->base_index;
 380                 return 0;
 381         }
 382         *id = *(--pool->curr);
 383         return 0;
 384 }
 385
 386 /**
 387  * Release ID.
 388  *
 389  * @param[in] pool
 390  *   Pointer to flow id pool.
 391  * @param[out] id
 392  *   The generated ID.
 393  *
 394  * @return
 395  *   0 on success, error value otherwise.
 396  */
 397 uint32_t
 398 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
 399 {
 400         uint32_t size;
 401         uint32_t size2;
 402         void *mem;
 403
 404         if (pool->curr == pool->last) {
 405                 size = pool->curr - pool->free_arr;
 406                 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
 407                 MLX5_ASSERT(size2 > size);
 408                 mem = rte_malloc("", size2 * sizeof(uint32_t), 0);
 409                 if (!mem) {
 410                         DRV_LOG(ERR, "can't allocate mem for id pool");
 411                         rte_errno  = ENOMEM;
 412                         return -rte_errno;
 413                 }
 414                 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
 415                 rte_free(pool->free_arr);
 416                 pool->free_arr = mem;
 417                 pool->curr = pool->free_arr + size;
 418                 pool->last = pool->free_arr + size2;
 419         }
 420         *pool->curr = id;
 421         pool->curr++;
 422         return 0;
 423 }
 424
 425 /**
 426  * Initialize the shared aging list information per port.
 427  *
 428  * @param[in] sh
 429  *   Pointer to mlx5_dev_ctx_shared object.
 430  */
 431 static void
 432 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 433 {
 434         uint32_t i;
 435         struct mlx5_age_info *age_info;
 436
 437         for (i = 0; i < sh->max_port; i++) {
 438                 age_info = &sh->port[i].age_info;
 439                 age_info->flags = 0;
 440                 TAILQ_INIT(&age_info->aged_counters);
 441                 rte_spinlock_init(&age_info->aged_sl);
 442                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 443         }
 444 }
 445
 446 /**
 447  * Initialize the counters management structure.
 448  *
 449  * @param[in] sh
 450  *   Pointer to mlx5_dev_ctx_shared object to free
 451  */
 452 static void
 453 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 454 {
 455         int i;
 456
 457         memset(&sh->cmng, 0, sizeof(sh->cmng));
 458         TAILQ_INIT(&sh->cmng.flow_counters);
 459         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 460                 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
 461                 rte_spinlock_init(&sh->cmng.ccont[i].resize_sl);
 462         }
 463 }
 464
 465 /**
 466  * Destroy all the resources allocated for a counter memory management.
 467  *
 468  * @param[in] mng
 469  *   Pointer to the memory management structure.
 470  */
 471 static void
 472 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 473 {
 474         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 475
 476         LIST_REMOVE(mng, next);
 477         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 478         claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
 479         rte_free(mem);
 480 }
 481
 482 /**
 483  * Close and release all the resources of the counters management.
 484  *
 485  * @param[in] sh
 486  *   Pointer to mlx5_dev_ctx_shared object to free.
 487  */
 488 static void
 489 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 490 {
 491         struct mlx5_counter_stats_mem_mng *mng;
 492         int i;
 493         int j;
 494         int retries = 1024;
 495
 496         rte_errno = 0;
 497         while (--retries) {
 498                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 499                 if (rte_errno != EINPROGRESS)
 500                         break;
 501                 rte_pause();
 502         }
 503         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 504                 struct mlx5_flow_counter_pool *pool;
 505                 uint32_t batch = !!(i > 1);
 506
 507                 if (!sh->cmng.ccont[i].pools)
 508                         continue;
 509                 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 510                 while (pool) {
 511                         if (batch && pool->min_dcs)
 512                                 claim_zero(mlx5_devx_cmd_destroy
 513                                                                (pool->min_dcs));
 514                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 515                                 if (MLX5_POOL_GET_CNT(pool, j)->action)
 516                                         claim_zero
 517                                          (mlx5_glue->destroy_flow_action
 518                                           (MLX5_POOL_GET_CNT
 519                                           (pool, j)->action));
 520                                 if (!batch && MLX5_GET_POOL_CNT_EXT
 521                                     (pool, j)->dcs)
 522                                         claim_zero(mlx5_devx_cmd_destroy
 523                                                    (MLX5_GET_POOL_CNT_EXT
 524                                                     (pool, j)->dcs));
 525                         }
 526                         TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, next);
 527                         rte_free(pool);
 528                         pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 529                 }
 530                 rte_free(sh->cmng.ccont[i].pools);
 531         }
 532         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 533         while (mng) {
 534                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 535                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 536         }
 537         memset(&sh->cmng, 0, sizeof(sh->cmng));
 538 }
 539
 540 /**
 541  * Initialize the flow resources' indexed mempool.
 542  *
 543  * @param[in] sh
 544  *   Pointer to mlx5_dev_ctx_shared object.
 545  * @param[in] sh
 546  *   Pointer to user dev config.
 547  */
 548 static void
 549 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 550                        const struct mlx5_dev_config *config)
 551 {
 552         uint8_t i;
 553         struct mlx5_indexed_pool_config cfg;
 554
 555         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 556                 cfg = mlx5_ipool_cfg[i];
 557                 switch (i) {
 558                 default:
 559                         break;
 560                 /*
 561                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 562                  * according to PCI function flow configuration.
 563                  */
 564                 case MLX5_IPOOL_MLX5_FLOW:
 565                         cfg.size = config->dv_flow_en ?
 566                                 sizeof(struct mlx5_flow_handle) :
 567                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 568                         break;
 569                 }
 570                 if (config->reclaim_mode)
 571                         cfg.release_mem_en = 1;
 572                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 573         }
 574 }
 575
 576 /**
 577  * Release the flow resources' indexed mempool.
 578  *
 579  * @param[in] sh
 580  *   Pointer to mlx5_dev_ctx_shared object.
 581  */
 582 static void
 583 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 584 {
 585         uint8_t i;
 586
 587         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 588                 mlx5_ipool_destroy(sh->ipool[i]);
 589 }
 590
 591 /**
 592  * Allocate shared device context. If there is multiport device the
 593  * master and representors will share this context, if there is single
 594  * port dedicated device, the context will be used by only given
 595  * port due to unification.
 596  *
 597  * Routine first searches the context for the specified device name,
 598  * if found the shared context assumed and reference counter is incremented.
 599  * If no context found the new one is created and initialized with specified
 600  * device context and parameters.
 601  *
 602  * @param[in] spawn
 603  *   Pointer to the device attributes (name, port, etc).
 604  * @param[in] config
 605  *   Pointer to device configuration structure.
 606  *
 607  * @return
 608  *   Pointer to mlx5_dev_ctx_shared object on success,
 609  *   otherwise NULL and rte_errno is set.
 610  */
 611 struct mlx5_dev_ctx_shared *
 612 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
 613                            const struct mlx5_dev_config *config)
 614 {
 615         struct mlx5_dev_ctx_shared *sh;
 616         int err = 0;
 617         uint32_t i;
 618         struct mlx5_devx_tis_attr tis_attr = { 0 };
 619
 620         MLX5_ASSERT(spawn);
 621         /* Secondary process should not create the shared context. */
 622         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 623         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 624         /* Search for IB context by device name. */
 625         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
 626                 if (!strcmp(sh->ibdev_name,
 627                         mlx5_os_get_dev_device_name(spawn->phys_dev))) {
 628                         sh->refcnt++;
 629                         goto exit;
 630                 }
 631         }
 632         /* No device found, we have to create new shared context. */
 633         MLX5_ASSERT(spawn->max_port);
 634         sh = rte_zmalloc("ethdev shared ib context",
 635                          sizeof(struct mlx5_dev_ctx_shared) +
 636                          spawn->max_port *
 637                          sizeof(struct mlx5_dev_shared_port),
 638                          RTE_CACHE_LINE_SIZE);
 639         if (!sh) {
 640                 DRV_LOG(ERR, "shared context allocation failure");
 641                 rte_errno  = ENOMEM;
 642                 goto exit;
 643         }
 644         err = mlx5_os_open_device(spawn, config, sh);
 645         if (!sh->ctx)
 646                 goto error;
 647         err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
 648         if (err) {
 649                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
 650                 goto error;
 651         }
 652         sh->refcnt = 1;
 653         sh->max_port = spawn->max_port;
 654         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
 655                 sizeof(sh->ibdev_name) - 1);
 656         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
 657                 sizeof(sh->ibdev_path) - 1);
 658         /*
 659          * Setting port_id to max unallowed value means
 660          * there is no interrupt subhandler installed for
 661          * the given port index i.
 662          */
 663         for (i = 0; i < sh->max_port; i++) {
 664                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 665                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
 666         }
 667         sh->pd = mlx5_glue->alloc_pd(sh->ctx);
 668         if (sh->pd == NULL) {
 669                 DRV_LOG(ERR, "PD allocation failure");
 670                 err = ENOMEM;
 671                 goto error;
 672         }
 673         if (sh->devx) {
 674                 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
 675                 if (err) {
 676                         DRV_LOG(ERR, "Fail to extract pdn from PD");
 677                         goto error;
 678                 }
 679                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
 680                 if (!sh->td) {
 681                         DRV_LOG(ERR, "TD allocation failure");
 682                         err = ENOMEM;
 683                         goto error;
 684                 }
 685                 tis_attr.transport_domain = sh->td->id;
 686                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
 687                 if (!sh->tis) {
 688                         DRV_LOG(ERR, "TIS allocation failure");
 689                         err = ENOMEM;
 690                         goto error;
 691                 }
 692         }
 693         sh->flow_id_pool = mlx5_flow_id_pool_alloc
 694                                         ((1 << HAIRPIN_FLOW_ID_BITS) - 1);
 695         if (!sh->flow_id_pool) {
 696                 DRV_LOG(ERR, "can't create flow id pool");
 697                 err = ENOMEM;
 698                 goto error;
 699         }
 700         /*
 701          * Once the device is added to the list of memory event
 702          * callback, its global MR cache table cannot be expanded
 703          * on the fly because of deadlock. If it overflows, lookup
 704          * should be done by searching MR list linearly, which is slow.
 705          *
 706          * At this point the device is not added to the memory
 707          * event list yet, context is just being created.
 708          */
 709         err = mlx5_mr_btree_init(&sh->share_cache.cache,
 710                                  MLX5_MR_BTREE_CACHE_N * 2,
 711                                  spawn->pci_dev->device.numa_node);
 712         if (err) {
 713                 err = rte_errno;
 714                 goto error;
 715         }
 716         mlx5_os_dev_shared_handler_install(sh);
 717         mlx5_flow_aging_init(sh);
 718         mlx5_flow_counters_mng_init(sh);
 719         mlx5_flow_ipool_create(sh, config);
 720         /* Add device to memory callback list. */
 721         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 722         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
 723                          sh, mem_event_cb);
 724         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 725         /* Add context to the global device list. */
 726         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
 727 exit:
 728         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 729         return sh;
 730 error:
 731         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 732         MLX5_ASSERT(sh);
 733         if (sh->tis)
 734                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 735         if (sh->td)
 736                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 737         if (sh->pd)
 738                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 739         if (sh->ctx)
 740                 claim_zero(mlx5_glue->close_device(sh->ctx));
 741         if (sh->flow_id_pool)
 742                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 743         rte_free(sh);
 744         MLX5_ASSERT(err > 0);
 745         rte_errno = err;
 746         return NULL;
 747 }
 748
 749 /**
 750  * Free shared IB device context. Decrement counter and if zero free
 751  * all allocated resources and close handles.
 752  *
 753  * @param[in] sh
 754  *   Pointer to mlx5_dev_ctx_shared object to free
 755  */
 756 void
 757 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
 758 {
 759         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 760 #ifdef RTE_LIBRTE_MLX5_DEBUG
 761         /* Check the object presence in the list. */
 762         struct mlx5_dev_ctx_shared *lctx;
 763
 764         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
 765                 if (lctx == sh)
 766                         break;
 767         MLX5_ASSERT(lctx);
 768         if (lctx != sh) {
 769                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
 770                 goto exit;
 771         }
 772 #endif
 773         MLX5_ASSERT(sh);
 774         MLX5_ASSERT(sh->refcnt);
 775         /* Secondary process should not free the shared context. */
 776         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 777         if (--sh->refcnt)
 778                 goto exit;
 779         /* Remove from memory callback device list. */
 780         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 781         LIST_REMOVE(sh, mem_event_cb);
 782         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 783         /* Release created Memory Regions. */
 784         mlx5_mr_release_cache(&sh->share_cache);
 785         /* Remove context from the global device list. */
 786         LIST_REMOVE(sh, next);
 787         /*
 788          *  Ensure there is no async event handler installed.
 789          *  Only primary process handles async device events.
 790          **/
 791         mlx5_flow_counters_mng_close(sh);
 792         mlx5_flow_ipool_destroy(sh);
 793         mlx5_os_dev_shared_handler_uninstall(sh);
 794         if (sh->pd)
 795                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 796         if (sh->tis)
 797                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 798         if (sh->td)
 799                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 800         if (sh->ctx)
 801                 claim_zero(mlx5_glue->close_device(sh->ctx));
 802         if (sh->flow_id_pool)
 803                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 804         rte_free(sh);
 805 exit:
 806         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 807 }
 808
 809 /**
 810  * Destroy table hash list and all the root entries per domain.
 811  *
 812  * @param[in] priv
 813  *   Pointer to the private device data structure.
 814  */
 815 void
 816 mlx5_free_table_hash_list(struct mlx5_priv *priv)
 817 {
 818         struct mlx5_dev_ctx_shared *sh = priv->sh;
 819         struct mlx5_flow_tbl_data_entry *tbl_data;
 820         union mlx5_flow_tbl_key table_key = {
 821                 {
 822                         .table_id = 0,
 823                         .reserved = 0,
 824                         .domain = 0,
 825                         .direction = 0,
 826                 }
 827         };
 828         struct mlx5_hlist_entry *pos;
 829
 830         if (!sh->flow_tbls)
 831                 return;
 832         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 833         if (pos) {
 834                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 835                                         entry);
 836                 MLX5_ASSERT(tbl_data);
 837                 mlx5_hlist_remove(sh->flow_tbls, pos);
 838                 rte_free(tbl_data);
 839         }
 840         table_key.direction = 1;
 841         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 842         if (pos) {
 843                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 844                                         entry);
 845                 MLX5_ASSERT(tbl_data);
 846                 mlx5_hlist_remove(sh->flow_tbls, pos);
 847                 rte_free(tbl_data);
 848         }
 849         table_key.direction = 0;
 850         table_key.domain = 1;
 851         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 852         if (pos) {
 853                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 854                                         entry);
 855                 MLX5_ASSERT(tbl_data);
 856                 mlx5_hlist_remove(sh->flow_tbls, pos);
 857                 rte_free(tbl_data);
 858         }
 859         mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
 860 }
 861
 862 /**
 863  * Initialize flow table hash list and create the root tables entry
 864  * for each domain.
 865  *
 866  * @param[in] priv
 867  *   Pointer to the private device data structure.
 868  *
 869  * @return
 870  *   Zero on success, positive error code otherwise.
 871  */
 872 int
 873 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
 874 {
 875         struct mlx5_dev_ctx_shared *sh = priv->sh;
 876         char s[MLX5_HLIST_NAMESIZE];
 877         int err = 0;
 878
 879         MLX5_ASSERT(sh);
 880         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
 881         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
 882         if (!sh->flow_tbls) {
 883                 DRV_LOG(ERR, "flow tables with hash creation failed.\n");
 884                 err = ENOMEM;
 885                 return err;
 886         }
 887 #ifndef HAVE_MLX5DV_DR
 888         /*
 889          * In case we have not DR support, the zero tables should be created
 890          * because DV expect to see them even if they cannot be created by
 891          * RDMA-CORE.
 892          */
 893         union mlx5_flow_tbl_key table_key = {
 894                 {
 895                         .table_id = 0,
 896                         .reserved = 0,
 897                         .domain = 0,
 898                         .direction = 0,
 899                 }
 900         };
 901         struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL,
 902                                                           sizeof(*tbl_data), 0);
 903
 904         if (!tbl_data) {
 905                 err = ENOMEM;
 906                 goto error;
 907         }
 908         tbl_data->entry.key = table_key.v64;
 909         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 910         if (err)
 911                 goto error;
 912         rte_atomic32_init(&tbl_data->tbl.refcnt);
 913         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 914         table_key.direction = 1;
 915         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 916         if (!tbl_data) {
 917                 err = ENOMEM;
 918                 goto error;
 919         }
 920         tbl_data->entry.key = table_key.v64;
 921         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 922         if (err)
 923                 goto error;
 924         rte_atomic32_init(&tbl_data->tbl.refcnt);
 925         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 926         table_key.direction = 0;
 927         table_key.domain = 1;
 928         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 929         if (!tbl_data) {
 930                 err = ENOMEM;
 931                 goto error;
 932         }
 933         tbl_data->entry.key = table_key.v64;
 934         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 935         if (err)
 936                 goto error;
 937         rte_atomic32_init(&tbl_data->tbl.refcnt);
 938         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 939         return err;
 940 error:
 941         mlx5_free_table_hash_list(priv);
 942 #endif /* HAVE_MLX5DV_DR */
 943         return err;
 944 }
 945
 946 /**
 947  * Initialize shared data between primary and secondary process.
 948  *
 949  * A memzone is reserved by primary process and secondary processes attach to
 950  * the memzone.
 951  *
 952  * @return
 953  *   0 on success, a negative errno value otherwise and rte_errno is set.
 954  */
 955 static int
 956 mlx5_init_shared_data(void)
 957 {
 958         const struct rte_memzone *mz;
 959         int ret = 0;
 960
 961         rte_spinlock_lock(&mlx5_shared_data_lock);
 962         if (mlx5_shared_data == NULL) {
 963                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
 964                         /* Allocate shared memory. */
 965                         mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
 966                                                  sizeof(*mlx5_shared_data),
 967                                                  SOCKET_ID_ANY, 0);
 968                         if (mz == NULL) {
 969                                 DRV_LOG(ERR,
 970                                         "Cannot allocate mlx5 shared data");
 971                                 ret = -rte_errno;
 972                                 goto error;
 973                         }
 974                         mlx5_shared_data = mz->addr;
 975                         memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
 976                         rte_spinlock_init(&mlx5_shared_data->lock);
 977                 } else {
 978                         /* Lookup allocated shared memory. */
 979                         mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
 980                         if (mz == NULL) {
 981                                 DRV_LOG(ERR,
 982                                         "Cannot attach mlx5 shared data");
 983                                 ret = -rte_errno;
 984                                 goto error;
 985                         }
 986                         mlx5_shared_data = mz->addr;
 987                         memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
 988                 }
 989         }
 990 error:
 991         rte_spinlock_unlock(&mlx5_shared_data_lock);
 992         return ret;
 993 }
 994
 995 /**
 996  * Retrieve integer value from environment variable.
 997  *
 998  * @param[in] name
 999  *   Environment variable name.
1000  *
1001  * @return
1002  *   Integer value, 0 if the variable is not set.
1003  */
1004 int
1005 mlx5_getenv_int(const char *name)
1006 {
1007         const char *val = getenv(name);
1008
1009         if (val == NULL)
1010                 return 0;
1011         return atoi(val);
1012 }
1013
1014 /**
1015  * DPDK callback to add udp tunnel port
1016  *
1017  * @param[in] dev
1018  *   A pointer to eth_dev
1019  * @param[in] udp_tunnel
1020  *   A pointer to udp tunnel
1021  *
1022  * @return
1023  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1024  */
1025 int
1026 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1027                          struct rte_eth_udp_tunnel *udp_tunnel)
1028 {
1029         MLX5_ASSERT(udp_tunnel != NULL);
1030         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1031             udp_tunnel->udp_port == 4789)
1032                 return 0;
1033         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1034             udp_tunnel->udp_port == 4790)
1035                 return 0;
1036         return -ENOTSUP;
1037 }
1038
1039 /**
1040  * Initialize process private data structure.
1041  *
1042  * @param dev
1043  *   Pointer to Ethernet device structure.
1044  *
1045  * @return
1046  *   0 on success, a negative errno value otherwise and rte_errno is set.
1047  */
1048 int
1049 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1050 {
1051         struct mlx5_priv *priv = dev->data->dev_private;
1052         struct mlx5_proc_priv *ppriv;
1053         size_t ppriv_size;
1054
1055         /*
1056          * UAR register table follows the process private structure. BlueFlame
1057          * registers for Tx queues are stored in the table.
1058          */
1059         ppriv_size =
1060                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1061         ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
1062                                   RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1063         if (!ppriv) {
1064                 rte_errno = ENOMEM;
1065                 return -rte_errno;
1066         }
1067         ppriv->uar_table_sz = ppriv_size;
1068         dev->process_private = ppriv;
1069         return 0;
1070 }
1071
1072 /**
1073  * Un-initialize process private data structure.
1074  *
1075  * @param dev
1076  *   Pointer to Ethernet device structure.
1077  */
1078 static void
1079 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1080 {
1081         if (!dev->process_private)
1082                 return;
1083         rte_free(dev->process_private);
1084         dev->process_private = NULL;
1085 }
1086
1087 /**
1088  * DPDK callback to close the device.
1089  *
1090  * Destroy all queues and objects, free memory.
1091  *
1092  * @param dev
1093  *   Pointer to Ethernet device structure.
1094  */
1095 void
1096 mlx5_dev_close(struct rte_eth_dev *dev)
1097 {
1098         struct mlx5_priv *priv = dev->data->dev_private;
1099         unsigned int i;
1100         int ret;
1101
1102         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1103                 /* Check if process_private released. */
1104                 if (!dev->process_private)
1105                         return;
1106                 mlx5_tx_uar_uninit_secondary(dev);
1107                 mlx5_proc_priv_uninit(dev);
1108                 rte_eth_dev_release_port(dev);
1109                 return;
1110         }
1111         if (!priv->sh)
1112                 return;
1113         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1114                 dev->data->port_id,
1115                 ((priv->sh->ctx != NULL) ?
1116                 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1117         /*
1118          * If default mreg copy action is removed at the stop stage,
1119          * the search will return none and nothing will be done anymore.
1120          */
1121         mlx5_flow_stop_default(dev);
1122         mlx5_traffic_disable(dev);
1123         /*
1124          * If all the flows are already flushed in the device stop stage,
1125          * then this will return directly without any action.
1126          */
1127         mlx5_flow_list_flush(dev, &priv->flows, true);
1128         mlx5_flow_meter_flush(dev, NULL);
1129         /* Free the intermediate buffers for flow creation. */
1130         mlx5_flow_free_intermediate(dev);
1131         /* Prevent crashes when queues are still in use. */
1132         dev->rx_pkt_burst = removed_rx_burst;
1133         dev->tx_pkt_burst = removed_tx_burst;
1134         rte_wmb();
1135         /* Disable datapath on secondary process. */
1136         mlx5_mp_req_stop_rxtx(dev);
1137         if (priv->rxqs != NULL) {
1138                 /* XXX race condition if mlx5_rx_burst() is still running. */
1139                 usleep(1000);
1140                 for (i = 0; (i != priv->rxqs_n); ++i)
1141                         mlx5_rxq_release(dev, i);
1142                 priv->rxqs_n = 0;
1143                 priv->rxqs = NULL;
1144         }
1145         if (priv->txqs != NULL) {
1146                 /* XXX race condition if mlx5_tx_burst() is still running. */
1147                 usleep(1000);
1148                 for (i = 0; (i != priv->txqs_n); ++i)
1149                         mlx5_txq_release(dev, i);
1150                 priv->txqs_n = 0;
1151                 priv->txqs = NULL;
1152         }
1153         mlx5_proc_priv_uninit(dev);
1154         if (priv->mreg_cp_tbl)
1155                 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1156         mlx5_mprq_free_mp(dev);
1157         mlx5_os_free_shared_dr(priv);
1158         if (priv->rss_conf.rss_key != NULL)
1159                 rte_free(priv->rss_conf.rss_key);
1160         if (priv->reta_idx != NULL)
1161                 rte_free(priv->reta_idx);
1162         if (priv->config.vf)
1163                 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1164                                        dev->data->mac_addrs,
1165                                        MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1166         if (priv->nl_socket_route >= 0)
1167                 close(priv->nl_socket_route);
1168         if (priv->nl_socket_rdma >= 0)
1169                 close(priv->nl_socket_rdma);
1170         if (priv->vmwa_context)
1171                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1172         ret = mlx5_hrxq_verify(dev);
1173         if (ret)
1174                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1175                         dev->data->port_id);
1176         ret = mlx5_ind_table_obj_verify(dev);
1177         if (ret)
1178                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1179                         dev->data->port_id);
1180         ret = mlx5_rxq_obj_verify(dev);
1181         if (ret)
1182                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1183                         dev->data->port_id);
1184         ret = mlx5_rxq_verify(dev);
1185         if (ret)
1186                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1187                         dev->data->port_id);
1188         ret = mlx5_txq_obj_verify(dev);
1189         if (ret)
1190                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1191                         dev->data->port_id);
1192         ret = mlx5_txq_verify(dev);
1193         if (ret)
1194                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1195                         dev->data->port_id);
1196         ret = mlx5_flow_verify(dev);
1197         if (ret)
1198                 DRV_LOG(WARNING, "port %u some flows still remain",
1199                         dev->data->port_id);
1200         /*
1201          * Free the shared context in last turn, because the cleanup
1202          * routines above may use some shared fields, like
1203          * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1204          * ifindex if Netlink fails.
1205          */
1206         mlx5_free_shared_dev_ctx(priv->sh);
1207         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1208                 unsigned int c = 0;
1209                 uint16_t port_id;
1210
1211                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1212                         struct mlx5_priv *opriv =
1213                                 rte_eth_devices[port_id].data->dev_private;
1214
1215                         if (!opriv ||
1216                             opriv->domain_id != priv->domain_id ||
1217                             &rte_eth_devices[port_id] == dev)
1218                                 continue;
1219                         ++c;
1220                         break;
1221                 }
1222                 if (!c)
1223                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1224         }
1225         memset(priv, 0, sizeof(*priv));
1226         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1227         /*
1228          * Reset mac_addrs to NULL such that it is not freed as part of
1229          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1230          * it is freed when dev_private is freed.
1231          */
1232         dev->data->mac_addrs = NULL;
1233 }
1234
1235 const struct eth_dev_ops mlx5_dev_ops = {
1236         .dev_configure = mlx5_dev_configure,
1237         .dev_start = mlx5_dev_start,
1238         .dev_stop = mlx5_dev_stop,
1239         .dev_set_link_down = mlx5_set_link_down,
1240         .dev_set_link_up = mlx5_set_link_up,
1241         .dev_close = mlx5_dev_close,
1242         .promiscuous_enable = mlx5_promiscuous_enable,
1243         .promiscuous_disable = mlx5_promiscuous_disable,
1244         .allmulticast_enable = mlx5_allmulticast_enable,
1245         .allmulticast_disable = mlx5_allmulticast_disable,
1246         .link_update = mlx5_link_update,
1247         .stats_get = mlx5_stats_get,
1248         .stats_reset = mlx5_stats_reset,
1249         .xstats_get = mlx5_xstats_get,
1250         .xstats_reset = mlx5_xstats_reset,
1251         .xstats_get_names = mlx5_xstats_get_names,
1252         .fw_version_get = mlx5_fw_version_get,
1253         .dev_infos_get = mlx5_dev_infos_get,
1254         .read_clock = mlx5_read_clock,
1255         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1256         .vlan_filter_set = mlx5_vlan_filter_set,
1257         .rx_queue_setup = mlx5_rx_queue_setup,
1258         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1259         .tx_queue_setup = mlx5_tx_queue_setup,
1260         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1261         .rx_queue_release = mlx5_rx_queue_release,
1262         .tx_queue_release = mlx5_tx_queue_release,
1263         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1264         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1265         .mac_addr_remove = mlx5_mac_addr_remove,
1266         .mac_addr_add = mlx5_mac_addr_add,
1267         .mac_addr_set = mlx5_mac_addr_set,
1268         .set_mc_addr_list = mlx5_set_mc_addr_list,
1269         .mtu_set = mlx5_dev_set_mtu,
1270         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1271         .vlan_offload_set = mlx5_vlan_offload_set,
1272         .reta_update = mlx5_dev_rss_reta_update,
1273         .reta_query = mlx5_dev_rss_reta_query,
1274         .rss_hash_update = mlx5_rss_hash_update,
1275         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1276         .filter_ctrl = mlx5_dev_filter_ctrl,
1277         .rx_descriptor_status = mlx5_rx_descriptor_status,
1278         .tx_descriptor_status = mlx5_tx_descriptor_status,
1279         .rxq_info_get = mlx5_rxq_info_get,
1280         .txq_info_get = mlx5_txq_info_get,
1281         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1282         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1283         .rx_queue_count = mlx5_rx_queue_count,
1284         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1285         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1286         .is_removed = mlx5_is_removed,
1287         .udp_tunnel_port_add  = mlx5_udp_tunnel_port_add,
1288         .get_module_info = mlx5_get_module_info,
1289         .get_module_eeprom = mlx5_get_module_eeprom,
1290         .hairpin_cap_get = mlx5_hairpin_cap_get,
1291         .mtr_ops_get = mlx5_flow_meter_ops_get,
1292 };
1293
1294 /* Available operations from secondary process. */
1295 const struct eth_dev_ops mlx5_dev_sec_ops = {
1296         .stats_get = mlx5_stats_get,
1297         .stats_reset = mlx5_stats_reset,
1298         .xstats_get = mlx5_xstats_get,
1299         .xstats_reset = mlx5_xstats_reset,
1300         .xstats_get_names = mlx5_xstats_get_names,
1301         .fw_version_get = mlx5_fw_version_get,
1302         .dev_infos_get = mlx5_dev_infos_get,
1303         .rx_descriptor_status = mlx5_rx_descriptor_status,
1304         .tx_descriptor_status = mlx5_tx_descriptor_status,
1305         .rxq_info_get = mlx5_rxq_info_get,
1306         .txq_info_get = mlx5_txq_info_get,
1307         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1308         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1309         .get_module_info = mlx5_get_module_info,
1310         .get_module_eeprom = mlx5_get_module_eeprom,
1311 };
1312
1313 /* Available operations in flow isolated mode. */
1314 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1315         .dev_configure = mlx5_dev_configure,
1316         .dev_start = mlx5_dev_start,
1317         .dev_stop = mlx5_dev_stop,
1318         .dev_set_link_down = mlx5_set_link_down,
1319         .dev_set_link_up = mlx5_set_link_up,
1320         .dev_close = mlx5_dev_close,
1321         .promiscuous_enable = mlx5_promiscuous_enable,
1322         .promiscuous_disable = mlx5_promiscuous_disable,
1323         .allmulticast_enable = mlx5_allmulticast_enable,
1324         .allmulticast_disable = mlx5_allmulticast_disable,
1325         .link_update = mlx5_link_update,
1326         .stats_get = mlx5_stats_get,
1327         .stats_reset = mlx5_stats_reset,
1328         .xstats_get = mlx5_xstats_get,
1329         .xstats_reset = mlx5_xstats_reset,
1330         .xstats_get_names = mlx5_xstats_get_names,
1331         .fw_version_get = mlx5_fw_version_get,
1332         .dev_infos_get = mlx5_dev_infos_get,
1333         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1334         .vlan_filter_set = mlx5_vlan_filter_set,
1335         .rx_queue_setup = mlx5_rx_queue_setup,
1336         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1337         .tx_queue_setup = mlx5_tx_queue_setup,
1338         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1339         .rx_queue_release = mlx5_rx_queue_release,
1340         .tx_queue_release = mlx5_tx_queue_release,
1341         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1342         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1343         .mac_addr_remove = mlx5_mac_addr_remove,
1344         .mac_addr_add = mlx5_mac_addr_add,
1345         .mac_addr_set = mlx5_mac_addr_set,
1346         .set_mc_addr_list = mlx5_set_mc_addr_list,
1347         .mtu_set = mlx5_dev_set_mtu,
1348         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1349         .vlan_offload_set = mlx5_vlan_offload_set,
1350         .filter_ctrl = mlx5_dev_filter_ctrl,
1351         .rx_descriptor_status = mlx5_rx_descriptor_status,
1352         .tx_descriptor_status = mlx5_tx_descriptor_status,
1353         .rxq_info_get = mlx5_rxq_info_get,
1354         .txq_info_get = mlx5_txq_info_get,
1355         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1356         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1357         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1358         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1359         .is_removed = mlx5_is_removed,
1360         .get_module_info = mlx5_get_module_info,
1361         .get_module_eeprom = mlx5_get_module_eeprom,
1362         .hairpin_cap_get = mlx5_hairpin_cap_get,
1363         .mtr_ops_get = mlx5_flow_meter_ops_get,
1364 };
1365
1366 /**
1367  * Verify and store value for device argument.
1368  *
1369  * @param[in] key
1370  *   Key argument to verify.
1371  * @param[in] val
1372  *   Value associated with key.
1373  * @param opaque
1374  *   User data.
1375  *
1376  * @return
1377  *   0 on success, a negative errno value otherwise and rte_errno is set.
1378  */
1379 static int
1380 mlx5_args_check(const char *key, const char *val, void *opaque)
1381 {
1382         struct mlx5_dev_config *config = opaque;
1383         unsigned long tmp;
1384
1385         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1386         if (!strcmp(MLX5_REPRESENTOR, key))
1387                 return 0;
1388         errno = 0;
1389         tmp = strtoul(val, NULL, 0);
1390         if (errno) {
1391                 rte_errno = errno;
1392                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1393                 return -rte_errno;
1394         }
1395         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1396                 config->cqe_comp = !!tmp;
1397         } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1398                 config->cqe_pad = !!tmp;
1399         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1400                 config->hw_padding = !!tmp;
1401         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1402                 config->mprq.enabled = !!tmp;
1403         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1404                 config->mprq.stride_num_n = tmp;
1405         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1406                 config->mprq.stride_size_n = tmp;
1407         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1408                 config->mprq.max_memcpy_len = tmp;
1409         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1410                 config->mprq.min_rxqs_num = tmp;
1411         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1412                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1413                                  " converted to txq_inline_max", key);
1414                 config->txq_inline_max = tmp;
1415         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1416                 config->txq_inline_max = tmp;
1417         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1418                 config->txq_inline_min = tmp;
1419         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1420                 config->txq_inline_mpw = tmp;
1421         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1422                 config->txqs_inline = tmp;
1423         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1424                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1425         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1426                 config->mps = !!tmp;
1427         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1428                 if (tmp != MLX5_TXDB_CACHED &&
1429                     tmp != MLX5_TXDB_NCACHED &&
1430                     tmp != MLX5_TXDB_HEURISTIC) {
1431                         DRV_LOG(ERR, "invalid Tx doorbell "
1432                                      "mapping parameter");
1433                         rte_errno = EINVAL;
1434                         return -rte_errno;
1435                 }
1436                 config->dbnc = tmp;
1437         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1438                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1439         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1440                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1441                                  " converted to txq_inline_mpw", key);
1442                 config->txq_inline_mpw = tmp;
1443         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1444                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1445         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1446                 config->rx_vec_en = !!tmp;
1447         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1448                 config->l3_vxlan_en = !!tmp;
1449         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1450                 config->vf_nl_en = !!tmp;
1451         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1452                 config->dv_esw_en = !!tmp;
1453         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1454                 config->dv_flow_en = !!tmp;
1455         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1456                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1457                     tmp != MLX5_XMETA_MODE_META16 &&
1458                     tmp != MLX5_XMETA_MODE_META32) {
1459                         DRV_LOG(ERR, "invalid extensive "
1460                                      "metadata parameter");
1461                         rte_errno = EINVAL;
1462                         return -rte_errno;
1463                 }
1464                 config->dv_xmeta_en = tmp;
1465         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1466                 config->mr_ext_memseg_en = !!tmp;
1467         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1468                 config->max_dump_files_num = tmp;
1469         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1470                 config->lro.timeout = tmp;
1471         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1472                 DRV_LOG(DEBUG, "class argument is %s.", val);
1473         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1474                 config->log_hp_size = tmp;
1475         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1476                 if (tmp != MLX5_RCM_NONE &&
1477                     tmp != MLX5_RCM_LIGHT &&
1478                     tmp != MLX5_RCM_AGGR) {
1479                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1480                         rte_errno = EINVAL;
1481                         return -rte_errno;
1482                 }
1483                 config->reclaim_mode = tmp;
1484         } else {
1485                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1486                 rte_errno = EINVAL;
1487                 return -rte_errno;
1488         }
1489         return 0;
1490 }
1491
1492 /**
1493  * Parse device parameters.
1494  *
1495  * @param config
1496  *   Pointer to device configuration structure.
1497  * @param devargs
1498  *   Device arguments structure.
1499  *
1500  * @return
1501  *   0 on success, a negative errno value otherwise and rte_errno is set.
1502  */
1503 int
1504 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1505 {
1506         const char **params = (const char *[]){
1507                 MLX5_RXQ_CQE_COMP_EN,
1508                 MLX5_RXQ_CQE_PAD_EN,
1509                 MLX5_RXQ_PKT_PAD_EN,
1510                 MLX5_RX_MPRQ_EN,
1511                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1512                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1513                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1514                 MLX5_RXQS_MIN_MPRQ,
1515                 MLX5_TXQ_INLINE,
1516                 MLX5_TXQ_INLINE_MIN,
1517                 MLX5_TXQ_INLINE_MAX,
1518                 MLX5_TXQ_INLINE_MPW,
1519                 MLX5_TXQS_MIN_INLINE,
1520                 MLX5_TXQS_MAX_VEC,
1521                 MLX5_TXQ_MPW_EN,
1522                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1523                 MLX5_TXQ_MAX_INLINE_LEN,
1524                 MLX5_TX_DB_NC,
1525                 MLX5_TX_VEC_EN,
1526                 MLX5_RX_VEC_EN,
1527                 MLX5_L3_VXLAN_EN,
1528                 MLX5_VF_NL_EN,
1529                 MLX5_DV_ESW_EN,
1530                 MLX5_DV_FLOW_EN,
1531                 MLX5_DV_XMETA_EN,
1532                 MLX5_MR_EXT_MEMSEG_EN,
1533                 MLX5_REPRESENTOR,
1534                 MLX5_MAX_DUMP_FILES_NUM,
1535                 MLX5_LRO_TIMEOUT_USEC,
1536                 MLX5_CLASS_ARG_NAME,
1537                 MLX5_HP_BUF_SIZE,
1538                 MLX5_RECLAIM_MEM,
1539                 NULL,
1540         };
1541         struct rte_kvargs *kvlist;
1542         int ret = 0;
1543         int i;
1544
1545         if (devargs == NULL)
1546                 return 0;
1547         /* Following UGLY cast is done to pass checkpatch. */
1548         kvlist = rte_kvargs_parse(devargs->args, params);
1549         if (kvlist == NULL) {
1550                 rte_errno = EINVAL;
1551                 return -rte_errno;
1552         }
1553         /* Process parameters. */
1554         for (i = 0; (params[i] != NULL); ++i) {
1555                 if (rte_kvargs_count(kvlist, params[i])) {
1556                         ret = rte_kvargs_process(kvlist, params[i],
1557                                                  mlx5_args_check, config);
1558                         if (ret) {
1559                                 rte_errno = EINVAL;
1560                                 rte_kvargs_free(kvlist);
1561                                 return -rte_errno;
1562                         }
1563                 }
1564         }
1565         rte_kvargs_free(kvlist);
1566         return 0;
1567 }
1568
1569 /**
1570  * PMD global initialization.
1571  *
1572  * Independent from individual device, this function initializes global
1573  * per-PMD data structures distinguishing primary and secondary processes.
1574  * Hence, each initialization is called once per a process.
1575  *
1576  * @return
1577  *   0 on success, a negative errno value otherwise and rte_errno is set.
1578  */
1579 int
1580 mlx5_init_once(void)
1581 {
1582         struct mlx5_shared_data *sd;
1583         struct mlx5_local_data *ld = &mlx5_local_data;
1584         int ret = 0;
1585
1586         if (mlx5_init_shared_data())
1587                 return -rte_errno;
1588         sd = mlx5_shared_data;
1589         MLX5_ASSERT(sd);
1590         rte_spinlock_lock(&sd->lock);
1591         switch (rte_eal_process_type()) {
1592         case RTE_PROC_PRIMARY:
1593                 if (sd->init_done)
1594                         break;
1595                 LIST_INIT(&sd->mem_event_cb_list);
1596                 rte_rwlock_init(&sd->mem_event_rwlock);
1597                 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1598                                                 mlx5_mr_mem_event_cb, NULL);
1599                 ret = mlx5_mp_init_primary(MLX5_MP_NAME,
1600                                            mlx5_mp_primary_handle);
1601                 if (ret)
1602                         goto out;
1603                 sd->init_done = true;
1604                 break;
1605         case RTE_PROC_SECONDARY:
1606                 if (ld->init_done)
1607                         break;
1608                 ret = mlx5_mp_init_secondary(MLX5_MP_NAME,
1609                                              mlx5_mp_secondary_handle);
1610                 if (ret)
1611                         goto out;
1612                 ++sd->secondary_cnt;
1613                 ld->init_done = true;
1614                 break;
1615         default:
1616                 break;
1617         }
1618 out:
1619         rte_spinlock_unlock(&sd->lock);
1620         return ret;
1621 }
1622
1623 /**
1624  * Configures the minimal amount of data to inline into WQE
1625  * while sending packets.
1626  *
1627  * - the txq_inline_min has the maximal priority, if this
1628  *   key is specified in devargs
1629  * - if DevX is enabled the inline mode is queried from the
1630  *   device (HCA attributes and NIC vport context if needed).
1631  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1632  *   and none (0 bytes) for other NICs
1633  *
1634  * @param spawn
1635  *   Verbs device parameters (name, port, switch_info) to spawn.
1636  * @param config
1637  *   Device configuration parameters.
1638  */
1639 void
1640 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1641                     struct mlx5_dev_config *config)
1642 {
1643         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1644                 /* Application defines size of inlined data explicitly. */
1645                 switch (spawn->pci_dev->id.device_id) {
1646                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1647                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1648                         if (config->txq_inline_min <
1649                                        (int)MLX5_INLINE_HSIZE_L2) {
1650                                 DRV_LOG(DEBUG,
1651                                         "txq_inline_mix aligned to minimal"
1652                                         " ConnectX-4 required value %d",
1653                                         (int)MLX5_INLINE_HSIZE_L2);
1654                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1655                         }
1656                         break;
1657                 }
1658                 goto exit;
1659         }
1660         if (config->hca_attr.eth_net_offloads) {
1661                 /* We have DevX enabled, inline mode queried successfully. */
1662                 switch (config->hca_attr.wqe_inline_mode) {
1663                 case MLX5_CAP_INLINE_MODE_L2:
1664                         /* outer L2 header must be inlined. */
1665                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1666                         goto exit;
1667                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1668                         /* No inline data are required by NIC. */
1669                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1670                         config->hw_vlan_insert =
1671                                 config->hca_attr.wqe_vlan_insert;
1672                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1673                         goto exit;
1674                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1675                         /* inline mode is defined by NIC vport context. */
1676                         if (!config->hca_attr.eth_virt)
1677                                 break;
1678                         switch (config->hca_attr.vport_inline_mode) {
1679                         case MLX5_INLINE_MODE_NONE:
1680                                 config->txq_inline_min =
1681                                         MLX5_INLINE_HSIZE_NONE;
1682                                 goto exit;
1683                         case MLX5_INLINE_MODE_L2:
1684                                 config->txq_inline_min =
1685                                         MLX5_INLINE_HSIZE_L2;
1686                                 goto exit;
1687                         case MLX5_INLINE_MODE_IP:
1688                                 config->txq_inline_min =
1689                                         MLX5_INLINE_HSIZE_L3;
1690                                 goto exit;
1691                         case MLX5_INLINE_MODE_TCP_UDP:
1692                                 config->txq_inline_min =
1693                                         MLX5_INLINE_HSIZE_L4;
1694                                 goto exit;
1695                         case MLX5_INLINE_MODE_INNER_L2:
1696                                 config->txq_inline_min =
1697                                         MLX5_INLINE_HSIZE_INNER_L2;
1698                                 goto exit;
1699                         case MLX5_INLINE_MODE_INNER_IP:
1700                                 config->txq_inline_min =
1701                                         MLX5_INLINE_HSIZE_INNER_L3;
1702                                 goto exit;
1703                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
1704                                 config->txq_inline_min =
1705                                         MLX5_INLINE_HSIZE_INNER_L4;
1706                                 goto exit;
1707                         }
1708                 }
1709         }
1710         /*
1711          * We get here if we are unable to deduce
1712          * inline data size with DevX. Try PCI ID
1713          * to determine old NICs.
1714          */
1715         switch (spawn->pci_dev->id.device_id) {
1716         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1717         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1718         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1719         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1720                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1721                 config->hw_vlan_insert = 0;
1722                 break;
1723         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1724         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1725         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1726         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1727                 /*
1728                  * These NICs support VLAN insertion from WQE and
1729                  * report the wqe_vlan_insert flag. But there is the bug
1730                  * and PFC control may be broken, so disable feature.
1731                  */
1732                 config->hw_vlan_insert = 0;
1733                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1734                 break;
1735         default:
1736                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1737                 break;
1738         }
1739 exit:
1740         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1741 }
1742
1743 /**
1744  * Configures the metadata mask fields in the shared context.
1745  *
1746  * @param [in] dev
1747  *   Pointer to Ethernet device.
1748  */
1749 void
1750 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1751 {
1752         struct mlx5_priv *priv = dev->data->dev_private;
1753         struct mlx5_dev_ctx_shared *sh = priv->sh;
1754         uint32_t meta, mark, reg_c0;
1755
1756         reg_c0 = ~priv->vport_meta_mask;
1757         switch (priv->config.dv_xmeta_en) {
1758         case MLX5_XMETA_MODE_LEGACY:
1759                 meta = UINT32_MAX;
1760                 mark = MLX5_FLOW_MARK_MASK;
1761                 break;
1762         case MLX5_XMETA_MODE_META16:
1763                 meta = reg_c0 >> rte_bsf32(reg_c0);
1764                 mark = MLX5_FLOW_MARK_MASK;
1765                 break;
1766         case MLX5_XMETA_MODE_META32:
1767                 meta = UINT32_MAX;
1768                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1769                 break;
1770         default:
1771                 meta = 0;
1772                 mark = 0;
1773                 MLX5_ASSERT(false);
1774                 break;
1775         }
1776         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1777                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1778                                  sh->dv_mark_mask, mark);
1779         else
1780                 sh->dv_mark_mask = mark;
1781         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1782                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1783                                  sh->dv_meta_mask, meta);
1784         else
1785                 sh->dv_meta_mask = meta;
1786         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1787                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1788                                  sh->dv_meta_mask, reg_c0);
1789         else
1790                 sh->dv_regc0_mask = reg_c0;
1791         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1792         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1793         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1794         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1795 }
1796
1797 /**
1798  * Allocate page of door-bells and register it using DevX API.
1799  *
1800  * @param [in] dev
1801  *   Pointer to Ethernet device.
1802  *
1803  * @return
1804  *   Pointer to new page on success, NULL otherwise.
1805  */
1806 static struct mlx5_devx_dbr_page *
1807 mlx5_alloc_dbr_page(struct rte_eth_dev *dev)
1808 {
1809         struct mlx5_priv *priv = dev->data->dev_private;
1810         struct mlx5_devx_dbr_page *page;
1811
1812         /* Allocate space for door-bell page and management data. */
1813         page = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_devx_dbr_page),
1814                                  RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1815         if (!page) {
1816                 DRV_LOG(ERR, "port %u cannot allocate dbr page",
1817                         dev->data->port_id);
1818                 return NULL;
1819         }
1820         /* Register allocated memory. */
1821         page->umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, page->dbrs,
1822                                               MLX5_DBR_PAGE_SIZE, 0);
1823         if (!page->umem) {
1824                 DRV_LOG(ERR, "port %u cannot umem reg dbr page",
1825                         dev->data->port_id);
1826                 rte_free(page);
1827                 return NULL;
1828         }
1829         return page;
1830 }
1831
1832 /**
1833  * Find the next available door-bell, allocate new page if needed.
1834  *
1835  * @param [in] dev
1836  *   Pointer to Ethernet device.
1837  * @param [out] dbr_page
1838  *   Door-bell page containing the page data.
1839  *
1840  * @return
1841  *   Door-bell address offset on success, a negative error value otherwise.
1842  */
1843 int64_t
1844 mlx5_get_dbr(struct rte_eth_dev *dev, struct mlx5_devx_dbr_page **dbr_page)
1845 {
1846         struct mlx5_priv *priv = dev->data->dev_private;
1847         struct mlx5_devx_dbr_page *page = NULL;
1848         uint32_t i, j;
1849
1850         LIST_FOREACH(page, &priv->dbrpgs, next)
1851                 if (page->dbr_count < MLX5_DBR_PER_PAGE)
1852                         break;
1853         if (!page) { /* No page with free door-bell exists. */
1854                 page = mlx5_alloc_dbr_page(dev);
1855                 if (!page) /* Failed to allocate new page. */
1856                         return (-1);
1857                 LIST_INSERT_HEAD(&priv->dbrpgs, page, next);
1858         }
1859         /* Loop to find bitmap part with clear bit. */
1860         for (i = 0;
1861              i < MLX5_DBR_BITMAP_SIZE && page->dbr_bitmap[i] == UINT64_MAX;
1862              i++)
1863                 ; /* Empty. */
1864         /* Find the first clear bit. */
1865         MLX5_ASSERT(i < MLX5_DBR_BITMAP_SIZE);
1866         j = rte_bsf64(~page->dbr_bitmap[i]);
1867         page->dbr_bitmap[i] |= (UINT64_C(1) << j);
1868         page->dbr_count++;
1869         *dbr_page = page;
1870         return (((i * 64) + j) * sizeof(uint64_t));
1871 }
1872
1873 /**
1874  * Release a door-bell record.
1875  *
1876  * @param [in] dev
1877  *   Pointer to Ethernet device.
1878  * @param [in] umem_id
1879  *   UMEM ID of page containing the door-bell record to release.
1880  * @param [in] offset
1881  *   Offset of door-bell record in page.
1882  *
1883  * @return
1884  *   0 on success, a negative error value otherwise.
1885  */
1886 int32_t
1887 mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id, uint64_t offset)
1888 {
1889         struct mlx5_priv *priv = dev->data->dev_private;
1890         struct mlx5_devx_dbr_page *page = NULL;
1891         int ret = 0;
1892
1893         LIST_FOREACH(page, &priv->dbrpgs, next)
1894                 /* Find the page this address belongs to. */
1895                 if (mlx5_os_get_umem_id(page->umem) == umem_id)
1896                         break;
1897         if (!page)
1898                 return -EINVAL;
1899         page->dbr_count--;
1900         if (!page->dbr_count) {
1901                 /* Page not used, free it and remove from list. */
1902                 LIST_REMOVE(page, next);
1903                 if (page->umem)
1904                         ret = -mlx5_glue->devx_umem_dereg(page->umem);
1905                 rte_free(page);
1906         } else {
1907                 /* Mark in bitmap that this door-bell is not in use. */
1908                 offset /= MLX5_DBR_SIZE;
1909                 int i = offset / 64;
1910                 int j = offset % 64;
1911
1912                 page->dbr_bitmap[i] &= ~(UINT64_C(1) << j);
1913         }
1914         return ret;
1915 }
1916
1917 int
1918 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1919 {
1920         static const char *const dynf_names[] = {
1921                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1922                 RTE_MBUF_DYNFLAG_METADATA_NAME
1923         };
1924         unsigned int i;
1925
1926         if (n < RTE_DIM(dynf_names))
1927                 return -ENOMEM;
1928         for (i = 0; i < RTE_DIM(dynf_names); i++) {
1929                 if (names[i] == NULL)
1930                         return -EINVAL;
1931                 strcpy(names[i], dynf_names[i]);
1932         }
1933         return RTE_DIM(dynf_names);
1934 }
1935
1936 /**
1937  * Comparison callback to sort device data.
1938  *
1939  * This is meant to be used with qsort().
1940  *
1941  * @param a[in]
1942  *   Pointer to pointer to first data object.
1943  * @param b[in]
1944  *   Pointer to pointer to second data object.
1945  *
1946  * @return
1947  *   0 if both objects are equal, less than 0 if the first argument is less
1948  *   than the second, greater than 0 otherwise.
1949  */
1950 int
1951 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1952                               struct mlx5_dev_config *config)
1953 {
1954         struct mlx5_dev_ctx_shared *sh = priv->sh;
1955         struct mlx5_dev_config *sh_conf = NULL;
1956         uint16_t port_id;
1957
1958         MLX5_ASSERT(sh);
1959         /* Nothing to compare for the single/first device. */
1960         if (sh->refcnt == 1)
1961                 return 0;
1962         /* Find the device with shared context. */
1963         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1964                 struct mlx5_priv *opriv =
1965                         rte_eth_devices[port_id].data->dev_private;
1966
1967                 if (opriv && opriv != priv && opriv->sh == sh) {
1968                         sh_conf = &opriv->config;
1969                         break;
1970                 }
1971         }
1972         if (!sh_conf)
1973                 return 0;
1974         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1975                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1976                              " for shared %s context", sh->ibdev_name);
1977                 rte_errno = EINVAL;
1978                 return rte_errno;
1979         }
1980         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1981                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1982                              " for shared %s context", sh->ibdev_name);
1983                 rte_errno = EINVAL;
1984                 return rte_errno;
1985         }
1986         return 0;
1987 }
1988
1989 /**
1990  * Look for the ethernet device belonging to mlx5 driver.
1991  *
1992  * @param[in] port_id
1993  *   port_id to start looking for device.
1994  * @param[in] pci_dev
1995  *   Pointer to the hint PCI device. When device is being probed
1996  *   the its siblings (master and preceding representors might
1997  *   not have assigned driver yet (because the mlx5_os_pci_probe()
1998  *   is not completed yet, for this case match on hint PCI
1999  *   device may be used to detect sibling device.
2000  *
2001  * @return
2002  *   port_id of found device, RTE_MAX_ETHPORT if not found.
2003  */
2004 uint16_t
2005 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
2006 {
2007         while (port_id < RTE_MAX_ETHPORTS) {
2008                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2009
2010                 if (dev->state != RTE_ETH_DEV_UNUSED &&
2011                     dev->device &&
2012                     (dev->device == &pci_dev->device ||
2013                      (dev->device->driver &&
2014                      dev->device->driver->name &&
2015                      !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
2016                         break;
2017                 port_id++;
2018         }
2019         if (port_id >= RTE_MAX_ETHPORTS)
2020                 return RTE_MAX_ETHPORTS;
2021         return port_id;
2022 }
2023
2024 /**
2025  * DPDK callback to remove a PCI device.
2026  *
2027  * This function removes all Ethernet devices belong to a given PCI device.
2028  *
2029  * @param[in] pci_dev
2030  *   Pointer to the PCI device.
2031  *
2032  * @return
2033  *   0 on success, the function cannot fail.
2034  */
2035 static int
2036 mlx5_pci_remove(struct rte_pci_device *pci_dev)
2037 {
2038         uint16_t port_id;
2039
2040         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
2041                 /*
2042                  * mlx5_dev_close() is not registered to secondary process,
2043                  * call the close function explicitly for secondary process.
2044                  */
2045                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2046                         mlx5_dev_close(&rte_eth_devices[port_id]);
2047                 else
2048                         rte_eth_dev_close(port_id);
2049         }
2050         return 0;
2051 }
2052
2053 static const struct rte_pci_id mlx5_pci_id_map[] = {
2054         {
2055                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2056                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2057         },
2058         {
2059                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2060                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2061         },
2062         {
2063                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2064                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2065         },
2066         {
2067                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2068                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2069         },
2070         {
2071                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2072                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2073         },
2074         {
2075                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2076                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2077         },
2078         {
2079                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2080                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2081         },
2082         {
2083                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2084                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2085         },
2086         {
2087                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2088                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2089         },
2090         {
2091                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2092                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2093         },
2094         {
2095                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2096                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2097         },
2098         {
2099                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2100                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2101         },
2102         {
2103                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2104                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2105         },
2106         {
2107                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2108                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
2109         },
2110         {
2111                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2112                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2113         },
2114         {
2115                 .vendor_id = 0
2116         }
2117 };
2118
2119 struct rte_pci_driver mlx5_driver = {
2120         .driver = {
2121                 .name = MLX5_DRIVER_NAME
2122         },
2123         .id_table = mlx5_pci_id_map,
2124         .probe = mlx5_os_pci_probe,
2125         .remove = mlx5_pci_remove,
2126         .dma_map = mlx5_dma_map,
2127         .dma_unmap = mlx5_dma_unmap,
2128         .drv_flags = PCI_DRV_FLAGS,
2129 };
2130
2131 /**
2132  * Driver initialization routine.
2133  */
2134 RTE_INIT(rte_mlx5_pmd_init)
2135 {
2136         /* Initialize driver log type. */
2137         mlx5_logtype = rte_log_register("pmd.net.mlx5");
2138         if (mlx5_logtype >= 0)
2139                 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
2140
2141         /* Build the static tables for Verbs conversion. */
2142         mlx5_set_ptype_table();
2143         mlx5_set_cksum_table();
2144         mlx5_set_swp_types_table();
2145         if (mlx5_glue)
2146                 rte_pci_register(&mlx5_driver);
2147 }
2148
2149 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2150 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2151 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");