1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
15 #include <linux/rtnetlink.h>
18 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
20 #pragma GCC diagnostic ignored "-Wpedantic"
22 #include <infiniband/verbs.h>
24 #pragma GCC diagnostic error "-Wpedantic"
27 #include <rte_malloc.h>
28 #include <rte_ethdev_driver.h>
29 #include <rte_ethdev_pci.h>
31 #include <rte_bus_pci.h>
32 #include <rte_common.h>
33 #include <rte_config.h>
34 #include <rte_kvargs.h>
35 #include <rte_rwlock.h>
36 #include <rte_spinlock.h>
37 #include <rte_string_fns.h>
38 #include <rte_alarm.h>
40 #include <mlx5_glue.h>
41 #include <mlx5_devx_cmds.h>
42 #include <mlx5_common.h>
44 #include "mlx5_defs.h"
46 #include "mlx5_utils.h"
47 #include "mlx5_rxtx.h"
48 #include "mlx5_autoconf.h"
50 #include "mlx5_flow.h"
52 /* Device parameter to enable RX completion queue compression. */
53 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
55 /* Device parameter to enable RX completion entry padding to 128B. */
56 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
58 /* Device parameter to enable padding Rx packet to cacheline size. */
59 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
61 /* Device parameter to enable Multi-Packet Rx queue. */
62 #define MLX5_RX_MPRQ_EN "mprq_en"
64 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
65 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
67 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
68 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
70 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
71 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
73 /* Device parameter to configure inline send. Deprecated, ignored.*/
74 #define MLX5_TXQ_INLINE "txq_inline"
76 /* Device parameter to limit packet size to inline with ordinary SEND. */
77 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
79 /* Device parameter to configure minimal data size to inline. */
80 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
82 /* Device parameter to limit packet size to inline with Enhanced MPW. */
83 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
86 * Device parameter to configure the number of TX queues threshold for
87 * enabling inline send.
89 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
92 * Device parameter to configure the number of TX queues threshold for
93 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
95 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
97 /* Device parameter to enable multi-packet send WQEs. */
98 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
101 * Device parameter to force doorbell register mapping
102 * to non-cahed region eliminating the extra write memory barrier.
104 #define MLX5_TX_DB_NC "tx_db_nc"
107 * Device parameter to include 2 dsegs in the title WQEBB.
108 * Deprecated, ignored.
110 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
113 * Device parameter to limit the size of inlining packet.
114 * Deprecated, ignored.
116 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
119 * Device parameter to enable hardware Tx vector.
120 * Deprecated, ignored (no vectorized Tx routines anymore).
122 #define MLX5_TX_VEC_EN "tx_vec_en"
124 /* Device parameter to enable hardware Rx vector. */
125 #define MLX5_RX_VEC_EN "rx_vec_en"
127 /* Allow L3 VXLAN flow creation. */
128 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
130 /* Activate DV E-Switch flow steering. */
131 #define MLX5_DV_ESW_EN "dv_esw_en"
133 /* Activate DV flow steering. */
134 #define MLX5_DV_FLOW_EN "dv_flow_en"
136 /* Enable extensive flow metadata support. */
137 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
139 /* Activate Netlink support in VF mode. */
140 #define MLX5_VF_NL_EN "vf_nl_en"
142 /* Enable extending memsegs when creating a MR. */
143 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
145 /* Select port representors to instantiate. */
146 #define MLX5_REPRESENTOR "representor"
148 /* Device parameter to configure the maximum number of dump files per queue. */
149 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
151 /* Configure timeout of LRO session (in microseconds). */
152 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
154 #ifndef HAVE_IBV_MLX5_MOD_MPW
155 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
156 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
159 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
160 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
163 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
165 /* Shared memory between primary and secondary processes. */
166 struct mlx5_shared_data *mlx5_shared_data;
168 /* Spinlock for mlx5_shared_data allocation. */
169 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
171 /* Process local data for secondary processes. */
172 static struct mlx5_local_data mlx5_local_data;
174 /** Driver-specific log messages type. */
177 /** Data associated with devices to spawn. */
178 struct mlx5_dev_spawn_data {
179 uint32_t ifindex; /**< Network interface index. */
180 uint32_t max_port; /**< IB device maximal port index. */
181 uint32_t ibv_port; /**< IB device physical port index. */
182 int pf_bond; /**< bonding device PF index. < 0 - no bonding */
183 struct mlx5_switch_info info; /**< Switch information. */
184 struct ibv_device *ibv_dev; /**< Associated IB device. */
185 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
186 struct rte_pci_device *pci_dev; /**< Backend PCI device. */
189 static LIST_HEAD(, mlx5_ibv_shared) mlx5_ibv_list = LIST_HEAD_INITIALIZER();
190 static pthread_mutex_t mlx5_ibv_list_mutex = PTHREAD_MUTEX_INITIALIZER;
192 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
193 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
195 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
196 #define MLX5_TAGS_HLIST_ARRAY_SIZE 8192
199 * Allocate ID pool structure.
202 * The maximum id can be allocated from the pool.
205 * Pointer to pool object, NULL value otherwise.
207 struct mlx5_flow_id_pool *
208 mlx5_flow_id_pool_alloc(uint32_t max_id)
210 struct mlx5_flow_id_pool *pool;
213 pool = rte_zmalloc("id pool allocation", sizeof(*pool),
214 RTE_CACHE_LINE_SIZE);
216 DRV_LOG(ERR, "can't allocate id pool");
220 mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
221 RTE_CACHE_LINE_SIZE);
223 DRV_LOG(ERR, "can't allocate mem for id pool");
227 pool->free_arr = mem;
228 pool->curr = pool->free_arr;
229 pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
230 pool->base_index = 0;
231 pool->max_id = max_id;
239 * Release ID pool structure.
242 * Pointer to flow id pool object to free.
245 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
247 rte_free(pool->free_arr);
255 * Pointer to flow id pool.
260 * 0 on success, error value otherwise.
263 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
265 if (pool->curr == pool->free_arr) {
266 if (pool->base_index == pool->max_id) {
268 DRV_LOG(ERR, "no free id");
271 *id = ++pool->base_index;
274 *id = *(--pool->curr);
282 * Pointer to flow id pool.
287 * 0 on success, error value otherwise.
290 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
296 if (pool->curr == pool->last) {
297 size = pool->curr - pool->free_arr;
298 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
299 assert(size2 > size);
300 mem = rte_malloc("", size2 * sizeof(uint32_t), 0);
302 DRV_LOG(ERR, "can't allocate mem for id pool");
306 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
307 rte_free(pool->free_arr);
308 pool->free_arr = mem;
309 pool->curr = pool->free_arr + size;
310 pool->last = pool->free_arr + size2;
318 * Initialize the counters management structure.
321 * Pointer to mlx5_ibv_shared object to free
324 mlx5_flow_counters_mng_init(struct mlx5_ibv_shared *sh)
328 TAILQ_INIT(&sh->cmng.flow_counters);
329 for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i)
330 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
334 * Destroy all the resources allocated for a counter memory management.
337 * Pointer to the memory management structure.
340 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
342 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
344 LIST_REMOVE(mng, next);
345 claim_zero(mlx5_devx_cmd_destroy(mng->dm));
346 claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
351 * Close and release all the resources of the counters management.
354 * Pointer to mlx5_ibv_shared object to free.
357 mlx5_flow_counters_mng_close(struct mlx5_ibv_shared *sh)
359 struct mlx5_counter_stats_mem_mng *mng;
366 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
367 if (rte_errno != EINPROGRESS)
371 for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i) {
372 struct mlx5_flow_counter_pool *pool;
373 uint32_t batch = !!(i % 2);
375 if (!sh->cmng.ccont[i].pools)
377 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
382 (mlx5_devx_cmd_destroy(pool->min_dcs));
384 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
385 if (pool->counters_raw[j].action)
387 (mlx5_glue->destroy_flow_action
388 (pool->counters_raw[j].action));
389 if (!batch && pool->counters_raw[j].dcs)
390 claim_zero(mlx5_devx_cmd_destroy
391 (pool->counters_raw[j].dcs));
393 TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool,
396 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
398 rte_free(sh->cmng.ccont[i].pools);
400 mng = LIST_FIRST(&sh->cmng.mem_mngs);
402 mlx5_flow_destroy_counter_stat_mem_mng(mng);
403 mng = LIST_FIRST(&sh->cmng.mem_mngs);
405 memset(&sh->cmng, 0, sizeof(sh->cmng));
409 * Extract pdn of PD object using DV API.
412 * Pointer to the verbs PD object.
414 * Pointer to the PD object number variable.
417 * 0 on success, error value otherwise.
419 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
421 mlx5_get_pdn(struct ibv_pd *pd __rte_unused, uint32_t *pdn __rte_unused)
423 struct mlx5dv_obj obj;
424 struct mlx5dv_pd pd_info;
428 obj.pd.out = &pd_info;
429 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);
431 DRV_LOG(DEBUG, "Fail to get PD object info");
437 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
440 mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config)
445 assert(rte_eal_process_type() == RTE_PROC_PRIMARY);
446 /* Get environment variable to store. */
447 env = getenv(MLX5_SHUT_UP_BF);
448 value = env ? !!strcmp(env, "0") : MLX5_ARG_UNSET;
449 if (config->dbnc == MLX5_ARG_UNSET)
450 setenv(MLX5_SHUT_UP_BF, MLX5_SHUT_UP_BF_DEFAULT, 1);
452 setenv(MLX5_SHUT_UP_BF,
453 config->dbnc == MLX5_TXDB_NCACHED ? "1" : "0", 1);
458 mlx5_restore_doorbell_mapping_env(int value)
460 assert(rte_eal_process_type() == RTE_PROC_PRIMARY);
461 /* Restore the original environment variable state. */
462 if (value == MLX5_ARG_UNSET)
463 unsetenv(MLX5_SHUT_UP_BF);
465 setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1);
469 * Allocate shared IB device context. If there is multiport device the
470 * master and representors will share this context, if there is single
471 * port dedicated IB device, the context will be used by only given
472 * port due to unification.
474 * Routine first searches the context for the specified IB device name,
475 * if found the shared context assumed and reference counter is incremented.
476 * If no context found the new one is created and initialized with specified
477 * IB device context and parameters.
480 * Pointer to the IB device attributes (name, port, etc).
482 * Pointer to device configuration structure.
485 * Pointer to mlx5_ibv_shared object on success,
486 * otherwise NULL and rte_errno is set.
488 static struct mlx5_ibv_shared *
489 mlx5_alloc_shared_ibctx(const struct mlx5_dev_spawn_data *spawn,
490 const struct mlx5_dev_config *config)
492 struct mlx5_ibv_shared *sh;
496 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
497 struct mlx5_devx_tis_attr tis_attr = { 0 };
501 /* Secondary process should not create the shared context. */
502 assert(rte_eal_process_type() == RTE_PROC_PRIMARY);
503 pthread_mutex_lock(&mlx5_ibv_list_mutex);
504 /* Search for IB context by device name. */
505 LIST_FOREACH(sh, &mlx5_ibv_list, next) {
506 if (!strcmp(sh->ibdev_name, spawn->ibv_dev->name)) {
511 /* No device found, we have to create new shared context. */
512 assert(spawn->max_port);
513 sh = rte_zmalloc("ethdev shared ib context",
514 sizeof(struct mlx5_ibv_shared) +
516 sizeof(struct mlx5_ibv_shared_port),
517 RTE_CACHE_LINE_SIZE);
519 DRV_LOG(ERR, "shared context allocation failure");
524 * Configure environment variable "MLX5_BF_SHUT_UP"
525 * before the device creation. The rdma_core library
526 * checks the variable at device creation and
527 * stores the result internally.
529 dbmap_env = mlx5_config_doorbell_mapping_env(config);
530 /* Try to open IB device with DV first, then usual Verbs. */
532 sh->ctx = mlx5_glue->dv_open_device(spawn->ibv_dev);
535 DRV_LOG(DEBUG, "DevX is supported");
536 /* The device is created, no need for environment. */
537 mlx5_restore_doorbell_mapping_env(dbmap_env);
539 /* The environment variable is still configured. */
540 sh->ctx = mlx5_glue->open_device(spawn->ibv_dev);
541 err = errno ? errno : ENODEV;
543 * The environment variable is not needed anymore,
544 * all device creation attempts are completed.
546 mlx5_restore_doorbell_mapping_env(dbmap_env);
549 DRV_LOG(DEBUG, "DevX is NOT supported");
551 err = mlx5_glue->query_device_ex(sh->ctx, NULL, &sh->device_attr);
553 DRV_LOG(DEBUG, "ibv_query_device_ex() failed");
557 sh->max_port = spawn->max_port;
558 strncpy(sh->ibdev_name, sh->ctx->device->name,
559 sizeof(sh->ibdev_name));
560 strncpy(sh->ibdev_path, sh->ctx->device->ibdev_path,
561 sizeof(sh->ibdev_path));
562 pthread_mutex_init(&sh->intr_mutex, NULL);
564 * Setting port_id to max unallowed value means
565 * there is no interrupt subhandler installed for
566 * the given port index i.
568 for (i = 0; i < sh->max_port; i++) {
569 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
570 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
572 sh->pd = mlx5_glue->alloc_pd(sh->ctx);
573 if (sh->pd == NULL) {
574 DRV_LOG(ERR, "PD allocation failure");
578 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
580 err = mlx5_get_pdn(sh->pd, &sh->pdn);
582 DRV_LOG(ERR, "Fail to extract pdn from PD");
585 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
587 DRV_LOG(ERR, "TD allocation failure");
591 tis_attr.transport_domain = sh->td->id;
592 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
594 DRV_LOG(ERR, "TIS allocation failure");
599 sh->flow_id_pool = mlx5_flow_id_pool_alloc(UINT32_MAX);
600 if (!sh->flow_id_pool) {
601 DRV_LOG(ERR, "can't create flow id pool");
605 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
607 * Once the device is added to the list of memory event
608 * callback, its global MR cache table cannot be expanded
609 * on the fly because of deadlock. If it overflows, lookup
610 * should be done by searching MR list linearly, which is slow.
612 * At this point the device is not added to the memory
613 * event list yet, context is just being created.
615 err = mlx5_mr_btree_init(&sh->mr.cache,
616 MLX5_MR_BTREE_CACHE_N * 2,
617 spawn->pci_dev->device.numa_node);
622 mlx5_flow_counters_mng_init(sh);
623 /* Add device to memory callback list. */
624 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
625 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
627 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
628 /* Add context to the global device list. */
629 LIST_INSERT_HEAD(&mlx5_ibv_list, sh, next);
631 pthread_mutex_unlock(&mlx5_ibv_list_mutex);
634 pthread_mutex_unlock(&mlx5_ibv_list_mutex);
637 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
639 claim_zero(mlx5_devx_cmd_destroy(sh->td));
641 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
643 claim_zero(mlx5_glue->close_device(sh->ctx));
644 if (sh->flow_id_pool)
645 mlx5_flow_id_pool_release(sh->flow_id_pool);
653 * Free shared IB device context. Decrement counter and if zero free
654 * all allocated resources and close handles.
657 * Pointer to mlx5_ibv_shared object to free
660 mlx5_free_shared_ibctx(struct mlx5_ibv_shared *sh)
662 pthread_mutex_lock(&mlx5_ibv_list_mutex);
664 /* Check the object presence in the list. */
665 struct mlx5_ibv_shared *lctx;
667 LIST_FOREACH(lctx, &mlx5_ibv_list, next)
672 DRV_LOG(ERR, "Freeing non-existing shared IB context");
678 /* Secondary process should not free the shared context. */
679 assert(rte_eal_process_type() == RTE_PROC_PRIMARY);
682 /* Release created Memory Regions. */
684 /* Remove from memory callback device list. */
685 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
686 LIST_REMOVE(sh, mem_event_cb);
687 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
688 /* Remove context from the global device list. */
689 LIST_REMOVE(sh, next);
691 * Ensure there is no async event handler installed.
692 * Only primary process handles async device events.
694 mlx5_flow_counters_mng_close(sh);
695 assert(!sh->intr_cnt);
697 mlx5_intr_callback_unregister
698 (&sh->intr_handle, mlx5_dev_interrupt_handler, sh);
699 #ifdef HAVE_MLX5_DEVX_ASYNC_SUPPORT
700 if (sh->devx_intr_cnt) {
701 if (sh->intr_handle_devx.fd)
702 rte_intr_callback_unregister(&sh->intr_handle_devx,
703 mlx5_dev_interrupt_handler_devx, sh);
705 mlx5dv_devx_destroy_cmd_comp(sh->devx_comp);
708 pthread_mutex_destroy(&sh->intr_mutex);
710 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
712 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
714 claim_zero(mlx5_devx_cmd_destroy(sh->td));
716 claim_zero(mlx5_glue->close_device(sh->ctx));
717 if (sh->flow_id_pool)
718 mlx5_flow_id_pool_release(sh->flow_id_pool);
721 pthread_mutex_unlock(&mlx5_ibv_list_mutex);
725 * Destroy table hash list and all the root entries per domain.
728 * Pointer to the private device data structure.
731 mlx5_free_table_hash_list(struct mlx5_priv *priv)
733 struct mlx5_ibv_shared *sh = priv->sh;
734 struct mlx5_flow_tbl_data_entry *tbl_data;
735 union mlx5_flow_tbl_key table_key = {
743 struct mlx5_hlist_entry *pos;
747 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
749 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
752 mlx5_hlist_remove(sh->flow_tbls, pos);
755 table_key.direction = 1;
756 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
758 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
761 mlx5_hlist_remove(sh->flow_tbls, pos);
764 table_key.direction = 0;
765 table_key.domain = 1;
766 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
768 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
771 mlx5_hlist_remove(sh->flow_tbls, pos);
774 mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
778 * Initialize flow table hash list and create the root tables entry
782 * Pointer to the private device data structure.
785 * Zero on success, positive error code otherwise.
788 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
790 struct mlx5_ibv_shared *sh = priv->sh;
791 char s[MLX5_HLIST_NAMESIZE];
795 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
796 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
797 if (!sh->flow_tbls) {
798 DRV_LOG(ERR, "flow tables with hash creation failed.\n");
802 #ifndef HAVE_MLX5DV_DR
804 * In case we have not DR support, the zero tables should be created
805 * because DV expect to see them even if they cannot be created by
808 union mlx5_flow_tbl_key table_key = {
816 struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL,
817 sizeof(*tbl_data), 0);
823 tbl_data->entry.key = table_key.v64;
824 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
827 rte_atomic32_init(&tbl_data->tbl.refcnt);
828 rte_atomic32_inc(&tbl_data->tbl.refcnt);
829 table_key.direction = 1;
830 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
835 tbl_data->entry.key = table_key.v64;
836 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
839 rte_atomic32_init(&tbl_data->tbl.refcnt);
840 rte_atomic32_inc(&tbl_data->tbl.refcnt);
841 table_key.direction = 0;
842 table_key.domain = 1;
843 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
848 tbl_data->entry.key = table_key.v64;
849 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
852 rte_atomic32_init(&tbl_data->tbl.refcnt);
853 rte_atomic32_inc(&tbl_data->tbl.refcnt);
856 mlx5_free_table_hash_list(priv);
857 #endif /* HAVE_MLX5DV_DR */
862 * Initialize DR related data within private structure.
863 * Routine checks the reference counter and does actual
864 * resources creation/initialization only if counter is zero.
867 * Pointer to the private device data structure.
870 * Zero on success, positive error code otherwise.
873 mlx5_alloc_shared_dr(struct mlx5_priv *priv)
875 struct mlx5_ibv_shared *sh = priv->sh;
876 char s[MLX5_HLIST_NAMESIZE];
880 err = mlx5_alloc_table_hash_list(priv);
882 DRV_LOG(DEBUG, "sh->flow_tbls[%p] already created, reuse\n",
883 (void *)sh->flow_tbls);
886 /* Create tags hash list table. */
887 snprintf(s, sizeof(s), "%s_tags", sh->ibdev_name);
888 sh->tag_table = mlx5_hlist_create(s, MLX5_TAGS_HLIST_ARRAY_SIZE);
889 if (!sh->tag_table) {
890 DRV_LOG(ERR, "tags with hash creation failed.\n");
894 #ifdef HAVE_MLX5DV_DR
898 /* Shared DV/DR structures is already initialized. */
903 /* Reference counter is zero, we should initialize structures. */
904 domain = mlx5_glue->dr_create_domain(sh->ctx,
905 MLX5DV_DR_DOMAIN_TYPE_NIC_RX);
907 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed");
911 sh->rx_domain = domain;
912 domain = mlx5_glue->dr_create_domain(sh->ctx,
913 MLX5DV_DR_DOMAIN_TYPE_NIC_TX);
915 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed");
919 pthread_mutex_init(&sh->dv_mutex, NULL);
920 sh->tx_domain = domain;
921 #ifdef HAVE_MLX5DV_DR_ESWITCH
922 if (priv->config.dv_esw_en) {
923 domain = mlx5_glue->dr_create_domain
924 (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB);
926 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed");
930 sh->fdb_domain = domain;
931 sh->esw_drop_action = mlx5_glue->dr_create_flow_action_drop();
934 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan();
935 #endif /* HAVE_MLX5DV_DR */
940 /* Rollback the created objects. */
942 mlx5_glue->dr_destroy_domain(sh->rx_domain);
943 sh->rx_domain = NULL;
946 mlx5_glue->dr_destroy_domain(sh->tx_domain);
947 sh->tx_domain = NULL;
949 if (sh->fdb_domain) {
950 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
951 sh->fdb_domain = NULL;
953 if (sh->esw_drop_action) {
954 mlx5_glue->destroy_flow_action(sh->esw_drop_action);
955 sh->esw_drop_action = NULL;
957 if (sh->pop_vlan_action) {
958 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
959 sh->pop_vlan_action = NULL;
962 /* tags should be destroyed with flow before. */
963 mlx5_hlist_destroy(sh->tag_table, NULL, NULL);
964 sh->tag_table = NULL;
966 mlx5_free_table_hash_list(priv);
971 * Destroy DR related data within private structure.
974 * Pointer to the private device data structure.
977 mlx5_free_shared_dr(struct mlx5_priv *priv)
979 struct mlx5_ibv_shared *sh;
981 if (!priv->dr_shared)
986 #ifdef HAVE_MLX5DV_DR
987 assert(sh->dv_refcnt);
988 if (sh->dv_refcnt && --sh->dv_refcnt)
991 mlx5_glue->dr_destroy_domain(sh->rx_domain);
992 sh->rx_domain = NULL;
995 mlx5_glue->dr_destroy_domain(sh->tx_domain);
996 sh->tx_domain = NULL;
998 #ifdef HAVE_MLX5DV_DR_ESWITCH
999 if (sh->fdb_domain) {
1000 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
1001 sh->fdb_domain = NULL;
1003 if (sh->esw_drop_action) {
1004 mlx5_glue->destroy_flow_action(sh->esw_drop_action);
1005 sh->esw_drop_action = NULL;
1008 if (sh->pop_vlan_action) {
1009 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
1010 sh->pop_vlan_action = NULL;
1012 pthread_mutex_destroy(&sh->dv_mutex);
1013 #endif /* HAVE_MLX5DV_DR */
1014 if (sh->tag_table) {
1015 /* tags should be destroyed with flow before. */
1016 mlx5_hlist_destroy(sh->tag_table, NULL, NULL);
1017 sh->tag_table = NULL;
1019 mlx5_free_table_hash_list(priv);
1023 * Initialize shared data between primary and secondary process.
1025 * A memzone is reserved by primary process and secondary processes attach to
1029 * 0 on success, a negative errno value otherwise and rte_errno is set.
1032 mlx5_init_shared_data(void)
1034 const struct rte_memzone *mz;
1037 rte_spinlock_lock(&mlx5_shared_data_lock);
1038 if (mlx5_shared_data == NULL) {
1039 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
1040 /* Allocate shared memory. */
1041 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
1042 sizeof(*mlx5_shared_data),
1046 "Cannot allocate mlx5 shared data");
1050 mlx5_shared_data = mz->addr;
1051 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
1052 rte_spinlock_init(&mlx5_shared_data->lock);
1054 /* Lookup allocated shared memory. */
1055 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
1058 "Cannot attach mlx5 shared data");
1062 mlx5_shared_data = mz->addr;
1063 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
1067 rte_spinlock_unlock(&mlx5_shared_data_lock);
1072 * Retrieve integer value from environment variable.
1075 * Environment variable name.
1078 * Integer value, 0 if the variable is not set.
1081 mlx5_getenv_int(const char *name)
1083 const char *val = getenv(name);
1091 * Verbs callback to allocate a memory. This function should allocate the space
1092 * according to the size provided residing inside a huge page.
1093 * Please note that all allocation must respect the alignment from libmlx5
1094 * (i.e. currently sysconf(_SC_PAGESIZE)).
1097 * The size in bytes of the memory to allocate.
1099 * A pointer to the callback data.
1102 * Allocated buffer, NULL otherwise and rte_errno is set.
1105 mlx5_alloc_verbs_buf(size_t size, void *data)
1107 struct mlx5_priv *priv = data;
1109 size_t alignment = sysconf(_SC_PAGESIZE);
1110 unsigned int socket = SOCKET_ID_ANY;
1112 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
1113 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
1115 socket = ctrl->socket;
1116 } else if (priv->verbs_alloc_ctx.type ==
1117 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
1118 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
1120 socket = ctrl->socket;
1122 assert(data != NULL);
1123 ret = rte_malloc_socket(__func__, size, alignment, socket);
1130 * Verbs callback to free a memory.
1133 * A pointer to the memory to free.
1135 * A pointer to the callback data.
1138 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
1140 assert(data != NULL);
1145 * DPDK callback to add udp tunnel port
1148 * A pointer to eth_dev
1149 * @param[in] udp_tunnel
1150 * A pointer to udp tunnel
1153 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1156 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1157 struct rte_eth_udp_tunnel *udp_tunnel)
1159 assert(udp_tunnel != NULL);
1160 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1161 udp_tunnel->udp_port == 4789)
1163 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1164 udp_tunnel->udp_port == 4790)
1170 * Initialize process private data structure.
1173 * Pointer to Ethernet device structure.
1176 * 0 on success, a negative errno value otherwise and rte_errno is set.
1179 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1181 struct mlx5_priv *priv = dev->data->dev_private;
1182 struct mlx5_proc_priv *ppriv;
1186 * UAR register table follows the process private structure. BlueFlame
1187 * registers for Tx queues are stored in the table.
1190 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1191 ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
1192 RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1197 ppriv->uar_table_sz = ppriv_size;
1198 dev->process_private = ppriv;
1203 * Un-initialize process private data structure.
1206 * Pointer to Ethernet device structure.
1209 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1211 if (!dev->process_private)
1213 rte_free(dev->process_private);
1214 dev->process_private = NULL;
1218 * DPDK callback to close the device.
1220 * Destroy all queues and objects, free memory.
1223 * Pointer to Ethernet device structure.
1226 mlx5_dev_close(struct rte_eth_dev *dev)
1228 struct mlx5_priv *priv = dev->data->dev_private;
1232 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1234 ((priv->sh->ctx != NULL) ? priv->sh->ctx->device->name : ""));
1235 /* In case mlx5_dev_stop() has not been called. */
1236 mlx5_dev_interrupt_handler_uninstall(dev);
1237 mlx5_dev_interrupt_handler_devx_uninstall(dev);
1238 mlx5_traffic_disable(dev);
1239 mlx5_flow_flush(dev, NULL);
1240 mlx5_flow_meter_flush(dev, NULL);
1241 /* Prevent crashes when queues are still in use. */
1242 dev->rx_pkt_burst = removed_rx_burst;
1243 dev->tx_pkt_burst = removed_tx_burst;
1245 /* Disable datapath on secondary process. */
1246 mlx5_mp_req_stop_rxtx(dev);
1247 if (priv->rxqs != NULL) {
1248 /* XXX race condition if mlx5_rx_burst() is still running. */
1250 for (i = 0; (i != priv->rxqs_n); ++i)
1251 mlx5_rxq_release(dev, i);
1255 if (priv->txqs != NULL) {
1256 /* XXX race condition if mlx5_tx_burst() is still running. */
1258 for (i = 0; (i != priv->txqs_n); ++i)
1259 mlx5_txq_release(dev, i);
1263 mlx5_proc_priv_uninit(dev);
1264 if (priv->mreg_cp_tbl)
1265 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1266 mlx5_mprq_free_mp(dev);
1267 mlx5_free_shared_dr(priv);
1268 if (priv->rss_conf.rss_key != NULL)
1269 rte_free(priv->rss_conf.rss_key);
1270 if (priv->reta_idx != NULL)
1271 rte_free(priv->reta_idx);
1272 if (priv->config.vf)
1273 mlx5_nl_mac_addr_flush(dev);
1274 if (priv->nl_socket_route >= 0)
1275 close(priv->nl_socket_route);
1276 if (priv->nl_socket_rdma >= 0)
1277 close(priv->nl_socket_rdma);
1278 if (priv->vmwa_context)
1279 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1282 * Free the shared context in last turn, because the cleanup
1283 * routines above may use some shared fields, like
1284 * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1285 * ifindex if Netlink fails.
1287 mlx5_free_shared_ibctx(priv->sh);
1290 ret = mlx5_hrxq_verify(dev);
1292 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1293 dev->data->port_id);
1294 ret = mlx5_ind_table_obj_verify(dev);
1296 DRV_LOG(WARNING, "port %u some indirection table still remain",
1297 dev->data->port_id);
1298 ret = mlx5_rxq_obj_verify(dev);
1300 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1301 dev->data->port_id);
1302 ret = mlx5_rxq_verify(dev);
1304 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1305 dev->data->port_id);
1306 ret = mlx5_txq_obj_verify(dev);
1308 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1309 dev->data->port_id);
1310 ret = mlx5_txq_verify(dev);
1312 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1313 dev->data->port_id);
1314 ret = mlx5_flow_verify(dev);
1316 DRV_LOG(WARNING, "port %u some flows still remain",
1317 dev->data->port_id);
1318 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1322 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1323 struct mlx5_priv *opriv =
1324 rte_eth_devices[port_id].data->dev_private;
1327 opriv->domain_id != priv->domain_id ||
1328 &rte_eth_devices[port_id] == dev)
1334 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1336 memset(priv, 0, sizeof(*priv));
1337 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1339 * Reset mac_addrs to NULL such that it is not freed as part of
1340 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1341 * it is freed when dev_private is freed.
1343 dev->data->mac_addrs = NULL;
1346 const struct eth_dev_ops mlx5_dev_ops = {
1347 .dev_configure = mlx5_dev_configure,
1348 .dev_start = mlx5_dev_start,
1349 .dev_stop = mlx5_dev_stop,
1350 .dev_set_link_down = mlx5_set_link_down,
1351 .dev_set_link_up = mlx5_set_link_up,
1352 .dev_close = mlx5_dev_close,
1353 .promiscuous_enable = mlx5_promiscuous_enable,
1354 .promiscuous_disable = mlx5_promiscuous_disable,
1355 .allmulticast_enable = mlx5_allmulticast_enable,
1356 .allmulticast_disable = mlx5_allmulticast_disable,
1357 .link_update = mlx5_link_update,
1358 .stats_get = mlx5_stats_get,
1359 .stats_reset = mlx5_stats_reset,
1360 .xstats_get = mlx5_xstats_get,
1361 .xstats_reset = mlx5_xstats_reset,
1362 .xstats_get_names = mlx5_xstats_get_names,
1363 .fw_version_get = mlx5_fw_version_get,
1364 .dev_infos_get = mlx5_dev_infos_get,
1365 .read_clock = mlx5_read_clock,
1366 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1367 .vlan_filter_set = mlx5_vlan_filter_set,
1368 .rx_queue_setup = mlx5_rx_queue_setup,
1369 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1370 .tx_queue_setup = mlx5_tx_queue_setup,
1371 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1372 .rx_queue_release = mlx5_rx_queue_release,
1373 .tx_queue_release = mlx5_tx_queue_release,
1374 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1375 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1376 .mac_addr_remove = mlx5_mac_addr_remove,
1377 .mac_addr_add = mlx5_mac_addr_add,
1378 .mac_addr_set = mlx5_mac_addr_set,
1379 .set_mc_addr_list = mlx5_set_mc_addr_list,
1380 .mtu_set = mlx5_dev_set_mtu,
1381 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1382 .vlan_offload_set = mlx5_vlan_offload_set,
1383 .reta_update = mlx5_dev_rss_reta_update,
1384 .reta_query = mlx5_dev_rss_reta_query,
1385 .rss_hash_update = mlx5_rss_hash_update,
1386 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1387 .filter_ctrl = mlx5_dev_filter_ctrl,
1388 .rx_descriptor_status = mlx5_rx_descriptor_status,
1389 .tx_descriptor_status = mlx5_tx_descriptor_status,
1390 .rx_queue_count = mlx5_rx_queue_count,
1391 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1392 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1393 .is_removed = mlx5_is_removed,
1394 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add,
1395 .get_module_info = mlx5_get_module_info,
1396 .get_module_eeprom = mlx5_get_module_eeprom,
1397 .hairpin_cap_get = mlx5_hairpin_cap_get,
1398 .mtr_ops_get = mlx5_flow_meter_ops_get,
1401 /* Available operations from secondary process. */
1402 static const struct eth_dev_ops mlx5_dev_sec_ops = {
1403 .stats_get = mlx5_stats_get,
1404 .stats_reset = mlx5_stats_reset,
1405 .xstats_get = mlx5_xstats_get,
1406 .xstats_reset = mlx5_xstats_reset,
1407 .xstats_get_names = mlx5_xstats_get_names,
1408 .fw_version_get = mlx5_fw_version_get,
1409 .dev_infos_get = mlx5_dev_infos_get,
1410 .rx_descriptor_status = mlx5_rx_descriptor_status,
1411 .tx_descriptor_status = mlx5_tx_descriptor_status,
1412 .get_module_info = mlx5_get_module_info,
1413 .get_module_eeprom = mlx5_get_module_eeprom,
1416 /* Available operations in flow isolated mode. */
1417 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1418 .dev_configure = mlx5_dev_configure,
1419 .dev_start = mlx5_dev_start,
1420 .dev_stop = mlx5_dev_stop,
1421 .dev_set_link_down = mlx5_set_link_down,
1422 .dev_set_link_up = mlx5_set_link_up,
1423 .dev_close = mlx5_dev_close,
1424 .promiscuous_enable = mlx5_promiscuous_enable,
1425 .promiscuous_disable = mlx5_promiscuous_disable,
1426 .allmulticast_enable = mlx5_allmulticast_enable,
1427 .allmulticast_disable = mlx5_allmulticast_disable,
1428 .link_update = mlx5_link_update,
1429 .stats_get = mlx5_stats_get,
1430 .stats_reset = mlx5_stats_reset,
1431 .xstats_get = mlx5_xstats_get,
1432 .xstats_reset = mlx5_xstats_reset,
1433 .xstats_get_names = mlx5_xstats_get_names,
1434 .fw_version_get = mlx5_fw_version_get,
1435 .dev_infos_get = mlx5_dev_infos_get,
1436 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1437 .vlan_filter_set = mlx5_vlan_filter_set,
1438 .rx_queue_setup = mlx5_rx_queue_setup,
1439 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1440 .tx_queue_setup = mlx5_tx_queue_setup,
1441 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1442 .rx_queue_release = mlx5_rx_queue_release,
1443 .tx_queue_release = mlx5_tx_queue_release,
1444 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1445 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1446 .mac_addr_remove = mlx5_mac_addr_remove,
1447 .mac_addr_add = mlx5_mac_addr_add,
1448 .mac_addr_set = mlx5_mac_addr_set,
1449 .set_mc_addr_list = mlx5_set_mc_addr_list,
1450 .mtu_set = mlx5_dev_set_mtu,
1451 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1452 .vlan_offload_set = mlx5_vlan_offload_set,
1453 .filter_ctrl = mlx5_dev_filter_ctrl,
1454 .rx_descriptor_status = mlx5_rx_descriptor_status,
1455 .tx_descriptor_status = mlx5_tx_descriptor_status,
1456 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1457 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1458 .is_removed = mlx5_is_removed,
1459 .get_module_info = mlx5_get_module_info,
1460 .get_module_eeprom = mlx5_get_module_eeprom,
1461 .hairpin_cap_get = mlx5_hairpin_cap_get,
1462 .mtr_ops_get = mlx5_flow_meter_ops_get,
1466 * Verify and store value for device argument.
1469 * Key argument to verify.
1471 * Value associated with key.
1476 * 0 on success, a negative errno value otherwise and rte_errno is set.
1479 mlx5_args_check(const char *key, const char *val, void *opaque)
1481 struct mlx5_dev_config *config = opaque;
1484 /* No-op, port representors are processed in mlx5_dev_spawn(). */
1485 if (!strcmp(MLX5_REPRESENTOR, key))
1488 tmp = strtoul(val, NULL, 0);
1491 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1494 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1495 config->cqe_comp = !!tmp;
1496 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1497 config->cqe_pad = !!tmp;
1498 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1499 config->hw_padding = !!tmp;
1500 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1501 config->mprq.enabled = !!tmp;
1502 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1503 config->mprq.stride_num_n = tmp;
1504 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1505 config->mprq.max_memcpy_len = tmp;
1506 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1507 config->mprq.min_rxqs_num = tmp;
1508 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1509 DRV_LOG(WARNING, "%s: deprecated parameter,"
1510 " converted to txq_inline_max", key);
1511 config->txq_inline_max = tmp;
1512 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1513 config->txq_inline_max = tmp;
1514 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1515 config->txq_inline_min = tmp;
1516 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1517 config->txq_inline_mpw = tmp;
1518 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1519 config->txqs_inline = tmp;
1520 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1521 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1522 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1523 config->mps = !!tmp;
1524 } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1525 if (tmp != MLX5_TXDB_CACHED &&
1526 tmp != MLX5_TXDB_NCACHED &&
1527 tmp != MLX5_TXDB_HEURISTIC) {
1528 DRV_LOG(ERR, "invalid Tx doorbell "
1529 "mapping parameter");
1534 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1535 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1536 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1537 DRV_LOG(WARNING, "%s: deprecated parameter,"
1538 " converted to txq_inline_mpw", key);
1539 config->txq_inline_mpw = tmp;
1540 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1541 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1542 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1543 config->rx_vec_en = !!tmp;
1544 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1545 config->l3_vxlan_en = !!tmp;
1546 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1547 config->vf_nl_en = !!tmp;
1548 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1549 config->dv_esw_en = !!tmp;
1550 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1551 config->dv_flow_en = !!tmp;
1552 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1553 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1554 tmp != MLX5_XMETA_MODE_META16 &&
1555 tmp != MLX5_XMETA_MODE_META32) {
1556 DRV_LOG(ERR, "invalid extensive "
1557 "metadata parameter");
1561 config->dv_xmeta_en = tmp;
1562 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1563 config->mr_ext_memseg_en = !!tmp;
1564 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1565 config->max_dump_files_num = tmp;
1566 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1567 config->lro.timeout = tmp;
1569 DRV_LOG(WARNING, "%s: unknown parameter", key);
1577 * Parse device parameters.
1580 * Pointer to device configuration structure.
1582 * Device arguments structure.
1585 * 0 on success, a negative errno value otherwise and rte_errno is set.
1588 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1590 const char **params = (const char *[]){
1591 MLX5_RXQ_CQE_COMP_EN,
1592 MLX5_RXQ_CQE_PAD_EN,
1593 MLX5_RXQ_PKT_PAD_EN,
1595 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1596 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1599 MLX5_TXQ_INLINE_MIN,
1600 MLX5_TXQ_INLINE_MAX,
1601 MLX5_TXQ_INLINE_MPW,
1602 MLX5_TXQS_MIN_INLINE,
1605 MLX5_TXQ_MPW_HDR_DSEG_EN,
1606 MLX5_TXQ_MAX_INLINE_LEN,
1615 MLX5_MR_EXT_MEMSEG_EN,
1617 MLX5_MAX_DUMP_FILES_NUM,
1618 MLX5_LRO_TIMEOUT_USEC,
1621 struct rte_kvargs *kvlist;
1625 if (devargs == NULL)
1627 /* Following UGLY cast is done to pass checkpatch. */
1628 kvlist = rte_kvargs_parse(devargs->args, params);
1629 if (kvlist == NULL) {
1633 /* Process parameters. */
1634 for (i = 0; (params[i] != NULL); ++i) {
1635 if (rte_kvargs_count(kvlist, params[i])) {
1636 ret = rte_kvargs_process(kvlist, params[i],
1637 mlx5_args_check, config);
1640 rte_kvargs_free(kvlist);
1645 rte_kvargs_free(kvlist);
1649 static struct rte_pci_driver mlx5_driver;
1652 * PMD global initialization.
1654 * Independent from individual device, this function initializes global
1655 * per-PMD data structures distinguishing primary and secondary processes.
1656 * Hence, each initialization is called once per a process.
1659 * 0 on success, a negative errno value otherwise and rte_errno is set.
1662 mlx5_init_once(void)
1664 struct mlx5_shared_data *sd;
1665 struct mlx5_local_data *ld = &mlx5_local_data;
1668 if (mlx5_init_shared_data())
1670 sd = mlx5_shared_data;
1672 rte_spinlock_lock(&sd->lock);
1673 switch (rte_eal_process_type()) {
1674 case RTE_PROC_PRIMARY:
1677 LIST_INIT(&sd->mem_event_cb_list);
1678 rte_rwlock_init(&sd->mem_event_rwlock);
1679 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1680 mlx5_mr_mem_event_cb, NULL);
1681 ret = mlx5_mp_init_primary();
1684 sd->init_done = true;
1686 case RTE_PROC_SECONDARY:
1689 ret = mlx5_mp_init_secondary();
1692 ++sd->secondary_cnt;
1693 ld->init_done = true;
1699 rte_spinlock_unlock(&sd->lock);
1704 * Configures the minimal amount of data to inline into WQE
1705 * while sending packets.
1707 * - the txq_inline_min has the maximal priority, if this
1708 * key is specified in devargs
1709 * - if DevX is enabled the inline mode is queried from the
1710 * device (HCA attributes and NIC vport context if needed).
1711 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4LX
1712 * and none (0 bytes) for other NICs
1715 * Verbs device parameters (name, port, switch_info) to spawn.
1717 * Device configuration parameters.
1720 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1721 struct mlx5_dev_config *config)
1723 if (config->txq_inline_min != MLX5_ARG_UNSET) {
1724 /* Application defines size of inlined data explicitly. */
1725 switch (spawn->pci_dev->id.device_id) {
1726 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1727 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1728 if (config->txq_inline_min <
1729 (int)MLX5_INLINE_HSIZE_L2) {
1731 "txq_inline_mix aligned to minimal"
1732 " ConnectX-4 required value %d",
1733 (int)MLX5_INLINE_HSIZE_L2);
1734 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1740 if (config->hca_attr.eth_net_offloads) {
1741 /* We have DevX enabled, inline mode queried successfully. */
1742 switch (config->hca_attr.wqe_inline_mode) {
1743 case MLX5_CAP_INLINE_MODE_L2:
1744 /* outer L2 header must be inlined. */
1745 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1747 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1748 /* No inline data are required by NIC. */
1749 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1750 config->hw_vlan_insert =
1751 config->hca_attr.wqe_vlan_insert;
1752 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1754 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1755 /* inline mode is defined by NIC vport context. */
1756 if (!config->hca_attr.eth_virt)
1758 switch (config->hca_attr.vport_inline_mode) {
1759 case MLX5_INLINE_MODE_NONE:
1760 config->txq_inline_min =
1761 MLX5_INLINE_HSIZE_NONE;
1763 case MLX5_INLINE_MODE_L2:
1764 config->txq_inline_min =
1765 MLX5_INLINE_HSIZE_L2;
1767 case MLX5_INLINE_MODE_IP:
1768 config->txq_inline_min =
1769 MLX5_INLINE_HSIZE_L3;
1771 case MLX5_INLINE_MODE_TCP_UDP:
1772 config->txq_inline_min =
1773 MLX5_INLINE_HSIZE_L4;
1775 case MLX5_INLINE_MODE_INNER_L2:
1776 config->txq_inline_min =
1777 MLX5_INLINE_HSIZE_INNER_L2;
1779 case MLX5_INLINE_MODE_INNER_IP:
1780 config->txq_inline_min =
1781 MLX5_INLINE_HSIZE_INNER_L3;
1783 case MLX5_INLINE_MODE_INNER_TCP_UDP:
1784 config->txq_inline_min =
1785 MLX5_INLINE_HSIZE_INNER_L4;
1791 * We get here if we are unable to deduce
1792 * inline data size with DevX. Try PCI ID
1793 * to determine old NICs.
1795 switch (spawn->pci_dev->id.device_id) {
1796 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1797 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1798 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1799 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1800 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1801 config->hw_vlan_insert = 0;
1803 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1804 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1805 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1806 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1808 * These NICs support VLAN insertion from WQE and
1809 * report the wqe_vlan_insert flag. But there is the bug
1810 * and PFC control may be broken, so disable feature.
1812 config->hw_vlan_insert = 0;
1813 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1816 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1820 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1824 * Configures the metadata mask fields in the shared context.
1827 * Pointer to Ethernet device.
1830 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1832 struct mlx5_priv *priv = dev->data->dev_private;
1833 struct mlx5_ibv_shared *sh = priv->sh;
1834 uint32_t meta, mark, reg_c0;
1836 reg_c0 = ~priv->vport_meta_mask;
1837 switch (priv->config.dv_xmeta_en) {
1838 case MLX5_XMETA_MODE_LEGACY:
1840 mark = MLX5_FLOW_MARK_MASK;
1842 case MLX5_XMETA_MODE_META16:
1843 meta = reg_c0 >> rte_bsf32(reg_c0);
1844 mark = MLX5_FLOW_MARK_MASK;
1846 case MLX5_XMETA_MODE_META32:
1848 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1856 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1857 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1858 sh->dv_mark_mask, mark);
1860 sh->dv_mark_mask = mark;
1861 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1862 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1863 sh->dv_meta_mask, meta);
1865 sh->dv_meta_mask = meta;
1866 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1867 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1868 sh->dv_meta_mask, reg_c0);
1870 sh->dv_regc0_mask = reg_c0;
1871 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1872 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1873 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1874 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1878 * Allocate page of door-bells and register it using DevX API.
1881 * Pointer to Ethernet device.
1884 * Pointer to new page on success, NULL otherwise.
1886 static struct mlx5_devx_dbr_page *
1887 mlx5_alloc_dbr_page(struct rte_eth_dev *dev)
1889 struct mlx5_priv *priv = dev->data->dev_private;
1890 struct mlx5_devx_dbr_page *page;
1892 /* Allocate space for door-bell page and management data. */
1893 page = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_devx_dbr_page),
1894 RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1896 DRV_LOG(ERR, "port %u cannot allocate dbr page",
1897 dev->data->port_id);
1900 /* Register allocated memory. */
1901 page->umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, page->dbrs,
1902 MLX5_DBR_PAGE_SIZE, 0);
1904 DRV_LOG(ERR, "port %u cannot umem reg dbr page",
1905 dev->data->port_id);
1913 * Find the next available door-bell, allocate new page if needed.
1916 * Pointer to Ethernet device.
1917 * @param [out] dbr_page
1918 * Door-bell page containing the page data.
1921 * Door-bell address offset on success, a negative error value otherwise.
1924 mlx5_get_dbr(struct rte_eth_dev *dev, struct mlx5_devx_dbr_page **dbr_page)
1926 struct mlx5_priv *priv = dev->data->dev_private;
1927 struct mlx5_devx_dbr_page *page = NULL;
1930 LIST_FOREACH(page, &priv->dbrpgs, next)
1931 if (page->dbr_count < MLX5_DBR_PER_PAGE)
1933 if (!page) { /* No page with free door-bell exists. */
1934 page = mlx5_alloc_dbr_page(dev);
1935 if (!page) /* Failed to allocate new page. */
1937 LIST_INSERT_HEAD(&priv->dbrpgs, page, next);
1939 /* Loop to find bitmap part with clear bit. */
1941 i < MLX5_DBR_BITMAP_SIZE && page->dbr_bitmap[i] == UINT64_MAX;
1944 /* Find the first clear bit. */
1945 j = rte_bsf64(~page->dbr_bitmap[i]);
1946 assert(i < (MLX5_DBR_PER_PAGE / 64));
1947 page->dbr_bitmap[i] |= (1 << j);
1950 return (((i * 64) + j) * sizeof(uint64_t));
1954 * Release a door-bell record.
1957 * Pointer to Ethernet device.
1958 * @param [in] umem_id
1959 * UMEM ID of page containing the door-bell record to release.
1960 * @param [in] offset
1961 * Offset of door-bell record in page.
1964 * 0 on success, a negative error value otherwise.
1967 mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id, uint64_t offset)
1969 struct mlx5_priv *priv = dev->data->dev_private;
1970 struct mlx5_devx_dbr_page *page = NULL;
1973 LIST_FOREACH(page, &priv->dbrpgs, next)
1974 /* Find the page this address belongs to. */
1975 if (page->umem->umem_id == umem_id)
1980 if (!page->dbr_count) {
1981 /* Page not used, free it and remove from list. */
1982 LIST_REMOVE(page, next);
1984 ret = -mlx5_glue->devx_umem_dereg(page->umem);
1987 /* Mark in bitmap that this door-bell is not in use. */
1988 offset /= MLX5_DBR_SIZE;
1989 int i = offset / 64;
1990 int j = offset % 64;
1992 page->dbr_bitmap[i] &= ~(1 << j);
1998 * Check sibling device configurations.
2000 * Sibling devices sharing the Infiniband device context
2001 * should have compatible configurations. This regards
2002 * representors and bonding slaves.
2005 * Private device descriptor.
2007 * Configuration of the device is going to be created.
2010 * 0 on success, EINVAL otherwise
2013 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2014 struct mlx5_dev_config *config)
2016 struct mlx5_ibv_shared *sh = priv->sh;
2017 struct mlx5_dev_config *sh_conf = NULL;
2021 /* Nothing to compare for the single/first device. */
2022 if (sh->refcnt == 1)
2024 /* Find the device with shared context. */
2025 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2026 struct mlx5_priv *opriv =
2027 rte_eth_devices[port_id].data->dev_private;
2029 if (opriv && opriv != priv && opriv->sh == sh) {
2030 sh_conf = &opriv->config;
2036 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2037 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2038 " for shared %s context", sh->ibdev_name);
2042 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2043 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2044 " for shared %s context", sh->ibdev_name);
2051 * Spawn an Ethernet device from Verbs information.
2054 * Backing DPDK device.
2056 * Verbs device parameters (name, port, switch_info) to spawn.
2058 * Device configuration parameters.
2061 * A valid Ethernet device object on success, NULL otherwise and rte_errno
2062 * is set. The following errors are defined:
2064 * EBUSY: device is not supposed to be spawned.
2065 * EEXIST: device is already spawned
2067 static struct rte_eth_dev *
2068 mlx5_dev_spawn(struct rte_device *dpdk_dev,
2069 struct mlx5_dev_spawn_data *spawn,
2070 struct mlx5_dev_config config)
2072 const struct mlx5_switch_info *switch_info = &spawn->info;
2073 struct mlx5_ibv_shared *sh = NULL;
2074 struct ibv_port_attr port_attr;
2075 struct mlx5dv_context dv_attr = { .comp_mask = 0 };
2076 struct rte_eth_dev *eth_dev = NULL;
2077 struct mlx5_priv *priv = NULL;
2079 unsigned int hw_padding = 0;
2081 unsigned int cqe_comp;
2082 unsigned int cqe_pad = 0;
2083 unsigned int tunnel_en = 0;
2084 unsigned int mpls_en = 0;
2085 unsigned int swp = 0;
2086 unsigned int mprq = 0;
2087 unsigned int mprq_min_stride_size_n = 0;
2088 unsigned int mprq_max_stride_size_n = 0;
2089 unsigned int mprq_min_stride_num_n = 0;
2090 unsigned int mprq_max_stride_num_n = 0;
2091 struct rte_ether_addr mac;
2092 char name[RTE_ETH_NAME_MAX_LEN];
2093 int own_domain_id = 0;
2096 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
2097 struct mlx5dv_devx_port devx_port = { .comp_mask = 0 };
2100 /* Determine if this port representor is supposed to be spawned. */
2101 if (switch_info->representor && dpdk_dev->devargs) {
2102 struct rte_eth_devargs eth_da;
2104 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, ð_da);
2107 DRV_LOG(ERR, "failed to process device arguments: %s",
2108 strerror(rte_errno));
2111 for (i = 0; i < eth_da.nb_representor_ports; ++i)
2112 if (eth_da.representor_ports[i] ==
2113 (uint16_t)switch_info->port_name)
2115 if (i == eth_da.nb_representor_ports) {
2120 /* Build device name. */
2121 if (spawn->pf_bond < 0) {
2122 /* Single device. */
2123 if (!switch_info->representor)
2124 strlcpy(name, dpdk_dev->name, sizeof(name));
2126 snprintf(name, sizeof(name), "%s_representor_%u",
2127 dpdk_dev->name, switch_info->port_name);
2129 /* Bonding device. */
2130 if (!switch_info->representor)
2131 snprintf(name, sizeof(name), "%s_%s",
2132 dpdk_dev->name, spawn->ibv_dev->name);
2134 snprintf(name, sizeof(name), "%s_%s_representor_%u",
2135 dpdk_dev->name, spawn->ibv_dev->name,
2136 switch_info->port_name);
2138 /* check if the device is already spawned */
2139 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
2143 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
2144 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
2145 eth_dev = rte_eth_dev_attach_secondary(name);
2146 if (eth_dev == NULL) {
2147 DRV_LOG(ERR, "can not attach rte ethdev");
2151 eth_dev->device = dpdk_dev;
2152 eth_dev->dev_ops = &mlx5_dev_sec_ops;
2153 err = mlx5_proc_priv_init(eth_dev);
2156 /* Receive command fd from primary process */
2157 err = mlx5_mp_req_verbs_cmd_fd(eth_dev);
2160 /* Remap UAR for Tx queues. */
2161 err = mlx5_tx_uar_init_secondary(eth_dev, err);
2165 * Ethdev pointer is still required as input since
2166 * the primary device is not accessible from the
2167 * secondary process.
2169 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev);
2170 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev);
2174 * Some parameters ("tx_db_nc" in particularly) are needed in
2175 * advance to create dv/verbs device context. We proceed the
2176 * devargs here to get ones, and later proceed devargs again
2177 * to override some hardware settings.
2179 err = mlx5_args(&config, dpdk_dev->devargs);
2182 DRV_LOG(ERR, "failed to process device arguments: %s",
2183 strerror(rte_errno));
2186 sh = mlx5_alloc_shared_ibctx(spawn, &config);
2189 config.devx = sh->devx;
2190 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR
2191 config.dest_tir = 1;
2193 #ifdef HAVE_IBV_MLX5_MOD_SWP
2194 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
2197 * Multi-packet send is supported by ConnectX-4 Lx PF as well
2198 * as all ConnectX-5 devices.
2200 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2201 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
2203 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
2204 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
2206 mlx5_glue->dv_query_device(sh->ctx, &dv_attr);
2207 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
2208 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
2209 DRV_LOG(DEBUG, "enhanced MPW is supported");
2210 mps = MLX5_MPW_ENHANCED;
2212 DRV_LOG(DEBUG, "MPW is supported");
2216 DRV_LOG(DEBUG, "MPW isn't supported");
2217 mps = MLX5_MPW_DISABLED;
2219 #ifdef HAVE_IBV_MLX5_MOD_SWP
2220 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
2221 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
2222 DRV_LOG(DEBUG, "SWP support: %u", swp);
2225 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
2226 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
2227 struct mlx5dv_striding_rq_caps mprq_caps =
2228 dv_attr.striding_rq_caps;
2230 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
2231 mprq_caps.min_single_stride_log_num_of_bytes);
2232 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
2233 mprq_caps.max_single_stride_log_num_of_bytes);
2234 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
2235 mprq_caps.min_single_wqe_log_num_of_strides);
2236 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
2237 mprq_caps.max_single_wqe_log_num_of_strides);
2238 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
2239 mprq_caps.supported_qpts);
2240 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
2242 mprq_min_stride_size_n =
2243 mprq_caps.min_single_stride_log_num_of_bytes;
2244 mprq_max_stride_size_n =
2245 mprq_caps.max_single_stride_log_num_of_bytes;
2246 mprq_min_stride_num_n =
2247 mprq_caps.min_single_wqe_log_num_of_strides;
2248 mprq_max_stride_num_n =
2249 mprq_caps.max_single_wqe_log_num_of_strides;
2250 config.mprq.stride_num_n = RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
2251 mprq_min_stride_num_n);
2254 if (RTE_CACHE_LINE_SIZE == 128 &&
2255 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
2259 config.cqe_comp = cqe_comp;
2260 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
2261 /* Whether device supports 128B Rx CQE padding. */
2262 cqe_pad = RTE_CACHE_LINE_SIZE == 128 &&
2263 (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD);
2265 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2266 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
2267 tunnel_en = ((dv_attr.tunnel_offloads_caps &
2268 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
2269 (dv_attr.tunnel_offloads_caps &
2270 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) &&
2271 (dv_attr.tunnel_offloads_caps &
2272 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE));
2274 DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
2275 tunnel_en ? "" : "not ");
2278 "tunnel offloading disabled due to old OFED/rdma-core version");
2280 config.tunnel_en = tunnel_en;
2281 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
2282 mpls_en = ((dv_attr.tunnel_offloads_caps &
2283 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
2284 (dv_attr.tunnel_offloads_caps &
2285 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
2286 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
2287 mpls_en ? "" : "not ");
2289 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
2290 " old OFED/rdma-core version or firmware configuration");
2292 config.mpls_en = mpls_en;
2293 /* Check port status. */
2294 err = mlx5_glue->query_port(sh->ctx, spawn->ibv_port, &port_attr);
2296 DRV_LOG(ERR, "port query failed: %s", strerror(err));
2299 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
2300 DRV_LOG(ERR, "port is not configured in Ethernet mode");
2304 if (port_attr.state != IBV_PORT_ACTIVE)
2305 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)",
2306 mlx5_glue->port_state_str(port_attr.state),
2308 /* Allocate private eth device data. */
2309 priv = rte_zmalloc("ethdev private structure",
2311 RTE_CACHE_LINE_SIZE);
2313 DRV_LOG(ERR, "priv allocation failure");
2318 priv->ibv_port = spawn->ibv_port;
2319 priv->pci_dev = spawn->pci_dev;
2320 priv->mtu = RTE_ETHER_MTU;
2322 /* Initialize UAR access locks for 32bit implementations. */
2323 rte_spinlock_init(&priv->uar_lock_cq);
2324 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
2325 rte_spinlock_init(&priv->uar_lock[i]);
2327 /* Some internal functions rely on Netlink sockets, open them now. */
2328 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA);
2329 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE);
2331 priv->representor = !!switch_info->representor;
2332 priv->master = !!switch_info->master;
2333 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
2334 priv->vport_meta_tag = 0;
2335 priv->vport_meta_mask = 0;
2336 priv->pf_bond = spawn->pf_bond;
2337 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
2339 * The DevX port query API is implemented. E-Switch may use
2340 * either vport or reg_c[0] metadata register to match on
2341 * vport index. The engaged part of metadata register is
2344 if (switch_info->representor || switch_info->master) {
2345 devx_port.comp_mask = MLX5DV_DEVX_PORT_VPORT |
2346 MLX5DV_DEVX_PORT_MATCH_REG_C_0;
2347 err = mlx5_glue->devx_port_query(sh->ctx, spawn->ibv_port,
2351 "can't query devx port %d on device %s",
2352 spawn->ibv_port, spawn->ibv_dev->name);
2353 devx_port.comp_mask = 0;
2356 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_MATCH_REG_C_0) {
2357 priv->vport_meta_tag = devx_port.reg_c_0.value;
2358 priv->vport_meta_mask = devx_port.reg_c_0.mask;
2359 if (!priv->vport_meta_mask) {
2360 DRV_LOG(ERR, "vport zero mask for port %d"
2361 " on bonding device %s",
2362 spawn->ibv_port, spawn->ibv_dev->name);
2366 if (priv->vport_meta_tag & ~priv->vport_meta_mask) {
2367 DRV_LOG(ERR, "invalid vport tag for port %d"
2368 " on bonding device %s",
2369 spawn->ibv_port, spawn->ibv_dev->name);
2374 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_VPORT) {
2375 priv->vport_id = devx_port.vport_num;
2376 } else if (spawn->pf_bond >= 0) {
2377 DRV_LOG(ERR, "can't deduce vport index for port %d"
2378 " on bonding device %s",
2379 spawn->ibv_port, spawn->ibv_dev->name);
2383 /* Suppose vport index in compatible way. */
2384 priv->vport_id = switch_info->representor ?
2385 switch_info->port_name + 1 : -1;
2389 * Kernel/rdma_core support single E-Switch per PF configurations
2390 * only and vport_id field contains the vport index for
2391 * associated VF, which is deduced from representor port name.
2392 * For example, let's have the IB device port 10, it has
2393 * attached network device eth0, which has port name attribute
2394 * pf0vf2, we can deduce the VF number as 2, and set vport index
2395 * as 3 (2+1). This assigning schema should be changed if the
2396 * multiple E-Switch instances per PF configurations or/and PCI
2397 * subfunctions are added.
2399 priv->vport_id = switch_info->representor ?
2400 switch_info->port_name + 1 : -1;
2402 /* representor_id field keeps the unmodified VF index. */
2403 priv->representor_id = switch_info->representor ?
2404 switch_info->port_name : -1;
2406 * Look for sibling devices in order to reuse their switch domain
2407 * if any, otherwise allocate one.
2409 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2410 const struct mlx5_priv *opriv =
2411 rte_eth_devices[port_id].data->dev_private;
2414 opriv->sh != priv->sh ||
2416 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
2418 priv->domain_id = opriv->domain_id;
2421 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
2422 err = rte_eth_switch_domain_alloc(&priv->domain_id);
2425 DRV_LOG(ERR, "unable to allocate switch domain: %s",
2426 strerror(rte_errno));
2431 /* Override some values set by hardware configuration. */
2432 mlx5_args(&config, dpdk_dev->devargs);
2433 err = mlx5_dev_check_sibling_config(priv, &config);
2436 config.hw_csum = !!(sh->device_attr.device_cap_flags_ex &
2437 IBV_DEVICE_RAW_IP_CSUM);
2438 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
2439 (config.hw_csum ? "" : "not "));
2440 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \
2441 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
2442 DRV_LOG(DEBUG, "counters are not supported");
2444 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR)
2445 if (config.dv_flow_en) {
2446 DRV_LOG(WARNING, "DV flow is not supported");
2447 config.dv_flow_en = 0;
2450 config.ind_table_max_size =
2451 sh->device_attr.rss_caps.max_rwq_indirection_table_size;
2453 * Remove this check once DPDK supports larger/variable
2454 * indirection tables.
2456 if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
2457 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
2458 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
2459 config.ind_table_max_size);
2460 config.hw_vlan_strip = !!(sh->device_attr.raw_packet_caps &
2461 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
2462 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
2463 (config.hw_vlan_strip ? "" : "not "));
2464 config.hw_fcs_strip = !!(sh->device_attr.raw_packet_caps &
2465 IBV_RAW_PACKET_CAP_SCATTER_FCS);
2466 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
2467 (config.hw_fcs_strip ? "" : "not "));
2468 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
2469 hw_padding = !!sh->device_attr.rx_pad_end_addr_align;
2470 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
2471 hw_padding = !!(sh->device_attr.device_cap_flags_ex &
2472 IBV_DEVICE_PCI_WRITE_END_PADDING);
2474 if (config.hw_padding && !hw_padding) {
2475 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
2476 config.hw_padding = 0;
2477 } else if (config.hw_padding) {
2478 DRV_LOG(DEBUG, "Rx end alignment padding is enabled");
2480 config.tso = (sh->device_attr.tso_caps.max_tso > 0 &&
2481 (sh->device_attr.tso_caps.supported_qpts &
2482 (1 << IBV_QPT_RAW_PACKET)));
2484 config.tso_max_payload_sz = sh->device_attr.tso_caps.max_tso;
2486 * MPW is disabled by default, while the Enhanced MPW is enabled
2489 if (config.mps == MLX5_ARG_UNSET)
2490 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED :
2493 config.mps = config.mps ? mps : MLX5_MPW_DISABLED;
2494 DRV_LOG(INFO, "%sMPS is %s",
2495 config.mps == MLX5_MPW_ENHANCED ? "enhanced " :
2496 config.mps == MLX5_MPW ? "legacy " : "",
2497 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
2498 if (config.cqe_comp && !cqe_comp) {
2499 DRV_LOG(WARNING, "Rx CQE compression isn't supported");
2500 config.cqe_comp = 0;
2502 if (config.cqe_pad && !cqe_pad) {
2503 DRV_LOG(WARNING, "Rx CQE padding isn't supported");
2505 } else if (config.cqe_pad) {
2506 DRV_LOG(INFO, "Rx CQE padding is enabled");
2509 priv->counter_fallback = 0;
2510 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config.hca_attr);
2515 if (!config.hca_attr.flow_counters_dump)
2516 priv->counter_fallback = 1;
2517 #ifndef HAVE_IBV_DEVX_ASYNC
2518 priv->counter_fallback = 1;
2520 if (priv->counter_fallback)
2521 DRV_LOG(INFO, "Use fall-back DV counter management");
2522 /* Check for LRO support. */
2523 if (config.dest_tir && config.hca_attr.lro_cap &&
2524 config.dv_flow_en) {
2525 /* TBD check tunnel lro caps. */
2526 config.lro.supported = config.hca_attr.lro_cap;
2527 DRV_LOG(DEBUG, "Device supports LRO");
2529 * If LRO timeout is not configured by application,
2530 * use the minimal supported value.
2532 if (!config.lro.timeout)
2533 config.lro.timeout =
2534 config.hca_attr.lro_timer_supported_periods[0];
2535 DRV_LOG(DEBUG, "LRO session timeout set to %d usec",
2536 config.lro.timeout);
2538 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER)
2539 if (config.hca_attr.qos.sup && config.hca_attr.qos.srtcm_sup &&
2540 config.dv_flow_en) {
2541 uint8_t reg_c_mask =
2542 config.hca_attr.qos.flow_meter_reg_c_ids;
2544 * Meter needs two REG_C's for color match and pre-sfx
2545 * flow match. Here get the REG_C for color match.
2546 * REG_C_0 and REG_C_1 is reserved for metadata feature.
2549 if (__builtin_popcount(reg_c_mask) < 1) {
2551 DRV_LOG(WARNING, "No available register for"
2554 priv->mtr_color_reg = ffs(reg_c_mask) - 1 +
2557 priv->mtr_reg_share =
2558 config.hca_attr.qos.flow_meter_reg_share;
2559 DRV_LOG(DEBUG, "The REG_C meter uses is %d",
2560 priv->mtr_color_reg);
2565 if (config.mprq.enabled && mprq) {
2566 if (config.mprq.stride_num_n > mprq_max_stride_num_n ||
2567 config.mprq.stride_num_n < mprq_min_stride_num_n) {
2568 config.mprq.stride_num_n =
2569 RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
2570 mprq_min_stride_num_n);
2572 "the number of strides"
2573 " for Multi-Packet RQ is out of range,"
2574 " setting default value (%u)",
2575 1 << config.mprq.stride_num_n);
2577 config.mprq.min_stride_size_n = mprq_min_stride_size_n;
2578 config.mprq.max_stride_size_n = mprq_max_stride_size_n;
2579 } else if (config.mprq.enabled && !mprq) {
2580 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
2581 config.mprq.enabled = 0;
2583 if (config.max_dump_files_num == 0)
2584 config.max_dump_files_num = 128;
2585 eth_dev = rte_eth_dev_allocate(name);
2586 if (eth_dev == NULL) {
2587 DRV_LOG(ERR, "can not allocate rte ethdev");
2591 /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */
2592 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2593 if (priv->representor) {
2594 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
2595 eth_dev->data->representor_id = priv->representor_id;
2598 * Store associated network device interface index. This index
2599 * is permanent throughout the lifetime of device. So, we may store
2600 * the ifindex here and use the cached value further.
2602 assert(spawn->ifindex);
2603 priv->if_index = spawn->ifindex;
2604 eth_dev->data->dev_private = priv;
2605 priv->dev_data = eth_dev->data;
2606 eth_dev->data->mac_addrs = priv->mac;
2607 eth_dev->device = dpdk_dev;
2608 /* Configure the first MAC address by default. */
2609 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
2611 "port %u cannot get MAC address, is mlx5_en"
2612 " loaded? (errno: %s)",
2613 eth_dev->data->port_id, strerror(rte_errno));
2618 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
2619 eth_dev->data->port_id,
2620 mac.addr_bytes[0], mac.addr_bytes[1],
2621 mac.addr_bytes[2], mac.addr_bytes[3],
2622 mac.addr_bytes[4], mac.addr_bytes[5]);
2625 char ifname[IF_NAMESIZE];
2627 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
2628 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
2629 eth_dev->data->port_id, ifname);
2631 DRV_LOG(DEBUG, "port %u ifname is unknown",
2632 eth_dev->data->port_id);
2635 /* Get actual MTU if possible. */
2636 err = mlx5_get_mtu(eth_dev, &priv->mtu);
2641 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
2643 /* Initialize burst functions to prevent crashes before link-up. */
2644 eth_dev->rx_pkt_burst = removed_rx_burst;
2645 eth_dev->tx_pkt_burst = removed_tx_burst;
2646 eth_dev->dev_ops = &mlx5_dev_ops;
2647 /* Register MAC address. */
2648 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
2649 if (config.vf && config.vf_nl_en)
2650 mlx5_nl_mac_addr_sync(eth_dev);
2651 TAILQ_INIT(&priv->flows);
2652 TAILQ_INIT(&priv->ctrl_flows);
2653 TAILQ_INIT(&priv->flow_meters);
2654 TAILQ_INIT(&priv->flow_meter_profiles);
2655 /* Hint libmlx5 to use PMD allocator for data plane resources */
2656 struct mlx5dv_ctx_allocators alctr = {
2657 .alloc = &mlx5_alloc_verbs_buf,
2658 .free = &mlx5_free_verbs_buf,
2661 mlx5_glue->dv_set_context_attr(sh->ctx,
2662 MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
2663 (void *)((uintptr_t)&alctr));
2664 /* Bring Ethernet device up. */
2665 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
2666 eth_dev->data->port_id);
2667 mlx5_set_link_up(eth_dev);
2669 * Even though the interrupt handler is not installed yet,
2670 * interrupts will still trigger on the async_fd from
2671 * Verbs context returned by ibv_open_device().
2673 mlx5_link_update(eth_dev, 0);
2674 #ifdef HAVE_MLX5DV_DR_ESWITCH
2675 if (!(config.hca_attr.eswitch_manager && config.dv_flow_en &&
2676 (switch_info->representor || switch_info->master)))
2677 config.dv_esw_en = 0;
2679 config.dv_esw_en = 0;
2681 /* Detect minimal data bytes to inline. */
2682 mlx5_set_min_inline(spawn, &config);
2683 /* Store device configuration on private structure. */
2684 priv->config = config;
2685 /* Create context for virtual machine VLAN workaround. */
2686 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex);
2687 if (config.dv_flow_en) {
2688 err = mlx5_alloc_shared_dr(priv);
2692 * RSS id is shared with meter flow id. Meter flow id can only
2693 * use the 24 MSB of the register.
2695 priv->qrss_id_pool = mlx5_flow_id_pool_alloc(UINT32_MAX >>
2696 MLX5_MTR_COLOR_BITS);
2697 if (!priv->qrss_id_pool) {
2698 DRV_LOG(ERR, "can't create flow id pool");
2703 /* Supported Verbs flow priority number detection. */
2704 err = mlx5_flow_discover_priorities(eth_dev);
2709 priv->config.flow_prio = err;
2710 if (!priv->config.dv_esw_en &&
2711 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2712 DRV_LOG(WARNING, "metadata mode %u is not supported "
2713 "(no E-Switch)", priv->config.dv_xmeta_en);
2714 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY;
2716 mlx5_set_metadata_mask(eth_dev);
2717 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
2718 !priv->sh->dv_regc0_mask) {
2719 DRV_LOG(ERR, "metadata mode %u is not supported "
2720 "(no metadata reg_c[0] is available)",
2721 priv->config.dv_xmeta_en);
2725 /* Query availibility of metadata reg_c's. */
2726 err = mlx5_flow_discover_mreg_c(eth_dev);
2731 if (!mlx5_flow_ext_mreg_supported(eth_dev)) {
2733 "port %u extensive metadata register is not supported",
2734 eth_dev->data->port_id);
2735 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2736 DRV_LOG(ERR, "metadata mode %u is not supported "
2737 "(no metadata registers available)",
2738 priv->config.dv_xmeta_en);
2743 if (priv->config.dv_flow_en &&
2744 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
2745 mlx5_flow_ext_mreg_supported(eth_dev) &&
2746 priv->sh->dv_regc0_mask) {
2747 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME,
2748 MLX5_FLOW_MREG_HTABLE_SZ);
2749 if (!priv->mreg_cp_tbl) {
2757 if (priv->mreg_cp_tbl)
2758 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
2760 mlx5_free_shared_dr(priv);
2761 if (priv->nl_socket_route >= 0)
2762 close(priv->nl_socket_route);
2763 if (priv->nl_socket_rdma >= 0)
2764 close(priv->nl_socket_rdma);
2765 if (priv->vmwa_context)
2766 mlx5_vlan_vmwa_exit(priv->vmwa_context);
2767 if (priv->qrss_id_pool)
2768 mlx5_flow_id_pool_release(priv->qrss_id_pool);
2770 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
2772 if (eth_dev != NULL)
2773 eth_dev->data->dev_private = NULL;
2775 if (eth_dev != NULL) {
2776 /* mac_addrs must not be freed alone because part of dev_private */
2777 eth_dev->data->mac_addrs = NULL;
2778 rte_eth_dev_release_port(eth_dev);
2781 mlx5_free_shared_ibctx(sh);
2788 * Comparison callback to sort device data.
2790 * This is meant to be used with qsort().
2793 * Pointer to pointer to first data object.
2795 * Pointer to pointer to second data object.
2798 * 0 if both objects are equal, less than 0 if the first argument is less
2799 * than the second, greater than 0 otherwise.
2802 mlx5_dev_spawn_data_cmp(const void *a, const void *b)
2804 const struct mlx5_switch_info *si_a =
2805 &((const struct mlx5_dev_spawn_data *)a)->info;
2806 const struct mlx5_switch_info *si_b =
2807 &((const struct mlx5_dev_spawn_data *)b)->info;
2810 /* Master device first. */
2811 ret = si_b->master - si_a->master;
2814 /* Then representor devices. */
2815 ret = si_b->representor - si_a->representor;
2818 /* Unidentified devices come last in no specific order. */
2819 if (!si_a->representor)
2821 /* Order representors by name. */
2822 return si_a->port_name - si_b->port_name;
2826 * Match PCI information for possible slaves of bonding device.
2828 * @param[in] ibv_dev
2829 * Pointer to Infiniband device structure.
2830 * @param[in] pci_dev
2831 * Pointer to PCI device structure to match PCI address.
2832 * @param[in] nl_rdma
2833 * Netlink RDMA group socket handle.
2836 * negative value if no bonding device found, otherwise
2837 * positive index of slave PF in bonding.
2840 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev,
2841 const struct rte_pci_device *pci_dev,
2844 char ifname[IF_NAMESIZE + 1];
2845 unsigned int ifindex;
2851 * Try to get master device name. If something goes
2852 * wrong suppose the lack of kernel support and no
2857 if (!strstr(ibv_dev->name, "bond"))
2859 np = mlx5_nl_portnum(nl_rdma, ibv_dev->name);
2863 * The Master device might not be on the predefined
2864 * port (not on port index 1, it is not garanted),
2865 * we have to scan all Infiniband device port and
2868 for (i = 1; i <= np; ++i) {
2869 /* Check whether Infiniband port is populated. */
2870 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i);
2873 if (!if_indextoname(ifindex, ifname))
2875 /* Try to read bonding slave names from sysfs. */
2877 "/sys/class/net/%s/master/bonding/slaves", ifname);
2878 file = fopen(slaves, "r");
2884 /* Use safe format to check maximal buffer length. */
2885 assert(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE);
2886 while (fscanf(file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) {
2887 char tmp_str[IF_NAMESIZE + 32];
2888 struct rte_pci_addr pci_addr;
2889 struct mlx5_switch_info info;
2891 /* Process slave interface names in the loop. */
2892 snprintf(tmp_str, sizeof(tmp_str),
2893 "/sys/class/net/%s", ifname);
2894 if (mlx5_dev_to_pci_addr(tmp_str, &pci_addr)) {
2895 DRV_LOG(WARNING, "can not get PCI address"
2896 " for netdev \"%s\"", ifname);
2899 if (pci_dev->addr.domain != pci_addr.domain ||
2900 pci_dev->addr.bus != pci_addr.bus ||
2901 pci_dev->addr.devid != pci_addr.devid ||
2902 pci_dev->addr.function != pci_addr.function)
2904 /* Slave interface PCI address match found. */
2906 snprintf(tmp_str, sizeof(tmp_str),
2907 "/sys/class/net/%s/phys_port_name", ifname);
2908 file = fopen(tmp_str, "rb");
2911 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET;
2912 if (fscanf(file, "%32s", tmp_str) == 1)
2913 mlx5_translate_port_name(tmp_str, &info);
2914 if (info.name_type == MLX5_PHYS_PORT_NAME_TYPE_LEGACY ||
2915 info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK)
2916 pf = info.port_name;
2925 * DPDK callback to register a PCI device.
2927 * This function spawns Ethernet devices out of a given PCI device.
2929 * @param[in] pci_drv
2930 * PCI driver structure (mlx5_driver).
2931 * @param[in] pci_dev
2932 * PCI device information.
2935 * 0 on success, a negative errno value otherwise and rte_errno is set.
2938 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2939 struct rte_pci_device *pci_dev)
2941 struct ibv_device **ibv_list;
2943 * Number of found IB Devices matching with requested PCI BDF.
2944 * nd != 1 means there are multiple IB devices over the same
2945 * PCI device and we have representors and master.
2947 unsigned int nd = 0;
2949 * Number of found IB device Ports. nd = 1 and np = 1..n means
2950 * we have the single multiport IB device, and there may be
2951 * representors attached to some of found ports.
2953 unsigned int np = 0;
2955 * Number of DPDK ethernet devices to Spawn - either over
2956 * multiple IB devices or multiple ports of single IB device.
2957 * Actually this is the number of iterations to spawn.
2959 unsigned int ns = 0;
2962 * < 0 - no bonding device (single one)
2963 * >= 0 - bonding device (value is slave PF index)
2966 struct mlx5_dev_spawn_data *list = NULL;
2967 struct mlx5_dev_config dev_config;
2970 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
2971 mlx5_pmd_socket_init();
2972 ret = mlx5_init_once();
2974 DRV_LOG(ERR, "unable to init PMD global data: %s",
2975 strerror(rte_errno));
2978 assert(pci_drv == &mlx5_driver);
2980 ibv_list = mlx5_glue->get_device_list(&ret);
2982 rte_errno = errno ? errno : ENOSYS;
2983 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?");
2987 * First scan the list of all Infiniband devices to find
2988 * matching ones, gathering into the list.
2990 struct ibv_device *ibv_match[ret + 1];
2991 int nl_route = mlx5_nl_init(NETLINK_ROUTE);
2992 int nl_rdma = mlx5_nl_init(NETLINK_RDMA);
2996 struct rte_pci_addr pci_addr;
2998 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name);
2999 bd = mlx5_device_bond_pci_match
3000 (ibv_list[ret], pci_dev, nl_rdma);
3003 * Bonding device detected. Only one match is allowed,
3004 * the bonding is supported over multi-port IB device,
3005 * there should be no matches on representor PCI
3006 * functions or non VF LAG bonding devices with
3007 * specified address.
3011 "multiple PCI match on bonding device"
3012 "\"%s\" found", ibv_list[ret]->name);
3017 DRV_LOG(INFO, "PCI information matches for"
3018 " slave %d bonding device \"%s\"",
3019 bd, ibv_list[ret]->name);
3020 ibv_match[nd++] = ibv_list[ret];
3023 if (mlx5_dev_to_pci_addr
3024 (ibv_list[ret]->ibdev_path, &pci_addr))
3026 if (pci_dev->addr.domain != pci_addr.domain ||
3027 pci_dev->addr.bus != pci_addr.bus ||
3028 pci_dev->addr.devid != pci_addr.devid ||
3029 pci_dev->addr.function != pci_addr.function)
3031 DRV_LOG(INFO, "PCI information matches for device \"%s\"",
3032 ibv_list[ret]->name);
3033 ibv_match[nd++] = ibv_list[ret];
3035 ibv_match[nd] = NULL;
3037 /* No device matches, just complain and bail out. */
3039 "no Verbs device matches PCI device " PCI_PRI_FMT ","
3040 " are kernel drivers loaded?",
3041 pci_dev->addr.domain, pci_dev->addr.bus,
3042 pci_dev->addr.devid, pci_dev->addr.function);
3049 * Found single matching device may have multiple ports.
3050 * Each port may be representor, we have to check the port
3051 * number and check the representors existence.
3054 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name);
3056 DRV_LOG(WARNING, "can not get IB device \"%s\""
3057 " ports number", ibv_match[0]->name);
3058 if (bd >= 0 && !np) {
3059 DRV_LOG(ERR, "can not get ports"
3060 " for bonding device");
3066 #ifndef HAVE_MLX5DV_DR_DEVX_PORT
3069 * This may happen if there is VF LAG kernel support and
3070 * application is compiled with older rdma_core library.
3073 "No kernel/verbs support for VF LAG bonding found.");
3074 rte_errno = ENOTSUP;
3080 * Now we can determine the maximal
3081 * amount of devices to be spawned.
3083 list = rte_zmalloc("device spawn data",
3084 sizeof(struct mlx5_dev_spawn_data) *
3086 RTE_CACHE_LINE_SIZE);
3088 DRV_LOG(ERR, "spawn data array allocation failure");
3093 if (bd >= 0 || np > 1) {
3095 * Single IB device with multiple ports found,
3096 * it may be E-Switch master device and representors.
3097 * We have to perform identification trough the ports.
3099 assert(nl_rdma >= 0);
3103 for (i = 1; i <= np; ++i) {
3104 list[ns].max_port = np;
3105 list[ns].ibv_port = i;
3106 list[ns].ibv_dev = ibv_match[0];
3107 list[ns].eth_dev = NULL;
3108 list[ns].pci_dev = pci_dev;
3109 list[ns].pf_bond = bd;
3110 list[ns].ifindex = mlx5_nl_ifindex
3111 (nl_rdma, list[ns].ibv_dev->name, i);
3112 if (!list[ns].ifindex) {
3114 * No network interface index found for the
3115 * specified port, it means there is no
3116 * representor on this port. It's OK,
3117 * there can be disabled ports, for example
3118 * if sriov_numvfs < sriov_totalvfs.
3124 ret = mlx5_nl_switch_info
3128 if (ret || (!list[ns].info.representor &&
3129 !list[ns].info.master)) {
3131 * We failed to recognize representors with
3132 * Netlink, let's try to perform the task
3135 ret = mlx5_sysfs_switch_info
3139 if (!ret && bd >= 0) {
3140 switch (list[ns].info.name_type) {
3141 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK:
3142 if (list[ns].info.port_name == bd)
3145 case MLX5_PHYS_PORT_NAME_TYPE_PFVF:
3146 if (list[ns].info.pf_num == bd)
3154 if (!ret && (list[ns].info.representor ^
3155 list[ns].info.master))
3160 "unable to recognize master/representors"
3161 " on the IB device with multiple ports");
3168 * The existence of several matching entries (nd > 1) means
3169 * port representors have been instantiated. No existing Verbs
3170 * call nor sysfs entries can tell them apart, this can only
3171 * be done through Netlink calls assuming kernel drivers are
3172 * recent enough to support them.
3174 * In the event of identification failure through Netlink,
3175 * try again through sysfs, then:
3177 * 1. A single IB device matches (nd == 1) with single
3178 * port (np=0/1) and is not a representor, assume
3179 * no switch support.
3181 * 2. Otherwise no safe assumptions can be made;
3182 * complain louder and bail out.
3185 for (i = 0; i != nd; ++i) {
3186 memset(&list[ns].info, 0, sizeof(list[ns].info));
3187 list[ns].max_port = 1;
3188 list[ns].ibv_port = 1;
3189 list[ns].ibv_dev = ibv_match[i];
3190 list[ns].eth_dev = NULL;
3191 list[ns].pci_dev = pci_dev;
3192 list[ns].pf_bond = -1;
3193 list[ns].ifindex = 0;
3195 list[ns].ifindex = mlx5_nl_ifindex
3196 (nl_rdma, list[ns].ibv_dev->name, 1);
3197 if (!list[ns].ifindex) {
3198 char ifname[IF_NAMESIZE];
3201 * Netlink failed, it may happen with old
3202 * ib_core kernel driver (before 4.16).
3203 * We can assume there is old driver because
3204 * here we are processing single ports IB
3205 * devices. Let's try sysfs to retrieve
3206 * the ifindex. The method works for
3207 * master device only.
3211 * Multiple devices found, assume
3212 * representors, can not distinguish
3213 * master/representor and retrieve
3214 * ifindex via sysfs.
3218 ret = mlx5_get_master_ifname
3219 (ibv_match[i]->ibdev_path, &ifname);
3222 if_nametoindex(ifname);
3223 if (!list[ns].ifindex) {
3225 * No network interface index found
3226 * for the specified device, it means
3227 * there it is neither representor
3235 ret = mlx5_nl_switch_info
3239 if (ret || (!list[ns].info.representor &&
3240 !list[ns].info.master)) {
3242 * We failed to recognize representors with
3243 * Netlink, let's try to perform the task
3246 ret = mlx5_sysfs_switch_info
3250 if (!ret && (list[ns].info.representor ^
3251 list[ns].info.master)) {
3253 } else if ((nd == 1) &&
3254 !list[ns].info.representor &&
3255 !list[ns].info.master) {
3257 * Single IB device with
3258 * one physical port and
3259 * attached network device.
3260 * May be SRIOV is not enabled
3261 * or there is no representors.
3263 DRV_LOG(INFO, "no E-Switch support detected");
3270 "unable to recognize master/representors"
3271 " on the multiple IB devices");
3279 * Sort list to probe devices in natural order for users convenience
3280 * (i.e. master first, then representors from lowest to highest ID).
3282 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp);
3283 /* Default configuration. */
3284 dev_config = (struct mlx5_dev_config){
3286 .mps = MLX5_ARG_UNSET,
3287 .dbnc = MLX5_ARG_UNSET,
3289 .txq_inline_max = MLX5_ARG_UNSET,
3290 .txq_inline_min = MLX5_ARG_UNSET,
3291 .txq_inline_mpw = MLX5_ARG_UNSET,
3292 .txqs_inline = MLX5_ARG_UNSET,
3294 .mr_ext_memseg_en = 1,
3296 .enabled = 0, /* Disabled by default. */
3297 .stride_num_n = MLX5_MPRQ_STRIDE_NUM_N,
3298 .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
3299 .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
3304 /* Device specific configuration. */
3305 switch (pci_dev->id.device_id) {
3306 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
3307 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
3308 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
3309 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
3310 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF:
3311 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF:
3312 case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF:
3318 for (i = 0; i != ns; ++i) {
3321 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device,
3324 if (!list[i].eth_dev) {
3325 if (rte_errno != EBUSY && rte_errno != EEXIST)
3327 /* Device is disabled or already spawned. Ignore it. */
3330 restore = list[i].eth_dev->data->dev_flags;
3331 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev);
3332 /* Restore non-PCI flags cleared by the above call. */
3333 list[i].eth_dev->data->dev_flags |= restore;
3334 mlx5_dev_interrupt_handler_devx_install(list[i].eth_dev);
3335 rte_eth_dev_probing_finish(list[i].eth_dev);
3339 "probe of PCI device " PCI_PRI_FMT " aborted after"
3340 " encountering an error: %s",
3341 pci_dev->addr.domain, pci_dev->addr.bus,
3342 pci_dev->addr.devid, pci_dev->addr.function,
3343 strerror(rte_errno));
3347 if (!list[i].eth_dev)
3349 mlx5_dev_close(list[i].eth_dev);
3350 /* mac_addrs must not be freed because in dev_private */
3351 list[i].eth_dev->data->mac_addrs = NULL;
3352 claim_zero(rte_eth_dev_release_port(list[i].eth_dev));
3354 /* Restore original error. */
3361 * Do the routine cleanup:
3362 * - close opened Netlink sockets
3363 * - free allocated spawn data array
3364 * - free the Infiniband device list
3373 mlx5_glue->free_device_list(ibv_list);
3378 * Look for the ethernet device belonging to mlx5 driver.
3380 * @param[in] port_id
3381 * port_id to start looking for device.
3382 * @param[in] pci_dev
3383 * Pointer to the hint PCI device. When device is being probed
3384 * the its siblings (master and preceding representors might
3385 * not have assigned driver yet (because the mlx5_pci_probe()
3386 * is not completed yet, for this case match on hint PCI
3387 * device may be used to detect sibling device.
3390 * port_id of found device, RTE_MAX_ETHPORT if not found.
3393 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
3395 while (port_id < RTE_MAX_ETHPORTS) {
3396 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
3398 if (dev->state != RTE_ETH_DEV_UNUSED &&
3400 (dev->device == &pci_dev->device ||
3401 (dev->device->driver &&
3402 dev->device->driver->name &&
3403 !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
3407 if (port_id >= RTE_MAX_ETHPORTS)
3408 return RTE_MAX_ETHPORTS;
3413 * DPDK callback to remove a PCI device.
3415 * This function removes all Ethernet devices belong to a given PCI device.
3417 * @param[in] pci_dev
3418 * Pointer to the PCI device.
3421 * 0 on success, the function cannot fail.
3424 mlx5_pci_remove(struct rte_pci_device *pci_dev)
3428 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device)
3429 rte_eth_dev_close(port_id);
3433 static const struct rte_pci_id mlx5_pci_id_map[] = {
3435 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3436 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
3439 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3440 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
3443 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3444 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
3447 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3448 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
3451 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3452 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
3455 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3456 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
3459 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3460 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
3463 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3464 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
3467 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3468 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
3471 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3472 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
3475 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3476 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
3479 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3480 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
3483 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3484 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
3487 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3488 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
3495 static struct rte_pci_driver mlx5_driver = {
3497 .name = MLX5_DRIVER_NAME
3499 .id_table = mlx5_pci_id_map,
3500 .probe = mlx5_pci_probe,
3501 .remove = mlx5_pci_remove,
3502 .dma_map = mlx5_dma_map,
3503 .dma_unmap = mlx5_dma_unmap,
3504 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV |
3505 RTE_PCI_DRV_PROBE_AGAIN,
3509 * Driver initialization routine.
3511 RTE_INIT(rte_mlx5_pmd_init)
3513 /* Initialize driver log type. */
3514 mlx5_logtype = rte_log_register("pmd.net.mlx5");
3515 if (mlx5_logtype >= 0)
3516 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
3518 /* Build the static tables for Verbs conversion. */
3519 mlx5_set_ptype_table();
3520 mlx5_set_cksum_table();
3521 mlx5_set_swp_types_table();
3523 rte_pci_register(&mlx5_driver);
3526 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
3527 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
3528 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");