drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <assert.h>
  10 #include <dlfcn.h>
  11 #include <stdint.h>
  12 #include <stdlib.h>
  13 #include <errno.h>
  14 #include <net/if.h>
  15 #include <sys/mman.h>
  16 #include <linux/rtnetlink.h>
  17
  18 /* Verbs header. */
  19 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  20 #ifdef PEDANTIC
  21 #pragma GCC diagnostic ignored "-Wpedantic"
  22 #endif
  23 #include <infiniband/verbs.h>
  24 #ifdef PEDANTIC
  25 #pragma GCC diagnostic error "-Wpedantic"
  26 #endif
  27
  28 #include <rte_malloc.h>
  29 #include <rte_ethdev_driver.h>
  30 #include <rte_ethdev_pci.h>
  31 #include <rte_pci.h>
  32 #include <rte_bus_pci.h>
  33 #include <rte_common.h>
  34 #include <rte_config.h>
  35 #include <rte_eal_memconfig.h>
  36 #include <rte_kvargs.h>
  37
  38 #include "mlx5.h"
  39 #include "mlx5_utils.h"
  40 #include "mlx5_rxtx.h"
  41 #include "mlx5_autoconf.h"
  42 #include "mlx5_defs.h"
  43 #include "mlx5_glue.h"
  44
  45 /* Device parameter to enable RX completion queue compression. */
  46 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  47
  48 /* Device parameter to configure inline send. */
  49 #define MLX5_TXQ_INLINE "txq_inline"
  50
  51 /*
  52  * Device parameter to configure the number of TX queues threshold for
  53  * enabling inline send.
  54  */
  55 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  56
  57 /* Device parameter to enable multi-packet send WQEs. */
  58 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  59
  60 /* Device parameter to include 2 dsegs in the title WQEBB. */
  61 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
  62
  63 /* Device parameter to limit the size of inlining packet. */
  64 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
  65
  66 /* Device parameter to enable hardware Tx vector. */
  67 #define MLX5_TX_VEC_EN "tx_vec_en"
  68
  69 /* Device parameter to enable hardware Rx vector. */
  70 #define MLX5_RX_VEC_EN "rx_vec_en"
  71
  72 /* Activate Netlink support in VF mode. */
  73 #define MLX5_VF_NL_EN "vf_nl_en"
  74
  75 #ifndef HAVE_IBV_MLX5_MOD_MPW
  76 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
  77 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
  78 #endif
  79
  80 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
  81 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
  82 #endif
  83
  84 /** Driver-specific log messages type. */
  85 int mlx5_logtype;
  86
  87 /**
  88  * Retrieve integer value from environment variable.
  89  *
  90  * @param[in] name
  91  *   Environment variable name.
  92  *
  93  * @return
  94  *   Integer value, 0 if the variable is not set.
  95  */
  96 int
  97 mlx5_getenv_int(const char *name)
  98 {
  99         const char *val = getenv(name);
 100
 101         if (val == NULL)
 102                 return 0;
 103         return atoi(val);
 104 }
 105
 106 /**
 107  * Verbs callback to allocate a memory. This function should allocate the space
 108  * according to the size provided residing inside a huge page.
 109  * Please note that all allocation must respect the alignment from libmlx5
 110  * (i.e. currently sysconf(_SC_PAGESIZE)).
 111  *
 112  * @param[in] size
 113  *   The size in bytes of the memory to allocate.
 114  * @param[in] data
 115  *   A pointer to the callback data.
 116  *
 117  * @return
 118  *   Allocated buffer, NULL otherwise and rte_errno is set.
 119  */
 120 static void *
 121 mlx5_alloc_verbs_buf(size_t size, void *data)
 122 {
 123         struct priv *priv = data;
 124         void *ret;
 125         size_t alignment = sysconf(_SC_PAGESIZE);
 126         unsigned int socket = SOCKET_ID_ANY;
 127
 128         if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
 129                 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
 130
 131                 socket = ctrl->socket;
 132         } else if (priv->verbs_alloc_ctx.type ==
 133                    MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
 134                 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
 135
 136                 socket = ctrl->socket;
 137         }
 138         assert(data != NULL);
 139         ret = rte_malloc_socket(__func__, size, alignment, socket);
 140         if (!ret && size)
 141                 rte_errno = ENOMEM;
 142         return ret;
 143 }
 144
 145 /**
 146  * Verbs callback to free a memory.
 147  *
 148  * @param[in] ptr
 149  *   A pointer to the memory to free.
 150  * @param[in] data
 151  *   A pointer to the callback data.
 152  */
 153 static void
 154 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
 155 {
 156         assert(data != NULL);
 157         rte_free(ptr);
 158 }
 159
 160 /**
 161  * DPDK callback to close the device.
 162  *
 163  * Destroy all queues and objects, free memory.
 164  *
 165  * @param dev
 166  *   Pointer to Ethernet device structure.
 167  */
 168 static void
 169 mlx5_dev_close(struct rte_eth_dev *dev)
 170 {
 171         struct priv *priv = dev->data->dev_private;
 172         unsigned int i;
 173         int ret;
 174
 175         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
 176                 dev->data->port_id,
 177                 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
 178         /* In case mlx5_dev_stop() has not been called. */
 179         mlx5_dev_interrupt_handler_uninstall(dev);
 180         mlx5_traffic_disable(dev);
 181         /* Prevent crashes when queues are still in use. */
 182         dev->rx_pkt_burst = removed_rx_burst;
 183         dev->tx_pkt_burst = removed_tx_burst;
 184         if (priv->rxqs != NULL) {
 185                 /* XXX race condition if mlx5_rx_burst() is still running. */
 186                 usleep(1000);
 187                 for (i = 0; (i != priv->rxqs_n); ++i)
 188                         mlx5_rxq_release(dev, i);
 189                 priv->rxqs_n = 0;
 190                 priv->rxqs = NULL;
 191         }
 192         if (priv->txqs != NULL) {
 193                 /* XXX race condition if mlx5_tx_burst() is still running. */
 194                 usleep(1000);
 195                 for (i = 0; (i != priv->txqs_n); ++i)
 196                         mlx5_txq_release(dev, i);
 197                 priv->txqs_n = 0;
 198                 priv->txqs = NULL;
 199         }
 200         mlx5_flow_delete_drop_queue(dev);
 201         if (priv->pd != NULL) {
 202                 assert(priv->ctx != NULL);
 203                 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
 204                 claim_zero(mlx5_glue->close_device(priv->ctx));
 205         } else
 206                 assert(priv->ctx == NULL);
 207         if (priv->rss_conf.rss_key != NULL)
 208                 rte_free(priv->rss_conf.rss_key);
 209         if (priv->reta_idx != NULL)
 210                 rte_free(priv->reta_idx);
 211         if (priv->primary_socket)
 212                 mlx5_socket_uninit(dev);
 213         if (priv->config.vf)
 214                 mlx5_nl_mac_addr_flush(dev);
 215         if (priv->nl_socket >= 0)
 216                 close(priv->nl_socket);
 217         ret = mlx5_hrxq_ibv_verify(dev);
 218         if (ret)
 219                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
 220                         dev->data->port_id);
 221         ret = mlx5_ind_table_ibv_verify(dev);
 222         if (ret)
 223                 DRV_LOG(WARNING, "port %u some indirection table still remain",
 224                         dev->data->port_id);
 225         ret = mlx5_rxq_ibv_verify(dev);
 226         if (ret)
 227                 DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain",
 228                         dev->data->port_id);
 229         ret = mlx5_rxq_verify(dev);
 230         if (ret)
 231                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
 232                         dev->data->port_id);
 233         ret = mlx5_txq_ibv_verify(dev);
 234         if (ret)
 235                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
 236                         dev->data->port_id);
 237         ret = mlx5_txq_verify(dev);
 238         if (ret)
 239                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
 240                         dev->data->port_id);
 241         ret = mlx5_flow_verify(dev);
 242         if (ret)
 243                 DRV_LOG(WARNING, "port %u some flows still remain",
 244                         dev->data->port_id);
 245         ret = mlx5_mr_verify(dev);
 246         if (ret)
 247                 DRV_LOG(WARNING, "port %u some memory region still remain",
 248                         dev->data->port_id);
 249         memset(priv, 0, sizeof(*priv));
 250 }
 251
 252 const struct eth_dev_ops mlx5_dev_ops = {
 253         .dev_configure = mlx5_dev_configure,
 254         .dev_start = mlx5_dev_start,
 255         .dev_stop = mlx5_dev_stop,
 256         .dev_set_link_down = mlx5_set_link_down,
 257         .dev_set_link_up = mlx5_set_link_up,
 258         .dev_close = mlx5_dev_close,
 259         .promiscuous_enable = mlx5_promiscuous_enable,
 260         .promiscuous_disable = mlx5_promiscuous_disable,
 261         .allmulticast_enable = mlx5_allmulticast_enable,
 262         .allmulticast_disable = mlx5_allmulticast_disable,
 263         .link_update = mlx5_link_update,
 264         .stats_get = mlx5_stats_get,
 265         .stats_reset = mlx5_stats_reset,
 266         .xstats_get = mlx5_xstats_get,
 267         .xstats_reset = mlx5_xstats_reset,
 268         .xstats_get_names = mlx5_xstats_get_names,
 269         .dev_infos_get = mlx5_dev_infos_get,
 270         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
 271         .vlan_filter_set = mlx5_vlan_filter_set,
 272         .rx_queue_setup = mlx5_rx_queue_setup,
 273         .tx_queue_setup = mlx5_tx_queue_setup,
 274         .rx_queue_release = mlx5_rx_queue_release,
 275         .tx_queue_release = mlx5_tx_queue_release,
 276         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
 277         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
 278         .mac_addr_remove = mlx5_mac_addr_remove,
 279         .mac_addr_add = mlx5_mac_addr_add,
 280         .mac_addr_set = mlx5_mac_addr_set,
 281         .set_mc_addr_list = mlx5_set_mc_addr_list,
 282         .mtu_set = mlx5_dev_set_mtu,
 283         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
 284         .vlan_offload_set = mlx5_vlan_offload_set,
 285         .reta_update = mlx5_dev_rss_reta_update,
 286         .reta_query = mlx5_dev_rss_reta_query,
 287         .rss_hash_update = mlx5_rss_hash_update,
 288         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
 289         .filter_ctrl = mlx5_dev_filter_ctrl,
 290         .rx_descriptor_status = mlx5_rx_descriptor_status,
 291         .tx_descriptor_status = mlx5_tx_descriptor_status,
 292         .rx_queue_intr_enable = mlx5_rx_intr_enable,
 293         .rx_queue_intr_disable = mlx5_rx_intr_disable,
 294         .is_removed = mlx5_is_removed,
 295 };
 296
 297 static const struct eth_dev_ops mlx5_dev_sec_ops = {
 298         .stats_get = mlx5_stats_get,
 299         .stats_reset = mlx5_stats_reset,
 300         .xstats_get = mlx5_xstats_get,
 301         .xstats_reset = mlx5_xstats_reset,
 302         .xstats_get_names = mlx5_xstats_get_names,
 303         .dev_infos_get = mlx5_dev_infos_get,
 304         .rx_descriptor_status = mlx5_rx_descriptor_status,
 305         .tx_descriptor_status = mlx5_tx_descriptor_status,
 306 };
 307
 308 /* Available operators in flow isolated mode. */
 309 const struct eth_dev_ops mlx5_dev_ops_isolate = {
 310         .dev_configure = mlx5_dev_configure,
 311         .dev_start = mlx5_dev_start,
 312         .dev_stop = mlx5_dev_stop,
 313         .dev_set_link_down = mlx5_set_link_down,
 314         .dev_set_link_up = mlx5_set_link_up,
 315         .dev_close = mlx5_dev_close,
 316         .link_update = mlx5_link_update,
 317         .stats_get = mlx5_stats_get,
 318         .stats_reset = mlx5_stats_reset,
 319         .xstats_get = mlx5_xstats_get,
 320         .xstats_reset = mlx5_xstats_reset,
 321         .xstats_get_names = mlx5_xstats_get_names,
 322         .dev_infos_get = mlx5_dev_infos_get,
 323         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
 324         .vlan_filter_set = mlx5_vlan_filter_set,
 325         .rx_queue_setup = mlx5_rx_queue_setup,
 326         .tx_queue_setup = mlx5_tx_queue_setup,
 327         .rx_queue_release = mlx5_rx_queue_release,
 328         .tx_queue_release = mlx5_tx_queue_release,
 329         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
 330         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
 331         .mac_addr_remove = mlx5_mac_addr_remove,
 332         .mac_addr_add = mlx5_mac_addr_add,
 333         .mac_addr_set = mlx5_mac_addr_set,
 334         .set_mc_addr_list = mlx5_set_mc_addr_list,
 335         .mtu_set = mlx5_dev_set_mtu,
 336         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
 337         .vlan_offload_set = mlx5_vlan_offload_set,
 338         .filter_ctrl = mlx5_dev_filter_ctrl,
 339         .rx_descriptor_status = mlx5_rx_descriptor_status,
 340         .tx_descriptor_status = mlx5_tx_descriptor_status,
 341         .rx_queue_intr_enable = mlx5_rx_intr_enable,
 342         .rx_queue_intr_disable = mlx5_rx_intr_disable,
 343         .is_removed = mlx5_is_removed,
 344 };
 345
 346 static struct {
 347         struct rte_pci_addr pci_addr; /* associated PCI address */
 348         uint32_t ports; /* physical ports bitfield. */
 349 } mlx5_dev[32];
 350
 351 /**
 352  * Get device index in mlx5_dev[] from PCI bus address.
 353  *
 354  * @param[in] pci_addr
 355  *   PCI bus address to look for.
 356  *
 357  * @return
 358  *   mlx5_dev[] index on success, -1 on failure.
 359  */
 360 static int
 361 mlx5_dev_idx(struct rte_pci_addr *pci_addr)
 362 {
 363         unsigned int i;
 364         int ret = -1;
 365
 366         assert(pci_addr != NULL);
 367         for (i = 0; (i != RTE_DIM(mlx5_dev)); ++i) {
 368                 if ((mlx5_dev[i].pci_addr.domain == pci_addr->domain) &&
 369                     (mlx5_dev[i].pci_addr.bus == pci_addr->bus) &&
 370                     (mlx5_dev[i].pci_addr.devid == pci_addr->devid) &&
 371                     (mlx5_dev[i].pci_addr.function == pci_addr->function))
 372                         return i;
 373                 if ((mlx5_dev[i].ports == 0) && (ret == -1))
 374                         ret = i;
 375         }
 376         return ret;
 377 }
 378
 379 /**
 380  * Verify and store value for device argument.
 381  *
 382  * @param[in] key
 383  *   Key argument to verify.
 384  * @param[in] val
 385  *   Value associated with key.
 386  * @param opaque
 387  *   User data.
 388  *
 389  * @return
 390  *   0 on success, a negative errno value otherwise and rte_errno is set.
 391  */
 392 static int
 393 mlx5_args_check(const char *key, const char *val, void *opaque)
 394 {
 395         struct mlx5_dev_config *config = opaque;
 396         unsigned long tmp;
 397
 398         errno = 0;
 399         tmp = strtoul(val, NULL, 0);
 400         if (errno) {
 401                 rte_errno = errno;
 402                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
 403                 return -rte_errno;
 404         }
 405         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
 406                 config->cqe_comp = !!tmp;
 407         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
 408                 config->txq_inline = tmp;
 409         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
 410                 config->txqs_inline = tmp;
 411         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
 412                 config->mps = !!tmp ? config->mps : 0;
 413         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
 414                 config->mpw_hdr_dseg = !!tmp;
 415         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
 416                 config->inline_max_packet_sz = tmp;
 417         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
 418                 config->tx_vec_en = !!tmp;
 419         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
 420                 config->rx_vec_en = !!tmp;
 421         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
 422                 config->vf_nl_en = !!tmp;
 423         } else {
 424                 DRV_LOG(WARNING, "%s: unknown parameter", key);
 425                 rte_errno = EINVAL;
 426                 return -rte_errno;
 427         }
 428         return 0;
 429 }
 430
 431 /**
 432  * Parse device parameters.
 433  *
 434  * @param config
 435  *   Pointer to device configuration structure.
 436  * @param devargs
 437  *   Device arguments structure.
 438  *
 439  * @return
 440  *   0 on success, a negative errno value otherwise and rte_errno is set.
 441  */
 442 static int
 443 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
 444 {
 445         const char **params = (const char *[]){
 446                 MLX5_RXQ_CQE_COMP_EN,
 447                 MLX5_TXQ_INLINE,
 448                 MLX5_TXQS_MIN_INLINE,
 449                 MLX5_TXQ_MPW_EN,
 450                 MLX5_TXQ_MPW_HDR_DSEG_EN,
 451                 MLX5_TXQ_MAX_INLINE_LEN,
 452                 MLX5_TX_VEC_EN,
 453                 MLX5_RX_VEC_EN,
 454                 MLX5_VF_NL_EN,
 455                 NULL,
 456         };
 457         struct rte_kvargs *kvlist;
 458         int ret = 0;
 459         int i;
 460
 461         if (devargs == NULL)
 462                 return 0;
 463         /* Following UGLY cast is done to pass checkpatch. */
 464         kvlist = rte_kvargs_parse(devargs->args, params);
 465         if (kvlist == NULL)
 466                 return 0;
 467         /* Process parameters. */
 468         for (i = 0; (params[i] != NULL); ++i) {
 469                 if (rte_kvargs_count(kvlist, params[i])) {
 470                         ret = rte_kvargs_process(kvlist, params[i],
 471                                                  mlx5_args_check, config);
 472                         if (ret) {
 473                                 rte_errno = EINVAL;
 474                                 rte_kvargs_free(kvlist);
 475                                 return -rte_errno;
 476                         }
 477                 }
 478         }
 479         rte_kvargs_free(kvlist);
 480         return 0;
 481 }
 482
 483 static struct rte_pci_driver mlx5_driver;
 484
 485 /*
 486  * Reserved UAR address space for TXQ UAR(hw doorbell) mapping, process
 487  * local resource used by both primary and secondary to avoid duplicate
 488  * reservation.
 489  * The space has to be available on both primary and secondary process,
 490  * TXQ UAR maps to this area using fixed mmap w/o double check.
 491  */
 492 static void *uar_base;
 493
 494 static int
 495 find_lower_va_bound(const struct rte_memseg_list *msl __rte_unused,
 496                 const struct rte_memseg *ms, void *arg)
 497 {
 498         void **addr = arg;
 499
 500         if (*addr == NULL)
 501                 *addr = ms->addr;
 502         else
 503                 *addr = RTE_MIN(*addr, ms->addr);
 504
 505         return 0;
 506 }
 507
 508 /**
 509  * Reserve UAR address space for primary process.
 510  *
 511  * @param[in] dev
 512  *   Pointer to Ethernet device.
 513  *
 514  * @return
 515  *   0 on success, a negative errno value otherwise and rte_errno is set.
 516  */
 517 static int
 518 mlx5_uar_init_primary(struct rte_eth_dev *dev)
 519 {
 520         struct priv *priv = dev->data->dev_private;
 521         void *addr = (void *)0;
 522
 523         if (uar_base) { /* UAR address space mapped. */
 524                 priv->uar_base = uar_base;
 525                 return 0;
 526         }
 527         /* find out lower bound of hugepage segments */
 528         rte_memseg_walk(find_lower_va_bound, &addr);
 529
 530         /* keep distance to hugepages to minimize potential conflicts. */
 531         addr = RTE_PTR_SUB(addr, MLX5_UAR_OFFSET + MLX5_UAR_SIZE);
 532         /* anonymous mmap, no real memory consumption. */
 533         addr = mmap(addr, MLX5_UAR_SIZE,
 534                     PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
 535         if (addr == MAP_FAILED) {
 536                 DRV_LOG(ERR,
 537                         "port %u failed to reserve UAR address space, please"
 538                         " adjust MLX5_UAR_SIZE or try --base-virtaddr",
 539                         dev->data->port_id);
 540                 rte_errno = ENOMEM;
 541                 return -rte_errno;
 542         }
 543         /* Accept either same addr or a new addr returned from mmap if target
 544          * range occupied.
 545          */
 546         DRV_LOG(INFO, "port %u reserved UAR address space: %p",
 547                 dev->data->port_id, addr);
 548         priv->uar_base = addr; /* for primary and secondary UAR re-mmap. */
 549         uar_base = addr; /* process local, don't reserve again. */
 550         return 0;
 551 }
 552
 553 /**
 554  * Reserve UAR address space for secondary process, align with
 555  * primary process.
 556  *
 557  * @param[in] dev
 558  *   Pointer to Ethernet device.
 559  *
 560  * @return
 561  *   0 on success, a negative errno value otherwise and rte_errno is set.
 562  */
 563 static int
 564 mlx5_uar_init_secondary(struct rte_eth_dev *dev)
 565 {
 566         struct priv *priv = dev->data->dev_private;
 567         void *addr;
 568
 569         assert(priv->uar_base);
 570         if (uar_base) { /* already reserved. */
 571                 assert(uar_base == priv->uar_base);
 572                 return 0;
 573         }
 574         /* anonymous mmap, no real memory consumption. */
 575         addr = mmap(priv->uar_base, MLX5_UAR_SIZE,
 576                     PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
 577         if (addr == MAP_FAILED) {
 578                 DRV_LOG(ERR, "port %u UAR mmap failed: %p size: %llu",
 579                         dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
 580                 rte_errno = ENXIO;
 581                 return -rte_errno;
 582         }
 583         if (priv->uar_base != addr) {
 584                 DRV_LOG(ERR,
 585                         "port %u UAR address %p size %llu occupied, please"
 586                         " adjust MLX5_UAR_OFFSET or try EAL parameter"
 587                         " --base-virtaddr",
 588                         dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
 589                 rte_errno = ENXIO;
 590                 return -rte_errno;
 591         }
 592         uar_base = addr; /* process local, don't reserve again */
 593         DRV_LOG(INFO, "port %u reserved UAR address space: %p",
 594                 dev->data->port_id, addr);
 595         return 0;
 596 }
 597
 598 /**
 599  * DPDK callback to register a PCI device.
 600  *
 601  * This function creates an Ethernet device for each port of a given
 602  * PCI device.
 603  *
 604  * @param[in] pci_drv
 605  *   PCI driver structure (mlx5_driver).
 606  * @param[in] pci_dev
 607  *   PCI device information.
 608  *
 609  * @return
 610  *   0 on success, a negative errno value otherwise and rte_errno is set.
 611  */
 612 static int
 613 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 614                struct rte_pci_device *pci_dev)
 615 {
 616         struct ibv_device **list = NULL;
 617         struct ibv_device *ibv_dev;
 618         int err = 0;
 619         struct ibv_context *attr_ctx = NULL;
 620         struct ibv_device_attr_ex device_attr;
 621         unsigned int vf;
 622         unsigned int mps;
 623         unsigned int cqe_comp;
 624         unsigned int tunnel_en = 0;
 625         unsigned int swp = 0;
 626         unsigned int verb_priorities = 0;
 627         int idx;
 628         int i;
 629         struct mlx5dv_context attrs_out = {0};
 630 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
 631         struct ibv_counter_set_description cs_desc;
 632 #endif
 633
 634         assert(pci_drv == &mlx5_driver);
 635         /* Get mlx5_dev[] index. */
 636         idx = mlx5_dev_idx(&pci_dev->addr);
 637         if (idx == -1) {
 638                 DRV_LOG(ERR, "this driver cannot support any more adapters");
 639                 err = ENOMEM;
 640                 goto error;
 641         }
 642         DRV_LOG(DEBUG, "using driver device index %d", idx);
 643         /* Save PCI address. */
 644         mlx5_dev[idx].pci_addr = pci_dev->addr;
 645         list = mlx5_glue->get_device_list(&i);
 646         if (list == NULL) {
 647                 assert(errno);
 648                 err = errno;
 649                 if (errno == ENOSYS)
 650                         DRV_LOG(ERR,
 651                                 "cannot list devices, is ib_uverbs loaded?");
 652                 goto error;
 653         }
 654         assert(i >= 0);
 655         /*
 656          * For each listed device, check related sysfs entry against
 657          * the provided PCI ID.
 658          */
 659         while (i != 0) {
 660                 struct rte_pci_addr pci_addr;
 661
 662                 --i;
 663                 DRV_LOG(DEBUG, "checking device \"%s\"", list[i]->name);
 664                 if (mlx5_ibv_device_to_pci_addr(list[i], &pci_addr))
 665                         continue;
 666                 if ((pci_dev->addr.domain != pci_addr.domain) ||
 667                     (pci_dev->addr.bus != pci_addr.bus) ||
 668                     (pci_dev->addr.devid != pci_addr.devid) ||
 669                     (pci_dev->addr.function != pci_addr.function))
 670                         continue;
 671                 DRV_LOG(INFO, "PCI information matches, using device \"%s\"",
 672                         list[i]->name);
 673                 vf = ((pci_dev->id.device_id ==
 674                        PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) ||
 675                       (pci_dev->id.device_id ==
 676                        PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) ||
 677                       (pci_dev->id.device_id ==
 678                        PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) ||
 679                       (pci_dev->id.device_id ==
 680                        PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF));
 681                 attr_ctx = mlx5_glue->open_device(list[i]);
 682                 rte_errno = errno;
 683                 err = rte_errno;
 684                 break;
 685         }
 686         if (attr_ctx == NULL) {
 687                 mlx5_glue->free_device_list(list);
 688                 switch (err) {
 689                 case 0:
 690                         DRV_LOG(ERR,
 691                                 "cannot access device, is mlx5_ib loaded?");
 692                         err = ENODEV;
 693                         goto error;
 694                 case EINVAL:
 695                         DRV_LOG(ERR,
 696                                 "cannot use device, are drivers up to date?");
 697                         goto error;
 698                 }
 699         }
 700         ibv_dev = list[i];
 701         DRV_LOG(DEBUG, "device opened");
 702 #ifdef HAVE_IBV_MLX5_MOD_SWP
 703         attrs_out.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
 704 #endif
 705         /*
 706          * Multi-packet send is supported by ConnectX-4 Lx PF as well
 707          * as all ConnectX-5 devices.
 708          */
 709 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
 710         attrs_out.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
 711 #endif
 712         mlx5_glue->dv_query_device(attr_ctx, &attrs_out);
 713         if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
 714                 if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
 715                         DRV_LOG(DEBUG, "enhanced MPW is supported");
 716                         mps = MLX5_MPW_ENHANCED;
 717                 } else {
 718                         DRV_LOG(DEBUG, "MPW is supported");
 719                         mps = MLX5_MPW;
 720                 }
 721         } else {
 722                 DRV_LOG(DEBUG, "MPW isn't supported");
 723                 mps = MLX5_MPW_DISABLED;
 724         }
 725 #ifdef HAVE_IBV_MLX5_MOD_SWP
 726         if (attrs_out.comp_mask | MLX5DV_CONTEXT_MASK_SWP)
 727                 swp = attrs_out.sw_parsing_caps.sw_parsing_offloads;
 728         DRV_LOG(DEBUG, "SWP support: %u", swp);
 729 #endif
 730         if (RTE_CACHE_LINE_SIZE == 128 &&
 731             !(attrs_out.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
 732                 cqe_comp = 0;
 733         else
 734                 cqe_comp = 1;
 735 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
 736         if (attrs_out.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
 737                 tunnel_en = ((attrs_out.tunnel_offloads_caps &
 738                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
 739                              (attrs_out.tunnel_offloads_caps &
 740                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE));
 741         }
 742         DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
 743                 tunnel_en ? "" : "not ");
 744 #else
 745         DRV_LOG(WARNING,
 746                 "tunnel offloading disabled due to old OFED/rdma-core version");
 747 #endif
 748         if (mlx5_glue->query_device_ex(attr_ctx, NULL, &device_attr)) {
 749                 err = errno;
 750                 goto error;
 751         }
 752         DRV_LOG(INFO, "%u port(s) detected",
 753                 device_attr.orig_attr.phys_port_cnt);
 754         for (i = 0; i < device_attr.orig_attr.phys_port_cnt; i++) {
 755                 char name[RTE_ETH_NAME_MAX_LEN];
 756                 int len;
 757                 uint32_t port = i + 1; /* ports are indexed from one */
 758                 uint32_t test = (1 << i);
 759                 struct ibv_context *ctx = NULL;
 760                 struct ibv_port_attr port_attr;
 761                 struct ibv_pd *pd = NULL;
 762                 struct priv *priv = NULL;
 763                 struct rte_eth_dev *eth_dev = NULL;
 764                 struct ibv_device_attr_ex device_attr_ex;
 765                 struct ether_addr mac;
 766                 struct mlx5_dev_config config = {
 767                         .cqe_comp = cqe_comp,
 768                         .mps = mps,
 769                         .tunnel_en = tunnel_en,
 770                         .tx_vec_en = 1,
 771                         .rx_vec_en = 1,
 772                         .mpw_hdr_dseg = 0,
 773                         .txq_inline = MLX5_ARG_UNSET,
 774                         .txqs_inline = MLX5_ARG_UNSET,
 775                         .inline_max_packet_sz = MLX5_ARG_UNSET,
 776                         .vf_nl_en = 1,
 777                         .swp = !!swp,
 778                 };
 779
 780                 len = snprintf(name, sizeof(name), PCI_PRI_FMT,
 781                          pci_dev->addr.domain, pci_dev->addr.bus,
 782                          pci_dev->addr.devid, pci_dev->addr.function);
 783                 if (device_attr.orig_attr.phys_port_cnt > 1)
 784                         snprintf(name + len, sizeof(name), " port %u", i);
 785                 mlx5_dev[idx].ports |= test;
 786                 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
 787                         eth_dev = rte_eth_dev_attach_secondary(name);
 788                         if (eth_dev == NULL) {
 789                                 DRV_LOG(ERR, "can not attach rte ethdev");
 790                                 rte_errno = ENOMEM;
 791                                 err = rte_errno;
 792                                 goto error;
 793                         }
 794                         eth_dev->device = &pci_dev->device;
 795                         eth_dev->dev_ops = &mlx5_dev_sec_ops;
 796                         err = mlx5_uar_init_secondary(eth_dev);
 797                         if (err)
 798                                 goto error;
 799                         /* Receive command fd from primary process */
 800                         err = mlx5_socket_connect(eth_dev);
 801                         if (err)
 802                                 goto error;
 803                         /* Remap UAR for Tx queues. */
 804                         err = mlx5_tx_uar_remap(eth_dev, err);
 805                         if (err)
 806                                 goto error;
 807                         /*
 808                          * Ethdev pointer is still required as input since
 809                          * the primary device is not accessible from the
 810                          * secondary process.
 811                          */
 812                         eth_dev->rx_pkt_burst =
 813                                 mlx5_select_rx_function(eth_dev);
 814                         eth_dev->tx_pkt_burst =
 815                                 mlx5_select_tx_function(eth_dev);
 816                         continue;
 817                 }
 818                 DRV_LOG(DEBUG, "using port %u (%08" PRIx32 ")", port, test);
 819                 ctx = mlx5_glue->open_device(ibv_dev);
 820                 if (ctx == NULL) {
 821                         err = ENODEV;
 822                         goto port_error;
 823                 }
 824                 /* Check port status. */
 825                 err = mlx5_glue->query_port(ctx, port, &port_attr);
 826                 if (err) {
 827                         DRV_LOG(ERR, "port query failed: %s", strerror(err));
 828                         goto port_error;
 829                 }
 830                 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
 831                         DRV_LOG(ERR,
 832                                 "port %d is not configured in Ethernet mode",
 833                                 port);
 834                         err = EINVAL;
 835                         goto port_error;
 836                 }
 837                 if (port_attr.state != IBV_PORT_ACTIVE)
 838                         DRV_LOG(DEBUG, "port %d is not active: \"%s\" (%d)",
 839                                 port,
 840                                 mlx5_glue->port_state_str(port_attr.state),
 841                                 port_attr.state);
 842                 /* Allocate protection domain. */
 843                 pd = mlx5_glue->alloc_pd(ctx);
 844                 if (pd == NULL) {
 845                         DRV_LOG(ERR, "PD allocation failure");
 846                         err = ENOMEM;
 847                         goto port_error;
 848                 }
 849                 mlx5_dev[idx].ports |= test;
 850                 /* from rte_ethdev.c */
 851                 priv = rte_zmalloc("ethdev private structure",
 852                                    sizeof(*priv),
 853                                    RTE_CACHE_LINE_SIZE);
 854                 if (priv == NULL) {
 855                         DRV_LOG(ERR, "priv allocation failure");
 856                         err = ENOMEM;
 857                         goto port_error;
 858                 }
 859                 priv->ctx = ctx;
 860                 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path,
 861                         sizeof(priv->ibdev_path));
 862                 priv->device_attr = device_attr;
 863                 priv->port = port;
 864                 priv->pd = pd;
 865                 priv->mtu = ETHER_MTU;
 866                 err = mlx5_args(&config, pci_dev->device.devargs);
 867                 if (err) {
 868                         DRV_LOG(ERR, "failed to process device arguments: %s",
 869                                 strerror(err));
 870                         goto port_error;
 871                 }
 872                 if (mlx5_glue->query_device_ex(ctx, NULL, &device_attr_ex)) {
 873                         DRV_LOG(ERR, "ibv_query_device_ex() failed");
 874                         err = errno;
 875                         goto port_error;
 876                 }
 877                 config.hw_csum = !!(device_attr_ex.device_cap_flags_ex &
 878                                     IBV_DEVICE_RAW_IP_CSUM);
 879                 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
 880                         (config.hw_csum ? "" : "not "));
 881 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
 882                 config.flow_counter_en = !!(device_attr.max_counter_sets);
 883                 mlx5_glue->describe_counter_set(ctx, 0, &cs_desc);
 884                 DRV_LOG(DEBUG,
 885                         "counter type = %d, num of cs = %ld, attributes = %d",
 886                         cs_desc.counter_type, cs_desc.num_of_cs,
 887                         cs_desc.attributes);
 888 #endif
 889                 config.ind_table_max_size =
 890                         device_attr_ex.rss_caps.max_rwq_indirection_table_size;
 891                 /* Remove this check once DPDK supports larger/variable
 892                  * indirection tables. */
 893                 if (config.ind_table_max_size >
 894                                 (unsigned int)ETH_RSS_RETA_SIZE_512)
 895                         config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
 896                 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
 897                         config.ind_table_max_size);
 898                 config.hw_vlan_strip = !!(device_attr_ex.raw_packet_caps &
 899                                          IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
 900                 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
 901                         (config.hw_vlan_strip ? "" : "not "));
 902
 903                 config.hw_fcs_strip = !!(device_attr_ex.raw_packet_caps &
 904                                          IBV_RAW_PACKET_CAP_SCATTER_FCS);
 905                 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
 906                         (config.hw_fcs_strip ? "" : "not "));
 907
 908 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
 909                 config.hw_padding = !!device_attr_ex.rx_pad_end_addr_align;
 910 #endif
 911                 DRV_LOG(DEBUG,
 912                         "hardware Rx end alignment padding is %ssupported",
 913                         (config.hw_padding ? "" : "not "));
 914                 config.vf = vf;
 915                 config.tso = ((device_attr_ex.tso_caps.max_tso > 0) &&
 916                               (device_attr_ex.tso_caps.supported_qpts &
 917                               (1 << IBV_QPT_RAW_PACKET)));
 918                 if (config.tso)
 919                         config.tso_max_payload_sz =
 920                                         device_attr_ex.tso_caps.max_tso;
 921                 if (config.mps && !mps) {
 922                         DRV_LOG(ERR,
 923                                 "multi-packet send not supported on this device"
 924                                 " (" MLX5_TXQ_MPW_EN ")");
 925                         err = ENOTSUP;
 926                         goto port_error;
 927                 }
 928                 DRV_LOG(INFO, "%s MPS is %s",
 929                         config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "",
 930                         config.mps != MLX5_MPW_DISABLED ? "enabled" :
 931                         "disabled");
 932                 if (config.cqe_comp && !cqe_comp) {
 933                         DRV_LOG(WARNING, "Rx CQE compression isn't supported");
 934                         config.cqe_comp = 0;
 935                 }
 936                 eth_dev = rte_eth_dev_allocate(name);
 937                 if (eth_dev == NULL) {
 938                         DRV_LOG(ERR, "can not allocate rte ethdev");
 939                         err = ENOMEM;
 940                         goto port_error;
 941                 }
 942                 eth_dev->data->dev_private = priv;
 943                 priv->dev = eth_dev;
 944                 eth_dev->data->mac_addrs = priv->mac;
 945                 eth_dev->device = &pci_dev->device;
 946                 rte_eth_copy_pci_info(eth_dev, pci_dev);
 947                 eth_dev->device->driver = &mlx5_driver.driver;
 948                 err = mlx5_uar_init_primary(eth_dev);
 949                 if (err)
 950                         goto port_error;
 951                 /* Configure the first MAC address by default. */
 952                 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
 953                         DRV_LOG(ERR,
 954                                 "port %u cannot get MAC address, is mlx5_en"
 955                                 " loaded? (errno: %s)",
 956                                 eth_dev->data->port_id, strerror(errno));
 957                         err = ENODEV;
 958                         goto port_error;
 959                 }
 960                 DRV_LOG(INFO,
 961                         "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
 962                         eth_dev->data->port_id,
 963                         mac.addr_bytes[0], mac.addr_bytes[1],
 964                         mac.addr_bytes[2], mac.addr_bytes[3],
 965                         mac.addr_bytes[4], mac.addr_bytes[5]);
 966 #ifndef NDEBUG
 967                 {
 968                         char ifname[IF_NAMESIZE];
 969
 970                         if (mlx5_get_ifname(eth_dev, &ifname) == 0)
 971                                 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
 972                                         eth_dev->data->port_id, ifname);
 973                         else
 974                                 DRV_LOG(DEBUG, "port %u ifname is unknown",
 975                                         eth_dev->data->port_id);
 976                 }
 977 #endif
 978                 /* Get actual MTU if possible. */
 979                 err = mlx5_get_mtu(eth_dev, &priv->mtu);
 980                 if (err)
 981                         goto port_error;
 982                 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
 983                         priv->mtu);
 984                 /*
 985                  * Initialize burst functions to prevent crashes before link-up.
 986                  */
 987                 eth_dev->rx_pkt_burst = removed_rx_burst;
 988                 eth_dev->tx_pkt_burst = removed_tx_burst;
 989                 eth_dev->dev_ops = &mlx5_dev_ops;
 990                 /* Register MAC address. */
 991                 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
 992                 priv->nl_socket = -1;
 993                 priv->nl_sn = 0;
 994                 if (vf && config.vf_nl_en) {
 995                         priv->nl_socket = mlx5_nl_init(RTMGRP_LINK);
 996                         if (priv->nl_socket < 0)
 997                                 priv->nl_socket = -1;
 998                         mlx5_nl_mac_addr_sync(eth_dev);
 999                 }
1000                 TAILQ_INIT(&priv->flows);
1001                 TAILQ_INIT(&priv->ctrl_flows);
1002                 /* Hint libmlx5 to use PMD allocator for data plane resources */
1003                 struct mlx5dv_ctx_allocators alctr = {
1004                         .alloc = &mlx5_alloc_verbs_buf,
1005                         .free = &mlx5_free_verbs_buf,
1006                         .data = priv,
1007                 };
1008                 mlx5_glue->dv_set_context_attr(ctx,
1009                                                MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
1010                                                (void *)((uintptr_t)&alctr));
1011                 /* Bring Ethernet device up. */
1012                 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
1013                         eth_dev->data->port_id);
1014                 mlx5_set_link_up(eth_dev);
1015                 /*
1016                  * Even though the interrupt handler is not installed yet,
1017                  * interrupts will still trigger on the asyn_fd from
1018                  * Verbs context returned by ibv_open_device().
1019                  */
1020                 mlx5_link_update(eth_dev, 0);
1021                 /* Store device configuration on private structure. */
1022                 priv->config = config;
1023                 /* Create drop queue. */
1024                 err = mlx5_flow_create_drop_queue(eth_dev);
1025                 if (err) {
1026                         DRV_LOG(ERR, "port %u drop queue allocation failed: %s",
1027                                 eth_dev->data->port_id, strerror(rte_errno));
1028                         goto port_error;
1029                 }
1030                 /* Supported Verbs flow priority number detection. */
1031                 if (verb_priorities == 0)
1032                         verb_priorities = mlx5_get_max_verbs_prio(eth_dev);
1033                 if (verb_priorities < MLX5_VERBS_FLOW_PRIO_8) {
1034                         DRV_LOG(ERR, "port %u wrong Verbs flow priorities: %u",
1035                                 eth_dev->data->port_id, verb_priorities);
1036                         goto port_error;
1037                 }
1038                 priv->config.max_verbs_prio = verb_priorities;
1039                 continue;
1040 port_error:
1041                 if (priv)
1042                         rte_free(priv);
1043                 if (pd)
1044                         claim_zero(mlx5_glue->dealloc_pd(pd));
1045                 if (ctx)
1046                         claim_zero(mlx5_glue->close_device(ctx));
1047                 break;
1048         }
1049         /*
1050          * XXX if something went wrong in the loop above, there is a resource
1051          * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as
1052          * long as the dpdk does not provide a way to deallocate a ethdev and a
1053          * way to enumerate the registered ethdevs to free the previous ones.
1054          */
1055         /* no port found, complain */
1056         if (!mlx5_dev[idx].ports) {
1057                 rte_errno = ENODEV;
1058                 err = rte_errno;
1059         }
1060 error:
1061         if (attr_ctx)
1062                 claim_zero(mlx5_glue->close_device(attr_ctx));
1063         if (list)
1064                 mlx5_glue->free_device_list(list);
1065         if (err) {
1066                 rte_errno = err;
1067                 return -rte_errno;
1068         }
1069         return 0;
1070 }
1071
1072 static const struct rte_pci_id mlx5_pci_id_map[] = {
1073         {
1074                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1075                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1076         },
1077         {
1078                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1079                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1080         },
1081         {
1082                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1083                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1084         },
1085         {
1086                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1087                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1088         },
1089         {
1090                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1091                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1092         },
1093         {
1094                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1095                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1096         },
1097         {
1098                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1099                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1100         },
1101         {
1102                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1103                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1104         },
1105         {
1106                 .vendor_id = 0
1107         }
1108 };
1109
1110 static struct rte_pci_driver mlx5_driver = {
1111         .driver = {
1112                 .name = MLX5_DRIVER_NAME
1113         },
1114         .id_table = mlx5_pci_id_map,
1115         .probe = mlx5_pci_probe,
1116         .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV,
1117 };
1118
1119 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1120
1121 /**
1122  * Suffix RTE_EAL_PMD_PATH with "-glue".
1123  *
1124  * This function performs a sanity check on RTE_EAL_PMD_PATH before
1125  * suffixing its last component.
1126  *
1127  * @param buf[out]
1128  *   Output buffer, should be large enough otherwise NULL is returned.
1129  * @param size
1130  *   Size of @p out.
1131  *
1132  * @return
1133  *   Pointer to @p buf or @p NULL in case suffix cannot be appended.
1134  */
1135 static char *
1136 mlx5_glue_path(char *buf, size_t size)
1137 {
1138         static const char *const bad[] = { "/", ".", "..", NULL };
1139         const char *path = RTE_EAL_PMD_PATH;
1140         size_t len = strlen(path);
1141         size_t off;
1142         int i;
1143
1144         while (len && path[len - 1] == '/')
1145                 --len;
1146         for (off = len; off && path[off - 1] != '/'; --off)
1147                 ;
1148         for (i = 0; bad[i]; ++i)
1149                 if (!strncmp(path + off, bad[i], (int)(len - off)))
1150                         goto error;
1151         i = snprintf(buf, size, "%.*s-glue", (int)len, path);
1152         if (i == -1 || (size_t)i >= size)
1153                 goto error;
1154         return buf;
1155 error:
1156         DRV_LOG(ERR,
1157                 "unable to append \"-glue\" to last component of"
1158                 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\"),"
1159                 " please re-configure DPDK");
1160         return NULL;
1161 }
1162
1163 /**
1164  * Initialization routine for run-time dependency on rdma-core.
1165  */
1166 static int
1167 mlx5_glue_init(void)
1168 {
1169         char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")];
1170         const char *path[] = {
1171                 /*
1172                  * A basic security check is necessary before trusting
1173                  * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH.
1174                  */
1175                 (geteuid() == getuid() && getegid() == getgid() ?
1176                  getenv("MLX5_GLUE_PATH") : NULL),
1177                 /*
1178                  * When RTE_EAL_PMD_PATH is set, use its glue-suffixed
1179                  * variant, otherwise let dlopen() look up libraries on its
1180                  * own.
1181                  */
1182                 (*RTE_EAL_PMD_PATH ?
1183                  mlx5_glue_path(glue_path, sizeof(glue_path)) : ""),
1184         };
1185         unsigned int i = 0;
1186         void *handle = NULL;
1187         void **sym;
1188         const char *dlmsg;
1189
1190         while (!handle && i != RTE_DIM(path)) {
1191                 const char *end;
1192                 size_t len;
1193                 int ret;
1194
1195                 if (!path[i]) {
1196                         ++i;
1197                         continue;
1198                 }
1199                 end = strpbrk(path[i], ":;");
1200                 if (!end)
1201                         end = path[i] + strlen(path[i]);
1202                 len = end - path[i];
1203                 ret = 0;
1204                 do {
1205                         char name[ret + 1];
1206
1207                         ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE,
1208                                        (int)len, path[i],
1209                                        (!len || *(end - 1) == '/') ? "" : "/");
1210                         if (ret == -1)
1211                                 break;
1212                         if (sizeof(name) != (size_t)ret + 1)
1213                                 continue;
1214                         DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"",
1215                                 name);
1216                         handle = dlopen(name, RTLD_LAZY);
1217                         break;
1218                 } while (1);
1219                 path[i] = end + 1;
1220                 if (!*end)
1221                         ++i;
1222         }
1223         if (!handle) {
1224                 rte_errno = EINVAL;
1225                 dlmsg = dlerror();
1226                 if (dlmsg)
1227                         DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg);
1228                 goto glue_error;
1229         }
1230         sym = dlsym(handle, "mlx5_glue");
1231         if (!sym || !*sym) {
1232                 rte_errno = EINVAL;
1233                 dlmsg = dlerror();
1234                 if (dlmsg)
1235                         DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg);
1236                 goto glue_error;
1237         }
1238         mlx5_glue = *sym;
1239         return 0;
1240 glue_error:
1241         if (handle)
1242                 dlclose(handle);
1243         DRV_LOG(WARNING,
1244                 "cannot initialize PMD due to missing run-time dependency on"
1245                 " rdma-core libraries (libibverbs, libmlx5)");
1246         return -rte_errno;
1247 }
1248
1249 #endif
1250
1251 /**
1252  * Driver initialization routine.
1253  */
1254 RTE_INIT(rte_mlx5_pmd_init);
1255 static void
1256 rte_mlx5_pmd_init(void)
1257 {
1258         /* Build the static tables for Verbs conversion. */
1259         mlx5_set_ptype_table();
1260         mlx5_set_cksum_table();
1261         mlx5_set_swp_types_table();
1262         /*
1263          * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
1264          * huge pages. Calling ibv_fork_init() during init allows
1265          * applications to use fork() safely for purposes other than
1266          * using this PMD, which is not supported in forked processes.
1267          */
1268         setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
1269         /* Match the size of Rx completion entry to the size of a cacheline. */
1270         if (RTE_CACHE_LINE_SIZE == 128)
1271                 setenv("MLX5_CQE_SIZE", "128", 0);
1272 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1273         if (mlx5_glue_init())
1274                 return;
1275         assert(mlx5_glue);
1276 #endif
1277 #ifndef NDEBUG
1278         /* Glue structure must not contain any NULL pointers. */
1279         {
1280                 unsigned int i;
1281
1282                 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i)
1283                         assert(((const void *const *)mlx5_glue)[i]);
1284         }
1285 #endif
1286         if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) {
1287                 DRV_LOG(ERR,
1288                         "rdma-core glue \"%s\" mismatch: \"%s\" is required",
1289                         mlx5_glue->version, MLX5_GLUE_VERSION);
1290                 return;
1291         }
1292         mlx5_glue->fork_init();
1293         rte_pci_register(&mlx5_driver);
1294 }
1295
1296 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1297 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1298 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");
1299
1300 /** Initialize driver log type. */
1301 RTE_INIT(vdev_netvsc_init_log)
1302 {
1303         mlx5_logtype = rte_log_register("pmd.net.mlx5");
1304         if (mlx5_logtype >= 0)
1305                 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
1306 }