drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <assert.h>
  10 #include <dlfcn.h>
  11 #include <stdint.h>
  12 #include <stdlib.h>
  13 #include <errno.h>
  14 #include <net/if.h>
  15 #include <sys/mman.h>
  16 #include <linux/rtnetlink.h>
  17
  18 /* Verbs header. */
  19 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  20 #ifdef PEDANTIC
  21 #pragma GCC diagnostic ignored "-Wpedantic"
  22 #endif
  23 #include <infiniband/verbs.h>
  24 #ifdef PEDANTIC
  25 #pragma GCC diagnostic error "-Wpedantic"
  26 #endif
  27
  28 #include <rte_malloc.h>
  29 #include <rte_ethdev_driver.h>
  30 #include <rte_ethdev_pci.h>
  31 #include <rte_pci.h>
  32 #include <rte_bus_pci.h>
  33 #include <rte_common.h>
  34 #include <rte_config.h>
  35 #include <rte_eal_memconfig.h>
  36 #include <rte_kvargs.h>
  37
  38 #include "mlx5.h"
  39 #include "mlx5_utils.h"
  40 #include "mlx5_rxtx.h"
  41 #include "mlx5_autoconf.h"
  42 #include "mlx5_defs.h"
  43 #include "mlx5_glue.h"
  44
  45 /* Device parameter to enable RX completion queue compression. */
  46 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  47
  48 /* Device parameter to configure inline send. */
  49 #define MLX5_TXQ_INLINE "txq_inline"
  50
  51 /*
  52  * Device parameter to configure the number of TX queues threshold for
  53  * enabling inline send.
  54  */
  55 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  56
  57 /* Device parameter to enable multi-packet send WQEs. */
  58 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  59
  60 /* Device parameter to include 2 dsegs in the title WQEBB. */
  61 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
  62
  63 /* Device parameter to limit the size of inlining packet. */
  64 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
  65
  66 /* Device parameter to enable hardware Tx vector. */
  67 #define MLX5_TX_VEC_EN "tx_vec_en"
  68
  69 /* Device parameter to enable hardware Rx vector. */
  70 #define MLX5_RX_VEC_EN "rx_vec_en"
  71
  72 /* Allow L3 VXLAN flow creation. */
  73 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
  74
  75 /* Activate Netlink support in VF mode. */
  76 #define MLX5_VF_NL_EN "vf_nl_en"
  77
  78 #ifndef HAVE_IBV_MLX5_MOD_MPW
  79 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
  80 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
  81 #endif
  82
  83 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
  84 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
  85 #endif
  86
  87 /** Driver-specific log messages type. */
  88 int mlx5_logtype;
  89
  90 /**
  91  * Retrieve integer value from environment variable.
  92  *
  93  * @param[in] name
  94  *   Environment variable name.
  95  *
  96  * @return
  97  *   Integer value, 0 if the variable is not set.
  98  */
  99 int
 100 mlx5_getenv_int(const char *name)
 101 {
 102         const char *val = getenv(name);
 103
 104         if (val == NULL)
 105                 return 0;
 106         return atoi(val);
 107 }
 108
 109 /**
 110  * Verbs callback to allocate a memory. This function should allocate the space
 111  * according to the size provided residing inside a huge page.
 112  * Please note that all allocation must respect the alignment from libmlx5
 113  * (i.e. currently sysconf(_SC_PAGESIZE)).
 114  *
 115  * @param[in] size
 116  *   The size in bytes of the memory to allocate.
 117  * @param[in] data
 118  *   A pointer to the callback data.
 119  *
 120  * @return
 121  *   Allocated buffer, NULL otherwise and rte_errno is set.
 122  */
 123 static void *
 124 mlx5_alloc_verbs_buf(size_t size, void *data)
 125 {
 126         struct priv *priv = data;
 127         void *ret;
 128         size_t alignment = sysconf(_SC_PAGESIZE);
 129         unsigned int socket = SOCKET_ID_ANY;
 130
 131         if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
 132                 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
 133
 134                 socket = ctrl->socket;
 135         } else if (priv->verbs_alloc_ctx.type ==
 136                    MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
 137                 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
 138
 139                 socket = ctrl->socket;
 140         }
 141         assert(data != NULL);
 142         ret = rte_malloc_socket(__func__, size, alignment, socket);
 143         if (!ret && size)
 144                 rte_errno = ENOMEM;
 145         return ret;
 146 }
 147
 148 /**
 149  * Verbs callback to free a memory.
 150  *
 151  * @param[in] ptr
 152  *   A pointer to the memory to free.
 153  * @param[in] data
 154  *   A pointer to the callback data.
 155  */
 156 static void
 157 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
 158 {
 159         assert(data != NULL);
 160         rte_free(ptr);
 161 }
 162
 163 /**
 164  * DPDK callback to close the device.
 165  *
 166  * Destroy all queues and objects, free memory.
 167  *
 168  * @param dev
 169  *   Pointer to Ethernet device structure.
 170  */
 171 static void
 172 mlx5_dev_close(struct rte_eth_dev *dev)
 173 {
 174         struct priv *priv = dev->data->dev_private;
 175         unsigned int i;
 176         int ret;
 177
 178         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
 179                 dev->data->port_id,
 180                 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
 181         /* In case mlx5_dev_stop() has not been called. */
 182         mlx5_dev_interrupt_handler_uninstall(dev);
 183         mlx5_traffic_disable(dev);
 184         /* Prevent crashes when queues are still in use. */
 185         dev->rx_pkt_burst = removed_rx_burst;
 186         dev->tx_pkt_burst = removed_tx_burst;
 187         if (priv->rxqs != NULL) {
 188                 /* XXX race condition if mlx5_rx_burst() is still running. */
 189                 usleep(1000);
 190                 for (i = 0; (i != priv->rxqs_n); ++i)
 191                         mlx5_rxq_release(dev, i);
 192                 priv->rxqs_n = 0;
 193                 priv->rxqs = NULL;
 194         }
 195         if (priv->txqs != NULL) {
 196                 /* XXX race condition if mlx5_tx_burst() is still running. */
 197                 usleep(1000);
 198                 for (i = 0; (i != priv->txqs_n); ++i)
 199                         mlx5_txq_release(dev, i);
 200                 priv->txqs_n = 0;
 201                 priv->txqs = NULL;
 202         }
 203         mlx5_flow_delete_drop_queue(dev);
 204         if (priv->pd != NULL) {
 205                 assert(priv->ctx != NULL);
 206                 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
 207                 claim_zero(mlx5_glue->close_device(priv->ctx));
 208         } else
 209                 assert(priv->ctx == NULL);
 210         if (priv->rss_conf.rss_key != NULL)
 211                 rte_free(priv->rss_conf.rss_key);
 212         if (priv->reta_idx != NULL)
 213                 rte_free(priv->reta_idx);
 214         if (priv->primary_socket)
 215                 mlx5_socket_uninit(dev);
 216         if (priv->config.vf)
 217                 mlx5_nl_mac_addr_flush(dev);
 218         if (priv->nl_socket >= 0)
 219                 close(priv->nl_socket);
 220         ret = mlx5_hrxq_ibv_verify(dev);
 221         if (ret)
 222                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
 223                         dev->data->port_id);
 224         ret = mlx5_ind_table_ibv_verify(dev);
 225         if (ret)
 226                 DRV_LOG(WARNING, "port %u some indirection table still remain",
 227                         dev->data->port_id);
 228         ret = mlx5_rxq_ibv_verify(dev);
 229         if (ret)
 230                 DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain",
 231                         dev->data->port_id);
 232         ret = mlx5_rxq_verify(dev);
 233         if (ret)
 234                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
 235                         dev->data->port_id);
 236         ret = mlx5_txq_ibv_verify(dev);
 237         if (ret)
 238                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
 239                         dev->data->port_id);
 240         ret = mlx5_txq_verify(dev);
 241         if (ret)
 242                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
 243                         dev->data->port_id);
 244         ret = mlx5_flow_verify(dev);
 245         if (ret)
 246                 DRV_LOG(WARNING, "port %u some flows still remain",
 247                         dev->data->port_id);
 248         memset(priv, 0, sizeof(*priv));
 249 }
 250
 251 const struct eth_dev_ops mlx5_dev_ops = {
 252         .dev_configure = mlx5_dev_configure,
 253         .dev_start = mlx5_dev_start,
 254         .dev_stop = mlx5_dev_stop,
 255         .dev_set_link_down = mlx5_set_link_down,
 256         .dev_set_link_up = mlx5_set_link_up,
 257         .dev_close = mlx5_dev_close,
 258         .promiscuous_enable = mlx5_promiscuous_enable,
 259         .promiscuous_disable = mlx5_promiscuous_disable,
 260         .allmulticast_enable = mlx5_allmulticast_enable,
 261         .allmulticast_disable = mlx5_allmulticast_disable,
 262         .link_update = mlx5_link_update,
 263         .stats_get = mlx5_stats_get,
 264         .stats_reset = mlx5_stats_reset,
 265         .xstats_get = mlx5_xstats_get,
 266         .xstats_reset = mlx5_xstats_reset,
 267         .xstats_get_names = mlx5_xstats_get_names,
 268         .dev_infos_get = mlx5_dev_infos_get,
 269         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
 270         .vlan_filter_set = mlx5_vlan_filter_set,
 271         .rx_queue_setup = mlx5_rx_queue_setup,
 272         .tx_queue_setup = mlx5_tx_queue_setup,
 273         .rx_queue_release = mlx5_rx_queue_release,
 274         .tx_queue_release = mlx5_tx_queue_release,
 275         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
 276         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
 277         .mac_addr_remove = mlx5_mac_addr_remove,
 278         .mac_addr_add = mlx5_mac_addr_add,
 279         .mac_addr_set = mlx5_mac_addr_set,
 280         .set_mc_addr_list = mlx5_set_mc_addr_list,
 281         .mtu_set = mlx5_dev_set_mtu,
 282         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
 283         .vlan_offload_set = mlx5_vlan_offload_set,
 284         .reta_update = mlx5_dev_rss_reta_update,
 285         .reta_query = mlx5_dev_rss_reta_query,
 286         .rss_hash_update = mlx5_rss_hash_update,
 287         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
 288         .filter_ctrl = mlx5_dev_filter_ctrl,
 289         .rx_descriptor_status = mlx5_rx_descriptor_status,
 290         .tx_descriptor_status = mlx5_tx_descriptor_status,
 291         .rx_queue_intr_enable = mlx5_rx_intr_enable,
 292         .rx_queue_intr_disable = mlx5_rx_intr_disable,
 293         .is_removed = mlx5_is_removed,
 294 };
 295
 296 static const struct eth_dev_ops mlx5_dev_sec_ops = {
 297         .stats_get = mlx5_stats_get,
 298         .stats_reset = mlx5_stats_reset,
 299         .xstats_get = mlx5_xstats_get,
 300         .xstats_reset = mlx5_xstats_reset,
 301         .xstats_get_names = mlx5_xstats_get_names,
 302         .dev_infos_get = mlx5_dev_infos_get,
 303         .rx_descriptor_status = mlx5_rx_descriptor_status,
 304         .tx_descriptor_status = mlx5_tx_descriptor_status,
 305 };
 306
 307 /* Available operators in flow isolated mode. */
 308 const struct eth_dev_ops mlx5_dev_ops_isolate = {
 309         .dev_configure = mlx5_dev_configure,
 310         .dev_start = mlx5_dev_start,
 311         .dev_stop = mlx5_dev_stop,
 312         .dev_set_link_down = mlx5_set_link_down,
 313         .dev_set_link_up = mlx5_set_link_up,
 314         .dev_close = mlx5_dev_close,
 315         .link_update = mlx5_link_update,
 316         .stats_get = mlx5_stats_get,
 317         .stats_reset = mlx5_stats_reset,
 318         .xstats_get = mlx5_xstats_get,
 319         .xstats_reset = mlx5_xstats_reset,
 320         .xstats_get_names = mlx5_xstats_get_names,
 321         .dev_infos_get = mlx5_dev_infos_get,
 322         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
 323         .vlan_filter_set = mlx5_vlan_filter_set,
 324         .rx_queue_setup = mlx5_rx_queue_setup,
 325         .tx_queue_setup = mlx5_tx_queue_setup,
 326         .rx_queue_release = mlx5_rx_queue_release,
 327         .tx_queue_release = mlx5_tx_queue_release,
 328         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
 329         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
 330         .mac_addr_remove = mlx5_mac_addr_remove,
 331         .mac_addr_add = mlx5_mac_addr_add,
 332         .mac_addr_set = mlx5_mac_addr_set,
 333         .set_mc_addr_list = mlx5_set_mc_addr_list,
 334         .mtu_set = mlx5_dev_set_mtu,
 335         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
 336         .vlan_offload_set = mlx5_vlan_offload_set,
 337         .filter_ctrl = mlx5_dev_filter_ctrl,
 338         .rx_descriptor_status = mlx5_rx_descriptor_status,
 339         .tx_descriptor_status = mlx5_tx_descriptor_status,
 340         .rx_queue_intr_enable = mlx5_rx_intr_enable,
 341         .rx_queue_intr_disable = mlx5_rx_intr_disable,
 342         .is_removed = mlx5_is_removed,
 343 };
 344
 345 static struct {
 346         struct rte_pci_addr pci_addr; /* associated PCI address */
 347         uint32_t ports; /* physical ports bitfield. */
 348 } mlx5_dev[32];
 349
 350 /**
 351  * Get device index in mlx5_dev[] from PCI bus address.
 352  *
 353  * @param[in] pci_addr
 354  *   PCI bus address to look for.
 355  *
 356  * @return
 357  *   mlx5_dev[] index on success, -1 on failure.
 358  */
 359 static int
 360 mlx5_dev_idx(struct rte_pci_addr *pci_addr)
 361 {
 362         unsigned int i;
 363         int ret = -1;
 364
 365         assert(pci_addr != NULL);
 366         for (i = 0; (i != RTE_DIM(mlx5_dev)); ++i) {
 367                 if ((mlx5_dev[i].pci_addr.domain == pci_addr->domain) &&
 368                     (mlx5_dev[i].pci_addr.bus == pci_addr->bus) &&
 369                     (mlx5_dev[i].pci_addr.devid == pci_addr->devid) &&
 370                     (mlx5_dev[i].pci_addr.function == pci_addr->function))
 371                         return i;
 372                 if ((mlx5_dev[i].ports == 0) && (ret == -1))
 373                         ret = i;
 374         }
 375         return ret;
 376 }
 377
 378 /**
 379  * Verify and store value for device argument.
 380  *
 381  * @param[in] key
 382  *   Key argument to verify.
 383  * @param[in] val
 384  *   Value associated with key.
 385  * @param opaque
 386  *   User data.
 387  *
 388  * @return
 389  *   0 on success, a negative errno value otherwise and rte_errno is set.
 390  */
 391 static int
 392 mlx5_args_check(const char *key, const char *val, void *opaque)
 393 {
 394         struct mlx5_dev_config *config = opaque;
 395         unsigned long tmp;
 396
 397         errno = 0;
 398         tmp = strtoul(val, NULL, 0);
 399         if (errno) {
 400                 rte_errno = errno;
 401                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
 402                 return -rte_errno;
 403         }
 404         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
 405                 config->cqe_comp = !!tmp;
 406         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
 407                 config->txq_inline = tmp;
 408         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
 409                 config->txqs_inline = tmp;
 410         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
 411                 config->mps = !!tmp ? config->mps : 0;
 412         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
 413                 config->mpw_hdr_dseg = !!tmp;
 414         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
 415                 config->inline_max_packet_sz = tmp;
 416         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
 417                 config->tx_vec_en = !!tmp;
 418         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
 419                 config->rx_vec_en = !!tmp;
 420         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
 421                 config->l3_vxlan_en = !!tmp;
 422         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
 423                 config->vf_nl_en = !!tmp;
 424         } else {
 425                 DRV_LOG(WARNING, "%s: unknown parameter", key);
 426                 rte_errno = EINVAL;
 427                 return -rte_errno;
 428         }
 429         return 0;
 430 }
 431
 432 /**
 433  * Parse device parameters.
 434  *
 435  * @param config
 436  *   Pointer to device configuration structure.
 437  * @param devargs
 438  *   Device arguments structure.
 439  *
 440  * @return
 441  *   0 on success, a negative errno value otherwise and rte_errno is set.
 442  */
 443 static int
 444 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
 445 {
 446         const char **params = (const char *[]){
 447                 MLX5_RXQ_CQE_COMP_EN,
 448                 MLX5_TXQ_INLINE,
 449                 MLX5_TXQS_MIN_INLINE,
 450                 MLX5_TXQ_MPW_EN,
 451                 MLX5_TXQ_MPW_HDR_DSEG_EN,
 452                 MLX5_TXQ_MAX_INLINE_LEN,
 453                 MLX5_TX_VEC_EN,
 454                 MLX5_RX_VEC_EN,
 455                 MLX5_L3_VXLAN_EN,
 456                 MLX5_VF_NL_EN,
 457                 NULL,
 458         };
 459         struct rte_kvargs *kvlist;
 460         int ret = 0;
 461         int i;
 462
 463         if (devargs == NULL)
 464                 return 0;
 465         /* Following UGLY cast is done to pass checkpatch. */
 466         kvlist = rte_kvargs_parse(devargs->args, params);
 467         if (kvlist == NULL)
 468                 return 0;
 469         /* Process parameters. */
 470         for (i = 0; (params[i] != NULL); ++i) {
 471                 if (rte_kvargs_count(kvlist, params[i])) {
 472                         ret = rte_kvargs_process(kvlist, params[i],
 473                                                  mlx5_args_check, config);
 474                         if (ret) {
 475                                 rte_errno = EINVAL;
 476                                 rte_kvargs_free(kvlist);
 477                                 return -rte_errno;
 478                         }
 479                 }
 480         }
 481         rte_kvargs_free(kvlist);
 482         return 0;
 483 }
 484
 485 static struct rte_pci_driver mlx5_driver;
 486
 487 /*
 488  * Reserved UAR address space for TXQ UAR(hw doorbell) mapping, process
 489  * local resource used by both primary and secondary to avoid duplicate
 490  * reservation.
 491  * The space has to be available on both primary and secondary process,
 492  * TXQ UAR maps to this area using fixed mmap w/o double check.
 493  */
 494 static void *uar_base;
 495
 496 static int
 497 find_lower_va_bound(const struct rte_memseg_list *msl __rte_unused,
 498                 const struct rte_memseg *ms, void *arg)
 499 {
 500         void **addr = arg;
 501
 502         if (*addr == NULL)
 503                 *addr = ms->addr;
 504         else
 505                 *addr = RTE_MIN(*addr, ms->addr);
 506
 507         return 0;
 508 }
 509
 510 /**
 511  * Reserve UAR address space for primary process.
 512  *
 513  * @param[in] dev
 514  *   Pointer to Ethernet device.
 515  *
 516  * @return
 517  *   0 on success, a negative errno value otherwise and rte_errno is set.
 518  */
 519 static int
 520 mlx5_uar_init_primary(struct rte_eth_dev *dev)
 521 {
 522         struct priv *priv = dev->data->dev_private;
 523         void *addr = (void *)0;
 524
 525         if (uar_base) { /* UAR address space mapped. */
 526                 priv->uar_base = uar_base;
 527                 return 0;
 528         }
 529         /* find out lower bound of hugepage segments */
 530         rte_memseg_walk(find_lower_va_bound, &addr);
 531
 532         /* keep distance to hugepages to minimize potential conflicts. */
 533         addr = RTE_PTR_SUB(addr, MLX5_UAR_OFFSET + MLX5_UAR_SIZE);
 534         /* anonymous mmap, no real memory consumption. */
 535         addr = mmap(addr, MLX5_UAR_SIZE,
 536                     PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
 537         if (addr == MAP_FAILED) {
 538                 DRV_LOG(ERR,
 539                         "port %u failed to reserve UAR address space, please"
 540                         " adjust MLX5_UAR_SIZE or try --base-virtaddr",
 541                         dev->data->port_id);
 542                 rte_errno = ENOMEM;
 543                 return -rte_errno;
 544         }
 545         /* Accept either same addr or a new addr returned from mmap if target
 546          * range occupied.
 547          */
 548         DRV_LOG(INFO, "port %u reserved UAR address space: %p",
 549                 dev->data->port_id, addr);
 550         priv->uar_base = addr; /* for primary and secondary UAR re-mmap. */
 551         uar_base = addr; /* process local, don't reserve again. */
 552         return 0;
 553 }
 554
 555 /**
 556  * Reserve UAR address space for secondary process, align with
 557  * primary process.
 558  *
 559  * @param[in] dev
 560  *   Pointer to Ethernet device.
 561  *
 562  * @return
 563  *   0 on success, a negative errno value otherwise and rte_errno is set.
 564  */
 565 static int
 566 mlx5_uar_init_secondary(struct rte_eth_dev *dev)
 567 {
 568         struct priv *priv = dev->data->dev_private;
 569         void *addr;
 570
 571         assert(priv->uar_base);
 572         if (uar_base) { /* already reserved. */
 573                 assert(uar_base == priv->uar_base);
 574                 return 0;
 575         }
 576         /* anonymous mmap, no real memory consumption. */
 577         addr = mmap(priv->uar_base, MLX5_UAR_SIZE,
 578                     PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
 579         if (addr == MAP_FAILED) {
 580                 DRV_LOG(ERR, "port %u UAR mmap failed: %p size: %llu",
 581                         dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
 582                 rte_errno = ENXIO;
 583                 return -rte_errno;
 584         }
 585         if (priv->uar_base != addr) {
 586                 DRV_LOG(ERR,
 587                         "port %u UAR address %p size %llu occupied, please"
 588                         " adjust MLX5_UAR_OFFSET or try EAL parameter"
 589                         " --base-virtaddr",
 590                         dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
 591                 rte_errno = ENXIO;
 592                 return -rte_errno;
 593         }
 594         uar_base = addr; /* process local, don't reserve again */
 595         DRV_LOG(INFO, "port %u reserved UAR address space: %p",
 596                 dev->data->port_id, addr);
 597         return 0;
 598 }
 599
 600 /**
 601  * DPDK callback to register a PCI device.
 602  *
 603  * This function creates an Ethernet device for each port of a given
 604  * PCI device.
 605  *
 606  * @param[in] pci_drv
 607  *   PCI driver structure (mlx5_driver).
 608  * @param[in] pci_dev
 609  *   PCI device information.
 610  *
 611  * @return
 612  *   0 on success, a negative errno value otherwise and rte_errno is set.
 613  */
 614 static int
 615 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 616                struct rte_pci_device *pci_dev)
 617 {
 618         struct ibv_device **list = NULL;
 619         struct ibv_device *ibv_dev;
 620         int err = 0;
 621         struct ibv_context *attr_ctx = NULL;
 622         struct ibv_device_attr_ex device_attr;
 623         unsigned int vf;
 624         unsigned int mps;
 625         unsigned int cqe_comp;
 626         unsigned int tunnel_en = 0;
 627         unsigned int swp = 0;
 628         unsigned int verb_priorities = 0;
 629         int idx;
 630         int i;
 631         struct mlx5dv_context attrs_out = {0};
 632 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
 633         struct ibv_counter_set_description cs_desc;
 634 #endif
 635
 636         assert(pci_drv == &mlx5_driver);
 637         /* Get mlx5_dev[] index. */
 638         idx = mlx5_dev_idx(&pci_dev->addr);
 639         if (idx == -1) {
 640                 DRV_LOG(ERR, "this driver cannot support any more adapters");
 641                 err = ENOMEM;
 642                 goto error;
 643         }
 644         DRV_LOG(DEBUG, "using driver device index %d", idx);
 645         /* Save PCI address. */
 646         mlx5_dev[idx].pci_addr = pci_dev->addr;
 647         list = mlx5_glue->get_device_list(&i);
 648         if (list == NULL) {
 649                 assert(errno);
 650                 err = errno;
 651                 if (errno == ENOSYS)
 652                         DRV_LOG(ERR,
 653                                 "cannot list devices, is ib_uverbs loaded?");
 654                 goto error;
 655         }
 656         assert(i >= 0);
 657         /*
 658          * For each listed device, check related sysfs entry against
 659          * the provided PCI ID.
 660          */
 661         while (i != 0) {
 662                 struct rte_pci_addr pci_addr;
 663
 664                 --i;
 665                 DRV_LOG(DEBUG, "checking device \"%s\"", list[i]->name);
 666                 if (mlx5_ibv_device_to_pci_addr(list[i], &pci_addr))
 667                         continue;
 668                 if ((pci_dev->addr.domain != pci_addr.domain) ||
 669                     (pci_dev->addr.bus != pci_addr.bus) ||
 670                     (pci_dev->addr.devid != pci_addr.devid) ||
 671                     (pci_dev->addr.function != pci_addr.function))
 672                         continue;
 673                 DRV_LOG(INFO, "PCI information matches, using device \"%s\"",
 674                         list[i]->name);
 675                 vf = ((pci_dev->id.device_id ==
 676                        PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) ||
 677                       (pci_dev->id.device_id ==
 678                        PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) ||
 679                       (pci_dev->id.device_id ==
 680                        PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) ||
 681                       (pci_dev->id.device_id ==
 682                        PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF));
 683                 attr_ctx = mlx5_glue->open_device(list[i]);
 684                 rte_errno = errno;
 685                 err = rte_errno;
 686                 break;
 687         }
 688         if (attr_ctx == NULL) {
 689                 switch (err) {
 690                 case 0:
 691                         DRV_LOG(ERR,
 692                                 "cannot access device, is mlx5_ib loaded?");
 693                         err = ENODEV;
 694                         break;
 695                 case EINVAL:
 696                         DRV_LOG(ERR,
 697                                 "cannot use device, are drivers up to date?");
 698                         break;
 699                 }
 700                 goto error;
 701         }
 702         ibv_dev = list[i];
 703         DRV_LOG(DEBUG, "device opened");
 704 #ifdef HAVE_IBV_MLX5_MOD_SWP
 705         attrs_out.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
 706 #endif
 707         /*
 708          * Multi-packet send is supported by ConnectX-4 Lx PF as well
 709          * as all ConnectX-5 devices.
 710          */
 711 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
 712         attrs_out.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
 713 #endif
 714         mlx5_glue->dv_query_device(attr_ctx, &attrs_out);
 715         if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
 716                 if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
 717                         DRV_LOG(DEBUG, "enhanced MPW is supported");
 718                         mps = MLX5_MPW_ENHANCED;
 719                 } else {
 720                         DRV_LOG(DEBUG, "MPW is supported");
 721                         mps = MLX5_MPW;
 722                 }
 723         } else {
 724                 DRV_LOG(DEBUG, "MPW isn't supported");
 725                 mps = MLX5_MPW_DISABLED;
 726         }
 727 #ifdef HAVE_IBV_MLX5_MOD_SWP
 728         if (attrs_out.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
 729                 swp = attrs_out.sw_parsing_caps.sw_parsing_offloads;
 730         DRV_LOG(DEBUG, "SWP support: %u", swp);
 731 #endif
 732         if (RTE_CACHE_LINE_SIZE == 128 &&
 733             !(attrs_out.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
 734                 cqe_comp = 0;
 735         else
 736                 cqe_comp = 1;
 737 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
 738         if (attrs_out.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
 739                 tunnel_en = ((attrs_out.tunnel_offloads_caps &
 740                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
 741                              (attrs_out.tunnel_offloads_caps &
 742                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE));
 743         }
 744         DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
 745                 tunnel_en ? "" : "not ");
 746 #else
 747         DRV_LOG(WARNING,
 748                 "tunnel offloading disabled due to old OFED/rdma-core version");
 749 #endif
 750         err = mlx5_glue->query_device_ex(attr_ctx, NULL, &device_attr);
 751         if (err) {
 752                 DEBUG("ibv_query_device_ex() failed");
 753                 goto error;
 754         }
 755         DRV_LOG(INFO, "%u port(s) detected",
 756                 device_attr.orig_attr.phys_port_cnt);
 757         for (i = 0; i < device_attr.orig_attr.phys_port_cnt; i++) {
 758                 char name[RTE_ETH_NAME_MAX_LEN];
 759                 int len;
 760                 uint32_t port = i + 1; /* ports are indexed from one */
 761                 uint32_t test = (1 << i);
 762                 struct ibv_context *ctx = NULL;
 763                 struct ibv_port_attr port_attr;
 764                 struct ibv_pd *pd = NULL;
 765                 struct priv *priv = NULL;
 766                 struct rte_eth_dev *eth_dev = NULL;
 767                 struct ibv_device_attr_ex device_attr_ex;
 768                 struct ether_addr mac;
 769                 struct mlx5_dev_config config = {
 770                         .cqe_comp = cqe_comp,
 771                         .mps = mps,
 772                         .tunnel_en = tunnel_en,
 773                         .tx_vec_en = 1,
 774                         .rx_vec_en = 1,
 775                         .mpw_hdr_dseg = 0,
 776                         .txq_inline = MLX5_ARG_UNSET,
 777                         .txqs_inline = MLX5_ARG_UNSET,
 778                         .inline_max_packet_sz = MLX5_ARG_UNSET,
 779                         .vf_nl_en = 1,
 780                         .swp = !!swp,
 781                 };
 782
 783                 len = snprintf(name, sizeof(name), PCI_PRI_FMT,
 784                          pci_dev->addr.domain, pci_dev->addr.bus,
 785                          pci_dev->addr.devid, pci_dev->addr.function);
 786                 if (device_attr.orig_attr.phys_port_cnt > 1)
 787                         snprintf(name + len, sizeof(name), " port %u", i);
 788                 mlx5_dev[idx].ports |= test;
 789                 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
 790                         eth_dev = rte_eth_dev_attach_secondary(name);
 791                         if (eth_dev == NULL) {
 792                                 DRV_LOG(ERR, "can not attach rte ethdev");
 793                                 rte_errno = ENOMEM;
 794                                 err = rte_errno;
 795                                 goto error;
 796                         }
 797                         eth_dev->device = &pci_dev->device;
 798                         eth_dev->dev_ops = &mlx5_dev_sec_ops;
 799                         err = mlx5_uar_init_secondary(eth_dev);
 800                         if (err) {
 801                                 err = rte_errno;
 802                                 goto error;
 803                         }
 804                         /* Receive command fd from primary process */
 805                         err = mlx5_socket_connect(eth_dev);
 806                         if (err < 0) {
 807                                 err = rte_errno;
 808                                 goto error;
 809                         }
 810                         /* Remap UAR for Tx queues. */
 811                         err = mlx5_tx_uar_remap(eth_dev, err);
 812                         if (err) {
 813                                 err = rte_errno;
 814                                 goto error;
 815                         }
 816                         /*
 817                          * Ethdev pointer is still required as input since
 818                          * the primary device is not accessible from the
 819                          * secondary process.
 820                          */
 821                         eth_dev->rx_pkt_burst =
 822                                 mlx5_select_rx_function(eth_dev);
 823                         eth_dev->tx_pkt_burst =
 824                                 mlx5_select_tx_function(eth_dev);
 825                         continue;
 826                 }
 827                 DRV_LOG(DEBUG, "using port %u (%08" PRIx32 ")", port, test);
 828                 ctx = mlx5_glue->open_device(ibv_dev);
 829                 if (ctx == NULL) {
 830                         err = ENODEV;
 831                         goto port_error;
 832                 }
 833                 /* Check port status. */
 834                 err = mlx5_glue->query_port(ctx, port, &port_attr);
 835                 if (err) {
 836                         DRV_LOG(ERR, "port query failed: %s", strerror(err));
 837                         goto port_error;
 838                 }
 839                 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
 840                         DRV_LOG(ERR,
 841                                 "port %d is not configured in Ethernet mode",
 842                                 port);
 843                         err = EINVAL;
 844                         goto port_error;
 845                 }
 846                 if (port_attr.state != IBV_PORT_ACTIVE)
 847                         DRV_LOG(DEBUG, "port %d is not active: \"%s\" (%d)",
 848                                 port,
 849                                 mlx5_glue->port_state_str(port_attr.state),
 850                                 port_attr.state);
 851                 /* Allocate protection domain. */
 852                 pd = mlx5_glue->alloc_pd(ctx);
 853                 if (pd == NULL) {
 854                         DRV_LOG(ERR, "PD allocation failure");
 855                         err = ENOMEM;
 856                         goto port_error;
 857                 }
 858                 mlx5_dev[idx].ports |= test;
 859                 /* from rte_ethdev.c */
 860                 priv = rte_zmalloc("ethdev private structure",
 861                                    sizeof(*priv),
 862                                    RTE_CACHE_LINE_SIZE);
 863                 if (priv == NULL) {
 864                         DRV_LOG(ERR, "priv allocation failure");
 865                         err = ENOMEM;
 866                         goto port_error;
 867                 }
 868                 priv->ctx = ctx;
 869                 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path,
 870                         sizeof(priv->ibdev_path));
 871                 priv->device_attr = device_attr;
 872                 priv->port = port;
 873                 priv->pd = pd;
 874                 priv->mtu = ETHER_MTU;
 875                 err = mlx5_args(&config, pci_dev->device.devargs);
 876                 if (err) {
 877                         DRV_LOG(ERR, "failed to process device arguments: %s",
 878                                 strerror(err));
 879                         err = rte_errno;
 880                         goto port_error;
 881                 }
 882                 err = mlx5_glue->query_device_ex(ctx, NULL, &device_attr_ex);
 883                 if (err) {
 884                         DRV_LOG(ERR, "ibv_query_device_ex() failed");
 885                         goto port_error;
 886                 }
 887                 config.hw_csum = !!(device_attr_ex.device_cap_flags_ex &
 888                                     IBV_DEVICE_RAW_IP_CSUM);
 889                 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
 890                         (config.hw_csum ? "" : "not "));
 891 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
 892                 config.flow_counter_en = !!(device_attr.max_counter_sets);
 893                 mlx5_glue->describe_counter_set(ctx, 0, &cs_desc);
 894                 DRV_LOG(DEBUG,
 895                         "counter type = %d, num of cs = %ld, attributes = %d",
 896                         cs_desc.counter_type, cs_desc.num_of_cs,
 897                         cs_desc.attributes);
 898 #endif
 899                 config.ind_table_max_size =
 900                         device_attr_ex.rss_caps.max_rwq_indirection_table_size;
 901                 /* Remove this check once DPDK supports larger/variable
 902                  * indirection tables. */
 903                 if (config.ind_table_max_size >
 904                                 (unsigned int)ETH_RSS_RETA_SIZE_512)
 905                         config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
 906                 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
 907                         config.ind_table_max_size);
 908                 config.hw_vlan_strip = !!(device_attr_ex.raw_packet_caps &
 909                                          IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
 910                 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
 911                         (config.hw_vlan_strip ? "" : "not "));
 912
 913                 config.hw_fcs_strip = !!(device_attr_ex.raw_packet_caps &
 914                                          IBV_RAW_PACKET_CAP_SCATTER_FCS);
 915                 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
 916                         (config.hw_fcs_strip ? "" : "not "));
 917
 918 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
 919                 config.hw_padding = !!device_attr_ex.rx_pad_end_addr_align;
 920 #endif
 921                 DRV_LOG(DEBUG,
 922                         "hardware Rx end alignment padding is %ssupported",
 923                         (config.hw_padding ? "" : "not "));
 924                 config.vf = vf;
 925                 config.tso = ((device_attr_ex.tso_caps.max_tso > 0) &&
 926                               (device_attr_ex.tso_caps.supported_qpts &
 927                               (1 << IBV_QPT_RAW_PACKET)));
 928                 if (config.tso)
 929                         config.tso_max_payload_sz =
 930                                         device_attr_ex.tso_caps.max_tso;
 931                 if (config.mps && !mps) {
 932                         DRV_LOG(ERR,
 933                                 "multi-packet send not supported on this device"
 934                                 " (" MLX5_TXQ_MPW_EN ")");
 935                         err = ENOTSUP;
 936                         goto port_error;
 937                 }
 938                 DRV_LOG(INFO, "%s MPS is %s",
 939                         config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "",
 940                         config.mps != MLX5_MPW_DISABLED ? "enabled" :
 941                         "disabled");
 942                 if (config.cqe_comp && !cqe_comp) {
 943                         DRV_LOG(WARNING, "Rx CQE compression isn't supported");
 944                         config.cqe_comp = 0;
 945                 }
 946                 eth_dev = rte_eth_dev_allocate(name);
 947                 if (eth_dev == NULL) {
 948                         DRV_LOG(ERR, "can not allocate rte ethdev");
 949                         err = ENOMEM;
 950                         goto port_error;
 951                 }
 952                 eth_dev->data->dev_private = priv;
 953                 priv->dev_data = eth_dev->data;
 954                 eth_dev->data->mac_addrs = priv->mac;
 955                 eth_dev->device = &pci_dev->device;
 956                 rte_eth_copy_pci_info(eth_dev, pci_dev);
 957                 eth_dev->device->driver = &mlx5_driver.driver;
 958                 err = mlx5_uar_init_primary(eth_dev);
 959                 if (err) {
 960                         err = rte_errno;
 961                         goto port_error;
 962                 }
 963                 /* Configure the first MAC address by default. */
 964                 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
 965                         DRV_LOG(ERR,
 966                                 "port %u cannot get MAC address, is mlx5_en"
 967                                 " loaded? (errno: %s)",
 968                                 eth_dev->data->port_id, strerror(errno));
 969                         err = ENODEV;
 970                         goto port_error;
 971                 }
 972                 DRV_LOG(INFO,
 973                         "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
 974                         eth_dev->data->port_id,
 975                         mac.addr_bytes[0], mac.addr_bytes[1],
 976                         mac.addr_bytes[2], mac.addr_bytes[3],
 977                         mac.addr_bytes[4], mac.addr_bytes[5]);
 978 #ifndef NDEBUG
 979                 {
 980                         char ifname[IF_NAMESIZE];
 981
 982                         if (mlx5_get_ifname(eth_dev, &ifname) == 0)
 983                                 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
 984                                         eth_dev->data->port_id, ifname);
 985                         else
 986                                 DRV_LOG(DEBUG, "port %u ifname is unknown",
 987                                         eth_dev->data->port_id);
 988                 }
 989 #endif
 990                 /* Get actual MTU if possible. */
 991                 err = mlx5_get_mtu(eth_dev, &priv->mtu);
 992                 if (err) {
 993                         err = rte_errno;
 994                         goto port_error;
 995                 }
 996                 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
 997                         priv->mtu);
 998                 /*
 999                  * Initialize burst functions to prevent crashes before link-up.
1000                  */
1001                 eth_dev->rx_pkt_burst = removed_rx_burst;
1002                 eth_dev->tx_pkt_burst = removed_tx_burst;
1003                 eth_dev->dev_ops = &mlx5_dev_ops;
1004                 /* Register MAC address. */
1005                 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
1006                 priv->nl_socket = -1;
1007                 priv->nl_sn = 0;
1008                 if (vf && config.vf_nl_en) {
1009                         priv->nl_socket = mlx5_nl_init(RTMGRP_LINK);
1010                         if (priv->nl_socket < 0)
1011                                 priv->nl_socket = -1;
1012                         mlx5_nl_mac_addr_sync(eth_dev);
1013                 }
1014                 TAILQ_INIT(&priv->flows);
1015                 TAILQ_INIT(&priv->ctrl_flows);
1016                 /* Hint libmlx5 to use PMD allocator for data plane resources */
1017                 struct mlx5dv_ctx_allocators alctr = {
1018                         .alloc = &mlx5_alloc_verbs_buf,
1019                         .free = &mlx5_free_verbs_buf,
1020                         .data = priv,
1021                 };
1022                 mlx5_glue->dv_set_context_attr(ctx,
1023                                                MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
1024                                                (void *)((uintptr_t)&alctr));
1025                 /* Bring Ethernet device up. */
1026                 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
1027                         eth_dev->data->port_id);
1028                 mlx5_set_link_up(eth_dev);
1029                 /*
1030                  * Even though the interrupt handler is not installed yet,
1031                  * interrupts will still trigger on the asyn_fd from
1032                  * Verbs context returned by ibv_open_device().
1033                  */
1034                 mlx5_link_update(eth_dev, 0);
1035                 /* Store device configuration on private structure. */
1036                 priv->config = config;
1037                 /* Create drop queue. */
1038                 err = mlx5_flow_create_drop_queue(eth_dev);
1039                 if (err) {
1040                         DRV_LOG(ERR, "port %u drop queue allocation failed: %s",
1041                                 eth_dev->data->port_id, strerror(rte_errno));
1042                         err = rte_errno;
1043                         goto port_error;
1044                 }
1045                 /* Supported Verbs flow priority number detection. */
1046                 if (verb_priorities == 0)
1047                         verb_priorities = mlx5_get_max_verbs_prio(eth_dev);
1048                 if (verb_priorities < MLX5_VERBS_FLOW_PRIO_8) {
1049                         DRV_LOG(ERR, "port %u wrong Verbs flow priorities: %u",
1050                                 eth_dev->data->port_id, verb_priorities);
1051                         goto port_error;
1052                 }
1053                 priv->config.max_verbs_prio = verb_priorities;
1054                 continue;
1055 port_error:
1056                 if (priv)
1057                         rte_free(priv);
1058                 if (pd)
1059                         claim_zero(mlx5_glue->dealloc_pd(pd));
1060                 if (ctx)
1061                         claim_zero(mlx5_glue->close_device(ctx));
1062                 if (eth_dev && rte_eal_process_type() == RTE_PROC_PRIMARY)
1063                         rte_eth_dev_release_port(eth_dev);
1064                 break;
1065         }
1066         /*
1067          * XXX if something went wrong in the loop above, there is a resource
1068          * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as
1069          * long as the dpdk does not provide a way to deallocate a ethdev and a
1070          * way to enumerate the registered ethdevs to free the previous ones.
1071          */
1072         /* no port found, complain */
1073         if (!mlx5_dev[idx].ports) {
1074                 rte_errno = ENODEV;
1075                 err = rte_errno;
1076         }
1077 error:
1078         if (attr_ctx)
1079                 claim_zero(mlx5_glue->close_device(attr_ctx));
1080         if (list)
1081                 mlx5_glue->free_device_list(list);
1082         if (err) {
1083                 rte_errno = err;
1084                 return -rte_errno;
1085         }
1086         return 0;
1087 }
1088
1089 static const struct rte_pci_id mlx5_pci_id_map[] = {
1090         {
1091                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1092                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1093         },
1094         {
1095                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1096                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1097         },
1098         {
1099                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1100                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1101         },
1102         {
1103                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1104                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1105         },
1106         {
1107                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1108                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1109         },
1110         {
1111                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1112                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1113         },
1114         {
1115                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1116                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1117         },
1118         {
1119                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1120                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1121         },
1122         {
1123                 .vendor_id = 0
1124         }
1125 };
1126
1127 static struct rte_pci_driver mlx5_driver = {
1128         .driver = {
1129                 .name = MLX5_DRIVER_NAME
1130         },
1131         .id_table = mlx5_pci_id_map,
1132         .probe = mlx5_pci_probe,
1133         .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV,
1134 };
1135
1136 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1137
1138 /**
1139  * Suffix RTE_EAL_PMD_PATH with "-glue".
1140  *
1141  * This function performs a sanity check on RTE_EAL_PMD_PATH before
1142  * suffixing its last component.
1143  *
1144  * @param buf[out]
1145  *   Output buffer, should be large enough otherwise NULL is returned.
1146  * @param size
1147  *   Size of @p out.
1148  *
1149  * @return
1150  *   Pointer to @p buf or @p NULL in case suffix cannot be appended.
1151  */
1152 static char *
1153 mlx5_glue_path(char *buf, size_t size)
1154 {
1155         static const char *const bad[] = { "/", ".", "..", NULL };
1156         const char *path = RTE_EAL_PMD_PATH;
1157         size_t len = strlen(path);
1158         size_t off;
1159         int i;
1160
1161         while (len && path[len - 1] == '/')
1162                 --len;
1163         for (off = len; off && path[off - 1] != '/'; --off)
1164                 ;
1165         for (i = 0; bad[i]; ++i)
1166                 if (!strncmp(path + off, bad[i], (int)(len - off)))
1167                         goto error;
1168         i = snprintf(buf, size, "%.*s-glue", (int)len, path);
1169         if (i == -1 || (size_t)i >= size)
1170                 goto error;
1171         return buf;
1172 error:
1173         DRV_LOG(ERR,
1174                 "unable to append \"-glue\" to last component of"
1175                 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\"),"
1176                 " please re-configure DPDK");
1177         return NULL;
1178 }
1179
1180 /**
1181  * Initialization routine for run-time dependency on rdma-core.
1182  */
1183 static int
1184 mlx5_glue_init(void)
1185 {
1186         char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")];
1187         const char *path[] = {
1188                 /*
1189                  * A basic security check is necessary before trusting
1190                  * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH.
1191                  */
1192                 (geteuid() == getuid() && getegid() == getgid() ?
1193                  getenv("MLX5_GLUE_PATH") : NULL),
1194                 /*
1195                  * When RTE_EAL_PMD_PATH is set, use its glue-suffixed
1196                  * variant, otherwise let dlopen() look up libraries on its
1197                  * own.
1198                  */
1199                 (*RTE_EAL_PMD_PATH ?
1200                  mlx5_glue_path(glue_path, sizeof(glue_path)) : ""),
1201         };
1202         unsigned int i = 0;
1203         void *handle = NULL;
1204         void **sym;
1205         const char *dlmsg;
1206
1207         while (!handle && i != RTE_DIM(path)) {
1208                 const char *end;
1209                 size_t len;
1210                 int ret;
1211
1212                 if (!path[i]) {
1213                         ++i;
1214                         continue;
1215                 }
1216                 end = strpbrk(path[i], ":;");
1217                 if (!end)
1218                         end = path[i] + strlen(path[i]);
1219                 len = end - path[i];
1220                 ret = 0;
1221                 do {
1222                         char name[ret + 1];
1223
1224                         ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE,
1225                                        (int)len, path[i],
1226                                        (!len || *(end - 1) == '/') ? "" : "/");
1227                         if (ret == -1)
1228                                 break;
1229                         if (sizeof(name) != (size_t)ret + 1)
1230                                 continue;
1231                         DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"",
1232                                 name);
1233                         handle = dlopen(name, RTLD_LAZY);
1234                         break;
1235                 } while (1);
1236                 path[i] = end + 1;
1237                 if (!*end)
1238                         ++i;
1239         }
1240         if (!handle) {
1241                 rte_errno = EINVAL;
1242                 dlmsg = dlerror();
1243                 if (dlmsg)
1244                         DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg);
1245                 goto glue_error;
1246         }
1247         sym = dlsym(handle, "mlx5_glue");
1248         if (!sym || !*sym) {
1249                 rte_errno = EINVAL;
1250                 dlmsg = dlerror();
1251                 if (dlmsg)
1252                         DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg);
1253                 goto glue_error;
1254         }
1255         mlx5_glue = *sym;
1256         return 0;
1257 glue_error:
1258         if (handle)
1259                 dlclose(handle);
1260         DRV_LOG(WARNING,
1261                 "cannot initialize PMD due to missing run-time dependency on"
1262                 " rdma-core libraries (libibverbs, libmlx5)");
1263         return -rte_errno;
1264 }
1265
1266 #endif
1267
1268 /**
1269  * Driver initialization routine.
1270  */
1271 RTE_INIT(rte_mlx5_pmd_init);
1272 static void
1273 rte_mlx5_pmd_init(void)
1274 {
1275         /* Build the static tables for Verbs conversion. */
1276         mlx5_set_ptype_table();
1277         mlx5_set_cksum_table();
1278         mlx5_set_swp_types_table();
1279         /*
1280          * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
1281          * huge pages. Calling ibv_fork_init() during init allows
1282          * applications to use fork() safely for purposes other than
1283          * using this PMD, which is not supported in forked processes.
1284          */
1285         setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
1286         /* Match the size of Rx completion entry to the size of a cacheline. */
1287         if (RTE_CACHE_LINE_SIZE == 128)
1288                 setenv("MLX5_CQE_SIZE", "128", 0);
1289 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1290         if (mlx5_glue_init())
1291                 return;
1292         assert(mlx5_glue);
1293 #endif
1294 #ifndef NDEBUG
1295         /* Glue structure must not contain any NULL pointers. */
1296         {
1297                 unsigned int i;
1298
1299                 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i)
1300                         assert(((const void *const *)mlx5_glue)[i]);
1301         }
1302 #endif
1303         if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) {
1304                 DRV_LOG(ERR,
1305                         "rdma-core glue \"%s\" mismatch: \"%s\" is required",
1306                         mlx5_glue->version, MLX5_GLUE_VERSION);
1307                 return;
1308         }
1309         mlx5_glue->fork_init();
1310         rte_pci_register(&mlx5_driver);
1311 }
1312
1313 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1314 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1315 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");
1316
1317 /** Initialize driver log type. */
1318 RTE_INIT(vdev_netvsc_init_log)
1319 {
1320         mlx5_logtype = rte_log_register("pmd.net.mlx5");
1321         if (mlx5_logtype >= 0)
1322                 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
1323 }