drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12 #include <net/if.h>
  13 #include <sys/mman.h>
  14 #include <linux/rtnetlink.h>
  15
  16 /* Verbs header. */
  17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  18 #ifdef PEDANTIC
  19 #pragma GCC diagnostic ignored "-Wpedantic"
  20 #endif
  21 #include <infiniband/verbs.h>
  22 #ifdef PEDANTIC
  23 #pragma GCC diagnostic error "-Wpedantic"
  24 #endif
  25
  26 #include <rte_malloc.h>
  27 #include <rte_ethdev_driver.h>
  28 #include <rte_ethdev_pci.h>
  29 #include <rte_pci.h>
  30 #include <rte_bus_pci.h>
  31 #include <rte_common.h>
  32 #include <rte_kvargs.h>
  33 #include <rte_rwlock.h>
  34 #include <rte_spinlock.h>
  35 #include <rte_string_fns.h>
  36 #include <rte_alarm.h>
  37
  38 #include <mlx5_glue.h>
  39 #include <mlx5_devx_cmds.h>
  40 #include <mlx5_common.h>
  41 #include <mlx5_common_os.h>
  42 #include <mlx5_common_mp.h>
  43
  44 #include "mlx5_defs.h"
  45 #include "mlx5.h"
  46 #include "mlx5_utils.h"
  47 #include "mlx5_rxtx.h"
  48 #include "mlx5_autoconf.h"
  49 #include "mlx5_mr.h"
  50 #include "mlx5_flow.h"
  51 #include "rte_pmd_mlx5.h"
  52
  53 /* Device parameter to enable RX completion queue compression. */
  54 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  55
  56 /* Device parameter to enable RX completion entry padding to 128B. */
  57 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
  58
  59 /* Device parameter to enable padding Rx packet to cacheline size. */
  60 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  61
  62 /* Device parameter to enable Multi-Packet Rx queue. */
  63 #define MLX5_RX_MPRQ_EN "mprq_en"
  64
  65 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  66 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  67
  68 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  69 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  70
  71 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  72 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  73
  74 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  75 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  76
  77 /* Device parameter to configure inline send. Deprecated, ignored.*/
  78 #define MLX5_TXQ_INLINE "txq_inline"
  79
  80 /* Device parameter to limit packet size to inline with ordinary SEND. */
  81 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  82
  83 /* Device parameter to configure minimal data size to inline. */
  84 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  85
  86 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  87 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  88
  89 /*
  90  * Device parameter to configure the number of TX queues threshold for
  91  * enabling inline send.
  92  */
  93 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  94
  95 /*
  96  * Device parameter to configure the number of TX queues threshold for
  97  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  98  */
  99 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
 100
 101 /* Device parameter to enable multi-packet send WQEs. */
 102 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
 103
 104 /*
 105  * Device parameter to force doorbell register mapping
 106  * to non-cahed region eliminating the extra write memory barrier.
 107  */
 108 #define MLX5_TX_DB_NC "tx_db_nc"
 109
 110 /*
 111  * Device parameter to include 2 dsegs in the title WQEBB.
 112  * Deprecated, ignored.
 113  */
 114 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 115
 116 /*
 117  * Device parameter to limit the size of inlining packet.
 118  * Deprecated, ignored.
 119  */
 120 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 121
 122 /*
 123  * Device parameter to enable Tx scheduling on timestamps
 124  * and specify the packet pacing granularity in nanoseconds.
 125  */
 126 #define MLX5_TX_PP "tx_pp"
 127
 128 /*
 129  * Device parameter to specify skew in nanoseconds on Tx datapath,
 130  * it represents the time between SQ start WQE processing and
 131  * appearing actual packet data on the wire.
 132  */
 133 #define MLX5_TX_SKEW "tx_skew"
 134
 135 /*
 136  * Device parameter to enable hardware Tx vector.
 137  * Deprecated, ignored (no vectorized Tx routines anymore).
 138  */
 139 #define MLX5_TX_VEC_EN "tx_vec_en"
 140
 141 /* Device parameter to enable hardware Rx vector. */
 142 #define MLX5_RX_VEC_EN "rx_vec_en"
 143
 144 /* Allow L3 VXLAN flow creation. */
 145 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 146
 147 /* Activate DV E-Switch flow steering. */
 148 #define MLX5_DV_ESW_EN "dv_esw_en"
 149
 150 /* Activate DV flow steering. */
 151 #define MLX5_DV_FLOW_EN "dv_flow_en"
 152
 153 /* Enable extensive flow metadata support. */
 154 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 155
 156 /* Device parameter to let the user manage the lacp traffic of bonded device */
 157 #define MLX5_LACP_BY_USER "lacp_by_user"
 158
 159 /* Activate Netlink support in VF mode. */
 160 #define MLX5_VF_NL_EN "vf_nl_en"
 161
 162 /* Enable extending memsegs when creating a MR. */
 163 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 164
 165 /* Select port representors to instantiate. */
 166 #define MLX5_REPRESENTOR "representor"
 167
 168 /* Device parameter to configure the maximum number of dump files per queue. */
 169 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 170
 171 /* Configure timeout of LRO session (in microseconds). */
 172 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 173
 174 /*
 175  * Device parameter to configure the total data buffer size for a single
 176  * hairpin queue (logarithm value).
 177  */
 178 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 179
 180 /* Flow memory reclaim mode. */
 181 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 182
 183 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
 184
 185 /* Shared memory between primary and secondary processes. */
 186 struct mlx5_shared_data *mlx5_shared_data;
 187
 188 /* Spinlock for mlx5_shared_data allocation. */
 189 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
 190
 191 /* Process local data for secondary processes. */
 192 static struct mlx5_local_data mlx5_local_data;
 193
 194 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 195                                                 LIST_HEAD_INITIALIZER();
 196 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
 197
 198 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 199 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 200         {
 201                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 202                 .trunk_size = 64,
 203                 .grow_trunk = 3,
 204                 .grow_shift = 2,
 205                 .need_lock = 0,
 206                 .release_mem_en = 1,
 207                 .malloc = rte_malloc_socket,
 208                 .free = rte_free,
 209                 .type = "mlx5_encap_decap_ipool",
 210         },
 211         {
 212                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 213                 .trunk_size = 64,
 214                 .grow_trunk = 3,
 215                 .grow_shift = 2,
 216                 .need_lock = 0,
 217                 .release_mem_en = 1,
 218                 .malloc = rte_malloc_socket,
 219                 .free = rte_free,
 220                 .type = "mlx5_push_vlan_ipool",
 221         },
 222         {
 223                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 224                 .trunk_size = 64,
 225                 .grow_trunk = 3,
 226                 .grow_shift = 2,
 227                 .need_lock = 0,
 228                 .release_mem_en = 1,
 229                 .malloc = rte_malloc_socket,
 230                 .free = rte_free,
 231                 .type = "mlx5_tag_ipool",
 232         },
 233         {
 234                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 235                 .trunk_size = 64,
 236                 .grow_trunk = 3,
 237                 .grow_shift = 2,
 238                 .need_lock = 0,
 239                 .release_mem_en = 1,
 240                 .malloc = rte_malloc_socket,
 241                 .free = rte_free,
 242                 .type = "mlx5_port_id_ipool",
 243         },
 244         {
 245                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 246                 .trunk_size = 64,
 247                 .grow_trunk = 3,
 248                 .grow_shift = 2,
 249                 .need_lock = 0,
 250                 .release_mem_en = 1,
 251                 .malloc = rte_malloc_socket,
 252                 .free = rte_free,
 253                 .type = "mlx5_jump_ipool",
 254         },
 255 #endif
 256         {
 257                 .size = sizeof(struct mlx5_flow_meter),
 258                 .trunk_size = 64,
 259                 .grow_trunk = 3,
 260                 .grow_shift = 2,
 261                 .need_lock = 0,
 262                 .release_mem_en = 1,
 263                 .malloc = rte_malloc_socket,
 264                 .free = rte_free,
 265                 .type = "mlx5_meter_ipool",
 266         },
 267         {
 268                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 269                 .trunk_size = 64,
 270                 .grow_trunk = 3,
 271                 .grow_shift = 2,
 272                 .need_lock = 0,
 273                 .release_mem_en = 1,
 274                 .malloc = rte_malloc_socket,
 275                 .free = rte_free,
 276                 .type = "mlx5_mcp_ipool",
 277         },
 278         {
 279                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 280                 .trunk_size = 64,
 281                 .grow_trunk = 3,
 282                 .grow_shift = 2,
 283                 .need_lock = 0,
 284                 .release_mem_en = 1,
 285                 .malloc = rte_malloc_socket,
 286                 .free = rte_free,
 287                 .type = "mlx5_hrxq_ipool",
 288         },
 289         {
 290                 /*
 291                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 292                  * It set in run time according to PCI function configuration.
 293                  */
 294                 .size = 0,
 295                 .trunk_size = 64,
 296                 .grow_trunk = 3,
 297                 .grow_shift = 2,
 298                 .need_lock = 0,
 299                 .release_mem_en = 1,
 300                 .malloc = rte_malloc_socket,
 301                 .free = rte_free,
 302                 .type = "mlx5_flow_handle_ipool",
 303         },
 304         {
 305                 .size = sizeof(struct rte_flow),
 306                 .trunk_size = 4096,
 307                 .need_lock = 1,
 308                 .release_mem_en = 1,
 309                 .malloc = rte_malloc_socket,
 310                 .free = rte_free,
 311                 .type = "rte_flow_ipool",
 312         },
 313 };
 314
 315
 316 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 317 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 318
 319 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 320
 321 /**
 322  * Allocate ID pool structure.
 323  *
 324  * @param[in] max_id
 325  *   The maximum id can be allocated from the pool.
 326  *
 327  * @return
 328  *   Pointer to pool object, NULL value otherwise.
 329  */
 330 struct mlx5_flow_id_pool *
 331 mlx5_flow_id_pool_alloc(uint32_t max_id)
 332 {
 333         struct mlx5_flow_id_pool *pool;
 334         void *mem;
 335
 336         pool = rte_zmalloc("id pool allocation", sizeof(*pool),
 337                            RTE_CACHE_LINE_SIZE);
 338         if (!pool) {
 339                 DRV_LOG(ERR, "can't allocate id pool");
 340                 rte_errno  = ENOMEM;
 341                 return NULL;
 342         }
 343         mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
 344                           RTE_CACHE_LINE_SIZE);
 345         if (!mem) {
 346                 DRV_LOG(ERR, "can't allocate mem for id pool");
 347                 rte_errno  = ENOMEM;
 348                 goto error;
 349         }
 350         pool->free_arr = mem;
 351         pool->curr = pool->free_arr;
 352         pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
 353         pool->base_index = 0;
 354         pool->max_id = max_id;
 355         return pool;
 356 error:
 357         rte_free(pool);
 358         return NULL;
 359 }
 360
 361 /**
 362  * Release ID pool structure.
 363  *
 364  * @param[in] pool
 365  *   Pointer to flow id pool object to free.
 366  */
 367 void
 368 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
 369 {
 370         rte_free(pool->free_arr);
 371         rte_free(pool);
 372 }
 373
 374 /**
 375  * Generate ID.
 376  *
 377  * @param[in] pool
 378  *   Pointer to flow id pool.
 379  * @param[out] id
 380  *   The generated ID.
 381  *
 382  * @return
 383  *   0 on success, error value otherwise.
 384  */
 385 uint32_t
 386 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
 387 {
 388         if (pool->curr == pool->free_arr) {
 389                 if (pool->base_index == pool->max_id) {
 390                         rte_errno  = ENOMEM;
 391                         DRV_LOG(ERR, "no free id");
 392                         return -rte_errno;
 393                 }
 394                 *id = ++pool->base_index;
 395                 return 0;
 396         }
 397         *id = *(--pool->curr);
 398         return 0;
 399 }
 400
 401 /**
 402  * Release ID.
 403  *
 404  * @param[in] pool
 405  *   Pointer to flow id pool.
 406  * @param[out] id
 407  *   The generated ID.
 408  *
 409  * @return
 410  *   0 on success, error value otherwise.
 411  */
 412 uint32_t
 413 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
 414 {
 415         uint32_t size;
 416         uint32_t size2;
 417         void *mem;
 418
 419         if (pool->curr == pool->last) {
 420                 size = pool->curr - pool->free_arr;
 421                 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
 422                 MLX5_ASSERT(size2 > size);
 423                 mem = rte_malloc("", size2 * sizeof(uint32_t), 0);
 424                 if (!mem) {
 425                         DRV_LOG(ERR, "can't allocate mem for id pool");
 426                         rte_errno  = ENOMEM;
 427                         return -rte_errno;
 428                 }
 429                 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
 430                 rte_free(pool->free_arr);
 431                 pool->free_arr = mem;
 432                 pool->curr = pool->free_arr + size;
 433                 pool->last = pool->free_arr + size2;
 434         }
 435         *pool->curr = id;
 436         pool->curr++;
 437         return 0;
 438 }
 439
 440 /**
 441  * Initialize the shared aging list information per port.
 442  *
 443  * @param[in] sh
 444  *   Pointer to mlx5_dev_ctx_shared object.
 445  */
 446 static void
 447 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 448 {
 449         uint32_t i;
 450         struct mlx5_age_info *age_info;
 451
 452         for (i = 0; i < sh->max_port; i++) {
 453                 age_info = &sh->port[i].age_info;
 454                 age_info->flags = 0;
 455                 TAILQ_INIT(&age_info->aged_counters);
 456                 rte_spinlock_init(&age_info->aged_sl);
 457                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 458         }
 459 }
 460
 461 /**
 462  * Initialize the counters management structure.
 463  *
 464  * @param[in] sh
 465  *   Pointer to mlx5_dev_ctx_shared object to free
 466  */
 467 static void
 468 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 469 {
 470         int i;
 471
 472         memset(&sh->cmng, 0, sizeof(sh->cmng));
 473         TAILQ_INIT(&sh->cmng.flow_counters);
 474         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 475                 sh->cmng.ccont[i].min_id = MLX5_CNT_BATCH_OFFSET;
 476                 sh->cmng.ccont[i].max_id = -1;
 477                 sh->cmng.ccont[i].last_pool_idx = POOL_IDX_INVALID;
 478                 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
 479                 rte_spinlock_init(&sh->cmng.ccont[i].resize_sl);
 480                 TAILQ_INIT(&sh->cmng.ccont[i].counters);
 481                 rte_spinlock_init(&sh->cmng.ccont[i].csl);
 482         }
 483 }
 484
 485 /**
 486  * Destroy all the resources allocated for a counter memory management.
 487  *
 488  * @param[in] mng
 489  *   Pointer to the memory management structure.
 490  */
 491 static void
 492 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 493 {
 494         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 495
 496         LIST_REMOVE(mng, next);
 497         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 498         claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
 499         rte_free(mem);
 500 }
 501
 502 /**
 503  * Close and release all the resources of the counters management.
 504  *
 505  * @param[in] sh
 506  *   Pointer to mlx5_dev_ctx_shared object to free.
 507  */
 508 static void
 509 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 510 {
 511         struct mlx5_counter_stats_mem_mng *mng;
 512         int i;
 513         int j;
 514         int retries = 1024;
 515
 516         rte_errno = 0;
 517         while (--retries) {
 518                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 519                 if (rte_errno != EINPROGRESS)
 520                         break;
 521                 rte_pause();
 522         }
 523         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 524                 struct mlx5_flow_counter_pool *pool;
 525                 uint32_t batch = !!(i > 1);
 526
 527                 if (!sh->cmng.ccont[i].pools)
 528                         continue;
 529                 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 530                 while (pool) {
 531                         if (batch && pool->min_dcs)
 532                                 claim_zero(mlx5_devx_cmd_destroy
 533                                                                (pool->min_dcs));
 534                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 535                                 if (MLX5_POOL_GET_CNT(pool, j)->action)
 536                                         claim_zero
 537                                          (mlx5_glue->destroy_flow_action
 538                                           (MLX5_POOL_GET_CNT
 539                                           (pool, j)->action));
 540                                 if (!batch && MLX5_GET_POOL_CNT_EXT
 541                                     (pool, j)->dcs)
 542                                         claim_zero(mlx5_devx_cmd_destroy
 543                                                    (MLX5_GET_POOL_CNT_EXT
 544                                                     (pool, j)->dcs));
 545                         }
 546                         TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, next);
 547                         rte_free(pool);
 548                         pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 549                 }
 550                 rte_free(sh->cmng.ccont[i].pools);
 551         }
 552         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 553         while (mng) {
 554                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 555                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 556         }
 557         memset(&sh->cmng, 0, sizeof(sh->cmng));
 558 }
 559
 560 /**
 561  * Initialize the flow resources' indexed mempool.
 562  *
 563  * @param[in] sh
 564  *   Pointer to mlx5_dev_ctx_shared object.
 565  * @param[in] sh
 566  *   Pointer to user dev config.
 567  */
 568 static void
 569 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 570                        const struct mlx5_dev_config *config)
 571 {
 572         uint8_t i;
 573         struct mlx5_indexed_pool_config cfg;
 574
 575         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 576                 cfg = mlx5_ipool_cfg[i];
 577                 switch (i) {
 578                 default:
 579                         break;
 580                 /*
 581                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 582                  * according to PCI function flow configuration.
 583                  */
 584                 case MLX5_IPOOL_MLX5_FLOW:
 585                         cfg.size = config->dv_flow_en ?
 586                                 sizeof(struct mlx5_flow_handle) :
 587                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 588                         break;
 589                 }
 590                 if (config->reclaim_mode)
 591                         cfg.release_mem_en = 1;
 592                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 593         }
 594 }
 595
 596 /**
 597  * Release the flow resources' indexed mempool.
 598  *
 599  * @param[in] sh
 600  *   Pointer to mlx5_dev_ctx_shared object.
 601  */
 602 static void
 603 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 604 {
 605         uint8_t i;
 606
 607         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 608                 mlx5_ipool_destroy(sh->ipool[i]);
 609 }
 610
 611 /*
 612  * Check if dynamic flex parser for eCPRI already exists.
 613  *
 614  * @param dev
 615  *   Pointer to Ethernet device structure.
 616  *
 617  * @return
 618  *   true on exists, false on not.
 619  */
 620 bool
 621 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
 622 {
 623         struct mlx5_priv *priv = dev->data->dev_private;
 624         struct mlx5_flex_parser_profiles *prf =
 625                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 626
 627         return !!prf->obj;
 628 }
 629
 630 /*
 631  * Allocation of a flex parser for eCPRI. Once created, this parser related
 632  * resources will be held until the device is closed.
 633  *
 634  * @param dev
 635  *   Pointer to Ethernet device structure.
 636  *
 637  * @return
 638  *   0 on success, a negative errno value otherwise and rte_errno is set.
 639  */
 640 int
 641 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
 642 {
 643         struct mlx5_priv *priv = dev->data->dev_private;
 644         struct mlx5_flex_parser_profiles *prf =
 645                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 646
 647         (void)prf;
 648         return 0;
 649 }
 650
 651 /**
 652  * Allocate shared device context. If there is multiport device the
 653  * master and representors will share this context, if there is single
 654  * port dedicated device, the context will be used by only given
 655  * port due to unification.
 656  *
 657  * Routine first searches the context for the specified device name,
 658  * if found the shared context assumed and reference counter is incremented.
 659  * If no context found the new one is created and initialized with specified
 660  * device context and parameters.
 661  *
 662  * @param[in] spawn
 663  *   Pointer to the device attributes (name, port, etc).
 664  * @param[in] config
 665  *   Pointer to device configuration structure.
 666  *
 667  * @return
 668  *   Pointer to mlx5_dev_ctx_shared object on success,
 669  *   otherwise NULL and rte_errno is set.
 670  */
 671 struct mlx5_dev_ctx_shared *
 672 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
 673                            const struct mlx5_dev_config *config)
 674 {
 675         struct mlx5_dev_ctx_shared *sh;
 676         int err = 0;
 677         uint32_t i;
 678         struct mlx5_devx_tis_attr tis_attr = { 0 };
 679
 680         MLX5_ASSERT(spawn);
 681         /* Secondary process should not create the shared context. */
 682         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 683         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 684         /* Search for IB context by device name. */
 685         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
 686                 if (!strcmp(sh->ibdev_name,
 687                         mlx5_os_get_dev_device_name(spawn->phys_dev))) {
 688                         sh->refcnt++;
 689                         goto exit;
 690                 }
 691         }
 692         /* No device found, we have to create new shared context. */
 693         MLX5_ASSERT(spawn->max_port);
 694         sh = rte_zmalloc("ethdev shared ib context",
 695                          sizeof(struct mlx5_dev_ctx_shared) +
 696                          spawn->max_port *
 697                          sizeof(struct mlx5_dev_shared_port),
 698                          RTE_CACHE_LINE_SIZE);
 699         if (!sh) {
 700                 DRV_LOG(ERR, "shared context allocation failure");
 701                 rte_errno  = ENOMEM;
 702                 goto exit;
 703         }
 704         err = mlx5_os_open_device(spawn, config, sh);
 705         if (!sh->ctx)
 706                 goto error;
 707         err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
 708         if (err) {
 709                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
 710                 goto error;
 711         }
 712         sh->refcnt = 1;
 713         sh->max_port = spawn->max_port;
 714         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
 715                 sizeof(sh->ibdev_name) - 1);
 716         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
 717                 sizeof(sh->ibdev_path) - 1);
 718         /*
 719          * Setting port_id to max unallowed value means
 720          * there is no interrupt subhandler installed for
 721          * the given port index i.
 722          */
 723         for (i = 0; i < sh->max_port; i++) {
 724                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 725                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
 726         }
 727         sh->pd = mlx5_glue->alloc_pd(sh->ctx);
 728         if (sh->pd == NULL) {
 729                 DRV_LOG(ERR, "PD allocation failure");
 730                 err = ENOMEM;
 731                 goto error;
 732         }
 733         if (sh->devx) {
 734                 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
 735                 if (err) {
 736                         DRV_LOG(ERR, "Fail to extract pdn from PD");
 737                         goto error;
 738                 }
 739                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
 740                 if (!sh->td) {
 741                         DRV_LOG(ERR, "TD allocation failure");
 742                         err = ENOMEM;
 743                         goto error;
 744                 }
 745                 tis_attr.transport_domain = sh->td->id;
 746                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
 747                 if (!sh->tis) {
 748                         DRV_LOG(ERR, "TIS allocation failure");
 749                         err = ENOMEM;
 750                         goto error;
 751                 }
 752                 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, 0);
 753                 if (!sh->tx_uar) {
 754                         DRV_LOG(ERR, "Failed to allocate DevX UAR.");
 755                         err = ENOMEM;
 756                         goto error;
 757                 }
 758         }
 759         sh->flow_id_pool = mlx5_flow_id_pool_alloc
 760                                         ((1 << HAIRPIN_FLOW_ID_BITS) - 1);
 761         if (!sh->flow_id_pool) {
 762                 DRV_LOG(ERR, "can't create flow id pool");
 763                 err = ENOMEM;
 764                 goto error;
 765         }
 766 #ifndef RTE_ARCH_64
 767         /* Initialize UAR access locks for 32bit implementations. */
 768         rte_spinlock_init(&sh->uar_lock_cq);
 769         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
 770                 rte_spinlock_init(&sh->uar_lock[i]);
 771 #endif
 772         /*
 773          * Once the device is added to the list of memory event
 774          * callback, its global MR cache table cannot be expanded
 775          * on the fly because of deadlock. If it overflows, lookup
 776          * should be done by searching MR list linearly, which is slow.
 777          *
 778          * At this point the device is not added to the memory
 779          * event list yet, context is just being created.
 780          */
 781         err = mlx5_mr_btree_init(&sh->share_cache.cache,
 782                                  MLX5_MR_BTREE_CACHE_N * 2,
 783                                  spawn->pci_dev->device.numa_node);
 784         if (err) {
 785                 err = rte_errno;
 786                 goto error;
 787         }
 788         mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
 789                               &sh->share_cache.dereg_mr_cb);
 790         mlx5_os_dev_shared_handler_install(sh);
 791         sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
 792         if (!sh->cnt_id_tbl) {
 793                 err = rte_errno;
 794                 goto error;
 795         }
 796         mlx5_flow_aging_init(sh);
 797         mlx5_flow_counters_mng_init(sh);
 798         mlx5_flow_ipool_create(sh, config);
 799         /* Add device to memory callback list. */
 800         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 801         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
 802                          sh, mem_event_cb);
 803         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 804         /* Add context to the global device list. */
 805         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
 806 exit:
 807         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 808         return sh;
 809 error:
 810         pthread_mutex_destroy(&sh->txpp.mutex);
 811         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 812         MLX5_ASSERT(sh);
 813         if (sh->cnt_id_tbl) {
 814                 mlx5_l3t_destroy(sh->cnt_id_tbl);
 815                 sh->cnt_id_tbl = NULL;
 816         }
 817         if (sh->tx_uar) {
 818                 mlx5_glue->devx_free_uar(sh->tx_uar);
 819                 sh->tx_uar = NULL;
 820         }
 821         if (sh->tis)
 822                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 823         if (sh->td)
 824                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 825         if (sh->pd)
 826                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 827         if (sh->ctx)
 828                 claim_zero(mlx5_glue->close_device(sh->ctx));
 829         if (sh->flow_id_pool)
 830                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 831         rte_free(sh);
 832         MLX5_ASSERT(err > 0);
 833         rte_errno = err;
 834         return NULL;
 835 }
 836
 837 /**
 838  * Free shared IB device context. Decrement counter and if zero free
 839  * all allocated resources and close handles.
 840  *
 841  * @param[in] sh
 842  *   Pointer to mlx5_dev_ctx_shared object to free
 843  */
 844 void
 845 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
 846 {
 847         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 848 #ifdef RTE_LIBRTE_MLX5_DEBUG
 849         /* Check the object presence in the list. */
 850         struct mlx5_dev_ctx_shared *lctx;
 851
 852         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
 853                 if (lctx == sh)
 854                         break;
 855         MLX5_ASSERT(lctx);
 856         if (lctx != sh) {
 857                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
 858                 goto exit;
 859         }
 860 #endif
 861         MLX5_ASSERT(sh);
 862         MLX5_ASSERT(sh->refcnt);
 863         /* Secondary process should not free the shared context. */
 864         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 865         if (--sh->refcnt)
 866                 goto exit;
 867         /* Remove from memory callback device list. */
 868         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 869         LIST_REMOVE(sh, mem_event_cb);
 870         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 871         /* Release created Memory Regions. */
 872         mlx5_mr_release_cache(&sh->share_cache);
 873         /* Remove context from the global device list. */
 874         LIST_REMOVE(sh, next);
 875         /*
 876          *  Ensure there is no async event handler installed.
 877          *  Only primary process handles async device events.
 878          **/
 879         mlx5_flow_counters_mng_close(sh);
 880         mlx5_flow_ipool_destroy(sh);
 881         mlx5_os_dev_shared_handler_uninstall(sh);
 882         if (sh->cnt_id_tbl) {
 883                 mlx5_l3t_destroy(sh->cnt_id_tbl);
 884                 sh->cnt_id_tbl = NULL;
 885         }
 886         if (sh->tx_uar) {
 887                 mlx5_glue->devx_free_uar(sh->tx_uar);
 888                 sh->tx_uar = NULL;
 889         }
 890         if (sh->pd)
 891                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 892         if (sh->tis)
 893                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 894         if (sh->td)
 895                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 896         if (sh->ctx)
 897                 claim_zero(mlx5_glue->close_device(sh->ctx));
 898         if (sh->flow_id_pool)
 899                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 900         pthread_mutex_destroy(&sh->txpp.mutex);
 901         rte_free(sh);
 902 exit:
 903         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 904 }
 905
 906 /**
 907  * Destroy table hash list and all the root entries per domain.
 908  *
 909  * @param[in] priv
 910  *   Pointer to the private device data structure.
 911  */
 912 void
 913 mlx5_free_table_hash_list(struct mlx5_priv *priv)
 914 {
 915         struct mlx5_dev_ctx_shared *sh = priv->sh;
 916         struct mlx5_flow_tbl_data_entry *tbl_data;
 917         union mlx5_flow_tbl_key table_key = {
 918                 {
 919                         .table_id = 0,
 920                         .reserved = 0,
 921                         .domain = 0,
 922                         .direction = 0,
 923                 }
 924         };
 925         struct mlx5_hlist_entry *pos;
 926
 927         if (!sh->flow_tbls)
 928                 return;
 929         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 930         if (pos) {
 931                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 932                                         entry);
 933                 MLX5_ASSERT(tbl_data);
 934                 mlx5_hlist_remove(sh->flow_tbls, pos);
 935                 rte_free(tbl_data);
 936         }
 937         table_key.direction = 1;
 938         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 939         if (pos) {
 940                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 941                                         entry);
 942                 MLX5_ASSERT(tbl_data);
 943                 mlx5_hlist_remove(sh->flow_tbls, pos);
 944                 rte_free(tbl_data);
 945         }
 946         table_key.direction = 0;
 947         table_key.domain = 1;
 948         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 949         if (pos) {
 950                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 951                                         entry);
 952                 MLX5_ASSERT(tbl_data);
 953                 mlx5_hlist_remove(sh->flow_tbls, pos);
 954                 rte_free(tbl_data);
 955         }
 956         mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
 957 }
 958
 959 /**
 960  * Initialize flow table hash list and create the root tables entry
 961  * for each domain.
 962  *
 963  * @param[in] priv
 964  *   Pointer to the private device data structure.
 965  *
 966  * @return
 967  *   Zero on success, positive error code otherwise.
 968  */
 969 int
 970 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
 971 {
 972         struct mlx5_dev_ctx_shared *sh = priv->sh;
 973         char s[MLX5_HLIST_NAMESIZE];
 974         int err = 0;
 975
 976         MLX5_ASSERT(sh);
 977         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
 978         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
 979         if (!sh->flow_tbls) {
 980                 DRV_LOG(ERR, "flow tables with hash creation failed.");
 981                 err = ENOMEM;
 982                 return err;
 983         }
 984 #ifndef HAVE_MLX5DV_DR
 985         /*
 986          * In case we have not DR support, the zero tables should be created
 987          * because DV expect to see them even if they cannot be created by
 988          * RDMA-CORE.
 989          */
 990         union mlx5_flow_tbl_key table_key = {
 991                 {
 992                         .table_id = 0,
 993                         .reserved = 0,
 994                         .domain = 0,
 995                         .direction = 0,
 996                 }
 997         };
 998         struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL,
 999                                                           sizeof(*tbl_data), 0);
1000
1001         if (!tbl_data) {
1002                 err = ENOMEM;
1003                 goto error;
1004         }
1005         tbl_data->entry.key = table_key.v64;
1006         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1007         if (err)
1008                 goto error;
1009         rte_atomic32_init(&tbl_data->tbl.refcnt);
1010         rte_atomic32_inc(&tbl_data->tbl.refcnt);
1011         table_key.direction = 1;
1012         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
1013         if (!tbl_data) {
1014                 err = ENOMEM;
1015                 goto error;
1016         }
1017         tbl_data->entry.key = table_key.v64;
1018         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1019         if (err)
1020                 goto error;
1021         rte_atomic32_init(&tbl_data->tbl.refcnt);
1022         rte_atomic32_inc(&tbl_data->tbl.refcnt);
1023         table_key.direction = 0;
1024         table_key.domain = 1;
1025         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
1026         if (!tbl_data) {
1027                 err = ENOMEM;
1028                 goto error;
1029         }
1030         tbl_data->entry.key = table_key.v64;
1031         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1032         if (err)
1033                 goto error;
1034         rte_atomic32_init(&tbl_data->tbl.refcnt);
1035         rte_atomic32_inc(&tbl_data->tbl.refcnt);
1036         return err;
1037 error:
1038         mlx5_free_table_hash_list(priv);
1039 #endif /* HAVE_MLX5DV_DR */
1040         return err;
1041 }
1042
1043 /**
1044  * Initialize shared data between primary and secondary process.
1045  *
1046  * A memzone is reserved by primary process and secondary processes attach to
1047  * the memzone.
1048  *
1049  * @return
1050  *   0 on success, a negative errno value otherwise and rte_errno is set.
1051  */
1052 static int
1053 mlx5_init_shared_data(void)
1054 {
1055         const struct rte_memzone *mz;
1056         int ret = 0;
1057
1058         rte_spinlock_lock(&mlx5_shared_data_lock);
1059         if (mlx5_shared_data == NULL) {
1060                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
1061                         /* Allocate shared memory. */
1062                         mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
1063                                                  sizeof(*mlx5_shared_data),
1064                                                  SOCKET_ID_ANY, 0);
1065                         if (mz == NULL) {
1066                                 DRV_LOG(ERR,
1067                                         "Cannot allocate mlx5 shared data");
1068                                 ret = -rte_errno;
1069                                 goto error;
1070                         }
1071                         mlx5_shared_data = mz->addr;
1072                         memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
1073                         rte_spinlock_init(&mlx5_shared_data->lock);
1074                 } else {
1075                         /* Lookup allocated shared memory. */
1076                         mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
1077                         if (mz == NULL) {
1078                                 DRV_LOG(ERR,
1079                                         "Cannot attach mlx5 shared data");
1080                                 ret = -rte_errno;
1081                                 goto error;
1082                         }
1083                         mlx5_shared_data = mz->addr;
1084                         memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
1085                 }
1086         }
1087 error:
1088         rte_spinlock_unlock(&mlx5_shared_data_lock);
1089         return ret;
1090 }
1091
1092 /**
1093  * Retrieve integer value from environment variable.
1094  *
1095  * @param[in] name
1096  *   Environment variable name.
1097  *
1098  * @return
1099  *   Integer value, 0 if the variable is not set.
1100  */
1101 int
1102 mlx5_getenv_int(const char *name)
1103 {
1104         const char *val = getenv(name);
1105
1106         if (val == NULL)
1107                 return 0;
1108         return atoi(val);
1109 }
1110
1111 /**
1112  * DPDK callback to add udp tunnel port
1113  *
1114  * @param[in] dev
1115  *   A pointer to eth_dev
1116  * @param[in] udp_tunnel
1117  *   A pointer to udp tunnel
1118  *
1119  * @return
1120  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1121  */
1122 int
1123 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1124                          struct rte_eth_udp_tunnel *udp_tunnel)
1125 {
1126         MLX5_ASSERT(udp_tunnel != NULL);
1127         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1128             udp_tunnel->udp_port == 4789)
1129                 return 0;
1130         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1131             udp_tunnel->udp_port == 4790)
1132                 return 0;
1133         return -ENOTSUP;
1134 }
1135
1136 /**
1137  * Initialize process private data structure.
1138  *
1139  * @param dev
1140  *   Pointer to Ethernet device structure.
1141  *
1142  * @return
1143  *   0 on success, a negative errno value otherwise and rte_errno is set.
1144  */
1145 int
1146 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1147 {
1148         struct mlx5_priv *priv = dev->data->dev_private;
1149         struct mlx5_proc_priv *ppriv;
1150         size_t ppriv_size;
1151
1152         /*
1153          * UAR register table follows the process private structure. BlueFlame
1154          * registers for Tx queues are stored in the table.
1155          */
1156         ppriv_size =
1157                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1158         ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
1159                                   RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1160         if (!ppriv) {
1161                 rte_errno = ENOMEM;
1162                 return -rte_errno;
1163         }
1164         ppriv->uar_table_sz = ppriv_size;
1165         dev->process_private = ppriv;
1166         return 0;
1167 }
1168
1169 /**
1170  * Un-initialize process private data structure.
1171  *
1172  * @param dev
1173  *   Pointer to Ethernet device structure.
1174  */
1175 static void
1176 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1177 {
1178         if (!dev->process_private)
1179                 return;
1180         rte_free(dev->process_private);
1181         dev->process_private = NULL;
1182 }
1183
1184 /**
1185  * DPDK callback to close the device.
1186  *
1187  * Destroy all queues and objects, free memory.
1188  *
1189  * @param dev
1190  *   Pointer to Ethernet device structure.
1191  */
1192 void
1193 mlx5_dev_close(struct rte_eth_dev *dev)
1194 {
1195         struct mlx5_priv *priv = dev->data->dev_private;
1196         unsigned int i;
1197         int ret;
1198
1199         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1200                 /* Check if process_private released. */
1201                 if (!dev->process_private)
1202                         return;
1203                 mlx5_tx_uar_uninit_secondary(dev);
1204                 mlx5_proc_priv_uninit(dev);
1205                 rte_eth_dev_release_port(dev);
1206                 return;
1207         }
1208         if (!priv->sh)
1209                 return;
1210         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1211                 dev->data->port_id,
1212                 ((priv->sh->ctx != NULL) ?
1213                 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1214         /*
1215          * If default mreg copy action is removed at the stop stage,
1216          * the search will return none and nothing will be done anymore.
1217          */
1218         mlx5_flow_stop_default(dev);
1219         mlx5_traffic_disable(dev);
1220         /*
1221          * If all the flows are already flushed in the device stop stage,
1222          * then this will return directly without any action.
1223          */
1224         mlx5_flow_list_flush(dev, &priv->flows, true);
1225         mlx5_flow_meter_flush(dev, NULL);
1226         /* Free the intermediate buffers for flow creation. */
1227         mlx5_flow_free_intermediate(dev);
1228         /* Prevent crashes when queues are still in use. */
1229         dev->rx_pkt_burst = removed_rx_burst;
1230         dev->tx_pkt_burst = removed_tx_burst;
1231         rte_wmb();
1232         /* Disable datapath on secondary process. */
1233         mlx5_mp_req_stop_rxtx(dev);
1234         if (priv->rxqs != NULL) {
1235                 /* XXX race condition if mlx5_rx_burst() is still running. */
1236                 usleep(1000);
1237                 for (i = 0; (i != priv->rxqs_n); ++i)
1238                         mlx5_rxq_release(dev, i);
1239                 priv->rxqs_n = 0;
1240                 priv->rxqs = NULL;
1241         }
1242         if (priv->txqs != NULL) {
1243                 /* XXX race condition if mlx5_tx_burst() is still running. */
1244                 usleep(1000);
1245                 for (i = 0; (i != priv->txqs_n); ++i)
1246                         mlx5_txq_release(dev, i);
1247                 priv->txqs_n = 0;
1248                 priv->txqs = NULL;
1249         }
1250         mlx5_proc_priv_uninit(dev);
1251         if (priv->mreg_cp_tbl)
1252                 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1253         mlx5_mprq_free_mp(dev);
1254         mlx5_os_free_shared_dr(priv);
1255         if (priv->rss_conf.rss_key != NULL)
1256                 rte_free(priv->rss_conf.rss_key);
1257         if (priv->reta_idx != NULL)
1258                 rte_free(priv->reta_idx);
1259         if (priv->config.vf)
1260                 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1261                                        dev->data->mac_addrs,
1262                                        MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1263         if (priv->nl_socket_route >= 0)
1264                 close(priv->nl_socket_route);
1265         if (priv->nl_socket_rdma >= 0)
1266                 close(priv->nl_socket_rdma);
1267         if (priv->vmwa_context)
1268                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1269         ret = mlx5_hrxq_verify(dev);
1270         if (ret)
1271                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1272                         dev->data->port_id);
1273         ret = mlx5_ind_table_obj_verify(dev);
1274         if (ret)
1275                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1276                         dev->data->port_id);
1277         ret = mlx5_rxq_obj_verify(dev);
1278         if (ret)
1279                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1280                         dev->data->port_id);
1281         ret = mlx5_rxq_verify(dev);
1282         if (ret)
1283                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1284                         dev->data->port_id);
1285         ret = mlx5_txq_obj_verify(dev);
1286         if (ret)
1287                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1288                         dev->data->port_id);
1289         ret = mlx5_txq_verify(dev);
1290         if (ret)
1291                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1292                         dev->data->port_id);
1293         ret = mlx5_flow_verify(dev);
1294         if (ret)
1295                 DRV_LOG(WARNING, "port %u some flows still remain",
1296                         dev->data->port_id);
1297         /*
1298          * Free the shared context in last turn, because the cleanup
1299          * routines above may use some shared fields, like
1300          * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1301          * ifindex if Netlink fails.
1302          */
1303         mlx5_free_shared_dev_ctx(priv->sh);
1304         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1305                 unsigned int c = 0;
1306                 uint16_t port_id;
1307
1308                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1309                         struct mlx5_priv *opriv =
1310                                 rte_eth_devices[port_id].data->dev_private;
1311
1312                         if (!opriv ||
1313                             opriv->domain_id != priv->domain_id ||
1314                             &rte_eth_devices[port_id] == dev)
1315                                 continue;
1316                         ++c;
1317                         break;
1318                 }
1319                 if (!c)
1320                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1321         }
1322         memset(priv, 0, sizeof(*priv));
1323         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1324         /*
1325          * Reset mac_addrs to NULL such that it is not freed as part of
1326          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1327          * it is freed when dev_private is freed.
1328          */
1329         dev->data->mac_addrs = NULL;
1330 }
1331
1332 /**
1333  * Verify and store value for device argument.
1334  *
1335  * @param[in] key
1336  *   Key argument to verify.
1337  * @param[in] val
1338  *   Value associated with key.
1339  * @param opaque
1340  *   User data.
1341  *
1342  * @return
1343  *   0 on success, a negative errno value otherwise and rte_errno is set.
1344  */
1345 static int
1346 mlx5_args_check(const char *key, const char *val, void *opaque)
1347 {
1348         struct mlx5_dev_config *config = opaque;
1349         unsigned long mod;
1350         signed long tmp;
1351
1352         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1353         if (!strcmp(MLX5_REPRESENTOR, key))
1354                 return 0;
1355         errno = 0;
1356         tmp = strtol(val, NULL, 0);
1357         if (errno) {
1358                 rte_errno = errno;
1359                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1360                 return -rte_errno;
1361         }
1362         if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1363                 /* Negative values are acceptable for some keys only. */
1364                 rte_errno = EINVAL;
1365                 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1366                 return -rte_errno;
1367         }
1368         mod = tmp >= 0 ? tmp : -tmp;
1369         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1370                 config->cqe_comp = !!tmp;
1371         } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1372                 config->cqe_pad = !!tmp;
1373         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1374                 config->hw_padding = !!tmp;
1375         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1376                 config->mprq.enabled = !!tmp;
1377         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1378                 config->mprq.stride_num_n = tmp;
1379         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1380                 config->mprq.stride_size_n = tmp;
1381         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1382                 config->mprq.max_memcpy_len = tmp;
1383         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1384                 config->mprq.min_rxqs_num = tmp;
1385         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1386                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1387                                  " converted to txq_inline_max", key);
1388                 config->txq_inline_max = tmp;
1389         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1390                 config->txq_inline_max = tmp;
1391         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1392                 config->txq_inline_min = tmp;
1393         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1394                 config->txq_inline_mpw = tmp;
1395         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1396                 config->txqs_inline = tmp;
1397         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1398                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1399         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1400                 config->mps = !!tmp;
1401         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1402                 if (tmp != MLX5_TXDB_CACHED &&
1403                     tmp != MLX5_TXDB_NCACHED &&
1404                     tmp != MLX5_TXDB_HEURISTIC) {
1405                         DRV_LOG(ERR, "invalid Tx doorbell "
1406                                      "mapping parameter");
1407                         rte_errno = EINVAL;
1408                         return -rte_errno;
1409                 }
1410                 config->dbnc = tmp;
1411         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1412                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1413         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1414                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1415                                  " converted to txq_inline_mpw", key);
1416                 config->txq_inline_mpw = tmp;
1417         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1418                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1419         } else if (strcmp(MLX5_TX_PP, key) == 0) {
1420                 if (!mod) {
1421                         DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1422                         rte_errno = EINVAL;
1423                         return -rte_errno;
1424                 }
1425                 config->tx_pp = tmp;
1426         } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1427                 config->tx_skew = tmp;
1428         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1429                 config->rx_vec_en = !!tmp;
1430         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1431                 config->l3_vxlan_en = !!tmp;
1432         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1433                 config->vf_nl_en = !!tmp;
1434         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1435                 config->dv_esw_en = !!tmp;
1436         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1437                 config->dv_flow_en = !!tmp;
1438         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1439                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1440                     tmp != MLX5_XMETA_MODE_META16 &&
1441                     tmp != MLX5_XMETA_MODE_META32) {
1442                         DRV_LOG(ERR, "invalid extensive "
1443                                      "metadata parameter");
1444                         rte_errno = EINVAL;
1445                         return -rte_errno;
1446                 }
1447                 config->dv_xmeta_en = tmp;
1448         } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1449                 config->lacp_by_user = !!tmp;
1450         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1451                 config->mr_ext_memseg_en = !!tmp;
1452         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1453                 config->max_dump_files_num = tmp;
1454         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1455                 config->lro.timeout = tmp;
1456         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1457                 DRV_LOG(DEBUG, "class argument is %s.", val);
1458         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1459                 config->log_hp_size = tmp;
1460         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1461                 if (tmp != MLX5_RCM_NONE &&
1462                     tmp != MLX5_RCM_LIGHT &&
1463                     tmp != MLX5_RCM_AGGR) {
1464                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1465                         rte_errno = EINVAL;
1466                         return -rte_errno;
1467                 }
1468                 config->reclaim_mode = tmp;
1469         } else {
1470                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1471                 rte_errno = EINVAL;
1472                 return -rte_errno;
1473         }
1474         return 0;
1475 }
1476
1477 /**
1478  * Parse device parameters.
1479  *
1480  * @param config
1481  *   Pointer to device configuration structure.
1482  * @param devargs
1483  *   Device arguments structure.
1484  *
1485  * @return
1486  *   0 on success, a negative errno value otherwise and rte_errno is set.
1487  */
1488 int
1489 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1490 {
1491         const char **params = (const char *[]){
1492                 MLX5_RXQ_CQE_COMP_EN,
1493                 MLX5_RXQ_CQE_PAD_EN,
1494                 MLX5_RXQ_PKT_PAD_EN,
1495                 MLX5_RX_MPRQ_EN,
1496                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1497                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1498                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1499                 MLX5_RXQS_MIN_MPRQ,
1500                 MLX5_TXQ_INLINE,
1501                 MLX5_TXQ_INLINE_MIN,
1502                 MLX5_TXQ_INLINE_MAX,
1503                 MLX5_TXQ_INLINE_MPW,
1504                 MLX5_TXQS_MIN_INLINE,
1505                 MLX5_TXQS_MAX_VEC,
1506                 MLX5_TXQ_MPW_EN,
1507                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1508                 MLX5_TXQ_MAX_INLINE_LEN,
1509                 MLX5_TX_DB_NC,
1510                 MLX5_TX_PP,
1511                 MLX5_TX_SKEW,
1512                 MLX5_TX_VEC_EN,
1513                 MLX5_RX_VEC_EN,
1514                 MLX5_L3_VXLAN_EN,
1515                 MLX5_VF_NL_EN,
1516                 MLX5_DV_ESW_EN,
1517                 MLX5_DV_FLOW_EN,
1518                 MLX5_DV_XMETA_EN,
1519                 MLX5_LACP_BY_USER,
1520                 MLX5_MR_EXT_MEMSEG_EN,
1521                 MLX5_REPRESENTOR,
1522                 MLX5_MAX_DUMP_FILES_NUM,
1523                 MLX5_LRO_TIMEOUT_USEC,
1524                 MLX5_CLASS_ARG_NAME,
1525                 MLX5_HP_BUF_SIZE,
1526                 MLX5_RECLAIM_MEM,
1527                 NULL,
1528         };
1529         struct rte_kvargs *kvlist;
1530         int ret = 0;
1531         int i;
1532
1533         if (devargs == NULL)
1534                 return 0;
1535         /* Following UGLY cast is done to pass checkpatch. */
1536         kvlist = rte_kvargs_parse(devargs->args, params);
1537         if (kvlist == NULL) {
1538                 rte_errno = EINVAL;
1539                 return -rte_errno;
1540         }
1541         /* Process parameters. */
1542         for (i = 0; (params[i] != NULL); ++i) {
1543                 if (rte_kvargs_count(kvlist, params[i])) {
1544                         ret = rte_kvargs_process(kvlist, params[i],
1545                                                  mlx5_args_check, config);
1546                         if (ret) {
1547                                 rte_errno = EINVAL;
1548                                 rte_kvargs_free(kvlist);
1549                                 return -rte_errno;
1550                         }
1551                 }
1552         }
1553         rte_kvargs_free(kvlist);
1554         return 0;
1555 }
1556
1557 /**
1558  * PMD global initialization.
1559  *
1560  * Independent from individual device, this function initializes global
1561  * per-PMD data structures distinguishing primary and secondary processes.
1562  * Hence, each initialization is called once per a process.
1563  *
1564  * @return
1565  *   0 on success, a negative errno value otherwise and rte_errno is set.
1566  */
1567 int
1568 mlx5_init_once(void)
1569 {
1570         struct mlx5_shared_data *sd;
1571         struct mlx5_local_data *ld = &mlx5_local_data;
1572         int ret = 0;
1573
1574         if (mlx5_init_shared_data())
1575                 return -rte_errno;
1576         sd = mlx5_shared_data;
1577         MLX5_ASSERT(sd);
1578         rte_spinlock_lock(&sd->lock);
1579         switch (rte_eal_process_type()) {
1580         case RTE_PROC_PRIMARY:
1581                 if (sd->init_done)
1582                         break;
1583                 LIST_INIT(&sd->mem_event_cb_list);
1584                 rte_rwlock_init(&sd->mem_event_rwlock);
1585                 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1586                                                 mlx5_mr_mem_event_cb, NULL);
1587                 ret = mlx5_mp_init_primary(MLX5_MP_NAME,
1588                                            mlx5_mp_primary_handle);
1589                 if (ret)
1590                         goto out;
1591                 sd->init_done = true;
1592                 break;
1593         case RTE_PROC_SECONDARY:
1594                 if (ld->init_done)
1595                         break;
1596                 ret = mlx5_mp_init_secondary(MLX5_MP_NAME,
1597                                              mlx5_mp_secondary_handle);
1598                 if (ret)
1599                         goto out;
1600                 ++sd->secondary_cnt;
1601                 ld->init_done = true;
1602                 break;
1603         default:
1604                 break;
1605         }
1606 out:
1607         rte_spinlock_unlock(&sd->lock);
1608         return ret;
1609 }
1610
1611 /**
1612  * Configures the minimal amount of data to inline into WQE
1613  * while sending packets.
1614  *
1615  * - the txq_inline_min has the maximal priority, if this
1616  *   key is specified in devargs
1617  * - if DevX is enabled the inline mode is queried from the
1618  *   device (HCA attributes and NIC vport context if needed).
1619  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1620  *   and none (0 bytes) for other NICs
1621  *
1622  * @param spawn
1623  *   Verbs device parameters (name, port, switch_info) to spawn.
1624  * @param config
1625  *   Device configuration parameters.
1626  */
1627 void
1628 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1629                     struct mlx5_dev_config *config)
1630 {
1631         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1632                 /* Application defines size of inlined data explicitly. */
1633                 switch (spawn->pci_dev->id.device_id) {
1634                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1635                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1636                         if (config->txq_inline_min <
1637                                        (int)MLX5_INLINE_HSIZE_L2) {
1638                                 DRV_LOG(DEBUG,
1639                                         "txq_inline_mix aligned to minimal"
1640                                         " ConnectX-4 required value %d",
1641                                         (int)MLX5_INLINE_HSIZE_L2);
1642                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1643                         }
1644                         break;
1645                 }
1646                 goto exit;
1647         }
1648         if (config->hca_attr.eth_net_offloads) {
1649                 /* We have DevX enabled, inline mode queried successfully. */
1650                 switch (config->hca_attr.wqe_inline_mode) {
1651                 case MLX5_CAP_INLINE_MODE_L2:
1652                         /* outer L2 header must be inlined. */
1653                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1654                         goto exit;
1655                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1656                         /* No inline data are required by NIC. */
1657                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1658                         config->hw_vlan_insert =
1659                                 config->hca_attr.wqe_vlan_insert;
1660                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1661                         goto exit;
1662                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1663                         /* inline mode is defined by NIC vport context. */
1664                         if (!config->hca_attr.eth_virt)
1665                                 break;
1666                         switch (config->hca_attr.vport_inline_mode) {
1667                         case MLX5_INLINE_MODE_NONE:
1668                                 config->txq_inline_min =
1669                                         MLX5_INLINE_HSIZE_NONE;
1670                                 goto exit;
1671                         case MLX5_INLINE_MODE_L2:
1672                                 config->txq_inline_min =
1673                                         MLX5_INLINE_HSIZE_L2;
1674                                 goto exit;
1675                         case MLX5_INLINE_MODE_IP:
1676                                 config->txq_inline_min =
1677                                         MLX5_INLINE_HSIZE_L3;
1678                                 goto exit;
1679                         case MLX5_INLINE_MODE_TCP_UDP:
1680                                 config->txq_inline_min =
1681                                         MLX5_INLINE_HSIZE_L4;
1682                                 goto exit;
1683                         case MLX5_INLINE_MODE_INNER_L2:
1684                                 config->txq_inline_min =
1685                                         MLX5_INLINE_HSIZE_INNER_L2;
1686                                 goto exit;
1687                         case MLX5_INLINE_MODE_INNER_IP:
1688                                 config->txq_inline_min =
1689                                         MLX5_INLINE_HSIZE_INNER_L3;
1690                                 goto exit;
1691                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
1692                                 config->txq_inline_min =
1693                                         MLX5_INLINE_HSIZE_INNER_L4;
1694                                 goto exit;
1695                         }
1696                 }
1697         }
1698         /*
1699          * We get here if we are unable to deduce
1700          * inline data size with DevX. Try PCI ID
1701          * to determine old NICs.
1702          */
1703         switch (spawn->pci_dev->id.device_id) {
1704         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1705         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1706         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1707         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1708                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1709                 config->hw_vlan_insert = 0;
1710                 break;
1711         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1712         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1713         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1714         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1715                 /*
1716                  * These NICs support VLAN insertion from WQE and
1717                  * report the wqe_vlan_insert flag. But there is the bug
1718                  * and PFC control may be broken, so disable feature.
1719                  */
1720                 config->hw_vlan_insert = 0;
1721                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1722                 break;
1723         default:
1724                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1725                 break;
1726         }
1727 exit:
1728         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1729 }
1730
1731 /**
1732  * Configures the metadata mask fields in the shared context.
1733  *
1734  * @param [in] dev
1735  *   Pointer to Ethernet device.
1736  */
1737 void
1738 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1739 {
1740         struct mlx5_priv *priv = dev->data->dev_private;
1741         struct mlx5_dev_ctx_shared *sh = priv->sh;
1742         uint32_t meta, mark, reg_c0;
1743
1744         reg_c0 = ~priv->vport_meta_mask;
1745         switch (priv->config.dv_xmeta_en) {
1746         case MLX5_XMETA_MODE_LEGACY:
1747                 meta = UINT32_MAX;
1748                 mark = MLX5_FLOW_MARK_MASK;
1749                 break;
1750         case MLX5_XMETA_MODE_META16:
1751                 meta = reg_c0 >> rte_bsf32(reg_c0);
1752                 mark = MLX5_FLOW_MARK_MASK;
1753                 break;
1754         case MLX5_XMETA_MODE_META32:
1755                 meta = UINT32_MAX;
1756                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1757                 break;
1758         default:
1759                 meta = 0;
1760                 mark = 0;
1761                 MLX5_ASSERT(false);
1762                 break;
1763         }
1764         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1765                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1766                                  sh->dv_mark_mask, mark);
1767         else
1768                 sh->dv_mark_mask = mark;
1769         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1770                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1771                                  sh->dv_meta_mask, meta);
1772         else
1773                 sh->dv_meta_mask = meta;
1774         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1775                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1776                                  sh->dv_meta_mask, reg_c0);
1777         else
1778                 sh->dv_regc0_mask = reg_c0;
1779         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1780         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1781         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1782         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1783 }
1784
1785 int
1786 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1787 {
1788         static const char *const dynf_names[] = {
1789                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1790                 RTE_MBUF_DYNFLAG_METADATA_NAME,
1791                 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
1792         };
1793         unsigned int i;
1794
1795         if (n < RTE_DIM(dynf_names))
1796                 return -ENOMEM;
1797         for (i = 0; i < RTE_DIM(dynf_names); i++) {
1798                 if (names[i] == NULL)
1799                         return -EINVAL;
1800                 strcpy(names[i], dynf_names[i]);
1801         }
1802         return RTE_DIM(dynf_names);
1803 }
1804
1805 /**
1806  * Comparison callback to sort device data.
1807  *
1808  * This is meant to be used with qsort().
1809  *
1810  * @param a[in]
1811  *   Pointer to pointer to first data object.
1812  * @param b[in]
1813  *   Pointer to pointer to second data object.
1814  *
1815  * @return
1816  *   0 if both objects are equal, less than 0 if the first argument is less
1817  *   than the second, greater than 0 otherwise.
1818  */
1819 int
1820 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1821                               struct mlx5_dev_config *config)
1822 {
1823         struct mlx5_dev_ctx_shared *sh = priv->sh;
1824         struct mlx5_dev_config *sh_conf = NULL;
1825         uint16_t port_id;
1826
1827         MLX5_ASSERT(sh);
1828         /* Nothing to compare for the single/first device. */
1829         if (sh->refcnt == 1)
1830                 return 0;
1831         /* Find the device with shared context. */
1832         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1833                 struct mlx5_priv *opriv =
1834                         rte_eth_devices[port_id].data->dev_private;
1835
1836                 if (opriv && opriv != priv && opriv->sh == sh) {
1837                         sh_conf = &opriv->config;
1838                         break;
1839                 }
1840         }
1841         if (!sh_conf)
1842                 return 0;
1843         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1844                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1845                              " for shared %s context", sh->ibdev_name);
1846                 rte_errno = EINVAL;
1847                 return rte_errno;
1848         }
1849         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1850                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1851                              " for shared %s context", sh->ibdev_name);
1852                 rte_errno = EINVAL;
1853                 return rte_errno;
1854         }
1855         return 0;
1856 }
1857
1858 /**
1859  * Look for the ethernet device belonging to mlx5 driver.
1860  *
1861  * @param[in] port_id
1862  *   port_id to start looking for device.
1863  * @param[in] pci_dev
1864  *   Pointer to the hint PCI device. When device is being probed
1865  *   the its siblings (master and preceding representors might
1866  *   not have assigned driver yet (because the mlx5_os_pci_probe()
1867  *   is not completed yet, for this case match on hint PCI
1868  *   device may be used to detect sibling device.
1869  *
1870  * @return
1871  *   port_id of found device, RTE_MAX_ETHPORT if not found.
1872  */
1873 uint16_t
1874 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
1875 {
1876         while (port_id < RTE_MAX_ETHPORTS) {
1877                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
1878
1879                 if (dev->state != RTE_ETH_DEV_UNUSED &&
1880                     dev->device &&
1881                     (dev->device == &pci_dev->device ||
1882                      (dev->device->driver &&
1883                      dev->device->driver->name &&
1884                      !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
1885                         break;
1886                 port_id++;
1887         }
1888         if (port_id >= RTE_MAX_ETHPORTS)
1889                 return RTE_MAX_ETHPORTS;
1890         return port_id;
1891 }
1892
1893 /**
1894  * DPDK callback to remove a PCI device.
1895  *
1896  * This function removes all Ethernet devices belong to a given PCI device.
1897  *
1898  * @param[in] pci_dev
1899  *   Pointer to the PCI device.
1900  *
1901  * @return
1902  *   0 on success, the function cannot fail.
1903  */
1904 static int
1905 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1906 {
1907         uint16_t port_id;
1908
1909         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
1910                 /*
1911                  * mlx5_dev_close() is not registered to secondary process,
1912                  * call the close function explicitly for secondary process.
1913                  */
1914                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
1915                         mlx5_dev_close(&rte_eth_devices[port_id]);
1916                 else
1917                         rte_eth_dev_close(port_id);
1918         }
1919         return 0;
1920 }
1921
1922 static const struct rte_pci_id mlx5_pci_id_map[] = {
1923         {
1924                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1925                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1926         },
1927         {
1928                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1929                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1930         },
1931         {
1932                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1933                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1934         },
1935         {
1936                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1937                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1938         },
1939         {
1940                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1941                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1942         },
1943         {
1944                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1945                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1946         },
1947         {
1948                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1949                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1950         },
1951         {
1952                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1953                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1954         },
1955         {
1956                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1957                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
1958         },
1959         {
1960                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1961                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
1962         },
1963         {
1964                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1965                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
1966         },
1967         {
1968                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1969                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
1970         },
1971         {
1972                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1973                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
1974         },
1975         {
1976                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1977                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
1978         },
1979         {
1980                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1981                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
1982         },
1983         {
1984                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1985                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
1986         },
1987         {
1988                 .vendor_id = 0
1989         }
1990 };
1991
1992 struct rte_pci_driver mlx5_driver = {
1993         .driver = {
1994                 .name = MLX5_DRIVER_NAME
1995         },
1996         .id_table = mlx5_pci_id_map,
1997         .probe = mlx5_os_pci_probe,
1998         .remove = mlx5_pci_remove,
1999         .dma_map = mlx5_dma_map,
2000         .dma_unmap = mlx5_dma_unmap,
2001         .drv_flags = PCI_DRV_FLAGS,
2002 };
2003
2004 /* Initialize driver log type. */
2005 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
2006
2007 /**
2008  * Driver initialization routine.
2009  */
2010 RTE_INIT(rte_mlx5_pmd_init)
2011 {
2012         /* Build the static tables for Verbs conversion. */
2013         mlx5_set_ptype_table();
2014         mlx5_set_cksum_table();
2015         mlx5_set_swp_types_table();
2016         if (mlx5_glue)
2017                 rte_pci_register(&mlx5_driver);
2018 }
2019
2020 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2021 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2022 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");