drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <assert.h>
  10 #include <dlfcn.h>
  11 #include <stdint.h>
  12 #include <stdlib.h>
  13 #include <errno.h>
  14 #include <net/if.h>
  15 #include <sys/mman.h>
  16 #include <linux/rtnetlink.h>
  17
  18 /* Verbs header. */
  19 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  20 #ifdef PEDANTIC
  21 #pragma GCC diagnostic ignored "-Wpedantic"
  22 #endif
  23 #include <infiniband/verbs.h>
  24 #ifdef PEDANTIC
  25 #pragma GCC diagnostic error "-Wpedantic"
  26 #endif
  27
  28 #include <rte_malloc.h>
  29 #include <rte_ethdev_driver.h>
  30 #include <rte_ethdev_pci.h>
  31 #include <rte_pci.h>
  32 #include <rte_bus_pci.h>
  33 #include <rte_common.h>
  34 #include <rte_config.h>
  35 #include <rte_eal_memconfig.h>
  36 #include <rte_kvargs.h>
  37
  38 #include "mlx5.h"
  39 #include "mlx5_utils.h"
  40 #include "mlx5_rxtx.h"
  41 #include "mlx5_autoconf.h"
  42 #include "mlx5_defs.h"
  43 #include "mlx5_glue.h"
  44
  45 /* Device parameter to enable RX completion queue compression. */
  46 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  47
  48 /* Device parameter to configure inline send. */
  49 #define MLX5_TXQ_INLINE "txq_inline"
  50
  51 /*
  52  * Device parameter to configure the number of TX queues threshold for
  53  * enabling inline send.
  54  */
  55 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  56
  57 /* Device parameter to enable multi-packet send WQEs. */
  58 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  59
  60 /* Device parameter to include 2 dsegs in the title WQEBB. */
  61 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
  62
  63 /* Device parameter to limit the size of inlining packet. */
  64 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
  65
  66 /* Device parameter to enable hardware Tx vector. */
  67 #define MLX5_TX_VEC_EN "tx_vec_en"
  68
  69 /* Device parameter to enable hardware Rx vector. */
  70 #define MLX5_RX_VEC_EN "rx_vec_en"
  71
  72 /* Allow L3 VXLAN flow creation. */
  73 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
  74
  75 /* Activate Netlink support in VF mode. */
  76 #define MLX5_VF_NL_EN "vf_nl_en"
  77
  78 #ifndef HAVE_IBV_MLX5_MOD_MPW
  79 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
  80 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
  81 #endif
  82
  83 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
  84 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
  85 #endif
  86
  87 /** Driver-specific log messages type. */
  88 int mlx5_logtype;
  89
  90 /**
  91  * Retrieve integer value from environment variable.
  92  *
  93  * @param[in] name
  94  *   Environment variable name.
  95  *
  96  * @return
  97  *   Integer value, 0 if the variable is not set.
  98  */
  99 int
 100 mlx5_getenv_int(const char *name)
 101 {
 102         const char *val = getenv(name);
 103
 104         if (val == NULL)
 105                 return 0;
 106         return atoi(val);
 107 }
 108
 109 /**
 110  * Verbs callback to allocate a memory. This function should allocate the space
 111  * according to the size provided residing inside a huge page.
 112  * Please note that all allocation must respect the alignment from libmlx5
 113  * (i.e. currently sysconf(_SC_PAGESIZE)).
 114  *
 115  * @param[in] size
 116  *   The size in bytes of the memory to allocate.
 117  * @param[in] data
 118  *   A pointer to the callback data.
 119  *
 120  * @return
 121  *   Allocated buffer, NULL otherwise and rte_errno is set.
 122  */
 123 static void *
 124 mlx5_alloc_verbs_buf(size_t size, void *data)
 125 {
 126         struct priv *priv = data;
 127         void *ret;
 128         size_t alignment = sysconf(_SC_PAGESIZE);
 129         unsigned int socket = SOCKET_ID_ANY;
 130
 131         if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
 132                 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
 133
 134                 socket = ctrl->socket;
 135         } else if (priv->verbs_alloc_ctx.type ==
 136                    MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
 137                 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
 138
 139                 socket = ctrl->socket;
 140         }
 141         assert(data != NULL);
 142         ret = rte_malloc_socket(__func__, size, alignment, socket);
 143         if (!ret && size)
 144                 rte_errno = ENOMEM;
 145         return ret;
 146 }
 147
 148 /**
 149  * Verbs callback to free a memory.
 150  *
 151  * @param[in] ptr
 152  *   A pointer to the memory to free.
 153  * @param[in] data
 154  *   A pointer to the callback data.
 155  */
 156 static void
 157 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
 158 {
 159         assert(data != NULL);
 160         rte_free(ptr);
 161 }
 162
 163 /**
 164  * DPDK callback to close the device.
 165  *
 166  * Destroy all queues and objects, free memory.
 167  *
 168  * @param dev
 169  *   Pointer to Ethernet device structure.
 170  */
 171 static void
 172 mlx5_dev_close(struct rte_eth_dev *dev)
 173 {
 174         struct priv *priv = dev->data->dev_private;
 175         unsigned int i;
 176         int ret;
 177
 178         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
 179                 dev->data->port_id,
 180                 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
 181         /* In case mlx5_dev_stop() has not been called. */
 182         mlx5_dev_interrupt_handler_uninstall(dev);
 183         mlx5_traffic_disable(dev);
 184         /* Prevent crashes when queues are still in use. */
 185         dev->rx_pkt_burst = removed_rx_burst;
 186         dev->tx_pkt_burst = removed_tx_burst;
 187         if (priv->rxqs != NULL) {
 188                 /* XXX race condition if mlx5_rx_burst() is still running. */
 189                 usleep(1000);
 190                 for (i = 0; (i != priv->rxqs_n); ++i)
 191                         mlx5_rxq_release(dev, i);
 192                 priv->rxqs_n = 0;
 193                 priv->rxqs = NULL;
 194         }
 195         if (priv->txqs != NULL) {
 196                 /* XXX race condition if mlx5_tx_burst() is still running. */
 197                 usleep(1000);
 198                 for (i = 0; (i != priv->txqs_n); ++i)
 199                         mlx5_txq_release(dev, i);
 200                 priv->txqs_n = 0;
 201                 priv->txqs = NULL;
 202         }
 203         mlx5_flow_delete_drop_queue(dev);
 204         if (priv->pd != NULL) {
 205                 assert(priv->ctx != NULL);
 206                 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
 207                 claim_zero(mlx5_glue->close_device(priv->ctx));
 208         } else
 209                 assert(priv->ctx == NULL);
 210         if (priv->rss_conf.rss_key != NULL)
 211                 rte_free(priv->rss_conf.rss_key);
 212         if (priv->reta_idx != NULL)
 213                 rte_free(priv->reta_idx);
 214         if (priv->primary_socket)
 215                 mlx5_socket_uninit(dev);
 216         if (priv->config.vf)
 217                 mlx5_nl_mac_addr_flush(dev);
 218         if (priv->nl_socket >= 0)
 219                 close(priv->nl_socket);
 220         ret = mlx5_hrxq_ibv_verify(dev);
 221         if (ret)
 222                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
 223                         dev->data->port_id);
 224         ret = mlx5_ind_table_ibv_verify(dev);
 225         if (ret)
 226                 DRV_LOG(WARNING, "port %u some indirection table still remain",
 227                         dev->data->port_id);
 228         ret = mlx5_rxq_ibv_verify(dev);
 229         if (ret)
 230                 DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain",
 231                         dev->data->port_id);
 232         ret = mlx5_rxq_verify(dev);
 233         if (ret)
 234                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
 235                         dev->data->port_id);
 236         ret = mlx5_txq_ibv_verify(dev);
 237         if (ret)
 238                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
 239                         dev->data->port_id);
 240         ret = mlx5_txq_verify(dev);
 241         if (ret)
 242                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
 243                         dev->data->port_id);
 244         ret = mlx5_flow_verify(dev);
 245         if (ret)
 246                 DRV_LOG(WARNING, "port %u some flows still remain",
 247                         dev->data->port_id);
 248         ret = mlx5_mr_verify(dev);
 249         if (ret)
 250                 DRV_LOG(WARNING, "port %u some memory region still remain",
 251                         dev->data->port_id);
 252         memset(priv, 0, sizeof(*priv));
 253 }
 254
 255 const struct eth_dev_ops mlx5_dev_ops = {
 256         .dev_configure = mlx5_dev_configure,
 257         .dev_start = mlx5_dev_start,
 258         .dev_stop = mlx5_dev_stop,
 259         .dev_set_link_down = mlx5_set_link_down,
 260         .dev_set_link_up = mlx5_set_link_up,
 261         .dev_close = mlx5_dev_close,
 262         .promiscuous_enable = mlx5_promiscuous_enable,
 263         .promiscuous_disable = mlx5_promiscuous_disable,
 264         .allmulticast_enable = mlx5_allmulticast_enable,
 265         .allmulticast_disable = mlx5_allmulticast_disable,
 266         .link_update = mlx5_link_update,
 267         .stats_get = mlx5_stats_get,
 268         .stats_reset = mlx5_stats_reset,
 269         .xstats_get = mlx5_xstats_get,
 270         .xstats_reset = mlx5_xstats_reset,
 271         .xstats_get_names = mlx5_xstats_get_names,
 272         .dev_infos_get = mlx5_dev_infos_get,
 273         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
 274         .vlan_filter_set = mlx5_vlan_filter_set,
 275         .rx_queue_setup = mlx5_rx_queue_setup,
 276         .tx_queue_setup = mlx5_tx_queue_setup,
 277         .rx_queue_release = mlx5_rx_queue_release,
 278         .tx_queue_release = mlx5_tx_queue_release,
 279         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
 280         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
 281         .mac_addr_remove = mlx5_mac_addr_remove,
 282         .mac_addr_add = mlx5_mac_addr_add,
 283         .mac_addr_set = mlx5_mac_addr_set,
 284         .set_mc_addr_list = mlx5_set_mc_addr_list,
 285         .mtu_set = mlx5_dev_set_mtu,
 286         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
 287         .vlan_offload_set = mlx5_vlan_offload_set,
 288         .reta_update = mlx5_dev_rss_reta_update,
 289         .reta_query = mlx5_dev_rss_reta_query,
 290         .rss_hash_update = mlx5_rss_hash_update,
 291         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
 292         .filter_ctrl = mlx5_dev_filter_ctrl,
 293         .rx_descriptor_status = mlx5_rx_descriptor_status,
 294         .tx_descriptor_status = mlx5_tx_descriptor_status,
 295         .rx_queue_intr_enable = mlx5_rx_intr_enable,
 296         .rx_queue_intr_disable = mlx5_rx_intr_disable,
 297         .is_removed = mlx5_is_removed,
 298 };
 299
 300 static const struct eth_dev_ops mlx5_dev_sec_ops = {
 301         .stats_get = mlx5_stats_get,
 302         .stats_reset = mlx5_stats_reset,
 303         .xstats_get = mlx5_xstats_get,
 304         .xstats_reset = mlx5_xstats_reset,
 305         .xstats_get_names = mlx5_xstats_get_names,
 306         .dev_infos_get = mlx5_dev_infos_get,
 307         .rx_descriptor_status = mlx5_rx_descriptor_status,
 308         .tx_descriptor_status = mlx5_tx_descriptor_status,
 309 };
 310
 311 /* Available operators in flow isolated mode. */
 312 const struct eth_dev_ops mlx5_dev_ops_isolate = {
 313         .dev_configure = mlx5_dev_configure,
 314         .dev_start = mlx5_dev_start,
 315         .dev_stop = mlx5_dev_stop,
 316         .dev_set_link_down = mlx5_set_link_down,
 317         .dev_set_link_up = mlx5_set_link_up,
 318         .dev_close = mlx5_dev_close,
 319         .link_update = mlx5_link_update,
 320         .stats_get = mlx5_stats_get,
 321         .stats_reset = mlx5_stats_reset,
 322         .xstats_get = mlx5_xstats_get,
 323         .xstats_reset = mlx5_xstats_reset,
 324         .xstats_get_names = mlx5_xstats_get_names,
 325         .dev_infos_get = mlx5_dev_infos_get,
 326         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
 327         .vlan_filter_set = mlx5_vlan_filter_set,
 328         .rx_queue_setup = mlx5_rx_queue_setup,
 329         .tx_queue_setup = mlx5_tx_queue_setup,
 330         .rx_queue_release = mlx5_rx_queue_release,
 331         .tx_queue_release = mlx5_tx_queue_release,
 332         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
 333         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
 334         .mac_addr_remove = mlx5_mac_addr_remove,
 335         .mac_addr_add = mlx5_mac_addr_add,
 336         .mac_addr_set = mlx5_mac_addr_set,
 337         .set_mc_addr_list = mlx5_set_mc_addr_list,
 338         .mtu_set = mlx5_dev_set_mtu,
 339         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
 340         .vlan_offload_set = mlx5_vlan_offload_set,
 341         .filter_ctrl = mlx5_dev_filter_ctrl,
 342         .rx_descriptor_status = mlx5_rx_descriptor_status,
 343         .tx_descriptor_status = mlx5_tx_descriptor_status,
 344         .rx_queue_intr_enable = mlx5_rx_intr_enable,
 345         .rx_queue_intr_disable = mlx5_rx_intr_disable,
 346         .is_removed = mlx5_is_removed,
 347 };
 348
 349 static struct {
 350         struct rte_pci_addr pci_addr; /* associated PCI address */
 351         uint32_t ports; /* physical ports bitfield. */
 352 } mlx5_dev[32];
 353
 354 /**
 355  * Get device index in mlx5_dev[] from PCI bus address.
 356  *
 357  * @param[in] pci_addr
 358  *   PCI bus address to look for.
 359  *
 360  * @return
 361  *   mlx5_dev[] index on success, -1 on failure.
 362  */
 363 static int
 364 mlx5_dev_idx(struct rte_pci_addr *pci_addr)
 365 {
 366         unsigned int i;
 367         int ret = -1;
 368
 369         assert(pci_addr != NULL);
 370         for (i = 0; (i != RTE_DIM(mlx5_dev)); ++i) {
 371                 if ((mlx5_dev[i].pci_addr.domain == pci_addr->domain) &&
 372                     (mlx5_dev[i].pci_addr.bus == pci_addr->bus) &&
 373                     (mlx5_dev[i].pci_addr.devid == pci_addr->devid) &&
 374                     (mlx5_dev[i].pci_addr.function == pci_addr->function))
 375                         return i;
 376                 if ((mlx5_dev[i].ports == 0) && (ret == -1))
 377                         ret = i;
 378         }
 379         return ret;
 380 }
 381
 382 /**
 383  * Verify and store value for device argument.
 384  *
 385  * @param[in] key
 386  *   Key argument to verify.
 387  * @param[in] val
 388  *   Value associated with key.
 389  * @param opaque
 390  *   User data.
 391  *
 392  * @return
 393  *   0 on success, a negative errno value otherwise and rte_errno is set.
 394  */
 395 static int
 396 mlx5_args_check(const char *key, const char *val, void *opaque)
 397 {
 398         struct mlx5_dev_config *config = opaque;
 399         unsigned long tmp;
 400
 401         errno = 0;
 402         tmp = strtoul(val, NULL, 0);
 403         if (errno) {
 404                 rte_errno = errno;
 405                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
 406                 return -rte_errno;
 407         }
 408         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
 409                 config->cqe_comp = !!tmp;
 410         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
 411                 config->txq_inline = tmp;
 412         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
 413                 config->txqs_inline = tmp;
 414         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
 415                 config->mps = !!tmp ? config->mps : 0;
 416         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
 417                 config->mpw_hdr_dseg = !!tmp;
 418         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
 419                 config->inline_max_packet_sz = tmp;
 420         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
 421                 config->tx_vec_en = !!tmp;
 422         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
 423                 config->rx_vec_en = !!tmp;
 424         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
 425                 config->l3_vxlan_en = !!tmp;
 426         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
 427                 config->vf_nl_en = !!tmp;
 428         } else {
 429                 DRV_LOG(WARNING, "%s: unknown parameter", key);
 430                 rte_errno = EINVAL;
 431                 return -rte_errno;
 432         }
 433         return 0;
 434 }
 435
 436 /**
 437  * Parse device parameters.
 438  *
 439  * @param config
 440  *   Pointer to device configuration structure.
 441  * @param devargs
 442  *   Device arguments structure.
 443  *
 444  * @return
 445  *   0 on success, a negative errno value otherwise and rte_errno is set.
 446  */
 447 static int
 448 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
 449 {
 450         const char **params = (const char *[]){
 451                 MLX5_RXQ_CQE_COMP_EN,
 452                 MLX5_TXQ_INLINE,
 453                 MLX5_TXQS_MIN_INLINE,
 454                 MLX5_TXQ_MPW_EN,
 455                 MLX5_TXQ_MPW_HDR_DSEG_EN,
 456                 MLX5_TXQ_MAX_INLINE_LEN,
 457                 MLX5_TX_VEC_EN,
 458                 MLX5_RX_VEC_EN,
 459                 MLX5_L3_VXLAN_EN,
 460                 MLX5_VF_NL_EN,
 461                 NULL,
 462         };
 463         struct rte_kvargs *kvlist;
 464         int ret = 0;
 465         int i;
 466
 467         if (devargs == NULL)
 468                 return 0;
 469         /* Following UGLY cast is done to pass checkpatch. */
 470         kvlist = rte_kvargs_parse(devargs->args, params);
 471         if (kvlist == NULL)
 472                 return 0;
 473         /* Process parameters. */
 474         for (i = 0; (params[i] != NULL); ++i) {
 475                 if (rte_kvargs_count(kvlist, params[i])) {
 476                         ret = rte_kvargs_process(kvlist, params[i],
 477                                                  mlx5_args_check, config);
 478                         if (ret) {
 479                                 rte_errno = EINVAL;
 480                                 rte_kvargs_free(kvlist);
 481                                 return -rte_errno;
 482                         }
 483                 }
 484         }
 485         rte_kvargs_free(kvlist);
 486         return 0;
 487 }
 488
 489 static struct rte_pci_driver mlx5_driver;
 490
 491 /*
 492  * Reserved UAR address space for TXQ UAR(hw doorbell) mapping, process
 493  * local resource used by both primary and secondary to avoid duplicate
 494  * reservation.
 495  * The space has to be available on both primary and secondary process,
 496  * TXQ UAR maps to this area using fixed mmap w/o double check.
 497  */
 498 static void *uar_base;
 499
 500 static int
 501 find_lower_va_bound(const struct rte_memseg_list *msl __rte_unused,
 502                 const struct rte_memseg *ms, void *arg)
 503 {
 504         void **addr = arg;
 505
 506         if (*addr == NULL)
 507                 *addr = ms->addr;
 508         else
 509                 *addr = RTE_MIN(*addr, ms->addr);
 510
 511         return 0;
 512 }
 513
 514 /**
 515  * Reserve UAR address space for primary process.
 516  *
 517  * @param[in] dev
 518  *   Pointer to Ethernet device.
 519  *
 520  * @return
 521  *   0 on success, a negative errno value otherwise and rte_errno is set.
 522  */
 523 static int
 524 mlx5_uar_init_primary(struct rte_eth_dev *dev)
 525 {
 526         struct priv *priv = dev->data->dev_private;
 527         void *addr = (void *)0;
 528
 529         if (uar_base) { /* UAR address space mapped. */
 530                 priv->uar_base = uar_base;
 531                 return 0;
 532         }
 533         /* find out lower bound of hugepage segments */
 534         rte_memseg_walk(find_lower_va_bound, &addr);
 535
 536         /* keep distance to hugepages to minimize potential conflicts. */
 537         addr = RTE_PTR_SUB(addr, MLX5_UAR_OFFSET + MLX5_UAR_SIZE);
 538         /* anonymous mmap, no real memory consumption. */
 539         addr = mmap(addr, MLX5_UAR_SIZE,
 540                     PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
 541         if (addr == MAP_FAILED) {
 542                 DRV_LOG(ERR,
 543                         "port %u failed to reserve UAR address space, please"
 544                         " adjust MLX5_UAR_SIZE or try --base-virtaddr",
 545                         dev->data->port_id);
 546                 rte_errno = ENOMEM;
 547                 return -rte_errno;
 548         }
 549         /* Accept either same addr or a new addr returned from mmap if target
 550          * range occupied.
 551          */
 552         DRV_LOG(INFO, "port %u reserved UAR address space: %p",
 553                 dev->data->port_id, addr);
 554         priv->uar_base = addr; /* for primary and secondary UAR re-mmap. */
 555         uar_base = addr; /* process local, don't reserve again. */
 556         return 0;
 557 }
 558
 559 /**
 560  * Reserve UAR address space for secondary process, align with
 561  * primary process.
 562  *
 563  * @param[in] dev
 564  *   Pointer to Ethernet device.
 565  *
 566  * @return
 567  *   0 on success, a negative errno value otherwise and rte_errno is set.
 568  */
 569 static int
 570 mlx5_uar_init_secondary(struct rte_eth_dev *dev)
 571 {
 572         struct priv *priv = dev->data->dev_private;
 573         void *addr;
 574
 575         assert(priv->uar_base);
 576         if (uar_base) { /* already reserved. */
 577                 assert(uar_base == priv->uar_base);
 578                 return 0;
 579         }
 580         /* anonymous mmap, no real memory consumption. */
 581         addr = mmap(priv->uar_base, MLX5_UAR_SIZE,
 582                     PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
 583         if (addr == MAP_FAILED) {
 584                 DRV_LOG(ERR, "port %u UAR mmap failed: %p size: %llu",
 585                         dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
 586                 rte_errno = ENXIO;
 587                 return -rte_errno;
 588         }
 589         if (priv->uar_base != addr) {
 590                 DRV_LOG(ERR,
 591                         "port %u UAR address %p size %llu occupied, please"
 592                         " adjust MLX5_UAR_OFFSET or try EAL parameter"
 593                         " --base-virtaddr",
 594                         dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
 595                 rte_errno = ENXIO;
 596                 return -rte_errno;
 597         }
 598         uar_base = addr; /* process local, don't reserve again */
 599         DRV_LOG(INFO, "port %u reserved UAR address space: %p",
 600                 dev->data->port_id, addr);
 601         return 0;
 602 }
 603
 604 /**
 605  * DPDK callback to register a PCI device.
 606  *
 607  * This function creates an Ethernet device for each port of a given
 608  * PCI device.
 609  *
 610  * @param[in] pci_drv
 611  *   PCI driver structure (mlx5_driver).
 612  * @param[in] pci_dev
 613  *   PCI device information.
 614  *
 615  * @return
 616  *   0 on success, a negative errno value otherwise and rte_errno is set.
 617  */
 618 static int
 619 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 620                struct rte_pci_device *pci_dev)
 621 {
 622         struct ibv_device **list = NULL;
 623         struct ibv_device *ibv_dev;
 624         int err = 0;
 625         struct ibv_context *attr_ctx = NULL;
 626         struct ibv_device_attr_ex device_attr;
 627         unsigned int vf;
 628         unsigned int mps;
 629         unsigned int cqe_comp;
 630         unsigned int tunnel_en = 0;
 631         unsigned int swp = 0;
 632         unsigned int verb_priorities = 0;
 633         int idx;
 634         int i;
 635         struct mlx5dv_context attrs_out = {0};
 636 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
 637         struct ibv_counter_set_description cs_desc;
 638 #endif
 639
 640         assert(pci_drv == &mlx5_driver);
 641         /* Get mlx5_dev[] index. */
 642         idx = mlx5_dev_idx(&pci_dev->addr);
 643         if (idx == -1) {
 644                 DRV_LOG(ERR, "this driver cannot support any more adapters");
 645                 err = ENOMEM;
 646                 goto error;
 647         }
 648         DRV_LOG(DEBUG, "using driver device index %d", idx);
 649         /* Save PCI address. */
 650         mlx5_dev[idx].pci_addr = pci_dev->addr;
 651         list = mlx5_glue->get_device_list(&i);
 652         if (list == NULL) {
 653                 assert(errno);
 654                 err = errno;
 655                 if (errno == ENOSYS)
 656                         DRV_LOG(ERR,
 657                                 "cannot list devices, is ib_uverbs loaded?");
 658                 goto error;
 659         }
 660         assert(i >= 0);
 661         /*
 662          * For each listed device, check related sysfs entry against
 663          * the provided PCI ID.
 664          */
 665         while (i != 0) {
 666                 struct rte_pci_addr pci_addr;
 667
 668                 --i;
 669                 DRV_LOG(DEBUG, "checking device \"%s\"", list[i]->name);
 670                 if (mlx5_ibv_device_to_pci_addr(list[i], &pci_addr))
 671                         continue;
 672                 if ((pci_dev->addr.domain != pci_addr.domain) ||
 673                     (pci_dev->addr.bus != pci_addr.bus) ||
 674                     (pci_dev->addr.devid != pci_addr.devid) ||
 675                     (pci_dev->addr.function != pci_addr.function))
 676                         continue;
 677                 DRV_LOG(INFO, "PCI information matches, using device \"%s\"",
 678                         list[i]->name);
 679                 vf = ((pci_dev->id.device_id ==
 680                        PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) ||
 681                       (pci_dev->id.device_id ==
 682                        PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) ||
 683                       (pci_dev->id.device_id ==
 684                        PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) ||
 685                       (pci_dev->id.device_id ==
 686                        PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF));
 687                 attr_ctx = mlx5_glue->open_device(list[i]);
 688                 rte_errno = errno;
 689                 err = rte_errno;
 690                 break;
 691         }
 692         if (attr_ctx == NULL) {
 693                 mlx5_glue->free_device_list(list);
 694                 switch (err) {
 695                 case 0:
 696                         DRV_LOG(ERR,
 697                                 "cannot access device, is mlx5_ib loaded?");
 698                         err = ENODEV;
 699                         goto error;
 700                 case EINVAL:
 701                         DRV_LOG(ERR,
 702                                 "cannot use device, are drivers up to date?");
 703                         goto error;
 704                 }
 705         }
 706         ibv_dev = list[i];
 707         DRV_LOG(DEBUG, "device opened");
 708 #ifdef HAVE_IBV_MLX5_MOD_SWP
 709         attrs_out.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
 710 #endif
 711         /*
 712          * Multi-packet send is supported by ConnectX-4 Lx PF as well
 713          * as all ConnectX-5 devices.
 714          */
 715 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
 716         attrs_out.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
 717 #endif
 718         mlx5_glue->dv_query_device(attr_ctx, &attrs_out);
 719         if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
 720                 if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
 721                         DRV_LOG(DEBUG, "enhanced MPW is supported");
 722                         mps = MLX5_MPW_ENHANCED;
 723                 } else {
 724                         DRV_LOG(DEBUG, "MPW is supported");
 725                         mps = MLX5_MPW;
 726                 }
 727         } else {
 728                 DRV_LOG(DEBUG, "MPW isn't supported");
 729                 mps = MLX5_MPW_DISABLED;
 730         }
 731 #ifdef HAVE_IBV_MLX5_MOD_SWP
 732         if (attrs_out.comp_mask | MLX5DV_CONTEXT_MASK_SWP)
 733                 swp = attrs_out.sw_parsing_caps.sw_parsing_offloads;
 734         DRV_LOG(DEBUG, "SWP support: %u", swp);
 735 #endif
 736         if (RTE_CACHE_LINE_SIZE == 128 &&
 737             !(attrs_out.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
 738                 cqe_comp = 0;
 739         else
 740                 cqe_comp = 1;
 741 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
 742         if (attrs_out.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
 743                 tunnel_en = ((attrs_out.tunnel_offloads_caps &
 744                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
 745                              (attrs_out.tunnel_offloads_caps &
 746                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE));
 747         }
 748         DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
 749                 tunnel_en ? "" : "not ");
 750 #else
 751         DRV_LOG(WARNING,
 752                 "tunnel offloading disabled due to old OFED/rdma-core version");
 753 #endif
 754         if (mlx5_glue->query_device_ex(attr_ctx, NULL, &device_attr)) {
 755                 err = errno;
 756                 goto error;
 757         }
 758         DRV_LOG(INFO, "%u port(s) detected",
 759                 device_attr.orig_attr.phys_port_cnt);
 760         for (i = 0; i < device_attr.orig_attr.phys_port_cnt; i++) {
 761                 char name[RTE_ETH_NAME_MAX_LEN];
 762                 int len;
 763                 uint32_t port = i + 1; /* ports are indexed from one */
 764                 uint32_t test = (1 << i);
 765                 struct ibv_context *ctx = NULL;
 766                 struct ibv_port_attr port_attr;
 767                 struct ibv_pd *pd = NULL;
 768                 struct priv *priv = NULL;
 769                 struct rte_eth_dev *eth_dev = NULL;
 770                 struct ibv_device_attr_ex device_attr_ex;
 771                 struct ether_addr mac;
 772                 struct mlx5_dev_config config = {
 773                         .cqe_comp = cqe_comp,
 774                         .mps = mps,
 775                         .tunnel_en = tunnel_en,
 776                         .tx_vec_en = 1,
 777                         .rx_vec_en = 1,
 778                         .mpw_hdr_dseg = 0,
 779                         .txq_inline = MLX5_ARG_UNSET,
 780                         .txqs_inline = MLX5_ARG_UNSET,
 781                         .inline_max_packet_sz = MLX5_ARG_UNSET,
 782                         .vf_nl_en = 1,
 783                         .swp = !!swp,
 784                 };
 785
 786                 len = snprintf(name, sizeof(name), PCI_PRI_FMT,
 787                          pci_dev->addr.domain, pci_dev->addr.bus,
 788                          pci_dev->addr.devid, pci_dev->addr.function);
 789                 if (device_attr.orig_attr.phys_port_cnt > 1)
 790                         snprintf(name + len, sizeof(name), " port %u", i);
 791                 mlx5_dev[idx].ports |= test;
 792                 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
 793                         eth_dev = rte_eth_dev_attach_secondary(name);
 794                         if (eth_dev == NULL) {
 795                                 DRV_LOG(ERR, "can not attach rte ethdev");
 796                                 rte_errno = ENOMEM;
 797                                 err = rte_errno;
 798                                 goto error;
 799                         }
 800                         eth_dev->device = &pci_dev->device;
 801                         eth_dev->dev_ops = &mlx5_dev_sec_ops;
 802                         err = mlx5_uar_init_secondary(eth_dev);
 803                         if (err)
 804                                 goto error;
 805                         /* Receive command fd from primary process */
 806                         err = mlx5_socket_connect(eth_dev);
 807                         if (err < 0)
 808                                 goto error;
 809                         /* Remap UAR for Tx queues. */
 810                         err = mlx5_tx_uar_remap(eth_dev, err);
 811                         if (err)
 812                                 goto error;
 813                         /*
 814                          * Ethdev pointer is still required as input since
 815                          * the primary device is not accessible from the
 816                          * secondary process.
 817                          */
 818                         eth_dev->rx_pkt_burst =
 819                                 mlx5_select_rx_function(eth_dev);
 820                         eth_dev->tx_pkt_burst =
 821                                 mlx5_select_tx_function(eth_dev);
 822                         continue;
 823                 }
 824                 DRV_LOG(DEBUG, "using port %u (%08" PRIx32 ")", port, test);
 825                 ctx = mlx5_glue->open_device(ibv_dev);
 826                 if (ctx == NULL) {
 827                         err = ENODEV;
 828                         goto port_error;
 829                 }
 830                 /* Check port status. */
 831                 err = mlx5_glue->query_port(ctx, port, &port_attr);
 832                 if (err) {
 833                         DRV_LOG(ERR, "port query failed: %s", strerror(err));
 834                         goto port_error;
 835                 }
 836                 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
 837                         DRV_LOG(ERR,
 838                                 "port %d is not configured in Ethernet mode",
 839                                 port);
 840                         err = EINVAL;
 841                         goto port_error;
 842                 }
 843                 if (port_attr.state != IBV_PORT_ACTIVE)
 844                         DRV_LOG(DEBUG, "port %d is not active: \"%s\" (%d)",
 845                                 port,
 846                                 mlx5_glue->port_state_str(port_attr.state),
 847                                 port_attr.state);
 848                 /* Allocate protection domain. */
 849                 pd = mlx5_glue->alloc_pd(ctx);
 850                 if (pd == NULL) {
 851                         DRV_LOG(ERR, "PD allocation failure");
 852                         err = ENOMEM;
 853                         goto port_error;
 854                 }
 855                 mlx5_dev[idx].ports |= test;
 856                 /* from rte_ethdev.c */
 857                 priv = rte_zmalloc("ethdev private structure",
 858                                    sizeof(*priv),
 859                                    RTE_CACHE_LINE_SIZE);
 860                 if (priv == NULL) {
 861                         DRV_LOG(ERR, "priv allocation failure");
 862                         err = ENOMEM;
 863                         goto port_error;
 864                 }
 865                 priv->ctx = ctx;
 866                 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path,
 867                         sizeof(priv->ibdev_path));
 868                 priv->device_attr = device_attr;
 869                 priv->port = port;
 870                 priv->pd = pd;
 871                 priv->mtu = ETHER_MTU;
 872                 err = mlx5_args(&config, pci_dev->device.devargs);
 873                 if (err) {
 874                         DRV_LOG(ERR, "failed to process device arguments: %s",
 875                                 strerror(err));
 876                         goto port_error;
 877                 }
 878                 if (mlx5_glue->query_device_ex(ctx, NULL, &device_attr_ex)) {
 879                         DRV_LOG(ERR, "ibv_query_device_ex() failed");
 880                         err = errno;
 881                         goto port_error;
 882                 }
 883                 config.hw_csum = !!(device_attr_ex.device_cap_flags_ex &
 884                                     IBV_DEVICE_RAW_IP_CSUM);
 885                 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
 886                         (config.hw_csum ? "" : "not "));
 887 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
 888                 config.flow_counter_en = !!(device_attr.max_counter_sets);
 889                 mlx5_glue->describe_counter_set(ctx, 0, &cs_desc);
 890                 DRV_LOG(DEBUG,
 891                         "counter type = %d, num of cs = %ld, attributes = %d",
 892                         cs_desc.counter_type, cs_desc.num_of_cs,
 893                         cs_desc.attributes);
 894 #endif
 895                 config.ind_table_max_size =
 896                         device_attr_ex.rss_caps.max_rwq_indirection_table_size;
 897                 /* Remove this check once DPDK supports larger/variable
 898                  * indirection tables. */
 899                 if (config.ind_table_max_size >
 900                                 (unsigned int)ETH_RSS_RETA_SIZE_512)
 901                         config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
 902                 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
 903                         config.ind_table_max_size);
 904                 config.hw_vlan_strip = !!(device_attr_ex.raw_packet_caps &
 905                                          IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
 906                 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
 907                         (config.hw_vlan_strip ? "" : "not "));
 908
 909                 config.hw_fcs_strip = !!(device_attr_ex.raw_packet_caps &
 910                                          IBV_RAW_PACKET_CAP_SCATTER_FCS);
 911                 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
 912                         (config.hw_fcs_strip ? "" : "not "));
 913
 914 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
 915                 config.hw_padding = !!device_attr_ex.rx_pad_end_addr_align;
 916 #endif
 917                 DRV_LOG(DEBUG,
 918                         "hardware Rx end alignment padding is %ssupported",
 919                         (config.hw_padding ? "" : "not "));
 920                 config.vf = vf;
 921                 config.tso = ((device_attr_ex.tso_caps.max_tso > 0) &&
 922                               (device_attr_ex.tso_caps.supported_qpts &
 923                               (1 << IBV_QPT_RAW_PACKET)));
 924                 if (config.tso)
 925                         config.tso_max_payload_sz =
 926                                         device_attr_ex.tso_caps.max_tso;
 927                 if (config.mps && !mps) {
 928                         DRV_LOG(ERR,
 929                                 "multi-packet send not supported on this device"
 930                                 " (" MLX5_TXQ_MPW_EN ")");
 931                         err = ENOTSUP;
 932                         goto port_error;
 933                 }
 934                 DRV_LOG(INFO, "%s MPS is %s",
 935                         config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "",
 936                         config.mps != MLX5_MPW_DISABLED ? "enabled" :
 937                         "disabled");
 938                 if (config.cqe_comp && !cqe_comp) {
 939                         DRV_LOG(WARNING, "Rx CQE compression isn't supported");
 940                         config.cqe_comp = 0;
 941                 }
 942                 eth_dev = rte_eth_dev_allocate(name);
 943                 if (eth_dev == NULL) {
 944                         DRV_LOG(ERR, "can not allocate rte ethdev");
 945                         err = ENOMEM;
 946                         goto port_error;
 947                 }
 948                 eth_dev->data->dev_private = priv;
 949                 priv->dev = eth_dev;
 950                 eth_dev->data->mac_addrs = priv->mac;
 951                 eth_dev->device = &pci_dev->device;
 952                 rte_eth_copy_pci_info(eth_dev, pci_dev);
 953                 eth_dev->device->driver = &mlx5_driver.driver;
 954                 err = mlx5_uar_init_primary(eth_dev);
 955                 if (err)
 956                         goto port_error;
 957                 /* Configure the first MAC address by default. */
 958                 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
 959                         DRV_LOG(ERR,
 960                                 "port %u cannot get MAC address, is mlx5_en"
 961                                 " loaded? (errno: %s)",
 962                                 eth_dev->data->port_id, strerror(errno));
 963                         err = ENODEV;
 964                         goto port_error;
 965                 }
 966                 DRV_LOG(INFO,
 967                         "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
 968                         eth_dev->data->port_id,
 969                         mac.addr_bytes[0], mac.addr_bytes[1],
 970                         mac.addr_bytes[2], mac.addr_bytes[3],
 971                         mac.addr_bytes[4], mac.addr_bytes[5]);
 972 #ifndef NDEBUG
 973                 {
 974                         char ifname[IF_NAMESIZE];
 975
 976                         if (mlx5_get_ifname(eth_dev, &ifname) == 0)
 977                                 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
 978                                         eth_dev->data->port_id, ifname);
 979                         else
 980                                 DRV_LOG(DEBUG, "port %u ifname is unknown",
 981                                         eth_dev->data->port_id);
 982                 }
 983 #endif
 984                 /* Get actual MTU if possible. */
 985                 err = mlx5_get_mtu(eth_dev, &priv->mtu);
 986                 if (err)
 987                         goto port_error;
 988                 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
 989                         priv->mtu);
 990                 /*
 991                  * Initialize burst functions to prevent crashes before link-up.
 992                  */
 993                 eth_dev->rx_pkt_burst = removed_rx_burst;
 994                 eth_dev->tx_pkt_burst = removed_tx_burst;
 995                 eth_dev->dev_ops = &mlx5_dev_ops;
 996                 /* Register MAC address. */
 997                 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
 998                 priv->nl_socket = -1;
 999                 priv->nl_sn = 0;
1000                 if (vf && config.vf_nl_en) {
1001                         priv->nl_socket = mlx5_nl_init(RTMGRP_LINK);
1002                         if (priv->nl_socket < 0)
1003                                 priv->nl_socket = -1;
1004                         mlx5_nl_mac_addr_sync(eth_dev);
1005                 }
1006                 TAILQ_INIT(&priv->flows);
1007                 TAILQ_INIT(&priv->ctrl_flows);
1008                 /* Hint libmlx5 to use PMD allocator for data plane resources */
1009                 struct mlx5dv_ctx_allocators alctr = {
1010                         .alloc = &mlx5_alloc_verbs_buf,
1011                         .free = &mlx5_free_verbs_buf,
1012                         .data = priv,
1013                 };
1014                 mlx5_glue->dv_set_context_attr(ctx,
1015                                                MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
1016                                                (void *)((uintptr_t)&alctr));
1017                 /* Bring Ethernet device up. */
1018                 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
1019                         eth_dev->data->port_id);
1020                 mlx5_set_link_up(eth_dev);
1021                 /*
1022                  * Even though the interrupt handler is not installed yet,
1023                  * interrupts will still trigger on the asyn_fd from
1024                  * Verbs context returned by ibv_open_device().
1025                  */
1026                 mlx5_link_update(eth_dev, 0);
1027                 /* Store device configuration on private structure. */
1028                 priv->config = config;
1029                 /* Create drop queue. */
1030                 err = mlx5_flow_create_drop_queue(eth_dev);
1031                 if (err) {
1032                         DRV_LOG(ERR, "port %u drop queue allocation failed: %s",
1033                                 eth_dev->data->port_id, strerror(rte_errno));
1034                         goto port_error;
1035                 }
1036                 /* Supported Verbs flow priority number detection. */
1037                 if (verb_priorities == 0)
1038                         verb_priorities = mlx5_get_max_verbs_prio(eth_dev);
1039                 if (verb_priorities < MLX5_VERBS_FLOW_PRIO_8) {
1040                         DRV_LOG(ERR, "port %u wrong Verbs flow priorities: %u",
1041                                 eth_dev->data->port_id, verb_priorities);
1042                         goto port_error;
1043                 }
1044                 priv->config.max_verbs_prio = verb_priorities;
1045                 continue;
1046 port_error:
1047                 if (priv)
1048                         rte_free(priv);
1049                 if (pd)
1050                         claim_zero(mlx5_glue->dealloc_pd(pd));
1051                 if (ctx)
1052                         claim_zero(mlx5_glue->close_device(ctx));
1053                 break;
1054         }
1055         /*
1056          * XXX if something went wrong in the loop above, there is a resource
1057          * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as
1058          * long as the dpdk does not provide a way to deallocate a ethdev and a
1059          * way to enumerate the registered ethdevs to free the previous ones.
1060          */
1061         /* no port found, complain */
1062         if (!mlx5_dev[idx].ports) {
1063                 rte_errno = ENODEV;
1064                 err = rte_errno;
1065         }
1066 error:
1067         if (attr_ctx)
1068                 claim_zero(mlx5_glue->close_device(attr_ctx));
1069         if (list)
1070                 mlx5_glue->free_device_list(list);
1071         if (err) {
1072                 rte_errno = err;
1073                 return -rte_errno;
1074         }
1075         return 0;
1076 }
1077
1078 static const struct rte_pci_id mlx5_pci_id_map[] = {
1079         {
1080                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1081                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1082         },
1083         {
1084                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1085                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1086         },
1087         {
1088                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1089                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1090         },
1091         {
1092                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1093                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1094         },
1095         {
1096                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1097                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1098         },
1099         {
1100                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1101                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1102         },
1103         {
1104                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1105                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1106         },
1107         {
1108                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1109                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1110         },
1111         {
1112                 .vendor_id = 0
1113         }
1114 };
1115
1116 static struct rte_pci_driver mlx5_driver = {
1117         .driver = {
1118                 .name = MLX5_DRIVER_NAME
1119         },
1120         .id_table = mlx5_pci_id_map,
1121         .probe = mlx5_pci_probe,
1122         .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV,
1123 };
1124
1125 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1126
1127 /**
1128  * Suffix RTE_EAL_PMD_PATH with "-glue".
1129  *
1130  * This function performs a sanity check on RTE_EAL_PMD_PATH before
1131  * suffixing its last component.
1132  *
1133  * @param buf[out]
1134  *   Output buffer, should be large enough otherwise NULL is returned.
1135  * @param size
1136  *   Size of @p out.
1137  *
1138  * @return
1139  *   Pointer to @p buf or @p NULL in case suffix cannot be appended.
1140  */
1141 static char *
1142 mlx5_glue_path(char *buf, size_t size)
1143 {
1144         static const char *const bad[] = { "/", ".", "..", NULL };
1145         const char *path = RTE_EAL_PMD_PATH;
1146         size_t len = strlen(path);
1147         size_t off;
1148         int i;
1149
1150         while (len && path[len - 1] == '/')
1151                 --len;
1152         for (off = len; off && path[off - 1] != '/'; --off)
1153                 ;
1154         for (i = 0; bad[i]; ++i)
1155                 if (!strncmp(path + off, bad[i], (int)(len - off)))
1156                         goto error;
1157         i = snprintf(buf, size, "%.*s-glue", (int)len, path);
1158         if (i == -1 || (size_t)i >= size)
1159                 goto error;
1160         return buf;
1161 error:
1162         DRV_LOG(ERR,
1163                 "unable to append \"-glue\" to last component of"
1164                 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\"),"
1165                 " please re-configure DPDK");
1166         return NULL;
1167 }
1168
1169 /**
1170  * Initialization routine for run-time dependency on rdma-core.
1171  */
1172 static int
1173 mlx5_glue_init(void)
1174 {
1175         char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")];
1176         const char *path[] = {
1177                 /*
1178                  * A basic security check is necessary before trusting
1179                  * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH.
1180                  */
1181                 (geteuid() == getuid() && getegid() == getgid() ?
1182                  getenv("MLX5_GLUE_PATH") : NULL),
1183                 /*
1184                  * When RTE_EAL_PMD_PATH is set, use its glue-suffixed
1185                  * variant, otherwise let dlopen() look up libraries on its
1186                  * own.
1187                  */
1188                 (*RTE_EAL_PMD_PATH ?
1189                  mlx5_glue_path(glue_path, sizeof(glue_path)) : ""),
1190         };
1191         unsigned int i = 0;
1192         void *handle = NULL;
1193         void **sym;
1194         const char *dlmsg;
1195
1196         while (!handle && i != RTE_DIM(path)) {
1197                 const char *end;
1198                 size_t len;
1199                 int ret;
1200
1201                 if (!path[i]) {
1202                         ++i;
1203                         continue;
1204                 }
1205                 end = strpbrk(path[i], ":;");
1206                 if (!end)
1207                         end = path[i] + strlen(path[i]);
1208                 len = end - path[i];
1209                 ret = 0;
1210                 do {
1211                         char name[ret + 1];
1212
1213                         ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE,
1214                                        (int)len, path[i],
1215                                        (!len || *(end - 1) == '/') ? "" : "/");
1216                         if (ret == -1)
1217                                 break;
1218                         if (sizeof(name) != (size_t)ret + 1)
1219                                 continue;
1220                         DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"",
1221                                 name);
1222                         handle = dlopen(name, RTLD_LAZY);
1223                         break;
1224                 } while (1);
1225                 path[i] = end + 1;
1226                 if (!*end)
1227                         ++i;
1228         }
1229         if (!handle) {
1230                 rte_errno = EINVAL;
1231                 dlmsg = dlerror();
1232                 if (dlmsg)
1233                         DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg);
1234                 goto glue_error;
1235         }
1236         sym = dlsym(handle, "mlx5_glue");
1237         if (!sym || !*sym) {
1238                 rte_errno = EINVAL;
1239                 dlmsg = dlerror();
1240                 if (dlmsg)
1241                         DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg);
1242                 goto glue_error;
1243         }
1244         mlx5_glue = *sym;
1245         return 0;
1246 glue_error:
1247         if (handle)
1248                 dlclose(handle);
1249         DRV_LOG(WARNING,
1250                 "cannot initialize PMD due to missing run-time dependency on"
1251                 " rdma-core libraries (libibverbs, libmlx5)");
1252         return -rte_errno;
1253 }
1254
1255 #endif
1256
1257 /**
1258  * Driver initialization routine.
1259  */
1260 RTE_INIT(rte_mlx5_pmd_init);
1261 static void
1262 rte_mlx5_pmd_init(void)
1263 {
1264         /* Build the static tables for Verbs conversion. */
1265         mlx5_set_ptype_table();
1266         mlx5_set_cksum_table();
1267         mlx5_set_swp_types_table();
1268         /*
1269          * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
1270          * huge pages. Calling ibv_fork_init() during init allows
1271          * applications to use fork() safely for purposes other than
1272          * using this PMD, which is not supported in forked processes.
1273          */
1274         setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
1275         /* Match the size of Rx completion entry to the size of a cacheline. */
1276         if (RTE_CACHE_LINE_SIZE == 128)
1277                 setenv("MLX5_CQE_SIZE", "128", 0);
1278 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1279         if (mlx5_glue_init())
1280                 return;
1281         assert(mlx5_glue);
1282 #endif
1283 #ifndef NDEBUG
1284         /* Glue structure must not contain any NULL pointers. */
1285         {
1286                 unsigned int i;
1287
1288                 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i)
1289                         assert(((const void *const *)mlx5_glue)[i]);
1290         }
1291 #endif
1292         if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) {
1293                 DRV_LOG(ERR,
1294                         "rdma-core glue \"%s\" mismatch: \"%s\" is required",
1295                         mlx5_glue->version, MLX5_GLUE_VERSION);
1296                 return;
1297         }
1298         mlx5_glue->fork_init();
1299         rte_pci_register(&mlx5_driver);
1300 }
1301
1302 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1303 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1304 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");
1305
1306 /** Initialize driver log type. */
1307 RTE_INIT(vdev_netvsc_init_log)
1308 {
1309         mlx5_logtype = rte_log_register("pmd.net.mlx5");
1310         if (mlx5_logtype >= 0)
1311                 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
1312 }