drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12 #include <net/if.h>
  13 #include <sys/mman.h>
  14 #include <linux/rtnetlink.h>
  15
  16 /* Verbs header. */
  17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  18 #ifdef PEDANTIC
  19 #pragma GCC diagnostic ignored "-Wpedantic"
  20 #endif
  21 #include <infiniband/verbs.h>
  22 #ifdef PEDANTIC
  23 #pragma GCC diagnostic error "-Wpedantic"
  24 #endif
  25
  26 #include <rte_malloc.h>
  27 #include <rte_ethdev_driver.h>
  28 #include <rte_ethdev_pci.h>
  29 #include <rte_pci.h>
  30 #include <rte_bus_pci.h>
  31 #include <rte_common.h>
  32 #include <rte_kvargs.h>
  33 #include <rte_rwlock.h>
  34 #include <rte_spinlock.h>
  35 #include <rte_string_fns.h>
  36 #include <rte_alarm.h>
  37
  38 #include <mlx5_glue.h>
  39 #include <mlx5_devx_cmds.h>
  40 #include <mlx5_common.h>
  41
  42 #include "mlx5_defs.h"
  43 #include "mlx5.h"
  44 #include "mlx5_utils.h"
  45 #include "mlx5_rxtx.h"
  46 #include "mlx5_autoconf.h"
  47 #include "mlx5_mr.h"
  48 #include "mlx5_flow.h"
  49 #include "rte_pmd_mlx5.h"
  50
  51 /* Device parameter to enable RX completion queue compression. */
  52 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  53
  54 /* Device parameter to enable RX completion entry padding to 128B. */
  55 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
  56
  57 /* Device parameter to enable padding Rx packet to cacheline size. */
  58 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  59
  60 /* Device parameter to enable Multi-Packet Rx queue. */
  61 #define MLX5_RX_MPRQ_EN "mprq_en"
  62
  63 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  64 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  65
  66 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  67 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  68
  69 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  70 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  71
  72 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  73 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  74
  75 /* Device parameter to configure inline send. Deprecated, ignored.*/
  76 #define MLX5_TXQ_INLINE "txq_inline"
  77
  78 /* Device parameter to limit packet size to inline with ordinary SEND. */
  79 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  80
  81 /* Device parameter to configure minimal data size to inline. */
  82 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  83
  84 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  85 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  86
  87 /*
  88  * Device parameter to configure the number of TX queues threshold for
  89  * enabling inline send.
  90  */
  91 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  92
  93 /*
  94  * Device parameter to configure the number of TX queues threshold for
  95  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  96  */
  97 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  98
  99 /* Device parameter to enable multi-packet send WQEs. */
 100 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
 101
 102 /*
 103  * Device parameter to force doorbell register mapping
 104  * to non-cahed region eliminating the extra write memory barrier.
 105  */
 106 #define MLX5_TX_DB_NC "tx_db_nc"
 107
 108 /*
 109  * Device parameter to include 2 dsegs in the title WQEBB.
 110  * Deprecated, ignored.
 111  */
 112 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 113
 114 /*
 115  * Device parameter to limit the size of inlining packet.
 116  * Deprecated, ignored.
 117  */
 118 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 119
 120 /*
 121  * Device parameter to enable hardware Tx vector.
 122  * Deprecated, ignored (no vectorized Tx routines anymore).
 123  */
 124 #define MLX5_TX_VEC_EN "tx_vec_en"
 125
 126 /* Device parameter to enable hardware Rx vector. */
 127 #define MLX5_RX_VEC_EN "rx_vec_en"
 128
 129 /* Allow L3 VXLAN flow creation. */
 130 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 131
 132 /* Activate DV E-Switch flow steering. */
 133 #define MLX5_DV_ESW_EN "dv_esw_en"
 134
 135 /* Activate DV flow steering. */
 136 #define MLX5_DV_FLOW_EN "dv_flow_en"
 137
 138 /* Enable extensive flow metadata support. */
 139 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 140
 141 /* Activate Netlink support in VF mode. */
 142 #define MLX5_VF_NL_EN "vf_nl_en"
 143
 144 /* Enable extending memsegs when creating a MR. */
 145 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 146
 147 /* Select port representors to instantiate. */
 148 #define MLX5_REPRESENTOR "representor"
 149
 150 /* Device parameter to configure the maximum number of dump files per queue. */
 151 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 152
 153 /* Configure timeout of LRO session (in microseconds). */
 154 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 155
 156 /*
 157  * Device parameter to configure the total data buffer size for a single
 158  * hairpin queue (logarithm value).
 159  */
 160 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 161
 162 #ifndef HAVE_IBV_MLX5_MOD_MPW
 163 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
 164 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
 165 #endif
 166
 167 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
 168 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
 169 #endif
 170
 171 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
 172
 173 /* Shared memory between primary and secondary processes. */
 174 struct mlx5_shared_data *mlx5_shared_data;
 175
 176 /* Spinlock for mlx5_shared_data allocation. */
 177 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
 178
 179 /* Process local data for secondary processes. */
 180 static struct mlx5_local_data mlx5_local_data;
 181
 182 /** Driver-specific log messages type. */
 183 int mlx5_logtype;
 184
 185 /** Data associated with devices to spawn. */
 186 struct mlx5_dev_spawn_data {
 187         uint32_t ifindex; /**< Network interface index. */
 188         uint32_t max_port; /**< IB device maximal port index. */
 189         uint32_t ibv_port; /**< IB device physical port index. */
 190         int pf_bond; /**< bonding device PF index. < 0 - no bonding */
 191         struct mlx5_switch_info info; /**< Switch information. */
 192         struct ibv_device *ibv_dev; /**< Associated IB device. */
 193         struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
 194         struct rte_pci_device *pci_dev; /**< Backend PCI device. */
 195 };
 196
 197 static LIST_HEAD(, mlx5_ibv_shared) mlx5_ibv_list = LIST_HEAD_INITIALIZER();
 198 static pthread_mutex_t mlx5_ibv_list_mutex = PTHREAD_MUTEX_INITIALIZER;
 199
 200 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 201 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 202
 203 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 204 #define MLX5_TAGS_HLIST_ARRAY_SIZE 8192
 205
 206 /**
 207  * Allocate ID pool structure.
 208  *
 209  * @param[in] max_id
 210  *   The maximum id can be allocated from the pool.
 211  *
 212  * @return
 213  *   Pointer to pool object, NULL value otherwise.
 214  */
 215 struct mlx5_flow_id_pool *
 216 mlx5_flow_id_pool_alloc(uint32_t max_id)
 217 {
 218         struct mlx5_flow_id_pool *pool;
 219         void *mem;
 220
 221         pool = rte_zmalloc("id pool allocation", sizeof(*pool),
 222                            RTE_CACHE_LINE_SIZE);
 223         if (!pool) {
 224                 DRV_LOG(ERR, "can't allocate id pool");
 225                 rte_errno  = ENOMEM;
 226                 return NULL;
 227         }
 228         mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
 229                           RTE_CACHE_LINE_SIZE);
 230         if (!mem) {
 231                 DRV_LOG(ERR, "can't allocate mem for id pool");
 232                 rte_errno  = ENOMEM;
 233                 goto error;
 234         }
 235         pool->free_arr = mem;
 236         pool->curr = pool->free_arr;
 237         pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
 238         pool->base_index = 0;
 239         pool->max_id = max_id;
 240         return pool;
 241 error:
 242         rte_free(pool);
 243         return NULL;
 244 }
 245
 246 /**
 247  * Release ID pool structure.
 248  *
 249  * @param[in] pool
 250  *   Pointer to flow id pool object to free.
 251  */
 252 void
 253 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
 254 {
 255         rte_free(pool->free_arr);
 256         rte_free(pool);
 257 }
 258
 259 /**
 260  * Generate ID.
 261  *
 262  * @param[in] pool
 263  *   Pointer to flow id pool.
 264  * @param[out] id
 265  *   The generated ID.
 266  *
 267  * @return
 268  *   0 on success, error value otherwise.
 269  */
 270 uint32_t
 271 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
 272 {
 273         if (pool->curr == pool->free_arr) {
 274                 if (pool->base_index == pool->max_id) {
 275                         rte_errno  = ENOMEM;
 276                         DRV_LOG(ERR, "no free id");
 277                         return -rte_errno;
 278                 }
 279                 *id = ++pool->base_index;
 280                 return 0;
 281         }
 282         *id = *(--pool->curr);
 283         return 0;
 284 }
 285
 286 /**
 287  * Release ID.
 288  *
 289  * @param[in] pool
 290  *   Pointer to flow id pool.
 291  * @param[out] id
 292  *   The generated ID.
 293  *
 294  * @return
 295  *   0 on success, error value otherwise.
 296  */
 297 uint32_t
 298 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
 299 {
 300         uint32_t size;
 301         uint32_t size2;
 302         void *mem;
 303
 304         if (pool->curr == pool->last) {
 305                 size = pool->curr - pool->free_arr;
 306                 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
 307                 MLX5_ASSERT(size2 > size);
 308                 mem = rte_malloc("", size2 * sizeof(uint32_t), 0);
 309                 if (!mem) {
 310                         DRV_LOG(ERR, "can't allocate mem for id pool");
 311                         rte_errno  = ENOMEM;
 312                         return -rte_errno;
 313                 }
 314                 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
 315                 rte_free(pool->free_arr);
 316                 pool->free_arr = mem;
 317                 pool->curr = pool->free_arr + size;
 318                 pool->last = pool->free_arr + size2;
 319         }
 320         *pool->curr = id;
 321         pool->curr++;
 322         return 0;
 323 }
 324
 325 /**
 326  * Initialize the counters management structure.
 327  *
 328  * @param[in] sh
 329  *   Pointer to mlx5_ibv_shared object to free
 330  */
 331 static void
 332 mlx5_flow_counters_mng_init(struct mlx5_ibv_shared *sh)
 333 {
 334         uint8_t i;
 335
 336         TAILQ_INIT(&sh->cmng.flow_counters);
 337         for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i)
 338                 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
 339 }
 340
 341 /**
 342  * Destroy all the resources allocated for a counter memory management.
 343  *
 344  * @param[in] mng
 345  *   Pointer to the memory management structure.
 346  */
 347 static void
 348 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 349 {
 350         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 351
 352         LIST_REMOVE(mng, next);
 353         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 354         claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
 355         rte_free(mem);
 356 }
 357
 358 /**
 359  * Close and release all the resources of the counters management.
 360  *
 361  * @param[in] sh
 362  *   Pointer to mlx5_ibv_shared object to free.
 363  */
 364 static void
 365 mlx5_flow_counters_mng_close(struct mlx5_ibv_shared *sh)
 366 {
 367         struct mlx5_counter_stats_mem_mng *mng;
 368         uint8_t i;
 369         int j;
 370         int retries = 1024;
 371
 372         rte_errno = 0;
 373         while (--retries) {
 374                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 375                 if (rte_errno != EINPROGRESS)
 376                         break;
 377                 rte_pause();
 378         }
 379         for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i) {
 380                 struct mlx5_flow_counter_pool *pool;
 381                 uint32_t batch = !!(i % 2);
 382
 383                 if (!sh->cmng.ccont[i].pools)
 384                         continue;
 385                 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 386                 while (pool) {
 387                         if (batch) {
 388                                 if (pool->min_dcs)
 389                                         claim_zero
 390                                         (mlx5_devx_cmd_destroy(pool->min_dcs));
 391                         }
 392                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 393                                 if (pool->counters_raw[j].action)
 394                                         claim_zero
 395                                         (mlx5_glue->destroy_flow_action
 396                                                (pool->counters_raw[j].action));
 397                                 if (!batch && MLX5_GET_POOL_CNT_EXT
 398                                     (pool, j)->dcs)
 399                                         claim_zero(mlx5_devx_cmd_destroy
 400                                                   (MLX5_GET_POOL_CNT_EXT
 401                                                   (pool, j)->dcs));
 402                         }
 403                         TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool,
 404                                      next);
 405                         rte_free(pool);
 406                         pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 407                 }
 408                 rte_free(sh->cmng.ccont[i].pools);
 409         }
 410         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 411         while (mng) {
 412                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 413                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 414         }
 415         memset(&sh->cmng, 0, sizeof(sh->cmng));
 416 }
 417
 418 /**
 419  * Extract pdn of PD object using DV API.
 420  *
 421  * @param[in] pd
 422  *   Pointer to the verbs PD object.
 423  * @param[out] pdn
 424  *   Pointer to the PD object number variable.
 425  *
 426  * @return
 427  *   0 on success, error value otherwise.
 428  */
 429 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 430 static int
 431 mlx5_get_pdn(struct ibv_pd *pd __rte_unused, uint32_t *pdn __rte_unused)
 432 {
 433         struct mlx5dv_obj obj;
 434         struct mlx5dv_pd pd_info;
 435         int ret = 0;
 436
 437         obj.pd.in = pd;
 438         obj.pd.out = &pd_info;
 439         ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);
 440         if (ret) {
 441                 DRV_LOG(DEBUG, "Fail to get PD object info");
 442                 return ret;
 443         }
 444         *pdn = pd_info.pdn;
 445         return 0;
 446 }
 447 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
 448
 449 static int
 450 mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config)
 451 {
 452         char *env;
 453         int value;
 454
 455         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 456         /* Get environment variable to store. */
 457         env = getenv(MLX5_SHUT_UP_BF);
 458         value = env ? !!strcmp(env, "0") : MLX5_ARG_UNSET;
 459         if (config->dbnc == MLX5_ARG_UNSET)
 460                 setenv(MLX5_SHUT_UP_BF, MLX5_SHUT_UP_BF_DEFAULT, 1);
 461         else
 462                 setenv(MLX5_SHUT_UP_BF,
 463                        config->dbnc == MLX5_TXDB_NCACHED ? "1" : "0", 1);
 464         return value;
 465 }
 466
 467 static void
 468 mlx5_restore_doorbell_mapping_env(int value)
 469 {
 470         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 471         /* Restore the original environment variable state. */
 472         if (value == MLX5_ARG_UNSET)
 473                 unsetenv(MLX5_SHUT_UP_BF);
 474         else
 475                 setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1);
 476 }
 477
 478 /**
 479  * Allocate shared IB device context. If there is multiport device the
 480  * master and representors will share this context, if there is single
 481  * port dedicated IB device, the context will be used by only given
 482  * port due to unification.
 483  *
 484  * Routine first searches the context for the specified IB device name,
 485  * if found the shared context assumed and reference counter is incremented.
 486  * If no context found the new one is created and initialized with specified
 487  * IB device context and parameters.
 488  *
 489  * @param[in] spawn
 490  *   Pointer to the IB device attributes (name, port, etc).
 491  * @param[in] config
 492  *   Pointer to device configuration structure.
 493  *
 494  * @return
 495  *   Pointer to mlx5_ibv_shared object on success,
 496  *   otherwise NULL and rte_errno is set.
 497  */
 498 static struct mlx5_ibv_shared *
 499 mlx5_alloc_shared_ibctx(const struct mlx5_dev_spawn_data *spawn,
 500                         const struct mlx5_dev_config *config)
 501 {
 502         struct mlx5_ibv_shared *sh;
 503         int dbmap_env;
 504         int err = 0;
 505         uint32_t i;
 506 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 507         struct mlx5_devx_tis_attr tis_attr = { 0 };
 508 #endif
 509
 510         MLX5_ASSERT(spawn);
 511         /* Secondary process should not create the shared context. */
 512         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 513         pthread_mutex_lock(&mlx5_ibv_list_mutex);
 514         /* Search for IB context by device name. */
 515         LIST_FOREACH(sh, &mlx5_ibv_list, next) {
 516                 if (!strcmp(sh->ibdev_name, spawn->ibv_dev->name)) {
 517                         sh->refcnt++;
 518                         goto exit;
 519                 }
 520         }
 521         /* No device found, we have to create new shared context. */
 522         MLX5_ASSERT(spawn->max_port);
 523         sh = rte_zmalloc("ethdev shared ib context",
 524                          sizeof(struct mlx5_ibv_shared) +
 525                          spawn->max_port *
 526                          sizeof(struct mlx5_ibv_shared_port),
 527                          RTE_CACHE_LINE_SIZE);
 528         if (!sh) {
 529                 DRV_LOG(ERR, "shared context allocation failure");
 530                 rte_errno  = ENOMEM;
 531                 goto exit;
 532         }
 533         /*
 534          * Configure environment variable "MLX5_BF_SHUT_UP"
 535          * before the device creation. The rdma_core library
 536          * checks the variable at device creation and
 537          * stores the result internally.
 538          */
 539         dbmap_env = mlx5_config_doorbell_mapping_env(config);
 540         /* Try to open IB device with DV first, then usual Verbs. */
 541         errno = 0;
 542         sh->ctx = mlx5_glue->dv_open_device(spawn->ibv_dev);
 543         if (sh->ctx) {
 544                 sh->devx = 1;
 545                 DRV_LOG(DEBUG, "DevX is supported");
 546                 /* The device is created, no need for environment. */
 547                 mlx5_restore_doorbell_mapping_env(dbmap_env);
 548         } else {
 549                 /* The environment variable is still configured. */
 550                 sh->ctx = mlx5_glue->open_device(spawn->ibv_dev);
 551                 err = errno ? errno : ENODEV;
 552                 /*
 553                  * The environment variable is not needed anymore,
 554                  * all device creation attempts are completed.
 555                  */
 556                 mlx5_restore_doorbell_mapping_env(dbmap_env);
 557                 if (!sh->ctx)
 558                         goto error;
 559                 DRV_LOG(DEBUG, "DevX is NOT supported");
 560         }
 561         err = mlx5_glue->query_device_ex(sh->ctx, NULL, &sh->device_attr);
 562         if (err) {
 563                 DRV_LOG(DEBUG, "ibv_query_device_ex() failed");
 564                 goto error;
 565         }
 566         sh->refcnt = 1;
 567         sh->max_port = spawn->max_port;
 568         strncpy(sh->ibdev_name, sh->ctx->device->name,
 569                 sizeof(sh->ibdev_name));
 570         strncpy(sh->ibdev_path, sh->ctx->device->ibdev_path,
 571                 sizeof(sh->ibdev_path));
 572         pthread_mutex_init(&sh->intr_mutex, NULL);
 573         /*
 574          * Setting port_id to max unallowed value means
 575          * there is no interrupt subhandler installed for
 576          * the given port index i.
 577          */
 578         for (i = 0; i < sh->max_port; i++) {
 579                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 580                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
 581         }
 582         sh->pd = mlx5_glue->alloc_pd(sh->ctx);
 583         if (sh->pd == NULL) {
 584                 DRV_LOG(ERR, "PD allocation failure");
 585                 err = ENOMEM;
 586                 goto error;
 587         }
 588 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 589         if (sh->devx) {
 590                 err = mlx5_get_pdn(sh->pd, &sh->pdn);
 591                 if (err) {
 592                         DRV_LOG(ERR, "Fail to extract pdn from PD");
 593                         goto error;
 594                 }
 595                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
 596                 if (!sh->td) {
 597                         DRV_LOG(ERR, "TD allocation failure");
 598                         err = ENOMEM;
 599                         goto error;
 600                 }
 601                 tis_attr.transport_domain = sh->td->id;
 602                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
 603                 if (!sh->tis) {
 604                         DRV_LOG(ERR, "TIS allocation failure");
 605                         err = ENOMEM;
 606                         goto error;
 607                 }
 608         }
 609         sh->flow_id_pool = mlx5_flow_id_pool_alloc(UINT32_MAX);
 610         if (!sh->flow_id_pool) {
 611                 DRV_LOG(ERR, "can't create flow id pool");
 612                 err = ENOMEM;
 613                 goto error;
 614         }
 615 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
 616         /*
 617          * Once the device is added to the list of memory event
 618          * callback, its global MR cache table cannot be expanded
 619          * on the fly because of deadlock. If it overflows, lookup
 620          * should be done by searching MR list linearly, which is slow.
 621          *
 622          * At this point the device is not added to the memory
 623          * event list yet, context is just being created.
 624          */
 625         err = mlx5_mr_btree_init(&sh->mr.cache,
 626                                  MLX5_MR_BTREE_CACHE_N * 2,
 627                                  spawn->pci_dev->device.numa_node);
 628         if (err) {
 629                 err = rte_errno;
 630                 goto error;
 631         }
 632         mlx5_flow_counters_mng_init(sh);
 633         /* Add device to memory callback list. */
 634         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 635         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
 636                          sh, mem_event_cb);
 637         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 638         /* Add context to the global device list. */
 639         LIST_INSERT_HEAD(&mlx5_ibv_list, sh, next);
 640 exit:
 641         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 642         return sh;
 643 error:
 644         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 645         MLX5_ASSERT(sh);
 646         if (sh->tis)
 647                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 648         if (sh->td)
 649                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 650         if (sh->pd)
 651                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 652         if (sh->ctx)
 653                 claim_zero(mlx5_glue->close_device(sh->ctx));
 654         if (sh->flow_id_pool)
 655                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 656         rte_free(sh);
 657         MLX5_ASSERT(err > 0);
 658         rte_errno = err;
 659         return NULL;
 660 }
 661
 662 /**
 663  * Free shared IB device context. Decrement counter and if zero free
 664  * all allocated resources and close handles.
 665  *
 666  * @param[in] sh
 667  *   Pointer to mlx5_ibv_shared object to free
 668  */
 669 static void
 670 mlx5_free_shared_ibctx(struct mlx5_ibv_shared *sh)
 671 {
 672         pthread_mutex_lock(&mlx5_ibv_list_mutex);
 673 #ifdef RTE_LIBRTE_MLX5_DEBUG
 674         /* Check the object presence in the list. */
 675         struct mlx5_ibv_shared *lctx;
 676
 677         LIST_FOREACH(lctx, &mlx5_ibv_list, next)
 678                 if (lctx == sh)
 679                         break;
 680         MLX5_ASSERT(lctx);
 681         if (lctx != sh) {
 682                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
 683                 goto exit;
 684         }
 685 #endif
 686         MLX5_ASSERT(sh);
 687         MLX5_ASSERT(sh->refcnt);
 688         /* Secondary process should not free the shared context. */
 689         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 690         if (--sh->refcnt)
 691                 goto exit;
 692         /* Remove from memory callback device list. */
 693         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 694         LIST_REMOVE(sh, mem_event_cb);
 695         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 696         /* Release created Memory Regions. */
 697         mlx5_mr_release(sh);
 698         /* Remove context from the global device list. */
 699         LIST_REMOVE(sh, next);
 700         /*
 701          *  Ensure there is no async event handler installed.
 702          *  Only primary process handles async device events.
 703          **/
 704         mlx5_flow_counters_mng_close(sh);
 705         MLX5_ASSERT(!sh->intr_cnt);
 706         if (sh->intr_cnt)
 707                 mlx5_intr_callback_unregister
 708                         (&sh->intr_handle, mlx5_dev_interrupt_handler, sh);
 709 #ifdef HAVE_MLX5_DEVX_ASYNC_SUPPORT
 710         if (sh->devx_intr_cnt) {
 711                 if (sh->intr_handle_devx.fd)
 712                         rte_intr_callback_unregister(&sh->intr_handle_devx,
 713                                           mlx5_dev_interrupt_handler_devx, sh);
 714                 if (sh->devx_comp)
 715                         mlx5dv_devx_destroy_cmd_comp(sh->devx_comp);
 716         }
 717 #endif
 718         pthread_mutex_destroy(&sh->intr_mutex);
 719         if (sh->pd)
 720                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 721         if (sh->tis)
 722                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 723         if (sh->td)
 724                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 725         if (sh->ctx)
 726                 claim_zero(mlx5_glue->close_device(sh->ctx));
 727         if (sh->flow_id_pool)
 728                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 729         rte_free(sh);
 730 exit:
 731         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 732 }
 733
 734 /**
 735  * Destroy table hash list and all the root entries per domain.
 736  *
 737  * @param[in] priv
 738  *   Pointer to the private device data structure.
 739  */
 740 static void
 741 mlx5_free_table_hash_list(struct mlx5_priv *priv)
 742 {
 743         struct mlx5_ibv_shared *sh = priv->sh;
 744         struct mlx5_flow_tbl_data_entry *tbl_data;
 745         union mlx5_flow_tbl_key table_key = {
 746                 {
 747                         .table_id = 0,
 748                         .reserved = 0,
 749                         .domain = 0,
 750                         .direction = 0,
 751                 }
 752         };
 753         struct mlx5_hlist_entry *pos;
 754
 755         if (!sh->flow_tbls)
 756                 return;
 757         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 758         if (pos) {
 759                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 760                                         entry);
 761                 MLX5_ASSERT(tbl_data);
 762                 mlx5_hlist_remove(sh->flow_tbls, pos);
 763                 rte_free(tbl_data);
 764         }
 765         table_key.direction = 1;
 766         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 767         if (pos) {
 768                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 769                                         entry);
 770                 MLX5_ASSERT(tbl_data);
 771                 mlx5_hlist_remove(sh->flow_tbls, pos);
 772                 rte_free(tbl_data);
 773         }
 774         table_key.direction = 0;
 775         table_key.domain = 1;
 776         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 777         if (pos) {
 778                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 779                                         entry);
 780                 MLX5_ASSERT(tbl_data);
 781                 mlx5_hlist_remove(sh->flow_tbls, pos);
 782                 rte_free(tbl_data);
 783         }
 784         mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
 785 }
 786
 787 /**
 788  * Initialize flow table hash list and create the root tables entry
 789  * for each domain.
 790  *
 791  * @param[in] priv
 792  *   Pointer to the private device data structure.
 793  *
 794  * @return
 795  *   Zero on success, positive error code otherwise.
 796  */
 797 static int
 798 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
 799 {
 800         struct mlx5_ibv_shared *sh = priv->sh;
 801         char s[MLX5_HLIST_NAMESIZE];
 802         int err = 0;
 803
 804         MLX5_ASSERT(sh);
 805         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
 806         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
 807         if (!sh->flow_tbls) {
 808                 DRV_LOG(ERR, "flow tables with hash creation failed.\n");
 809                 err = ENOMEM;
 810                 return err;
 811         }
 812 #ifndef HAVE_MLX5DV_DR
 813         /*
 814          * In case we have not DR support, the zero tables should be created
 815          * because DV expect to see them even if they cannot be created by
 816          * RDMA-CORE.
 817          */
 818         union mlx5_flow_tbl_key table_key = {
 819                 {
 820                         .table_id = 0,
 821                         .reserved = 0,
 822                         .domain = 0,
 823                         .direction = 0,
 824                 }
 825         };
 826         struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL,
 827                                                           sizeof(*tbl_data), 0);
 828
 829         if (!tbl_data) {
 830                 err = ENOMEM;
 831                 goto error;
 832         }
 833         tbl_data->entry.key = table_key.v64;
 834         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 835         if (err)
 836                 goto error;
 837         rte_atomic32_init(&tbl_data->tbl.refcnt);
 838         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 839         table_key.direction = 1;
 840         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 841         if (!tbl_data) {
 842                 err = ENOMEM;
 843                 goto error;
 844         }
 845         tbl_data->entry.key = table_key.v64;
 846         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 847         if (err)
 848                 goto error;
 849         rte_atomic32_init(&tbl_data->tbl.refcnt);
 850         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 851         table_key.direction = 0;
 852         table_key.domain = 1;
 853         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 854         if (!tbl_data) {
 855                 err = ENOMEM;
 856                 goto error;
 857         }
 858         tbl_data->entry.key = table_key.v64;
 859         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 860         if (err)
 861                 goto error;
 862         rte_atomic32_init(&tbl_data->tbl.refcnt);
 863         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 864         return err;
 865 error:
 866         mlx5_free_table_hash_list(priv);
 867 #endif /* HAVE_MLX5DV_DR */
 868         return err;
 869 }
 870
 871 /**
 872  * Initialize DR related data within private structure.
 873  * Routine checks the reference counter and does actual
 874  * resources creation/initialization only if counter is zero.
 875  *
 876  * @param[in] priv
 877  *   Pointer to the private device data structure.
 878  *
 879  * @return
 880  *   Zero on success, positive error code otherwise.
 881  */
 882 static int
 883 mlx5_alloc_shared_dr(struct mlx5_priv *priv)
 884 {
 885         struct mlx5_ibv_shared *sh = priv->sh;
 886         char s[MLX5_HLIST_NAMESIZE];
 887         int err = 0;
 888
 889         if (!sh->flow_tbls)
 890                 err = mlx5_alloc_table_hash_list(priv);
 891         else
 892                 DRV_LOG(DEBUG, "sh->flow_tbls[%p] already created, reuse\n",
 893                         (void *)sh->flow_tbls);
 894         if (err)
 895                 return err;
 896         /* Create tags hash list table. */
 897         snprintf(s, sizeof(s), "%s_tags", sh->ibdev_name);
 898         sh->tag_table = mlx5_hlist_create(s, MLX5_TAGS_HLIST_ARRAY_SIZE);
 899         if (!sh->tag_table) {
 900                 DRV_LOG(ERR, "tags with hash creation failed.\n");
 901                 err = ENOMEM;
 902                 goto error;
 903         }
 904 #ifdef HAVE_MLX5DV_DR
 905         void *domain;
 906
 907         if (sh->dv_refcnt) {
 908                 /* Shared DV/DR structures is already initialized. */
 909                 sh->dv_refcnt++;
 910                 priv->dr_shared = 1;
 911                 return 0;
 912         }
 913         /* Reference counter is zero, we should initialize structures. */
 914         domain = mlx5_glue->dr_create_domain(sh->ctx,
 915                                              MLX5DV_DR_DOMAIN_TYPE_NIC_RX);
 916         if (!domain) {
 917                 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed");
 918                 err = errno;
 919                 goto error;
 920         }
 921         sh->rx_domain = domain;
 922         domain = mlx5_glue->dr_create_domain(sh->ctx,
 923                                              MLX5DV_DR_DOMAIN_TYPE_NIC_TX);
 924         if (!domain) {
 925                 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed");
 926                 err = errno;
 927                 goto error;
 928         }
 929         pthread_mutex_init(&sh->dv_mutex, NULL);
 930         sh->tx_domain = domain;
 931 #ifdef HAVE_MLX5DV_DR_ESWITCH
 932         if (priv->config.dv_esw_en) {
 933                 domain  = mlx5_glue->dr_create_domain
 934                         (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB);
 935                 if (!domain) {
 936                         DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed");
 937                         err = errno;
 938                         goto error;
 939                 }
 940                 sh->fdb_domain = domain;
 941                 sh->esw_drop_action = mlx5_glue->dr_create_flow_action_drop();
 942         }
 943 #endif
 944         sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan();
 945 #endif /* HAVE_MLX5DV_DR */
 946         sh->dv_refcnt++;
 947         priv->dr_shared = 1;
 948         return 0;
 949 error:
 950         /* Rollback the created objects. */
 951         if (sh->rx_domain) {
 952                 mlx5_glue->dr_destroy_domain(sh->rx_domain);
 953                 sh->rx_domain = NULL;
 954         }
 955         if (sh->tx_domain) {
 956                 mlx5_glue->dr_destroy_domain(sh->tx_domain);
 957                 sh->tx_domain = NULL;
 958         }
 959         if (sh->fdb_domain) {
 960                 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
 961                 sh->fdb_domain = NULL;
 962         }
 963         if (sh->esw_drop_action) {
 964                 mlx5_glue->destroy_flow_action(sh->esw_drop_action);
 965                 sh->esw_drop_action = NULL;
 966         }
 967         if (sh->pop_vlan_action) {
 968                 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
 969                 sh->pop_vlan_action = NULL;
 970         }
 971         if (sh->tag_table) {
 972                 /* tags should be destroyed with flow before. */
 973                 mlx5_hlist_destroy(sh->tag_table, NULL, NULL);
 974                 sh->tag_table = NULL;
 975         }
 976         mlx5_free_table_hash_list(priv);
 977         return err;
 978 }
 979
 980 /**
 981  * Destroy DR related data within private structure.
 982  *
 983  * @param[in] priv
 984  *   Pointer to the private device data structure.
 985  */
 986 static void
 987 mlx5_free_shared_dr(struct mlx5_priv *priv)
 988 {
 989         struct mlx5_ibv_shared *sh;
 990
 991         if (!priv->dr_shared)
 992                 return;
 993         priv->dr_shared = 0;
 994         sh = priv->sh;
 995         MLX5_ASSERT(sh);
 996 #ifdef HAVE_MLX5DV_DR
 997         MLX5_ASSERT(sh->dv_refcnt);
 998         if (sh->dv_refcnt && --sh->dv_refcnt)
 999                 return;
1000         if (sh->rx_domain) {
1001                 mlx5_glue->dr_destroy_domain(sh->rx_domain);
1002                 sh->rx_domain = NULL;
1003         }
1004         if (sh->tx_domain) {
1005                 mlx5_glue->dr_destroy_domain(sh->tx_domain);
1006                 sh->tx_domain = NULL;
1007         }
1008 #ifdef HAVE_MLX5DV_DR_ESWITCH
1009         if (sh->fdb_domain) {
1010                 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
1011                 sh->fdb_domain = NULL;
1012         }
1013         if (sh->esw_drop_action) {
1014                 mlx5_glue->destroy_flow_action(sh->esw_drop_action);
1015                 sh->esw_drop_action = NULL;
1016         }
1017 #endif
1018         if (sh->pop_vlan_action) {
1019                 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
1020                 sh->pop_vlan_action = NULL;
1021         }
1022         pthread_mutex_destroy(&sh->dv_mutex);
1023 #endif /* HAVE_MLX5DV_DR */
1024         if (sh->tag_table) {
1025                 /* tags should be destroyed with flow before. */
1026                 mlx5_hlist_destroy(sh->tag_table, NULL, NULL);
1027                 sh->tag_table = NULL;
1028         }
1029         mlx5_free_table_hash_list(priv);
1030 }
1031
1032 /**
1033  * Initialize shared data between primary and secondary process.
1034  *
1035  * A memzone is reserved by primary process and secondary processes attach to
1036  * the memzone.
1037  *
1038  * @return
1039  *   0 on success, a negative errno value otherwise and rte_errno is set.
1040  */
1041 static int
1042 mlx5_init_shared_data(void)
1043 {
1044         const struct rte_memzone *mz;
1045         int ret = 0;
1046
1047         rte_spinlock_lock(&mlx5_shared_data_lock);
1048         if (mlx5_shared_data == NULL) {
1049                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
1050                         /* Allocate shared memory. */
1051                         mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
1052                                                  sizeof(*mlx5_shared_data),
1053                                                  SOCKET_ID_ANY, 0);
1054                         if (mz == NULL) {
1055                                 DRV_LOG(ERR,
1056                                         "Cannot allocate mlx5 shared data");
1057                                 ret = -rte_errno;
1058                                 goto error;
1059                         }
1060                         mlx5_shared_data = mz->addr;
1061                         memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
1062                         rte_spinlock_init(&mlx5_shared_data->lock);
1063                 } else {
1064                         /* Lookup allocated shared memory. */
1065                         mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
1066                         if (mz == NULL) {
1067                                 DRV_LOG(ERR,
1068                                         "Cannot attach mlx5 shared data");
1069                                 ret = -rte_errno;
1070                                 goto error;
1071                         }
1072                         mlx5_shared_data = mz->addr;
1073                         memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
1074                 }
1075         }
1076 error:
1077         rte_spinlock_unlock(&mlx5_shared_data_lock);
1078         return ret;
1079 }
1080
1081 /**
1082  * Retrieve integer value from environment variable.
1083  *
1084  * @param[in] name
1085  *   Environment variable name.
1086  *
1087  * @return
1088  *   Integer value, 0 if the variable is not set.
1089  */
1090 int
1091 mlx5_getenv_int(const char *name)
1092 {
1093         const char *val = getenv(name);
1094
1095         if (val == NULL)
1096                 return 0;
1097         return atoi(val);
1098 }
1099
1100 /**
1101  * Verbs callback to allocate a memory. This function should allocate the space
1102  * according to the size provided residing inside a huge page.
1103  * Please note that all allocation must respect the alignment from libmlx5
1104  * (i.e. currently sysconf(_SC_PAGESIZE)).
1105  *
1106  * @param[in] size
1107  *   The size in bytes of the memory to allocate.
1108  * @param[in] data
1109  *   A pointer to the callback data.
1110  *
1111  * @return
1112  *   Allocated buffer, NULL otherwise and rte_errno is set.
1113  */
1114 static void *
1115 mlx5_alloc_verbs_buf(size_t size, void *data)
1116 {
1117         struct mlx5_priv *priv = data;
1118         void *ret;
1119         size_t alignment = sysconf(_SC_PAGESIZE);
1120         unsigned int socket = SOCKET_ID_ANY;
1121
1122         if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
1123                 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
1124
1125                 socket = ctrl->socket;
1126         } else if (priv->verbs_alloc_ctx.type ==
1127                    MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
1128                 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
1129
1130                 socket = ctrl->socket;
1131         }
1132         MLX5_ASSERT(data != NULL);
1133         ret = rte_malloc_socket(__func__, size, alignment, socket);
1134         if (!ret && size)
1135                 rte_errno = ENOMEM;
1136         return ret;
1137 }
1138
1139 /**
1140  * Verbs callback to free a memory.
1141  *
1142  * @param[in] ptr
1143  *   A pointer to the memory to free.
1144  * @param[in] data
1145  *   A pointer to the callback data.
1146  */
1147 static void
1148 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
1149 {
1150         MLX5_ASSERT(data != NULL);
1151         rte_free(ptr);
1152 }
1153
1154 /**
1155  * DPDK callback to add udp tunnel port
1156  *
1157  * @param[in] dev
1158  *   A pointer to eth_dev
1159  * @param[in] udp_tunnel
1160  *   A pointer to udp tunnel
1161  *
1162  * @return
1163  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1164  */
1165 int
1166 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1167                          struct rte_eth_udp_tunnel *udp_tunnel)
1168 {
1169         MLX5_ASSERT(udp_tunnel != NULL);
1170         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1171             udp_tunnel->udp_port == 4789)
1172                 return 0;
1173         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1174             udp_tunnel->udp_port == 4790)
1175                 return 0;
1176         return -ENOTSUP;
1177 }
1178
1179 /**
1180  * Initialize process private data structure.
1181  *
1182  * @param dev
1183  *   Pointer to Ethernet device structure.
1184  *
1185  * @return
1186  *   0 on success, a negative errno value otherwise and rte_errno is set.
1187  */
1188 int
1189 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1190 {
1191         struct mlx5_priv *priv = dev->data->dev_private;
1192         struct mlx5_proc_priv *ppriv;
1193         size_t ppriv_size;
1194
1195         /*
1196          * UAR register table follows the process private structure. BlueFlame
1197          * registers for Tx queues are stored in the table.
1198          */
1199         ppriv_size =
1200                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1201         ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
1202                                   RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1203         if (!ppriv) {
1204                 rte_errno = ENOMEM;
1205                 return -rte_errno;
1206         }
1207         ppriv->uar_table_sz = ppriv_size;
1208         dev->process_private = ppriv;
1209         return 0;
1210 }
1211
1212 /**
1213  * Un-initialize process private data structure.
1214  *
1215  * @param dev
1216  *   Pointer to Ethernet device structure.
1217  */
1218 static void
1219 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1220 {
1221         if (!dev->process_private)
1222                 return;
1223         rte_free(dev->process_private);
1224         dev->process_private = NULL;
1225 }
1226
1227 /**
1228  * DPDK callback to close the device.
1229  *
1230  * Destroy all queues and objects, free memory.
1231  *
1232  * @param dev
1233  *   Pointer to Ethernet device structure.
1234  */
1235 static void
1236 mlx5_dev_close(struct rte_eth_dev *dev)
1237 {
1238         struct mlx5_priv *priv = dev->data->dev_private;
1239         unsigned int i;
1240         int ret;
1241
1242         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1243                 dev->data->port_id,
1244                 ((priv->sh->ctx != NULL) ? priv->sh->ctx->device->name : ""));
1245         /* In case mlx5_dev_stop() has not been called. */
1246         mlx5_dev_interrupt_handler_uninstall(dev);
1247         mlx5_dev_interrupt_handler_devx_uninstall(dev);
1248         /*
1249          * If default mreg copy action is removed at the stop stage,
1250          * the search will return none and nothing will be done anymore.
1251          */
1252         mlx5_flow_stop_default(dev);
1253         mlx5_traffic_disable(dev);
1254         /*
1255          * If all the flows are already flushed in the device stop stage,
1256          * then this will return directly without any action.
1257          */
1258         mlx5_flow_list_flush(dev, &priv->flows, true);
1259         mlx5_flow_meter_flush(dev, NULL);
1260         /* Free the intermediate buffers for flow creation. */
1261         mlx5_flow_free_intermediate(dev);
1262         /* Prevent crashes when queues are still in use. */
1263         dev->rx_pkt_burst = removed_rx_burst;
1264         dev->tx_pkt_burst = removed_tx_burst;
1265         rte_wmb();
1266         /* Disable datapath on secondary process. */
1267         mlx5_mp_req_stop_rxtx(dev);
1268         if (priv->rxqs != NULL) {
1269                 /* XXX race condition if mlx5_rx_burst() is still running. */
1270                 usleep(1000);
1271                 for (i = 0; (i != priv->rxqs_n); ++i)
1272                         mlx5_rxq_release(dev, i);
1273                 priv->rxqs_n = 0;
1274                 priv->rxqs = NULL;
1275         }
1276         if (priv->txqs != NULL) {
1277                 /* XXX race condition if mlx5_tx_burst() is still running. */
1278                 usleep(1000);
1279                 for (i = 0; (i != priv->txqs_n); ++i)
1280                         mlx5_txq_release(dev, i);
1281                 priv->txqs_n = 0;
1282                 priv->txqs = NULL;
1283         }
1284         mlx5_proc_priv_uninit(dev);
1285         if (priv->mreg_cp_tbl)
1286                 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1287         mlx5_mprq_free_mp(dev);
1288         mlx5_free_shared_dr(priv);
1289         if (priv->rss_conf.rss_key != NULL)
1290                 rte_free(priv->rss_conf.rss_key);
1291         if (priv->reta_idx != NULL)
1292                 rte_free(priv->reta_idx);
1293         if (priv->config.vf)
1294                 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1295                                        dev->data->mac_addrs,
1296                                        MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1297         if (priv->nl_socket_route >= 0)
1298                 close(priv->nl_socket_route);
1299         if (priv->nl_socket_rdma >= 0)
1300                 close(priv->nl_socket_rdma);
1301         if (priv->vmwa_context)
1302                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1303         if (priv->sh) {
1304                 /*
1305                  * Free the shared context in last turn, because the cleanup
1306                  * routines above may use some shared fields, like
1307                  * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1308                  * ifindex if Netlink fails.
1309                  */
1310                 mlx5_free_shared_ibctx(priv->sh);
1311                 priv->sh = NULL;
1312         }
1313         ret = mlx5_hrxq_verify(dev);
1314         if (ret)
1315                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1316                         dev->data->port_id);
1317         ret = mlx5_ind_table_obj_verify(dev);
1318         if (ret)
1319                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1320                         dev->data->port_id);
1321         ret = mlx5_rxq_obj_verify(dev);
1322         if (ret)
1323                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1324                         dev->data->port_id);
1325         ret = mlx5_rxq_verify(dev);
1326         if (ret)
1327                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1328                         dev->data->port_id);
1329         ret = mlx5_txq_obj_verify(dev);
1330         if (ret)
1331                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1332                         dev->data->port_id);
1333         ret = mlx5_txq_verify(dev);
1334         if (ret)
1335                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1336                         dev->data->port_id);
1337         ret = mlx5_flow_verify(dev);
1338         if (ret)
1339                 DRV_LOG(WARNING, "port %u some flows still remain",
1340                         dev->data->port_id);
1341         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1342                 unsigned int c = 0;
1343                 uint16_t port_id;
1344
1345                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1346                         struct mlx5_priv *opriv =
1347                                 rte_eth_devices[port_id].data->dev_private;
1348
1349                         if (!opriv ||
1350                             opriv->domain_id != priv->domain_id ||
1351                             &rte_eth_devices[port_id] == dev)
1352                                 continue;
1353                         ++c;
1354                         break;
1355                 }
1356                 if (!c)
1357                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1358         }
1359         memset(priv, 0, sizeof(*priv));
1360         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1361         /*
1362          * Reset mac_addrs to NULL such that it is not freed as part of
1363          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1364          * it is freed when dev_private is freed.
1365          */
1366         dev->data->mac_addrs = NULL;
1367 }
1368
1369 const struct eth_dev_ops mlx5_dev_ops = {
1370         .dev_configure = mlx5_dev_configure,
1371         .dev_start = mlx5_dev_start,
1372         .dev_stop = mlx5_dev_stop,
1373         .dev_set_link_down = mlx5_set_link_down,
1374         .dev_set_link_up = mlx5_set_link_up,
1375         .dev_close = mlx5_dev_close,
1376         .promiscuous_enable = mlx5_promiscuous_enable,
1377         .promiscuous_disable = mlx5_promiscuous_disable,
1378         .allmulticast_enable = mlx5_allmulticast_enable,
1379         .allmulticast_disable = mlx5_allmulticast_disable,
1380         .link_update = mlx5_link_update,
1381         .stats_get = mlx5_stats_get,
1382         .stats_reset = mlx5_stats_reset,
1383         .xstats_get = mlx5_xstats_get,
1384         .xstats_reset = mlx5_xstats_reset,
1385         .xstats_get_names = mlx5_xstats_get_names,
1386         .fw_version_get = mlx5_fw_version_get,
1387         .dev_infos_get = mlx5_dev_infos_get,
1388         .read_clock = mlx5_read_clock,
1389         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1390         .vlan_filter_set = mlx5_vlan_filter_set,
1391         .rx_queue_setup = mlx5_rx_queue_setup,
1392         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1393         .tx_queue_setup = mlx5_tx_queue_setup,
1394         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1395         .rx_queue_release = mlx5_rx_queue_release,
1396         .tx_queue_release = mlx5_tx_queue_release,
1397         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1398         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1399         .mac_addr_remove = mlx5_mac_addr_remove,
1400         .mac_addr_add = mlx5_mac_addr_add,
1401         .mac_addr_set = mlx5_mac_addr_set,
1402         .set_mc_addr_list = mlx5_set_mc_addr_list,
1403         .mtu_set = mlx5_dev_set_mtu,
1404         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1405         .vlan_offload_set = mlx5_vlan_offload_set,
1406         .reta_update = mlx5_dev_rss_reta_update,
1407         .reta_query = mlx5_dev_rss_reta_query,
1408         .rss_hash_update = mlx5_rss_hash_update,
1409         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1410         .filter_ctrl = mlx5_dev_filter_ctrl,
1411         .rx_descriptor_status = mlx5_rx_descriptor_status,
1412         .tx_descriptor_status = mlx5_tx_descriptor_status,
1413         .rxq_info_get = mlx5_rxq_info_get,
1414         .txq_info_get = mlx5_txq_info_get,
1415         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1416         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1417         .rx_queue_count = mlx5_rx_queue_count,
1418         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1419         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1420         .is_removed = mlx5_is_removed,
1421         .udp_tunnel_port_add  = mlx5_udp_tunnel_port_add,
1422         .get_module_info = mlx5_get_module_info,
1423         .get_module_eeprom = mlx5_get_module_eeprom,
1424         .hairpin_cap_get = mlx5_hairpin_cap_get,
1425         .mtr_ops_get = mlx5_flow_meter_ops_get,
1426 };
1427
1428 /* Available operations from secondary process. */
1429 static const struct eth_dev_ops mlx5_dev_sec_ops = {
1430         .stats_get = mlx5_stats_get,
1431         .stats_reset = mlx5_stats_reset,
1432         .xstats_get = mlx5_xstats_get,
1433         .xstats_reset = mlx5_xstats_reset,
1434         .xstats_get_names = mlx5_xstats_get_names,
1435         .fw_version_get = mlx5_fw_version_get,
1436         .dev_infos_get = mlx5_dev_infos_get,
1437         .rx_descriptor_status = mlx5_rx_descriptor_status,
1438         .tx_descriptor_status = mlx5_tx_descriptor_status,
1439         .rxq_info_get = mlx5_rxq_info_get,
1440         .txq_info_get = mlx5_txq_info_get,
1441         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1442         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1443         .get_module_info = mlx5_get_module_info,
1444         .get_module_eeprom = mlx5_get_module_eeprom,
1445 };
1446
1447 /* Available operations in flow isolated mode. */
1448 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1449         .dev_configure = mlx5_dev_configure,
1450         .dev_start = mlx5_dev_start,
1451         .dev_stop = mlx5_dev_stop,
1452         .dev_set_link_down = mlx5_set_link_down,
1453         .dev_set_link_up = mlx5_set_link_up,
1454         .dev_close = mlx5_dev_close,
1455         .promiscuous_enable = mlx5_promiscuous_enable,
1456         .promiscuous_disable = mlx5_promiscuous_disable,
1457         .allmulticast_enable = mlx5_allmulticast_enable,
1458         .allmulticast_disable = mlx5_allmulticast_disable,
1459         .link_update = mlx5_link_update,
1460         .stats_get = mlx5_stats_get,
1461         .stats_reset = mlx5_stats_reset,
1462         .xstats_get = mlx5_xstats_get,
1463         .xstats_reset = mlx5_xstats_reset,
1464         .xstats_get_names = mlx5_xstats_get_names,
1465         .fw_version_get = mlx5_fw_version_get,
1466         .dev_infos_get = mlx5_dev_infos_get,
1467         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1468         .vlan_filter_set = mlx5_vlan_filter_set,
1469         .rx_queue_setup = mlx5_rx_queue_setup,
1470         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1471         .tx_queue_setup = mlx5_tx_queue_setup,
1472         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1473         .rx_queue_release = mlx5_rx_queue_release,
1474         .tx_queue_release = mlx5_tx_queue_release,
1475         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1476         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1477         .mac_addr_remove = mlx5_mac_addr_remove,
1478         .mac_addr_add = mlx5_mac_addr_add,
1479         .mac_addr_set = mlx5_mac_addr_set,
1480         .set_mc_addr_list = mlx5_set_mc_addr_list,
1481         .mtu_set = mlx5_dev_set_mtu,
1482         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1483         .vlan_offload_set = mlx5_vlan_offload_set,
1484         .filter_ctrl = mlx5_dev_filter_ctrl,
1485         .rx_descriptor_status = mlx5_rx_descriptor_status,
1486         .tx_descriptor_status = mlx5_tx_descriptor_status,
1487         .rxq_info_get = mlx5_rxq_info_get,
1488         .txq_info_get = mlx5_txq_info_get,
1489         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1490         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1491         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1492         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1493         .is_removed = mlx5_is_removed,
1494         .get_module_info = mlx5_get_module_info,
1495         .get_module_eeprom = mlx5_get_module_eeprom,
1496         .hairpin_cap_get = mlx5_hairpin_cap_get,
1497         .mtr_ops_get = mlx5_flow_meter_ops_get,
1498 };
1499
1500 /**
1501  * Verify and store value for device argument.
1502  *
1503  * @param[in] key
1504  *   Key argument to verify.
1505  * @param[in] val
1506  *   Value associated with key.
1507  * @param opaque
1508  *   User data.
1509  *
1510  * @return
1511  *   0 on success, a negative errno value otherwise and rte_errno is set.
1512  */
1513 static int
1514 mlx5_args_check(const char *key, const char *val, void *opaque)
1515 {
1516         struct mlx5_dev_config *config = opaque;
1517         unsigned long tmp;
1518
1519         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1520         if (!strcmp(MLX5_REPRESENTOR, key))
1521                 return 0;
1522         errno = 0;
1523         tmp = strtoul(val, NULL, 0);
1524         if (errno) {
1525                 rte_errno = errno;
1526                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1527                 return -rte_errno;
1528         }
1529         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1530                 config->cqe_comp = !!tmp;
1531         } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1532                 config->cqe_pad = !!tmp;
1533         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1534                 config->hw_padding = !!tmp;
1535         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1536                 config->mprq.enabled = !!tmp;
1537         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1538                 config->mprq.stride_num_n = tmp;
1539         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1540                 config->mprq.stride_size_n = tmp;
1541         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1542                 config->mprq.max_memcpy_len = tmp;
1543         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1544                 config->mprq.min_rxqs_num = tmp;
1545         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1546                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1547                                  " converted to txq_inline_max", key);
1548                 config->txq_inline_max = tmp;
1549         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1550                 config->txq_inline_max = tmp;
1551         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1552                 config->txq_inline_min = tmp;
1553         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1554                 config->txq_inline_mpw = tmp;
1555         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1556                 config->txqs_inline = tmp;
1557         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1558                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1559         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1560                 config->mps = !!tmp;
1561         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1562                 if (tmp != MLX5_TXDB_CACHED &&
1563                     tmp != MLX5_TXDB_NCACHED &&
1564                     tmp != MLX5_TXDB_HEURISTIC) {
1565                         DRV_LOG(ERR, "invalid Tx doorbell "
1566                                      "mapping parameter");
1567                         rte_errno = EINVAL;
1568                         return -rte_errno;
1569                 }
1570                 config->dbnc = tmp;
1571         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1572                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1573         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1574                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1575                                  " converted to txq_inline_mpw", key);
1576                 config->txq_inline_mpw = tmp;
1577         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1578                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1579         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1580                 config->rx_vec_en = !!tmp;
1581         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1582                 config->l3_vxlan_en = !!tmp;
1583         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1584                 config->vf_nl_en = !!tmp;
1585         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1586                 config->dv_esw_en = !!tmp;
1587         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1588                 config->dv_flow_en = !!tmp;
1589         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1590                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1591                     tmp != MLX5_XMETA_MODE_META16 &&
1592                     tmp != MLX5_XMETA_MODE_META32) {
1593                         DRV_LOG(ERR, "invalid extensive "
1594                                      "metadata parameter");
1595                         rte_errno = EINVAL;
1596                         return -rte_errno;
1597                 }
1598                 config->dv_xmeta_en = tmp;
1599         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1600                 config->mr_ext_memseg_en = !!tmp;
1601         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1602                 config->max_dump_files_num = tmp;
1603         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1604                 config->lro.timeout = tmp;
1605         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1606                 DRV_LOG(DEBUG, "class argument is %s.", val);
1607         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1608                 config->log_hp_size = tmp;
1609         } else {
1610                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1611                 rte_errno = EINVAL;
1612                 return -rte_errno;
1613         }
1614         return 0;
1615 }
1616
1617 /**
1618  * Parse device parameters.
1619  *
1620  * @param config
1621  *   Pointer to device configuration structure.
1622  * @param devargs
1623  *   Device arguments structure.
1624  *
1625  * @return
1626  *   0 on success, a negative errno value otherwise and rte_errno is set.
1627  */
1628 static int
1629 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1630 {
1631         const char **params = (const char *[]){
1632                 MLX5_RXQ_CQE_COMP_EN,
1633                 MLX5_RXQ_CQE_PAD_EN,
1634                 MLX5_RXQ_PKT_PAD_EN,
1635                 MLX5_RX_MPRQ_EN,
1636                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1637                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1638                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1639                 MLX5_RXQS_MIN_MPRQ,
1640                 MLX5_TXQ_INLINE,
1641                 MLX5_TXQ_INLINE_MIN,
1642                 MLX5_TXQ_INLINE_MAX,
1643                 MLX5_TXQ_INLINE_MPW,
1644                 MLX5_TXQS_MIN_INLINE,
1645                 MLX5_TXQS_MAX_VEC,
1646                 MLX5_TXQ_MPW_EN,
1647                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1648                 MLX5_TXQ_MAX_INLINE_LEN,
1649                 MLX5_TX_DB_NC,
1650                 MLX5_TX_VEC_EN,
1651                 MLX5_RX_VEC_EN,
1652                 MLX5_L3_VXLAN_EN,
1653                 MLX5_VF_NL_EN,
1654                 MLX5_DV_ESW_EN,
1655                 MLX5_DV_FLOW_EN,
1656                 MLX5_DV_XMETA_EN,
1657                 MLX5_MR_EXT_MEMSEG_EN,
1658                 MLX5_REPRESENTOR,
1659                 MLX5_MAX_DUMP_FILES_NUM,
1660                 MLX5_LRO_TIMEOUT_USEC,
1661                 MLX5_CLASS_ARG_NAME,
1662                 MLX5_HP_BUF_SIZE,
1663                 NULL,
1664         };
1665         struct rte_kvargs *kvlist;
1666         int ret = 0;
1667         int i;
1668
1669         if (devargs == NULL)
1670                 return 0;
1671         /* Following UGLY cast is done to pass checkpatch. */
1672         kvlist = rte_kvargs_parse(devargs->args, params);
1673         if (kvlist == NULL) {
1674                 rte_errno = EINVAL;
1675                 return -rte_errno;
1676         }
1677         /* Process parameters. */
1678         for (i = 0; (params[i] != NULL); ++i) {
1679                 if (rte_kvargs_count(kvlist, params[i])) {
1680                         ret = rte_kvargs_process(kvlist, params[i],
1681                                                  mlx5_args_check, config);
1682                         if (ret) {
1683                                 rte_errno = EINVAL;
1684                                 rte_kvargs_free(kvlist);
1685                                 return -rte_errno;
1686                         }
1687                 }
1688         }
1689         rte_kvargs_free(kvlist);
1690         return 0;
1691 }
1692
1693 static struct rte_pci_driver mlx5_driver;
1694
1695 /**
1696  * PMD global initialization.
1697  *
1698  * Independent from individual device, this function initializes global
1699  * per-PMD data structures distinguishing primary and secondary processes.
1700  * Hence, each initialization is called once per a process.
1701  *
1702  * @return
1703  *   0 on success, a negative errno value otherwise and rte_errno is set.
1704  */
1705 static int
1706 mlx5_init_once(void)
1707 {
1708         struct mlx5_shared_data *sd;
1709         struct mlx5_local_data *ld = &mlx5_local_data;
1710         int ret = 0;
1711
1712         if (mlx5_init_shared_data())
1713                 return -rte_errno;
1714         sd = mlx5_shared_data;
1715         MLX5_ASSERT(sd);
1716         rte_spinlock_lock(&sd->lock);
1717         switch (rte_eal_process_type()) {
1718         case RTE_PROC_PRIMARY:
1719                 if (sd->init_done)
1720                         break;
1721                 LIST_INIT(&sd->mem_event_cb_list);
1722                 rte_rwlock_init(&sd->mem_event_rwlock);
1723                 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1724                                                 mlx5_mr_mem_event_cb, NULL);
1725                 ret = mlx5_mp_init_primary();
1726                 if (ret)
1727                         goto out;
1728                 sd->init_done = true;
1729                 break;
1730         case RTE_PROC_SECONDARY:
1731                 if (ld->init_done)
1732                         break;
1733                 ret = mlx5_mp_init_secondary();
1734                 if (ret)
1735                         goto out;
1736                 ++sd->secondary_cnt;
1737                 ld->init_done = true;
1738                 break;
1739         default:
1740                 break;
1741         }
1742 out:
1743         rte_spinlock_unlock(&sd->lock);
1744         return ret;
1745 }
1746
1747 /**
1748  * Configures the minimal amount of data to inline into WQE
1749  * while sending packets.
1750  *
1751  * - the txq_inline_min has the maximal priority, if this
1752  *   key is specified in devargs
1753  * - if DevX is enabled the inline mode is queried from the
1754  *   device (HCA attributes and NIC vport context if needed).
1755  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1756  *   and none (0 bytes) for other NICs
1757  *
1758  * @param spawn
1759  *   Verbs device parameters (name, port, switch_info) to spawn.
1760  * @param config
1761  *   Device configuration parameters.
1762  */
1763 static void
1764 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1765                     struct mlx5_dev_config *config)
1766 {
1767         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1768                 /* Application defines size of inlined data explicitly. */
1769                 switch (spawn->pci_dev->id.device_id) {
1770                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1771                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1772                         if (config->txq_inline_min <
1773                                        (int)MLX5_INLINE_HSIZE_L2) {
1774                                 DRV_LOG(DEBUG,
1775                                         "txq_inline_mix aligned to minimal"
1776                                         " ConnectX-4 required value %d",
1777                                         (int)MLX5_INLINE_HSIZE_L2);
1778                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1779                         }
1780                         break;
1781                 }
1782                 goto exit;
1783         }
1784         if (config->hca_attr.eth_net_offloads) {
1785                 /* We have DevX enabled, inline mode queried successfully. */
1786                 switch (config->hca_attr.wqe_inline_mode) {
1787                 case MLX5_CAP_INLINE_MODE_L2:
1788                         /* outer L2 header must be inlined. */
1789                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1790                         goto exit;
1791                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1792                         /* No inline data are required by NIC. */
1793                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1794                         config->hw_vlan_insert =
1795                                 config->hca_attr.wqe_vlan_insert;
1796                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1797                         goto exit;
1798                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1799                         /* inline mode is defined by NIC vport context. */
1800                         if (!config->hca_attr.eth_virt)
1801                                 break;
1802                         switch (config->hca_attr.vport_inline_mode) {
1803                         case MLX5_INLINE_MODE_NONE:
1804                                 config->txq_inline_min =
1805                                         MLX5_INLINE_HSIZE_NONE;
1806                                 goto exit;
1807                         case MLX5_INLINE_MODE_L2:
1808                                 config->txq_inline_min =
1809                                         MLX5_INLINE_HSIZE_L2;
1810                                 goto exit;
1811                         case MLX5_INLINE_MODE_IP:
1812                                 config->txq_inline_min =
1813                                         MLX5_INLINE_HSIZE_L3;
1814                                 goto exit;
1815                         case MLX5_INLINE_MODE_TCP_UDP:
1816                                 config->txq_inline_min =
1817                                         MLX5_INLINE_HSIZE_L4;
1818                                 goto exit;
1819                         case MLX5_INLINE_MODE_INNER_L2:
1820                                 config->txq_inline_min =
1821                                         MLX5_INLINE_HSIZE_INNER_L2;
1822                                 goto exit;
1823                         case MLX5_INLINE_MODE_INNER_IP:
1824                                 config->txq_inline_min =
1825                                         MLX5_INLINE_HSIZE_INNER_L3;
1826                                 goto exit;
1827                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
1828                                 config->txq_inline_min =
1829                                         MLX5_INLINE_HSIZE_INNER_L4;
1830                                 goto exit;
1831                         }
1832                 }
1833         }
1834         /*
1835          * We get here if we are unable to deduce
1836          * inline data size with DevX. Try PCI ID
1837          * to determine old NICs.
1838          */
1839         switch (spawn->pci_dev->id.device_id) {
1840         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1841         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1842         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1843         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1844                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1845                 config->hw_vlan_insert = 0;
1846                 break;
1847         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1848         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1849         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1850         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1851                 /*
1852                  * These NICs support VLAN insertion from WQE and
1853                  * report the wqe_vlan_insert flag. But there is the bug
1854                  * and PFC control may be broken, so disable feature.
1855                  */
1856                 config->hw_vlan_insert = 0;
1857                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1858                 break;
1859         default:
1860                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1861                 break;
1862         }
1863 exit:
1864         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1865 }
1866
1867 /**
1868  * Configures the metadata mask fields in the shared context.
1869  *
1870  * @param [in] dev
1871  *   Pointer to Ethernet device.
1872  */
1873 static void
1874 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1875 {
1876         struct mlx5_priv *priv = dev->data->dev_private;
1877         struct mlx5_ibv_shared *sh = priv->sh;
1878         uint32_t meta, mark, reg_c0;
1879
1880         reg_c0 = ~priv->vport_meta_mask;
1881         switch (priv->config.dv_xmeta_en) {
1882         case MLX5_XMETA_MODE_LEGACY:
1883                 meta = UINT32_MAX;
1884                 mark = MLX5_FLOW_MARK_MASK;
1885                 break;
1886         case MLX5_XMETA_MODE_META16:
1887                 meta = reg_c0 >> rte_bsf32(reg_c0);
1888                 mark = MLX5_FLOW_MARK_MASK;
1889                 break;
1890         case MLX5_XMETA_MODE_META32:
1891                 meta = UINT32_MAX;
1892                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1893                 break;
1894         default:
1895                 meta = 0;
1896                 mark = 0;
1897                 MLX5_ASSERT(false);
1898                 break;
1899         }
1900         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1901                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1902                                  sh->dv_mark_mask, mark);
1903         else
1904                 sh->dv_mark_mask = mark;
1905         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1906                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1907                                  sh->dv_meta_mask, meta);
1908         else
1909                 sh->dv_meta_mask = meta;
1910         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1911                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1912                                  sh->dv_meta_mask, reg_c0);
1913         else
1914                 sh->dv_regc0_mask = reg_c0;
1915         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1916         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1917         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1918         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1919 }
1920
1921 /**
1922  * Allocate page of door-bells and register it using DevX API.
1923  *
1924  * @param [in] dev
1925  *   Pointer to Ethernet device.
1926  *
1927  * @return
1928  *   Pointer to new page on success, NULL otherwise.
1929  */
1930 static struct mlx5_devx_dbr_page *
1931 mlx5_alloc_dbr_page(struct rte_eth_dev *dev)
1932 {
1933         struct mlx5_priv *priv = dev->data->dev_private;
1934         struct mlx5_devx_dbr_page *page;
1935
1936         /* Allocate space for door-bell page and management data. */
1937         page = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_devx_dbr_page),
1938                                  RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1939         if (!page) {
1940                 DRV_LOG(ERR, "port %u cannot allocate dbr page",
1941                         dev->data->port_id);
1942                 return NULL;
1943         }
1944         /* Register allocated memory. */
1945         page->umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, page->dbrs,
1946                                               MLX5_DBR_PAGE_SIZE, 0);
1947         if (!page->umem) {
1948                 DRV_LOG(ERR, "port %u cannot umem reg dbr page",
1949                         dev->data->port_id);
1950                 rte_free(page);
1951                 return NULL;
1952         }
1953         return page;
1954 }
1955
1956 /**
1957  * Find the next available door-bell, allocate new page if needed.
1958  *
1959  * @param [in] dev
1960  *   Pointer to Ethernet device.
1961  * @param [out] dbr_page
1962  *   Door-bell page containing the page data.
1963  *
1964  * @return
1965  *   Door-bell address offset on success, a negative error value otherwise.
1966  */
1967 int64_t
1968 mlx5_get_dbr(struct rte_eth_dev *dev, struct mlx5_devx_dbr_page **dbr_page)
1969 {
1970         struct mlx5_priv *priv = dev->data->dev_private;
1971         struct mlx5_devx_dbr_page *page = NULL;
1972         uint32_t i, j;
1973
1974         LIST_FOREACH(page, &priv->dbrpgs, next)
1975                 if (page->dbr_count < MLX5_DBR_PER_PAGE)
1976                         break;
1977         if (!page) { /* No page with free door-bell exists. */
1978                 page = mlx5_alloc_dbr_page(dev);
1979                 if (!page) /* Failed to allocate new page. */
1980                         return (-1);
1981                 LIST_INSERT_HEAD(&priv->dbrpgs, page, next);
1982         }
1983         /* Loop to find bitmap part with clear bit. */
1984         for (i = 0;
1985              i < MLX5_DBR_BITMAP_SIZE && page->dbr_bitmap[i] == UINT64_MAX;
1986              i++)
1987                 ; /* Empty. */
1988         /* Find the first clear bit. */
1989         j = rte_bsf64(~page->dbr_bitmap[i]);
1990         MLX5_ASSERT(i < (MLX5_DBR_PER_PAGE / 64));
1991         page->dbr_bitmap[i] |= (1 << j);
1992         page->dbr_count++;
1993         *dbr_page = page;
1994         return (((i * 64) + j) * sizeof(uint64_t));
1995 }
1996
1997 /**
1998  * Release a door-bell record.
1999  *
2000  * @param [in] dev
2001  *   Pointer to Ethernet device.
2002  * @param [in] umem_id
2003  *   UMEM ID of page containing the door-bell record to release.
2004  * @param [in] offset
2005  *   Offset of door-bell record in page.
2006  *
2007  * @return
2008  *   0 on success, a negative error value otherwise.
2009  */
2010 int32_t
2011 mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id, uint64_t offset)
2012 {
2013         struct mlx5_priv *priv = dev->data->dev_private;
2014         struct mlx5_devx_dbr_page *page = NULL;
2015         int ret = 0;
2016
2017         LIST_FOREACH(page, &priv->dbrpgs, next)
2018                 /* Find the page this address belongs to. */
2019                 if (page->umem->umem_id == umem_id)
2020                         break;
2021         if (!page)
2022                 return -EINVAL;
2023         page->dbr_count--;
2024         if (!page->dbr_count) {
2025                 /* Page not used, free it and remove from list. */
2026                 LIST_REMOVE(page, next);
2027                 if (page->umem)
2028                         ret = -mlx5_glue->devx_umem_dereg(page->umem);
2029                 rte_free(page);
2030         } else {
2031                 /* Mark in bitmap that this door-bell is not in use. */
2032                 offset /= MLX5_DBR_SIZE;
2033                 int i = offset / 64;
2034                 int j = offset % 64;
2035
2036                 page->dbr_bitmap[i] &= ~(1 << j);
2037         }
2038         return ret;
2039 }
2040
2041 int
2042 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2043 {
2044         static const char *const dynf_names[] = {
2045                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2046                 RTE_MBUF_DYNFLAG_METADATA_NAME
2047         };
2048         unsigned int i;
2049
2050         if (n < RTE_DIM(dynf_names))
2051                 return -ENOMEM;
2052         for (i = 0; i < RTE_DIM(dynf_names); i++) {
2053                 if (names[i] == NULL)
2054                         return -EINVAL;
2055                 strcpy(names[i], dynf_names[i]);
2056         }
2057         return RTE_DIM(dynf_names);
2058 }
2059
2060 /**
2061  * Check sibling device configurations.
2062  *
2063  * Sibling devices sharing the Infiniband device context
2064  * should have compatible configurations. This regards
2065  * representors and bonding slaves.
2066  *
2067  * @param priv
2068  *   Private device descriptor.
2069  * @param config
2070  *   Configuration of the device is going to be created.
2071  *
2072  * @return
2073  *   0 on success, EINVAL otherwise
2074  */
2075 static int
2076 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2077                               struct mlx5_dev_config *config)
2078 {
2079         struct mlx5_ibv_shared *sh = priv->sh;
2080         struct mlx5_dev_config *sh_conf = NULL;
2081         uint16_t port_id;
2082
2083         MLX5_ASSERT(sh);
2084         /* Nothing to compare for the single/first device. */
2085         if (sh->refcnt == 1)
2086                 return 0;
2087         /* Find the device with shared context. */
2088         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2089                 struct mlx5_priv *opriv =
2090                         rte_eth_devices[port_id].data->dev_private;
2091
2092                 if (opriv && opriv != priv && opriv->sh == sh) {
2093                         sh_conf = &opriv->config;
2094                         break;
2095                 }
2096         }
2097         if (!sh_conf)
2098                 return 0;
2099         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2100                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2101                              " for shared %s context", sh->ibdev_name);
2102                 rte_errno = EINVAL;
2103                 return rte_errno;
2104         }
2105         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2106                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2107                              " for shared %s context", sh->ibdev_name);
2108                 rte_errno = EINVAL;
2109                 return rte_errno;
2110         }
2111         return 0;
2112 }
2113 /**
2114  * Spawn an Ethernet device from Verbs information.
2115  *
2116  * @param dpdk_dev
2117  *   Backing DPDK device.
2118  * @param spawn
2119  *   Verbs device parameters (name, port, switch_info) to spawn.
2120  * @param config
2121  *   Device configuration parameters.
2122  *
2123  * @return
2124  *   A valid Ethernet device object on success, NULL otherwise and rte_errno
2125  *   is set. The following errors are defined:
2126  *
2127  *   EBUSY: device is not supposed to be spawned.
2128  *   EEXIST: device is already spawned
2129  */
2130 static struct rte_eth_dev *
2131 mlx5_dev_spawn(struct rte_device *dpdk_dev,
2132                struct mlx5_dev_spawn_data *spawn,
2133                struct mlx5_dev_config config)
2134 {
2135         const struct mlx5_switch_info *switch_info = &spawn->info;
2136         struct mlx5_ibv_shared *sh = NULL;
2137         struct ibv_port_attr port_attr;
2138         struct mlx5dv_context dv_attr = { .comp_mask = 0 };
2139         struct rte_eth_dev *eth_dev = NULL;
2140         struct mlx5_priv *priv = NULL;
2141         int err = 0;
2142         unsigned int hw_padding = 0;
2143         unsigned int mps;
2144         unsigned int cqe_comp;
2145         unsigned int cqe_pad = 0;
2146         unsigned int tunnel_en = 0;
2147         unsigned int mpls_en = 0;
2148         unsigned int swp = 0;
2149         unsigned int mprq = 0;
2150         unsigned int mprq_min_stride_size_n = 0;
2151         unsigned int mprq_max_stride_size_n = 0;
2152         unsigned int mprq_min_stride_num_n = 0;
2153         unsigned int mprq_max_stride_num_n = 0;
2154         struct rte_ether_addr mac;
2155         char name[RTE_ETH_NAME_MAX_LEN];
2156         int own_domain_id = 0;
2157         uint16_t port_id;
2158         unsigned int i;
2159 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
2160         struct mlx5dv_devx_port devx_port = { .comp_mask = 0 };
2161 #endif
2162
2163         /* Determine if this port representor is supposed to be spawned. */
2164         if (switch_info->representor && dpdk_dev->devargs) {
2165                 struct rte_eth_devargs eth_da;
2166
2167                 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, &eth_da);
2168                 if (err) {
2169                         rte_errno = -err;
2170                         DRV_LOG(ERR, "failed to process device arguments: %s",
2171                                 strerror(rte_errno));
2172                         return NULL;
2173                 }
2174                 for (i = 0; i < eth_da.nb_representor_ports; ++i)
2175                         if (eth_da.representor_ports[i] ==
2176                             (uint16_t)switch_info->port_name)
2177                                 break;
2178                 if (i == eth_da.nb_representor_ports) {
2179                         rte_errno = EBUSY;
2180                         return NULL;
2181                 }
2182         }
2183         /* Build device name. */
2184         if (spawn->pf_bond <  0) {
2185                 /* Single device. */
2186                 if (!switch_info->representor)
2187                         strlcpy(name, dpdk_dev->name, sizeof(name));
2188                 else
2189                         snprintf(name, sizeof(name), "%s_representor_%u",
2190                                  dpdk_dev->name, switch_info->port_name);
2191         } else {
2192                 /* Bonding device. */
2193                 if (!switch_info->representor)
2194                         snprintf(name, sizeof(name), "%s_%s",
2195                                  dpdk_dev->name, spawn->ibv_dev->name);
2196                 else
2197                         snprintf(name, sizeof(name), "%s_%s_representor_%u",
2198                                  dpdk_dev->name, spawn->ibv_dev->name,
2199                                  switch_info->port_name);
2200         }
2201         /* check if the device is already spawned */
2202         if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
2203                 rte_errno = EEXIST;
2204                 return NULL;
2205         }
2206         DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
2207         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
2208                 eth_dev = rte_eth_dev_attach_secondary(name);
2209                 if (eth_dev == NULL) {
2210                         DRV_LOG(ERR, "can not attach rte ethdev");
2211                         rte_errno = ENOMEM;
2212                         return NULL;
2213                 }
2214                 eth_dev->device = dpdk_dev;
2215                 eth_dev->dev_ops = &mlx5_dev_sec_ops;
2216                 err = mlx5_proc_priv_init(eth_dev);
2217                 if (err)
2218                         return NULL;
2219                 /* Receive command fd from primary process */
2220                 err = mlx5_mp_req_verbs_cmd_fd(eth_dev);
2221                 if (err < 0)
2222                         return NULL;
2223                 /* Remap UAR for Tx queues. */
2224                 err = mlx5_tx_uar_init_secondary(eth_dev, err);
2225                 if (err)
2226                         return NULL;
2227                 /*
2228                  * Ethdev pointer is still required as input since
2229                  * the primary device is not accessible from the
2230                  * secondary process.
2231                  */
2232                 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev);
2233                 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev);
2234                 return eth_dev;
2235         }
2236         /*
2237          * Some parameters ("tx_db_nc" in particularly) are needed in
2238          * advance to create dv/verbs device context. We proceed the
2239          * devargs here to get ones, and later proceed devargs again
2240          * to override some hardware settings.
2241          */
2242         err = mlx5_args(&config, dpdk_dev->devargs);
2243         if (err) {
2244                 err = rte_errno;
2245                 DRV_LOG(ERR, "failed to process device arguments: %s",
2246                         strerror(rte_errno));
2247                 goto error;
2248         }
2249         sh = mlx5_alloc_shared_ibctx(spawn, &config);
2250         if (!sh)
2251                 return NULL;
2252         config.devx = sh->devx;
2253 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR
2254         config.dest_tir = 1;
2255 #endif
2256 #ifdef HAVE_IBV_MLX5_MOD_SWP
2257         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
2258 #endif
2259         /*
2260          * Multi-packet send is supported by ConnectX-4 Lx PF as well
2261          * as all ConnectX-5 devices.
2262          */
2263 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2264         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
2265 #endif
2266 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
2267         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
2268 #endif
2269         mlx5_glue->dv_query_device(sh->ctx, &dv_attr);
2270         if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
2271                 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
2272                         DRV_LOG(DEBUG, "enhanced MPW is supported");
2273                         mps = MLX5_MPW_ENHANCED;
2274                 } else {
2275                         DRV_LOG(DEBUG, "MPW is supported");
2276                         mps = MLX5_MPW;
2277                 }
2278         } else {
2279                 DRV_LOG(DEBUG, "MPW isn't supported");
2280                 mps = MLX5_MPW_DISABLED;
2281         }
2282 #ifdef HAVE_IBV_MLX5_MOD_SWP
2283         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
2284                 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
2285         DRV_LOG(DEBUG, "SWP support: %u", swp);
2286 #endif
2287         config.swp = !!swp;
2288 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
2289         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
2290                 struct mlx5dv_striding_rq_caps mprq_caps =
2291                         dv_attr.striding_rq_caps;
2292
2293                 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
2294                         mprq_caps.min_single_stride_log_num_of_bytes);
2295                 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
2296                         mprq_caps.max_single_stride_log_num_of_bytes);
2297                 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
2298                         mprq_caps.min_single_wqe_log_num_of_strides);
2299                 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
2300                         mprq_caps.max_single_wqe_log_num_of_strides);
2301                 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
2302                         mprq_caps.supported_qpts);
2303                 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
2304                 mprq = 1;
2305                 mprq_min_stride_size_n =
2306                         mprq_caps.min_single_stride_log_num_of_bytes;
2307                 mprq_max_stride_size_n =
2308                         mprq_caps.max_single_stride_log_num_of_bytes;
2309                 mprq_min_stride_num_n =
2310                         mprq_caps.min_single_wqe_log_num_of_strides;
2311                 mprq_max_stride_num_n =
2312                         mprq_caps.max_single_wqe_log_num_of_strides;
2313         }
2314 #endif
2315         if (RTE_CACHE_LINE_SIZE == 128 &&
2316             !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
2317                 cqe_comp = 0;
2318         else
2319                 cqe_comp = 1;
2320         config.cqe_comp = cqe_comp;
2321 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
2322         /* Whether device supports 128B Rx CQE padding. */
2323         cqe_pad = RTE_CACHE_LINE_SIZE == 128 &&
2324                   (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD);
2325 #endif
2326 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2327         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
2328                 tunnel_en = ((dv_attr.tunnel_offloads_caps &
2329                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
2330                              (dv_attr.tunnel_offloads_caps &
2331                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) &&
2332                              (dv_attr.tunnel_offloads_caps &
2333                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE));
2334         }
2335         DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
2336                 tunnel_en ? "" : "not ");
2337 #else
2338         DRV_LOG(WARNING,
2339                 "tunnel offloading disabled due to old OFED/rdma-core version");
2340 #endif
2341         config.tunnel_en = tunnel_en;
2342 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
2343         mpls_en = ((dv_attr.tunnel_offloads_caps &
2344                     MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
2345                    (dv_attr.tunnel_offloads_caps &
2346                     MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
2347         DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
2348                 mpls_en ? "" : "not ");
2349 #else
2350         DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
2351                 " old OFED/rdma-core version or firmware configuration");
2352 #endif
2353         config.mpls_en = mpls_en;
2354         /* Check port status. */
2355         err = mlx5_glue->query_port(sh->ctx, spawn->ibv_port, &port_attr);
2356         if (err) {
2357                 DRV_LOG(ERR, "port query failed: %s", strerror(err));
2358                 goto error;
2359         }
2360         if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
2361                 DRV_LOG(ERR, "port is not configured in Ethernet mode");
2362                 err = EINVAL;
2363                 goto error;
2364         }
2365         if (port_attr.state != IBV_PORT_ACTIVE)
2366                 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)",
2367                         mlx5_glue->port_state_str(port_attr.state),
2368                         port_attr.state);
2369         /* Allocate private eth device data. */
2370         priv = rte_zmalloc("ethdev private structure",
2371                            sizeof(*priv),
2372                            RTE_CACHE_LINE_SIZE);
2373         if (priv == NULL) {
2374                 DRV_LOG(ERR, "priv allocation failure");
2375                 err = ENOMEM;
2376                 goto error;
2377         }
2378         priv->sh = sh;
2379         priv->ibv_port = spawn->ibv_port;
2380         priv->pci_dev = spawn->pci_dev;
2381         priv->mtu = RTE_ETHER_MTU;
2382 #ifndef RTE_ARCH_64
2383         /* Initialize UAR access locks for 32bit implementations. */
2384         rte_spinlock_init(&priv->uar_lock_cq);
2385         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
2386                 rte_spinlock_init(&priv->uar_lock[i]);
2387 #endif
2388         /* Some internal functions rely on Netlink sockets, open them now. */
2389         priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA);
2390         priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE);
2391         priv->representor = !!switch_info->representor;
2392         priv->master = !!switch_info->master;
2393         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
2394         priv->vport_meta_tag = 0;
2395         priv->vport_meta_mask = 0;
2396         priv->pf_bond = spawn->pf_bond;
2397 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
2398         /*
2399          * The DevX port query API is implemented. E-Switch may use
2400          * either vport or reg_c[0] metadata register to match on
2401          * vport index. The engaged part of metadata register is
2402          * defined by mask.
2403          */
2404         if (switch_info->representor || switch_info->master) {
2405                 devx_port.comp_mask = MLX5DV_DEVX_PORT_VPORT |
2406                                       MLX5DV_DEVX_PORT_MATCH_REG_C_0;
2407                 err = mlx5_glue->devx_port_query(sh->ctx, spawn->ibv_port,
2408                                                  &devx_port);
2409                 if (err) {
2410                         DRV_LOG(WARNING,
2411                                 "can't query devx port %d on device %s",
2412                                 spawn->ibv_port, spawn->ibv_dev->name);
2413                         devx_port.comp_mask = 0;
2414                 }
2415         }
2416         if (devx_port.comp_mask & MLX5DV_DEVX_PORT_MATCH_REG_C_0) {
2417                 priv->vport_meta_tag = devx_port.reg_c_0.value;
2418                 priv->vport_meta_mask = devx_port.reg_c_0.mask;
2419                 if (!priv->vport_meta_mask) {
2420                         DRV_LOG(ERR, "vport zero mask for port %d"
2421                                      " on bonding device %s",
2422                                      spawn->ibv_port, spawn->ibv_dev->name);
2423                         err = ENOTSUP;
2424                         goto error;
2425                 }
2426                 if (priv->vport_meta_tag & ~priv->vport_meta_mask) {
2427                         DRV_LOG(ERR, "invalid vport tag for port %d"
2428                                      " on bonding device %s",
2429                                      spawn->ibv_port, spawn->ibv_dev->name);
2430                         err = ENOTSUP;
2431                         goto error;
2432                 }
2433         }
2434         if (devx_port.comp_mask & MLX5DV_DEVX_PORT_VPORT) {
2435                 priv->vport_id = devx_port.vport_num;
2436         } else if (spawn->pf_bond >= 0) {
2437                 DRV_LOG(ERR, "can't deduce vport index for port %d"
2438                              " on bonding device %s",
2439                              spawn->ibv_port, spawn->ibv_dev->name);
2440                 err = ENOTSUP;
2441                 goto error;
2442         } else {
2443                 /* Suppose vport index in compatible way. */
2444                 priv->vport_id = switch_info->representor ?
2445                                  switch_info->port_name + 1 : -1;
2446         }
2447 #else
2448         /*
2449          * Kernel/rdma_core support single E-Switch per PF configurations
2450          * only and vport_id field contains the vport index for
2451          * associated VF, which is deduced from representor port name.
2452          * For example, let's have the IB device port 10, it has
2453          * attached network device eth0, which has port name attribute
2454          * pf0vf2, we can deduce the VF number as 2, and set vport index
2455          * as 3 (2+1). This assigning schema should be changed if the
2456          * multiple E-Switch instances per PF configurations or/and PCI
2457          * subfunctions are added.
2458          */
2459         priv->vport_id = switch_info->representor ?
2460                          switch_info->port_name + 1 : -1;
2461 #endif
2462         /* representor_id field keeps the unmodified VF index. */
2463         priv->representor_id = switch_info->representor ?
2464                                switch_info->port_name : -1;
2465         /*
2466          * Look for sibling devices in order to reuse their switch domain
2467          * if any, otherwise allocate one.
2468          */
2469         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2470                 const struct mlx5_priv *opriv =
2471                         rte_eth_devices[port_id].data->dev_private;
2472
2473                 if (!opriv ||
2474                     opriv->sh != priv->sh ||
2475                         opriv->domain_id ==
2476                         RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
2477                         continue;
2478                 priv->domain_id = opriv->domain_id;
2479                 break;
2480         }
2481         if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
2482                 err = rte_eth_switch_domain_alloc(&priv->domain_id);
2483                 if (err) {
2484                         err = rte_errno;
2485                         DRV_LOG(ERR, "unable to allocate switch domain: %s",
2486                                 strerror(rte_errno));
2487                         goto error;
2488                 }
2489                 own_domain_id = 1;
2490         }
2491         /* Override some values set by hardware configuration. */
2492         mlx5_args(&config, dpdk_dev->devargs);
2493         err = mlx5_dev_check_sibling_config(priv, &config);
2494         if (err)
2495                 goto error;
2496         config.hw_csum = !!(sh->device_attr.device_cap_flags_ex &
2497                             IBV_DEVICE_RAW_IP_CSUM);
2498         DRV_LOG(DEBUG, "checksum offloading is %ssupported",
2499                 (config.hw_csum ? "" : "not "));
2500 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \
2501         !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
2502         DRV_LOG(DEBUG, "counters are not supported");
2503 #endif
2504 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR)
2505         if (config.dv_flow_en) {
2506                 DRV_LOG(WARNING, "DV flow is not supported");
2507                 config.dv_flow_en = 0;
2508         }
2509 #endif
2510         config.ind_table_max_size =
2511                 sh->device_attr.rss_caps.max_rwq_indirection_table_size;
2512         /*
2513          * Remove this check once DPDK supports larger/variable
2514          * indirection tables.
2515          */
2516         if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
2517                 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
2518         DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
2519                 config.ind_table_max_size);
2520         config.hw_vlan_strip = !!(sh->device_attr.raw_packet_caps &
2521                                   IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
2522         DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
2523                 (config.hw_vlan_strip ? "" : "not "));
2524         config.hw_fcs_strip = !!(sh->device_attr.raw_packet_caps &
2525                                  IBV_RAW_PACKET_CAP_SCATTER_FCS);
2526         DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
2527                 (config.hw_fcs_strip ? "" : "not "));
2528 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
2529         hw_padding = !!sh->device_attr.rx_pad_end_addr_align;
2530 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
2531         hw_padding = !!(sh->device_attr.device_cap_flags_ex &
2532                         IBV_DEVICE_PCI_WRITE_END_PADDING);
2533 #endif
2534         if (config.hw_padding && !hw_padding) {
2535                 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
2536                 config.hw_padding = 0;
2537         } else if (config.hw_padding) {
2538                 DRV_LOG(DEBUG, "Rx end alignment padding is enabled");
2539         }
2540         config.tso = (sh->device_attr.tso_caps.max_tso > 0 &&
2541                       (sh->device_attr.tso_caps.supported_qpts &
2542                        (1 << IBV_QPT_RAW_PACKET)));
2543         if (config.tso)
2544                 config.tso_max_payload_sz = sh->device_attr.tso_caps.max_tso;
2545         /*
2546          * MPW is disabled by default, while the Enhanced MPW is enabled
2547          * by default.
2548          */
2549         if (config.mps == MLX5_ARG_UNSET)
2550                 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED :
2551                                                           MLX5_MPW_DISABLED;
2552         else
2553                 config.mps = config.mps ? mps : MLX5_MPW_DISABLED;
2554         DRV_LOG(INFO, "%sMPS is %s",
2555                 config.mps == MLX5_MPW_ENHANCED ? "enhanced " :
2556                 config.mps == MLX5_MPW ? "legacy " : "",
2557                 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
2558         if (config.cqe_comp && !cqe_comp) {
2559                 DRV_LOG(WARNING, "Rx CQE compression isn't supported");
2560                 config.cqe_comp = 0;
2561         }
2562         if (config.cqe_pad && !cqe_pad) {
2563                 DRV_LOG(WARNING, "Rx CQE padding isn't supported");
2564                 config.cqe_pad = 0;
2565         } else if (config.cqe_pad) {
2566                 DRV_LOG(INFO, "Rx CQE padding is enabled");
2567         }
2568         if (config.devx) {
2569                 priv->counter_fallback = 0;
2570                 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config.hca_attr);
2571                 if (err) {
2572                         err = -err;
2573                         goto error;
2574                 }
2575                 if (!config.hca_attr.flow_counters_dump)
2576                         priv->counter_fallback = 1;
2577 #ifndef HAVE_IBV_DEVX_ASYNC
2578                 priv->counter_fallback = 1;
2579 #endif
2580                 if (priv->counter_fallback)
2581                         DRV_LOG(INFO, "Use fall-back DV counter management");
2582                 /* Check for LRO support. */
2583                 if (config.dest_tir && config.hca_attr.lro_cap &&
2584                     config.dv_flow_en) {
2585                         /* TBD check tunnel lro caps. */
2586                         config.lro.supported = config.hca_attr.lro_cap;
2587                         DRV_LOG(DEBUG, "Device supports LRO");
2588                         /*
2589                          * If LRO timeout is not configured by application,
2590                          * use the minimal supported value.
2591                          */
2592                         if (!config.lro.timeout)
2593                                 config.lro.timeout =
2594                                 config.hca_attr.lro_timer_supported_periods[0];
2595                         DRV_LOG(DEBUG, "LRO session timeout set to %d usec",
2596                                 config.lro.timeout);
2597                 }
2598 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER)
2599                 if (config.hca_attr.qos.sup && config.hca_attr.qos.srtcm_sup &&
2600                     config.dv_flow_en) {
2601                         uint8_t reg_c_mask =
2602                                 config.hca_attr.qos.flow_meter_reg_c_ids;
2603                         /*
2604                          * Meter needs two REG_C's for color match and pre-sfx
2605                          * flow match. Here get the REG_C for color match.
2606                          * REG_C_0 and REG_C_1 is reserved for metadata feature.
2607                          */
2608                         reg_c_mask &= 0xfc;
2609                         if (__builtin_popcount(reg_c_mask) < 1) {
2610                                 priv->mtr_en = 0;
2611                                 DRV_LOG(WARNING, "No available register for"
2612                                         " meter.");
2613                         } else {
2614                                 priv->mtr_color_reg = ffs(reg_c_mask) - 1 +
2615                                                       REG_C_0;
2616                                 priv->mtr_en = 1;
2617                                 priv->mtr_reg_share =
2618                                       config.hca_attr.qos.flow_meter_reg_share;
2619                                 DRV_LOG(DEBUG, "The REG_C meter uses is %d",
2620                                         priv->mtr_color_reg);
2621                         }
2622                 }
2623 #endif
2624         }
2625         if (config.mprq.enabled && mprq) {
2626                 if (config.mprq.stride_num_n &&
2627                     (config.mprq.stride_num_n > mprq_max_stride_num_n ||
2628                      config.mprq.stride_num_n < mprq_min_stride_num_n)) {
2629                         config.mprq.stride_num_n =
2630                                 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
2631                                                 mprq_min_stride_num_n),
2632                                         mprq_max_stride_num_n);
2633                         DRV_LOG(WARNING,
2634                                 "the number of strides"
2635                                 " for Multi-Packet RQ is out of range,"
2636                                 " setting default value (%u)",
2637                                 1 << config.mprq.stride_num_n);
2638                 }
2639                 if (config.mprq.stride_size_n &&
2640                     (config.mprq.stride_size_n > mprq_max_stride_size_n ||
2641                      config.mprq.stride_size_n < mprq_min_stride_size_n)) {
2642                         config.mprq.stride_size_n =
2643                                 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N,
2644                                                 mprq_min_stride_size_n),
2645                                         mprq_max_stride_size_n);
2646                         DRV_LOG(WARNING,
2647                                 "the size of a stride"
2648                                 " for Multi-Packet RQ is out of range,"
2649                                 " setting default value (%u)",
2650                                 1 << config.mprq.stride_size_n);
2651                 }
2652                 config.mprq.min_stride_size_n = mprq_min_stride_size_n;
2653                 config.mprq.max_stride_size_n = mprq_max_stride_size_n;
2654         } else if (config.mprq.enabled && !mprq) {
2655                 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
2656                 config.mprq.enabled = 0;
2657         }
2658         if (config.max_dump_files_num == 0)
2659                 config.max_dump_files_num = 128;
2660         eth_dev = rte_eth_dev_allocate(name);
2661         if (eth_dev == NULL) {
2662                 DRV_LOG(ERR, "can not allocate rte ethdev");
2663                 err = ENOMEM;
2664                 goto error;
2665         }
2666         /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */
2667         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2668         if (priv->representor) {
2669                 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
2670                 eth_dev->data->representor_id = priv->representor_id;
2671         }
2672         /*
2673          * Store associated network device interface index. This index
2674          * is permanent throughout the lifetime of device. So, we may store
2675          * the ifindex here and use the cached value further.
2676          */
2677         MLX5_ASSERT(spawn->ifindex);
2678         priv->if_index = spawn->ifindex;
2679         eth_dev->data->dev_private = priv;
2680         priv->dev_data = eth_dev->data;
2681         eth_dev->data->mac_addrs = priv->mac;
2682         eth_dev->device = dpdk_dev;
2683         /* Configure the first MAC address by default. */
2684         if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
2685                 DRV_LOG(ERR,
2686                         "port %u cannot get MAC address, is mlx5_en"
2687                         " loaded? (errno: %s)",
2688                         eth_dev->data->port_id, strerror(rte_errno));
2689                 err = ENODEV;
2690                 goto error;
2691         }
2692         DRV_LOG(INFO,
2693                 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
2694                 eth_dev->data->port_id,
2695                 mac.addr_bytes[0], mac.addr_bytes[1],
2696                 mac.addr_bytes[2], mac.addr_bytes[3],
2697                 mac.addr_bytes[4], mac.addr_bytes[5]);
2698 #ifdef RTE_LIBRTE_MLX5_DEBUG
2699         {
2700                 char ifname[IF_NAMESIZE];
2701
2702                 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
2703                         DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
2704                                 eth_dev->data->port_id, ifname);
2705                 else
2706                         DRV_LOG(DEBUG, "port %u ifname is unknown",
2707                                 eth_dev->data->port_id);
2708         }
2709 #endif
2710         /* Get actual MTU if possible. */
2711         err = mlx5_get_mtu(eth_dev, &priv->mtu);
2712         if (err) {
2713                 err = rte_errno;
2714                 goto error;
2715         }
2716         DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
2717                 priv->mtu);
2718         /* Initialize burst functions to prevent crashes before link-up. */
2719         eth_dev->rx_pkt_burst = removed_rx_burst;
2720         eth_dev->tx_pkt_burst = removed_tx_burst;
2721         eth_dev->dev_ops = &mlx5_dev_ops;
2722         /* Register MAC address. */
2723         claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
2724         if (config.vf && config.vf_nl_en)
2725                 mlx5_nl_mac_addr_sync(priv->nl_socket_route,
2726                                       mlx5_ifindex(eth_dev),
2727                                       eth_dev->data->mac_addrs,
2728                                       MLX5_MAX_MAC_ADDRESSES);
2729         TAILQ_INIT(&priv->flows);
2730         TAILQ_INIT(&priv->ctrl_flows);
2731         TAILQ_INIT(&priv->flow_meters);
2732         TAILQ_INIT(&priv->flow_meter_profiles);
2733         /* Hint libmlx5 to use PMD allocator for data plane resources */
2734         struct mlx5dv_ctx_allocators alctr = {
2735                 .alloc = &mlx5_alloc_verbs_buf,
2736                 .free = &mlx5_free_verbs_buf,
2737                 .data = priv,
2738         };
2739         mlx5_glue->dv_set_context_attr(sh->ctx,
2740                                        MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
2741                                        (void *)((uintptr_t)&alctr));
2742         /* Bring Ethernet device up. */
2743         DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
2744                 eth_dev->data->port_id);
2745         mlx5_set_link_up(eth_dev);
2746         /*
2747          * Even though the interrupt handler is not installed yet,
2748          * interrupts will still trigger on the async_fd from
2749          * Verbs context returned by ibv_open_device().
2750          */
2751         mlx5_link_update(eth_dev, 0);
2752 #ifdef HAVE_MLX5DV_DR_ESWITCH
2753         if (!(config.hca_attr.eswitch_manager && config.dv_flow_en &&
2754               (switch_info->representor || switch_info->master)))
2755                 config.dv_esw_en = 0;
2756 #else
2757         config.dv_esw_en = 0;
2758 #endif
2759         /* Detect minimal data bytes to inline. */
2760         mlx5_set_min_inline(spawn, &config);
2761         /* Store device configuration on private structure. */
2762         priv->config = config;
2763         /* Create context for virtual machine VLAN workaround. */
2764         priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex);
2765         if (config.dv_flow_en) {
2766                 err = mlx5_alloc_shared_dr(priv);
2767                 if (err)
2768                         goto error;
2769                 /*
2770                  * RSS id is shared with meter flow id. Meter flow id can only
2771                  * use the 24 MSB of the register.
2772                  */
2773                 priv->qrss_id_pool = mlx5_flow_id_pool_alloc(UINT32_MAX >>
2774                                      MLX5_MTR_COLOR_BITS);
2775                 if (!priv->qrss_id_pool) {
2776                         DRV_LOG(ERR, "can't create flow id pool");
2777                         err = ENOMEM;
2778                         goto error;
2779                 }
2780         }
2781         /* Supported Verbs flow priority number detection. */
2782         err = mlx5_flow_discover_priorities(eth_dev);
2783         if (err < 0) {
2784                 err = -err;
2785                 goto error;
2786         }
2787         priv->config.flow_prio = err;
2788         if (!priv->config.dv_esw_en &&
2789             priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2790                 DRV_LOG(WARNING, "metadata mode %u is not supported "
2791                                  "(no E-Switch)", priv->config.dv_xmeta_en);
2792                 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY;
2793         }
2794         mlx5_set_metadata_mask(eth_dev);
2795         if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
2796             !priv->sh->dv_regc0_mask) {
2797                 DRV_LOG(ERR, "metadata mode %u is not supported "
2798                              "(no metadata reg_c[0] is available)",
2799                              priv->config.dv_xmeta_en);
2800                         err = ENOTSUP;
2801                         goto error;
2802         }
2803         /*
2804          * Allocate the buffer for flow creating, just once.
2805          * The allocation must be done before any flow creating.
2806          */
2807         mlx5_flow_alloc_intermediate(eth_dev);
2808         /* Query availibility of metadata reg_c's. */
2809         err = mlx5_flow_discover_mreg_c(eth_dev);
2810         if (err < 0) {
2811                 err = -err;
2812                 goto error;
2813         }
2814         if (!mlx5_flow_ext_mreg_supported(eth_dev)) {
2815                 DRV_LOG(DEBUG,
2816                         "port %u extensive metadata register is not supported",
2817                         eth_dev->data->port_id);
2818                 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2819                         DRV_LOG(ERR, "metadata mode %u is not supported "
2820                                      "(no metadata registers available)",
2821                                      priv->config.dv_xmeta_en);
2822                         err = ENOTSUP;
2823                         goto error;
2824                 }
2825         }
2826         if (priv->config.dv_flow_en &&
2827             priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
2828             mlx5_flow_ext_mreg_supported(eth_dev) &&
2829             priv->sh->dv_regc0_mask) {
2830                 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME,
2831                                                       MLX5_FLOW_MREG_HTABLE_SZ);
2832                 if (!priv->mreg_cp_tbl) {
2833                         err = ENOMEM;
2834                         goto error;
2835                 }
2836         }
2837         return eth_dev;
2838 error:
2839         if (priv) {
2840                 if (priv->mreg_cp_tbl)
2841                         mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
2842                 if (priv->sh)
2843                         mlx5_free_shared_dr(priv);
2844                 if (priv->nl_socket_route >= 0)
2845                         close(priv->nl_socket_route);
2846                 if (priv->nl_socket_rdma >= 0)
2847                         close(priv->nl_socket_rdma);
2848                 if (priv->vmwa_context)
2849                         mlx5_vlan_vmwa_exit(priv->vmwa_context);
2850                 if (priv->qrss_id_pool)
2851                         mlx5_flow_id_pool_release(priv->qrss_id_pool);
2852                 if (own_domain_id)
2853                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
2854                 rte_free(priv);
2855                 if (eth_dev != NULL)
2856                         eth_dev->data->dev_private = NULL;
2857         }
2858         if (eth_dev != NULL) {
2859                 /* mac_addrs must not be freed alone because part of dev_private */
2860                 eth_dev->data->mac_addrs = NULL;
2861                 rte_eth_dev_release_port(eth_dev);
2862         }
2863         if (sh)
2864                 mlx5_free_shared_ibctx(sh);
2865         MLX5_ASSERT(err > 0);
2866         rte_errno = err;
2867         return NULL;
2868 }
2869
2870 /**
2871  * Comparison callback to sort device data.
2872  *
2873  * This is meant to be used with qsort().
2874  *
2875  * @param a[in]
2876  *   Pointer to pointer to first data object.
2877  * @param b[in]
2878  *   Pointer to pointer to second data object.
2879  *
2880  * @return
2881  *   0 if both objects are equal, less than 0 if the first argument is less
2882  *   than the second, greater than 0 otherwise.
2883  */
2884 static int
2885 mlx5_dev_spawn_data_cmp(const void *a, const void *b)
2886 {
2887         const struct mlx5_switch_info *si_a =
2888                 &((const struct mlx5_dev_spawn_data *)a)->info;
2889         const struct mlx5_switch_info *si_b =
2890                 &((const struct mlx5_dev_spawn_data *)b)->info;
2891         int ret;
2892
2893         /* Master device first. */
2894         ret = si_b->master - si_a->master;
2895         if (ret)
2896                 return ret;
2897         /* Then representor devices. */
2898         ret = si_b->representor - si_a->representor;
2899         if (ret)
2900                 return ret;
2901         /* Unidentified devices come last in no specific order. */
2902         if (!si_a->representor)
2903                 return 0;
2904         /* Order representors by name. */
2905         return si_a->port_name - si_b->port_name;
2906 }
2907
2908 /**
2909  * Match PCI information for possible slaves of bonding device.
2910  *
2911  * @param[in] ibv_dev
2912  *   Pointer to Infiniband device structure.
2913  * @param[in] pci_dev
2914  *   Pointer to PCI device structure to match PCI address.
2915  * @param[in] nl_rdma
2916  *   Netlink RDMA group socket handle.
2917  *
2918  * @return
2919  *   negative value if no bonding device found, otherwise
2920  *   positive index of slave PF in bonding.
2921  */
2922 static int
2923 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev,
2924                            const struct rte_pci_device *pci_dev,
2925                            int nl_rdma)
2926 {
2927         char ifname[IF_NAMESIZE + 1];
2928         unsigned int ifindex;
2929         unsigned int np, i;
2930         FILE *file = NULL;
2931         int pf = -1;
2932
2933         /*
2934          * Try to get master device name. If something goes
2935          * wrong suppose the lack of kernel support and no
2936          * bonding devices.
2937          */
2938         if (nl_rdma < 0)
2939                 return -1;
2940         if (!strstr(ibv_dev->name, "bond"))
2941                 return -1;
2942         np = mlx5_nl_portnum(nl_rdma, ibv_dev->name);
2943         if (!np)
2944                 return -1;
2945         /*
2946          * The Master device might not be on the predefined
2947          * port (not on port index 1, it is not garanted),
2948          * we have to scan all Infiniband device port and
2949          * find master.
2950          */
2951         for (i = 1; i <= np; ++i) {
2952                 /* Check whether Infiniband port is populated. */
2953                 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i);
2954                 if (!ifindex)
2955                         continue;
2956                 if (!if_indextoname(ifindex, ifname))
2957                         continue;
2958                 /* Try to read bonding slave names from sysfs. */
2959                 MKSTR(slaves,
2960                       "/sys/class/net/%s/master/bonding/slaves", ifname);
2961                 file = fopen(slaves, "r");
2962                 if (file)
2963                         break;
2964         }
2965         if (!file)
2966                 return -1;
2967         /* Use safe format to check maximal buffer length. */
2968         MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE);
2969         while (fscanf(file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) {
2970                 char tmp_str[IF_NAMESIZE + 32];
2971                 struct rte_pci_addr pci_addr;
2972                 struct mlx5_switch_info info;
2973
2974                 /* Process slave interface names in the loop. */
2975                 snprintf(tmp_str, sizeof(tmp_str),
2976                          "/sys/class/net/%s", ifname);
2977                 if (mlx5_dev_to_pci_addr(tmp_str, &pci_addr)) {
2978                         DRV_LOG(WARNING, "can not get PCI address"
2979                                          " for netdev \"%s\"", ifname);
2980                         continue;
2981                 }
2982                 if (pci_dev->addr.domain != pci_addr.domain ||
2983                     pci_dev->addr.bus != pci_addr.bus ||
2984                     pci_dev->addr.devid != pci_addr.devid ||
2985                     pci_dev->addr.function != pci_addr.function)
2986                         continue;
2987                 /* Slave interface PCI address match found. */
2988                 fclose(file);
2989                 snprintf(tmp_str, sizeof(tmp_str),
2990                          "/sys/class/net/%s/phys_port_name", ifname);
2991                 file = fopen(tmp_str, "rb");
2992                 if (!file)
2993                         break;
2994                 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET;
2995                 if (fscanf(file, "%32s", tmp_str) == 1)
2996                         mlx5_translate_port_name(tmp_str, &info);
2997                 if (info.name_type == MLX5_PHYS_PORT_NAME_TYPE_LEGACY ||
2998                     info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK)
2999                         pf = info.port_name;
3000                 break;
3001         }
3002         if (file)
3003                 fclose(file);
3004         return pf;
3005 }
3006
3007 /**
3008  * DPDK callback to register a PCI device.
3009  *
3010  * This function spawns Ethernet devices out of a given PCI device.
3011  *
3012  * @param[in] pci_drv
3013  *   PCI driver structure (mlx5_driver).
3014  * @param[in] pci_dev
3015  *   PCI device information.
3016  *
3017  * @return
3018  *   0 on success, a negative errno value otherwise and rte_errno is set.
3019  */
3020 static int
3021 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3022                struct rte_pci_device *pci_dev)
3023 {
3024         struct ibv_device **ibv_list;
3025         /*
3026          * Number of found IB Devices matching with requested PCI BDF.
3027          * nd != 1 means there are multiple IB devices over the same
3028          * PCI device and we have representors and master.
3029          */
3030         unsigned int nd = 0;
3031         /*
3032          * Number of found IB device Ports. nd = 1 and np = 1..n means
3033          * we have the single multiport IB device, and there may be
3034          * representors attached to some of found ports.
3035          */
3036         unsigned int np = 0;
3037         /*
3038          * Number of DPDK ethernet devices to Spawn - either over
3039          * multiple IB devices or multiple ports of single IB device.
3040          * Actually this is the number of iterations to spawn.
3041          */
3042         unsigned int ns = 0;
3043         /*
3044          * Bonding device
3045          *   < 0 - no bonding device (single one)
3046          *  >= 0 - bonding device (value is slave PF index)
3047          */
3048         int bd = -1;
3049         struct mlx5_dev_spawn_data *list = NULL;
3050         struct mlx5_dev_config dev_config;
3051         int ret;
3052
3053         if (mlx5_class_get(pci_dev->device.devargs) != MLX5_CLASS_NET) {
3054                 DRV_LOG(DEBUG, "Skip probing - should be probed by other mlx5"
3055                         " driver.");
3056                 return 1;
3057         }
3058         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
3059                 mlx5_pmd_socket_init();
3060         ret = mlx5_init_once();
3061         if (ret) {
3062                 DRV_LOG(ERR, "unable to init PMD global data: %s",
3063                         strerror(rte_errno));
3064                 return -rte_errno;
3065         }
3066         MLX5_ASSERT(pci_drv == &mlx5_driver);
3067         errno = 0;
3068         ibv_list = mlx5_glue->get_device_list(&ret);
3069         if (!ibv_list) {
3070                 rte_errno = errno ? errno : ENOSYS;
3071                 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?");
3072                 return -rte_errno;
3073         }
3074         /*
3075          * First scan the list of all Infiniband devices to find
3076          * matching ones, gathering into the list.
3077          */
3078         struct ibv_device *ibv_match[ret + 1];
3079         int nl_route = mlx5_nl_init(NETLINK_ROUTE);
3080         int nl_rdma = mlx5_nl_init(NETLINK_RDMA);
3081         unsigned int i;
3082
3083         while (ret-- > 0) {
3084                 struct rte_pci_addr pci_addr;
3085
3086                 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name);
3087                 bd = mlx5_device_bond_pci_match
3088                                 (ibv_list[ret], pci_dev, nl_rdma);
3089                 if (bd >= 0) {
3090                         /*
3091                          * Bonding device detected. Only one match is allowed,
3092                          * the bonding is supported over multi-port IB device,
3093                          * there should be no matches on representor PCI
3094                          * functions or non VF LAG bonding devices with
3095                          * specified address.
3096                          */
3097                         if (nd) {
3098                                 DRV_LOG(ERR,
3099                                         "multiple PCI match on bonding device"
3100                                         "\"%s\" found", ibv_list[ret]->name);
3101                                 rte_errno = ENOENT;
3102                                 ret = -rte_errno;
3103                                 goto exit;
3104                         }
3105                         DRV_LOG(INFO, "PCI information matches for"
3106                                       " slave %d bonding device \"%s\"",
3107                                       bd, ibv_list[ret]->name);
3108                         ibv_match[nd++] = ibv_list[ret];
3109                         break;
3110                 }
3111                 if (mlx5_dev_to_pci_addr
3112                         (ibv_list[ret]->ibdev_path, &pci_addr))
3113                         continue;
3114                 if (pci_dev->addr.domain != pci_addr.domain ||
3115                     pci_dev->addr.bus != pci_addr.bus ||
3116                     pci_dev->addr.devid != pci_addr.devid ||
3117                     pci_dev->addr.function != pci_addr.function)
3118                         continue;
3119                 DRV_LOG(INFO, "PCI information matches for device \"%s\"",
3120                         ibv_list[ret]->name);
3121                 ibv_match[nd++] = ibv_list[ret];
3122         }
3123         ibv_match[nd] = NULL;
3124         if (!nd) {
3125                 /* No device matches, just complain and bail out. */
3126                 DRV_LOG(WARNING,
3127                         "no Verbs device matches PCI device " PCI_PRI_FMT ","
3128                         " are kernel drivers loaded?",
3129                         pci_dev->addr.domain, pci_dev->addr.bus,
3130                         pci_dev->addr.devid, pci_dev->addr.function);
3131                 rte_errno = ENOENT;
3132                 ret = -rte_errno;
3133                 goto exit;
3134         }
3135         if (nd == 1) {
3136                 /*
3137                  * Found single matching device may have multiple ports.
3138                  * Each port may be representor, we have to check the port
3139                  * number and check the representors existence.
3140                  */
3141                 if (nl_rdma >= 0)
3142                         np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name);
3143                 if (!np)
3144                         DRV_LOG(WARNING, "can not get IB device \"%s\""
3145                                          " ports number", ibv_match[0]->name);
3146                 if (bd >= 0 && !np) {
3147                         DRV_LOG(ERR, "can not get ports"
3148                                      " for bonding device");
3149                         rte_errno = ENOENT;
3150                         ret = -rte_errno;
3151                         goto exit;
3152                 }
3153         }
3154 #ifndef HAVE_MLX5DV_DR_DEVX_PORT
3155         if (bd >= 0) {
3156                 /*
3157                  * This may happen if there is VF LAG kernel support and
3158                  * application is compiled with older rdma_core library.
3159                  */
3160                 DRV_LOG(ERR,
3161                         "No kernel/verbs support for VF LAG bonding found.");
3162                 rte_errno = ENOTSUP;
3163                 ret = -rte_errno;
3164                 goto exit;
3165         }
3166 #endif
3167         /*
3168          * Now we can determine the maximal
3169          * amount of devices to be spawned.
3170          */
3171         list = rte_zmalloc("device spawn data",
3172                          sizeof(struct mlx5_dev_spawn_data) *
3173                          (np ? np : nd),
3174                          RTE_CACHE_LINE_SIZE);
3175         if (!list) {
3176                 DRV_LOG(ERR, "spawn data array allocation failure");
3177                 rte_errno = ENOMEM;
3178                 ret = -rte_errno;
3179                 goto exit;
3180         }
3181         if (bd >= 0 || np > 1) {
3182                 /*
3183                  * Single IB device with multiple ports found,
3184                  * it may be E-Switch master device and representors.
3185                  * We have to perform identification trough the ports.
3186                  */
3187                 MLX5_ASSERT(nl_rdma >= 0);
3188                 MLX5_ASSERT(ns == 0);
3189                 MLX5_ASSERT(nd == 1);
3190                 MLX5_ASSERT(np);
3191                 for (i = 1; i <= np; ++i) {
3192                         list[ns].max_port = np;
3193                         list[ns].ibv_port = i;
3194                         list[ns].ibv_dev = ibv_match[0];
3195                         list[ns].eth_dev = NULL;
3196                         list[ns].pci_dev = pci_dev;
3197                         list[ns].pf_bond = bd;
3198                         list[ns].ifindex = mlx5_nl_ifindex
3199                                         (nl_rdma, list[ns].ibv_dev->name, i);
3200                         if (!list[ns].ifindex) {
3201                                 /*
3202                                  * No network interface index found for the
3203                                  * specified port, it means there is no
3204                                  * representor on this port. It's OK,
3205                                  * there can be disabled ports, for example
3206                                  * if sriov_numvfs < sriov_totalvfs.
3207                                  */
3208                                 continue;
3209                         }
3210                         ret = -1;
3211                         if (nl_route >= 0)
3212                                 ret = mlx5_nl_switch_info
3213                                                (nl_route,
3214                                                 list[ns].ifindex,
3215                                                 &list[ns].info);
3216                         if (ret || (!list[ns].info.representor &&
3217                                     !list[ns].info.master)) {
3218                                 /*
3219                                  * We failed to recognize representors with
3220                                  * Netlink, let's try to perform the task
3221                                  * with sysfs.
3222                                  */
3223                                 ret =  mlx5_sysfs_switch_info
3224                                                 (list[ns].ifindex,
3225                                                  &list[ns].info);
3226                         }
3227                         if (!ret && bd >= 0) {
3228                                 switch (list[ns].info.name_type) {
3229                                 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK:
3230                                         if (list[ns].info.port_name == bd)
3231                                                 ns++;
3232                                         break;
3233                                 case MLX5_PHYS_PORT_NAME_TYPE_PFVF:
3234                                         if (list[ns].info.pf_num == bd)
3235                                                 ns++;
3236                                         break;
3237                                 default:
3238                                         break;
3239                                 }
3240                                 continue;
3241                         }
3242                         if (!ret && (list[ns].info.representor ^
3243                                      list[ns].info.master))
3244                                 ns++;
3245                 }
3246                 if (!ns) {
3247                         DRV_LOG(ERR,
3248                                 "unable to recognize master/representors"
3249                                 " on the IB device with multiple ports");
3250                         rte_errno = ENOENT;
3251                         ret = -rte_errno;
3252                         goto exit;
3253                 }
3254         } else {
3255                 /*
3256                  * The existence of several matching entries (nd > 1) means
3257                  * port representors have been instantiated. No existing Verbs
3258                  * call nor sysfs entries can tell them apart, this can only
3259                  * be done through Netlink calls assuming kernel drivers are
3260                  * recent enough to support them.
3261                  *
3262                  * In the event of identification failure through Netlink,
3263                  * try again through sysfs, then:
3264                  *
3265                  * 1. A single IB device matches (nd == 1) with single
3266                  *    port (np=0/1) and is not a representor, assume
3267                  *    no switch support.
3268                  *
3269                  * 2. Otherwise no safe assumptions can be made;
3270                  *    complain louder and bail out.
3271                  */
3272                 np = 1;
3273                 for (i = 0; i != nd; ++i) {
3274                         memset(&list[ns].info, 0, sizeof(list[ns].info));
3275                         list[ns].max_port = 1;
3276                         list[ns].ibv_port = 1;
3277                         list[ns].ibv_dev = ibv_match[i];
3278                         list[ns].eth_dev = NULL;
3279                         list[ns].pci_dev = pci_dev;
3280                         list[ns].pf_bond = -1;
3281                         list[ns].ifindex = 0;
3282                         if (nl_rdma >= 0)
3283                                 list[ns].ifindex = mlx5_nl_ifindex
3284                                         (nl_rdma, list[ns].ibv_dev->name, 1);
3285                         if (!list[ns].ifindex) {
3286                                 char ifname[IF_NAMESIZE];
3287
3288                                 /*
3289                                  * Netlink failed, it may happen with old
3290                                  * ib_core kernel driver (before 4.16).
3291                                  * We can assume there is old driver because
3292                                  * here we are processing single ports IB
3293                                  * devices. Let's try sysfs to retrieve
3294                                  * the ifindex. The method works for
3295                                  * master device only.
3296                                  */
3297                                 if (nd > 1) {
3298                                         /*
3299                                          * Multiple devices found, assume
3300                                          * representors, can not distinguish
3301                                          * master/representor and retrieve
3302                                          * ifindex via sysfs.
3303                                          */
3304                                         continue;
3305                                 }
3306                                 ret = mlx5_get_master_ifname
3307                                         (ibv_match[i]->ibdev_path, &ifname);
3308                                 if (!ret)
3309                                         list[ns].ifindex =
3310                                                 if_nametoindex(ifname);
3311                                 if (!list[ns].ifindex) {
3312                                         /*
3313                                          * No network interface index found
3314                                          * for the specified device, it means
3315                                          * there it is neither representor
3316                                          * nor master.
3317                                          */
3318                                         continue;
3319                                 }
3320                         }
3321                         ret = -1;
3322                         if (nl_route >= 0)
3323                                 ret = mlx5_nl_switch_info
3324                                                (nl_route,
3325                                                 list[ns].ifindex,
3326                                                 &list[ns].info);
3327                         if (ret || (!list[ns].info.representor &&
3328                                     !list[ns].info.master)) {
3329                                 /*
3330                                  * We failed to recognize representors with
3331                                  * Netlink, let's try to perform the task
3332                                  * with sysfs.
3333                                  */
3334                                 ret =  mlx5_sysfs_switch_info
3335                                                 (list[ns].ifindex,
3336                                                  &list[ns].info);
3337                         }
3338                         if (!ret && (list[ns].info.representor ^
3339                                      list[ns].info.master)) {
3340                                 ns++;
3341                         } else if ((nd == 1) &&
3342                                    !list[ns].info.representor &&
3343                                    !list[ns].info.master) {
3344                                 /*
3345                                  * Single IB device with
3346                                  * one physical port and
3347                                  * attached network device.
3348                                  * May be SRIOV is not enabled
3349                                  * or there is no representors.
3350                                  */
3351                                 DRV_LOG(INFO, "no E-Switch support detected");
3352                                 ns++;
3353                                 break;
3354                         }
3355                 }
3356                 if (!ns) {
3357                         DRV_LOG(ERR,
3358                                 "unable to recognize master/representors"
3359                                 " on the multiple IB devices");
3360                         rte_errno = ENOENT;
3361                         ret = -rte_errno;
3362                         goto exit;
3363                 }
3364         }
3365         MLX5_ASSERT(ns);
3366         /*
3367          * Sort list to probe devices in natural order for users convenience
3368          * (i.e. master first, then representors from lowest to highest ID).
3369          */
3370         qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp);
3371         /* Default configuration. */
3372         dev_config = (struct mlx5_dev_config){
3373                 .hw_padding = 0,
3374                 .mps = MLX5_ARG_UNSET,
3375                 .dbnc = MLX5_ARG_UNSET,
3376                 .rx_vec_en = 1,
3377                 .txq_inline_max = MLX5_ARG_UNSET,
3378                 .txq_inline_min = MLX5_ARG_UNSET,
3379                 .txq_inline_mpw = MLX5_ARG_UNSET,
3380                 .txqs_inline = MLX5_ARG_UNSET,
3381                 .vf_nl_en = 1,
3382                 .mr_ext_memseg_en = 1,
3383                 .mprq = {
3384                         .enabled = 0, /* Disabled by default. */
3385                         .stride_num_n = 0,
3386                         .stride_size_n = 0,
3387                         .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
3388                         .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
3389                 },
3390                 .dv_esw_en = 1,
3391                 .dv_flow_en = 1,
3392                 .log_hp_size = MLX5_ARG_UNSET,
3393         };
3394         /* Device specific configuration. */
3395         switch (pci_dev->id.device_id) {
3396         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
3397         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
3398         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
3399         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
3400         case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF:
3401         case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF:
3402         case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF:
3403                 dev_config.vf = 1;
3404                 break;
3405         default:
3406                 break;
3407         }
3408         for (i = 0; i != ns; ++i) {
3409                 uint32_t restore;
3410
3411                 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device,
3412                                                  &list[i],
3413                                                  dev_config);
3414                 if (!list[i].eth_dev) {
3415                         if (rte_errno != EBUSY && rte_errno != EEXIST)
3416                                 break;
3417                         /* Device is disabled or already spawned. Ignore it. */
3418                         continue;
3419                 }
3420                 restore = list[i].eth_dev->data->dev_flags;
3421                 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev);
3422                 /* Restore non-PCI flags cleared by the above call. */
3423                 list[i].eth_dev->data->dev_flags |= restore;
3424                 mlx5_dev_interrupt_handler_devx_install(list[i].eth_dev);
3425                 rte_eth_dev_probing_finish(list[i].eth_dev);
3426         }
3427         if (i != ns) {
3428                 DRV_LOG(ERR,
3429                         "probe of PCI device " PCI_PRI_FMT " aborted after"
3430                         " encountering an error: %s",
3431                         pci_dev->addr.domain, pci_dev->addr.bus,
3432                         pci_dev->addr.devid, pci_dev->addr.function,
3433                         strerror(rte_errno));
3434                 ret = -rte_errno;
3435                 /* Roll back. */
3436                 while (i--) {
3437                         if (!list[i].eth_dev)
3438                                 continue;
3439                         mlx5_dev_close(list[i].eth_dev);
3440                         /* mac_addrs must not be freed because in dev_private */
3441                         list[i].eth_dev->data->mac_addrs = NULL;
3442                         claim_zero(rte_eth_dev_release_port(list[i].eth_dev));
3443                 }
3444                 /* Restore original error. */
3445                 rte_errno = -ret;
3446         } else {
3447                 ret = 0;
3448         }
3449 exit:
3450         /*
3451          * Do the routine cleanup:
3452          * - close opened Netlink sockets
3453          * - free allocated spawn data array
3454          * - free the Infiniband device list
3455          */
3456         if (nl_rdma >= 0)
3457                 close(nl_rdma);
3458         if (nl_route >= 0)
3459                 close(nl_route);
3460         if (list)
3461                 rte_free(list);
3462         MLX5_ASSERT(ibv_list);
3463         mlx5_glue->free_device_list(ibv_list);
3464         return ret;
3465 }
3466
3467 /**
3468  * Look for the ethernet device belonging to mlx5 driver.
3469  *
3470  * @param[in] port_id
3471  *   port_id to start looking for device.
3472  * @param[in] pci_dev
3473  *   Pointer to the hint PCI device. When device is being probed
3474  *   the its siblings (master and preceding representors might
3475  *   not have assigned driver yet (because the mlx5_pci_probe()
3476  *   is not completed yet, for this case match on hint PCI
3477  *   device may be used to detect sibling device.
3478  *
3479  * @return
3480  *   port_id of found device, RTE_MAX_ETHPORT if not found.
3481  */
3482 uint16_t
3483 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
3484 {
3485         while (port_id < RTE_MAX_ETHPORTS) {
3486                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
3487
3488                 if (dev->state != RTE_ETH_DEV_UNUSED &&
3489                     dev->device &&
3490                     (dev->device == &pci_dev->device ||
3491                      (dev->device->driver &&
3492                      dev->device->driver->name &&
3493                      !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
3494                         break;
3495                 port_id++;
3496         }
3497         if (port_id >= RTE_MAX_ETHPORTS)
3498                 return RTE_MAX_ETHPORTS;
3499         return port_id;
3500 }
3501
3502 /**
3503  * DPDK callback to remove a PCI device.
3504  *
3505  * This function removes all Ethernet devices belong to a given PCI device.
3506  *
3507  * @param[in] pci_dev
3508  *   Pointer to the PCI device.
3509  *
3510  * @return
3511  *   0 on success, the function cannot fail.
3512  */
3513 static int
3514 mlx5_pci_remove(struct rte_pci_device *pci_dev)
3515 {
3516         uint16_t port_id;
3517
3518         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device)
3519                 rte_eth_dev_close(port_id);
3520         return 0;
3521 }
3522
3523 static const struct rte_pci_id mlx5_pci_id_map[] = {
3524         {
3525                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3526                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
3527         },
3528         {
3529                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3530                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
3531         },
3532         {
3533                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3534                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
3535         },
3536         {
3537                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3538                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
3539         },
3540         {
3541                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3542                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
3543         },
3544         {
3545                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3546                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
3547         },
3548         {
3549                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3550                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
3551         },
3552         {
3553                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3554                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
3555         },
3556         {
3557                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3558                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
3559         },
3560         {
3561                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3562                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
3563         },
3564         {
3565                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3566                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
3567         },
3568         {
3569                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3570                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
3571         },
3572         {
3573                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3574                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
3575         },
3576         {
3577                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3578                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
3579         },
3580         {
3581                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3582                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
3583         },
3584         {
3585                 .vendor_id = 0
3586         }
3587 };
3588
3589 static struct rte_pci_driver mlx5_driver = {
3590         .driver = {
3591                 .name = MLX5_DRIVER_NAME
3592         },
3593         .id_table = mlx5_pci_id_map,
3594         .probe = mlx5_pci_probe,
3595         .remove = mlx5_pci_remove,
3596         .dma_map = mlx5_dma_map,
3597         .dma_unmap = mlx5_dma_unmap,
3598         .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV |
3599                      RTE_PCI_DRV_PROBE_AGAIN,
3600 };
3601
3602 /**
3603  * Driver initialization routine.
3604  */
3605 RTE_INIT(rte_mlx5_pmd_init)
3606 {
3607         /* Initialize driver log type. */
3608         mlx5_logtype = rte_log_register("pmd.net.mlx5");
3609         if (mlx5_logtype >= 0)
3610                 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
3611
3612         /* Build the static tables for Verbs conversion. */
3613         mlx5_set_ptype_table();
3614         mlx5_set_cksum_table();
3615         mlx5_set_swp_types_table();
3616         if (mlx5_glue)
3617                 rte_pci_register(&mlx5_driver);
3618 }
3619
3620 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
3621 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
3622 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");