drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <assert.h>
  10 #include <dlfcn.h>
  11 #include <stdint.h>
  12 #include <stdlib.h>
  13 #include <errno.h>
  14 #include <net/if.h>
  15 #include <sys/mman.h>
  16 #include <linux/rtnetlink.h>
  17
  18 /* Verbs header. */
  19 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  20 #ifdef PEDANTIC
  21 #pragma GCC diagnostic ignored "-Wpedantic"
  22 #endif
  23 #include <infiniband/verbs.h>
  24 #ifdef PEDANTIC
  25 #pragma GCC diagnostic error "-Wpedantic"
  26 #endif
  27
  28 #include <rte_malloc.h>
  29 #include <rte_ethdev_driver.h>
  30 #include <rte_ethdev_pci.h>
  31 #include <rte_pci.h>
  32 #include <rte_bus_pci.h>
  33 #include <rte_common.h>
  34 #include <rte_config.h>
  35 #include <rte_eal_memconfig.h>
  36 #include <rte_kvargs.h>
  37 #include <rte_rwlock.h>
  38 #include <rte_spinlock.h>
  39 #include <rte_string_fns.h>
  40
  41 #include "mlx5.h"
  42 #include "mlx5_utils.h"
  43 #include "mlx5_rxtx.h"
  44 #include "mlx5_autoconf.h"
  45 #include "mlx5_defs.h"
  46 #include "mlx5_glue.h"
  47 #include "mlx5_mr.h"
  48
  49 /* Device parameter to enable RX completion queue compression. */
  50 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  51
  52 /* Device parameter to enable Multi-Packet Rx queue. */
  53 #define MLX5_RX_MPRQ_EN "mprq_en"
  54
  55 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  56 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  57
  58 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  59 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  60
  61 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  62 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  63
  64 /* Device parameter to configure inline send. */
  65 #define MLX5_TXQ_INLINE "txq_inline"
  66
  67 /*
  68  * Device parameter to configure the number of TX queues threshold for
  69  * enabling inline send.
  70  */
  71 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  72
  73 /* Device parameter to enable multi-packet send WQEs. */
  74 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  75
  76 /* Device parameter to include 2 dsegs in the title WQEBB. */
  77 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
  78
  79 /* Device parameter to limit the size of inlining packet. */
  80 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
  81
  82 /* Device parameter to enable hardware Tx vector. */
  83 #define MLX5_TX_VEC_EN "tx_vec_en"
  84
  85 /* Device parameter to enable hardware Rx vector. */
  86 #define MLX5_RX_VEC_EN "rx_vec_en"
  87
  88 /* Allow L3 VXLAN flow creation. */
  89 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
  90
  91 /* Activate Netlink support in VF mode. */
  92 #define MLX5_VF_NL_EN "vf_nl_en"
  93
  94 #ifndef HAVE_IBV_MLX5_MOD_MPW
  95 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
  96 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
  97 #endif
  98
  99 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
 100 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
 101 #endif
 102
 103 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
 104
 105 /* Shared memory between primary and secondary processes. */
 106 struct mlx5_shared_data *mlx5_shared_data;
 107
 108 /* Spinlock for mlx5_shared_data allocation. */
 109 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
 110
 111 /** Driver-specific log messages type. */
 112 int mlx5_logtype;
 113
 114 /**
 115  * Prepare shared data between primary and secondary process.
 116  */
 117 static void
 118 mlx5_prepare_shared_data(void)
 119 {
 120         const struct rte_memzone *mz;
 121
 122         rte_spinlock_lock(&mlx5_shared_data_lock);
 123         if (mlx5_shared_data == NULL) {
 124                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
 125                         /* Allocate shared memory. */
 126                         mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
 127                                                  sizeof(*mlx5_shared_data),
 128                                                  SOCKET_ID_ANY, 0);
 129                 } else {
 130                         /* Lookup allocated shared memory. */
 131                         mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
 132                 }
 133                 if (mz == NULL)
 134                         rte_panic("Cannot allocate mlx5 shared data\n");
 135                 mlx5_shared_data = mz->addr;
 136                 /* Initialize shared data. */
 137                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
 138                         LIST_INIT(&mlx5_shared_data->mem_event_cb_list);
 139                         rte_rwlock_init(&mlx5_shared_data->mem_event_rwlock);
 140                 }
 141                 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
 142                                                 mlx5_mr_mem_event_cb, NULL);
 143         }
 144         rte_spinlock_unlock(&mlx5_shared_data_lock);
 145 }
 146
 147 /**
 148  * Retrieve integer value from environment variable.
 149  *
 150  * @param[in] name
 151  *   Environment variable name.
 152  *
 153  * @return
 154  *   Integer value, 0 if the variable is not set.
 155  */
 156 int
 157 mlx5_getenv_int(const char *name)
 158 {
 159         const char *val = getenv(name);
 160
 161         if (val == NULL)
 162                 return 0;
 163         return atoi(val);
 164 }
 165
 166 /**
 167  * Verbs callback to allocate a memory. This function should allocate the space
 168  * according to the size provided residing inside a huge page.
 169  * Please note that all allocation must respect the alignment from libmlx5
 170  * (i.e. currently sysconf(_SC_PAGESIZE)).
 171  *
 172  * @param[in] size
 173  *   The size in bytes of the memory to allocate.
 174  * @param[in] data
 175  *   A pointer to the callback data.
 176  *
 177  * @return
 178  *   Allocated buffer, NULL otherwise and rte_errno is set.
 179  */
 180 static void *
 181 mlx5_alloc_verbs_buf(size_t size, void *data)
 182 {
 183         struct priv *priv = data;
 184         void *ret;
 185         size_t alignment = sysconf(_SC_PAGESIZE);
 186         unsigned int socket = SOCKET_ID_ANY;
 187
 188         if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
 189                 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
 190
 191                 socket = ctrl->socket;
 192         } else if (priv->verbs_alloc_ctx.type ==
 193                    MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
 194                 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
 195
 196                 socket = ctrl->socket;
 197         }
 198         assert(data != NULL);
 199         ret = rte_malloc_socket(__func__, size, alignment, socket);
 200         if (!ret && size)
 201                 rte_errno = ENOMEM;
 202         return ret;
 203 }
 204
 205 /**
 206  * Verbs callback to free a memory.
 207  *
 208  * @param[in] ptr
 209  *   A pointer to the memory to free.
 210  * @param[in] data
 211  *   A pointer to the callback data.
 212  */
 213 static void
 214 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
 215 {
 216         assert(data != NULL);
 217         rte_free(ptr);
 218 }
 219
 220 /**
 221  * DPDK callback to close the device.
 222  *
 223  * Destroy all queues and objects, free memory.
 224  *
 225  * @param dev
 226  *   Pointer to Ethernet device structure.
 227  */
 228 static void
 229 mlx5_dev_close(struct rte_eth_dev *dev)
 230 {
 231         struct priv *priv = dev->data->dev_private;
 232         unsigned int i;
 233         int ret;
 234
 235         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
 236                 dev->data->port_id,
 237                 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
 238         /* In case mlx5_dev_stop() has not been called. */
 239         mlx5_dev_interrupt_handler_uninstall(dev);
 240         mlx5_traffic_disable(dev);
 241         /* Prevent crashes when queues are still in use. */
 242         dev->rx_pkt_burst = removed_rx_burst;
 243         dev->tx_pkt_burst = removed_tx_burst;
 244         if (priv->rxqs != NULL) {
 245                 /* XXX race condition if mlx5_rx_burst() is still running. */
 246                 usleep(1000);
 247                 for (i = 0; (i != priv->rxqs_n); ++i)
 248                         mlx5_rxq_release(dev, i);
 249                 priv->rxqs_n = 0;
 250                 priv->rxqs = NULL;
 251         }
 252         if (priv->txqs != NULL) {
 253                 /* XXX race condition if mlx5_tx_burst() is still running. */
 254                 usleep(1000);
 255                 for (i = 0; (i != priv->txqs_n); ++i)
 256                         mlx5_txq_release(dev, i);
 257                 priv->txqs_n = 0;
 258                 priv->txqs = NULL;
 259         }
 260         mlx5_flow_delete_drop_queue(dev);
 261         mlx5_mprq_free_mp(dev);
 262         mlx5_mr_release(dev);
 263         if (priv->pd != NULL) {
 264                 assert(priv->ctx != NULL);
 265                 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
 266                 claim_zero(mlx5_glue->close_device(priv->ctx));
 267         } else
 268                 assert(priv->ctx == NULL);
 269         if (priv->rss_conf.rss_key != NULL)
 270                 rte_free(priv->rss_conf.rss_key);
 271         if (priv->reta_idx != NULL)
 272                 rte_free(priv->reta_idx);
 273         if (priv->primary_socket)
 274                 mlx5_socket_uninit(dev);
 275         if (priv->config.vf)
 276                 mlx5_nl_mac_addr_flush(dev);
 277         if (priv->nl_socket >= 0)
 278                 close(priv->nl_socket);
 279         ret = mlx5_hrxq_ibv_verify(dev);
 280         if (ret)
 281                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
 282                         dev->data->port_id);
 283         ret = mlx5_ind_table_ibv_verify(dev);
 284         if (ret)
 285                 DRV_LOG(WARNING, "port %u some indirection table still remain",
 286                         dev->data->port_id);
 287         ret = mlx5_rxq_ibv_verify(dev);
 288         if (ret)
 289                 DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain",
 290                         dev->data->port_id);
 291         ret = mlx5_rxq_verify(dev);
 292         if (ret)
 293                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
 294                         dev->data->port_id);
 295         ret = mlx5_txq_ibv_verify(dev);
 296         if (ret)
 297                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
 298                         dev->data->port_id);
 299         ret = mlx5_txq_verify(dev);
 300         if (ret)
 301                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
 302                         dev->data->port_id);
 303         ret = mlx5_flow_verify(dev);
 304         if (ret)
 305                 DRV_LOG(WARNING, "port %u some flows still remain",
 306                         dev->data->port_id);
 307         memset(priv, 0, sizeof(*priv));
 308 }
 309
 310 const struct eth_dev_ops mlx5_dev_ops = {
 311         .dev_configure = mlx5_dev_configure,
 312         .dev_start = mlx5_dev_start,
 313         .dev_stop = mlx5_dev_stop,
 314         .dev_set_link_down = mlx5_set_link_down,
 315         .dev_set_link_up = mlx5_set_link_up,
 316         .dev_close = mlx5_dev_close,
 317         .promiscuous_enable = mlx5_promiscuous_enable,
 318         .promiscuous_disable = mlx5_promiscuous_disable,
 319         .allmulticast_enable = mlx5_allmulticast_enable,
 320         .allmulticast_disable = mlx5_allmulticast_disable,
 321         .link_update = mlx5_link_update,
 322         .stats_get = mlx5_stats_get,
 323         .stats_reset = mlx5_stats_reset,
 324         .xstats_get = mlx5_xstats_get,
 325         .xstats_reset = mlx5_xstats_reset,
 326         .xstats_get_names = mlx5_xstats_get_names,
 327         .dev_infos_get = mlx5_dev_infos_get,
 328         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
 329         .vlan_filter_set = mlx5_vlan_filter_set,
 330         .rx_queue_setup = mlx5_rx_queue_setup,
 331         .tx_queue_setup = mlx5_tx_queue_setup,
 332         .rx_queue_release = mlx5_rx_queue_release,
 333         .tx_queue_release = mlx5_tx_queue_release,
 334         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
 335         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
 336         .mac_addr_remove = mlx5_mac_addr_remove,
 337         .mac_addr_add = mlx5_mac_addr_add,
 338         .mac_addr_set = mlx5_mac_addr_set,
 339         .set_mc_addr_list = mlx5_set_mc_addr_list,
 340         .mtu_set = mlx5_dev_set_mtu,
 341         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
 342         .vlan_offload_set = mlx5_vlan_offload_set,
 343         .reta_update = mlx5_dev_rss_reta_update,
 344         .reta_query = mlx5_dev_rss_reta_query,
 345         .rss_hash_update = mlx5_rss_hash_update,
 346         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
 347         .filter_ctrl = mlx5_dev_filter_ctrl,
 348         .rx_descriptor_status = mlx5_rx_descriptor_status,
 349         .tx_descriptor_status = mlx5_tx_descriptor_status,
 350         .rx_queue_intr_enable = mlx5_rx_intr_enable,
 351         .rx_queue_intr_disable = mlx5_rx_intr_disable,
 352         .is_removed = mlx5_is_removed,
 353 };
 354
 355 static const struct eth_dev_ops mlx5_dev_sec_ops = {
 356         .stats_get = mlx5_stats_get,
 357         .stats_reset = mlx5_stats_reset,
 358         .xstats_get = mlx5_xstats_get,
 359         .xstats_reset = mlx5_xstats_reset,
 360         .xstats_get_names = mlx5_xstats_get_names,
 361         .dev_infos_get = mlx5_dev_infos_get,
 362         .rx_descriptor_status = mlx5_rx_descriptor_status,
 363         .tx_descriptor_status = mlx5_tx_descriptor_status,
 364 };
 365
 366 /* Available operators in flow isolated mode. */
 367 const struct eth_dev_ops mlx5_dev_ops_isolate = {
 368         .dev_configure = mlx5_dev_configure,
 369         .dev_start = mlx5_dev_start,
 370         .dev_stop = mlx5_dev_stop,
 371         .dev_set_link_down = mlx5_set_link_down,
 372         .dev_set_link_up = mlx5_set_link_up,
 373         .dev_close = mlx5_dev_close,
 374         .link_update = mlx5_link_update,
 375         .stats_get = mlx5_stats_get,
 376         .stats_reset = mlx5_stats_reset,
 377         .xstats_get = mlx5_xstats_get,
 378         .xstats_reset = mlx5_xstats_reset,
 379         .xstats_get_names = mlx5_xstats_get_names,
 380         .dev_infos_get = mlx5_dev_infos_get,
 381         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
 382         .vlan_filter_set = mlx5_vlan_filter_set,
 383         .rx_queue_setup = mlx5_rx_queue_setup,
 384         .tx_queue_setup = mlx5_tx_queue_setup,
 385         .rx_queue_release = mlx5_rx_queue_release,
 386         .tx_queue_release = mlx5_tx_queue_release,
 387         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
 388         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
 389         .mac_addr_remove = mlx5_mac_addr_remove,
 390         .mac_addr_add = mlx5_mac_addr_add,
 391         .mac_addr_set = mlx5_mac_addr_set,
 392         .set_mc_addr_list = mlx5_set_mc_addr_list,
 393         .mtu_set = mlx5_dev_set_mtu,
 394         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
 395         .vlan_offload_set = mlx5_vlan_offload_set,
 396         .filter_ctrl = mlx5_dev_filter_ctrl,
 397         .rx_descriptor_status = mlx5_rx_descriptor_status,
 398         .tx_descriptor_status = mlx5_tx_descriptor_status,
 399         .rx_queue_intr_enable = mlx5_rx_intr_enable,
 400         .rx_queue_intr_disable = mlx5_rx_intr_disable,
 401         .is_removed = mlx5_is_removed,
 402 };
 403
 404 /**
 405  * Verify and store value for device argument.
 406  *
 407  * @param[in] key
 408  *   Key argument to verify.
 409  * @param[in] val
 410  *   Value associated with key.
 411  * @param opaque
 412  *   User data.
 413  *
 414  * @return
 415  *   0 on success, a negative errno value otherwise and rte_errno is set.
 416  */
 417 static int
 418 mlx5_args_check(const char *key, const char *val, void *opaque)
 419 {
 420         struct mlx5_dev_config *config = opaque;
 421         unsigned long tmp;
 422
 423         errno = 0;
 424         tmp = strtoul(val, NULL, 0);
 425         if (errno) {
 426                 rte_errno = errno;
 427                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
 428                 return -rte_errno;
 429         }
 430         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
 431                 config->cqe_comp = !!tmp;
 432         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
 433                 config->mprq.enabled = !!tmp;
 434         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
 435                 config->mprq.stride_num_n = tmp;
 436         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
 437                 config->mprq.max_memcpy_len = tmp;
 438         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
 439                 config->mprq.min_rxqs_num = tmp;
 440         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
 441                 config->txq_inline = tmp;
 442         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
 443                 config->txqs_inline = tmp;
 444         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
 445                 config->mps = !!tmp ? config->mps : 0;
 446         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
 447                 config->mpw_hdr_dseg = !!tmp;
 448         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
 449                 config->inline_max_packet_sz = tmp;
 450         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
 451                 config->tx_vec_en = !!tmp;
 452         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
 453                 config->rx_vec_en = !!tmp;
 454         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
 455                 config->l3_vxlan_en = !!tmp;
 456         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
 457                 config->vf_nl_en = !!tmp;
 458         } else {
 459                 DRV_LOG(WARNING, "%s: unknown parameter", key);
 460                 rte_errno = EINVAL;
 461                 return -rte_errno;
 462         }
 463         return 0;
 464 }
 465
 466 /**
 467  * Parse device parameters.
 468  *
 469  * @param config
 470  *   Pointer to device configuration structure.
 471  * @param devargs
 472  *   Device arguments structure.
 473  *
 474  * @return
 475  *   0 on success, a negative errno value otherwise and rte_errno is set.
 476  */
 477 static int
 478 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
 479 {
 480         const char **params = (const char *[]){
 481                 MLX5_RXQ_CQE_COMP_EN,
 482                 MLX5_RX_MPRQ_EN,
 483                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
 484                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
 485                 MLX5_RXQS_MIN_MPRQ,
 486                 MLX5_TXQ_INLINE,
 487                 MLX5_TXQS_MIN_INLINE,
 488                 MLX5_TXQ_MPW_EN,
 489                 MLX5_TXQ_MPW_HDR_DSEG_EN,
 490                 MLX5_TXQ_MAX_INLINE_LEN,
 491                 MLX5_TX_VEC_EN,
 492                 MLX5_RX_VEC_EN,
 493                 MLX5_L3_VXLAN_EN,
 494                 MLX5_VF_NL_EN,
 495                 NULL,
 496         };
 497         struct rte_kvargs *kvlist;
 498         int ret = 0;
 499         int i;
 500
 501         if (devargs == NULL)
 502                 return 0;
 503         /* Following UGLY cast is done to pass checkpatch. */
 504         kvlist = rte_kvargs_parse(devargs->args, params);
 505         if (kvlist == NULL)
 506                 return 0;
 507         /* Process parameters. */
 508         for (i = 0; (params[i] != NULL); ++i) {
 509                 if (rte_kvargs_count(kvlist, params[i])) {
 510                         ret = rte_kvargs_process(kvlist, params[i],
 511                                                  mlx5_args_check, config);
 512                         if (ret) {
 513                                 rte_errno = EINVAL;
 514                                 rte_kvargs_free(kvlist);
 515                                 return -rte_errno;
 516                         }
 517                 }
 518         }
 519         rte_kvargs_free(kvlist);
 520         return 0;
 521 }
 522
 523 static struct rte_pci_driver mlx5_driver;
 524
 525 /*
 526  * Reserved UAR address space for TXQ UAR(hw doorbell) mapping, process
 527  * local resource used by both primary and secondary to avoid duplicate
 528  * reservation.
 529  * The space has to be available on both primary and secondary process,
 530  * TXQ UAR maps to this area using fixed mmap w/o double check.
 531  */
 532 static void *uar_base;
 533
 534 static int
 535 find_lower_va_bound(const struct rte_memseg_list *msl __rte_unused,
 536                 const struct rte_memseg *ms, void *arg)
 537 {
 538         void **addr = arg;
 539
 540         if (*addr == NULL)
 541                 *addr = ms->addr;
 542         else
 543                 *addr = RTE_MIN(*addr, ms->addr);
 544
 545         return 0;
 546 }
 547
 548 /**
 549  * Reserve UAR address space for primary process.
 550  *
 551  * @param[in] dev
 552  *   Pointer to Ethernet device.
 553  *
 554  * @return
 555  *   0 on success, a negative errno value otherwise and rte_errno is set.
 556  */
 557 static int
 558 mlx5_uar_init_primary(struct rte_eth_dev *dev)
 559 {
 560         struct priv *priv = dev->data->dev_private;
 561         void *addr = (void *)0;
 562
 563         if (uar_base) { /* UAR address space mapped. */
 564                 priv->uar_base = uar_base;
 565                 return 0;
 566         }
 567         /* find out lower bound of hugepage segments */
 568         rte_memseg_walk(find_lower_va_bound, &addr);
 569
 570         /* keep distance to hugepages to minimize potential conflicts. */
 571         addr = RTE_PTR_SUB(addr, MLX5_UAR_OFFSET + MLX5_UAR_SIZE);
 572         /* anonymous mmap, no real memory consumption. */
 573         addr = mmap(addr, MLX5_UAR_SIZE,
 574                     PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
 575         if (addr == MAP_FAILED) {
 576                 DRV_LOG(ERR,
 577                         "port %u failed to reserve UAR address space, please"
 578                         " adjust MLX5_UAR_SIZE or try --base-virtaddr",
 579                         dev->data->port_id);
 580                 rte_errno = ENOMEM;
 581                 return -rte_errno;
 582         }
 583         /* Accept either same addr or a new addr returned from mmap if target
 584          * range occupied.
 585          */
 586         DRV_LOG(INFO, "port %u reserved UAR address space: %p",
 587                 dev->data->port_id, addr);
 588         priv->uar_base = addr; /* for primary and secondary UAR re-mmap. */
 589         uar_base = addr; /* process local, don't reserve again. */
 590         return 0;
 591 }
 592
 593 /**
 594  * Reserve UAR address space for secondary process, align with
 595  * primary process.
 596  *
 597  * @param[in] dev
 598  *   Pointer to Ethernet device.
 599  *
 600  * @return
 601  *   0 on success, a negative errno value otherwise and rte_errno is set.
 602  */
 603 static int
 604 mlx5_uar_init_secondary(struct rte_eth_dev *dev)
 605 {
 606         struct priv *priv = dev->data->dev_private;
 607         void *addr;
 608
 609         assert(priv->uar_base);
 610         if (uar_base) { /* already reserved. */
 611                 assert(uar_base == priv->uar_base);
 612                 return 0;
 613         }
 614         /* anonymous mmap, no real memory consumption. */
 615         addr = mmap(priv->uar_base, MLX5_UAR_SIZE,
 616                     PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
 617         if (addr == MAP_FAILED) {
 618                 DRV_LOG(ERR, "port %u UAR mmap failed: %p size: %llu",
 619                         dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
 620                 rte_errno = ENXIO;
 621                 return -rte_errno;
 622         }
 623         if (priv->uar_base != addr) {
 624                 DRV_LOG(ERR,
 625                         "port %u UAR address %p size %llu occupied, please"
 626                         " adjust MLX5_UAR_OFFSET or try EAL parameter"
 627                         " --base-virtaddr",
 628                         dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
 629                 rte_errno = ENXIO;
 630                 return -rte_errno;
 631         }
 632         uar_base = addr; /* process local, don't reserve again */
 633         DRV_LOG(INFO, "port %u reserved UAR address space: %p",
 634                 dev->data->port_id, addr);
 635         return 0;
 636 }
 637
 638 /**
 639  * Spawn an Ethernet device from Verbs information.
 640  *
 641  * @param dpdk_dev
 642  *   Backing DPDK device.
 643  * @param ibv_dev
 644  *   Verbs device.
 645  * @param vf
 646  *   If nonzero, enable VF-specific features.
 647  *
 648  * @return
 649  *   A valid Ethernet device object on success, NULL otherwise and rte_errno
 650  *   is set.
 651  */
 652 static struct rte_eth_dev *
 653 mlx5_dev_spawn(struct rte_device *dpdk_dev,
 654                struct ibv_device *ibv_dev,
 655                int vf)
 656 {
 657         struct ibv_context *ctx;
 658         struct ibv_device_attr_ex attr;
 659         struct ibv_pd *pd = NULL;
 660         struct mlx5dv_context dv_attr = { .comp_mask = 0 };
 661         struct rte_eth_dev *eth_dev = NULL;
 662         struct priv *priv = NULL;
 663         int err = 0;
 664         unsigned int mps;
 665         unsigned int cqe_comp;
 666         unsigned int tunnel_en = 0;
 667         unsigned int mpls_en = 0;
 668         unsigned int swp = 0;
 669         unsigned int verb_priorities = 0;
 670         unsigned int mprq = 0;
 671         unsigned int mprq_min_stride_size_n = 0;
 672         unsigned int mprq_max_stride_size_n = 0;
 673         unsigned int mprq_min_stride_num_n = 0;
 674         unsigned int mprq_max_stride_num_n = 0;
 675 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
 676         struct ibv_counter_set_description cs_desc = { .counter_type = 0 };
 677 #endif
 678
 679         /* Prepare shared data between primary and secondary process. */
 680         mlx5_prepare_shared_data();
 681         errno = 0;
 682         ctx = mlx5_glue->open_device(ibv_dev);
 683         if (!ctx) {
 684                 rte_errno = errno ? errno : ENODEV;
 685                 return NULL;
 686         }
 687 #ifdef HAVE_IBV_MLX5_MOD_SWP
 688         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
 689 #endif
 690         /*
 691          * Multi-packet send is supported by ConnectX-4 Lx PF as well
 692          * as all ConnectX-5 devices.
 693          */
 694 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
 695         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
 696 #endif
 697 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
 698         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
 699 #endif
 700         mlx5_glue->dv_query_device(ctx, &dv_attr);
 701         if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
 702                 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
 703                         DRV_LOG(DEBUG, "enhanced MPW is supported");
 704                         mps = MLX5_MPW_ENHANCED;
 705                 } else {
 706                         DRV_LOG(DEBUG, "MPW is supported");
 707                         mps = MLX5_MPW;
 708                 }
 709         } else {
 710                 DRV_LOG(DEBUG, "MPW isn't supported");
 711                 mps = MLX5_MPW_DISABLED;
 712         }
 713 #ifdef HAVE_IBV_MLX5_MOD_SWP
 714         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
 715                 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
 716         DRV_LOG(DEBUG, "SWP support: %u", swp);
 717 #endif
 718 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
 719         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
 720                 struct mlx5dv_striding_rq_caps mprq_caps =
 721                         dv_attr.striding_rq_caps;
 722
 723                 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
 724                         mprq_caps.min_single_stride_log_num_of_bytes);
 725                 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
 726                         mprq_caps.max_single_stride_log_num_of_bytes);
 727                 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
 728                         mprq_caps.min_single_wqe_log_num_of_strides);
 729                 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
 730                         mprq_caps.max_single_wqe_log_num_of_strides);
 731                 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
 732                         mprq_caps.supported_qpts);
 733                 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
 734                 mprq = 1;
 735                 mprq_min_stride_size_n =
 736                         mprq_caps.min_single_stride_log_num_of_bytes;
 737                 mprq_max_stride_size_n =
 738                         mprq_caps.max_single_stride_log_num_of_bytes;
 739                 mprq_min_stride_num_n =
 740                         mprq_caps.min_single_wqe_log_num_of_strides;
 741                 mprq_max_stride_num_n =
 742                         mprq_caps.max_single_wqe_log_num_of_strides;
 743         }
 744 #endif
 745         if (RTE_CACHE_LINE_SIZE == 128 &&
 746             !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
 747                 cqe_comp = 0;
 748         else
 749                 cqe_comp = 1;
 750 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
 751         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
 752                 tunnel_en = ((dv_attr.tunnel_offloads_caps &
 753                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
 754                              (dv_attr.tunnel_offloads_caps &
 755                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE));
 756         }
 757         DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
 758                 tunnel_en ? "" : "not ");
 759 #else
 760         DRV_LOG(WARNING,
 761                 "tunnel offloading disabled due to old OFED/rdma-core version");
 762 #endif
 763 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
 764         mpls_en = ((dv_attr.tunnel_offloads_caps &
 765                     MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
 766                    (dv_attr.tunnel_offloads_caps &
 767                     MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
 768         DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
 769                 mpls_en ? "" : "not ");
 770 #else
 771         DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
 772                 " old OFED/rdma-core version or firmware configuration");
 773 #endif
 774         err = mlx5_glue->query_device_ex(ctx, NULL, &attr);
 775         if (err) {
 776                 DEBUG("ibv_query_device_ex() failed");
 777                 goto error;
 778         }
 779         {
 780                 char name[RTE_ETH_NAME_MAX_LEN];
 781                 struct ibv_port_attr port_attr;
 782                 struct ether_addr mac;
 783                 struct mlx5_dev_config config = {
 784                         .cqe_comp = cqe_comp,
 785                         .mps = mps,
 786                         .tunnel_en = tunnel_en,
 787                         .mpls_en = mpls_en,
 788                         .tx_vec_en = 1,
 789                         .rx_vec_en = 1,
 790                         .mpw_hdr_dseg = 0,
 791                         .txq_inline = MLX5_ARG_UNSET,
 792                         .txqs_inline = MLX5_ARG_UNSET,
 793                         .inline_max_packet_sz = MLX5_ARG_UNSET,
 794                         .vf_nl_en = 1,
 795                         .swp = !!swp,
 796                         .mprq = {
 797                                 .enabled = 0, /* Disabled by default. */
 798                                 .stride_num_n = RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
 799                                                         mprq_min_stride_num_n),
 800                                 .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
 801                                 .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
 802                         },
 803                 };
 804
 805                 rte_strlcpy(name, dpdk_dev->name, sizeof(name));
 806                 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
 807                         eth_dev = rte_eth_dev_attach_secondary(name);
 808                         if (eth_dev == NULL) {
 809                                 DRV_LOG(ERR, "can not attach rte ethdev");
 810                                 rte_errno = ENOMEM;
 811                                 err = rte_errno;
 812                                 goto error;
 813                         }
 814                         eth_dev->device = dpdk_dev;
 815                         eth_dev->dev_ops = &mlx5_dev_sec_ops;
 816                         err = mlx5_uar_init_secondary(eth_dev);
 817                         if (err) {
 818                                 err = rte_errno;
 819                                 goto error;
 820                         }
 821                         /* Receive command fd from primary process */
 822                         err = mlx5_socket_connect(eth_dev);
 823                         if (err < 0) {
 824                                 err = rte_errno;
 825                                 goto error;
 826                         }
 827                         /* Remap UAR for Tx queues. */
 828                         err = mlx5_tx_uar_remap(eth_dev, err);
 829                         if (err) {
 830                                 err = rte_errno;
 831                                 goto error;
 832                         }
 833                         /*
 834                          * Ethdev pointer is still required as input since
 835                          * the primary device is not accessible from the
 836                          * secondary process.
 837                          */
 838                         eth_dev->rx_pkt_burst =
 839                                 mlx5_select_rx_function(eth_dev);
 840                         eth_dev->tx_pkt_burst =
 841                                 mlx5_select_tx_function(eth_dev);
 842                         claim_zero(mlx5_glue->close_device(ctx));
 843                         return eth_dev;
 844                 }
 845                 /* Check port status. */
 846                 err = mlx5_glue->query_port(ctx, 1, &port_attr);
 847                 if (err) {
 848                         DRV_LOG(ERR, "port query failed: %s", strerror(err));
 849                         goto error;
 850                 }
 851                 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
 852                         DRV_LOG(ERR, "port is not configured in Ethernet mode");
 853                         err = EINVAL;
 854                         goto error;
 855                 }
 856                 if (port_attr.state != IBV_PORT_ACTIVE)
 857                         DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)",
 858                                 mlx5_glue->port_state_str(port_attr.state),
 859                                 port_attr.state);
 860                 /* Allocate protection domain. */
 861                 pd = mlx5_glue->alloc_pd(ctx);
 862                 if (pd == NULL) {
 863                         DRV_LOG(ERR, "PD allocation failure");
 864                         err = ENOMEM;
 865                         goto error;
 866                 }
 867                 /* from rte_ethdev.c */
 868                 priv = rte_zmalloc("ethdev private structure",
 869                                    sizeof(*priv),
 870                                    RTE_CACHE_LINE_SIZE);
 871                 if (priv == NULL) {
 872                         DRV_LOG(ERR, "priv allocation failure");
 873                         err = ENOMEM;
 874                         goto error;
 875                 }
 876                 priv->ctx = ctx;
 877                 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path,
 878                         sizeof(priv->ibdev_path));
 879                 priv->device_attr = attr;
 880                 priv->pd = pd;
 881                 priv->mtu = ETHER_MTU;
 882                 err = mlx5_args(&config, dpdk_dev->devargs);
 883                 if (err) {
 884                         err = rte_errno;
 885                         DRV_LOG(ERR, "failed to process device arguments: %s",
 886                                 strerror(rte_errno));
 887                         goto error;
 888                 }
 889                 config.hw_csum = !!(attr.device_cap_flags_ex &
 890                                     IBV_DEVICE_RAW_IP_CSUM);
 891                 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
 892                         (config.hw_csum ? "" : "not "));
 893 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
 894                 config.flow_counter_en = !!attr.max_counter_sets;
 895                 mlx5_glue->describe_counter_set(ctx, 0, &cs_desc);
 896                 DRV_LOG(DEBUG,
 897                         "counter type = %d, num of cs = %ld, attributes = %d",
 898                         cs_desc.counter_type, cs_desc.num_of_cs,
 899                         cs_desc.attributes);
 900 #endif
 901                 config.ind_table_max_size =
 902                         attr.rss_caps.max_rwq_indirection_table_size;
 903                 /* Remove this check once DPDK supports larger/variable
 904                  * indirection tables. */
 905                 if (config.ind_table_max_size >
 906                                 (unsigned int)ETH_RSS_RETA_SIZE_512)
 907                         config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
 908                 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
 909                         config.ind_table_max_size);
 910                 config.hw_vlan_strip = !!(attr.raw_packet_caps &
 911                                          IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
 912                 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
 913                         (config.hw_vlan_strip ? "" : "not "));
 914
 915                 config.hw_fcs_strip = !!(attr.raw_packet_caps &
 916                                          IBV_RAW_PACKET_CAP_SCATTER_FCS);
 917                 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
 918                         (config.hw_fcs_strip ? "" : "not "));
 919
 920 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
 921                 config.hw_padding = !!attr.rx_pad_end_addr_align;
 922 #endif
 923                 DRV_LOG(DEBUG,
 924                         "hardware Rx end alignment padding is %ssupported",
 925                         (config.hw_padding ? "" : "not "));
 926                 config.vf = vf;
 927                 config.tso = (attr.tso_caps.max_tso > 0 &&
 928                               (attr.tso_caps.supported_qpts &
 929                                (1 << IBV_QPT_RAW_PACKET)));
 930                 if (config.tso)
 931                         config.tso_max_payload_sz = attr.tso_caps.max_tso;
 932                 if (config.mps && !mps) {
 933                         DRV_LOG(ERR,
 934                                 "multi-packet send not supported on this device"
 935                                 " (" MLX5_TXQ_MPW_EN ")");
 936                         err = ENOTSUP;
 937                         goto error;
 938                 }
 939                 DRV_LOG(INFO, "%s MPS is %s",
 940                         config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "",
 941                         config.mps != MLX5_MPW_DISABLED ? "enabled" :
 942                         "disabled");
 943                 if (config.cqe_comp && !cqe_comp) {
 944                         DRV_LOG(WARNING, "Rx CQE compression isn't supported");
 945                         config.cqe_comp = 0;
 946                 }
 947                 if (config.mprq.enabled && mprq) {
 948                         if (config.mprq.stride_num_n > mprq_max_stride_num_n ||
 949                             config.mprq.stride_num_n < mprq_min_stride_num_n) {
 950                                 config.mprq.stride_num_n =
 951                                         RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
 952                                                 mprq_min_stride_num_n);
 953                                 DRV_LOG(WARNING,
 954                                         "the number of strides"
 955                                         " for Multi-Packet RQ is out of range,"
 956                                         " setting default value (%u)",
 957                                         1 << config.mprq.stride_num_n);
 958                         }
 959                         config.mprq.min_stride_size_n = mprq_min_stride_size_n;
 960                         config.mprq.max_stride_size_n = mprq_max_stride_size_n;
 961                 } else if (config.mprq.enabled && !mprq) {
 962                         DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
 963                         config.mprq.enabled = 0;
 964                 }
 965                 eth_dev = rte_eth_dev_allocate(name);
 966                 if (eth_dev == NULL) {
 967                         DRV_LOG(ERR, "can not allocate rte ethdev");
 968                         err = ENOMEM;
 969                         goto error;
 970                 }
 971                 eth_dev->data->dev_private = priv;
 972                 priv->dev_data = eth_dev->data;
 973                 eth_dev->data->mac_addrs = priv->mac;
 974                 eth_dev->device = dpdk_dev;
 975                 eth_dev->device->driver = &mlx5_driver.driver;
 976                 err = mlx5_uar_init_primary(eth_dev);
 977                 if (err) {
 978                         err = rte_errno;
 979                         goto error;
 980                 }
 981                 /* Configure the first MAC address by default. */
 982                 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
 983                         DRV_LOG(ERR,
 984                                 "port %u cannot get MAC address, is mlx5_en"
 985                                 " loaded? (errno: %s)",
 986                                 eth_dev->data->port_id, strerror(rte_errno));
 987                         err = ENODEV;
 988                         goto error;
 989                 }
 990                 DRV_LOG(INFO,
 991                         "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
 992                         eth_dev->data->port_id,
 993                         mac.addr_bytes[0], mac.addr_bytes[1],
 994                         mac.addr_bytes[2], mac.addr_bytes[3],
 995                         mac.addr_bytes[4], mac.addr_bytes[5]);
 996 #ifndef NDEBUG
 997                 {
 998                         char ifname[IF_NAMESIZE];
 999
1000                         if (mlx5_get_ifname(eth_dev, &ifname) == 0)
1001                                 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
1002                                         eth_dev->data->port_id, ifname);
1003                         else
1004                                 DRV_LOG(DEBUG, "port %u ifname is unknown",
1005                                         eth_dev->data->port_id);
1006                 }
1007 #endif
1008                 /* Get actual MTU if possible. */
1009                 err = mlx5_get_mtu(eth_dev, &priv->mtu);
1010                 if (err) {
1011                         err = rte_errno;
1012                         goto error;
1013                 }
1014                 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
1015                         priv->mtu);
1016                 /*
1017                  * Initialize burst functions to prevent crashes before link-up.
1018                  */
1019                 eth_dev->rx_pkt_burst = removed_rx_burst;
1020                 eth_dev->tx_pkt_burst = removed_tx_burst;
1021                 eth_dev->dev_ops = &mlx5_dev_ops;
1022                 /* Register MAC address. */
1023                 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
1024                 priv->nl_socket = -1;
1025                 priv->nl_sn = 0;
1026                 if (vf && config.vf_nl_en) {
1027                         priv->nl_socket = mlx5_nl_init(RTMGRP_LINK);
1028                         if (priv->nl_socket < 0)
1029                                 priv->nl_socket = -1;
1030                         mlx5_nl_mac_addr_sync(eth_dev);
1031                 }
1032                 TAILQ_INIT(&priv->flows);
1033                 TAILQ_INIT(&priv->ctrl_flows);
1034                 /* Hint libmlx5 to use PMD allocator for data plane resources */
1035                 struct mlx5dv_ctx_allocators alctr = {
1036                         .alloc = &mlx5_alloc_verbs_buf,
1037                         .free = &mlx5_free_verbs_buf,
1038                         .data = priv,
1039                 };
1040                 mlx5_glue->dv_set_context_attr(ctx,
1041                                                MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
1042                                                (void *)((uintptr_t)&alctr));
1043                 /* Bring Ethernet device up. */
1044                 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
1045                         eth_dev->data->port_id);
1046                 mlx5_set_link_up(eth_dev);
1047                 /*
1048                  * Even though the interrupt handler is not installed yet,
1049                  * interrupts will still trigger on the asyn_fd from
1050                  * Verbs context returned by ibv_open_device().
1051                  */
1052                 mlx5_link_update(eth_dev, 0);
1053                 /* Store device configuration on private structure. */
1054                 priv->config = config;
1055                 /* Create drop queue. */
1056                 err = mlx5_flow_create_drop_queue(eth_dev);
1057                 if (err) {
1058                         DRV_LOG(ERR, "port %u drop queue allocation failed: %s",
1059                                 eth_dev->data->port_id, strerror(rte_errno));
1060                         err = rte_errno;
1061                         goto error;
1062                 }
1063                 /* Supported Verbs flow priority number detection. */
1064                 if (verb_priorities == 0)
1065                         verb_priorities = mlx5_get_max_verbs_prio(eth_dev);
1066                 if (verb_priorities < MLX5_VERBS_FLOW_PRIO_8) {
1067                         DRV_LOG(ERR, "port %u wrong Verbs flow priorities: %u",
1068                                 eth_dev->data->port_id, verb_priorities);
1069                         err = ENOTSUP;
1070                         goto error;
1071                 }
1072                 priv->config.max_verbs_prio = verb_priorities;
1073                 /*
1074                  * Once the device is added to the list of memory event
1075                  * callback, its global MR cache table cannot be expanded
1076                  * on the fly because of deadlock. If it overflows, lookup
1077                  * should be done by searching MR list linearly, which is slow.
1078                  */
1079                 err = mlx5_mr_btree_init(&priv->mr.cache,
1080                                          MLX5_MR_BTREE_CACHE_N * 2,
1081                                          eth_dev->device->numa_node);
1082                 if (err) {
1083                         err = rte_errno;
1084                         goto error;
1085                 }
1086                 /* Add device to memory callback list. */
1087                 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1088                 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1089                                  priv, mem_event_cb);
1090                 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1091                 rte_eth_dev_probing_finish(eth_dev);
1092                 return eth_dev;
1093         }
1094 error:
1095         if (priv)
1096                 rte_free(priv);
1097         if (pd)
1098                 claim_zero(mlx5_glue->dealloc_pd(pd));
1099         if (eth_dev)
1100                 rte_eth_dev_release_port(eth_dev);
1101         if (ctx)
1102                 claim_zero(mlx5_glue->close_device(ctx));
1103         assert(err > 0);
1104         rte_errno = err;
1105         return NULL;
1106 }
1107
1108 /**
1109  * DPDK callback to register a PCI device.
1110  *
1111  * This function spawns an Ethernet device out of a given PCI device.
1112  *
1113  * @param[in] pci_drv
1114  *   PCI driver structure (mlx5_driver).
1115  * @param[in] pci_dev
1116  *   PCI device information.
1117  *
1118  * @return
1119  *   0 on success, a negative errno value otherwise and rte_errno is set.
1120  */
1121 static int
1122 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1123                struct rte_pci_device *pci_dev)
1124 {
1125         struct ibv_device **ibv_list;
1126         struct rte_eth_dev *eth_dev = NULL;
1127         int vf;
1128         int ret;
1129
1130         assert(pci_drv == &mlx5_driver);
1131         errno = 0;
1132         ibv_list = mlx5_glue->get_device_list(&ret);
1133         if (!ibv_list) {
1134                 rte_errno = errno ? errno : ENOSYS;
1135                 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?");
1136                 return -rte_errno;
1137         }
1138         while (ret-- > 0) {
1139                 struct rte_pci_addr pci_addr;
1140
1141                 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name);
1142                 if (mlx5_ibv_device_to_pci_addr(ibv_list[ret], &pci_addr))
1143                         continue;
1144                 if (pci_dev->addr.domain != pci_addr.domain ||
1145                     pci_dev->addr.bus != pci_addr.bus ||
1146                     pci_dev->addr.devid != pci_addr.devid ||
1147                     pci_dev->addr.function != pci_addr.function)
1148                         continue;
1149                 DRV_LOG(INFO, "PCI information matches, using device \"%s\"",
1150                         ibv_list[ret]->name);
1151                 break;
1152         }
1153         switch (pci_dev->id.device_id) {
1154         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1155         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1156         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1157         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1158                 vf = 1;
1159                 break;
1160         default:
1161                 vf = 0;
1162         }
1163         if (ret >= 0)
1164                 eth_dev = mlx5_dev_spawn(&pci_dev->device, ibv_list[ret], vf);
1165         mlx5_glue->free_device_list(ibv_list);
1166         if (!ret) {
1167                 DRV_LOG(WARNING,
1168                         "no Verbs device matches PCI device " PCI_PRI_FMT ","
1169                         " are kernel drivers loaded?",
1170                         pci_dev->addr.domain, pci_dev->addr.bus,
1171                         pci_dev->addr.devid, pci_dev->addr.function);
1172                 rte_errno = ENOENT;
1173                 ret = -rte_errno;
1174         } else if (!eth_dev) {
1175                 DRV_LOG(ERR,
1176                         "probe of PCI device " PCI_PRI_FMT " aborted after"
1177                         " encountering an error: %s",
1178                         pci_dev->addr.domain, pci_dev->addr.bus,
1179                         pci_dev->addr.devid, pci_dev->addr.function,
1180                         strerror(rte_errno));
1181                 ret = -rte_errno;
1182         } else {
1183                 rte_eth_copy_pci_info(eth_dev, pci_dev);
1184                 rte_eth_dev_probing_finish(eth_dev);
1185                 ret = 0;
1186         }
1187         return ret;
1188 }
1189
1190 static const struct rte_pci_id mlx5_pci_id_map[] = {
1191         {
1192                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1193                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1194         },
1195         {
1196                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1197                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1198         },
1199         {
1200                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1201                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1202         },
1203         {
1204                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1205                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1206         },
1207         {
1208                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1209                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1210         },
1211         {
1212                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1213                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1214         },
1215         {
1216                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1217                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1218         },
1219         {
1220                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1221                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1222         },
1223         {
1224                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1225                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
1226         },
1227         {
1228                 .vendor_id = 0
1229         }
1230 };
1231
1232 static struct rte_pci_driver mlx5_driver = {
1233         .driver = {
1234                 .name = MLX5_DRIVER_NAME
1235         },
1236         .id_table = mlx5_pci_id_map,
1237         .probe = mlx5_pci_probe,
1238         .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV,
1239 };
1240
1241 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1242
1243 /**
1244  * Suffix RTE_EAL_PMD_PATH with "-glue".
1245  *
1246  * This function performs a sanity check on RTE_EAL_PMD_PATH before
1247  * suffixing its last component.
1248  *
1249  * @param buf[out]
1250  *   Output buffer, should be large enough otherwise NULL is returned.
1251  * @param size
1252  *   Size of @p out.
1253  *
1254  * @return
1255  *   Pointer to @p buf or @p NULL in case suffix cannot be appended.
1256  */
1257 static char *
1258 mlx5_glue_path(char *buf, size_t size)
1259 {
1260         static const char *const bad[] = { "/", ".", "..", NULL };
1261         const char *path = RTE_EAL_PMD_PATH;
1262         size_t len = strlen(path);
1263         size_t off;
1264         int i;
1265
1266         while (len && path[len - 1] == '/')
1267                 --len;
1268         for (off = len; off && path[off - 1] != '/'; --off)
1269                 ;
1270         for (i = 0; bad[i]; ++i)
1271                 if (!strncmp(path + off, bad[i], (int)(len - off)))
1272                         goto error;
1273         i = snprintf(buf, size, "%.*s-glue", (int)len, path);
1274         if (i == -1 || (size_t)i >= size)
1275                 goto error;
1276         return buf;
1277 error:
1278         DRV_LOG(ERR,
1279                 "unable to append \"-glue\" to last component of"
1280                 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\"),"
1281                 " please re-configure DPDK");
1282         return NULL;
1283 }
1284
1285 /**
1286  * Initialization routine for run-time dependency on rdma-core.
1287  */
1288 static int
1289 mlx5_glue_init(void)
1290 {
1291         char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")];
1292         const char *path[] = {
1293                 /*
1294                  * A basic security check is necessary before trusting
1295                  * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH.
1296                  */
1297                 (geteuid() == getuid() && getegid() == getgid() ?
1298                  getenv("MLX5_GLUE_PATH") : NULL),
1299                 /*
1300                  * When RTE_EAL_PMD_PATH is set, use its glue-suffixed
1301                  * variant, otherwise let dlopen() look up libraries on its
1302                  * own.
1303                  */
1304                 (*RTE_EAL_PMD_PATH ?
1305                  mlx5_glue_path(glue_path, sizeof(glue_path)) : ""),
1306         };
1307         unsigned int i = 0;
1308         void *handle = NULL;
1309         void **sym;
1310         const char *dlmsg;
1311
1312         while (!handle && i != RTE_DIM(path)) {
1313                 const char *end;
1314                 size_t len;
1315                 int ret;
1316
1317                 if (!path[i]) {
1318                         ++i;
1319                         continue;
1320                 }
1321                 end = strpbrk(path[i], ":;");
1322                 if (!end)
1323                         end = path[i] + strlen(path[i]);
1324                 len = end - path[i];
1325                 ret = 0;
1326                 do {
1327                         char name[ret + 1];
1328
1329                         ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE,
1330                                        (int)len, path[i],
1331                                        (!len || *(end - 1) == '/') ? "" : "/");
1332                         if (ret == -1)
1333                                 break;
1334                         if (sizeof(name) != (size_t)ret + 1)
1335                                 continue;
1336                         DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"",
1337                                 name);
1338                         handle = dlopen(name, RTLD_LAZY);
1339                         break;
1340                 } while (1);
1341                 path[i] = end + 1;
1342                 if (!*end)
1343                         ++i;
1344         }
1345         if (!handle) {
1346                 rte_errno = EINVAL;
1347                 dlmsg = dlerror();
1348                 if (dlmsg)
1349                         DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg);
1350                 goto glue_error;
1351         }
1352         sym = dlsym(handle, "mlx5_glue");
1353         if (!sym || !*sym) {
1354                 rte_errno = EINVAL;
1355                 dlmsg = dlerror();
1356                 if (dlmsg)
1357                         DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg);
1358                 goto glue_error;
1359         }
1360         mlx5_glue = *sym;
1361         return 0;
1362 glue_error:
1363         if (handle)
1364                 dlclose(handle);
1365         DRV_LOG(WARNING,
1366                 "cannot initialize PMD due to missing run-time dependency on"
1367                 " rdma-core libraries (libibverbs, libmlx5)");
1368         return -rte_errno;
1369 }
1370
1371 #endif
1372
1373 /**
1374  * Driver initialization routine.
1375  */
1376 RTE_INIT(rte_mlx5_pmd_init)
1377 {
1378         /* Initialize driver log type. */
1379         mlx5_logtype = rte_log_register("pmd.net.mlx5");
1380         if (mlx5_logtype >= 0)
1381                 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
1382
1383         /* Build the static tables for Verbs conversion. */
1384         mlx5_set_ptype_table();
1385         mlx5_set_cksum_table();
1386         mlx5_set_swp_types_table();
1387         /*
1388          * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
1389          * huge pages. Calling ibv_fork_init() during init allows
1390          * applications to use fork() safely for purposes other than
1391          * using this PMD, which is not supported in forked processes.
1392          */
1393         setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
1394         /* Match the size of Rx completion entry to the size of a cacheline. */
1395         if (RTE_CACHE_LINE_SIZE == 128)
1396                 setenv("MLX5_CQE_SIZE", "128", 0);
1397         /*
1398          * MLX5_DEVICE_FATAL_CLEANUP tells ibv_destroy functions to
1399          * cleanup all the Verbs resources even when the device was removed.
1400          */
1401         setenv("MLX5_DEVICE_FATAL_CLEANUP", "1", 1);
1402 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1403         if (mlx5_glue_init())
1404                 return;
1405         assert(mlx5_glue);
1406 #endif
1407 #ifndef NDEBUG
1408         /* Glue structure must not contain any NULL pointers. */
1409         {
1410                 unsigned int i;
1411
1412                 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i)
1413                         assert(((const void *const *)mlx5_glue)[i]);
1414         }
1415 #endif
1416         if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) {
1417                 DRV_LOG(ERR,
1418                         "rdma-core glue \"%s\" mismatch: \"%s\" is required",
1419                         mlx5_glue->version, MLX5_GLUE_VERSION);
1420                 return;
1421         }
1422         mlx5_glue->fork_init();
1423         rte_pci_register(&mlx5_driver);
1424 }
1425
1426 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1427 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1428 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");