drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12 #include <net/if.h>
  13 #include <sys/mman.h>
  14 #include <linux/rtnetlink.h>
  15
  16 /* Verbs header. */
  17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  18 #ifdef PEDANTIC
  19 #pragma GCC diagnostic ignored "-Wpedantic"
  20 #endif
  21 #include <infiniband/verbs.h>
  22 #ifdef PEDANTIC
  23 #pragma GCC diagnostic error "-Wpedantic"
  24 #endif
  25
  26 #include <rte_malloc.h>
  27 #include <rte_ethdev_driver.h>
  28 #include <rte_ethdev_pci.h>
  29 #include <rte_pci.h>
  30 #include <rte_bus_pci.h>
  31 #include <rte_common.h>
  32 #include <rte_kvargs.h>
  33 #include <rte_rwlock.h>
  34 #include <rte_spinlock.h>
  35 #include <rte_string_fns.h>
  36 #include <rte_alarm.h>
  37
  38 #include <mlx5_glue.h>
  39 #include <mlx5_devx_cmds.h>
  40 #include <mlx5_common.h>
  41 #include <mlx5_common_mp.h>
  42
  43 #include "mlx5_defs.h"
  44 #include "mlx5.h"
  45 #include "mlx5_utils.h"
  46 #include "mlx5_rxtx.h"
  47 #include "mlx5_autoconf.h"
  48 #include "mlx5_mr.h"
  49 #include "mlx5_flow.h"
  50 #include "rte_pmd_mlx5.h"
  51
  52 /* Device parameter to enable RX completion queue compression. */
  53 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  54
  55 /* Device parameter to enable RX completion entry padding to 128B. */
  56 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
  57
  58 /* Device parameter to enable padding Rx packet to cacheline size. */
  59 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  60
  61 /* Device parameter to enable Multi-Packet Rx queue. */
  62 #define MLX5_RX_MPRQ_EN "mprq_en"
  63
  64 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  65 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  66
  67 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  68 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  69
  70 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  71 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  72
  73 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  74 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  75
  76 /* Device parameter to configure inline send. Deprecated, ignored.*/
  77 #define MLX5_TXQ_INLINE "txq_inline"
  78
  79 /* Device parameter to limit packet size to inline with ordinary SEND. */
  80 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  81
  82 /* Device parameter to configure minimal data size to inline. */
  83 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  84
  85 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  86 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  87
  88 /*
  89  * Device parameter to configure the number of TX queues threshold for
  90  * enabling inline send.
  91  */
  92 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  93
  94 /*
  95  * Device parameter to configure the number of TX queues threshold for
  96  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  97  */
  98 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  99
 100 /* Device parameter to enable multi-packet send WQEs. */
 101 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
 102
 103 /*
 104  * Device parameter to force doorbell register mapping
 105  * to non-cahed region eliminating the extra write memory barrier.
 106  */
 107 #define MLX5_TX_DB_NC "tx_db_nc"
 108
 109 /*
 110  * Device parameter to include 2 dsegs in the title WQEBB.
 111  * Deprecated, ignored.
 112  */
 113 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 114
 115 /*
 116  * Device parameter to limit the size of inlining packet.
 117  * Deprecated, ignored.
 118  */
 119 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 120
 121 /*
 122  * Device parameter to enable hardware Tx vector.
 123  * Deprecated, ignored (no vectorized Tx routines anymore).
 124  */
 125 #define MLX5_TX_VEC_EN "tx_vec_en"
 126
 127 /* Device parameter to enable hardware Rx vector. */
 128 #define MLX5_RX_VEC_EN "rx_vec_en"
 129
 130 /* Allow L3 VXLAN flow creation. */
 131 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 132
 133 /* Activate DV E-Switch flow steering. */
 134 #define MLX5_DV_ESW_EN "dv_esw_en"
 135
 136 /* Activate DV flow steering. */
 137 #define MLX5_DV_FLOW_EN "dv_flow_en"
 138
 139 /* Enable extensive flow metadata support. */
 140 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 141
 142 /* Activate Netlink support in VF mode. */
 143 #define MLX5_VF_NL_EN "vf_nl_en"
 144
 145 /* Enable extending memsegs when creating a MR. */
 146 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 147
 148 /* Select port representors to instantiate. */
 149 #define MLX5_REPRESENTOR "representor"
 150
 151 /* Device parameter to configure the maximum number of dump files per queue. */
 152 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 153
 154 /* Configure timeout of LRO session (in microseconds). */
 155 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 156
 157 /*
 158  * Device parameter to configure the total data buffer size for a single
 159  * hairpin queue (logarithm value).
 160  */
 161 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 162
 163 #ifndef HAVE_IBV_MLX5_MOD_MPW
 164 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
 165 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
 166 #endif
 167
 168 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
 169 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
 170 #endif
 171
 172 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
 173
 174 /* Shared memory between primary and secondary processes. */
 175 struct mlx5_shared_data *mlx5_shared_data;
 176
 177 /* Spinlock for mlx5_shared_data allocation. */
 178 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
 179
 180 /* Process local data for secondary processes. */
 181 static struct mlx5_local_data mlx5_local_data;
 182
 183 /** Driver-specific log messages type. */
 184 int mlx5_logtype;
 185
 186 /** Data associated with devices to spawn. */
 187 struct mlx5_dev_spawn_data {
 188         uint32_t ifindex; /**< Network interface index. */
 189         uint32_t max_port; /**< IB device maximal port index. */
 190         uint32_t ibv_port; /**< IB device physical port index. */
 191         int pf_bond; /**< bonding device PF index. < 0 - no bonding */
 192         struct mlx5_switch_info info; /**< Switch information. */
 193         struct ibv_device *ibv_dev; /**< Associated IB device. */
 194         struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
 195         struct rte_pci_device *pci_dev; /**< Backend PCI device. */
 196 };
 197
 198 static LIST_HEAD(, mlx5_ibv_shared) mlx5_ibv_list = LIST_HEAD_INITIALIZER();
 199 static pthread_mutex_t mlx5_ibv_list_mutex = PTHREAD_MUTEX_INITIALIZER;
 200
 201 static struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 202         {
 203                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 204                 .trunk_size = 64,
 205                 .grow_trunk = 3,
 206                 .grow_shift = 2,
 207                 .need_lock = 0,
 208                 .release_mem_en = 1,
 209                 .malloc = rte_malloc_socket,
 210                 .free = rte_free,
 211                 .type = "mlx5_encap_decap_ipool",
 212         },
 213         {
 214                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 215                 .trunk_size = 64,
 216                 .grow_trunk = 3,
 217                 .grow_shift = 2,
 218                 .need_lock = 0,
 219                 .release_mem_en = 1,
 220                 .malloc = rte_malloc_socket,
 221                 .free = rte_free,
 222                 .type = "mlx5_push_vlan_ipool",
 223         },
 224         {
 225                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 226                 .trunk_size = 64,
 227                 .grow_trunk = 3,
 228                 .grow_shift = 2,
 229                 .need_lock = 0,
 230                 .release_mem_en = 1,
 231                 .malloc = rte_malloc_socket,
 232                 .free = rte_free,
 233                 .type = "mlx5_tag_ipool",
 234         },
 235         {
 236                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 237                 .trunk_size = 64,
 238                 .grow_trunk = 3,
 239                 .grow_shift = 2,
 240                 .need_lock = 0,
 241                 .release_mem_en = 1,
 242                 .malloc = rte_malloc_socket,
 243                 .free = rte_free,
 244                 .type = "mlx5_port_id_ipool",
 245         },
 246 };
 247
 248
 249 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 250 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 251
 252 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 253 #define MLX5_TAGS_HLIST_ARRAY_SIZE 8192
 254
 255 /**
 256  * Allocate ID pool structure.
 257  *
 258  * @param[in] max_id
 259  *   The maximum id can be allocated from the pool.
 260  *
 261  * @return
 262  *   Pointer to pool object, NULL value otherwise.
 263  */
 264 struct mlx5_flow_id_pool *
 265 mlx5_flow_id_pool_alloc(uint32_t max_id)
 266 {
 267         struct mlx5_flow_id_pool *pool;
 268         void *mem;
 269
 270         pool = rte_zmalloc("id pool allocation", sizeof(*pool),
 271                            RTE_CACHE_LINE_SIZE);
 272         if (!pool) {
 273                 DRV_LOG(ERR, "can't allocate id pool");
 274                 rte_errno  = ENOMEM;
 275                 return NULL;
 276         }
 277         mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
 278                           RTE_CACHE_LINE_SIZE);
 279         if (!mem) {
 280                 DRV_LOG(ERR, "can't allocate mem for id pool");
 281                 rte_errno  = ENOMEM;
 282                 goto error;
 283         }
 284         pool->free_arr = mem;
 285         pool->curr = pool->free_arr;
 286         pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
 287         pool->base_index = 0;
 288         pool->max_id = max_id;
 289         return pool;
 290 error:
 291         rte_free(pool);
 292         return NULL;
 293 }
 294
 295 /**
 296  * Release ID pool structure.
 297  *
 298  * @param[in] pool
 299  *   Pointer to flow id pool object to free.
 300  */
 301 void
 302 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
 303 {
 304         rte_free(pool->free_arr);
 305         rte_free(pool);
 306 }
 307
 308 /**
 309  * Generate ID.
 310  *
 311  * @param[in] pool
 312  *   Pointer to flow id pool.
 313  * @param[out] id
 314  *   The generated ID.
 315  *
 316  * @return
 317  *   0 on success, error value otherwise.
 318  */
 319 uint32_t
 320 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
 321 {
 322         if (pool->curr == pool->free_arr) {
 323                 if (pool->base_index == pool->max_id) {
 324                         rte_errno  = ENOMEM;
 325                         DRV_LOG(ERR, "no free id");
 326                         return -rte_errno;
 327                 }
 328                 *id = ++pool->base_index;
 329                 return 0;
 330         }
 331         *id = *(--pool->curr);
 332         return 0;
 333 }
 334
 335 /**
 336  * Release ID.
 337  *
 338  * @param[in] pool
 339  *   Pointer to flow id pool.
 340  * @param[out] id
 341  *   The generated ID.
 342  *
 343  * @return
 344  *   0 on success, error value otherwise.
 345  */
 346 uint32_t
 347 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
 348 {
 349         uint32_t size;
 350         uint32_t size2;
 351         void *mem;
 352
 353         if (pool->curr == pool->last) {
 354                 size = pool->curr - pool->free_arr;
 355                 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
 356                 MLX5_ASSERT(size2 > size);
 357                 mem = rte_malloc("", size2 * sizeof(uint32_t), 0);
 358                 if (!mem) {
 359                         DRV_LOG(ERR, "can't allocate mem for id pool");
 360                         rte_errno  = ENOMEM;
 361                         return -rte_errno;
 362                 }
 363                 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
 364                 rte_free(pool->free_arr);
 365                 pool->free_arr = mem;
 366                 pool->curr = pool->free_arr + size;
 367                 pool->last = pool->free_arr + size2;
 368         }
 369         *pool->curr = id;
 370         pool->curr++;
 371         return 0;
 372 }
 373
 374 /**
 375  * Initialize the counters management structure.
 376  *
 377  * @param[in] sh
 378  *   Pointer to mlx5_ibv_shared object to free
 379  */
 380 static void
 381 mlx5_flow_counters_mng_init(struct mlx5_ibv_shared *sh)
 382 {
 383         uint8_t i;
 384
 385         TAILQ_INIT(&sh->cmng.flow_counters);
 386         for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i)
 387                 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
 388 }
 389
 390 /**
 391  * Destroy all the resources allocated for a counter memory management.
 392  *
 393  * @param[in] mng
 394  *   Pointer to the memory management structure.
 395  */
 396 static void
 397 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 398 {
 399         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 400
 401         LIST_REMOVE(mng, next);
 402         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 403         claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
 404         rte_free(mem);
 405 }
 406
 407 /**
 408  * Close and release all the resources of the counters management.
 409  *
 410  * @param[in] sh
 411  *   Pointer to mlx5_ibv_shared object to free.
 412  */
 413 static void
 414 mlx5_flow_counters_mng_close(struct mlx5_ibv_shared *sh)
 415 {
 416         struct mlx5_counter_stats_mem_mng *mng;
 417         uint8_t i;
 418         int j;
 419         int retries = 1024;
 420
 421         rte_errno = 0;
 422         while (--retries) {
 423                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 424                 if (rte_errno != EINPROGRESS)
 425                         break;
 426                 rte_pause();
 427         }
 428         for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i) {
 429                 struct mlx5_flow_counter_pool *pool;
 430                 uint32_t batch = !!(i % 2);
 431
 432                 if (!sh->cmng.ccont[i].pools)
 433                         continue;
 434                 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 435                 while (pool) {
 436                         if (batch) {
 437                                 if (pool->min_dcs)
 438                                         claim_zero
 439                                         (mlx5_devx_cmd_destroy(pool->min_dcs));
 440                         }
 441                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 442                                 if (pool->counters_raw[j].action)
 443                                         claim_zero
 444                                         (mlx5_glue->destroy_flow_action
 445                                                (pool->counters_raw[j].action));
 446                                 if (!batch && MLX5_GET_POOL_CNT_EXT
 447                                     (pool, j)->dcs)
 448                                         claim_zero(mlx5_devx_cmd_destroy
 449                                                   (MLX5_GET_POOL_CNT_EXT
 450                                                   (pool, j)->dcs));
 451                         }
 452                         TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool,
 453                                      next);
 454                         rte_free(pool);
 455                         pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 456                 }
 457                 rte_free(sh->cmng.ccont[i].pools);
 458         }
 459         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 460         while (mng) {
 461                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 462                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 463         }
 464         memset(&sh->cmng, 0, sizeof(sh->cmng));
 465 }
 466
 467 /**
 468  * Initialize the flow resources' indexed mempool.
 469  *
 470  * @param[in] sh
 471  *   Pointer to mlx5_ibv_shared object.
 472  */
 473 static void
 474 mlx5_flow_ipool_create(struct mlx5_ibv_shared *sh)
 475 {
 476         uint8_t i;
 477
 478         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 479                 sh->ipool[i] = mlx5_ipool_create(&mlx5_ipool_cfg[i]);
 480 }
 481
 482 /**
 483  * Release the flow resources' indexed mempool.
 484  *
 485  * @param[in] sh
 486  *   Pointer to mlx5_ibv_shared object.
 487  */
 488 static void
 489 mlx5_flow_ipool_destroy(struct mlx5_ibv_shared *sh)
 490 {
 491         uint8_t i;
 492
 493         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 494                 mlx5_ipool_destroy(sh->ipool[i]);
 495 }
 496
 497 /**
 498  * Extract pdn of PD object using DV API.
 499  *
 500  * @param[in] pd
 501  *   Pointer to the verbs PD object.
 502  * @param[out] pdn
 503  *   Pointer to the PD object number variable.
 504  *
 505  * @return
 506  *   0 on success, error value otherwise.
 507  */
 508 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 509 static int
 510 mlx5_get_pdn(struct ibv_pd *pd __rte_unused, uint32_t *pdn __rte_unused)
 511 {
 512         struct mlx5dv_obj obj;
 513         struct mlx5dv_pd pd_info;
 514         int ret = 0;
 515
 516         obj.pd.in = pd;
 517         obj.pd.out = &pd_info;
 518         ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);
 519         if (ret) {
 520                 DRV_LOG(DEBUG, "Fail to get PD object info");
 521                 return ret;
 522         }
 523         *pdn = pd_info.pdn;
 524         return 0;
 525 }
 526 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
 527
 528 static int
 529 mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config)
 530 {
 531         char *env;
 532         int value;
 533
 534         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 535         /* Get environment variable to store. */
 536         env = getenv(MLX5_SHUT_UP_BF);
 537         value = env ? !!strcmp(env, "0") : MLX5_ARG_UNSET;
 538         if (config->dbnc == MLX5_ARG_UNSET)
 539                 setenv(MLX5_SHUT_UP_BF, MLX5_SHUT_UP_BF_DEFAULT, 1);
 540         else
 541                 setenv(MLX5_SHUT_UP_BF,
 542                        config->dbnc == MLX5_TXDB_NCACHED ? "1" : "0", 1);
 543         return value;
 544 }
 545
 546 static void
 547 mlx5_restore_doorbell_mapping_env(int value)
 548 {
 549         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 550         /* Restore the original environment variable state. */
 551         if (value == MLX5_ARG_UNSET)
 552                 unsetenv(MLX5_SHUT_UP_BF);
 553         else
 554                 setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1);
 555 }
 556
 557 /**
 558  * Allocate shared IB device context. If there is multiport device the
 559  * master and representors will share this context, if there is single
 560  * port dedicated IB device, the context will be used by only given
 561  * port due to unification.
 562  *
 563  * Routine first searches the context for the specified IB device name,
 564  * if found the shared context assumed and reference counter is incremented.
 565  * If no context found the new one is created and initialized with specified
 566  * IB device context and parameters.
 567  *
 568  * @param[in] spawn
 569  *   Pointer to the IB device attributes (name, port, etc).
 570  * @param[in] config
 571  *   Pointer to device configuration structure.
 572  *
 573  * @return
 574  *   Pointer to mlx5_ibv_shared object on success,
 575  *   otherwise NULL and rte_errno is set.
 576  */
 577 static struct mlx5_ibv_shared *
 578 mlx5_alloc_shared_ibctx(const struct mlx5_dev_spawn_data *spawn,
 579                         const struct mlx5_dev_config *config)
 580 {
 581         struct mlx5_ibv_shared *sh;
 582         int dbmap_env;
 583         int err = 0;
 584         uint32_t i;
 585 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 586         struct mlx5_devx_tis_attr tis_attr = { 0 };
 587 #endif
 588
 589         MLX5_ASSERT(spawn);
 590         /* Secondary process should not create the shared context. */
 591         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 592         pthread_mutex_lock(&mlx5_ibv_list_mutex);
 593         /* Search for IB context by device name. */
 594         LIST_FOREACH(sh, &mlx5_ibv_list, next) {
 595                 if (!strcmp(sh->ibdev_name, spawn->ibv_dev->name)) {
 596                         sh->refcnt++;
 597                         goto exit;
 598                 }
 599         }
 600         /* No device found, we have to create new shared context. */
 601         MLX5_ASSERT(spawn->max_port);
 602         sh = rte_zmalloc("ethdev shared ib context",
 603                          sizeof(struct mlx5_ibv_shared) +
 604                          spawn->max_port *
 605                          sizeof(struct mlx5_ibv_shared_port),
 606                          RTE_CACHE_LINE_SIZE);
 607         if (!sh) {
 608                 DRV_LOG(ERR, "shared context allocation failure");
 609                 rte_errno  = ENOMEM;
 610                 goto exit;
 611         }
 612         /*
 613          * Configure environment variable "MLX5_BF_SHUT_UP"
 614          * before the device creation. The rdma_core library
 615          * checks the variable at device creation and
 616          * stores the result internally.
 617          */
 618         dbmap_env = mlx5_config_doorbell_mapping_env(config);
 619         /* Try to open IB device with DV first, then usual Verbs. */
 620         errno = 0;
 621         sh->ctx = mlx5_glue->dv_open_device(spawn->ibv_dev);
 622         if (sh->ctx) {
 623                 sh->devx = 1;
 624                 DRV_LOG(DEBUG, "DevX is supported");
 625                 /* The device is created, no need for environment. */
 626                 mlx5_restore_doorbell_mapping_env(dbmap_env);
 627         } else {
 628                 /* The environment variable is still configured. */
 629                 sh->ctx = mlx5_glue->open_device(spawn->ibv_dev);
 630                 err = errno ? errno : ENODEV;
 631                 /*
 632                  * The environment variable is not needed anymore,
 633                  * all device creation attempts are completed.
 634                  */
 635                 mlx5_restore_doorbell_mapping_env(dbmap_env);
 636                 if (!sh->ctx)
 637                         goto error;
 638                 DRV_LOG(DEBUG, "DevX is NOT supported");
 639         }
 640         err = mlx5_glue->query_device_ex(sh->ctx, NULL, &sh->device_attr);
 641         if (err) {
 642                 DRV_LOG(DEBUG, "ibv_query_device_ex() failed");
 643                 goto error;
 644         }
 645         sh->refcnt = 1;
 646         sh->max_port = spawn->max_port;
 647         strncpy(sh->ibdev_name, sh->ctx->device->name,
 648                 sizeof(sh->ibdev_name));
 649         strncpy(sh->ibdev_path, sh->ctx->device->ibdev_path,
 650                 sizeof(sh->ibdev_path));
 651         pthread_mutex_init(&sh->intr_mutex, NULL);
 652         /*
 653          * Setting port_id to max unallowed value means
 654          * there is no interrupt subhandler installed for
 655          * the given port index i.
 656          */
 657         for (i = 0; i < sh->max_port; i++) {
 658                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 659                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
 660         }
 661         sh->pd = mlx5_glue->alloc_pd(sh->ctx);
 662         if (sh->pd == NULL) {
 663                 DRV_LOG(ERR, "PD allocation failure");
 664                 err = ENOMEM;
 665                 goto error;
 666         }
 667 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 668         if (sh->devx) {
 669                 err = mlx5_get_pdn(sh->pd, &sh->pdn);
 670                 if (err) {
 671                         DRV_LOG(ERR, "Fail to extract pdn from PD");
 672                         goto error;
 673                 }
 674                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
 675                 if (!sh->td) {
 676                         DRV_LOG(ERR, "TD allocation failure");
 677                         err = ENOMEM;
 678                         goto error;
 679                 }
 680                 tis_attr.transport_domain = sh->td->id;
 681                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
 682                 if (!sh->tis) {
 683                         DRV_LOG(ERR, "TIS allocation failure");
 684                         err = ENOMEM;
 685                         goto error;
 686                 }
 687         }
 688         sh->flow_id_pool = mlx5_flow_id_pool_alloc(UINT32_MAX);
 689         if (!sh->flow_id_pool) {
 690                 DRV_LOG(ERR, "can't create flow id pool");
 691                 err = ENOMEM;
 692                 goto error;
 693         }
 694 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
 695         /*
 696          * Once the device is added to the list of memory event
 697          * callback, its global MR cache table cannot be expanded
 698          * on the fly because of deadlock. If it overflows, lookup
 699          * should be done by searching MR list linearly, which is slow.
 700          *
 701          * At this point the device is not added to the memory
 702          * event list yet, context is just being created.
 703          */
 704         err = mlx5_mr_btree_init(&sh->share_cache.cache,
 705                                  MLX5_MR_BTREE_CACHE_N * 2,
 706                                  spawn->pci_dev->device.numa_node);
 707         if (err) {
 708                 err = rte_errno;
 709                 goto error;
 710         }
 711         mlx5_flow_counters_mng_init(sh);
 712         mlx5_flow_ipool_create(sh);
 713         /* Add device to memory callback list. */
 714         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 715         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
 716                          sh, mem_event_cb);
 717         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 718         /* Add context to the global device list. */
 719         LIST_INSERT_HEAD(&mlx5_ibv_list, sh, next);
 720 exit:
 721         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 722         return sh;
 723 error:
 724         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 725         MLX5_ASSERT(sh);
 726         if (sh->tis)
 727                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 728         if (sh->td)
 729                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 730         if (sh->pd)
 731                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 732         if (sh->ctx)
 733                 claim_zero(mlx5_glue->close_device(sh->ctx));
 734         if (sh->flow_id_pool)
 735                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 736         rte_free(sh);
 737         MLX5_ASSERT(err > 0);
 738         rte_errno = err;
 739         return NULL;
 740 }
 741
 742 /**
 743  * Free shared IB device context. Decrement counter and if zero free
 744  * all allocated resources and close handles.
 745  *
 746  * @param[in] sh
 747  *   Pointer to mlx5_ibv_shared object to free
 748  */
 749 static void
 750 mlx5_free_shared_ibctx(struct mlx5_ibv_shared *sh)
 751 {
 752         pthread_mutex_lock(&mlx5_ibv_list_mutex);
 753 #ifdef RTE_LIBRTE_MLX5_DEBUG
 754         /* Check the object presence in the list. */
 755         struct mlx5_ibv_shared *lctx;
 756
 757         LIST_FOREACH(lctx, &mlx5_ibv_list, next)
 758                 if (lctx == sh)
 759                         break;
 760         MLX5_ASSERT(lctx);
 761         if (lctx != sh) {
 762                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
 763                 goto exit;
 764         }
 765 #endif
 766         MLX5_ASSERT(sh);
 767         MLX5_ASSERT(sh->refcnt);
 768         /* Secondary process should not free the shared context. */
 769         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 770         if (--sh->refcnt)
 771                 goto exit;
 772         /* Remove from memory callback device list. */
 773         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 774         LIST_REMOVE(sh, mem_event_cb);
 775         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 776         /* Release created Memory Regions. */
 777         mlx5_mr_release_cache(&sh->share_cache);
 778         /* Remove context from the global device list. */
 779         LIST_REMOVE(sh, next);
 780         /*
 781          *  Ensure there is no async event handler installed.
 782          *  Only primary process handles async device events.
 783          **/
 784         mlx5_flow_counters_mng_close(sh);
 785         mlx5_flow_ipool_destroy(sh);
 786         MLX5_ASSERT(!sh->intr_cnt);
 787         if (sh->intr_cnt)
 788                 mlx5_intr_callback_unregister
 789                         (&sh->intr_handle, mlx5_dev_interrupt_handler, sh);
 790 #ifdef HAVE_MLX5_DEVX_ASYNC_SUPPORT
 791         if (sh->devx_intr_cnt) {
 792                 if (sh->intr_handle_devx.fd)
 793                         rte_intr_callback_unregister(&sh->intr_handle_devx,
 794                                           mlx5_dev_interrupt_handler_devx, sh);
 795                 if (sh->devx_comp)
 796                         mlx5dv_devx_destroy_cmd_comp(sh->devx_comp);
 797         }
 798 #endif
 799         pthread_mutex_destroy(&sh->intr_mutex);
 800         if (sh->pd)
 801                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 802         if (sh->tis)
 803                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 804         if (sh->td)
 805                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 806         if (sh->ctx)
 807                 claim_zero(mlx5_glue->close_device(sh->ctx));
 808         if (sh->flow_id_pool)
 809                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 810         rte_free(sh);
 811 exit:
 812         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 813 }
 814
 815 /**
 816  * Destroy table hash list and all the root entries per domain.
 817  *
 818  * @param[in] priv
 819  *   Pointer to the private device data structure.
 820  */
 821 static void
 822 mlx5_free_table_hash_list(struct mlx5_priv *priv)
 823 {
 824         struct mlx5_ibv_shared *sh = priv->sh;
 825         struct mlx5_flow_tbl_data_entry *tbl_data;
 826         union mlx5_flow_tbl_key table_key = {
 827                 {
 828                         .table_id = 0,
 829                         .reserved = 0,
 830                         .domain = 0,
 831                         .direction = 0,
 832                 }
 833         };
 834         struct mlx5_hlist_entry *pos;
 835
 836         if (!sh->flow_tbls)
 837                 return;
 838         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 839         if (pos) {
 840                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 841                                         entry);
 842                 MLX5_ASSERT(tbl_data);
 843                 mlx5_hlist_remove(sh->flow_tbls, pos);
 844                 rte_free(tbl_data);
 845         }
 846         table_key.direction = 1;
 847         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 848         if (pos) {
 849                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 850                                         entry);
 851                 MLX5_ASSERT(tbl_data);
 852                 mlx5_hlist_remove(sh->flow_tbls, pos);
 853                 rte_free(tbl_data);
 854         }
 855         table_key.direction = 0;
 856         table_key.domain = 1;
 857         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 858         if (pos) {
 859                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 860                                         entry);
 861                 MLX5_ASSERT(tbl_data);
 862                 mlx5_hlist_remove(sh->flow_tbls, pos);
 863                 rte_free(tbl_data);
 864         }
 865         mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
 866 }
 867
 868 /**
 869  * Initialize flow table hash list and create the root tables entry
 870  * for each domain.
 871  *
 872  * @param[in] priv
 873  *   Pointer to the private device data structure.
 874  *
 875  * @return
 876  *   Zero on success, positive error code otherwise.
 877  */
 878 static int
 879 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
 880 {
 881         struct mlx5_ibv_shared *sh = priv->sh;
 882         char s[MLX5_HLIST_NAMESIZE];
 883         int err = 0;
 884
 885         MLX5_ASSERT(sh);
 886         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
 887         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
 888         if (!sh->flow_tbls) {
 889                 DRV_LOG(ERR, "flow tables with hash creation failed.\n");
 890                 err = ENOMEM;
 891                 return err;
 892         }
 893 #ifndef HAVE_MLX5DV_DR
 894         /*
 895          * In case we have not DR support, the zero tables should be created
 896          * because DV expect to see them even if they cannot be created by
 897          * RDMA-CORE.
 898          */
 899         union mlx5_flow_tbl_key table_key = {
 900                 {
 901                         .table_id = 0,
 902                         .reserved = 0,
 903                         .domain = 0,
 904                         .direction = 0,
 905                 }
 906         };
 907         struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL,
 908                                                           sizeof(*tbl_data), 0);
 909
 910         if (!tbl_data) {
 911                 err = ENOMEM;
 912                 goto error;
 913         }
 914         tbl_data->entry.key = table_key.v64;
 915         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 916         if (err)
 917                 goto error;
 918         rte_atomic32_init(&tbl_data->tbl.refcnt);
 919         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 920         table_key.direction = 1;
 921         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 922         if (!tbl_data) {
 923                 err = ENOMEM;
 924                 goto error;
 925         }
 926         tbl_data->entry.key = table_key.v64;
 927         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 928         if (err)
 929                 goto error;
 930         rte_atomic32_init(&tbl_data->tbl.refcnt);
 931         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 932         table_key.direction = 0;
 933         table_key.domain = 1;
 934         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 935         if (!tbl_data) {
 936                 err = ENOMEM;
 937                 goto error;
 938         }
 939         tbl_data->entry.key = table_key.v64;
 940         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 941         if (err)
 942                 goto error;
 943         rte_atomic32_init(&tbl_data->tbl.refcnt);
 944         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 945         return err;
 946 error:
 947         mlx5_free_table_hash_list(priv);
 948 #endif /* HAVE_MLX5DV_DR */
 949         return err;
 950 }
 951
 952 /**
 953  * Initialize DR related data within private structure.
 954  * Routine checks the reference counter and does actual
 955  * resources creation/initialization only if counter is zero.
 956  *
 957  * @param[in] priv
 958  *   Pointer to the private device data structure.
 959  *
 960  * @return
 961  *   Zero on success, positive error code otherwise.
 962  */
 963 static int
 964 mlx5_alloc_shared_dr(struct mlx5_priv *priv)
 965 {
 966         struct mlx5_ibv_shared *sh = priv->sh;
 967         char s[MLX5_HLIST_NAMESIZE];
 968         int err = 0;
 969
 970         if (!sh->flow_tbls)
 971                 err = mlx5_alloc_table_hash_list(priv);
 972         else
 973                 DRV_LOG(DEBUG, "sh->flow_tbls[%p] already created, reuse\n",
 974                         (void *)sh->flow_tbls);
 975         if (err)
 976                 return err;
 977         /* Create tags hash list table. */
 978         snprintf(s, sizeof(s), "%s_tags", sh->ibdev_name);
 979         sh->tag_table = mlx5_hlist_create(s, MLX5_TAGS_HLIST_ARRAY_SIZE);
 980         if (!sh->tag_table) {
 981                 DRV_LOG(ERR, "tags with hash creation failed.\n");
 982                 err = ENOMEM;
 983                 goto error;
 984         }
 985 #ifdef HAVE_MLX5DV_DR
 986         void *domain;
 987
 988         if (sh->dv_refcnt) {
 989                 /* Shared DV/DR structures is already initialized. */
 990                 sh->dv_refcnt++;
 991                 priv->dr_shared = 1;
 992                 return 0;
 993         }
 994         /* Reference counter is zero, we should initialize structures. */
 995         domain = mlx5_glue->dr_create_domain(sh->ctx,
 996                                              MLX5DV_DR_DOMAIN_TYPE_NIC_RX);
 997         if (!domain) {
 998                 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed");
 999                 err = errno;
1000                 goto error;
1001         }
1002         sh->rx_domain = domain;
1003         domain = mlx5_glue->dr_create_domain(sh->ctx,
1004                                              MLX5DV_DR_DOMAIN_TYPE_NIC_TX);
1005         if (!domain) {
1006                 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed");
1007                 err = errno;
1008                 goto error;
1009         }
1010         pthread_mutex_init(&sh->dv_mutex, NULL);
1011         sh->tx_domain = domain;
1012 #ifdef HAVE_MLX5DV_DR_ESWITCH
1013         if (priv->config.dv_esw_en) {
1014                 domain  = mlx5_glue->dr_create_domain
1015                         (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB);
1016                 if (!domain) {
1017                         DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed");
1018                         err = errno;
1019                         goto error;
1020                 }
1021                 sh->fdb_domain = domain;
1022                 sh->esw_drop_action = mlx5_glue->dr_create_flow_action_drop();
1023         }
1024 #endif
1025         sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan();
1026 #endif /* HAVE_MLX5DV_DR */
1027         sh->dv_refcnt++;
1028         priv->dr_shared = 1;
1029         return 0;
1030 error:
1031         /* Rollback the created objects. */
1032         if (sh->rx_domain) {
1033                 mlx5_glue->dr_destroy_domain(sh->rx_domain);
1034                 sh->rx_domain = NULL;
1035         }
1036         if (sh->tx_domain) {
1037                 mlx5_glue->dr_destroy_domain(sh->tx_domain);
1038                 sh->tx_domain = NULL;
1039         }
1040         if (sh->fdb_domain) {
1041                 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
1042                 sh->fdb_domain = NULL;
1043         }
1044         if (sh->esw_drop_action) {
1045                 mlx5_glue->destroy_flow_action(sh->esw_drop_action);
1046                 sh->esw_drop_action = NULL;
1047         }
1048         if (sh->pop_vlan_action) {
1049                 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
1050                 sh->pop_vlan_action = NULL;
1051         }
1052         if (sh->tag_table) {
1053                 /* tags should be destroyed with flow before. */
1054                 mlx5_hlist_destroy(sh->tag_table, NULL, NULL);
1055                 sh->tag_table = NULL;
1056         }
1057         mlx5_free_table_hash_list(priv);
1058         return err;
1059 }
1060
1061 /**
1062  * Destroy DR related data within private structure.
1063  *
1064  * @param[in] priv
1065  *   Pointer to the private device data structure.
1066  */
1067 static void
1068 mlx5_free_shared_dr(struct mlx5_priv *priv)
1069 {
1070         struct mlx5_ibv_shared *sh;
1071
1072         if (!priv->dr_shared)
1073                 return;
1074         priv->dr_shared = 0;
1075         sh = priv->sh;
1076         MLX5_ASSERT(sh);
1077 #ifdef HAVE_MLX5DV_DR
1078         MLX5_ASSERT(sh->dv_refcnt);
1079         if (sh->dv_refcnt && --sh->dv_refcnt)
1080                 return;
1081         if (sh->rx_domain) {
1082                 mlx5_glue->dr_destroy_domain(sh->rx_domain);
1083                 sh->rx_domain = NULL;
1084         }
1085         if (sh->tx_domain) {
1086                 mlx5_glue->dr_destroy_domain(sh->tx_domain);
1087                 sh->tx_domain = NULL;
1088         }
1089 #ifdef HAVE_MLX5DV_DR_ESWITCH
1090         if (sh->fdb_domain) {
1091                 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
1092                 sh->fdb_domain = NULL;
1093         }
1094         if (sh->esw_drop_action) {
1095                 mlx5_glue->destroy_flow_action(sh->esw_drop_action);
1096                 sh->esw_drop_action = NULL;
1097         }
1098 #endif
1099         if (sh->pop_vlan_action) {
1100                 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
1101                 sh->pop_vlan_action = NULL;
1102         }
1103         pthread_mutex_destroy(&sh->dv_mutex);
1104 #endif /* HAVE_MLX5DV_DR */
1105         if (sh->tag_table) {
1106                 /* tags should be destroyed with flow before. */
1107                 mlx5_hlist_destroy(sh->tag_table, NULL, NULL);
1108                 sh->tag_table = NULL;
1109         }
1110         mlx5_free_table_hash_list(priv);
1111 }
1112
1113 /**
1114  * Initialize shared data between primary and secondary process.
1115  *
1116  * A memzone is reserved by primary process and secondary processes attach to
1117  * the memzone.
1118  *
1119  * @return
1120  *   0 on success, a negative errno value otherwise and rte_errno is set.
1121  */
1122 static int
1123 mlx5_init_shared_data(void)
1124 {
1125         const struct rte_memzone *mz;
1126         int ret = 0;
1127
1128         rte_spinlock_lock(&mlx5_shared_data_lock);
1129         if (mlx5_shared_data == NULL) {
1130                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
1131                         /* Allocate shared memory. */
1132                         mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
1133                                                  sizeof(*mlx5_shared_data),
1134                                                  SOCKET_ID_ANY, 0);
1135                         if (mz == NULL) {
1136                                 DRV_LOG(ERR,
1137                                         "Cannot allocate mlx5 shared data");
1138                                 ret = -rte_errno;
1139                                 goto error;
1140                         }
1141                         mlx5_shared_data = mz->addr;
1142                         memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
1143                         rte_spinlock_init(&mlx5_shared_data->lock);
1144                 } else {
1145                         /* Lookup allocated shared memory. */
1146                         mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
1147                         if (mz == NULL) {
1148                                 DRV_LOG(ERR,
1149                                         "Cannot attach mlx5 shared data");
1150                                 ret = -rte_errno;
1151                                 goto error;
1152                         }
1153                         mlx5_shared_data = mz->addr;
1154                         memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
1155                 }
1156         }
1157 error:
1158         rte_spinlock_unlock(&mlx5_shared_data_lock);
1159         return ret;
1160 }
1161
1162 /**
1163  * Retrieve integer value from environment variable.
1164  *
1165  * @param[in] name
1166  *   Environment variable name.
1167  *
1168  * @return
1169  *   Integer value, 0 if the variable is not set.
1170  */
1171 int
1172 mlx5_getenv_int(const char *name)
1173 {
1174         const char *val = getenv(name);
1175
1176         if (val == NULL)
1177                 return 0;
1178         return atoi(val);
1179 }
1180
1181 /**
1182  * Verbs callback to allocate a memory. This function should allocate the space
1183  * according to the size provided residing inside a huge page.
1184  * Please note that all allocation must respect the alignment from libmlx5
1185  * (i.e. currently sysconf(_SC_PAGESIZE)).
1186  *
1187  * @param[in] size
1188  *   The size in bytes of the memory to allocate.
1189  * @param[in] data
1190  *   A pointer to the callback data.
1191  *
1192  * @return
1193  *   Allocated buffer, NULL otherwise and rte_errno is set.
1194  */
1195 static void *
1196 mlx5_alloc_verbs_buf(size_t size, void *data)
1197 {
1198         struct mlx5_priv *priv = data;
1199         void *ret;
1200         size_t alignment = sysconf(_SC_PAGESIZE);
1201         unsigned int socket = SOCKET_ID_ANY;
1202
1203         if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
1204                 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
1205
1206                 socket = ctrl->socket;
1207         } else if (priv->verbs_alloc_ctx.type ==
1208                    MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
1209                 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
1210
1211                 socket = ctrl->socket;
1212         }
1213         MLX5_ASSERT(data != NULL);
1214         ret = rte_malloc_socket(__func__, size, alignment, socket);
1215         if (!ret && size)
1216                 rte_errno = ENOMEM;
1217         return ret;
1218 }
1219
1220 /**
1221  * Verbs callback to free a memory.
1222  *
1223  * @param[in] ptr
1224  *   A pointer to the memory to free.
1225  * @param[in] data
1226  *   A pointer to the callback data.
1227  */
1228 static void
1229 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
1230 {
1231         MLX5_ASSERT(data != NULL);
1232         rte_free(ptr);
1233 }
1234
1235 /**
1236  * DPDK callback to add udp tunnel port
1237  *
1238  * @param[in] dev
1239  *   A pointer to eth_dev
1240  * @param[in] udp_tunnel
1241  *   A pointer to udp tunnel
1242  *
1243  * @return
1244  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1245  */
1246 int
1247 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1248                          struct rte_eth_udp_tunnel *udp_tunnel)
1249 {
1250         MLX5_ASSERT(udp_tunnel != NULL);
1251         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1252             udp_tunnel->udp_port == 4789)
1253                 return 0;
1254         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1255             udp_tunnel->udp_port == 4790)
1256                 return 0;
1257         return -ENOTSUP;
1258 }
1259
1260 /**
1261  * Initialize process private data structure.
1262  *
1263  * @param dev
1264  *   Pointer to Ethernet device structure.
1265  *
1266  * @return
1267  *   0 on success, a negative errno value otherwise and rte_errno is set.
1268  */
1269 int
1270 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1271 {
1272         struct mlx5_priv *priv = dev->data->dev_private;
1273         struct mlx5_proc_priv *ppriv;
1274         size_t ppriv_size;
1275
1276         /*
1277          * UAR register table follows the process private structure. BlueFlame
1278          * registers for Tx queues are stored in the table.
1279          */
1280         ppriv_size =
1281                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1282         ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
1283                                   RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1284         if (!ppriv) {
1285                 rte_errno = ENOMEM;
1286                 return -rte_errno;
1287         }
1288         ppriv->uar_table_sz = ppriv_size;
1289         dev->process_private = ppriv;
1290         return 0;
1291 }
1292
1293 /**
1294  * Un-initialize process private data structure.
1295  *
1296  * @param dev
1297  *   Pointer to Ethernet device structure.
1298  */
1299 static void
1300 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1301 {
1302         if (!dev->process_private)
1303                 return;
1304         rte_free(dev->process_private);
1305         dev->process_private = NULL;
1306 }
1307
1308 /**
1309  * DPDK callback to close the device.
1310  *
1311  * Destroy all queues and objects, free memory.
1312  *
1313  * @param dev
1314  *   Pointer to Ethernet device structure.
1315  */
1316 static void
1317 mlx5_dev_close(struct rte_eth_dev *dev)
1318 {
1319         struct mlx5_priv *priv = dev->data->dev_private;
1320         unsigned int i;
1321         int ret;
1322
1323         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1324                 dev->data->port_id,
1325                 ((priv->sh->ctx != NULL) ? priv->sh->ctx->device->name : ""));
1326         /* In case mlx5_dev_stop() has not been called. */
1327         mlx5_dev_interrupt_handler_uninstall(dev);
1328         mlx5_dev_interrupt_handler_devx_uninstall(dev);
1329         /*
1330          * If default mreg copy action is removed at the stop stage,
1331          * the search will return none and nothing will be done anymore.
1332          */
1333         mlx5_flow_stop_default(dev);
1334         mlx5_traffic_disable(dev);
1335         /*
1336          * If all the flows are already flushed in the device stop stage,
1337          * then this will return directly without any action.
1338          */
1339         mlx5_flow_list_flush(dev, &priv->flows, true);
1340         mlx5_flow_meter_flush(dev, NULL);
1341         /* Free the intermediate buffers for flow creation. */
1342         mlx5_flow_free_intermediate(dev);
1343         /* Prevent crashes when queues are still in use. */
1344         dev->rx_pkt_burst = removed_rx_burst;
1345         dev->tx_pkt_burst = removed_tx_burst;
1346         rte_wmb();
1347         /* Disable datapath on secondary process. */
1348         mlx5_mp_req_stop_rxtx(dev);
1349         if (priv->rxqs != NULL) {
1350                 /* XXX race condition if mlx5_rx_burst() is still running. */
1351                 usleep(1000);
1352                 for (i = 0; (i != priv->rxqs_n); ++i)
1353                         mlx5_rxq_release(dev, i);
1354                 priv->rxqs_n = 0;
1355                 priv->rxqs = NULL;
1356         }
1357         if (priv->txqs != NULL) {
1358                 /* XXX race condition if mlx5_tx_burst() is still running. */
1359                 usleep(1000);
1360                 for (i = 0; (i != priv->txqs_n); ++i)
1361                         mlx5_txq_release(dev, i);
1362                 priv->txqs_n = 0;
1363                 priv->txqs = NULL;
1364         }
1365         mlx5_proc_priv_uninit(dev);
1366         if (priv->mreg_cp_tbl)
1367                 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1368         mlx5_mprq_free_mp(dev);
1369         mlx5_free_shared_dr(priv);
1370         if (priv->rss_conf.rss_key != NULL)
1371                 rte_free(priv->rss_conf.rss_key);
1372         if (priv->reta_idx != NULL)
1373                 rte_free(priv->reta_idx);
1374         if (priv->config.vf)
1375                 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1376                                        dev->data->mac_addrs,
1377                                        MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1378         if (priv->nl_socket_route >= 0)
1379                 close(priv->nl_socket_route);
1380         if (priv->nl_socket_rdma >= 0)
1381                 close(priv->nl_socket_rdma);
1382         if (priv->vmwa_context)
1383                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1384         if (priv->sh) {
1385                 /*
1386                  * Free the shared context in last turn, because the cleanup
1387                  * routines above may use some shared fields, like
1388                  * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1389                  * ifindex if Netlink fails.
1390                  */
1391                 mlx5_free_shared_ibctx(priv->sh);
1392                 priv->sh = NULL;
1393         }
1394         ret = mlx5_hrxq_verify(dev);
1395         if (ret)
1396                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1397                         dev->data->port_id);
1398         ret = mlx5_ind_table_obj_verify(dev);
1399         if (ret)
1400                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1401                         dev->data->port_id);
1402         ret = mlx5_rxq_obj_verify(dev);
1403         if (ret)
1404                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1405                         dev->data->port_id);
1406         ret = mlx5_rxq_verify(dev);
1407         if (ret)
1408                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1409                         dev->data->port_id);
1410         ret = mlx5_txq_obj_verify(dev);
1411         if (ret)
1412                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1413                         dev->data->port_id);
1414         ret = mlx5_txq_verify(dev);
1415         if (ret)
1416                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1417                         dev->data->port_id);
1418         ret = mlx5_flow_verify(dev);
1419         if (ret)
1420                 DRV_LOG(WARNING, "port %u some flows still remain",
1421                         dev->data->port_id);
1422         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1423                 unsigned int c = 0;
1424                 uint16_t port_id;
1425
1426                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1427                         struct mlx5_priv *opriv =
1428                                 rte_eth_devices[port_id].data->dev_private;
1429
1430                         if (!opriv ||
1431                             opriv->domain_id != priv->domain_id ||
1432                             &rte_eth_devices[port_id] == dev)
1433                                 continue;
1434                         ++c;
1435                         break;
1436                 }
1437                 if (!c)
1438                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1439         }
1440         memset(priv, 0, sizeof(*priv));
1441         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1442         /*
1443          * Reset mac_addrs to NULL such that it is not freed as part of
1444          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1445          * it is freed when dev_private is freed.
1446          */
1447         dev->data->mac_addrs = NULL;
1448 }
1449
1450 const struct eth_dev_ops mlx5_dev_ops = {
1451         .dev_configure = mlx5_dev_configure,
1452         .dev_start = mlx5_dev_start,
1453         .dev_stop = mlx5_dev_stop,
1454         .dev_set_link_down = mlx5_set_link_down,
1455         .dev_set_link_up = mlx5_set_link_up,
1456         .dev_close = mlx5_dev_close,
1457         .promiscuous_enable = mlx5_promiscuous_enable,
1458         .promiscuous_disable = mlx5_promiscuous_disable,
1459         .allmulticast_enable = mlx5_allmulticast_enable,
1460         .allmulticast_disable = mlx5_allmulticast_disable,
1461         .link_update = mlx5_link_update,
1462         .stats_get = mlx5_stats_get,
1463         .stats_reset = mlx5_stats_reset,
1464         .xstats_get = mlx5_xstats_get,
1465         .xstats_reset = mlx5_xstats_reset,
1466         .xstats_get_names = mlx5_xstats_get_names,
1467         .fw_version_get = mlx5_fw_version_get,
1468         .dev_infos_get = mlx5_dev_infos_get,
1469         .read_clock = mlx5_read_clock,
1470         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1471         .vlan_filter_set = mlx5_vlan_filter_set,
1472         .rx_queue_setup = mlx5_rx_queue_setup,
1473         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1474         .tx_queue_setup = mlx5_tx_queue_setup,
1475         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1476         .rx_queue_release = mlx5_rx_queue_release,
1477         .tx_queue_release = mlx5_tx_queue_release,
1478         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1479         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1480         .mac_addr_remove = mlx5_mac_addr_remove,
1481         .mac_addr_add = mlx5_mac_addr_add,
1482         .mac_addr_set = mlx5_mac_addr_set,
1483         .set_mc_addr_list = mlx5_set_mc_addr_list,
1484         .mtu_set = mlx5_dev_set_mtu,
1485         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1486         .vlan_offload_set = mlx5_vlan_offload_set,
1487         .reta_update = mlx5_dev_rss_reta_update,
1488         .reta_query = mlx5_dev_rss_reta_query,
1489         .rss_hash_update = mlx5_rss_hash_update,
1490         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1491         .filter_ctrl = mlx5_dev_filter_ctrl,
1492         .rx_descriptor_status = mlx5_rx_descriptor_status,
1493         .tx_descriptor_status = mlx5_tx_descriptor_status,
1494         .rxq_info_get = mlx5_rxq_info_get,
1495         .txq_info_get = mlx5_txq_info_get,
1496         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1497         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1498         .rx_queue_count = mlx5_rx_queue_count,
1499         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1500         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1501         .is_removed = mlx5_is_removed,
1502         .udp_tunnel_port_add  = mlx5_udp_tunnel_port_add,
1503         .get_module_info = mlx5_get_module_info,
1504         .get_module_eeprom = mlx5_get_module_eeprom,
1505         .hairpin_cap_get = mlx5_hairpin_cap_get,
1506         .mtr_ops_get = mlx5_flow_meter_ops_get,
1507 };
1508
1509 /* Available operations from secondary process. */
1510 static const struct eth_dev_ops mlx5_dev_sec_ops = {
1511         .stats_get = mlx5_stats_get,
1512         .stats_reset = mlx5_stats_reset,
1513         .xstats_get = mlx5_xstats_get,
1514         .xstats_reset = mlx5_xstats_reset,
1515         .xstats_get_names = mlx5_xstats_get_names,
1516         .fw_version_get = mlx5_fw_version_get,
1517         .dev_infos_get = mlx5_dev_infos_get,
1518         .rx_descriptor_status = mlx5_rx_descriptor_status,
1519         .tx_descriptor_status = mlx5_tx_descriptor_status,
1520         .rxq_info_get = mlx5_rxq_info_get,
1521         .txq_info_get = mlx5_txq_info_get,
1522         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1523         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1524         .get_module_info = mlx5_get_module_info,
1525         .get_module_eeprom = mlx5_get_module_eeprom,
1526 };
1527
1528 /* Available operations in flow isolated mode. */
1529 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1530         .dev_configure = mlx5_dev_configure,
1531         .dev_start = mlx5_dev_start,
1532         .dev_stop = mlx5_dev_stop,
1533         .dev_set_link_down = mlx5_set_link_down,
1534         .dev_set_link_up = mlx5_set_link_up,
1535         .dev_close = mlx5_dev_close,
1536         .promiscuous_enable = mlx5_promiscuous_enable,
1537         .promiscuous_disable = mlx5_promiscuous_disable,
1538         .allmulticast_enable = mlx5_allmulticast_enable,
1539         .allmulticast_disable = mlx5_allmulticast_disable,
1540         .link_update = mlx5_link_update,
1541         .stats_get = mlx5_stats_get,
1542         .stats_reset = mlx5_stats_reset,
1543         .xstats_get = mlx5_xstats_get,
1544         .xstats_reset = mlx5_xstats_reset,
1545         .xstats_get_names = mlx5_xstats_get_names,
1546         .fw_version_get = mlx5_fw_version_get,
1547         .dev_infos_get = mlx5_dev_infos_get,
1548         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1549         .vlan_filter_set = mlx5_vlan_filter_set,
1550         .rx_queue_setup = mlx5_rx_queue_setup,
1551         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1552         .tx_queue_setup = mlx5_tx_queue_setup,
1553         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1554         .rx_queue_release = mlx5_rx_queue_release,
1555         .tx_queue_release = mlx5_tx_queue_release,
1556         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1557         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1558         .mac_addr_remove = mlx5_mac_addr_remove,
1559         .mac_addr_add = mlx5_mac_addr_add,
1560         .mac_addr_set = mlx5_mac_addr_set,
1561         .set_mc_addr_list = mlx5_set_mc_addr_list,
1562         .mtu_set = mlx5_dev_set_mtu,
1563         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1564         .vlan_offload_set = mlx5_vlan_offload_set,
1565         .filter_ctrl = mlx5_dev_filter_ctrl,
1566         .rx_descriptor_status = mlx5_rx_descriptor_status,
1567         .tx_descriptor_status = mlx5_tx_descriptor_status,
1568         .rxq_info_get = mlx5_rxq_info_get,
1569         .txq_info_get = mlx5_txq_info_get,
1570         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1571         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1572         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1573         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1574         .is_removed = mlx5_is_removed,
1575         .get_module_info = mlx5_get_module_info,
1576         .get_module_eeprom = mlx5_get_module_eeprom,
1577         .hairpin_cap_get = mlx5_hairpin_cap_get,
1578         .mtr_ops_get = mlx5_flow_meter_ops_get,
1579 };
1580
1581 /**
1582  * Verify and store value for device argument.
1583  *
1584  * @param[in] key
1585  *   Key argument to verify.
1586  * @param[in] val
1587  *   Value associated with key.
1588  * @param opaque
1589  *   User data.
1590  *
1591  * @return
1592  *   0 on success, a negative errno value otherwise and rte_errno is set.
1593  */
1594 static int
1595 mlx5_args_check(const char *key, const char *val, void *opaque)
1596 {
1597         struct mlx5_dev_config *config = opaque;
1598         unsigned long tmp;
1599
1600         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1601         if (!strcmp(MLX5_REPRESENTOR, key))
1602                 return 0;
1603         errno = 0;
1604         tmp = strtoul(val, NULL, 0);
1605         if (errno) {
1606                 rte_errno = errno;
1607                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1608                 return -rte_errno;
1609         }
1610         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1611                 config->cqe_comp = !!tmp;
1612         } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1613                 config->cqe_pad = !!tmp;
1614         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1615                 config->hw_padding = !!tmp;
1616         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1617                 config->mprq.enabled = !!tmp;
1618         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1619                 config->mprq.stride_num_n = tmp;
1620         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1621                 config->mprq.stride_size_n = tmp;
1622         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1623                 config->mprq.max_memcpy_len = tmp;
1624         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1625                 config->mprq.min_rxqs_num = tmp;
1626         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1627                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1628                                  " converted to txq_inline_max", key);
1629                 config->txq_inline_max = tmp;
1630         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1631                 config->txq_inline_max = tmp;
1632         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1633                 config->txq_inline_min = tmp;
1634         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1635                 config->txq_inline_mpw = tmp;
1636         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1637                 config->txqs_inline = tmp;
1638         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1639                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1640         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1641                 config->mps = !!tmp;
1642         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1643                 if (tmp != MLX5_TXDB_CACHED &&
1644                     tmp != MLX5_TXDB_NCACHED &&
1645                     tmp != MLX5_TXDB_HEURISTIC) {
1646                         DRV_LOG(ERR, "invalid Tx doorbell "
1647                                      "mapping parameter");
1648                         rte_errno = EINVAL;
1649                         return -rte_errno;
1650                 }
1651                 config->dbnc = tmp;
1652         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1653                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1654         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1655                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1656                                  " converted to txq_inline_mpw", key);
1657                 config->txq_inline_mpw = tmp;
1658         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1659                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1660         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1661                 config->rx_vec_en = !!tmp;
1662         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1663                 config->l3_vxlan_en = !!tmp;
1664         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1665                 config->vf_nl_en = !!tmp;
1666         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1667                 config->dv_esw_en = !!tmp;
1668         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1669                 config->dv_flow_en = !!tmp;
1670         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1671                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1672                     tmp != MLX5_XMETA_MODE_META16 &&
1673                     tmp != MLX5_XMETA_MODE_META32) {
1674                         DRV_LOG(ERR, "invalid extensive "
1675                                      "metadata parameter");
1676                         rte_errno = EINVAL;
1677                         return -rte_errno;
1678                 }
1679                 config->dv_xmeta_en = tmp;
1680         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1681                 config->mr_ext_memseg_en = !!tmp;
1682         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1683                 config->max_dump_files_num = tmp;
1684         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1685                 config->lro.timeout = tmp;
1686         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1687                 DRV_LOG(DEBUG, "class argument is %s.", val);
1688         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1689                 config->log_hp_size = tmp;
1690         } else {
1691                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1692                 rte_errno = EINVAL;
1693                 return -rte_errno;
1694         }
1695         return 0;
1696 }
1697
1698 /**
1699  * Parse device parameters.
1700  *
1701  * @param config
1702  *   Pointer to device configuration structure.
1703  * @param devargs
1704  *   Device arguments structure.
1705  *
1706  * @return
1707  *   0 on success, a negative errno value otherwise and rte_errno is set.
1708  */
1709 static int
1710 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1711 {
1712         const char **params = (const char *[]){
1713                 MLX5_RXQ_CQE_COMP_EN,
1714                 MLX5_RXQ_CQE_PAD_EN,
1715                 MLX5_RXQ_PKT_PAD_EN,
1716                 MLX5_RX_MPRQ_EN,
1717                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1718                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1719                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1720                 MLX5_RXQS_MIN_MPRQ,
1721                 MLX5_TXQ_INLINE,
1722                 MLX5_TXQ_INLINE_MIN,
1723                 MLX5_TXQ_INLINE_MAX,
1724                 MLX5_TXQ_INLINE_MPW,
1725                 MLX5_TXQS_MIN_INLINE,
1726                 MLX5_TXQS_MAX_VEC,
1727                 MLX5_TXQ_MPW_EN,
1728                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1729                 MLX5_TXQ_MAX_INLINE_LEN,
1730                 MLX5_TX_DB_NC,
1731                 MLX5_TX_VEC_EN,
1732                 MLX5_RX_VEC_EN,
1733                 MLX5_L3_VXLAN_EN,
1734                 MLX5_VF_NL_EN,
1735                 MLX5_DV_ESW_EN,
1736                 MLX5_DV_FLOW_EN,
1737                 MLX5_DV_XMETA_EN,
1738                 MLX5_MR_EXT_MEMSEG_EN,
1739                 MLX5_REPRESENTOR,
1740                 MLX5_MAX_DUMP_FILES_NUM,
1741                 MLX5_LRO_TIMEOUT_USEC,
1742                 MLX5_CLASS_ARG_NAME,
1743                 MLX5_HP_BUF_SIZE,
1744                 NULL,
1745         };
1746         struct rte_kvargs *kvlist;
1747         int ret = 0;
1748         int i;
1749
1750         if (devargs == NULL)
1751                 return 0;
1752         /* Following UGLY cast is done to pass checkpatch. */
1753         kvlist = rte_kvargs_parse(devargs->args, params);
1754         if (kvlist == NULL) {
1755                 rte_errno = EINVAL;
1756                 return -rte_errno;
1757         }
1758         /* Process parameters. */
1759         for (i = 0; (params[i] != NULL); ++i) {
1760                 if (rte_kvargs_count(kvlist, params[i])) {
1761                         ret = rte_kvargs_process(kvlist, params[i],
1762                                                  mlx5_args_check, config);
1763                         if (ret) {
1764                                 rte_errno = EINVAL;
1765                                 rte_kvargs_free(kvlist);
1766                                 return -rte_errno;
1767                         }
1768                 }
1769         }
1770         rte_kvargs_free(kvlist);
1771         return 0;
1772 }
1773
1774 static struct rte_pci_driver mlx5_driver;
1775
1776 /**
1777  * PMD global initialization.
1778  *
1779  * Independent from individual device, this function initializes global
1780  * per-PMD data structures distinguishing primary and secondary processes.
1781  * Hence, each initialization is called once per a process.
1782  *
1783  * @return
1784  *   0 on success, a negative errno value otherwise and rte_errno is set.
1785  */
1786 static int
1787 mlx5_init_once(void)
1788 {
1789         struct mlx5_shared_data *sd;
1790         struct mlx5_local_data *ld = &mlx5_local_data;
1791         int ret = 0;
1792
1793         if (mlx5_init_shared_data())
1794                 return -rte_errno;
1795         sd = mlx5_shared_data;
1796         MLX5_ASSERT(sd);
1797         rte_spinlock_lock(&sd->lock);
1798         switch (rte_eal_process_type()) {
1799         case RTE_PROC_PRIMARY:
1800                 if (sd->init_done)
1801                         break;
1802                 LIST_INIT(&sd->mem_event_cb_list);
1803                 rte_rwlock_init(&sd->mem_event_rwlock);
1804                 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1805                                                 mlx5_mr_mem_event_cb, NULL);
1806                 ret = mlx5_mp_init_primary(MLX5_MP_NAME,
1807                                            mlx5_mp_primary_handle);
1808                 if (ret)
1809                         goto out;
1810                 sd->init_done = true;
1811                 break;
1812         case RTE_PROC_SECONDARY:
1813                 if (ld->init_done)
1814                         break;
1815                 ret = mlx5_mp_init_secondary(MLX5_MP_NAME,
1816                                              mlx5_mp_secondary_handle);
1817                 if (ret)
1818                         goto out;
1819                 ++sd->secondary_cnt;
1820                 ld->init_done = true;
1821                 break;
1822         default:
1823                 break;
1824         }
1825 out:
1826         rte_spinlock_unlock(&sd->lock);
1827         return ret;
1828 }
1829
1830 /**
1831  * Configures the minimal amount of data to inline into WQE
1832  * while sending packets.
1833  *
1834  * - the txq_inline_min has the maximal priority, if this
1835  *   key is specified in devargs
1836  * - if DevX is enabled the inline mode is queried from the
1837  *   device (HCA attributes and NIC vport context if needed).
1838  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1839  *   and none (0 bytes) for other NICs
1840  *
1841  * @param spawn
1842  *   Verbs device parameters (name, port, switch_info) to spawn.
1843  * @param config
1844  *   Device configuration parameters.
1845  */
1846 static void
1847 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1848                     struct mlx5_dev_config *config)
1849 {
1850         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1851                 /* Application defines size of inlined data explicitly. */
1852                 switch (spawn->pci_dev->id.device_id) {
1853                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1854                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1855                         if (config->txq_inline_min <
1856                                        (int)MLX5_INLINE_HSIZE_L2) {
1857                                 DRV_LOG(DEBUG,
1858                                         "txq_inline_mix aligned to minimal"
1859                                         " ConnectX-4 required value %d",
1860                                         (int)MLX5_INLINE_HSIZE_L2);
1861                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1862                         }
1863                         break;
1864                 }
1865                 goto exit;
1866         }
1867         if (config->hca_attr.eth_net_offloads) {
1868                 /* We have DevX enabled, inline mode queried successfully. */
1869                 switch (config->hca_attr.wqe_inline_mode) {
1870                 case MLX5_CAP_INLINE_MODE_L2:
1871                         /* outer L2 header must be inlined. */
1872                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1873                         goto exit;
1874                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1875                         /* No inline data are required by NIC. */
1876                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1877                         config->hw_vlan_insert =
1878                                 config->hca_attr.wqe_vlan_insert;
1879                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1880                         goto exit;
1881                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1882                         /* inline mode is defined by NIC vport context. */
1883                         if (!config->hca_attr.eth_virt)
1884                                 break;
1885                         switch (config->hca_attr.vport_inline_mode) {
1886                         case MLX5_INLINE_MODE_NONE:
1887                                 config->txq_inline_min =
1888                                         MLX5_INLINE_HSIZE_NONE;
1889                                 goto exit;
1890                         case MLX5_INLINE_MODE_L2:
1891                                 config->txq_inline_min =
1892                                         MLX5_INLINE_HSIZE_L2;
1893                                 goto exit;
1894                         case MLX5_INLINE_MODE_IP:
1895                                 config->txq_inline_min =
1896                                         MLX5_INLINE_HSIZE_L3;
1897                                 goto exit;
1898                         case MLX5_INLINE_MODE_TCP_UDP:
1899                                 config->txq_inline_min =
1900                                         MLX5_INLINE_HSIZE_L4;
1901                                 goto exit;
1902                         case MLX5_INLINE_MODE_INNER_L2:
1903                                 config->txq_inline_min =
1904                                         MLX5_INLINE_HSIZE_INNER_L2;
1905                                 goto exit;
1906                         case MLX5_INLINE_MODE_INNER_IP:
1907                                 config->txq_inline_min =
1908                                         MLX5_INLINE_HSIZE_INNER_L3;
1909                                 goto exit;
1910                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
1911                                 config->txq_inline_min =
1912                                         MLX5_INLINE_HSIZE_INNER_L4;
1913                                 goto exit;
1914                         }
1915                 }
1916         }
1917         /*
1918          * We get here if we are unable to deduce
1919          * inline data size with DevX. Try PCI ID
1920          * to determine old NICs.
1921          */
1922         switch (spawn->pci_dev->id.device_id) {
1923         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1924         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1925         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1926         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1927                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1928                 config->hw_vlan_insert = 0;
1929                 break;
1930         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1931         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1932         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1933         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1934                 /*
1935                  * These NICs support VLAN insertion from WQE and
1936                  * report the wqe_vlan_insert flag. But there is the bug
1937                  * and PFC control may be broken, so disable feature.
1938                  */
1939                 config->hw_vlan_insert = 0;
1940                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1941                 break;
1942         default:
1943                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1944                 break;
1945         }
1946 exit:
1947         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1948 }
1949
1950 /**
1951  * Configures the metadata mask fields in the shared context.
1952  *
1953  * @param [in] dev
1954  *   Pointer to Ethernet device.
1955  */
1956 static void
1957 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1958 {
1959         struct mlx5_priv *priv = dev->data->dev_private;
1960         struct mlx5_ibv_shared *sh = priv->sh;
1961         uint32_t meta, mark, reg_c0;
1962
1963         reg_c0 = ~priv->vport_meta_mask;
1964         switch (priv->config.dv_xmeta_en) {
1965         case MLX5_XMETA_MODE_LEGACY:
1966                 meta = UINT32_MAX;
1967                 mark = MLX5_FLOW_MARK_MASK;
1968                 break;
1969         case MLX5_XMETA_MODE_META16:
1970                 meta = reg_c0 >> rte_bsf32(reg_c0);
1971                 mark = MLX5_FLOW_MARK_MASK;
1972                 break;
1973         case MLX5_XMETA_MODE_META32:
1974                 meta = UINT32_MAX;
1975                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1976                 break;
1977         default:
1978                 meta = 0;
1979                 mark = 0;
1980                 MLX5_ASSERT(false);
1981                 break;
1982         }
1983         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1984                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1985                                  sh->dv_mark_mask, mark);
1986         else
1987                 sh->dv_mark_mask = mark;
1988         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1989                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1990                                  sh->dv_meta_mask, meta);
1991         else
1992                 sh->dv_meta_mask = meta;
1993         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1994                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1995                                  sh->dv_meta_mask, reg_c0);
1996         else
1997                 sh->dv_regc0_mask = reg_c0;
1998         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1999         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2000         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2001         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2002 }
2003
2004 /**
2005  * Allocate page of door-bells and register it using DevX API.
2006  *
2007  * @param [in] dev
2008  *   Pointer to Ethernet device.
2009  *
2010  * @return
2011  *   Pointer to new page on success, NULL otherwise.
2012  */
2013 static struct mlx5_devx_dbr_page *
2014 mlx5_alloc_dbr_page(struct rte_eth_dev *dev)
2015 {
2016         struct mlx5_priv *priv = dev->data->dev_private;
2017         struct mlx5_devx_dbr_page *page;
2018
2019         /* Allocate space for door-bell page and management data. */
2020         page = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_devx_dbr_page),
2021                                  RTE_CACHE_LINE_SIZE, dev->device->numa_node);
2022         if (!page) {
2023                 DRV_LOG(ERR, "port %u cannot allocate dbr page",
2024                         dev->data->port_id);
2025                 return NULL;
2026         }
2027         /* Register allocated memory. */
2028         page->umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, page->dbrs,
2029                                               MLX5_DBR_PAGE_SIZE, 0);
2030         if (!page->umem) {
2031                 DRV_LOG(ERR, "port %u cannot umem reg dbr page",
2032                         dev->data->port_id);
2033                 rte_free(page);
2034                 return NULL;
2035         }
2036         return page;
2037 }
2038
2039 /**
2040  * Find the next available door-bell, allocate new page if needed.
2041  *
2042  * @param [in] dev
2043  *   Pointer to Ethernet device.
2044  * @param [out] dbr_page
2045  *   Door-bell page containing the page data.
2046  *
2047  * @return
2048  *   Door-bell address offset on success, a negative error value otherwise.
2049  */
2050 int64_t
2051 mlx5_get_dbr(struct rte_eth_dev *dev, struct mlx5_devx_dbr_page **dbr_page)
2052 {
2053         struct mlx5_priv *priv = dev->data->dev_private;
2054         struct mlx5_devx_dbr_page *page = NULL;
2055         uint32_t i, j;
2056
2057         LIST_FOREACH(page, &priv->dbrpgs, next)
2058                 if (page->dbr_count < MLX5_DBR_PER_PAGE)
2059                         break;
2060         if (!page) { /* No page with free door-bell exists. */
2061                 page = mlx5_alloc_dbr_page(dev);
2062                 if (!page) /* Failed to allocate new page. */
2063                         return (-1);
2064                 LIST_INSERT_HEAD(&priv->dbrpgs, page, next);
2065         }
2066         /* Loop to find bitmap part with clear bit. */
2067         for (i = 0;
2068              i < MLX5_DBR_BITMAP_SIZE && page->dbr_bitmap[i] == UINT64_MAX;
2069              i++)
2070                 ; /* Empty. */
2071         /* Find the first clear bit. */
2072         j = rte_bsf64(~page->dbr_bitmap[i]);
2073         MLX5_ASSERT(i < (MLX5_DBR_PER_PAGE / 64));
2074         page->dbr_bitmap[i] |= (1 << j);
2075         page->dbr_count++;
2076         *dbr_page = page;
2077         return (((i * 64) + j) * sizeof(uint64_t));
2078 }
2079
2080 /**
2081  * Release a door-bell record.
2082  *
2083  * @param [in] dev
2084  *   Pointer to Ethernet device.
2085  * @param [in] umem_id
2086  *   UMEM ID of page containing the door-bell record to release.
2087  * @param [in] offset
2088  *   Offset of door-bell record in page.
2089  *
2090  * @return
2091  *   0 on success, a negative error value otherwise.
2092  */
2093 int32_t
2094 mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id, uint64_t offset)
2095 {
2096         struct mlx5_priv *priv = dev->data->dev_private;
2097         struct mlx5_devx_dbr_page *page = NULL;
2098         int ret = 0;
2099
2100         LIST_FOREACH(page, &priv->dbrpgs, next)
2101                 /* Find the page this address belongs to. */
2102                 if (page->umem->umem_id == umem_id)
2103                         break;
2104         if (!page)
2105                 return -EINVAL;
2106         page->dbr_count--;
2107         if (!page->dbr_count) {
2108                 /* Page not used, free it and remove from list. */
2109                 LIST_REMOVE(page, next);
2110                 if (page->umem)
2111                         ret = -mlx5_glue->devx_umem_dereg(page->umem);
2112                 rte_free(page);
2113         } else {
2114                 /* Mark in bitmap that this door-bell is not in use. */
2115                 offset /= MLX5_DBR_SIZE;
2116                 int i = offset / 64;
2117                 int j = offset % 64;
2118
2119                 page->dbr_bitmap[i] &= ~(1 << j);
2120         }
2121         return ret;
2122 }
2123
2124 int
2125 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2126 {
2127         static const char *const dynf_names[] = {
2128                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2129                 RTE_MBUF_DYNFLAG_METADATA_NAME
2130         };
2131         unsigned int i;
2132
2133         if (n < RTE_DIM(dynf_names))
2134                 return -ENOMEM;
2135         for (i = 0; i < RTE_DIM(dynf_names); i++) {
2136                 if (names[i] == NULL)
2137                         return -EINVAL;
2138                 strcpy(names[i], dynf_names[i]);
2139         }
2140         return RTE_DIM(dynf_names);
2141 }
2142
2143 /**
2144  * Check sibling device configurations.
2145  *
2146  * Sibling devices sharing the Infiniband device context
2147  * should have compatible configurations. This regards
2148  * representors and bonding slaves.
2149  *
2150  * @param priv
2151  *   Private device descriptor.
2152  * @param config
2153  *   Configuration of the device is going to be created.
2154  *
2155  * @return
2156  *   0 on success, EINVAL otherwise
2157  */
2158 static int
2159 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2160                               struct mlx5_dev_config *config)
2161 {
2162         struct mlx5_ibv_shared *sh = priv->sh;
2163         struct mlx5_dev_config *sh_conf = NULL;
2164         uint16_t port_id;
2165
2166         MLX5_ASSERT(sh);
2167         /* Nothing to compare for the single/first device. */
2168         if (sh->refcnt == 1)
2169                 return 0;
2170         /* Find the device with shared context. */
2171         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2172                 struct mlx5_priv *opriv =
2173                         rte_eth_devices[port_id].data->dev_private;
2174
2175                 if (opriv && opriv != priv && opriv->sh == sh) {
2176                         sh_conf = &opriv->config;
2177                         break;
2178                 }
2179         }
2180         if (!sh_conf)
2181                 return 0;
2182         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2183                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2184                              " for shared %s context", sh->ibdev_name);
2185                 rte_errno = EINVAL;
2186                 return rte_errno;
2187         }
2188         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2189                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2190                              " for shared %s context", sh->ibdev_name);
2191                 rte_errno = EINVAL;
2192                 return rte_errno;
2193         }
2194         return 0;
2195 }
2196 /**
2197  * Spawn an Ethernet device from Verbs information.
2198  *
2199  * @param dpdk_dev
2200  *   Backing DPDK device.
2201  * @param spawn
2202  *   Verbs device parameters (name, port, switch_info) to spawn.
2203  * @param config
2204  *   Device configuration parameters.
2205  *
2206  * @return
2207  *   A valid Ethernet device object on success, NULL otherwise and rte_errno
2208  *   is set. The following errors are defined:
2209  *
2210  *   EBUSY: device is not supposed to be spawned.
2211  *   EEXIST: device is already spawned
2212  */
2213 static struct rte_eth_dev *
2214 mlx5_dev_spawn(struct rte_device *dpdk_dev,
2215                struct mlx5_dev_spawn_data *spawn,
2216                struct mlx5_dev_config config)
2217 {
2218         const struct mlx5_switch_info *switch_info = &spawn->info;
2219         struct mlx5_ibv_shared *sh = NULL;
2220         struct ibv_port_attr port_attr;
2221         struct mlx5dv_context dv_attr = { .comp_mask = 0 };
2222         struct rte_eth_dev *eth_dev = NULL;
2223         struct mlx5_priv *priv = NULL;
2224         int err = 0;
2225         unsigned int hw_padding = 0;
2226         unsigned int mps;
2227         unsigned int cqe_comp;
2228         unsigned int cqe_pad = 0;
2229         unsigned int tunnel_en = 0;
2230         unsigned int mpls_en = 0;
2231         unsigned int swp = 0;
2232         unsigned int mprq = 0;
2233         unsigned int mprq_min_stride_size_n = 0;
2234         unsigned int mprq_max_stride_size_n = 0;
2235         unsigned int mprq_min_stride_num_n = 0;
2236         unsigned int mprq_max_stride_num_n = 0;
2237         struct rte_ether_addr mac;
2238         char name[RTE_ETH_NAME_MAX_LEN];
2239         int own_domain_id = 0;
2240         uint16_t port_id;
2241         unsigned int i;
2242 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
2243         struct mlx5dv_devx_port devx_port = { .comp_mask = 0 };
2244 #endif
2245
2246         /* Determine if this port representor is supposed to be spawned. */
2247         if (switch_info->representor && dpdk_dev->devargs) {
2248                 struct rte_eth_devargs eth_da;
2249
2250                 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, &eth_da);
2251                 if (err) {
2252                         rte_errno = -err;
2253                         DRV_LOG(ERR, "failed to process device arguments: %s",
2254                                 strerror(rte_errno));
2255                         return NULL;
2256                 }
2257                 for (i = 0; i < eth_da.nb_representor_ports; ++i)
2258                         if (eth_da.representor_ports[i] ==
2259                             (uint16_t)switch_info->port_name)
2260                                 break;
2261                 if (i == eth_da.nb_representor_ports) {
2262                         rte_errno = EBUSY;
2263                         return NULL;
2264                 }
2265         }
2266         /* Build device name. */
2267         if (spawn->pf_bond <  0) {
2268                 /* Single device. */
2269                 if (!switch_info->representor)
2270                         strlcpy(name, dpdk_dev->name, sizeof(name));
2271                 else
2272                         snprintf(name, sizeof(name), "%s_representor_%u",
2273                                  dpdk_dev->name, switch_info->port_name);
2274         } else {
2275                 /* Bonding device. */
2276                 if (!switch_info->representor)
2277                         snprintf(name, sizeof(name), "%s_%s",
2278                                  dpdk_dev->name, spawn->ibv_dev->name);
2279                 else
2280                         snprintf(name, sizeof(name), "%s_%s_representor_%u",
2281                                  dpdk_dev->name, spawn->ibv_dev->name,
2282                                  switch_info->port_name);
2283         }
2284         /* check if the device is already spawned */
2285         if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
2286                 rte_errno = EEXIST;
2287                 return NULL;
2288         }
2289         DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
2290         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
2291                 struct mlx5_mp_id mp_id;
2292
2293                 eth_dev = rte_eth_dev_attach_secondary(name);
2294                 if (eth_dev == NULL) {
2295                         DRV_LOG(ERR, "can not attach rte ethdev");
2296                         rte_errno = ENOMEM;
2297                         return NULL;
2298                 }
2299                 eth_dev->device = dpdk_dev;
2300                 eth_dev->dev_ops = &mlx5_dev_sec_ops;
2301                 err = mlx5_proc_priv_init(eth_dev);
2302                 if (err)
2303                         return NULL;
2304                 mp_id.port_id = eth_dev->data->port_id;
2305                 strlcpy(mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);
2306                 /* Receive command fd from primary process */
2307                 err = mlx5_mp_req_verbs_cmd_fd(&mp_id);
2308                 if (err < 0)
2309                         return NULL;
2310                 /* Remap UAR for Tx queues. */
2311                 err = mlx5_tx_uar_init_secondary(eth_dev, err);
2312                 if (err)
2313                         return NULL;
2314                 /*
2315                  * Ethdev pointer is still required as input since
2316                  * the primary device is not accessible from the
2317                  * secondary process.
2318                  */
2319                 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev);
2320                 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev);
2321                 return eth_dev;
2322         }
2323         /*
2324          * Some parameters ("tx_db_nc" in particularly) are needed in
2325          * advance to create dv/verbs device context. We proceed the
2326          * devargs here to get ones, and later proceed devargs again
2327          * to override some hardware settings.
2328          */
2329         err = mlx5_args(&config, dpdk_dev->devargs);
2330         if (err) {
2331                 err = rte_errno;
2332                 DRV_LOG(ERR, "failed to process device arguments: %s",
2333                         strerror(rte_errno));
2334                 goto error;
2335         }
2336         sh = mlx5_alloc_shared_ibctx(spawn, &config);
2337         if (!sh)
2338                 return NULL;
2339         config.devx = sh->devx;
2340 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR
2341         config.dest_tir = 1;
2342 #endif
2343 #ifdef HAVE_IBV_MLX5_MOD_SWP
2344         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
2345 #endif
2346         /*
2347          * Multi-packet send is supported by ConnectX-4 Lx PF as well
2348          * as all ConnectX-5 devices.
2349          */
2350 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2351         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
2352 #endif
2353 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
2354         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
2355 #endif
2356         mlx5_glue->dv_query_device(sh->ctx, &dv_attr);
2357         if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
2358                 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
2359                         DRV_LOG(DEBUG, "enhanced MPW is supported");
2360                         mps = MLX5_MPW_ENHANCED;
2361                 } else {
2362                         DRV_LOG(DEBUG, "MPW is supported");
2363                         mps = MLX5_MPW;
2364                 }
2365         } else {
2366                 DRV_LOG(DEBUG, "MPW isn't supported");
2367                 mps = MLX5_MPW_DISABLED;
2368         }
2369 #ifdef HAVE_IBV_MLX5_MOD_SWP
2370         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
2371                 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
2372         DRV_LOG(DEBUG, "SWP support: %u", swp);
2373 #endif
2374         config.swp = !!swp;
2375 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
2376         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
2377                 struct mlx5dv_striding_rq_caps mprq_caps =
2378                         dv_attr.striding_rq_caps;
2379
2380                 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
2381                         mprq_caps.min_single_stride_log_num_of_bytes);
2382                 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
2383                         mprq_caps.max_single_stride_log_num_of_bytes);
2384                 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
2385                         mprq_caps.min_single_wqe_log_num_of_strides);
2386                 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
2387                         mprq_caps.max_single_wqe_log_num_of_strides);
2388                 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
2389                         mprq_caps.supported_qpts);
2390                 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
2391                 mprq = 1;
2392                 mprq_min_stride_size_n =
2393                         mprq_caps.min_single_stride_log_num_of_bytes;
2394                 mprq_max_stride_size_n =
2395                         mprq_caps.max_single_stride_log_num_of_bytes;
2396                 mprq_min_stride_num_n =
2397                         mprq_caps.min_single_wqe_log_num_of_strides;
2398                 mprq_max_stride_num_n =
2399                         mprq_caps.max_single_wqe_log_num_of_strides;
2400         }
2401 #endif
2402         if (RTE_CACHE_LINE_SIZE == 128 &&
2403             !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
2404                 cqe_comp = 0;
2405         else
2406                 cqe_comp = 1;
2407         config.cqe_comp = cqe_comp;
2408 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
2409         /* Whether device supports 128B Rx CQE padding. */
2410         cqe_pad = RTE_CACHE_LINE_SIZE == 128 &&
2411                   (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD);
2412 #endif
2413 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2414         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
2415                 tunnel_en = ((dv_attr.tunnel_offloads_caps &
2416                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
2417                              (dv_attr.tunnel_offloads_caps &
2418                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) &&
2419                              (dv_attr.tunnel_offloads_caps &
2420                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE));
2421         }
2422         DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
2423                 tunnel_en ? "" : "not ");
2424 #else
2425         DRV_LOG(WARNING,
2426                 "tunnel offloading disabled due to old OFED/rdma-core version");
2427 #endif
2428         config.tunnel_en = tunnel_en;
2429 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
2430         mpls_en = ((dv_attr.tunnel_offloads_caps &
2431                     MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
2432                    (dv_attr.tunnel_offloads_caps &
2433                     MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
2434         DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
2435                 mpls_en ? "" : "not ");
2436 #else
2437         DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
2438                 " old OFED/rdma-core version or firmware configuration");
2439 #endif
2440         config.mpls_en = mpls_en;
2441         /* Check port status. */
2442         err = mlx5_glue->query_port(sh->ctx, spawn->ibv_port, &port_attr);
2443         if (err) {
2444                 DRV_LOG(ERR, "port query failed: %s", strerror(err));
2445                 goto error;
2446         }
2447         if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
2448                 DRV_LOG(ERR, "port is not configured in Ethernet mode");
2449                 err = EINVAL;
2450                 goto error;
2451         }
2452         if (port_attr.state != IBV_PORT_ACTIVE)
2453                 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)",
2454                         mlx5_glue->port_state_str(port_attr.state),
2455                         port_attr.state);
2456         /* Allocate private eth device data. */
2457         priv = rte_zmalloc("ethdev private structure",
2458                            sizeof(*priv),
2459                            RTE_CACHE_LINE_SIZE);
2460         if (priv == NULL) {
2461                 DRV_LOG(ERR, "priv allocation failure");
2462                 err = ENOMEM;
2463                 goto error;
2464         }
2465         priv->sh = sh;
2466         priv->ibv_port = spawn->ibv_port;
2467         priv->pci_dev = spawn->pci_dev;
2468         priv->mtu = RTE_ETHER_MTU;
2469         priv->mp_id.port_id = port_id;
2470         strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);
2471 #ifndef RTE_ARCH_64
2472         /* Initialize UAR access locks for 32bit implementations. */
2473         rte_spinlock_init(&priv->uar_lock_cq);
2474         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
2475                 rte_spinlock_init(&priv->uar_lock[i]);
2476 #endif
2477         /* Some internal functions rely on Netlink sockets, open them now. */
2478         priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA);
2479         priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE);
2480         priv->representor = !!switch_info->representor;
2481         priv->master = !!switch_info->master;
2482         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
2483         priv->vport_meta_tag = 0;
2484         priv->vport_meta_mask = 0;
2485         priv->pf_bond = spawn->pf_bond;
2486 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
2487         /*
2488          * The DevX port query API is implemented. E-Switch may use
2489          * either vport or reg_c[0] metadata register to match on
2490          * vport index. The engaged part of metadata register is
2491          * defined by mask.
2492          */
2493         if (switch_info->representor || switch_info->master) {
2494                 devx_port.comp_mask = MLX5DV_DEVX_PORT_VPORT |
2495                                       MLX5DV_DEVX_PORT_MATCH_REG_C_0;
2496                 err = mlx5_glue->devx_port_query(sh->ctx, spawn->ibv_port,
2497                                                  &devx_port);
2498                 if (err) {
2499                         DRV_LOG(WARNING,
2500                                 "can't query devx port %d on device %s",
2501                                 spawn->ibv_port, spawn->ibv_dev->name);
2502                         devx_port.comp_mask = 0;
2503                 }
2504         }
2505         if (devx_port.comp_mask & MLX5DV_DEVX_PORT_MATCH_REG_C_0) {
2506                 priv->vport_meta_tag = devx_port.reg_c_0.value;
2507                 priv->vport_meta_mask = devx_port.reg_c_0.mask;
2508                 if (!priv->vport_meta_mask) {
2509                         DRV_LOG(ERR, "vport zero mask for port %d"
2510                                      " on bonding device %s",
2511                                      spawn->ibv_port, spawn->ibv_dev->name);
2512                         err = ENOTSUP;
2513                         goto error;
2514                 }
2515                 if (priv->vport_meta_tag & ~priv->vport_meta_mask) {
2516                         DRV_LOG(ERR, "invalid vport tag for port %d"
2517                                      " on bonding device %s",
2518                                      spawn->ibv_port, spawn->ibv_dev->name);
2519                         err = ENOTSUP;
2520                         goto error;
2521                 }
2522         }
2523         if (devx_port.comp_mask & MLX5DV_DEVX_PORT_VPORT) {
2524                 priv->vport_id = devx_port.vport_num;
2525         } else if (spawn->pf_bond >= 0) {
2526                 DRV_LOG(ERR, "can't deduce vport index for port %d"
2527                              " on bonding device %s",
2528                              spawn->ibv_port, spawn->ibv_dev->name);
2529                 err = ENOTSUP;
2530                 goto error;
2531         } else {
2532                 /* Suppose vport index in compatible way. */
2533                 priv->vport_id = switch_info->representor ?
2534                                  switch_info->port_name + 1 : -1;
2535         }
2536 #else
2537         /*
2538          * Kernel/rdma_core support single E-Switch per PF configurations
2539          * only and vport_id field contains the vport index for
2540          * associated VF, which is deduced from representor port name.
2541          * For example, let's have the IB device port 10, it has
2542          * attached network device eth0, which has port name attribute
2543          * pf0vf2, we can deduce the VF number as 2, and set vport index
2544          * as 3 (2+1). This assigning schema should be changed if the
2545          * multiple E-Switch instances per PF configurations or/and PCI
2546          * subfunctions are added.
2547          */
2548         priv->vport_id = switch_info->representor ?
2549                          switch_info->port_name + 1 : -1;
2550 #endif
2551         /* representor_id field keeps the unmodified VF index. */
2552         priv->representor_id = switch_info->representor ?
2553                                switch_info->port_name : -1;
2554         /*
2555          * Look for sibling devices in order to reuse their switch domain
2556          * if any, otherwise allocate one.
2557          */
2558         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2559                 const struct mlx5_priv *opriv =
2560                         rte_eth_devices[port_id].data->dev_private;
2561
2562                 if (!opriv ||
2563                     opriv->sh != priv->sh ||
2564                         opriv->domain_id ==
2565                         RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
2566                         continue;
2567                 priv->domain_id = opriv->domain_id;
2568                 break;
2569         }
2570         if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
2571                 err = rte_eth_switch_domain_alloc(&priv->domain_id);
2572                 if (err) {
2573                         err = rte_errno;
2574                         DRV_LOG(ERR, "unable to allocate switch domain: %s",
2575                                 strerror(rte_errno));
2576                         goto error;
2577                 }
2578                 own_domain_id = 1;
2579         }
2580         /* Override some values set by hardware configuration. */
2581         mlx5_args(&config, dpdk_dev->devargs);
2582         err = mlx5_dev_check_sibling_config(priv, &config);
2583         if (err)
2584                 goto error;
2585         config.hw_csum = !!(sh->device_attr.device_cap_flags_ex &
2586                             IBV_DEVICE_RAW_IP_CSUM);
2587         DRV_LOG(DEBUG, "checksum offloading is %ssupported",
2588                 (config.hw_csum ? "" : "not "));
2589 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \
2590         !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
2591         DRV_LOG(DEBUG, "counters are not supported");
2592 #endif
2593 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR)
2594         if (config.dv_flow_en) {
2595                 DRV_LOG(WARNING, "DV flow is not supported");
2596                 config.dv_flow_en = 0;
2597         }
2598 #endif
2599         config.ind_table_max_size =
2600                 sh->device_attr.rss_caps.max_rwq_indirection_table_size;
2601         /*
2602          * Remove this check once DPDK supports larger/variable
2603          * indirection tables.
2604          */
2605         if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
2606                 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
2607         DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
2608                 config.ind_table_max_size);
2609         config.hw_vlan_strip = !!(sh->device_attr.raw_packet_caps &
2610                                   IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
2611         DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
2612                 (config.hw_vlan_strip ? "" : "not "));
2613         config.hw_fcs_strip = !!(sh->device_attr.raw_packet_caps &
2614                                  IBV_RAW_PACKET_CAP_SCATTER_FCS);
2615         DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
2616                 (config.hw_fcs_strip ? "" : "not "));
2617 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
2618         hw_padding = !!sh->device_attr.rx_pad_end_addr_align;
2619 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
2620         hw_padding = !!(sh->device_attr.device_cap_flags_ex &
2621                         IBV_DEVICE_PCI_WRITE_END_PADDING);
2622 #endif
2623         if (config.hw_padding && !hw_padding) {
2624                 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
2625                 config.hw_padding = 0;
2626         } else if (config.hw_padding) {
2627                 DRV_LOG(DEBUG, "Rx end alignment padding is enabled");
2628         }
2629         config.tso = (sh->device_attr.tso_caps.max_tso > 0 &&
2630                       (sh->device_attr.tso_caps.supported_qpts &
2631                        (1 << IBV_QPT_RAW_PACKET)));
2632         if (config.tso)
2633                 config.tso_max_payload_sz = sh->device_attr.tso_caps.max_tso;
2634         /*
2635          * MPW is disabled by default, while the Enhanced MPW is enabled
2636          * by default.
2637          */
2638         if (config.mps == MLX5_ARG_UNSET)
2639                 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED :
2640                                                           MLX5_MPW_DISABLED;
2641         else
2642                 config.mps = config.mps ? mps : MLX5_MPW_DISABLED;
2643         DRV_LOG(INFO, "%sMPS is %s",
2644                 config.mps == MLX5_MPW_ENHANCED ? "enhanced " :
2645                 config.mps == MLX5_MPW ? "legacy " : "",
2646                 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
2647         if (config.cqe_comp && !cqe_comp) {
2648                 DRV_LOG(WARNING, "Rx CQE compression isn't supported");
2649                 config.cqe_comp = 0;
2650         }
2651         if (config.cqe_pad && !cqe_pad) {
2652                 DRV_LOG(WARNING, "Rx CQE padding isn't supported");
2653                 config.cqe_pad = 0;
2654         } else if (config.cqe_pad) {
2655                 DRV_LOG(INFO, "Rx CQE padding is enabled");
2656         }
2657         if (config.devx) {
2658                 priv->counter_fallback = 0;
2659                 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config.hca_attr);
2660                 if (err) {
2661                         err = -err;
2662                         goto error;
2663                 }
2664                 if (!config.hca_attr.flow_counters_dump)
2665                         priv->counter_fallback = 1;
2666 #ifndef HAVE_IBV_DEVX_ASYNC
2667                 priv->counter_fallback = 1;
2668 #endif
2669                 if (priv->counter_fallback)
2670                         DRV_LOG(INFO, "Use fall-back DV counter management");
2671                 /* Check for LRO support. */
2672                 if (config.dest_tir && config.hca_attr.lro_cap &&
2673                     config.dv_flow_en) {
2674                         /* TBD check tunnel lro caps. */
2675                         config.lro.supported = config.hca_attr.lro_cap;
2676                         DRV_LOG(DEBUG, "Device supports LRO");
2677                         /*
2678                          * If LRO timeout is not configured by application,
2679                          * use the minimal supported value.
2680                          */
2681                         if (!config.lro.timeout)
2682                                 config.lro.timeout =
2683                                 config.hca_attr.lro_timer_supported_periods[0];
2684                         DRV_LOG(DEBUG, "LRO session timeout set to %d usec",
2685                                 config.lro.timeout);
2686                 }
2687 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER)
2688                 if (config.hca_attr.qos.sup && config.hca_attr.qos.srtcm_sup &&
2689                     config.dv_flow_en) {
2690                         uint8_t reg_c_mask =
2691                                 config.hca_attr.qos.flow_meter_reg_c_ids;
2692                         /*
2693                          * Meter needs two REG_C's for color match and pre-sfx
2694                          * flow match. Here get the REG_C for color match.
2695                          * REG_C_0 and REG_C_1 is reserved for metadata feature.
2696                          */
2697                         reg_c_mask &= 0xfc;
2698                         if (__builtin_popcount(reg_c_mask) < 1) {
2699                                 priv->mtr_en = 0;
2700                                 DRV_LOG(WARNING, "No available register for"
2701                                         " meter.");
2702                         } else {
2703                                 priv->mtr_color_reg = ffs(reg_c_mask) - 1 +
2704                                                       REG_C_0;
2705                                 priv->mtr_en = 1;
2706                                 priv->mtr_reg_share =
2707                                       config.hca_attr.qos.flow_meter_reg_share;
2708                                 DRV_LOG(DEBUG, "The REG_C meter uses is %d",
2709                                         priv->mtr_color_reg);
2710                         }
2711                 }
2712 #endif
2713         }
2714         if (config.mprq.enabled && mprq) {
2715                 if (config.mprq.stride_num_n &&
2716                     (config.mprq.stride_num_n > mprq_max_stride_num_n ||
2717                      config.mprq.stride_num_n < mprq_min_stride_num_n)) {
2718                         config.mprq.stride_num_n =
2719                                 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
2720                                                 mprq_min_stride_num_n),
2721                                         mprq_max_stride_num_n);
2722                         DRV_LOG(WARNING,
2723                                 "the number of strides"
2724                                 " for Multi-Packet RQ is out of range,"
2725                                 " setting default value (%u)",
2726                                 1 << config.mprq.stride_num_n);
2727                 }
2728                 if (config.mprq.stride_size_n &&
2729                     (config.mprq.stride_size_n > mprq_max_stride_size_n ||
2730                      config.mprq.stride_size_n < mprq_min_stride_size_n)) {
2731                         config.mprq.stride_size_n =
2732                                 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N,
2733                                                 mprq_min_stride_size_n),
2734                                         mprq_max_stride_size_n);
2735                         DRV_LOG(WARNING,
2736                                 "the size of a stride"
2737                                 " for Multi-Packet RQ is out of range,"
2738                                 " setting default value (%u)",
2739                                 1 << config.mprq.stride_size_n);
2740                 }
2741                 config.mprq.min_stride_size_n = mprq_min_stride_size_n;
2742                 config.mprq.max_stride_size_n = mprq_max_stride_size_n;
2743         } else if (config.mprq.enabled && !mprq) {
2744                 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
2745                 config.mprq.enabled = 0;
2746         }
2747         if (config.max_dump_files_num == 0)
2748                 config.max_dump_files_num = 128;
2749         eth_dev = rte_eth_dev_allocate(name);
2750         if (eth_dev == NULL) {
2751                 DRV_LOG(ERR, "can not allocate rte ethdev");
2752                 err = ENOMEM;
2753                 goto error;
2754         }
2755         /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */
2756         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2757         if (priv->representor) {
2758                 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
2759                 eth_dev->data->representor_id = priv->representor_id;
2760         }
2761         /*
2762          * Store associated network device interface index. This index
2763          * is permanent throughout the lifetime of device. So, we may store
2764          * the ifindex here and use the cached value further.
2765          */
2766         MLX5_ASSERT(spawn->ifindex);
2767         priv->if_index = spawn->ifindex;
2768         eth_dev->data->dev_private = priv;
2769         priv->dev_data = eth_dev->data;
2770         eth_dev->data->mac_addrs = priv->mac;
2771         eth_dev->device = dpdk_dev;
2772         /* Configure the first MAC address by default. */
2773         if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
2774                 DRV_LOG(ERR,
2775                         "port %u cannot get MAC address, is mlx5_en"
2776                         " loaded? (errno: %s)",
2777                         eth_dev->data->port_id, strerror(rte_errno));
2778                 err = ENODEV;
2779                 goto error;
2780         }
2781         DRV_LOG(INFO,
2782                 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
2783                 eth_dev->data->port_id,
2784                 mac.addr_bytes[0], mac.addr_bytes[1],
2785                 mac.addr_bytes[2], mac.addr_bytes[3],
2786                 mac.addr_bytes[4], mac.addr_bytes[5]);
2787 #ifdef RTE_LIBRTE_MLX5_DEBUG
2788         {
2789                 char ifname[IF_NAMESIZE];
2790
2791                 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
2792                         DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
2793                                 eth_dev->data->port_id, ifname);
2794                 else
2795                         DRV_LOG(DEBUG, "port %u ifname is unknown",
2796                                 eth_dev->data->port_id);
2797         }
2798 #endif
2799         /* Get actual MTU if possible. */
2800         err = mlx5_get_mtu(eth_dev, &priv->mtu);
2801         if (err) {
2802                 err = rte_errno;
2803                 goto error;
2804         }
2805         DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
2806                 priv->mtu);
2807         /* Initialize burst functions to prevent crashes before link-up. */
2808         eth_dev->rx_pkt_burst = removed_rx_burst;
2809         eth_dev->tx_pkt_burst = removed_tx_burst;
2810         eth_dev->dev_ops = &mlx5_dev_ops;
2811         /* Register MAC address. */
2812         claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
2813         if (config.vf && config.vf_nl_en)
2814                 mlx5_nl_mac_addr_sync(priv->nl_socket_route,
2815                                       mlx5_ifindex(eth_dev),
2816                                       eth_dev->data->mac_addrs,
2817                                       MLX5_MAX_MAC_ADDRESSES);
2818         TAILQ_INIT(&priv->flows);
2819         TAILQ_INIT(&priv->ctrl_flows);
2820         TAILQ_INIT(&priv->flow_meters);
2821         TAILQ_INIT(&priv->flow_meter_profiles);
2822         /* Hint libmlx5 to use PMD allocator for data plane resources */
2823         struct mlx5dv_ctx_allocators alctr = {
2824                 .alloc = &mlx5_alloc_verbs_buf,
2825                 .free = &mlx5_free_verbs_buf,
2826                 .data = priv,
2827         };
2828         mlx5_glue->dv_set_context_attr(sh->ctx,
2829                                        MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
2830                                        (void *)((uintptr_t)&alctr));
2831         /* Bring Ethernet device up. */
2832         DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
2833                 eth_dev->data->port_id);
2834         mlx5_set_link_up(eth_dev);
2835         /*
2836          * Even though the interrupt handler is not installed yet,
2837          * interrupts will still trigger on the async_fd from
2838          * Verbs context returned by ibv_open_device().
2839          */
2840         mlx5_link_update(eth_dev, 0);
2841 #ifdef HAVE_MLX5DV_DR_ESWITCH
2842         if (!(config.hca_attr.eswitch_manager && config.dv_flow_en &&
2843               (switch_info->representor || switch_info->master)))
2844                 config.dv_esw_en = 0;
2845 #else
2846         config.dv_esw_en = 0;
2847 #endif
2848         /* Detect minimal data bytes to inline. */
2849         mlx5_set_min_inline(spawn, &config);
2850         /* Store device configuration on private structure. */
2851         priv->config = config;
2852         /* Create context for virtual machine VLAN workaround. */
2853         priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex);
2854         if (config.dv_flow_en) {
2855                 err = mlx5_alloc_shared_dr(priv);
2856                 if (err)
2857                         goto error;
2858                 /*
2859                  * RSS id is shared with meter flow id. Meter flow id can only
2860                  * use the 24 MSB of the register.
2861                  */
2862                 priv->qrss_id_pool = mlx5_flow_id_pool_alloc(UINT32_MAX >>
2863                                      MLX5_MTR_COLOR_BITS);
2864                 if (!priv->qrss_id_pool) {
2865                         DRV_LOG(ERR, "can't create flow id pool");
2866                         err = ENOMEM;
2867                         goto error;
2868                 }
2869         }
2870         /* Supported Verbs flow priority number detection. */
2871         err = mlx5_flow_discover_priorities(eth_dev);
2872         if (err < 0) {
2873                 err = -err;
2874                 goto error;
2875         }
2876         priv->config.flow_prio = err;
2877         if (!priv->config.dv_esw_en &&
2878             priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2879                 DRV_LOG(WARNING, "metadata mode %u is not supported "
2880                                  "(no E-Switch)", priv->config.dv_xmeta_en);
2881                 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY;
2882         }
2883         mlx5_set_metadata_mask(eth_dev);
2884         if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
2885             !priv->sh->dv_regc0_mask) {
2886                 DRV_LOG(ERR, "metadata mode %u is not supported "
2887                              "(no metadata reg_c[0] is available)",
2888                              priv->config.dv_xmeta_en);
2889                         err = ENOTSUP;
2890                         goto error;
2891         }
2892         /*
2893          * Allocate the buffer for flow creating, just once.
2894          * The allocation must be done before any flow creating.
2895          */
2896         mlx5_flow_alloc_intermediate(eth_dev);
2897         /* Query availibility of metadata reg_c's. */
2898         err = mlx5_flow_discover_mreg_c(eth_dev);
2899         if (err < 0) {
2900                 err = -err;
2901                 goto error;
2902         }
2903         if (!mlx5_flow_ext_mreg_supported(eth_dev)) {
2904                 DRV_LOG(DEBUG,
2905                         "port %u extensive metadata register is not supported",
2906                         eth_dev->data->port_id);
2907                 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2908                         DRV_LOG(ERR, "metadata mode %u is not supported "
2909                                      "(no metadata registers available)",
2910                                      priv->config.dv_xmeta_en);
2911                         err = ENOTSUP;
2912                         goto error;
2913                 }
2914         }
2915         if (priv->config.dv_flow_en &&
2916             priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
2917             mlx5_flow_ext_mreg_supported(eth_dev) &&
2918             priv->sh->dv_regc0_mask) {
2919                 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME,
2920                                                       MLX5_FLOW_MREG_HTABLE_SZ);
2921                 if (!priv->mreg_cp_tbl) {
2922                         err = ENOMEM;
2923                         goto error;
2924                 }
2925         }
2926         return eth_dev;
2927 error:
2928         if (priv) {
2929                 if (priv->mreg_cp_tbl)
2930                         mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
2931                 if (priv->sh)
2932                         mlx5_free_shared_dr(priv);
2933                 if (priv->nl_socket_route >= 0)
2934                         close(priv->nl_socket_route);
2935                 if (priv->nl_socket_rdma >= 0)
2936                         close(priv->nl_socket_rdma);
2937                 if (priv->vmwa_context)
2938                         mlx5_vlan_vmwa_exit(priv->vmwa_context);
2939                 if (priv->qrss_id_pool)
2940                         mlx5_flow_id_pool_release(priv->qrss_id_pool);
2941                 if (own_domain_id)
2942                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
2943                 rte_free(priv);
2944                 if (eth_dev != NULL)
2945                         eth_dev->data->dev_private = NULL;
2946         }
2947         if (eth_dev != NULL) {
2948                 /* mac_addrs must not be freed alone because part of dev_private */
2949                 eth_dev->data->mac_addrs = NULL;
2950                 rte_eth_dev_release_port(eth_dev);
2951         }
2952         if (sh)
2953                 mlx5_free_shared_ibctx(sh);
2954         MLX5_ASSERT(err > 0);
2955         rte_errno = err;
2956         return NULL;
2957 }
2958
2959 /**
2960  * Comparison callback to sort device data.
2961  *
2962  * This is meant to be used with qsort().
2963  *
2964  * @param a[in]
2965  *   Pointer to pointer to first data object.
2966  * @param b[in]
2967  *   Pointer to pointer to second data object.
2968  *
2969  * @return
2970  *   0 if both objects are equal, less than 0 if the first argument is less
2971  *   than the second, greater than 0 otherwise.
2972  */
2973 static int
2974 mlx5_dev_spawn_data_cmp(const void *a, const void *b)
2975 {
2976         const struct mlx5_switch_info *si_a =
2977                 &((const struct mlx5_dev_spawn_data *)a)->info;
2978         const struct mlx5_switch_info *si_b =
2979                 &((const struct mlx5_dev_spawn_data *)b)->info;
2980         int ret;
2981
2982         /* Master device first. */
2983         ret = si_b->master - si_a->master;
2984         if (ret)
2985                 return ret;
2986         /* Then representor devices. */
2987         ret = si_b->representor - si_a->representor;
2988         if (ret)
2989                 return ret;
2990         /* Unidentified devices come last in no specific order. */
2991         if (!si_a->representor)
2992                 return 0;
2993         /* Order representors by name. */
2994         return si_a->port_name - si_b->port_name;
2995 }
2996
2997 /**
2998  * Match PCI information for possible slaves of bonding device.
2999  *
3000  * @param[in] ibv_dev
3001  *   Pointer to Infiniband device structure.
3002  * @param[in] pci_dev
3003  *   Pointer to PCI device structure to match PCI address.
3004  * @param[in] nl_rdma
3005  *   Netlink RDMA group socket handle.
3006  *
3007  * @return
3008  *   negative value if no bonding device found, otherwise
3009  *   positive index of slave PF in bonding.
3010  */
3011 static int
3012 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev,
3013                            const struct rte_pci_device *pci_dev,
3014                            int nl_rdma)
3015 {
3016         char ifname[IF_NAMESIZE + 1];
3017         unsigned int ifindex;
3018         unsigned int np, i;
3019         FILE *file = NULL;
3020         int pf = -1;
3021
3022         /*
3023          * Try to get master device name. If something goes
3024          * wrong suppose the lack of kernel support and no
3025          * bonding devices.
3026          */
3027         if (nl_rdma < 0)
3028                 return -1;
3029         if (!strstr(ibv_dev->name, "bond"))
3030                 return -1;
3031         np = mlx5_nl_portnum(nl_rdma, ibv_dev->name);
3032         if (!np)
3033                 return -1;
3034         /*
3035          * The Master device might not be on the predefined
3036          * port (not on port index 1, it is not garanted),
3037          * we have to scan all Infiniband device port and
3038          * find master.
3039          */
3040         for (i = 1; i <= np; ++i) {
3041                 /* Check whether Infiniband port is populated. */
3042                 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i);
3043                 if (!ifindex)
3044                         continue;
3045                 if (!if_indextoname(ifindex, ifname))
3046                         continue;
3047                 /* Try to read bonding slave names from sysfs. */
3048                 MKSTR(slaves,
3049                       "/sys/class/net/%s/master/bonding/slaves", ifname);
3050                 file = fopen(slaves, "r");
3051                 if (file)
3052                         break;
3053         }
3054         if (!file)
3055                 return -1;
3056         /* Use safe format to check maximal buffer length. */
3057         MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE);
3058         while (fscanf(file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) {
3059                 char tmp_str[IF_NAMESIZE + 32];
3060                 struct rte_pci_addr pci_addr;
3061                 struct mlx5_switch_info info;
3062
3063                 /* Process slave interface names in the loop. */
3064                 snprintf(tmp_str, sizeof(tmp_str),
3065                          "/sys/class/net/%s", ifname);
3066                 if (mlx5_dev_to_pci_addr(tmp_str, &pci_addr)) {
3067                         DRV_LOG(WARNING, "can not get PCI address"
3068                                          " for netdev \"%s\"", ifname);
3069                         continue;
3070                 }
3071                 if (pci_dev->addr.domain != pci_addr.domain ||
3072                     pci_dev->addr.bus != pci_addr.bus ||
3073                     pci_dev->addr.devid != pci_addr.devid ||
3074                     pci_dev->addr.function != pci_addr.function)
3075                         continue;
3076                 /* Slave interface PCI address match found. */
3077                 fclose(file);
3078                 snprintf(tmp_str, sizeof(tmp_str),
3079                          "/sys/class/net/%s/phys_port_name", ifname);
3080                 file = fopen(tmp_str, "rb");
3081                 if (!file)
3082                         break;
3083                 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET;
3084                 if (fscanf(file, "%32s", tmp_str) == 1)
3085                         mlx5_translate_port_name(tmp_str, &info);
3086                 if (info.name_type == MLX5_PHYS_PORT_NAME_TYPE_LEGACY ||
3087                     info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK)
3088                         pf = info.port_name;
3089                 break;
3090         }
3091         if (file)
3092                 fclose(file);
3093         return pf;
3094 }
3095
3096 /**
3097  * DPDK callback to register a PCI device.
3098  *
3099  * This function spawns Ethernet devices out of a given PCI device.
3100  *
3101  * @param[in] pci_drv
3102  *   PCI driver structure (mlx5_driver).
3103  * @param[in] pci_dev
3104  *   PCI device information.
3105  *
3106  * @return
3107  *   0 on success, a negative errno value otherwise and rte_errno is set.
3108  */
3109 static int
3110 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3111                struct rte_pci_device *pci_dev)
3112 {
3113         struct ibv_device **ibv_list;
3114         /*
3115          * Number of found IB Devices matching with requested PCI BDF.
3116          * nd != 1 means there are multiple IB devices over the same
3117          * PCI device and we have representors and master.
3118          */
3119         unsigned int nd = 0;
3120         /*
3121          * Number of found IB device Ports. nd = 1 and np = 1..n means
3122          * we have the single multiport IB device, and there may be
3123          * representors attached to some of found ports.
3124          */
3125         unsigned int np = 0;
3126         /*
3127          * Number of DPDK ethernet devices to Spawn - either over
3128          * multiple IB devices or multiple ports of single IB device.
3129          * Actually this is the number of iterations to spawn.
3130          */
3131         unsigned int ns = 0;
3132         /*
3133          * Bonding device
3134          *   < 0 - no bonding device (single one)
3135          *  >= 0 - bonding device (value is slave PF index)
3136          */
3137         int bd = -1;
3138         struct mlx5_dev_spawn_data *list = NULL;
3139         struct mlx5_dev_config dev_config;
3140         int ret;
3141
3142         if (mlx5_class_get(pci_dev->device.devargs) != MLX5_CLASS_NET) {
3143                 DRV_LOG(DEBUG, "Skip probing - should be probed by other mlx5"
3144                         " driver.");
3145                 return 1;
3146         }
3147         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
3148                 mlx5_pmd_socket_init();
3149         ret = mlx5_init_once();
3150         if (ret) {
3151                 DRV_LOG(ERR, "unable to init PMD global data: %s",
3152                         strerror(rte_errno));
3153                 return -rte_errno;
3154         }
3155         MLX5_ASSERT(pci_drv == &mlx5_driver);
3156         errno = 0;
3157         ibv_list = mlx5_glue->get_device_list(&ret);
3158         if (!ibv_list) {
3159                 rte_errno = errno ? errno : ENOSYS;
3160                 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?");
3161                 return -rte_errno;
3162         }
3163         /*
3164          * First scan the list of all Infiniband devices to find
3165          * matching ones, gathering into the list.
3166          */
3167         struct ibv_device *ibv_match[ret + 1];
3168         int nl_route = mlx5_nl_init(NETLINK_ROUTE);
3169         int nl_rdma = mlx5_nl_init(NETLINK_RDMA);
3170         unsigned int i;
3171
3172         while (ret-- > 0) {
3173                 struct rte_pci_addr pci_addr;
3174
3175                 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name);
3176                 bd = mlx5_device_bond_pci_match
3177                                 (ibv_list[ret], pci_dev, nl_rdma);
3178                 if (bd >= 0) {
3179                         /*
3180                          * Bonding device detected. Only one match is allowed,
3181                          * the bonding is supported over multi-port IB device,
3182                          * there should be no matches on representor PCI
3183                          * functions or non VF LAG bonding devices with
3184                          * specified address.
3185                          */
3186                         if (nd) {
3187                                 DRV_LOG(ERR,
3188                                         "multiple PCI match on bonding device"
3189                                         "\"%s\" found", ibv_list[ret]->name);
3190                                 rte_errno = ENOENT;
3191                                 ret = -rte_errno;
3192                                 goto exit;
3193                         }
3194                         DRV_LOG(INFO, "PCI information matches for"
3195                                       " slave %d bonding device \"%s\"",
3196                                       bd, ibv_list[ret]->name);
3197                         ibv_match[nd++] = ibv_list[ret];
3198                         break;
3199                 }
3200                 if (mlx5_dev_to_pci_addr
3201                         (ibv_list[ret]->ibdev_path, &pci_addr))
3202                         continue;
3203                 if (pci_dev->addr.domain != pci_addr.domain ||
3204                     pci_dev->addr.bus != pci_addr.bus ||
3205                     pci_dev->addr.devid != pci_addr.devid ||
3206                     pci_dev->addr.function != pci_addr.function)
3207                         continue;
3208                 DRV_LOG(INFO, "PCI information matches for device \"%s\"",
3209                         ibv_list[ret]->name);
3210                 ibv_match[nd++] = ibv_list[ret];
3211         }
3212         ibv_match[nd] = NULL;
3213         if (!nd) {
3214                 /* No device matches, just complain and bail out. */
3215                 DRV_LOG(WARNING,
3216                         "no Verbs device matches PCI device " PCI_PRI_FMT ","
3217                         " are kernel drivers loaded?",
3218                         pci_dev->addr.domain, pci_dev->addr.bus,
3219                         pci_dev->addr.devid, pci_dev->addr.function);
3220                 rte_errno = ENOENT;
3221                 ret = -rte_errno;
3222                 goto exit;
3223         }
3224         if (nd == 1) {
3225                 /*
3226                  * Found single matching device may have multiple ports.
3227                  * Each port may be representor, we have to check the port
3228                  * number and check the representors existence.
3229                  */
3230                 if (nl_rdma >= 0)
3231                         np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name);
3232                 if (!np)
3233                         DRV_LOG(WARNING, "can not get IB device \"%s\""
3234                                          " ports number", ibv_match[0]->name);
3235                 if (bd >= 0 && !np) {
3236                         DRV_LOG(ERR, "can not get ports"
3237                                      " for bonding device");
3238                         rte_errno = ENOENT;
3239                         ret = -rte_errno;
3240                         goto exit;
3241                 }
3242         }
3243 #ifndef HAVE_MLX5DV_DR_DEVX_PORT
3244         if (bd >= 0) {
3245                 /*
3246                  * This may happen if there is VF LAG kernel support and
3247                  * application is compiled with older rdma_core library.
3248                  */
3249                 DRV_LOG(ERR,
3250                         "No kernel/verbs support for VF LAG bonding found.");
3251                 rte_errno = ENOTSUP;
3252                 ret = -rte_errno;
3253                 goto exit;
3254         }
3255 #endif
3256         /*
3257          * Now we can determine the maximal
3258          * amount of devices to be spawned.
3259          */
3260         list = rte_zmalloc("device spawn data",
3261                          sizeof(struct mlx5_dev_spawn_data) *
3262                          (np ? np : nd),
3263                          RTE_CACHE_LINE_SIZE);
3264         if (!list) {
3265                 DRV_LOG(ERR, "spawn data array allocation failure");
3266                 rte_errno = ENOMEM;
3267                 ret = -rte_errno;
3268                 goto exit;
3269         }
3270         if (bd >= 0 || np > 1) {
3271                 /*
3272                  * Single IB device with multiple ports found,
3273                  * it may be E-Switch master device and representors.
3274                  * We have to perform identification trough the ports.
3275                  */
3276                 MLX5_ASSERT(nl_rdma >= 0);
3277                 MLX5_ASSERT(ns == 0);
3278                 MLX5_ASSERT(nd == 1);
3279                 MLX5_ASSERT(np);
3280                 for (i = 1; i <= np; ++i) {
3281                         list[ns].max_port = np;
3282                         list[ns].ibv_port = i;
3283                         list[ns].ibv_dev = ibv_match[0];
3284                         list[ns].eth_dev = NULL;
3285                         list[ns].pci_dev = pci_dev;
3286                         list[ns].pf_bond = bd;
3287                         list[ns].ifindex = mlx5_nl_ifindex
3288                                         (nl_rdma, list[ns].ibv_dev->name, i);
3289                         if (!list[ns].ifindex) {
3290                                 /*
3291                                  * No network interface index found for the
3292                                  * specified port, it means there is no
3293                                  * representor on this port. It's OK,
3294                                  * there can be disabled ports, for example
3295                                  * if sriov_numvfs < sriov_totalvfs.
3296                                  */
3297                                 continue;
3298                         }
3299                         ret = -1;
3300                         if (nl_route >= 0)
3301                                 ret = mlx5_nl_switch_info
3302                                                (nl_route,
3303                                                 list[ns].ifindex,
3304                                                 &list[ns].info);
3305                         if (ret || (!list[ns].info.representor &&
3306                                     !list[ns].info.master)) {
3307                                 /*
3308                                  * We failed to recognize representors with
3309                                  * Netlink, let's try to perform the task
3310                                  * with sysfs.
3311                                  */
3312                                 ret =  mlx5_sysfs_switch_info
3313                                                 (list[ns].ifindex,
3314                                                  &list[ns].info);
3315                         }
3316                         if (!ret && bd >= 0) {
3317                                 switch (list[ns].info.name_type) {
3318                                 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK:
3319                                         if (list[ns].info.port_name == bd)
3320                                                 ns++;
3321                                         break;
3322                                 case MLX5_PHYS_PORT_NAME_TYPE_PFVF:
3323                                         if (list[ns].info.pf_num == bd)
3324                                                 ns++;
3325                                         break;
3326                                 default:
3327                                         break;
3328                                 }
3329                                 continue;
3330                         }
3331                         if (!ret && (list[ns].info.representor ^
3332                                      list[ns].info.master))
3333                                 ns++;
3334                 }
3335                 if (!ns) {
3336                         DRV_LOG(ERR,
3337                                 "unable to recognize master/representors"
3338                                 " on the IB device with multiple ports");
3339                         rte_errno = ENOENT;
3340                         ret = -rte_errno;
3341                         goto exit;
3342                 }
3343         } else {
3344                 /*
3345                  * The existence of several matching entries (nd > 1) means
3346                  * port representors have been instantiated. No existing Verbs
3347                  * call nor sysfs entries can tell them apart, this can only
3348                  * be done through Netlink calls assuming kernel drivers are
3349                  * recent enough to support them.
3350                  *
3351                  * In the event of identification failure through Netlink,
3352                  * try again through sysfs, then:
3353                  *
3354                  * 1. A single IB device matches (nd == 1) with single
3355                  *    port (np=0/1) and is not a representor, assume
3356                  *    no switch support.
3357                  *
3358                  * 2. Otherwise no safe assumptions can be made;
3359                  *    complain louder and bail out.
3360                  */
3361                 np = 1;
3362                 for (i = 0; i != nd; ++i) {
3363                         memset(&list[ns].info, 0, sizeof(list[ns].info));
3364                         list[ns].max_port = 1;
3365                         list[ns].ibv_port = 1;
3366                         list[ns].ibv_dev = ibv_match[i];
3367                         list[ns].eth_dev = NULL;
3368                         list[ns].pci_dev = pci_dev;
3369                         list[ns].pf_bond = -1;
3370                         list[ns].ifindex = 0;
3371                         if (nl_rdma >= 0)
3372                                 list[ns].ifindex = mlx5_nl_ifindex
3373                                         (nl_rdma, list[ns].ibv_dev->name, 1);
3374                         if (!list[ns].ifindex) {
3375                                 char ifname[IF_NAMESIZE];
3376
3377                                 /*
3378                                  * Netlink failed, it may happen with old
3379                                  * ib_core kernel driver (before 4.16).
3380                                  * We can assume there is old driver because
3381                                  * here we are processing single ports IB
3382                                  * devices. Let's try sysfs to retrieve
3383                                  * the ifindex. The method works for
3384                                  * master device only.
3385                                  */
3386                                 if (nd > 1) {
3387                                         /*
3388                                          * Multiple devices found, assume
3389                                          * representors, can not distinguish
3390                                          * master/representor and retrieve
3391                                          * ifindex via sysfs.
3392                                          */
3393                                         continue;
3394                                 }
3395                                 ret = mlx5_get_master_ifname
3396                                         (ibv_match[i]->ibdev_path, &ifname);
3397                                 if (!ret)
3398                                         list[ns].ifindex =
3399                                                 if_nametoindex(ifname);
3400                                 if (!list[ns].ifindex) {
3401                                         /*
3402                                          * No network interface index found
3403                                          * for the specified device, it means
3404                                          * there it is neither representor
3405                                          * nor master.
3406                                          */
3407                                         continue;
3408                                 }
3409                         }
3410                         ret = -1;
3411                         if (nl_route >= 0)
3412                                 ret = mlx5_nl_switch_info
3413                                                (nl_route,
3414                                                 list[ns].ifindex,
3415                                                 &list[ns].info);
3416                         if (ret || (!list[ns].info.representor &&
3417                                     !list[ns].info.master)) {
3418                                 /*
3419                                  * We failed to recognize representors with
3420                                  * Netlink, let's try to perform the task
3421                                  * with sysfs.
3422                                  */
3423                                 ret =  mlx5_sysfs_switch_info
3424                                                 (list[ns].ifindex,
3425                                                  &list[ns].info);
3426                         }
3427                         if (!ret && (list[ns].info.representor ^
3428                                      list[ns].info.master)) {
3429                                 ns++;
3430                         } else if ((nd == 1) &&
3431                                    !list[ns].info.representor &&
3432                                    !list[ns].info.master) {
3433                                 /*
3434                                  * Single IB device with
3435                                  * one physical port and
3436                                  * attached network device.
3437                                  * May be SRIOV is not enabled
3438                                  * or there is no representors.
3439                                  */
3440                                 DRV_LOG(INFO, "no E-Switch support detected");
3441                                 ns++;
3442                                 break;
3443                         }
3444                 }
3445                 if (!ns) {
3446                         DRV_LOG(ERR,
3447                                 "unable to recognize master/representors"
3448                                 " on the multiple IB devices");
3449                         rte_errno = ENOENT;
3450                         ret = -rte_errno;
3451                         goto exit;
3452                 }
3453         }
3454         MLX5_ASSERT(ns);
3455         /*
3456          * Sort list to probe devices in natural order for users convenience
3457          * (i.e. master first, then representors from lowest to highest ID).
3458          */
3459         qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp);
3460         /* Default configuration. */
3461         dev_config = (struct mlx5_dev_config){
3462                 .hw_padding = 0,
3463                 .mps = MLX5_ARG_UNSET,
3464                 .dbnc = MLX5_ARG_UNSET,
3465                 .rx_vec_en = 1,
3466                 .txq_inline_max = MLX5_ARG_UNSET,
3467                 .txq_inline_min = MLX5_ARG_UNSET,
3468                 .txq_inline_mpw = MLX5_ARG_UNSET,
3469                 .txqs_inline = MLX5_ARG_UNSET,
3470                 .vf_nl_en = 1,
3471                 .mr_ext_memseg_en = 1,
3472                 .mprq = {
3473                         .enabled = 0, /* Disabled by default. */
3474                         .stride_num_n = 0,
3475                         .stride_size_n = 0,
3476                         .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
3477                         .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
3478                 },
3479                 .dv_esw_en = 1,
3480                 .dv_flow_en = 1,
3481                 .log_hp_size = MLX5_ARG_UNSET,
3482         };
3483         /* Device specific configuration. */
3484         switch (pci_dev->id.device_id) {
3485         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
3486         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
3487         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
3488         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
3489         case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF:
3490         case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF:
3491         case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF:
3492                 dev_config.vf = 1;
3493                 break;
3494         default:
3495                 break;
3496         }
3497         for (i = 0; i != ns; ++i) {
3498                 uint32_t restore;
3499
3500                 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device,
3501                                                  &list[i],
3502                                                  dev_config);
3503                 if (!list[i].eth_dev) {
3504                         if (rte_errno != EBUSY && rte_errno != EEXIST)
3505                                 break;
3506                         /* Device is disabled or already spawned. Ignore it. */
3507                         continue;
3508                 }
3509                 restore = list[i].eth_dev->data->dev_flags;
3510                 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev);
3511                 /* Restore non-PCI flags cleared by the above call. */
3512                 list[i].eth_dev->data->dev_flags |= restore;
3513                 mlx5_dev_interrupt_handler_devx_install(list[i].eth_dev);
3514                 rte_eth_dev_probing_finish(list[i].eth_dev);
3515         }
3516         if (i != ns) {
3517                 DRV_LOG(ERR,
3518                         "probe of PCI device " PCI_PRI_FMT " aborted after"
3519                         " encountering an error: %s",
3520                         pci_dev->addr.domain, pci_dev->addr.bus,
3521                         pci_dev->addr.devid, pci_dev->addr.function,
3522                         strerror(rte_errno));
3523                 ret = -rte_errno;
3524                 /* Roll back. */
3525                 while (i--) {
3526                         if (!list[i].eth_dev)
3527                                 continue;
3528                         mlx5_dev_close(list[i].eth_dev);
3529                         /* mac_addrs must not be freed because in dev_private */
3530                         list[i].eth_dev->data->mac_addrs = NULL;
3531                         claim_zero(rte_eth_dev_release_port(list[i].eth_dev));
3532                 }
3533                 /* Restore original error. */
3534                 rte_errno = -ret;
3535         } else {
3536                 ret = 0;
3537         }
3538 exit:
3539         /*
3540          * Do the routine cleanup:
3541          * - close opened Netlink sockets
3542          * - free allocated spawn data array
3543          * - free the Infiniband device list
3544          */
3545         if (nl_rdma >= 0)
3546                 close(nl_rdma);
3547         if (nl_route >= 0)
3548                 close(nl_route);
3549         if (list)
3550                 rte_free(list);
3551         MLX5_ASSERT(ibv_list);
3552         mlx5_glue->free_device_list(ibv_list);
3553         return ret;
3554 }
3555
3556 /**
3557  * Look for the ethernet device belonging to mlx5 driver.
3558  *
3559  * @param[in] port_id
3560  *   port_id to start looking for device.
3561  * @param[in] pci_dev
3562  *   Pointer to the hint PCI device. When device is being probed
3563  *   the its siblings (master and preceding representors might
3564  *   not have assigned driver yet (because the mlx5_pci_probe()
3565  *   is not completed yet, for this case match on hint PCI
3566  *   device may be used to detect sibling device.
3567  *
3568  * @return
3569  *   port_id of found device, RTE_MAX_ETHPORT if not found.
3570  */
3571 uint16_t
3572 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
3573 {
3574         while (port_id < RTE_MAX_ETHPORTS) {
3575                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
3576
3577                 if (dev->state != RTE_ETH_DEV_UNUSED &&
3578                     dev->device &&
3579                     (dev->device == &pci_dev->device ||
3580                      (dev->device->driver &&
3581                      dev->device->driver->name &&
3582                      !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
3583                         break;
3584                 port_id++;
3585         }
3586         if (port_id >= RTE_MAX_ETHPORTS)
3587                 return RTE_MAX_ETHPORTS;
3588         return port_id;
3589 }
3590
3591 /**
3592  * DPDK callback to remove a PCI device.
3593  *
3594  * This function removes all Ethernet devices belong to a given PCI device.
3595  *
3596  * @param[in] pci_dev
3597  *   Pointer to the PCI device.
3598  *
3599  * @return
3600  *   0 on success, the function cannot fail.
3601  */
3602 static int
3603 mlx5_pci_remove(struct rte_pci_device *pci_dev)
3604 {
3605         uint16_t port_id;
3606
3607         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device)
3608                 rte_eth_dev_close(port_id);
3609         return 0;
3610 }
3611
3612 static const struct rte_pci_id mlx5_pci_id_map[] = {
3613         {
3614                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3615                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
3616         },
3617         {
3618                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3619                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
3620         },
3621         {
3622                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3623                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
3624         },
3625         {
3626                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3627                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
3628         },
3629         {
3630                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3631                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
3632         },
3633         {
3634                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3635                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
3636         },
3637         {
3638                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3639                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
3640         },
3641         {
3642                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3643                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
3644         },
3645         {
3646                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3647                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
3648         },
3649         {
3650                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3651                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
3652         },
3653         {
3654                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3655                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
3656         },
3657         {
3658                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3659                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
3660         },
3661         {
3662                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3663                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
3664         },
3665         {
3666                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3667                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
3668         },
3669         {
3670                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3671                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
3672         },
3673         {
3674                 .vendor_id = 0
3675         }
3676 };
3677
3678 static struct rte_pci_driver mlx5_driver = {
3679         .driver = {
3680                 .name = MLX5_DRIVER_NAME
3681         },
3682         .id_table = mlx5_pci_id_map,
3683         .probe = mlx5_pci_probe,
3684         .remove = mlx5_pci_remove,
3685         .dma_map = mlx5_dma_map,
3686         .dma_unmap = mlx5_dma_unmap,
3687         .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV |
3688                      RTE_PCI_DRV_PROBE_AGAIN,
3689 };
3690
3691 /**
3692  * Driver initialization routine.
3693  */
3694 RTE_INIT(rte_mlx5_pmd_init)
3695 {
3696         /* Initialize driver log type. */
3697         mlx5_logtype = rte_log_register("pmd.net.mlx5");
3698         if (mlx5_logtype >= 0)
3699                 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
3700
3701         /* Build the static tables for Verbs conversion. */
3702         mlx5_set_ptype_table();
3703         mlx5_set_cksum_table();
3704         mlx5_set_swp_types_table();
3705         if (mlx5_glue)
3706                 rte_pci_register(&mlx5_driver);
3707 }
3708
3709 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
3710 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
3711 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");