4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
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14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
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18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
46 #pragma GCC diagnostic ignored "-Wpedantic"
48 #include <infiniband/verbs.h>
50 #pragma GCC diagnostic error "-Wpedantic"
53 /* DPDK headers don't like -pedantic. */
55 #pragma GCC diagnostic ignored "-Wpedantic"
57 #include <rte_malloc.h>
58 #include <rte_ethdev.h>
59 #include <rte_ethdev_pci.h>
61 #include <rte_common.h>
62 #include <rte_kvargs.h>
64 #pragma GCC diagnostic error "-Wpedantic"
68 #include "mlx5_utils.h"
69 #include "mlx5_rxtx.h"
70 #include "mlx5_autoconf.h"
71 #include "mlx5_defs.h"
73 /* Device parameter to enable RX completion queue compression. */
74 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
76 /* Device parameter to configure inline send. */
77 #define MLX5_TXQ_INLINE "txq_inline"
80 * Device parameter to configure the number of TX queues threshold for
81 * enabling inline send.
83 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
85 /* Device parameter to enable multi-packet send WQEs. */
86 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
88 /* Device parameter to include 2 dsegs in the title WQEBB. */
89 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
91 /* Device parameter to limit the size of inlining packet. */
92 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
94 /* Device parameter to enable hardware TSO offload. */
95 #define MLX5_TSO "tso"
98 * Retrieve integer value from environment variable.
101 * Environment variable name.
104 * Integer value, 0 if the variable is not set.
107 mlx5_getenv_int(const char *name)
109 const char *val = getenv(name);
117 * DPDK callback to close the device.
119 * Destroy all queues and objects, free memory.
122 * Pointer to Ethernet device structure.
125 mlx5_dev_close(struct rte_eth_dev *dev)
127 struct priv *priv = mlx5_get_priv(dev);
131 DEBUG("%p: closing device \"%s\"",
133 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
134 /* In case mlx5_dev_stop() has not been called. */
135 priv_dev_interrupt_handler_uninstall(priv, dev);
136 priv_special_flow_disable_all(priv);
137 priv_mac_addrs_disable(priv);
138 priv_destroy_hash_rxqs(priv);
140 /* Remove flow director elements. */
141 priv_fdir_disable(priv);
142 priv_fdir_delete_filters_list(priv);
144 /* Prevent crashes when queues are still in use. */
145 dev->rx_pkt_burst = removed_rx_burst;
146 dev->tx_pkt_burst = removed_tx_burst;
147 if (priv->rxqs != NULL) {
148 /* XXX race condition if mlx5_rx_burst() is still running. */
150 for (i = 0; (i != priv->rxqs_n); ++i) {
151 struct rxq *rxq = (*priv->rxqs)[i];
152 struct rxq_ctrl *rxq_ctrl;
156 rxq_ctrl = container_of(rxq, struct rxq_ctrl, rxq);
157 (*priv->rxqs)[i] = NULL;
158 rxq_cleanup(rxq_ctrl);
164 if (priv->txqs != NULL) {
165 /* XXX race condition if mlx5_tx_burst() is still running. */
167 for (i = 0; (i != priv->txqs_n); ++i) {
168 struct txq *txq = (*priv->txqs)[i];
169 struct txq_ctrl *txq_ctrl;
173 txq_ctrl = container_of(txq, struct txq_ctrl, txq);
174 (*priv->txqs)[i] = NULL;
175 txq_cleanup(txq_ctrl);
181 if (priv->pd != NULL) {
182 assert(priv->ctx != NULL);
183 claim_zero(ibv_dealloc_pd(priv->pd));
184 claim_zero(ibv_close_device(priv->ctx));
186 assert(priv->ctx == NULL);
187 if (priv->rss_conf != NULL) {
188 for (i = 0; (i != hash_rxq_init_n); ++i)
189 rte_free((*priv->rss_conf)[i]);
190 rte_free(priv->rss_conf);
192 if (priv->reta_idx != NULL)
193 rte_free(priv->reta_idx);
195 memset(priv, 0, sizeof(*priv));
198 static const struct eth_dev_ops mlx5_dev_ops = {
199 .dev_configure = mlx5_dev_configure,
200 .dev_start = mlx5_dev_start,
201 .dev_stop = mlx5_dev_stop,
202 .dev_set_link_down = mlx5_set_link_down,
203 .dev_set_link_up = mlx5_set_link_up,
204 .dev_close = mlx5_dev_close,
205 .promiscuous_enable = mlx5_promiscuous_enable,
206 .promiscuous_disable = mlx5_promiscuous_disable,
207 .allmulticast_enable = mlx5_allmulticast_enable,
208 .allmulticast_disable = mlx5_allmulticast_disable,
209 .link_update = mlx5_link_update,
210 .stats_get = mlx5_stats_get,
211 .stats_reset = mlx5_stats_reset,
212 .xstats_get = mlx5_xstats_get,
213 .xstats_reset = mlx5_xstats_reset,
214 .xstats_get_names = mlx5_xstats_get_names,
215 .dev_infos_get = mlx5_dev_infos_get,
216 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
217 .vlan_filter_set = mlx5_vlan_filter_set,
218 .rx_queue_setup = mlx5_rx_queue_setup,
219 .tx_queue_setup = mlx5_tx_queue_setup,
220 .rx_queue_release = mlx5_rx_queue_release,
221 .tx_queue_release = mlx5_tx_queue_release,
222 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
223 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
224 .mac_addr_remove = mlx5_mac_addr_remove,
225 .mac_addr_add = mlx5_mac_addr_add,
226 .mac_addr_set = mlx5_mac_addr_set,
227 .mtu_set = mlx5_dev_set_mtu,
228 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
229 .vlan_offload_set = mlx5_vlan_offload_set,
230 .reta_update = mlx5_dev_rss_reta_update,
231 .reta_query = mlx5_dev_rss_reta_query,
232 .rss_hash_update = mlx5_rss_hash_update,
233 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
234 .filter_ctrl = mlx5_dev_filter_ctrl,
235 .rx_descriptor_status = mlx5_rx_descriptor_status,
236 .tx_descriptor_status = mlx5_tx_descriptor_status,
237 .rx_queue_intr_enable = mlx5_rx_intr_enable,
238 .rx_queue_intr_disable = mlx5_rx_intr_disable,
242 struct rte_pci_addr pci_addr; /* associated PCI address */
243 uint32_t ports; /* physical ports bitfield. */
247 * Get device index in mlx5_dev[] from PCI bus address.
249 * @param[in] pci_addr
250 * PCI bus address to look for.
253 * mlx5_dev[] index on success, -1 on failure.
256 mlx5_dev_idx(struct rte_pci_addr *pci_addr)
261 assert(pci_addr != NULL);
262 for (i = 0; (i != RTE_DIM(mlx5_dev)); ++i) {
263 if ((mlx5_dev[i].pci_addr.domain == pci_addr->domain) &&
264 (mlx5_dev[i].pci_addr.bus == pci_addr->bus) &&
265 (mlx5_dev[i].pci_addr.devid == pci_addr->devid) &&
266 (mlx5_dev[i].pci_addr.function == pci_addr->function))
268 if ((mlx5_dev[i].ports == 0) && (ret == -1))
275 * Verify and store value for device argument.
278 * Key argument to verify.
280 * Value associated with key.
285 * 0 on success, negative errno value on failure.
288 mlx5_args_check(const char *key, const char *val, void *opaque)
290 struct priv *priv = opaque;
294 tmp = strtoul(val, NULL, 0);
296 WARN("%s: \"%s\" is not a valid integer", key, val);
299 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
300 priv->cqe_comp = !!tmp;
301 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
302 priv->txq_inline = tmp;
303 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
304 priv->txqs_inline = tmp;
305 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
306 priv->mps = !!tmp ? priv->mps : MLX5_MPW_DISABLED;
307 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
308 priv->mpw_hdr_dseg = !!tmp;
309 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
310 priv->inline_max_packet_sz = tmp;
311 } else if (strcmp(MLX5_TSO, key) == 0) {
314 WARN("%s: unknown parameter", key);
321 * Parse device parameters.
324 * Pointer to private structure.
326 * Device arguments structure.
329 * 0 on success, errno value on failure.
332 mlx5_args(struct priv *priv, struct rte_devargs *devargs)
334 const char **params = (const char *[]){
335 MLX5_RXQ_CQE_COMP_EN,
337 MLX5_TXQS_MIN_INLINE,
339 MLX5_TXQ_MPW_HDR_DSEG_EN,
340 MLX5_TXQ_MAX_INLINE_LEN,
344 struct rte_kvargs *kvlist;
350 /* Following UGLY cast is done to pass checkpatch. */
351 kvlist = rte_kvargs_parse(devargs->args, params);
354 /* Process parameters. */
355 for (i = 0; (params[i] != NULL); ++i) {
356 if (rte_kvargs_count(kvlist, params[i])) {
357 ret = rte_kvargs_process(kvlist, params[i],
358 mlx5_args_check, priv);
360 rte_kvargs_free(kvlist);
365 rte_kvargs_free(kvlist);
369 static struct rte_pci_driver mlx5_driver;
372 * DPDK callback to register a PCI device.
374 * This function creates an Ethernet device for each port of a given
378 * PCI driver structure (mlx5_driver).
380 * PCI device information.
383 * 0 on success, negative errno value on failure.
386 mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
388 struct ibv_device **list;
389 struct ibv_device *ibv_dev;
391 struct ibv_context *attr_ctx = NULL;
392 struct ibv_device_attr device_attr;
395 unsigned int tunnel_en;
400 assert(pci_drv == &mlx5_driver);
401 /* Get mlx5_dev[] index. */
402 idx = mlx5_dev_idx(&pci_dev->addr);
404 ERROR("this driver cannot support any more adapters");
407 DEBUG("using driver device index %d", idx);
409 /* Save PCI address. */
410 mlx5_dev[idx].pci_addr = pci_dev->addr;
411 list = ibv_get_device_list(&i);
415 ERROR("cannot list devices, is ib_uverbs loaded?");
420 * For each listed device, check related sysfs entry against
421 * the provided PCI ID.
424 struct rte_pci_addr pci_addr;
427 DEBUG("checking device \"%s\"", list[i]->name);
428 if (mlx5_ibv_device_to_pci_addr(list[i], &pci_addr))
430 if ((pci_dev->addr.domain != pci_addr.domain) ||
431 (pci_dev->addr.bus != pci_addr.bus) ||
432 (pci_dev->addr.devid != pci_addr.devid) ||
433 (pci_dev->addr.function != pci_addr.function))
435 sriov = ((pci_dev->id.device_id ==
436 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) ||
437 (pci_dev->id.device_id ==
438 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) ||
439 (pci_dev->id.device_id ==
440 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) ||
441 (pci_dev->id.device_id ==
442 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF));
444 * Multi-packet send is supported by ConnectX-4 Lx PF as well
445 * as all ConnectX-5 devices.
447 switch (pci_dev->id.device_id) {
448 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
450 mps = MLX5_MPW_DISABLED;
452 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
455 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
456 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
457 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
458 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
460 mps = MLX5_MPW_ENHANCED;
463 mps = MLX5_MPW_DISABLED;
465 INFO("PCI information matches, using device \"%s\""
466 " (SR-IOV: %s, %sMPS: %s)",
468 sriov ? "true" : "false",
469 mps == MLX5_MPW_ENHANCED ? "Enhanced " : "",
470 mps != MLX5_MPW_DISABLED ? "true" : "false");
471 attr_ctx = ibv_open_device(list[i]);
475 if (attr_ctx == NULL) {
476 ibv_free_device_list(list);
479 ERROR("cannot access device, is mlx5_ib loaded?");
482 ERROR("cannot use device, are drivers up to date?");
490 DEBUG("device opened");
491 if (ibv_query_device(attr_ctx, &device_attr))
493 INFO("%u port(s) detected", device_attr.phys_port_cnt);
495 for (i = 0; i < device_attr.phys_port_cnt; i++) {
496 uint32_t port = i + 1; /* ports are indexed from one */
497 uint32_t test = (1 << i);
498 struct ibv_context *ctx = NULL;
499 struct ibv_port_attr port_attr;
500 struct ibv_pd *pd = NULL;
501 struct priv *priv = NULL;
502 struct rte_eth_dev *eth_dev;
503 struct ibv_exp_device_attr exp_device_attr;
504 struct ether_addr mac;
505 uint16_t num_vfs = 0;
507 exp_device_attr.comp_mask =
508 IBV_EXP_DEVICE_ATTR_EXP_CAP_FLAGS |
509 IBV_EXP_DEVICE_ATTR_RX_HASH |
510 IBV_EXP_DEVICE_ATTR_VLAN_OFFLOADS |
511 IBV_EXP_DEVICE_ATTR_RX_PAD_END_ALIGN |
512 IBV_EXP_DEVICE_ATTR_TSO_CAPS |
515 DEBUG("using port %u (%08" PRIx32 ")", port, test);
517 ctx = ibv_open_device(ibv_dev);
521 /* Check port status. */
522 err = ibv_query_port(ctx, port, &port_attr);
524 ERROR("port query failed: %s", strerror(err));
528 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
529 ERROR("port %d is not configured in Ethernet mode",
534 if (port_attr.state != IBV_PORT_ACTIVE)
535 DEBUG("port %d is not active: \"%s\" (%d)",
536 port, ibv_port_state_str(port_attr.state),
539 /* Allocate protection domain. */
540 pd = ibv_alloc_pd(ctx);
542 ERROR("PD allocation failure");
547 mlx5_dev[idx].ports |= test;
549 /* from rte_ethdev.c */
550 priv = rte_zmalloc("ethdev private structure",
552 RTE_CACHE_LINE_SIZE);
554 ERROR("priv allocation failure");
560 priv->device_attr = device_attr;
563 priv->mtu = ETHER_MTU;
564 priv->mps = mps; /* Enable MPW by default if supported. */
565 /* Set default values for Enhanced MPW, a.k.a MPWv2. */
566 if (mps == MLX5_MPW_ENHANCED) {
567 priv->mpw_hdr_dseg = 0;
568 priv->txqs_inline = MLX5_EMPW_MIN_TXQS;
569 priv->inline_max_packet_sz = MLX5_EMPW_MAX_INLINE_LEN;
570 priv->txq_inline = MLX5_WQE_SIZE_MAX - MLX5_WQE_SIZE;
572 priv->cqe_comp = 1; /* Enable compression by default. */
573 priv->tunnel_en = tunnel_en;
574 err = mlx5_args(priv, pci_dev->device.devargs);
576 ERROR("failed to process device arguments: %s",
580 if (ibv_exp_query_device(ctx, &exp_device_attr)) {
581 ERROR("ibv_exp_query_device() failed");
586 ((exp_device_attr.exp_device_cap_flags &
587 IBV_EXP_DEVICE_RX_CSUM_TCP_UDP_PKT) &&
588 (exp_device_attr.exp_device_cap_flags &
589 IBV_EXP_DEVICE_RX_CSUM_IP_PKT));
590 DEBUG("checksum offloading is %ssupported",
591 (priv->hw_csum ? "" : "not "));
593 priv->hw_csum_l2tun = !!(exp_device_attr.exp_device_cap_flags &
594 IBV_EXP_DEVICE_VXLAN_SUPPORT);
595 DEBUG("L2 tunnel checksum offloads are %ssupported",
596 (priv->hw_csum_l2tun ? "" : "not "));
598 priv->ind_table_max_size = exp_device_attr.rx_hash_caps.max_rwq_indirection_table_size;
599 /* Remove this check once DPDK supports larger/variable
600 * indirection tables. */
601 if (priv->ind_table_max_size >
602 (unsigned int)ETH_RSS_RETA_SIZE_512)
603 priv->ind_table_max_size = ETH_RSS_RETA_SIZE_512;
604 DEBUG("maximum RX indirection table size is %u",
605 priv->ind_table_max_size);
606 priv->hw_vlan_strip = !!(exp_device_attr.wq_vlan_offloads_cap &
607 IBV_EXP_RECEIVE_WQ_CVLAN_STRIP);
608 DEBUG("VLAN stripping is %ssupported",
609 (priv->hw_vlan_strip ? "" : "not "));
611 priv->hw_fcs_strip = !!(exp_device_attr.exp_device_cap_flags &
612 IBV_EXP_DEVICE_SCATTER_FCS);
613 DEBUG("FCS stripping configuration is %ssupported",
614 (priv->hw_fcs_strip ? "" : "not "));
616 priv->hw_padding = !!exp_device_attr.rx_pad_end_addr_align;
617 DEBUG("hardware RX end alignment padding is %ssupported",
618 (priv->hw_padding ? "" : "not "));
620 priv_get_num_vfs(priv, &num_vfs);
621 priv->sriov = (num_vfs || sriov);
622 priv->tso = ((priv->tso) &&
623 (exp_device_attr.tso_caps.max_tso > 0) &&
624 (exp_device_attr.tso_caps.supported_qpts &
625 (1 << IBV_QPT_RAW_ETH)));
627 priv->max_tso_payload_sz =
628 exp_device_attr.tso_caps.max_tso;
629 if (priv->mps && !mps) {
630 ERROR("multi-packet send not supported on this device"
631 " (" MLX5_TXQ_MPW_EN ")");
634 } else if (priv->mps && priv->tso) {
635 WARN("multi-packet send not supported in conjunction "
636 "with TSO. MPS disabled");
640 priv->mps == MLX5_MPW_ENHANCED ? "Enhanced " : "",
641 priv->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
642 /* Allocate and register default RSS hash keys. */
643 priv->rss_conf = rte_calloc(__func__, hash_rxq_init_n,
644 sizeof((*priv->rss_conf)[0]), 0);
645 if (priv->rss_conf == NULL) {
649 err = rss_hash_rss_conf_new_key(priv,
650 rss_hash_default_key,
651 rss_hash_default_key_len,
655 /* Configure the first MAC address by default. */
656 if (priv_get_mac(priv, &mac.addr_bytes)) {
657 ERROR("cannot get MAC address, is mlx5_en loaded?"
658 " (errno: %s)", strerror(errno));
661 INFO("port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
663 mac.addr_bytes[0], mac.addr_bytes[1],
664 mac.addr_bytes[2], mac.addr_bytes[3],
665 mac.addr_bytes[4], mac.addr_bytes[5]);
666 /* Register MAC address. */
667 claim_zero(priv_mac_addr_add(priv, 0,
668 (const uint8_t (*)[ETHER_ADDR_LEN])
670 /* Initialize FD filters list. */
671 err = fdir_init_filters_list(priv);
676 char ifname[IF_NAMESIZE];
678 if (priv_get_ifname(priv, &ifname) == 0)
679 DEBUG("port %u ifname is \"%s\"",
682 DEBUG("port %u ifname is unknown", priv->port);
685 /* Get actual MTU if possible. */
686 priv_get_mtu(priv, &priv->mtu);
687 DEBUG("port %u MTU is %u", priv->port, priv->mtu);
689 /* from rte_ethdev.c */
691 char name[RTE_ETH_NAME_MAX_LEN];
693 snprintf(name, sizeof(name), "%s port %u",
694 ibv_get_device_name(ibv_dev), port);
695 eth_dev = rte_eth_dev_allocate(name);
697 if (eth_dev == NULL) {
698 ERROR("can not allocate rte ethdev");
703 /* Secondary processes have to use local storage for their
704 * private data as well as a copy of eth_dev->data, but this
705 * pointer must not be modified before burst functions are
706 * actually called. */
707 if (mlx5_is_secondary()) {
708 struct mlx5_secondary_data *sd =
709 &mlx5_secondary_data[eth_dev->data->port_id];
710 sd->primary_priv = eth_dev->data->dev_private;
711 if (sd->primary_priv == NULL) {
712 ERROR("no private data for port %u",
713 eth_dev->data->port_id);
717 sd->shared_dev_data = eth_dev->data;
718 rte_spinlock_init(&sd->lock);
719 memcpy(sd->data.name, sd->shared_dev_data->name,
720 sizeof(sd->data.name));
721 sd->data.dev_private = priv;
722 sd->data.rx_mbuf_alloc_failed = 0;
723 sd->data.mtu = ETHER_MTU;
724 sd->data.port_id = sd->shared_dev_data->port_id;
725 sd->data.mac_addrs = priv->mac;
726 eth_dev->tx_pkt_burst = mlx5_tx_burst_secondary_setup;
727 eth_dev->rx_pkt_burst = mlx5_rx_burst_secondary_setup;
729 eth_dev->data->dev_private = priv;
730 eth_dev->data->mac_addrs = priv->mac;
733 eth_dev->device = &pci_dev->device;
734 rte_eth_copy_pci_info(eth_dev, pci_dev);
735 eth_dev->device->driver = &mlx5_driver.driver;
737 eth_dev->dev_ops = &mlx5_dev_ops;
739 /* Bring Ethernet device up. */
740 DEBUG("forcing Ethernet interface up");
741 priv_set_flags(priv, ~IFF_UP, IFF_UP);
742 mlx5_link_update(priv->dev, 1);
747 rte_free(priv->rss_conf);
751 claim_zero(ibv_dealloc_pd(pd));
753 claim_zero(ibv_close_device(ctx));
758 * XXX if something went wrong in the loop above, there is a resource
759 * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as
760 * long as the dpdk does not provide a way to deallocate a ethdev and a
761 * way to enumerate the registered ethdevs to free the previous ones.
764 /* no port found, complain */
765 if (!mlx5_dev[idx].ports) {
772 claim_zero(ibv_close_device(attr_ctx));
774 ibv_free_device_list(list);
779 static const struct rte_pci_id mlx5_pci_id_map[] = {
781 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
782 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
785 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
786 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
789 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
790 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
793 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
794 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
797 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
798 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
801 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
802 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
805 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
806 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
809 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
810 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
817 static struct rte_pci_driver mlx5_driver = {
819 .name = MLX5_DRIVER_NAME
821 .id_table = mlx5_pci_id_map,
822 .probe = mlx5_pci_probe,
823 .drv_flags = RTE_PCI_DRV_INTR_LSC,
827 * Driver initialization routine.
829 RTE_INIT(rte_mlx5_pmd_init);
831 rte_mlx5_pmd_init(void)
834 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
835 * huge pages. Calling ibv_fork_init() during init allows
836 * applications to use fork() safely for purposes other than
837 * using this PMD, which is not supported in forked processes.
839 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
841 rte_eal_pci_register(&mlx5_driver);
844 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
845 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
846 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");