1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
14 #include <netinet/in.h>
15 #include <sys/queue.h>
18 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
20 #pragma GCC diagnostic ignored "-Wpedantic"
22 #include <infiniband/verbs.h>
24 #pragma GCC diagnostic error "-Wpedantic"
28 #include <rte_ether.h>
29 #include <rte_ethdev_driver.h>
30 #include <rte_rwlock.h>
31 #include <rte_interrupts.h>
32 #include <rte_errno.h>
35 #include "mlx5_utils.h"
37 #include "mlx5_autoconf.h"
38 #include "mlx5_defs.h"
41 PCI_VENDOR_ID_MELLANOX = 0x15b3,
45 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
46 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
47 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
48 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
49 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
50 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
51 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
52 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
53 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2,
54 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3,
55 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b,
56 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c,
59 /* Request types for IPC. */
60 enum mlx5_mp_req_type {
61 MLX5_MP_REQ_VERBS_CMD_FD = 1,
62 MLX5_MP_REQ_CREATE_MR,
63 MLX5_MP_REQ_START_RXTX,
64 MLX5_MP_REQ_STOP_RXTX,
65 MLX5_MP_REQ_QUEUE_STATE_MODIFY,
68 struct mlx5_mp_arg_queue_state_modify {
69 uint8_t is_wq; /* Set if WQ. */
70 uint16_t queue_id; /* DPDK queue ID. */
71 enum ibv_wq_state state; /* WQ requested state. */
74 /* Pameters for IPC. */
75 struct mlx5_mp_param {
76 enum mlx5_mp_req_type type;
81 uintptr_t addr; /* MLX5_MP_REQ_CREATE_MR */
82 struct mlx5_mp_arg_queue_state_modify state_modify;
83 /* MLX5_MP_REQ_QUEUE_STATE_MODIFY */
87 /** Request timeout for IPC. */
88 #define MLX5_MP_REQ_TIMEOUT_SEC 5
90 /** Key string for IPC. */
91 #define MLX5_MP_NAME "net_mlx5_mp"
93 /* Recognized Infiniband device physical port name types. */
94 enum mlx5_phys_port_name_type {
95 MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */
96 MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */
97 MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */
98 MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */
99 MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */
102 /** Switch information returned by mlx5_nl_switch_info(). */
103 struct mlx5_switch_info {
104 uint32_t master:1; /**< Master device. */
105 uint32_t representor:1; /**< Representor device. */
106 enum mlx5_phys_port_name_type name_type; /** < Port name type. */
107 int32_t pf_num; /**< PF number (valid for pfxvfx format only). */
108 int32_t port_name; /**< Representor port name. */
109 uint64_t switch_id; /**< Switch identifier. */
112 LIST_HEAD(mlx5_dev_list, mlx5_ibv_shared);
114 /* Shared data between primary and secondary processes. */
115 struct mlx5_shared_data {
117 /* Global spinlock for primary and secondary processes. */
118 int init_done; /* Whether primary has done initialization. */
119 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
120 struct mlx5_dev_list mem_event_cb_list;
121 rte_rwlock_t mem_event_rwlock;
124 /* Per-process data structure, not visible to other processes. */
125 struct mlx5_local_data {
126 int init_done; /* Whether a secondary has done initialization. */
129 extern struct mlx5_shared_data *mlx5_shared_data;
131 struct mlx5_counter_ctrl {
132 /* Name of the counter. */
133 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE];
134 /* Name of the counter on the device table. */
135 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE];
136 uint32_t ib:1; /**< Nonzero for IB counters. */
139 struct mlx5_xstats_ctrl {
140 /* Number of device stats. */
142 /* Number of device stats identified by PMD. */
143 uint16_t mlx5_stats_n;
144 /* Index in the device counters table. */
145 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
146 uint64_t base[MLX5_MAX_XSTATS];
147 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS];
150 struct mlx5_stats_ctrl {
151 /* Base for imissed counter. */
152 uint64_t imissed_base;
155 /* devX creation object */
156 struct mlx5_devx_obj {
157 struct mlx5dv_devx_obj *obj; /* The DV object. */
158 int id; /* The object ID. */
161 struct mlx5_devx_mkey_attr {
168 /* HCA supports this number of time periods for LRO. */
169 #define MLX5_LRO_NUM_SUPP_PERIODS 4
171 /* HCA attributes. */
172 struct mlx5_hca_attr {
173 uint32_t eswitch_manager:1;
174 uint32_t flow_counters_dump:1;
175 uint8_t flow_counter_bulk_alloc_bitmap;
176 uint32_t eth_net_offloads:1;
178 uint32_t wqe_vlan_insert:1;
179 uint32_t wqe_inline_mode:2;
180 uint32_t vport_inline_mode:3;
182 uint32_t tunnel_lro_gre:1;
183 uint32_t tunnel_lro_vxlan:1;
184 uint32_t lro_max_msg_sz_mode:2;
185 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
189 TAILQ_HEAD(mlx5_flows, rte_flow);
191 /* Default PMD specific parameter value. */
192 #define MLX5_ARG_UNSET (-1)
194 #define MLX5_LRO_SUPPORTED(dev) \
195 (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported)
197 #define MLX5_LRO_ENABLED(dev) \
198 ((dev)->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO)
200 #define MLX5_FLOW_IPV4_LRO (1 << 0)
201 #define MLX5_FLOW_IPV6_LRO (1 << 1)
203 /* LRO configurations structure. */
204 struct mlx5_lro_config {
205 uint32_t supported:1; /* Whether LRO is supported. */
206 uint32_t timeout; /* User configuration. */
210 * Device configuration structure.
212 * Merged configuration from:
214 * - Device capabilities,
215 * - User device parameters disabled features.
217 struct mlx5_dev_config {
218 unsigned int hw_csum:1; /* Checksum offload is supported. */
219 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
220 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */
221 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
222 unsigned int hw_padding:1; /* End alignment padding is supported. */
223 unsigned int vf:1; /* This is a VF. */
224 unsigned int tunnel_en:1;
225 /* Whether tunnel stateless offloads are supported. */
226 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
227 unsigned int cqe_comp:1; /* CQE compression is enabled. */
228 unsigned int cqe_pad:1; /* CQE padding is enabled. */
229 unsigned int tso:1; /* Whether TSO is supported. */
230 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
231 unsigned int mr_ext_memseg_en:1;
232 /* Whether memseg should be extended for MR creation. */
233 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
234 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
235 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */
236 unsigned int dv_flow_en:1; /* Enable DV flow. */
237 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
238 unsigned int devx:1; /* Whether devx interface is available or not. */
239 unsigned int dest_tir:1; /* Whether advanced DR API is available. */
241 unsigned int enabled:1; /* Whether MPRQ is enabled. */
242 unsigned int stride_num_n; /* Number of strides. */
243 unsigned int min_stride_size_n; /* Min size of a stride. */
244 unsigned int max_stride_size_n; /* Max size of a stride. */
245 unsigned int max_memcpy_len;
246 /* Maximum packet size to memcpy Rx packets. */
247 unsigned int min_rxqs_num;
248 /* Rx queue count threshold to enable MPRQ. */
249 } mprq; /* Configurations for Multi-Packet RQ. */
250 int mps; /* Multi-packet send supported mode. */
251 unsigned int flow_prio; /* Number of flow priorities. */
252 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
253 unsigned int ind_table_max_size; /* Maximum indirection table size. */
254 unsigned int max_dump_files_num; /* Maximum dump files per queue. */
255 int txqs_inline; /* Queue number threshold for inlining. */
256 int txq_inline_min; /* Minimal amount of data bytes to inline. */
257 int txq_inline_max; /* Max packet size for inlining with SEND. */
258 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */
259 struct mlx5_hca_attr hca_attr; /* HCA attributes. */
260 struct mlx5_lro_config lro; /* LRO configuration. */
263 struct mlx5_devx_wq_attr {
265 uint32_t wq_signature:1;
266 uint32_t end_padding_mode:2;
268 uint32_t hds_skip_first_sge:1;
269 uint32_t log2_hds_buf_size:3;
270 uint32_t page_offset:5;
273 uint32_t uar_page:24;
277 uint32_t log_wq_stride:4;
278 uint32_t log_wq_pg_sz:5;
279 uint32_t log_wq_sz:5;
280 uint32_t dbr_umem_valid:1;
281 uint32_t wq_umem_valid:1;
282 uint32_t log_hairpin_num_packets:5;
283 uint32_t log_hairpin_data_sz:5;
284 uint32_t single_wqe_log_num_of_strides:4;
285 uint32_t two_byte_shift_en:1;
286 uint32_t single_stride_log_num_of_bytes:3;
287 uint32_t dbr_umem_id;
289 uint64_t wq_umem_offset;
292 /* Create RQ attributes structure, used by create RQ operation. */
293 struct mlx5_devx_create_rq_attr {
295 uint32_t delay_drop_en:1;
296 uint32_t scatter_fcs:1;
298 uint32_t mem_rq_type:4;
300 uint32_t flush_in_error_en:1;
302 uint32_t user_index:24;
304 uint32_t counter_set_id:8;
306 struct mlx5_devx_wq_attr wq_attr;
309 /* Modify RQ attributes structure, used by modify RQ operation. */
310 struct mlx5_devx_modify_rq_attr {
312 uint32_t rq_state:4; /* Current RQ state. */
313 uint32_t state:4; /* Required RQ state. */
314 uint32_t scatter_fcs:1;
316 uint32_t counter_set_id:8;
317 uint32_t hairpin_peer_sq:24;
318 uint32_t hairpin_peer_vhca:16;
319 uint64_t modify_bitmask;
320 uint32_t lwm:16; /* Contained WQ lwm. */
323 struct mlx5_rx_hash_field_select {
324 uint32_t l3_prot_type:1;
325 uint32_t l4_prot_type:1;
326 uint32_t selected_fields:30;
329 /* TIR attributes structure, used by TIR operations. */
330 struct mlx5_devx_tir_attr {
331 uint32_t disp_type:4;
332 uint32_t lro_timeout_period_usecs:16;
333 uint32_t lro_enable_mask:4;
334 uint32_t lro_max_msg_sz:8;
335 uint32_t inline_rqn:24;
336 uint32_t rx_hash_symmetric:1;
337 uint32_t tunneled_offload_en:1;
338 uint32_t indirect_table:24;
339 uint32_t rx_hash_fn:4;
340 uint32_t self_lb_block:2;
341 uint32_t transport_domain:24;
342 uint32_t rx_hash_toeplitz_key[10];
343 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer;
344 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner;
348 * Type of object being allocated.
350 enum mlx5_verbs_alloc_type {
351 MLX5_VERBS_ALLOC_TYPE_NONE,
352 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
353 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
357 * Verbs allocator needs a context to know in the callback which kind of
358 * resources it is allocating.
360 struct mlx5_verbs_alloc_ctx {
361 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
362 const void *obj; /* Pointer to the DPDK object. */
365 LIST_HEAD(mlx5_mr_list, mlx5_mr);
367 /* Flow drop context necessary due to Verbs API. */
369 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
370 struct mlx5_rxq_ibv *rxq; /* Verbs Rx queue. */
373 #define MLX5_COUNTERS_PER_POOL 512
374 #define MLX5_MAX_PENDING_QUERIES 4
376 struct mlx5_flow_counter_pool;
378 struct flow_counter_stats {
383 /* Counters information. */
384 struct mlx5_flow_counter {
385 TAILQ_ENTRY(mlx5_flow_counter) next;
386 /**< Pointer to the next flow counter structure. */
387 uint32_t shared:1; /**< Share counter ID with other flow rules. */
389 /**< Whether the counter was allocated by batch command. */
390 uint32_t ref_cnt:30; /**< Reference counter. */
391 uint32_t id; /**< Counter ID. */
392 union { /**< Holds the counters for the rule. */
393 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42)
394 struct ibv_counter_set *cs;
395 #elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
396 struct ibv_counters *cs;
398 struct mlx5_devx_obj *dcs; /**< Counter Devx object. */
399 struct mlx5_flow_counter_pool *pool; /**< The counter pool. */
402 uint64_t hits; /**< Reset value of hits packets. */
403 int64_t query_gen; /**< Generation of the last release. */
405 uint64_t bytes; /**< Reset value of bytes. */
406 void *action; /**< Pointer to the dv action. */
409 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter);
411 /* Counter pool structure - query is in pool resolution. */
412 struct mlx5_flow_counter_pool {
413 TAILQ_ENTRY(mlx5_flow_counter_pool) next;
414 struct mlx5_counters counters; /* Free counter list. */
416 struct mlx5_devx_obj *min_dcs;
417 rte_atomic64_t a64_dcs;
419 /* The devx object of the minimum counter ID. */
420 rte_atomic64_t query_gen;
421 uint32_t n_counters: 16; /* Number of devx allocated counters. */
422 rte_spinlock_t sl; /* The pool lock. */
423 struct mlx5_counter_stats_raw *raw;
424 struct mlx5_counter_stats_raw *raw_hw; /* The raw on HW working. */
425 struct mlx5_flow_counter counters_raw[]; /* The pool counters memory. */
428 struct mlx5_counter_stats_raw;
430 /* Memory management structure for group of counter statistics raws. */
431 struct mlx5_counter_stats_mem_mng {
432 LIST_ENTRY(mlx5_counter_stats_mem_mng) next;
433 struct mlx5_counter_stats_raw *raws;
434 struct mlx5_devx_obj *dm;
435 struct mlx5dv_devx_umem *umem;
438 /* Raw memory structure for the counter statistics values of a pool. */
439 struct mlx5_counter_stats_raw {
440 LIST_ENTRY(mlx5_counter_stats_raw) next;
442 struct mlx5_counter_stats_mem_mng *mem_mng;
443 volatile struct flow_counter_stats *data;
446 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool);
448 /* Container structure for counter pools. */
449 struct mlx5_pools_container {
450 rte_atomic16_t n_valid; /* Number of valid pools. */
451 uint16_t n; /* Number of pools. */
452 struct mlx5_counter_pools pool_list; /* Counter pool list. */
453 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */
454 struct mlx5_counter_stats_mem_mng *init_mem_mng;
455 /* Hold the memory management for the next allocated pools raws. */
458 /* Counter global management structure. */
459 struct mlx5_flow_counter_mng {
460 uint8_t mhi[2]; /* master \ host container index. */
461 struct mlx5_pools_container ccont[2 * 2];
462 /* 2 containers for single and for batch for double-buffer. */
463 struct mlx5_counters flow_counters; /* Legacy flow counter list. */
464 uint8_t pending_queries;
467 uint8_t query_thread_on;
468 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs;
469 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws;
472 /* Per port data of shared IB device. */
473 struct mlx5_ibv_shared_port {
476 * Interrupt handler port_id. Used by shared interrupt
477 * handler to find the corresponding rte_eth device
478 * by IB port index. If value is equal or greater
479 * RTE_MAX_ETHPORTS it means there is no subhandler
480 * installed for specified IB port index.
484 /* Table structure. */
485 struct mlx5_flow_tbl_resource {
486 void *obj; /**< Pointer to DR table object. */
487 rte_atomic32_t refcnt; /**< Reference counter. */
490 #define MLX5_MAX_TABLES 1024
491 #define MLX5_MAX_TABLES_FDB 32
492 #define MLX5_GROUP_FACTOR 1
495 * Shared Infiniband device context for Master/Representors
496 * which belong to same IB device with multiple IB ports.
498 struct mlx5_ibv_shared {
499 LIST_ENTRY(mlx5_ibv_shared) next;
501 uint32_t devx:1; /* Opened with DV. */
502 uint32_t max_port; /* Maximal IB device port index. */
503 struct ibv_context *ctx; /* Verbs/DV context. */
504 struct ibv_pd *pd; /* Protection Domain. */
505 uint32_t tdn; /* Transport Domain number. */
506 char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */
507 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
508 struct ibv_device_attr_ex device_attr; /* Device properties. */
509 struct rte_pci_device *pci_dev; /* Backend PCI device. */
510 LIST_ENTRY(mlx5_ibv_shared) mem_event_cb;
511 /**< Called by memory event callback. */
513 uint32_t dev_gen; /* Generation number to flush local caches. */
514 rte_rwlock_t rwlock; /* MR Lock. */
515 struct mlx5_mr_btree cache; /* Global MR cache table. */
516 struct mlx5_mr_list mr_list; /* Registered MR list. */
517 struct mlx5_mr_list mr_free_list; /* Freed MR list. */
519 /* Shared DV/DR flow data section. */
520 pthread_mutex_t dv_mutex; /* DV context mutex. */
521 uint32_t dv_refcnt; /* DV/DR data reference counter. */
522 void *fdb_domain; /* FDB Direct Rules name space handle. */
523 struct mlx5_flow_tbl_resource fdb_tbl[MLX5_MAX_TABLES_FDB];
524 /* FDB Direct Rules tables. */
525 void *rx_domain; /* RX Direct Rules name space handle. */
526 struct mlx5_flow_tbl_resource rx_tbl[MLX5_MAX_TABLES];
527 /* RX Direct Rules tables. */
528 void *tx_domain; /* TX Direct Rules name space handle. */
529 struct mlx5_flow_tbl_resource tx_tbl[MLX5_MAX_TABLES];
530 void *esw_drop_action; /* Pointer to DR E-Switch drop action. */
531 /* TX Direct Rules tables/ */
532 LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers;
533 LIST_HEAD(encap_decap, mlx5_flow_dv_encap_decap_resource) encaps_decaps;
534 LIST_HEAD(modify_cmd, mlx5_flow_dv_modify_hdr_resource) modify_cmds;
535 LIST_HEAD(tag, mlx5_flow_dv_tag_resource) tags;
536 LIST_HEAD(jump, mlx5_flow_dv_jump_tbl_resource) jump_tbl;
537 LIST_HEAD(port_id_action_list, mlx5_flow_dv_port_id_action_resource)
538 port_id_action_list; /* List of port ID actions. */
539 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */
540 /* Shared interrupt handler section. */
541 pthread_mutex_t intr_mutex; /* Interrupt config mutex. */
542 uint32_t intr_cnt; /* Interrupt handler reference counter. */
543 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */
544 struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */
545 struct mlx5dv_devx_cmd_comp *devx_comp; /* DEVX async comp obj. */
546 struct mlx5_ibv_shared_port port[]; /* per device port data array. */
549 /* Per-process private structure. */
550 struct mlx5_proc_priv {
552 /* Size of UAR register table. */
554 /* Table of UAR registers for each process. */
557 #define MLX5_PROC_PRIV(port_id) \
558 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private)
561 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
562 struct mlx5_ibv_shared *sh; /* Shared IB device context. */
563 uint32_t ibv_port; /* IB device port number. */
564 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
565 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
566 /* Bit-field of MAC addresses owned by the PMD. */
567 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
568 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
569 /* Device properties. */
570 uint16_t mtu; /* Configured MTU. */
571 unsigned int isolated:1; /* Whether isolated mode is enabled. */
572 unsigned int representor:1; /* Device is a port representor. */
573 unsigned int master:1; /* Device is a E-Switch master. */
574 unsigned int dr_shared:1; /* DV/DR data is shared. */
575 unsigned int counter_fallback:1; /* Use counter fallback management. */
576 uint16_t domain_id; /* Switch domain identifier. */
577 uint16_t vport_id; /* Associated VF vport index (if any). */
578 int32_t representor_id; /* Port representor identifier. */
579 unsigned int if_index; /* Associated kernel network device index. */
581 unsigned int rxqs_n; /* RX queues array size. */
582 unsigned int txqs_n; /* TX queues array size. */
583 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
584 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
585 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
586 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
587 unsigned int (*reta_idx)[]; /* RETA index table. */
588 unsigned int reta_idx_n; /* RETA index size. */
589 struct mlx5_drop drop_queue; /* Flow drop queues. */
590 struct mlx5_flows flows; /* RTE Flow rules. */
591 struct mlx5_flows ctrl_flows; /* Control flow rules. */
592 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
593 LIST_HEAD(rxqibv, mlx5_rxq_ibv) rxqsibv; /* Verbs Rx queues. */
594 LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */
595 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
596 LIST_HEAD(txqibv, mlx5_txq_ibv) txqsibv; /* Verbs Tx queues. */
597 /* Verbs Indirection tables. */
598 LIST_HEAD(ind_tables, mlx5_ind_table_ibv) ind_tbls;
599 /* Pointer to next element. */
600 rte_atomic32_t refcnt; /**< Reference counter. */
601 struct ibv_flow_action *verbs_action;
602 /**< Verbs modify header action object. */
603 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
604 /* Tags resources cache. */
605 uint32_t link_speed_capa; /* Link speed capabilities. */
606 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
607 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
608 struct mlx5_dev_config config; /* Device configuration. */
609 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
610 /* Context for Verbs allocator. */
611 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
612 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
613 uint32_t nl_sn; /* Netlink message sequence number. */
615 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
616 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
617 /* UAR same-page access control required in 32bit implementations. */
621 #define PORT_ID(priv) ((priv)->dev_data->port_id)
622 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
626 int mlx5_getenv_int(const char *);
627 int mlx5_proc_priv_init(struct rte_eth_dev *dev);
631 int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]);
632 int mlx5_get_master_ifname(const char *ibdev_path, char (*ifname)[IF_NAMESIZE]);
633 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
634 int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr);
635 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
636 int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep,
638 int mlx5_dev_configure(struct rte_eth_dev *dev);
639 void mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
640 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock);
641 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
642 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
643 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
644 int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status);
645 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
646 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
647 struct rte_eth_fc_conf *fc_conf);
648 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
649 struct rte_eth_fc_conf *fc_conf);
650 int mlx5_ibv_device_to_pci_addr(const struct ibv_device *device,
651 struct rte_pci_addr *pci_addr);
652 void mlx5_dev_link_status_handler(void *arg);
653 void mlx5_dev_interrupt_handler(void *arg);
654 void mlx5_dev_interrupt_handler_devx(void *arg);
655 void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev);
656 void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev);
657 int mlx5_set_link_down(struct rte_eth_dev *dev);
658 int mlx5_set_link_up(struct rte_eth_dev *dev);
659 int mlx5_is_removed(struct rte_eth_dev *dev);
660 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
661 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
662 unsigned int mlx5_dev_to_port_id(const struct rte_device *dev,
664 unsigned int port_list_n);
665 int mlx5_port_to_eswitch_info(uint16_t port, uint16_t *es_domain_id,
666 uint16_t *es_port_id);
667 int mlx5_sysfs_switch_info(unsigned int ifindex,
668 struct mlx5_switch_info *info);
669 void mlx5_sysfs_check_switch_info(bool device_dir,
670 struct mlx5_switch_info *switch_info);
671 void mlx5_nl_check_switch_info(bool nun_vf_set,
672 struct mlx5_switch_info *switch_info);
673 void mlx5_translate_port_name(const char *port_name_in,
674 struct mlx5_switch_info *port_info_out);
675 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle,
676 rte_intr_callback_fn cb_fn, void *cb_arg);
680 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]);
681 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
682 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
683 uint32_t index, uint32_t vmdq);
684 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);
685 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
686 struct rte_ether_addr *mc_addr_set,
687 uint32_t nb_mc_addr);
691 int mlx5_rss_hash_update(struct rte_eth_dev *dev,
692 struct rte_eth_rss_conf *rss_conf);
693 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
694 struct rte_eth_rss_conf *rss_conf);
695 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
696 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
697 struct rte_eth_rss_reta_entry64 *reta_conf,
699 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
700 struct rte_eth_rss_reta_entry64 *reta_conf,
705 void mlx5_promiscuous_enable(struct rte_eth_dev *dev);
706 void mlx5_promiscuous_disable(struct rte_eth_dev *dev);
707 void mlx5_allmulticast_enable(struct rte_eth_dev *dev);
708 void mlx5_allmulticast_disable(struct rte_eth_dev *dev);
712 void mlx5_stats_init(struct rte_eth_dev *dev);
713 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
714 void mlx5_stats_reset(struct rte_eth_dev *dev);
715 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
717 void mlx5_xstats_reset(struct rte_eth_dev *dev);
718 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
719 struct rte_eth_xstat_name *xstats_names,
724 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
725 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
726 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
730 int mlx5_dev_start(struct rte_eth_dev *dev);
731 void mlx5_dev_stop(struct rte_eth_dev *dev);
732 int mlx5_traffic_enable(struct rte_eth_dev *dev);
733 void mlx5_traffic_disable(struct rte_eth_dev *dev);
734 int mlx5_traffic_restart(struct rte_eth_dev *dev);
738 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
739 void mlx5_flow_print(struct rte_flow *flow);
740 int mlx5_flow_validate(struct rte_eth_dev *dev,
741 const struct rte_flow_attr *attr,
742 const struct rte_flow_item items[],
743 const struct rte_flow_action actions[],
744 struct rte_flow_error *error);
745 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
746 const struct rte_flow_attr *attr,
747 const struct rte_flow_item items[],
748 const struct rte_flow_action actions[],
749 struct rte_flow_error *error);
750 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
751 struct rte_flow_error *error);
752 void mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list);
753 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
754 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
755 const struct rte_flow_action *action, void *data,
756 struct rte_flow_error *error);
757 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
758 struct rte_flow_error *error);
759 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
760 enum rte_filter_type filter_type,
761 enum rte_filter_op filter_op,
763 int mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list);
764 void mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list);
765 int mlx5_flow_verify(struct rte_eth_dev *dev);
766 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
767 struct rte_flow_item_eth *eth_spec,
768 struct rte_flow_item_eth *eth_mask,
769 struct rte_flow_item_vlan *vlan_spec,
770 struct rte_flow_item_vlan *vlan_mask);
771 int mlx5_ctrl_flow(struct rte_eth_dev *dev,
772 struct rte_flow_item_eth *eth_spec,
773 struct rte_flow_item_eth *eth_mask);
774 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev);
775 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev);
776 void mlx5_flow_async_pool_query_handle(struct mlx5_ibv_shared *sh,
777 uint64_t async_id, int status);
778 void mlx5_set_query_alarm(struct mlx5_ibv_shared *sh);
779 void mlx5_flow_query_alarm(void *arg);
782 void mlx5_mp_req_start_rxtx(struct rte_eth_dev *dev);
783 void mlx5_mp_req_stop_rxtx(struct rte_eth_dev *dev);
784 int mlx5_mp_req_mr_create(struct rte_eth_dev *dev, uintptr_t addr);
785 int mlx5_mp_req_verbs_cmd_fd(struct rte_eth_dev *dev);
786 int mlx5_mp_req_queue_state_modify(struct rte_eth_dev *dev,
787 struct mlx5_mp_arg_queue_state_modify *sm);
788 int mlx5_mp_init_primary(void);
789 void mlx5_mp_uninit_primary(void);
790 int mlx5_mp_init_secondary(void);
791 void mlx5_mp_uninit_secondary(void);
795 int mlx5_nl_init(int protocol);
796 int mlx5_nl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
798 int mlx5_nl_mac_addr_remove(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
800 void mlx5_nl_mac_addr_sync(struct rte_eth_dev *dev);
801 void mlx5_nl_mac_addr_flush(struct rte_eth_dev *dev);
802 int mlx5_nl_promisc(struct rte_eth_dev *dev, int enable);
803 int mlx5_nl_allmulti(struct rte_eth_dev *dev, int enable);
804 unsigned int mlx5_nl_portnum(int nl, const char *name);
805 unsigned int mlx5_nl_ifindex(int nl, const char *name, uint32_t pindex);
806 int mlx5_nl_switch_info(int nl, unsigned int ifindex,
807 struct mlx5_switch_info *info);
809 /* mlx5_devx_cmds.c */
811 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx,
813 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj);
814 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
815 int clear, uint32_t n_counters,
816 uint64_t *pkts, uint64_t *bytes,
817 uint32_t mkey, void *addr,
818 struct mlx5dv_devx_cmd_comp *cmd_comp,
820 int mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx,
821 struct mlx5_hca_attr *attr);
822 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(struct ibv_context *ctx,
823 struct mlx5_devx_mkey_attr *attr);
824 int mlx5_devx_get_out_command_status(void *out);
825 int mlx5_devx_cmd_qp_query_tis_td(struct ibv_qp *qp, uint32_t tis_num,
827 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(struct ibv_context *ctx,
828 struct mlx5_devx_create_rq_attr *rq_attr,
830 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
831 struct mlx5_devx_modify_rq_attr *rq_attr);
832 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(struct ibv_context *ctx,
833 struct mlx5_devx_tir_attr *tir_attr);
835 #endif /* RTE_PMD_MLX5_H_ */