4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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34 #ifndef RTE_PMD_MLX5_H_
35 #define RTE_PMD_MLX5_H_
41 #include <netinet/in.h>
42 #include <sys/queue.h>
45 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
47 #pragma GCC diagnostic ignored "-Wpedantic"
49 #include <infiniband/verbs.h>
51 #pragma GCC diagnostic error "-Wpedantic"
55 #include <rte_ether.h>
56 #include <rte_ethdev.h>
57 #include <rte_spinlock.h>
58 #include <rte_interrupts.h>
59 #include <rte_errno.h>
62 #include "mlx5_utils.h"
63 #include "mlx5_rxtx.h"
64 #include "mlx5_autoconf.h"
65 #include "mlx5_defs.h"
68 PCI_VENDOR_ID_MELLANOX = 0x15b3,
72 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
73 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
74 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
75 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
76 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
77 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
78 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
79 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
82 struct mlx5_xstats_ctrl {
83 /* Number of device stats. */
85 /* Index in the device counters table. */
86 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
87 uint64_t base[MLX5_MAX_XSTATS];
91 TAILQ_HEAD(mlx5_flows, rte_flow);
94 struct rte_eth_dev *dev; /* Ethernet device of master process. */
95 struct ibv_context *ctx; /* Verbs context. */
96 struct ibv_device_attr_ex device_attr; /* Device properties. */
97 struct ibv_pd *pd; /* Protection Domain. */
98 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
100 * MAC addresses array and configuration bit-field.
101 * An extra entry that cannot be modified by the DPDK is reserved
102 * for broadcast frames (destination MAC address ff:ff:ff:ff:ff:ff).
104 struct ether_addr mac[MLX5_MAX_MAC_ADDRESSES];
105 BITFIELD_DECLARE(mac_configured, uint32_t, MLX5_MAX_MAC_ADDRESSES);
106 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
107 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
108 /* Device properties. */
109 uint16_t mtu; /* Configured MTU. */
110 uint8_t port; /* Physical port number. */
111 unsigned int hw_csum:1; /* Checksum offload is supported. */
112 unsigned int hw_csum_l2tun:1; /* Same for L2 tunnels. */
113 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
114 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
115 unsigned int hw_padding:1; /* End alignment padding is supported. */
116 unsigned int sriov:1; /* This is a VF or PF with VF devices. */
117 unsigned int mps:2; /* Multi-packet send mode (0: disabled). */
118 unsigned int mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
119 unsigned int cqe_comp:1; /* Whether CQE compression is enabled. */
120 unsigned int pending_alarm:1; /* An alarm is pending. */
121 unsigned int tso:1; /* Whether TSO is supported. */
122 unsigned int tunnel_en:1;
123 unsigned int isolated:1; /* Whether isolated mode is enabled. */
124 unsigned int tx_vec_en:1; /* Whether Tx vector is enabled. */
125 unsigned int rx_vec_en:1; /* Whether Rx vector is enabled. */
126 /* Whether Tx offloads for tunneled packets are supported. */
127 unsigned int max_tso_payload_sz; /* Maximum TCP payload for TSO. */
128 unsigned int txq_inline; /* Maximum packet size for inlining. */
129 unsigned int txqs_inline; /* Queue number threshold for inlining. */
130 unsigned int inline_max_packet_sz; /* Max packet size for inlining. */
132 unsigned int rxqs_n; /* RX queues array size. */
133 unsigned int txqs_n; /* TX queues array size. */
134 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
135 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
136 /* Indirection tables referencing all RX WQs. */
137 struct ibv_rwq_ind_table *(*ind_tables)[];
138 unsigned int ind_tables_n; /* Number of indirection tables. */
139 unsigned int ind_table_max_size; /* Maximum indirection table size. */
140 /* Hash RX QPs feeding the indirection table. */
141 struct hash_rxq (*hash_rxqs)[];
142 unsigned int hash_rxqs_n; /* Hash RX QPs array size. */
143 /* RSS configuration array indexed by hash RX queue type. */
144 struct rte_eth_rss_conf *(*rss_conf)[];
145 uint64_t rss_hf; /* RSS DPDK bit field of active RSS. */
146 struct rte_intr_handle intr_handle; /* Interrupt handler. */
147 unsigned int (*reta_idx)[]; /* RETA index table. */
148 unsigned int reta_idx_n; /* RETA index size. */
149 struct mlx5_hrxq_drop *flow_drop_queue; /* Flow drop queue. */
150 struct mlx5_flows flows; /* RTE Flow rules. */
151 struct mlx5_flows ctrl_flows; /* Control flow rules. */
152 LIST_HEAD(mr, mlx5_mr) mr; /* Memory region. */
153 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
154 LIST_HEAD(rxqibv, mlx5_rxq_ibv) rxqsibv; /* Verbs Rx queues. */
155 LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */
156 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
157 LIST_HEAD(txqibv, mlx5_txq_ibv) txqsibv; /* Verbs Tx queues. */
158 /* Verbs Indirection tables. */
159 LIST_HEAD(ind_tables, mlx5_ind_table_ibv) ind_tbls;
160 uint32_t link_speed_capa; /* Link speed capabilities. */
161 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
162 rte_spinlock_t lock; /* Lock for control functions. */
163 int primary_socket; /* Unix socket for primary process. */
164 struct rte_intr_handle intr_handle_socket; /* Interrupt handler. */
168 * Lock private structure to protect it from concurrent access in the
172 * Pointer to private structure.
175 priv_lock(struct priv *priv)
177 rte_spinlock_lock(&priv->lock);
181 * Unlock private structure.
184 * Pointer to private structure.
187 priv_unlock(struct priv *priv)
189 rte_spinlock_unlock(&priv->lock);
194 int mlx5_getenv_int(const char *);
198 struct priv *mlx5_get_priv(struct rte_eth_dev *dev);
199 int mlx5_is_secondary(void);
200 int priv_get_ifname(const struct priv *, char (*)[IF_NAMESIZE]);
201 int priv_ifreq(const struct priv *, int req, struct ifreq *);
202 int priv_is_ib_cntr(const char *);
203 int priv_get_cntr_sysfs(struct priv *, const char *, uint64_t *);
204 int priv_get_num_vfs(struct priv *, uint16_t *);
205 int priv_get_mtu(struct priv *, uint16_t *);
206 int priv_set_flags(struct priv *, unsigned int, unsigned int);
207 int mlx5_dev_configure(struct rte_eth_dev *);
208 void mlx5_dev_infos_get(struct rte_eth_dev *, struct rte_eth_dev_info *);
209 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
210 int mlx5_link_update(struct rte_eth_dev *, int);
211 int mlx5_dev_set_mtu(struct rte_eth_dev *, uint16_t);
212 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *, struct rte_eth_fc_conf *);
213 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *, struct rte_eth_fc_conf *);
214 int mlx5_ibv_device_to_pci_addr(const struct ibv_device *,
215 struct rte_pci_addr *);
216 void mlx5_dev_link_status_handler(void *);
217 void mlx5_dev_interrupt_handler(void *);
218 void priv_dev_interrupt_handler_uninstall(struct priv *, struct rte_eth_dev *);
219 void priv_dev_interrupt_handler_install(struct priv *, struct rte_eth_dev *);
220 int mlx5_set_link_down(struct rte_eth_dev *dev);
221 int mlx5_set_link_up(struct rte_eth_dev *dev);
222 void priv_dev_select_tx_function(struct priv *priv, struct rte_eth_dev *dev);
223 void priv_dev_select_rx_function(struct priv *priv, struct rte_eth_dev *dev);
227 int priv_get_mac(struct priv *, uint8_t (*)[ETHER_ADDR_LEN]);
228 void hash_rxq_mac_addrs_del(struct hash_rxq *);
229 void priv_mac_addrs_disable(struct priv *);
230 void mlx5_mac_addr_remove(struct rte_eth_dev *, uint32_t);
231 int hash_rxq_mac_addrs_add(struct hash_rxq *);
232 int priv_mac_addr_add(struct priv *, unsigned int,
233 const uint8_t (*)[ETHER_ADDR_LEN]);
234 int priv_mac_addrs_enable(struct priv *);
235 int mlx5_mac_addr_add(struct rte_eth_dev *, struct ether_addr *, uint32_t,
237 void mlx5_mac_addr_set(struct rte_eth_dev *, struct ether_addr *);
241 int rss_hash_rss_conf_new_key(struct priv *, const uint8_t *, unsigned int,
243 int mlx5_rss_hash_update(struct rte_eth_dev *, struct rte_eth_rss_conf *);
244 int mlx5_rss_hash_conf_get(struct rte_eth_dev *, struct rte_eth_rss_conf *);
245 int priv_rss_reta_index_resize(struct priv *, unsigned int);
246 int mlx5_dev_rss_reta_query(struct rte_eth_dev *,
247 struct rte_eth_rss_reta_entry64 *, uint16_t);
248 int mlx5_dev_rss_reta_update(struct rte_eth_dev *,
249 struct rte_eth_rss_reta_entry64 *, uint16_t);
253 int priv_special_flow_enable(struct priv *, enum hash_rxq_flow_type);
254 void priv_special_flow_disable(struct priv *, enum hash_rxq_flow_type);
255 int priv_special_flow_enable_all(struct priv *);
256 void priv_special_flow_disable_all(struct priv *);
257 void mlx5_promiscuous_enable(struct rte_eth_dev *);
258 void mlx5_promiscuous_disable(struct rte_eth_dev *);
259 void mlx5_allmulticast_enable(struct rte_eth_dev *);
260 void mlx5_allmulticast_disable(struct rte_eth_dev *);
264 void priv_xstats_init(struct priv *);
265 void mlx5_stats_get(struct rte_eth_dev *, struct rte_eth_stats *);
266 void mlx5_stats_reset(struct rte_eth_dev *);
267 int mlx5_xstats_get(struct rte_eth_dev *,
268 struct rte_eth_xstat *, unsigned int);
269 void mlx5_xstats_reset(struct rte_eth_dev *);
270 int mlx5_xstats_get_names(struct rte_eth_dev *,
271 struct rte_eth_xstat_name *, unsigned int);
275 int mlx5_vlan_filter_set(struct rte_eth_dev *, uint16_t, int);
276 void mlx5_vlan_offload_set(struct rte_eth_dev *, int);
277 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *, uint16_t, int);
281 int mlx5_dev_start(struct rte_eth_dev *);
282 void mlx5_dev_stop(struct rte_eth_dev *);
286 int mlx5_dev_filter_ctrl(struct rte_eth_dev *, enum rte_filter_type,
287 enum rte_filter_op, void *);
288 int mlx5_flow_validate(struct rte_eth_dev *, const struct rte_flow_attr *,
289 const struct rte_flow_item [],
290 const struct rte_flow_action [],
291 struct rte_flow_error *);
292 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *,
293 const struct rte_flow_attr *,
294 const struct rte_flow_item [],
295 const struct rte_flow_action [],
296 struct rte_flow_error *);
297 int mlx5_flow_destroy(struct rte_eth_dev *, struct rte_flow *,
298 struct rte_flow_error *);
299 void priv_flow_flush(struct priv *, struct mlx5_flows *);
300 int mlx5_flow_flush(struct rte_eth_dev *, struct rte_flow_error *);
301 int mlx5_flow_isolate(struct rte_eth_dev *, int, struct rte_flow_error *);
302 int priv_flow_start(struct priv *, struct mlx5_flows *);
303 void priv_flow_stop(struct priv *, struct mlx5_flows *);
304 int priv_flow_verify(struct priv *);
305 int mlx5_ctrl_flow(struct rte_eth_dev *, struct rte_flow_item_eth *,
306 struct rte_flow_item_eth *, unsigned int);
310 int priv_socket_init(struct priv *priv);
311 int priv_socket_uninit(struct priv *priv);
312 void priv_socket_handle(struct priv *priv);
313 int priv_socket_connect(struct priv *priv);
317 struct mlx5_mr *priv_mr_new(struct priv *, struct rte_mempool *);
318 struct mlx5_mr *priv_mr_get(struct priv *, struct rte_mempool *);
319 int priv_mr_release(struct priv *, struct mlx5_mr *);
320 int priv_mr_verify(struct priv *);
322 #endif /* RTE_PMD_MLX5_H_ */