1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
21 #pragma GCC diagnostic error "-Wpedantic"
24 #include <rte_atomic.h>
25 #include <rte_alarm.h>
30 /* Pattern outer Layer bits. */
31 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
32 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
33 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
34 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
35 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
36 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
38 /* Pattern inner Layer bits. */
39 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
40 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
41 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
42 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
43 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
44 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
46 /* Pattern tunnel Layer bits. */
47 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
48 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
49 #define MLX5_FLOW_LAYER_GRE (1u << 14)
50 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
51 /* List of tunnel Layer bits continued below. */
53 /* General pattern items bits. */
54 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
55 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
57 /* Pattern MISC bits. */
58 #define MLX5_FLOW_LAYER_ICMP (1u << 18)
59 #define MLX5_FLOW_LAYER_ICMP6 (1u << 19)
60 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 20)
62 /* Pattern tunnel Layer bits (continued). */
63 #define MLX5_FLOW_LAYER_IPIP (1u << 21)
64 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 22)
65 #define MLX5_FLOW_LAYER_NVGRE (1u << 23)
68 #define MLX5_FLOW_LAYER_OUTER_L3 \
69 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
70 #define MLX5_FLOW_LAYER_OUTER_L4 \
71 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
72 #define MLX5_FLOW_LAYER_OUTER \
73 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
74 MLX5_FLOW_LAYER_OUTER_L4)
76 /* LRO support mask, i.e. flow contains IPv4/IPv6 and TCP. */
77 #define MLX5_FLOW_LAYER_IPV4_LRO \
78 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L4_TCP)
79 #define MLX5_FLOW_LAYER_IPV6_LRO \
80 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_OUTER_L4_TCP)
83 #define MLX5_FLOW_LAYER_TUNNEL \
84 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
85 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
86 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP)
89 #define MLX5_FLOW_LAYER_INNER_L3 \
90 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
91 #define MLX5_FLOW_LAYER_INNER_L4 \
92 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
93 #define MLX5_FLOW_LAYER_INNER \
94 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
95 MLX5_FLOW_LAYER_INNER_L4)
98 #define MLX5_FLOW_LAYER_L2 \
99 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
100 #define MLX5_FLOW_LAYER_L3_IPV4 \
101 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
102 #define MLX5_FLOW_LAYER_L3_IPV6 \
103 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
104 #define MLX5_FLOW_LAYER_L3 \
105 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
106 #define MLX5_FLOW_LAYER_L4 \
107 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
110 #define MLX5_FLOW_ACTION_DROP (1u << 0)
111 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
112 #define MLX5_FLOW_ACTION_RSS (1u << 2)
113 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
114 #define MLX5_FLOW_ACTION_MARK (1u << 4)
115 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
116 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
117 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
118 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
119 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
120 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
121 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
122 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
123 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
124 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
125 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
126 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
127 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
128 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
129 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
130 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
131 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
132 #define MLX5_FLOW_ACTION_VXLAN_ENCAP (1u << 22)
133 #define MLX5_FLOW_ACTION_VXLAN_DECAP (1u << 23)
134 #define MLX5_FLOW_ACTION_NVGRE_ENCAP (1u << 24)
135 #define MLX5_FLOW_ACTION_NVGRE_DECAP (1u << 25)
136 #define MLX5_FLOW_ACTION_RAW_ENCAP (1u << 26)
137 #define MLX5_FLOW_ACTION_RAW_DECAP (1u << 27)
138 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 28)
139 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 29)
140 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 30)
141 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 31)
143 #define MLX5_FLOW_FATE_ACTIONS \
144 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
145 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP)
147 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
148 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
149 MLX5_FLOW_ACTION_JUMP)
151 #define MLX5_FLOW_ENCAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_ENCAP | \
152 MLX5_FLOW_ACTION_NVGRE_ENCAP | \
153 MLX5_FLOW_ACTION_RAW_ENCAP | \
154 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
156 #define MLX5_FLOW_DECAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_DECAP | \
157 MLX5_FLOW_ACTION_NVGRE_DECAP | \
158 MLX5_FLOW_ACTION_RAW_DECAP | \
159 MLX5_FLOW_ACTION_OF_POP_VLAN)
161 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
162 MLX5_FLOW_ACTION_SET_IPV4_DST | \
163 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
164 MLX5_FLOW_ACTION_SET_IPV6_DST | \
165 MLX5_FLOW_ACTION_SET_TP_SRC | \
166 MLX5_FLOW_ACTION_SET_TP_DST | \
167 MLX5_FLOW_ACTION_SET_TTL | \
168 MLX5_FLOW_ACTION_DEC_TTL | \
169 MLX5_FLOW_ACTION_SET_MAC_SRC | \
170 MLX5_FLOW_ACTION_SET_MAC_DST | \
171 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
172 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
173 MLX5_FLOW_ACTION_INC_TCP_ACK | \
174 MLX5_FLOW_ACTION_DEC_TCP_ACK)
176 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
177 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
180 #define IPPROTO_MPLS 137
183 /* UDP port number for MPLS */
184 #define MLX5_UDP_PORT_MPLS 6635
186 /* UDP port numbers for VxLAN. */
187 #define MLX5_UDP_PORT_VXLAN 4789
188 #define MLX5_UDP_PORT_VXLAN_GPE 4790
190 /* Priority reserved for default flows. */
191 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
194 * Number of sub priorities.
195 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
196 * matching on the NIC (firmware dependent) L4 most have the higher priority
197 * followed by L3 and ending with L2.
199 #define MLX5_PRIORITY_MAP_L2 2
200 #define MLX5_PRIORITY_MAP_L3 1
201 #define MLX5_PRIORITY_MAP_L4 0
202 #define MLX5_PRIORITY_MAP_MAX 3
204 /* Valid layer type for IPV4 RSS. */
205 #define MLX5_IPV4_LAYER_TYPES \
206 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
207 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
208 ETH_RSS_NONFRAG_IPV4_OTHER)
210 /* IBV hash source bits for IPV4. */
211 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
213 /* Valid layer type for IPV6 RSS. */
214 #define MLX5_IPV6_LAYER_TYPES \
215 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
216 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
217 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
219 /* IBV hash source bits for IPV6. */
220 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
222 enum mlx5_flow_drv_type {
225 MLX5_FLOW_TYPE_VERBS,
229 /* Matcher PRM representation */
230 struct mlx5_flow_dv_match_params {
232 /**< Size of match value. Do NOT split size and key! */
233 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
234 /**< Matcher value. This value is used as the mask or as a key. */
237 /* Matcher structure. */
238 struct mlx5_flow_dv_matcher {
239 LIST_ENTRY(mlx5_flow_dv_matcher) next;
240 /* Pointer to the next element. */
241 rte_atomic32_t refcnt; /**< Reference counter. */
242 void *matcher_object; /**< Pointer to DV matcher */
243 uint16_t crc; /**< CRC of key. */
244 uint16_t priority; /**< Priority of matcher. */
245 uint8_t egress; /**< Egress matcher. */
246 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
247 uint32_t group; /**< The matcher group. */
248 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
251 #define MLX5_ENCAP_MAX_LEN 132
253 /* Encap/decap resource structure. */
254 struct mlx5_flow_dv_encap_decap_resource {
255 LIST_ENTRY(mlx5_flow_dv_encap_decap_resource) next;
256 /* Pointer to next element. */
257 rte_atomic32_t refcnt; /**< Reference counter. */
259 /**< Verbs encap/decap action object. */
260 uint8_t buf[MLX5_ENCAP_MAX_LEN];
262 uint8_t reformat_type;
264 uint64_t flags; /**< Flags for RDMA API. */
267 /* Tag resource structure. */
268 struct mlx5_flow_dv_tag_resource {
269 LIST_ENTRY(mlx5_flow_dv_tag_resource) next;
270 /* Pointer to next element. */
271 rte_atomic32_t refcnt; /**< Reference counter. */
273 /**< Verbs tag action object. */
274 uint32_t tag; /**< the tag value. */
277 /* Number of modification commands. */
278 #define MLX5_MODIFY_NUM 8
280 /* Modify resource structure */
281 struct mlx5_flow_dv_modify_hdr_resource {
282 LIST_ENTRY(mlx5_flow_dv_modify_hdr_resource) next;
283 /* Pointer to next element. */
284 rte_atomic32_t refcnt; /**< Reference counter. */
285 struct ibv_flow_action *verbs_action;
286 /**< Verbs modify header action object. */
287 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
288 uint32_t actions_num; /**< Number of modification actions. */
289 struct mlx5_modification_cmd actions[MLX5_MODIFY_NUM];
290 /**< Modification actions. */
291 uint64_t flags; /**< Flags for RDMA API. */
294 /* Jump action resource structure. */
295 struct mlx5_flow_dv_jump_tbl_resource {
296 LIST_ENTRY(mlx5_flow_dv_jump_tbl_resource) next;
297 /* Pointer to next element. */
298 rte_atomic32_t refcnt; /**< Reference counter. */
299 void *action; /**< Pointer to the rdma core action. */
300 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
301 struct mlx5_flow_tbl_resource *tbl; /**< The target table. */
304 /* Port ID resource structure. */
305 struct mlx5_flow_dv_port_id_action_resource {
306 LIST_ENTRY(mlx5_flow_dv_port_id_action_resource) next;
307 /* Pointer to next element. */
308 rte_atomic32_t refcnt; /**< Reference counter. */
310 /**< Verbs tag action object. */
311 uint32_t port_id; /**< Port ID value. */
314 /* Push VLAN action resource structure */
315 struct mlx5_flow_dv_push_vlan_action_resource {
316 LIST_ENTRY(mlx5_flow_dv_push_vlan_action_resource) next;
317 /* Pointer to next element. */
318 rte_atomic32_t refcnt; /**< Reference counter. */
319 void *action; /**< Direct verbs action object. */
320 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
321 rte_be32_t vlan_tag; /**< VLAN tag value. */
325 * Max number of actions per DV flow.
326 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
327 * In rdma-core file providers/mlx5/verbs.c
329 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
331 /* DV flows structure. */
332 struct mlx5_flow_dv {
333 uint64_t hash_fields; /**< Fields that participate in the hash. */
334 struct mlx5_hrxq *hrxq; /**< Hash Rx queues. */
336 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
337 struct mlx5_flow_dv_match_params value;
338 /**< Holds the value that the packet is compared to. */
339 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
340 /**< Pointer to encap/decap resource in cache. */
341 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
342 /**< Pointer to modify header resource in cache. */
343 struct ibv_flow *flow; /**< Installed flow. */
344 struct mlx5_flow_dv_jump_tbl_resource *jump;
345 /**< Pointer to the jump action resource. */
346 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
347 /**< Pointer to port ID action resource. */
348 struct mlx5_vf_vlan vf_vlan;
349 /**< Structure for VF VLAN workaround. */
350 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
351 /**< Pointer to push VLAN action resource in cache. */
352 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
353 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS];
356 int actions_n; /**< number of actions. */
359 /* Verbs specification header. */
360 struct ibv_spec_header {
361 enum ibv_flow_spec_type type;
365 /** Handles information leading to a drop fate. */
366 struct mlx5_flow_verbs {
367 LIST_ENTRY(mlx5_flow_verbs) next;
368 unsigned int size; /**< Size of the attribute. */
370 struct ibv_flow_attr *attr;
371 /**< Pointer to the Specification buffer. */
372 uint8_t *specs; /**< Pointer to the specifications. */
374 struct ibv_flow *flow; /**< Verbs flow pointer. */
375 struct mlx5_hrxq *hrxq; /**< Hash Rx queue object. */
376 uint64_t hash_fields; /**< Verbs hash Rx queue hash fields. */
377 struct mlx5_vf_vlan vf_vlan;
378 /**< Structure for VF VLAN workaround. */
381 /** Device flow structure. */
383 LIST_ENTRY(mlx5_flow) next;
384 struct rte_flow *flow; /**< Pointer to the main flow. */
386 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
388 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
389 struct mlx5_flow_dv dv;
391 struct mlx5_flow_verbs verbs;
395 /* Flow structure. */
397 TAILQ_ENTRY(rte_flow) next; /**< Pointer to the next flow structure. */
398 enum mlx5_flow_drv_type drv_type; /**< Driver type. */
399 struct mlx5_flow_counter *counter; /**< Holds flow counter. */
400 struct mlx5_flow_dv_tag_resource *tag_resource;
401 /**< pointer to the tag action. */
402 struct rte_flow_action_rss rss;/**< RSS context. */
403 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
404 uint16_t (*queue)[]; /**< Destination queues to redirect traffic to. */
405 LIST_HEAD(dev_flows, mlx5_flow) dev_flows;
406 /**< Device flows that are part of the flow. */
408 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
409 struct mlx5_fdir *fdir; /**< Pointer to associated FDIR if any. */
410 uint8_t ingress; /**< 1 if the flow is ingress. */
411 uint32_t group; /**< The group index. */
412 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
415 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
416 const struct rte_flow_attr *attr,
417 const struct rte_flow_item items[],
418 const struct rte_flow_action actions[],
419 struct rte_flow_error *error);
420 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
421 (const struct rte_flow_attr *attr, const struct rte_flow_item items[],
422 const struct rte_flow_action actions[], struct rte_flow_error *error);
423 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
424 struct mlx5_flow *dev_flow,
425 const struct rte_flow_attr *attr,
426 const struct rte_flow_item items[],
427 const struct rte_flow_action actions[],
428 struct rte_flow_error *error);
429 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
430 struct rte_flow_error *error);
431 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
432 struct rte_flow *flow);
433 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
434 struct rte_flow *flow);
435 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
436 struct rte_flow *flow,
437 const struct rte_flow_action *actions,
439 struct rte_flow_error *error);
440 struct mlx5_flow_driver_ops {
441 mlx5_flow_validate_t validate;
442 mlx5_flow_prepare_t prepare;
443 mlx5_flow_translate_t translate;
444 mlx5_flow_apply_t apply;
445 mlx5_flow_remove_t remove;
446 mlx5_flow_destroy_t destroy;
447 mlx5_flow_query_t query;
450 #define MLX5_CNT_CONTAINER(sh, batch, thread) (&(sh)->cmng.ccont \
451 [(((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
452 #define MLX5_CNT_CONTAINER_UNUSED(sh, batch, thread) (&(sh)->cmng.ccont \
453 [(~((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
457 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, int tunnel,
458 uint64_t layer_types,
459 uint64_t hash_fields);
460 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
461 uint32_t subpriority);
462 const struct rte_flow_action *mlx5_flow_find_action
463 (const struct rte_flow_action *actions,
464 enum rte_flow_action_type action);
465 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
466 const struct rte_flow_attr *attr,
467 struct rte_flow_error *error);
468 int mlx5_flow_validate_action_drop(uint64_t action_flags,
469 const struct rte_flow_attr *attr,
470 struct rte_flow_error *error);
471 int mlx5_flow_validate_action_flag(uint64_t action_flags,
472 const struct rte_flow_attr *attr,
473 struct rte_flow_error *error);
474 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
475 uint64_t action_flags,
476 const struct rte_flow_attr *attr,
477 struct rte_flow_error *error);
478 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
479 uint64_t action_flags,
480 struct rte_eth_dev *dev,
481 const struct rte_flow_attr *attr,
482 struct rte_flow_error *error);
483 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
484 uint64_t action_flags,
485 struct rte_eth_dev *dev,
486 const struct rte_flow_attr *attr,
488 struct rte_flow_error *error);
489 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
490 const struct rte_flow_attr *attributes,
491 struct rte_flow_error *error);
492 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
494 const uint8_t *nic_mask,
496 struct rte_flow_error *error);
497 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
499 struct rte_flow_error *error);
500 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
502 uint8_t target_protocol,
503 struct rte_flow_error *error);
504 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
506 const struct rte_flow_item *gre_item,
507 struct rte_flow_error *error);
508 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
510 const struct rte_flow_item_ipv4 *acc_mask,
511 struct rte_flow_error *error);
512 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
514 const struct rte_flow_item_ipv6 *acc_mask,
515 struct rte_flow_error *error);
516 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
517 const struct rte_flow_item *item,
520 struct rte_flow_error *error);
521 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
523 uint8_t target_protocol,
524 const struct rte_flow_item_tcp *flow_mask,
525 struct rte_flow_error *error);
526 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
528 uint8_t target_protocol,
529 struct rte_flow_error *error);
530 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
532 struct rte_eth_dev *dev,
533 struct rte_flow_error *error);
534 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
536 struct rte_flow_error *error);
537 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
539 struct rte_eth_dev *dev,
540 struct rte_flow_error *error);
541 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
543 uint8_t target_protocol,
544 struct rte_flow_error *error);
545 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
547 uint8_t target_protocol,
548 struct rte_flow_error *error);
549 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
551 uint8_t target_protocol,
552 struct rte_flow_error *error);
553 #endif /* RTE_PMD_MLX5_FLOW_H_ */