1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
11 #include <sys/queue.h>
13 #include <rte_alarm.h>
16 #include <mlx5_glue.h>
21 /* Private rte flow items. */
22 enum mlx5_rte_flow_item_type {
23 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
24 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
25 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
26 MLX5_RTE_FLOW_ITEM_TYPE_VLAN,
27 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL,
30 /* Private (internal) rte flow actions. */
31 enum mlx5_rte_flow_action_type {
32 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
33 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
34 MLX5_RTE_FLOW_ACTION_TYPE_MARK,
35 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
36 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
37 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET,
38 MLX5_RTE_FLOW_ACTION_TYPE_AGE,
41 #define MLX5_INDIRECT_ACTION_TYPE_OFFSET 30
44 MLX5_INDIRECT_ACTION_TYPE_RSS,
45 MLX5_INDIRECT_ACTION_TYPE_AGE,
48 /* Matches on selected register. */
49 struct mlx5_rte_flow_item_tag {
54 /* Modify selected register. */
55 struct mlx5_rte_flow_action_set_tag {
60 struct mlx5_flow_action_copy_mreg {
65 /* Matches on source queue. */
66 struct mlx5_rte_flow_item_tx_queue {
70 /* Feature name to allocate metadata register. */
71 enum mlx5_feature_name {
85 /* Default queue number. */
86 #define MLX5_RSSQ_DEFAULT_NUM 16
88 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
89 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
90 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
91 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
92 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
93 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
95 /* Pattern inner Layer bits. */
96 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
97 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
98 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
99 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
100 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
101 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
103 /* Pattern tunnel Layer bits. */
104 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
105 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
106 #define MLX5_FLOW_LAYER_GRE (1u << 14)
107 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
108 /* List of tunnel Layer bits continued below. */
110 /* General pattern items bits. */
111 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
112 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
113 #define MLX5_FLOW_ITEM_TAG (1u << 18)
114 #define MLX5_FLOW_ITEM_MARK (1u << 19)
116 /* Pattern MISC bits. */
117 #define MLX5_FLOW_LAYER_ICMP (1u << 20)
118 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21)
119 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22)
121 /* Pattern tunnel Layer bits (continued). */
122 #define MLX5_FLOW_LAYER_IPIP (1u << 23)
123 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24)
124 #define MLX5_FLOW_LAYER_NVGRE (1u << 25)
125 #define MLX5_FLOW_LAYER_GENEVE (1u << 26)
128 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)
130 /* Pattern tunnel Layer bits (continued). */
131 #define MLX5_FLOW_LAYER_GTP (1u << 28)
133 /* Pattern eCPRI Layer bit. */
134 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29)
136 /* IPv6 Fragment Extension Header bit. */
137 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30)
138 #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31)
140 /* Pattern tunnel Layer bits (continued). */
141 #define MLX5_FLOW_LAYER_GENEVE_OPT (UINT64_C(1) << 32)
142 #define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33)
145 #define MLX5_FLOW_LAYER_OUTER_L3 \
146 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
147 #define MLX5_FLOW_LAYER_OUTER_L4 \
148 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
149 #define MLX5_FLOW_LAYER_OUTER \
150 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
151 MLX5_FLOW_LAYER_OUTER_L4)
154 #define MLX5_FLOW_LAYER_TUNNEL \
155 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
156 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
157 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
158 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP)
161 #define MLX5_FLOW_LAYER_INNER_L3 \
162 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
163 #define MLX5_FLOW_LAYER_INNER_L4 \
164 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
165 #define MLX5_FLOW_LAYER_INNER \
166 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
167 MLX5_FLOW_LAYER_INNER_L4)
170 #define MLX5_FLOW_LAYER_L2 \
171 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
172 #define MLX5_FLOW_LAYER_L3_IPV4 \
173 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
174 #define MLX5_FLOW_LAYER_L3_IPV6 \
175 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
176 #define MLX5_FLOW_LAYER_L3 \
177 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
178 #define MLX5_FLOW_LAYER_L4 \
179 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
182 #define MLX5_FLOW_ACTION_DROP (1u << 0)
183 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
184 #define MLX5_FLOW_ACTION_RSS (1u << 2)
185 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
186 #define MLX5_FLOW_ACTION_MARK (1u << 4)
187 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
188 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
189 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
190 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
191 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
192 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
193 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
194 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
195 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
196 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
197 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
198 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
199 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
200 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
201 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
202 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
203 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
204 #define MLX5_FLOW_ACTION_ENCAP (1u << 22)
205 #define MLX5_FLOW_ACTION_DECAP (1u << 23)
206 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24)
207 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25)
208 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26)
209 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27)
210 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28)
211 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29)
212 #define MLX5_FLOW_ACTION_SET_META (1ull << 30)
213 #define MLX5_FLOW_ACTION_METER (1ull << 31)
214 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32)
215 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33)
216 #define MLX5_FLOW_ACTION_AGE (1ull << 34)
217 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35)
218 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36)
219 #define MLX5_FLOW_ACTION_TUNNEL_SET (1ull << 37)
220 #define MLX5_FLOW_ACTION_TUNNEL_MATCH (1ull << 38)
221 #define MLX5_FLOW_ACTION_MODIFY_FIELD (1ull << 39)
223 #define MLX5_FLOW_FATE_ACTIONS \
224 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
225 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \
226 MLX5_FLOW_ACTION_DEFAULT_MISS)
228 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
229 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
230 MLX5_FLOW_ACTION_JUMP)
233 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
234 MLX5_FLOW_ACTION_SET_IPV4_DST | \
235 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
236 MLX5_FLOW_ACTION_SET_IPV6_DST | \
237 MLX5_FLOW_ACTION_SET_TP_SRC | \
238 MLX5_FLOW_ACTION_SET_TP_DST | \
239 MLX5_FLOW_ACTION_SET_TTL | \
240 MLX5_FLOW_ACTION_DEC_TTL | \
241 MLX5_FLOW_ACTION_SET_MAC_SRC | \
242 MLX5_FLOW_ACTION_SET_MAC_DST | \
243 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
244 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
245 MLX5_FLOW_ACTION_INC_TCP_ACK | \
246 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
247 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
248 MLX5_FLOW_ACTION_SET_TAG | \
249 MLX5_FLOW_ACTION_MARK_EXT | \
250 MLX5_FLOW_ACTION_SET_META | \
251 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \
252 MLX5_FLOW_ACTION_SET_IPV6_DSCP | \
253 MLX5_FLOW_ACTION_MODIFY_FIELD)
255 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
256 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
258 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP)
261 #define IPPROTO_MPLS 137
264 /* UDP port number for MPLS */
265 #define MLX5_UDP_PORT_MPLS 6635
267 /* UDP port numbers for VxLAN. */
268 #define MLX5_UDP_PORT_VXLAN 4789
269 #define MLX5_UDP_PORT_VXLAN_GPE 4790
271 /* UDP port numbers for GENEVE. */
272 #define MLX5_UDP_PORT_GENEVE 6081
274 /* Lowest priority indicator. */
275 #define MLX5_FLOW_LOWEST_PRIO_INDICATOR ((uint32_t)-1)
278 * Max priority for ingress\egress flow groups
279 * greater than 0 and for any transfer flow group.
280 * From user configation: 0 - 21843.
282 #define MLX5_NON_ROOT_FLOW_MAX_PRIO (21843 + 1)
285 * Number of sub priorities.
286 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
287 * matching on the NIC (firmware dependent) L4 most have the higher priority
288 * followed by L3 and ending with L2.
290 #define MLX5_PRIORITY_MAP_L2 2
291 #define MLX5_PRIORITY_MAP_L3 1
292 #define MLX5_PRIORITY_MAP_L4 0
293 #define MLX5_PRIORITY_MAP_MAX 3
295 /* Valid layer type for IPV4 RSS. */
296 #define MLX5_IPV4_LAYER_TYPES \
297 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
298 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
299 ETH_RSS_NONFRAG_IPV4_OTHER)
301 /* IBV hash source bits for IPV4. */
302 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
304 /* Valid layer type for IPV6 RSS. */
305 #define MLX5_IPV6_LAYER_TYPES \
306 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
307 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
308 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
310 /* IBV hash source bits for IPV6. */
311 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
313 /* IBV hash bits for L3 SRC. */
314 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6)
316 /* IBV hash bits for L3 DST. */
317 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6)
319 /* IBV hash bits for TCP. */
320 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
321 IBV_RX_HASH_DST_PORT_TCP)
323 /* IBV hash bits for UDP. */
324 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \
325 IBV_RX_HASH_DST_PORT_UDP)
327 /* IBV hash bits for L4 SRC. */
328 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
329 IBV_RX_HASH_SRC_PORT_UDP)
331 /* IBV hash bits for L4 DST. */
332 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \
333 IBV_RX_HASH_DST_PORT_UDP)
335 /* Geneve header first 16Bit */
336 #define MLX5_GENEVE_VER_MASK 0x3
337 #define MLX5_GENEVE_VER_SHIFT 14
338 #define MLX5_GENEVE_VER_VAL(a) \
339 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
340 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
341 #define MLX5_GENEVE_OPTLEN_SHIFT 8
342 #define MLX5_GENEVE_OPTLEN_VAL(a) \
343 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
344 #define MLX5_GENEVE_OAMF_MASK 0x1
345 #define MLX5_GENEVE_OAMF_SHIFT 7
346 #define MLX5_GENEVE_OAMF_VAL(a) \
347 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
348 #define MLX5_GENEVE_CRITO_MASK 0x1
349 #define MLX5_GENEVE_CRITO_SHIFT 6
350 #define MLX5_GENEVE_CRITO_VAL(a) \
351 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
352 #define MLX5_GENEVE_RSVD_MASK 0x3F
353 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
355 * The length of the Geneve options fields, expressed in four byte multiples,
356 * not including the eight byte fixed tunnel.
358 #define MLX5_GENEVE_OPT_LEN_0 14
359 #define MLX5_GENEVE_OPT_LEN_1 63
361 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_ether_hdr) + \
362 sizeof(struct rte_ipv4_hdr))
363 /* GTP extension header flag. */
364 #define MLX5_GTP_EXT_HEADER_FLAG 4
366 /* GTP extension header max PDU type value. */
367 #define MLX5_GTP_EXT_MAX_PDU_TYPE 15
369 /* GTP extension header PDU type shift. */
370 #define MLX5_GTP_PDU_TYPE_SHIFT(a) ((a) << 4)
372 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */
373 #define MLX5_IPV4_FRAG_OFFSET_MASK \
374 (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG)
376 /* Specific item's fields can accept a range of values (using spec and last). */
377 #define MLX5_ITEM_RANGE_NOT_ACCEPTED false
378 #define MLX5_ITEM_RANGE_ACCEPTED true
380 /* Software header modify action numbers of a flow. */
381 #define MLX5_ACT_NUM_MDF_IPV4 1
382 #define MLX5_ACT_NUM_MDF_IPV6 4
383 #define MLX5_ACT_NUM_MDF_MAC 2
384 #define MLX5_ACT_NUM_MDF_VID 1
385 #define MLX5_ACT_NUM_MDF_PORT 2
386 #define MLX5_ACT_NUM_MDF_TTL 1
387 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL
388 #define MLX5_ACT_NUM_MDF_TCPSEQ 1
389 #define MLX5_ACT_NUM_MDF_TCPACK 1
390 #define MLX5_ACT_NUM_SET_REG 1
391 #define MLX5_ACT_NUM_SET_TAG 1
392 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG
393 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG
394 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG
395 #define MLX5_ACT_NUM_SET_DSCP 1
397 /* Maximum number of fields to modify in MODIFY_FIELD */
398 #define MLX5_ACT_MAX_MOD_FIELDS 5
400 enum mlx5_flow_drv_type {
403 MLX5_FLOW_TYPE_VERBS,
407 /* Fate action type. */
408 enum mlx5_flow_fate_type {
409 MLX5_FLOW_FATE_NONE, /* Egress flow. */
410 MLX5_FLOW_FATE_QUEUE,
412 MLX5_FLOW_FATE_PORT_ID,
414 MLX5_FLOW_FATE_DEFAULT_MISS,
415 MLX5_FLOW_FATE_SHARED_RSS,
419 /* Matcher PRM representation */
420 struct mlx5_flow_dv_match_params {
422 /**< Size of match value. Do NOT split size and key! */
423 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
424 /**< Matcher value. This value is used as the mask or as a key. */
427 /* Matcher structure. */
428 struct mlx5_flow_dv_matcher {
429 struct mlx5_cache_entry entry; /**< Pointer to the next element. */
430 struct mlx5_flow_tbl_resource *tbl;
431 /**< Pointer to the table(group) the matcher associated with. */
432 void *matcher_object; /**< Pointer to DV matcher */
433 uint16_t crc; /**< CRC of key. */
434 uint16_t priority; /**< Priority of matcher. */
435 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
438 #define MLX5_ENCAP_MAX_LEN 132
440 /* Encap/decap resource structure. */
441 struct mlx5_flow_dv_encap_decap_resource {
442 struct mlx5_hlist_entry entry;
443 /* Pointer to next element. */
444 uint32_t refcnt; /**< Reference counter. */
446 /**< Encap/decap action object. */
447 uint8_t buf[MLX5_ENCAP_MAX_LEN];
449 uint8_t reformat_type;
451 uint64_t flags; /**< Flags for RDMA API. */
452 uint32_t idx; /**< Index for the index memory pool. */
455 /* Tag resource structure. */
456 struct mlx5_flow_dv_tag_resource {
457 struct mlx5_hlist_entry entry;
458 /**< hash list entry for tag resource, tag value as the key. */
460 /**< Tag action object. */
461 uint32_t refcnt; /**< Reference counter. */
462 uint32_t idx; /**< Index for the index memory pool. */
463 uint32_t tag_id; /**< Tag ID. */
467 * Number of modification commands.
468 * The maximal actions amount in FW is some constant, and it is 16 in the
469 * latest releases. In some old releases, it will be limited to 8.
470 * Since there is no interface to query the capacity, the maximal value should
471 * be used to allow PMD to create the flow. The validation will be done in the
472 * lower driver layer or FW. A failure will be returned if exceeds the maximal
473 * supported actions number on the root table.
474 * On non-root tables, there is no limitation, but 32 is enough right now.
476 #define MLX5_MAX_MODIFY_NUM 32
477 #define MLX5_ROOT_TBL_MODIFY_NUM 16
479 /* Modify resource structure */
480 struct mlx5_flow_dv_modify_hdr_resource {
481 struct mlx5_hlist_entry entry;
482 void *action; /**< Modify header action object. */
483 /* Key area for hash list matching: */
484 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
485 uint32_t actions_num; /**< Number of modification actions. */
486 uint64_t flags; /**< Flags for RDMA API. */
487 struct mlx5_modification_cmd actions[];
488 /**< Modification actions. */
491 /* Modify resource key of the hash organization. */
492 union mlx5_flow_modify_hdr_key {
494 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
495 uint32_t actions_num:5; /**< Number of modification actions. */
496 uint32_t group:19; /**< Flow group id. */
497 uint32_t cksum; /**< Actions check sum. */
499 uint64_t v64; /**< full 64bits value of key */
502 /* Jump action resource structure. */
503 struct mlx5_flow_dv_jump_tbl_resource {
504 void *action; /**< Pointer to the rdma core action. */
507 /* Port ID resource structure. */
508 struct mlx5_flow_dv_port_id_action_resource {
509 struct mlx5_cache_entry entry;
510 void *action; /**< Action object. */
511 uint32_t port_id; /**< Port ID value. */
512 uint32_t idx; /**< Indexed pool memory index. */
515 /* Push VLAN action resource structure */
516 struct mlx5_flow_dv_push_vlan_action_resource {
517 struct mlx5_cache_entry entry; /* Cache entry. */
518 void *action; /**< Action object. */
519 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
520 rte_be32_t vlan_tag; /**< VLAN tag value. */
521 uint32_t idx; /**< Indexed pool memory index. */
524 /* Metadata register copy table entry. */
525 struct mlx5_flow_mreg_copy_resource {
527 * Hash list entry for copy table.
528 * - Key is 32/64-bit MARK action ID.
529 * - MUST be the first entry.
531 struct mlx5_hlist_entry hlist_ent;
532 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next;
533 /* List entry for device flows. */
535 uint32_t rix_flow; /* Built flow for copy. */
539 /* Table tunnel parameter. */
540 struct mlx5_flow_tbl_tunnel_prm {
541 const struct mlx5_flow_tunnel *tunnel;
546 /* Table data structure of the hash organization. */
547 struct mlx5_flow_tbl_data_entry {
548 struct mlx5_hlist_entry entry;
549 /**< hash list entry, 64-bits key inside. */
550 struct mlx5_flow_tbl_resource tbl;
551 /**< flow table resource. */
552 struct mlx5_cache_list matchers;
553 /**< matchers' header associated with the flow table. */
554 struct mlx5_flow_dv_jump_tbl_resource jump;
555 /**< jump resource, at most one for each table created. */
556 uint32_t idx; /**< index for the indexed mempool. */
557 /**< tunnel offload */
558 const struct mlx5_flow_tunnel *tunnel;
561 uint32_t tunnel_offload:1; /* Tunnel offlod table or not. */
562 uint32_t is_egress:1; /**< Egress table. */
563 uint32_t is_transfer:1; /**< Transfer table. */
564 uint32_t dummy:1; /**< DR table. */
565 uint32_t reserve:27; /**< Reserved to future using. */
566 uint32_t table_id; /**< Table ID. */
569 /* Sub rdma-core actions list. */
570 struct mlx5_flow_sub_actions_list {
571 uint32_t actions_num; /**< Number of sample actions. */
572 uint64_t action_flags;
573 void *dr_queue_action;
576 void *dr_port_id_action;
577 void *dr_encap_action;
578 void *dr_jump_action;
581 /* Sample sub-actions resource list. */
582 struct mlx5_flow_sub_actions_idx {
583 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
584 uint32_t rix_tag; /**< Index to the tag action. */
585 uint32_t rix_port_id_action; /**< Index to port ID action resource. */
586 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */
587 uint32_t rix_jump; /**< Index to the jump action resource. */
590 /* Sample action resource structure. */
591 struct mlx5_flow_dv_sample_resource {
592 struct mlx5_cache_entry entry; /**< Cache entry. */
594 void *verbs_action; /**< Verbs sample action object. */
595 void **sub_actions; /**< Sample sub-action array. */
597 struct rte_eth_dev *dev; /**< Device registers the action. */
598 uint32_t idx; /** Sample object index. */
599 uint8_t ft_type; /** Flow Table Type */
600 uint32_t ft_id; /** Flow Table Level */
601 uint32_t ratio; /** Sample Ratio */
602 uint64_t set_action; /** Restore reg_c0 value */
603 void *normal_path_tbl; /** Flow Table pointer */
604 struct mlx5_flow_sub_actions_idx sample_idx;
605 /**< Action index resources. */
606 struct mlx5_flow_sub_actions_list sample_act;
607 /**< Action resources. */
610 #define MLX5_MAX_DEST_NUM 2
612 /* Destination array action resource structure. */
613 struct mlx5_flow_dv_dest_array_resource {
614 struct mlx5_cache_entry entry; /**< Cache entry. */
615 uint32_t idx; /** Destination array action object index. */
616 uint8_t ft_type; /** Flow Table Type */
617 uint8_t num_of_dest; /**< Number of destination actions. */
618 struct rte_eth_dev *dev; /**< Device registers the action. */
619 void *action; /**< Pointer to the rdma core action. */
620 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM];
621 /**< Action index resources. */
622 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM];
623 /**< Action resources. */
626 /* PMD flow priority for tunnel */
627 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \
628 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4)
631 /** Device flow handle structure for DV mode only. */
632 struct mlx5_flow_handle_dv {
634 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
635 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
636 /**< Pointer to modify header resource in cache. */
637 uint32_t rix_encap_decap;
638 /**< Index to encap/decap resource in cache. */
639 uint32_t rix_push_vlan;
640 /**< Index to push VLAN action resource in cache. */
642 /**< Index to the tag action. */
644 /**< Index to sample action resource in cache. */
645 uint32_t rix_dest_array;
646 /**< Index to destination array resource in cache. */
649 /** Device flow handle structure: used both for creating & destroying. */
650 struct mlx5_flow_handle {
651 SILIST_ENTRY(uint32_t)next;
652 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */
653 /**< Index to next device flow handle. */
655 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
656 void *drv_flow; /**< pointer to driver flow object. */
657 uint32_t split_flow_id:27; /**< Sub flow unique match flow id. */
658 uint32_t is_meter_flow_id:1; /**< Indate if flow_id is for meter. */
659 uint32_t mark:1; /**< Metadate rxq mark flag. */
660 uint32_t fate_action:3; /**< Fate action type. */
662 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
663 uint32_t rix_jump; /**< Index to the jump action resource. */
664 uint32_t rix_port_id_action;
665 /**< Index to port ID action resource. */
667 /**< Generic value indicates the fate action. */
668 uint32_t rix_default_fate;
669 /**< Indicates default miss fate action. */
671 /**< Indicates shared RSS fate action. */
673 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
674 struct mlx5_flow_handle_dv dvh;
679 * Size for Verbs device flow handle structure only. Do not use the DV only
680 * structure in Verbs. No DV flows attributes will be accessed.
681 * Macro offsetof() could also be used here.
683 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
684 #define MLX5_FLOW_HANDLE_VERBS_SIZE \
685 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv))
687 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle))
691 * Max number of actions per DV flow.
692 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
693 * in rdma-core file providers/mlx5/verbs.c.
695 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
697 /** Device flow structure only for DV flow creation. */
698 struct mlx5_flow_dv_workspace {
699 uint32_t group; /**< The group index. */
700 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
701 int actions_n; /**< number of actions. */
702 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */
703 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
704 /**< Pointer to encap/decap resource in cache. */
705 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
706 /**< Pointer to push VLAN action resource in cache. */
707 struct mlx5_flow_dv_tag_resource *tag_resource;
708 /**< pointer to the tag action. */
709 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
710 /**< Pointer to port ID action resource. */
711 struct mlx5_flow_dv_jump_tbl_resource *jump;
712 /**< Pointer to the jump action resource. */
713 struct mlx5_flow_dv_match_params value;
714 /**< Holds the value that the packet is compared to. */
715 struct mlx5_flow_dv_sample_resource *sample_res;
716 /**< Pointer to the sample action resource. */
717 struct mlx5_flow_dv_dest_array_resource *dest_array_res;
718 /**< Pointer to the destination array resource. */
721 #ifdef HAVE_INFINIBAND_VERBS_H
723 * Maximal Verbs flow specifications & actions size.
724 * Some elements are mutually exclusive, but enough space should be allocated.
725 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers.
726 * 2. One tunnel header (exception: GRE + MPLS),
727 * SPEC length: GRE == tunnel.
728 * Actions: 1. 1 Mark OR Flag.
729 * 2. 1 Drop (if any).
730 * 3. No limitation for counters, but it makes no sense to support too
731 * many counters in a single device flow.
733 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
734 #define MLX5_VERBS_MAX_SPEC_SIZE \
736 (2 * (sizeof(struct ibv_flow_spec_eth) + \
737 sizeof(struct ibv_flow_spec_ipv6) + \
738 sizeof(struct ibv_flow_spec_tcp_udp)) + \
739 sizeof(struct ibv_flow_spec_gre) + \
740 sizeof(struct ibv_flow_spec_mpls)) \
743 #define MLX5_VERBS_MAX_SPEC_SIZE \
745 (2 * (sizeof(struct ibv_flow_spec_eth) + \
746 sizeof(struct ibv_flow_spec_ipv6) + \
747 sizeof(struct ibv_flow_spec_tcp_udp)) + \
748 sizeof(struct ibv_flow_spec_tunnel)) \
752 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \
753 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
754 #define MLX5_VERBS_MAX_ACT_SIZE \
756 sizeof(struct ibv_flow_spec_action_tag) + \
757 sizeof(struct ibv_flow_spec_action_drop) + \
758 sizeof(struct ibv_flow_spec_counter_action) * 4 \
761 #define MLX5_VERBS_MAX_ACT_SIZE \
763 sizeof(struct ibv_flow_spec_action_tag) + \
764 sizeof(struct ibv_flow_spec_action_drop) \
768 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \
769 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE)
771 /** Device flow structure only for Verbs flow creation. */
772 struct mlx5_flow_verbs_workspace {
773 unsigned int size; /**< Size of the attribute. */
774 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */
775 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE];
776 /**< Specifications & actions buffer of verbs flow. */
778 #endif /* HAVE_INFINIBAND_VERBS_H */
780 #define MLX5_SCALE_FLOW_GROUP_BIT 0
781 #define MLX5_SCALE_JUMP_FLOW_GROUP_BIT 1
783 /** Maximal number of device sub-flows supported. */
784 #define MLX5_NUM_MAX_DEV_FLOWS 32
786 /** Device flow structure. */
789 struct rte_flow *flow; /**< Pointer to the main flow. */
790 uint32_t flow_idx; /**< The memory pool index to the main flow. */
791 uint64_t hash_fields; /**< Hash Rx queue hash fields. */
793 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
794 bool external; /**< true if the flow is created external to PMD. */
795 uint8_t ingress:1; /**< 1 if the flow is ingress. */
796 uint8_t skip_scale:2;
798 * Each Bit be set to 1 if Skip the scale the flow group with factor.
799 * If bit0 be set to 1, then skip the scale the original flow group;
800 * If bit1 be set to 1, then skip the scale the jump flow group if
801 * having jump action.
802 * 00: Enable scale in a flow, default value.
803 * 01: Skip scale the flow group with factor, enable scale the group
805 * 10: Enable scale the group with factor, skip scale the group of
807 * 11: Skip scale the table with factor both for flow group and jump
811 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
812 struct mlx5_flow_dv_workspace dv;
814 #ifdef HAVE_INFINIBAND_VERBS_H
815 struct mlx5_flow_verbs_workspace verbs;
818 struct mlx5_flow_handle *handle;
819 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */
820 const struct mlx5_flow_tunnel *tunnel;
823 /* Flow meter state. */
824 #define MLX5_FLOW_METER_DISABLE 0
825 #define MLX5_FLOW_METER_ENABLE 1
827 #define MLX5_MAN_WIDTH 8
828 /* Modify this value if enum rte_mtr_color changes. */
829 #define RTE_MTR_DROPPED RTE_COLORS
831 /* Meter policer statistics */
832 struct mlx5_flow_policer_stats {
834 /**< Color counter for pass. */
836 /**< Color counter for drop. */
839 /* Meter table structure. */
840 struct mlx5_meter_domain_info {
841 struct mlx5_flow_tbl_resource *tbl;
843 struct mlx5_flow_tbl_resource *sfx_tbl;
844 /**< Meter suffix table. */
845 struct mlx5_flow_dv_matcher *drop_matcher;
846 /**< Matcher for Drop. */
847 struct mlx5_flow_dv_matcher *color_matcher;
848 /**< Matcher for Color. */
850 /**< Meter match action. */
852 /**< Meter green rule. */
854 /**< Meter drop rule. */
857 /* Meter table set for TX RX FDB. */
858 struct mlx5_meter_domains_infos {
860 /**< Table user count. */
861 struct mlx5_meter_domain_info egress;
862 /**< TX meter table. */
863 struct mlx5_meter_domain_info ingress;
864 /**< RX meter table. */
865 struct mlx5_meter_domain_info transfer;
866 /**< FDB meter table. */
868 /**< Counters for green rule. */
870 /**< Counters for green rule. */
871 uint32_t fmp[MLX5_ST_SZ_DW(flow_meter_parameters)];
872 /**< Flow meter parameter. */
874 /**< Flow meter parameter size. */
876 /**< Flow meter action. */
879 /* Meter parameter structure. */
880 struct mlx5_flow_meter {
881 TAILQ_ENTRY(mlx5_flow_meter) next;
882 /**< Pointer to the next flow meter structure. */
883 uint32_t idx; /* Index to meter object. */
886 struct mlx5_flow_meter_profile *profile;
887 /**< Meter profile parameters. */
889 rte_spinlock_t sl; /**< Meter action spinlock. */
891 /** Policer actions (per meter output color). */
892 enum rte_mtr_policer_action action[RTE_COLORS];
894 uint32_t green_bytes:1;
895 /** Set green bytes stats to be enabled. */
896 uint32_t green_pkts:1;
897 /** Set green packets stats to be enabled. */
898 uint32_t red_bytes:1;
899 /** Set red bytes stats to be enabled. */
901 /** Set red packets stats to be enabled. */
902 uint32_t bytes_dropped:1;
903 /** Set bytes dropped stats to be enabled. */
904 uint32_t pkts_dropped:1;
905 /** Set packets dropped stats to be enabled. */
907 /**< Rule applies to ingress traffic. */
910 /**< Rule applies to egress traffic. */
913 * Instead of simply matching the properties of traffic as it would
914 * appear on a given DPDK port ID, enabling this attribute transfers
915 * a flow rule to the lowest possible level of any device endpoints
916 * found in the pattern.
918 * When supported, this effectively enables an application to
919 * re-route traffic not necessarily intended for it (e.g. coming
920 * from or addressed to different physical ports, VFs or
921 * applications) at the device level.
923 * It complements the behavior of some pattern items such as
924 * RTE_FLOW_ITEM_TYPE_PHY_PORT and is meaningless without them.
926 * When transferring flow rules, ingress and egress attributes keep
927 * their original meaning, as if processing traffic emitted or
928 * received by the application.
931 struct mlx5_meter_domains_infos *mfts;
932 /**< Flow table created for this meter. */
933 struct mlx5_flow_policer_stats policer_stats;
934 /**< Meter policer statistics. */
937 uint32_t active_state:1;
940 /**< Meter shared or not. */
941 struct mlx5_indexed_pool *flow_ipool;
942 /**< Index pool for flow id. */
945 /* RFC2697 parameter structure. */
946 struct mlx5_flow_meter_srtcm_rfc2697_prm {
947 /* green_saturation_value = cbs_mantissa * 2^cbs_exponent */
948 uint32_t cbs_exponent:5;
949 uint32_t cbs_mantissa:8;
950 /* cir = 8G * cir_mantissa * 1/(2^cir_exponent) Bytes/Sec */
951 uint32_t cir_exponent:5;
952 uint32_t cir_mantissa:8;
953 /* yellow _saturation_value = ebs_mantissa * 2^ebs_exponent */
954 uint32_t ebs_exponent:5;
955 uint32_t ebs_mantissa:8;
958 /* Flow meter profile structure. */
959 struct mlx5_flow_meter_profile {
960 TAILQ_ENTRY(mlx5_flow_meter_profile) next;
961 /**< Pointer to the next flow meter structure. */
962 uint32_t meter_profile_id; /**< Profile id. */
963 struct rte_mtr_meter_profile profile; /**< Profile detail. */
965 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm;
966 /**< srtcm_rfc2697 struct. */
968 uint32_t ref_cnt; /**< Use count. */
971 #define MLX5_MAX_TUNNELS 256
972 #define MLX5_TNL_MISS_RULE_PRIORITY 3
973 #define MLX5_TNL_MISS_FDB_JUMP_GRP 0x1234faac
976 * When tunnel offload is active, all JUMP group ids are converted
977 * using the same method. That conversion is applied both to tunnel and
978 * regular rule types.
979 * Group ids used in tunnel rules are relative to it's tunnel (!).
980 * Application can create number of steer rules, using the same
981 * tunnel, with different group id in each rule.
982 * Each tunnel stores its groups internally in PMD tunnel object.
983 * Groups used in regular rules do not belong to any tunnel and are stored
987 struct mlx5_flow_tunnel {
988 LIST_ENTRY(mlx5_flow_tunnel) chain;
989 struct rte_flow_tunnel app_tunnel; /** app tunnel copy */
990 uint32_t tunnel_id; /** unique tunnel ID */
992 struct rte_flow_action action;
993 struct rte_flow_item item;
994 struct mlx5_hlist *groups; /** tunnel groups */
997 /** PMD tunnel related context */
998 struct mlx5_flow_tunnel_hub {
1000 * Access to the list MUST be MT protected
1002 LIST_HEAD(, mlx5_flow_tunnel) tunnels;
1003 /* protect access to the tunnels list */
1005 struct mlx5_hlist *groups; /** non tunnel groups */
1008 /* convert jump group to flow table ID in tunnel rules */
1009 struct tunnel_tbl_entry {
1010 struct mlx5_hlist_entry hash;
1011 uint32_t flow_table;
1016 static inline uint32_t
1017 tunnel_id_to_flow_tbl(uint32_t id)
1019 return id | (1u << 16);
1022 static inline uint32_t
1023 tunnel_flow_tbl_to_id(uint32_t flow_tbl)
1025 return flow_tbl & ~(1u << 16);
1028 union tunnel_tbl_key {
1036 static inline struct mlx5_flow_tunnel_hub *
1037 mlx5_tunnel_hub(struct rte_eth_dev *dev)
1039 struct mlx5_priv *priv = dev->data->dev_private;
1040 return priv->sh->tunnel_hub;
1044 is_tunnel_offload_active(struct rte_eth_dev *dev)
1046 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1047 struct mlx5_priv *priv = dev->data->dev_private;
1048 return !!priv->config.dv_miss_info;
1056 is_flow_tunnel_match_rule(__rte_unused struct rte_eth_dev *dev,
1057 __rte_unused const struct rte_flow_attr *attr,
1058 __rte_unused const struct rte_flow_item items[],
1059 __rte_unused const struct rte_flow_action actions[])
1061 return (items[0].type == (typeof(items[0].type))
1062 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL);
1066 is_flow_tunnel_steer_rule(__rte_unused struct rte_eth_dev *dev,
1067 __rte_unused const struct rte_flow_attr *attr,
1068 __rte_unused const struct rte_flow_item items[],
1069 __rte_unused const struct rte_flow_action actions[])
1071 return (actions[0].type == (typeof(actions[0].type))
1072 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET);
1075 static inline const struct mlx5_flow_tunnel *
1076 flow_actions_to_tunnel(const struct rte_flow_action actions[])
1078 return actions[0].conf;
1081 static inline const struct mlx5_flow_tunnel *
1082 flow_items_to_tunnel(const struct rte_flow_item items[])
1084 return items[0].spec;
1087 /* Flow structure. */
1089 ILIST_ENTRY(uint32_t)next; /**< Index to the next flow structure. */
1090 uint32_t dev_handles;
1091 /**< Device flow handles that are part of the flow. */
1092 uint32_t drv_type:2; /**< Driver type. */
1094 uint32_t meter:16; /**< Holds flow meter id. */
1095 uint32_t rix_mreg_copy;
1096 /**< Index to metadata register copy table resource. */
1097 uint32_t counter; /**< Holds flow counter. */
1098 uint32_t tunnel_id; /**< Tunnel id */
1099 uint32_t age; /**< Holds ASO age bit index. */
1100 uint32_t geneve_tlv_option; /**< Holds Geneve TLV option id. > */
1104 * Define list of valid combinations of RX Hash fields
1105 * (see enum ibv_rx_hash_fields).
1107 #define MLX5_RSS_HASH_IPV4 (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
1108 #define MLX5_RSS_HASH_IPV4_TCP \
1109 (MLX5_RSS_HASH_IPV4 | \
1110 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP)
1111 #define MLX5_RSS_HASH_IPV4_UDP \
1112 (MLX5_RSS_HASH_IPV4 | \
1113 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP)
1114 #define MLX5_RSS_HASH_IPV6 (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
1115 #define MLX5_RSS_HASH_IPV6_TCP \
1116 (MLX5_RSS_HASH_IPV6 | \
1117 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP)
1118 #define MLX5_RSS_HASH_IPV6_UDP \
1119 (MLX5_RSS_HASH_IPV6 | \
1120 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP)
1121 #define MLX5_RSS_HASH_IPV4_SRC_ONLY IBV_RX_HASH_SRC_IPV4
1122 #define MLX5_RSS_HASH_IPV4_DST_ONLY IBV_RX_HASH_DST_IPV4
1123 #define MLX5_RSS_HASH_IPV6_SRC_ONLY IBV_RX_HASH_SRC_IPV6
1124 #define MLX5_RSS_HASH_IPV6_DST_ONLY IBV_RX_HASH_DST_IPV6
1125 #define MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY \
1126 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_UDP)
1127 #define MLX5_RSS_HASH_IPV4_UDP_DST_ONLY \
1128 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_UDP)
1129 #define MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY \
1130 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_UDP)
1131 #define MLX5_RSS_HASH_IPV6_UDP_DST_ONLY \
1132 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_UDP)
1133 #define MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY \
1134 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_TCP)
1135 #define MLX5_RSS_HASH_IPV4_TCP_DST_ONLY \
1136 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_TCP)
1137 #define MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY \
1138 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_TCP)
1139 #define MLX5_RSS_HASH_IPV6_TCP_DST_ONLY \
1140 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_TCP)
1141 #define MLX5_RSS_HASH_NONE 0ULL
1143 /* array of valid combinations of RX Hash fields for RSS */
1144 static const uint64_t mlx5_rss_hash_fields[] = {
1146 MLX5_RSS_HASH_IPV4_TCP,
1147 MLX5_RSS_HASH_IPV4_UDP,
1149 MLX5_RSS_HASH_IPV6_TCP,
1150 MLX5_RSS_HASH_IPV6_UDP,
1154 /* Shared RSS action structure */
1155 struct mlx5_shared_action_rss {
1156 ILIST_ENTRY(uint32_t)next; /**< Index to the next RSS structure. */
1157 uint32_t refcnt; /**< Atomically accessed refcnt. */
1158 struct rte_flow_action_rss origin; /**< Original rte RSS action. */
1159 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
1160 struct mlx5_ind_table_obj *ind_tbl;
1161 /**< Hash RX queues (hrxq, hrxq_tunnel fields) indirection table. */
1162 uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN];
1163 /**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */
1164 rte_spinlock_t action_rss_sl; /**< Shared RSS action spinlock. */
1167 struct rte_flow_action_handle {
1171 /* Thread specific flow workspace intermediate data. */
1172 struct mlx5_flow_workspace {
1173 /* If creating another flow in same thread, push new as stack. */
1174 struct mlx5_flow_workspace *prev;
1175 struct mlx5_flow_workspace *next;
1176 uint32_t inuse; /* can't create new flow with current. */
1177 struct mlx5_flow flows[MLX5_NUM_MAX_DEV_FLOWS];
1178 struct mlx5_flow_rss_desc rss_desc;
1179 uint32_t rssq_num; /* Allocated queue num in rss_desc. */
1180 uint32_t flow_idx; /* Intermediate device flow index. */
1181 struct mlx5_flow_meter *fm; /* Pointer to the meter in flow. */
1184 struct mlx5_flow_split_info {
1186 /**< True if flow is created by request external to PMD. */
1187 uint8_t skip_scale; /**< Skip the scale the table with factor. */
1188 uint32_t flow_idx; /**< This memory pool index to the flow. */
1189 uint32_t prefix_mark; /**< Prefix subflow mark flag. */
1190 uint64_t prefix_layers; /**< Prefix subflow layers. */
1193 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
1194 const struct rte_flow_attr *attr,
1195 const struct rte_flow_item items[],
1196 const struct rte_flow_action actions[],
1199 struct rte_flow_error *error);
1200 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
1201 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
1202 const struct rte_flow_item items[],
1203 const struct rte_flow_action actions[], struct rte_flow_error *error);
1204 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
1205 struct mlx5_flow *dev_flow,
1206 const struct rte_flow_attr *attr,
1207 const struct rte_flow_item items[],
1208 const struct rte_flow_action actions[],
1209 struct rte_flow_error *error);
1210 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
1211 struct rte_flow_error *error);
1212 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
1213 struct rte_flow *flow);
1214 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
1215 struct rte_flow *flow);
1216 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
1217 struct rte_flow *flow,
1218 const struct rte_flow_action *actions,
1220 struct rte_flow_error *error);
1221 typedef struct mlx5_meter_domains_infos *(*mlx5_flow_create_mtr_tbls_t)
1222 (struct rte_eth_dev *dev);
1223 typedef int (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev,
1224 struct mlx5_meter_domains_infos *tbls);
1225 typedef int (*mlx5_flow_create_policer_rules_t)
1226 (struct rte_eth_dev *dev,
1227 struct mlx5_flow_meter *fm,
1228 const struct rte_flow_attr *attr);
1229 typedef int (*mlx5_flow_destroy_policer_rules_t)
1230 (struct rte_eth_dev *dev,
1231 const struct mlx5_flow_meter *fm,
1232 const struct rte_flow_attr *attr);
1233 typedef uint32_t (*mlx5_flow_counter_alloc_t)
1234 (struct rte_eth_dev *dev);
1235 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev,
1237 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev,
1239 bool clear, uint64_t *pkts,
1241 typedef int (*mlx5_flow_get_aged_flows_t)
1242 (struct rte_eth_dev *dev,
1244 uint32_t nb_contexts,
1245 struct rte_flow_error *error);
1246 typedef int (*mlx5_flow_action_validate_t)
1247 (struct rte_eth_dev *dev,
1248 const struct rte_flow_indir_action_conf *conf,
1249 const struct rte_flow_action *action,
1250 struct rte_flow_error *error);
1251 typedef struct rte_flow_action_handle *(*mlx5_flow_action_create_t)
1252 (struct rte_eth_dev *dev,
1253 const struct rte_flow_indir_action_conf *conf,
1254 const struct rte_flow_action *action,
1255 struct rte_flow_error *error);
1256 typedef int (*mlx5_flow_action_destroy_t)
1257 (struct rte_eth_dev *dev,
1258 struct rte_flow_action_handle *action,
1259 struct rte_flow_error *error);
1260 typedef int (*mlx5_flow_action_update_t)
1261 (struct rte_eth_dev *dev,
1262 struct rte_flow_action_handle *action,
1264 struct rte_flow_error *error);
1265 typedef int (*mlx5_flow_action_query_t)
1266 (struct rte_eth_dev *dev,
1267 const struct rte_flow_action_handle *action,
1269 struct rte_flow_error *error);
1270 typedef int (*mlx5_flow_sync_domain_t)
1271 (struct rte_eth_dev *dev,
1275 struct mlx5_flow_driver_ops {
1276 mlx5_flow_validate_t validate;
1277 mlx5_flow_prepare_t prepare;
1278 mlx5_flow_translate_t translate;
1279 mlx5_flow_apply_t apply;
1280 mlx5_flow_remove_t remove;
1281 mlx5_flow_destroy_t destroy;
1282 mlx5_flow_query_t query;
1283 mlx5_flow_create_mtr_tbls_t create_mtr_tbls;
1284 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls;
1285 mlx5_flow_create_policer_rules_t prepare_policer_rules;
1286 mlx5_flow_destroy_policer_rules_t destroy_policer_rules;
1287 mlx5_flow_counter_alloc_t counter_alloc;
1288 mlx5_flow_counter_free_t counter_free;
1289 mlx5_flow_counter_query_t counter_query;
1290 mlx5_flow_get_aged_flows_t get_aged_flows;
1291 mlx5_flow_action_validate_t action_validate;
1292 mlx5_flow_action_create_t action_create;
1293 mlx5_flow_action_destroy_t action_destroy;
1294 mlx5_flow_action_update_t action_update;
1295 mlx5_flow_action_query_t action_query;
1296 mlx5_flow_sync_domain_t sync_domain;
1301 struct mlx5_flow_workspace *mlx5_flow_get_thread_workspace(void);
1303 struct flow_grp_info {
1304 uint64_t external:1;
1305 uint64_t transfer:1;
1306 uint64_t fdb_def_rule:1;
1307 /* force standard group translation */
1308 uint64_t std_tbl_fix:1;
1309 uint64_t skip_scale:2;
1313 tunnel_use_standard_attr_group_translate
1314 (struct rte_eth_dev *dev,
1315 const struct mlx5_flow_tunnel *tunnel,
1316 const struct rte_flow_attr *attr,
1317 const struct rte_flow_item items[],
1318 const struct rte_flow_action actions[])
1322 if (!is_tunnel_offload_active(dev))
1323 /* no tunnel offload API */
1327 * OvS will use jump to group 0 in tunnel steer rule.
1328 * If tunnel steer rule starts from group 0 (attr.group == 0)
1329 * that 0 group must be translated with standard method.
1330 * attr.group == 0 in tunnel match rule translated with tunnel
1333 verdict = !attr->group &&
1334 is_flow_tunnel_steer_rule(dev, attr, items, actions);
1337 * non-tunnel group translation uses standard method for
1338 * root group only: attr.group == 0
1340 verdict = !attr->group;
1346 int mlx5_flow_group_to_table(struct rte_eth_dev *dev,
1347 const struct mlx5_flow_tunnel *tunnel,
1348 uint32_t group, uint32_t *table,
1349 const struct flow_grp_info *flags,
1350 struct rte_flow_error *error);
1351 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc,
1352 int tunnel, uint64_t layer_types,
1353 uint64_t hash_fields);
1354 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
1355 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
1356 uint32_t subpriority);
1357 uint32_t mlx5_get_lowest_priority(struct rte_eth_dev *dev,
1358 const struct rte_flow_attr *attr);
1359 uint16_t mlx5_get_matcher_priority(struct rte_eth_dev *dev,
1360 const struct rte_flow_attr *attr,
1361 uint32_t subpriority);
1362 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
1363 enum mlx5_feature_name feature,
1365 struct rte_flow_error *error);
1366 const struct rte_flow_action *mlx5_flow_find_action
1367 (const struct rte_flow_action *actions,
1368 enum rte_flow_action_type action);
1369 int mlx5_validate_action_rss(struct rte_eth_dev *dev,
1370 const struct rte_flow_action *action,
1371 struct rte_flow_error *error);
1372 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
1373 const struct rte_flow_attr *attr,
1374 struct rte_flow_error *error);
1375 int mlx5_flow_validate_action_drop(uint64_t action_flags,
1376 const struct rte_flow_attr *attr,
1377 struct rte_flow_error *error);
1378 int mlx5_flow_validate_action_flag(uint64_t action_flags,
1379 const struct rte_flow_attr *attr,
1380 struct rte_flow_error *error);
1381 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
1382 uint64_t action_flags,
1383 const struct rte_flow_attr *attr,
1384 struct rte_flow_error *error);
1385 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
1386 uint64_t action_flags,
1387 struct rte_eth_dev *dev,
1388 const struct rte_flow_attr *attr,
1389 struct rte_flow_error *error);
1390 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
1391 uint64_t action_flags,
1392 struct rte_eth_dev *dev,
1393 const struct rte_flow_attr *attr,
1394 uint64_t item_flags,
1395 struct rte_flow_error *error);
1396 int mlx5_flow_validate_action_default_miss(uint64_t action_flags,
1397 const struct rte_flow_attr *attr,
1398 struct rte_flow_error *error);
1399 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
1400 const struct rte_flow_attr *attributes,
1401 struct rte_flow_error *error);
1402 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
1403 const uint8_t *mask,
1404 const uint8_t *nic_mask,
1406 bool range_accepted,
1407 struct rte_flow_error *error);
1408 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
1409 uint64_t item_flags, bool ext_vlan_sup,
1410 struct rte_flow_error *error);
1411 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
1412 uint64_t item_flags,
1413 uint8_t target_protocol,
1414 struct rte_flow_error *error);
1415 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
1416 uint64_t item_flags,
1417 const struct rte_flow_item *gre_item,
1418 struct rte_flow_error *error);
1419 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
1420 uint64_t item_flags,
1422 uint16_t ether_type,
1423 const struct rte_flow_item_ipv4 *acc_mask,
1424 bool range_accepted,
1425 struct rte_flow_error *error);
1426 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
1427 uint64_t item_flags,
1429 uint16_t ether_type,
1430 const struct rte_flow_item_ipv6 *acc_mask,
1431 struct rte_flow_error *error);
1432 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
1433 const struct rte_flow_item *item,
1434 uint64_t item_flags,
1435 uint64_t prev_layer,
1436 struct rte_flow_error *error);
1437 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
1438 uint64_t item_flags,
1439 uint8_t target_protocol,
1440 const struct rte_flow_item_tcp *flow_mask,
1441 struct rte_flow_error *error);
1442 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
1443 uint64_t item_flags,
1444 uint8_t target_protocol,
1445 struct rte_flow_error *error);
1446 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
1447 uint64_t item_flags,
1448 struct rte_eth_dev *dev,
1449 struct rte_flow_error *error);
1450 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
1451 uint64_t item_flags,
1452 struct rte_flow_error *error);
1453 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
1454 uint64_t item_flags,
1455 struct rte_eth_dev *dev,
1456 struct rte_flow_error *error);
1457 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
1458 uint64_t item_flags,
1459 uint8_t target_protocol,
1460 struct rte_flow_error *error);
1461 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
1462 uint64_t item_flags,
1463 uint8_t target_protocol,
1464 struct rte_flow_error *error);
1465 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
1466 uint64_t item_flags,
1467 uint8_t target_protocol,
1468 struct rte_flow_error *error);
1469 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
1470 uint64_t item_flags,
1471 struct rte_eth_dev *dev,
1472 struct rte_flow_error *error);
1473 int mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item,
1475 const struct rte_flow_item *geneve_item,
1476 struct rte_eth_dev *dev,
1477 struct rte_flow_error *error);
1478 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item,
1479 uint64_t item_flags,
1481 uint16_t ether_type,
1482 const struct rte_flow_item_ecpri *acc_mask,
1483 struct rte_flow_error *error);
1484 struct mlx5_meter_domains_infos *mlx5_flow_create_mtr_tbls
1485 (struct rte_eth_dev *dev);
1486 int mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev,
1487 struct mlx5_meter_domains_infos *tbl);
1488 int mlx5_flow_prepare_policer_rules(struct rte_eth_dev *dev,
1489 struct mlx5_flow_meter *fm,
1490 const struct rte_flow_attr *attr);
1491 int mlx5_flow_destroy_policer_rules(struct rte_eth_dev *dev,
1492 struct mlx5_flow_meter *fm,
1493 const struct rte_flow_attr *attr);
1494 int mlx5_flow_meter_flush(struct rte_eth_dev *dev,
1495 struct rte_mtr_error *error);
1496 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev);
1497 int mlx5_action_handle_flush(struct rte_eth_dev *dev);
1498 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id);
1499 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh);
1501 /* Hash list callbacks for flow tables: */
1502 struct mlx5_hlist_entry *flow_dv_tbl_create_cb(struct mlx5_hlist *list,
1503 uint64_t key, void *entry_ctx);
1504 int flow_dv_tbl_match_cb(struct mlx5_hlist *list,
1505 struct mlx5_hlist_entry *entry, uint64_t key,
1507 void flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
1508 struct mlx5_hlist_entry *entry);
1509 struct mlx5_flow_tbl_resource *flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
1510 uint32_t table_id, uint8_t egress, uint8_t transfer,
1511 bool external, const struct mlx5_flow_tunnel *tunnel,
1512 uint32_t group_id, uint8_t dummy, struct rte_flow_error *error);
1514 struct mlx5_hlist_entry *flow_dv_tag_create_cb(struct mlx5_hlist *list,
1515 uint64_t key, void *cb_ctx);
1516 int flow_dv_tag_match_cb(struct mlx5_hlist *list,
1517 struct mlx5_hlist_entry *entry, uint64_t key,
1519 void flow_dv_tag_remove_cb(struct mlx5_hlist *list,
1520 struct mlx5_hlist_entry *entry);
1522 int flow_dv_modify_match_cb(struct mlx5_hlist *list,
1523 struct mlx5_hlist_entry *entry,
1524 uint64_t key, void *cb_ctx);
1525 struct mlx5_hlist_entry *flow_dv_modify_create_cb(struct mlx5_hlist *list,
1526 uint64_t key, void *ctx);
1527 void flow_dv_modify_remove_cb(struct mlx5_hlist *list,
1528 struct mlx5_hlist_entry *entry);
1530 struct mlx5_hlist_entry *flow_dv_mreg_create_cb(struct mlx5_hlist *list,
1531 uint64_t key, void *ctx);
1532 int flow_dv_mreg_match_cb(struct mlx5_hlist *list,
1533 struct mlx5_hlist_entry *entry, uint64_t key,
1535 void flow_dv_mreg_remove_cb(struct mlx5_hlist *list,
1536 struct mlx5_hlist_entry *entry);
1538 int flow_dv_encap_decap_match_cb(struct mlx5_hlist *list,
1539 struct mlx5_hlist_entry *entry,
1540 uint64_t key, void *cb_ctx);
1541 struct mlx5_hlist_entry *flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
1542 uint64_t key, void *cb_ctx);
1543 void flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
1544 struct mlx5_hlist_entry *entry);
1546 int flow_dv_matcher_match_cb(struct mlx5_cache_list *list,
1547 struct mlx5_cache_entry *entry, void *ctx);
1548 struct mlx5_cache_entry *flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
1549 struct mlx5_cache_entry *entry, void *ctx);
1550 void flow_dv_matcher_remove_cb(struct mlx5_cache_list *list,
1551 struct mlx5_cache_entry *entry);
1553 int flow_dv_port_id_match_cb(struct mlx5_cache_list *list,
1554 struct mlx5_cache_entry *entry, void *cb_ctx);
1555 struct mlx5_cache_entry *flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
1556 struct mlx5_cache_entry *entry, void *cb_ctx);
1557 void flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
1558 struct mlx5_cache_entry *entry);
1560 int flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list,
1561 struct mlx5_cache_entry *entry, void *cb_ctx);
1562 struct mlx5_cache_entry *flow_dv_push_vlan_create_cb
1563 (struct mlx5_cache_list *list,
1564 struct mlx5_cache_entry *entry, void *cb_ctx);
1565 void flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
1566 struct mlx5_cache_entry *entry);
1568 int flow_dv_sample_match_cb(struct mlx5_cache_list *list,
1569 struct mlx5_cache_entry *entry, void *cb_ctx);
1570 struct mlx5_cache_entry *flow_dv_sample_create_cb
1571 (struct mlx5_cache_list *list,
1572 struct mlx5_cache_entry *entry, void *cb_ctx);
1573 void flow_dv_sample_remove_cb(struct mlx5_cache_list *list,
1574 struct mlx5_cache_entry *entry);
1576 int flow_dv_dest_array_match_cb(struct mlx5_cache_list *list,
1577 struct mlx5_cache_entry *entry, void *cb_ctx);
1578 struct mlx5_cache_entry *flow_dv_dest_array_create_cb
1579 (struct mlx5_cache_list *list,
1580 struct mlx5_cache_entry *entry, void *cb_ctx);
1581 void flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list,
1582 struct mlx5_cache_entry *entry);
1583 struct mlx5_aso_age_action *flow_aso_age_get_by_idx(struct rte_eth_dev *dev,
1585 int flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
1586 const struct rte_flow_item *item,
1587 struct rte_flow_error *error);
1589 void flow_release_workspace(void *data);
1590 int mlx5_flow_os_init_workspace_once(void);
1591 void *mlx5_flow_os_get_specific_workspace(void);
1592 int mlx5_flow_os_set_specific_workspace(struct mlx5_flow_workspace *data);
1593 void mlx5_flow_os_release_workspace(void);
1596 #endif /* RTE_PMD_MLX5_FLOW_H_ */