drivers/net/mlx5/mlx5_flow_aso.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2020 Mellanox Technologies, Ltd
   3  */
   4 #include <mlx5_prm.h>
   5 #include <rte_malloc.h>
   6 #include <rte_cycles.h>
   7 #include <rte_eal_paging.h>
   8
   9 #include <mlx5_malloc.h>
  10 #include <mlx5_common_os.h>
  11 #include <mlx5_common_devx.h>
  12
  13 #include "mlx5.h"
  14 #include "mlx5_flow.h"
  15
  16 /**
  17  * Destroy Completion Queue used for ASO access.
  18  *
  19  * @param[in] cq
  20  *   ASO CQ to destroy.
  21  */
  22 static void
  23 mlx5_aso_cq_destroy(struct mlx5_aso_cq *cq)
  24 {
  25         if (cq->cq_obj.cq)
  26                 mlx5_devx_cq_destroy(&cq->cq_obj);
  27         memset(cq, 0, sizeof(*cq));
  28 }
  29
  30 /**
  31  * Create Completion Queue used for ASO access.
  32  *
  33  * @param[in] ctx
  34  *   Context returned from mlx5 open_device() glue function.
  35  * @param[in/out] cq
  36  *   Pointer to CQ to create.
  37  * @param[in] log_desc_n
  38  *   Log of number of descriptors in queue.
  39  * @param[in] socket
  40  *   Socket to use for allocation.
  41  * @param[in] uar_page_id
  42  *   UAR page ID to use.
  43  *
  44  * @return
  45  *   0 on success, a negative errno value otherwise and rte_errno is set.
  46  */
  47 static int
  48 mlx5_aso_cq_create(void *ctx, struct mlx5_aso_cq *cq, uint16_t log_desc_n,
  49                    int socket, int uar_page_id)
  50 {
  51         struct mlx5_devx_cq_attr attr = {
  52                 .uar_page_id = uar_page_id,
  53         };
  54
  55         cq->log_desc_n = log_desc_n;
  56         cq->cq_ci = 0;
  57         return mlx5_devx_cq_create(ctx, &cq->cq_obj, log_desc_n, &attr, socket);
  58 }
  59
  60 /**
  61  * Free MR resources.
  62  *
  63  * @param[in] mr
  64  *   MR to free.
  65  */
  66 static void
  67 mlx5_aso_devx_dereg_mr(struct mlx5_aso_devx_mr *mr)
  68 {
  69         claim_zero(mlx5_devx_cmd_destroy(mr->mkey));
  70         if (!mr->is_indirect && mr->umem)
  71                 claim_zero(mlx5_glue->devx_umem_dereg(mr->umem));
  72         mlx5_free(mr->buf);
  73         memset(mr, 0, sizeof(*mr));
  74 }
  75
  76 /**
  77  * Register Memory Region.
  78  *
  79  * @param[in] ctx
  80  *   Context returned from mlx5 open_device() glue function.
  81  * @param[in] length
  82  *   Size of MR buffer.
  83  * @param[in/out] mr
  84  *   Pointer to MR to create.
  85  * @param[in] socket
  86  *   Socket to use for allocation.
  87  * @param[in] pdn
  88  *   Protection Domain number to use.
  89  *
  90  * @return
  91  *   0 on success, a negative errno value otherwise and rte_errno is set.
  92  */
  93 static int
  94 mlx5_aso_devx_reg_mr(void *ctx, size_t length, struct mlx5_aso_devx_mr *mr,
  95                      int socket, int pdn)
  96 {
  97         struct mlx5_devx_mkey_attr mkey_attr;
  98
  99         mr->buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, length, 4096,
 100                               socket);
 101         if (!mr->buf) {
 102                 DRV_LOG(ERR, "Failed to create ASO bits mem for MR by Devx.");
 103                 return -1;
 104         }
 105         mr->umem = mlx5_os_umem_reg(ctx, mr->buf, length,
 106                                                  IBV_ACCESS_LOCAL_WRITE);
 107         if (!mr->umem) {
 108                 DRV_LOG(ERR, "Failed to register Umem for MR by Devx.");
 109                 goto error;
 110         }
 111         mkey_attr.addr = (uintptr_t)mr->buf;
 112         mkey_attr.size = length;
 113         mkey_attr.umem_id = mlx5_os_get_umem_id(mr->umem);
 114         mkey_attr.pd = pdn;
 115         mkey_attr.pg_access = 1;
 116         mkey_attr.klm_array = NULL;
 117         mkey_attr.klm_num = 0;
 118         mkey_attr.relaxed_ordering_read = 0;
 119         mkey_attr.relaxed_ordering_write = 0;
 120         mr->mkey = mlx5_devx_cmd_mkey_create(ctx, &mkey_attr);
 121         if (!mr->mkey) {
 122                 DRV_LOG(ERR, "Failed to create direct Mkey.");
 123                 goto error;
 124         }
 125         mr->length = length;
 126         mr->is_indirect = false;
 127         return 0;
 128 error:
 129         if (mr->umem)
 130                 claim_zero(mlx5_glue->devx_umem_dereg(mr->umem));
 131         mlx5_free(mr->buf);
 132         return -1;
 133 }
 134
 135 /**
 136  * Destroy Send Queue used for ASO access.
 137  *
 138  * @param[in] sq
 139  *   ASO SQ to destroy.
 140  */
 141 static void
 142 mlx5_aso_destroy_sq(struct mlx5_aso_sq *sq)
 143 {
 144         mlx5_devx_sq_destroy(&sq->sq_obj);
 145         mlx5_aso_cq_destroy(&sq->cq);
 146         memset(sq, 0, sizeof(*sq));
 147 }
 148
 149 /**
 150  * Initialize Send Queue used for ASO access.
 151  *
 152  * @param[in] sq
 153  *   ASO SQ to initialize.
 154  */
 155 static void
 156 mlx5_aso_age_init_sq(struct mlx5_aso_sq *sq)
 157 {
 158         volatile struct mlx5_aso_wqe *restrict wqe;
 159         int i;
 160         int size = 1 << sq->log_desc_n;
 161         uint64_t addr;
 162
 163         /* All the next fields state should stay constant. */
 164         for (i = 0, wqe = &sq->sq_obj.aso_wqes[0]; i < size; ++i, ++wqe) {
 165                 wqe->general_cseg.sq_ds = rte_cpu_to_be_32((sq->sqn << 8) |
 166                                                           (sizeof(*wqe) >> 4));
 167                 wqe->aso_cseg.lkey = rte_cpu_to_be_32(sq->mr.mkey->id);
 168                 addr = (uint64_t)((uint64_t *)sq->mr.buf + i *
 169                                             MLX5_ASO_AGE_ACTIONS_PER_POOL / 64);
 170                 wqe->aso_cseg.va_h = rte_cpu_to_be_32((uint32_t)(addr >> 32));
 171                 wqe->aso_cseg.va_l_r = rte_cpu_to_be_32((uint32_t)addr | 1u);
 172                 wqe->aso_cseg.operand_masks = rte_cpu_to_be_32
 173                         (0u |
 174                          (ASO_OPER_LOGICAL_OR << ASO_CSEG_COND_OPER_OFFSET) |
 175                          (ASO_OP_ALWAYS_TRUE << ASO_CSEG_COND_1_OPER_OFFSET) |
 176                          (ASO_OP_ALWAYS_TRUE << ASO_CSEG_COND_0_OPER_OFFSET) |
 177                          (BYTEWISE_64BYTE << ASO_CSEG_DATA_MASK_MODE_OFFSET));
 178                 wqe->aso_cseg.data_mask = RTE_BE64(UINT64_MAX);
 179         }
 180 }
 181
 182 /**
 183  * Initialize Send Queue used for ASO flow meter access.
 184  *
 185  * @param[in] sq
 186  *   ASO SQ to initialize.
 187  */
 188 static void
 189 mlx5_aso_mtr_init_sq(struct mlx5_aso_sq *sq)
 190 {
 191         volatile struct mlx5_aso_wqe *restrict wqe;
 192         int i;
 193         int size = 1 << sq->log_desc_n;
 194         uint32_t idx;
 195
 196         /* All the next fields state should stay constant. */
 197         for (i = 0, wqe = &sq->sq_obj.aso_wqes[0]; i < size; ++i, ++wqe) {
 198                 wqe->general_cseg.sq_ds = rte_cpu_to_be_32((sq->sqn << 8) |
 199                                                           (sizeof(*wqe) >> 4));
 200                 wqe->aso_cseg.operand_masks = RTE_BE32(0u |
 201                          (ASO_OPER_LOGICAL_OR << ASO_CSEG_COND_OPER_OFFSET) |
 202                          (ASO_OP_ALWAYS_TRUE << ASO_CSEG_COND_1_OPER_OFFSET) |
 203                          (ASO_OP_ALWAYS_TRUE << ASO_CSEG_COND_0_OPER_OFFSET) |
 204                          (BYTEWISE_64BYTE << ASO_CSEG_DATA_MASK_MODE_OFFSET));
 205                 wqe->general_cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<
 206                                                          MLX5_COMP_MODE_OFFSET);
 207                 for (idx = 0; idx < MLX5_ASO_METERS_PER_WQE;
 208                         idx++)
 209                         wqe->aso_dseg.mtrs[idx].v_bo_sc_bbog_mm =
 210                                 RTE_BE32((1 << ASO_DSEG_VALID_OFFSET) |
 211                                 (MLX5_FLOW_COLOR_GREEN << ASO_DSEG_SC_OFFSET));
 212         }
 213 }
 214
 215 /**
 216  * Create Send Queue used for ASO access.
 217  *
 218  * @param[in] ctx
 219  *   Context returned from mlx5 open_device() glue function.
 220  * @param[in/out] sq
 221  *   Pointer to SQ to create.
 222  * @param[in] socket
 223  *   Socket to use for allocation.
 224  * @param[in] uar
 225  *   User Access Region object.
 226  * @param[in] pdn
 227  *   Protection Domain number to use.
 228  * @param[in] log_desc_n
 229  *   Log of number of descriptors in queue.
 230  *
 231  * @return
 232  *   0 on success, a negative errno value otherwise and rte_errno is set.
 233  */
 234 static int
 235 mlx5_aso_sq_create(void *ctx, struct mlx5_aso_sq *sq, int socket,
 236                    void *uar, uint32_t pdn,  uint16_t log_desc_n,
 237                    uint32_t ts_format)
 238 {
 239         struct mlx5_devx_create_sq_attr attr = {
 240                 .user_index = 0xFFFF,
 241                 .wq_attr = (struct mlx5_devx_wq_attr){
 242                         .pd = pdn,
 243                         .uar_page = mlx5_os_get_devx_uar_page_id(uar),
 244                 },
 245                 .ts_format = mlx5_ts_format_conv(ts_format),
 246         };
 247         struct mlx5_devx_modify_sq_attr modify_attr = {
 248                 .state = MLX5_SQC_STATE_RDY,
 249         };
 250         uint16_t log_wqbb_n;
 251         int ret;
 252
 253         if (mlx5_aso_cq_create(ctx, &sq->cq, log_desc_n, socket,
 254                                mlx5_os_get_devx_uar_page_id(uar)))
 255                 goto error;
 256         sq->log_desc_n = log_desc_n;
 257         attr.cqn = sq->cq.cq_obj.cq->id;
 258         /* for mlx5_aso_wqe that is twice the size of mlx5_wqe */
 259         log_wqbb_n = log_desc_n + 1;
 260         ret = mlx5_devx_sq_create(ctx, &sq->sq_obj, log_wqbb_n, &attr, socket);
 261         if (ret) {
 262                 DRV_LOG(ERR, "Can't create SQ object.");
 263                 rte_errno = ENOMEM;
 264                 goto error;
 265         }
 266         ret = mlx5_devx_cmd_modify_sq(sq->sq_obj.sq, &modify_attr);
 267         if (ret) {
 268                 DRV_LOG(ERR, "Can't change SQ state to ready.");
 269                 rte_errno = ENOMEM;
 270                 goto error;
 271         }
 272         sq->pi = 0;
 273         sq->head = 0;
 274         sq->tail = 0;
 275         sq->sqn = sq->sq_obj.sq->id;
 276         sq->uar_addr = mlx5_os_get_devx_uar_reg_addr(uar);
 277         rte_spinlock_init(&sq->sqsl);
 278         return 0;
 279 error:
 280         mlx5_aso_destroy_sq(sq);
 281         return -1;
 282 }
 283
 284 /**
 285  * API to create and initialize Send Queue used for ASO access.
 286  *
 287  * @param[in] sh
 288  *   Pointer to shared device context.
 289  *
 290  * @return
 291  *   0 on success, a negative errno value otherwise and rte_errno is set.
 292  */
 293 int
 294 mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh,
 295                         enum mlx5_access_aso_opc_mod aso_opc_mod)
 296 {
 297         uint32_t sq_desc_n = 1 << MLX5_ASO_QUEUE_LOG_DESC;
 298
 299         switch (aso_opc_mod) {
 300         case ASO_OPC_MOD_FLOW_HIT:
 301                 if (mlx5_aso_devx_reg_mr(sh->ctx,
 302                         (MLX5_ASO_AGE_ACTIONS_PER_POOL / 8) *
 303                         sq_desc_n, &sh->aso_age_mng->aso_sq.mr, 0, sh->pdn))
 304                         return -1;
 305                 if (mlx5_aso_sq_create(sh->ctx, &sh->aso_age_mng->aso_sq, 0,
 306                                   sh->tx_uar, sh->pdn, MLX5_ASO_QUEUE_LOG_DESC,
 307                                   sh->sq_ts_format)) {
 308                         mlx5_aso_devx_dereg_mr(&sh->aso_age_mng->aso_sq.mr);
 309                         return -1;
 310                 }
 311                 mlx5_aso_age_init_sq(&sh->aso_age_mng->aso_sq);
 312                 break;
 313         case ASO_OPC_MOD_POLICER:
 314                 if (mlx5_aso_sq_create(sh->ctx, &sh->mtrmng->sq, 0,
 315                                   sh->tx_uar, sh->pdn, MLX5_ASO_QUEUE_LOG_DESC,
 316                                   sh->sq_ts_format))
 317                         return -1;
 318                 mlx5_aso_mtr_init_sq(&sh->mtrmng->sq);
 319                 break;
 320         default:
 321                 DRV_LOG(ERR, "Unknown ASO operation mode");
 322                 return -1;
 323         }
 324         return 0;
 325 }
 326
 327 /**
 328  * API to destroy Send Queue used for ASO access.
 329  *
 330  * @param[in] sh
 331  *   Pointer to shared device context.
 332  */
 333 void
 334 mlx5_aso_queue_uninit(struct mlx5_dev_ctx_shared *sh,
 335                                 enum mlx5_access_aso_opc_mod aso_opc_mod)
 336 {
 337         struct mlx5_aso_sq *sq;
 338
 339         switch (aso_opc_mod) {
 340         case ASO_OPC_MOD_FLOW_HIT:
 341                 mlx5_aso_devx_dereg_mr(&sh->aso_age_mng->aso_sq.mr);
 342                 sq = &sh->aso_age_mng->aso_sq;
 343                 break;
 344         case ASO_OPC_MOD_POLICER:
 345                 sq = &sh->mtrmng->sq;
 346                 break;
 347         default:
 348                 DRV_LOG(ERR, "Unknown ASO operation mode");
 349                 return;
 350         }
 351         mlx5_aso_destroy_sq(sq);
 352 }
 353
 354 /**
 355  * Write a burst of WQEs to ASO SQ.
 356  *
 357  * @param[in] mng
 358  *   ASO management data, contains the SQ.
 359  * @param[in] n
 360  *   Index of the last valid pool.
 361  *
 362  * @return
 363  *   Number of WQEs in burst.
 364  */
 365 static uint16_t
 366 mlx5_aso_sq_enqueue_burst(struct mlx5_aso_age_mng *mng, uint16_t n)
 367 {
 368         volatile struct mlx5_aso_wqe *wqe;
 369         struct mlx5_aso_sq *sq = &mng->aso_sq;
 370         struct mlx5_aso_age_pool *pool;
 371         uint16_t size = 1 << sq->log_desc_n;
 372         uint16_t mask = size - 1;
 373         uint16_t max;
 374         uint16_t start_head = sq->head;
 375
 376         max = RTE_MIN(size - (uint16_t)(sq->head - sq->tail), n - sq->next);
 377         if (unlikely(!max))
 378                 return 0;
 379         sq->elts[start_head & mask].burst_size = max;
 380         do {
 381                 wqe = &sq->sq_obj.aso_wqes[sq->head & mask];
 382                 rte_prefetch0(&sq->sq_obj.aso_wqes[(sq->head + 1) & mask]);
 383                 /* Fill next WQE. */
 384                 rte_spinlock_lock(&mng->resize_sl);
 385                 pool = mng->pools[sq->next];
 386                 rte_spinlock_unlock(&mng->resize_sl);
 387                 sq->elts[sq->head & mask].pool = pool;
 388                 wqe->general_cseg.misc =
 389                                 rte_cpu_to_be_32(((struct mlx5_devx_obj *)
 390                                                  (pool->flow_hit_aso_obj))->id);
 391                 wqe->general_cseg.flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR <<
 392                                                          MLX5_COMP_MODE_OFFSET);
 393                 wqe->general_cseg.opcode = rte_cpu_to_be_32
 394                                                 (MLX5_OPCODE_ACCESS_ASO |
 395                                                  (ASO_OPC_MOD_FLOW_HIT <<
 396                                                   WQE_CSEG_OPC_MOD_OFFSET) |
 397                                                  (sq->pi <<
 398                                                   WQE_CSEG_WQE_INDEX_OFFSET));
 399                 sq->pi += 2; /* Each WQE contains 2 WQEBB's. */
 400                 sq->head++;
 401                 sq->next++;
 402                 max--;
 403         } while (max);
 404         wqe->general_cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<
 405                                                          MLX5_COMP_MODE_OFFSET);
 406         rte_io_wmb();
 407         sq->sq_obj.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(sq->pi);
 408         rte_wmb();
 409         *sq->uar_addr = *(volatile uint64_t *)wqe; /* Assume 64 bit ARCH.*/
 410         rte_wmb();
 411         return sq->elts[start_head & mask].burst_size;
 412 }
 413
 414 /**
 415  * Debug utility function. Dump contents of error CQE and WQE.
 416  *
 417  * @param[in] cqe
 418  *   Error CQE to dump.
 419  * @param[in] wqe
 420  *   Error WQE to dump.
 421  */
 422 static void
 423 mlx5_aso_dump_err_objs(volatile uint32_t *cqe, volatile uint32_t *wqe)
 424 {
 425         int i;
 426
 427         DRV_LOG(ERR, "Error cqe:");
 428         for (i = 0; i < 16; i += 4)
 429                 DRV_LOG(ERR, "%08X %08X %08X %08X", cqe[i], cqe[i + 1],
 430                         cqe[i + 2], cqe[i + 3]);
 431         DRV_LOG(ERR, "\nError wqe:");
 432         for (i = 0; i < (int)sizeof(struct mlx5_aso_wqe) / 4; i += 4)
 433                 DRV_LOG(ERR, "%08X %08X %08X %08X", wqe[i], wqe[i + 1],
 434                         wqe[i + 2], wqe[i + 3]);
 435 }
 436
 437 /**
 438  * Handle case of error CQE.
 439  *
 440  * @param[in] sq
 441  *   ASO SQ to use.
 442  */
 443 static void
 444 mlx5_aso_cqe_err_handle(struct mlx5_aso_sq *sq)
 445 {
 446         struct mlx5_aso_cq *cq = &sq->cq;
 447         uint32_t idx = cq->cq_ci & ((1 << cq->log_desc_n) - 1);
 448         volatile struct mlx5_err_cqe *cqe =
 449                         (volatile struct mlx5_err_cqe *)&cq->cq_obj.cqes[idx];
 450
 451         cq->errors++;
 452         idx = rte_be_to_cpu_16(cqe->wqe_counter) & (1u << sq->log_desc_n);
 453         mlx5_aso_dump_err_objs((volatile uint32_t *)cqe,
 454                                (volatile uint32_t *)&sq->sq_obj.aso_wqes[idx]);
 455 }
 456
 457 /**
 458  * Update ASO objects upon completion.
 459  *
 460  * @param[in] sh
 461  *   Shared device context.
 462  * @param[in] n
 463  *   Number of completed ASO objects.
 464  */
 465 static void
 466 mlx5_aso_age_action_update(struct mlx5_dev_ctx_shared *sh, uint16_t n)
 467 {
 468         struct mlx5_aso_age_mng *mng = sh->aso_age_mng;
 469         struct mlx5_aso_sq *sq = &mng->aso_sq;
 470         struct mlx5_age_info *age_info;
 471         const uint16_t size = 1 << sq->log_desc_n;
 472         const uint16_t mask = size - 1;
 473         const uint64_t curr = MLX5_CURR_TIME_SEC;
 474         uint16_t expected = AGE_CANDIDATE;
 475         uint16_t i;
 476
 477         for (i = 0; i < n; ++i) {
 478                 uint16_t idx = (sq->tail + i) & mask;
 479                 struct mlx5_aso_age_pool *pool = sq->elts[idx].pool;
 480                 uint64_t diff = curr - pool->time_of_last_age_check;
 481                 uint64_t *addr = sq->mr.buf;
 482                 int j;
 483
 484                 addr += idx * MLX5_ASO_AGE_ACTIONS_PER_POOL / 64;
 485                 pool->time_of_last_age_check = curr;
 486                 for (j = 0; j < MLX5_ASO_AGE_ACTIONS_PER_POOL; j++) {
 487                         struct mlx5_aso_age_action *act = &pool->actions[j];
 488                         struct mlx5_age_param *ap = &act->age_params;
 489                         uint8_t byte;
 490                         uint8_t offset;
 491                         uint8_t *u8addr;
 492                         uint8_t hit;
 493
 494                         if (__atomic_load_n(&ap->state, __ATOMIC_RELAXED) !=
 495                                             AGE_CANDIDATE)
 496                                 continue;
 497                         byte = 63 - (j / 8);
 498                         offset = j % 8;
 499                         u8addr = (uint8_t *)addr;
 500                         hit = (u8addr[byte] >> offset) & 0x1;
 501                         if (hit) {
 502                                 __atomic_store_n(&ap->sec_since_last_hit, 0,
 503                                                  __ATOMIC_RELAXED);
 504                         } else {
 505                                 struct mlx5_priv *priv;
 506
 507                                 __atomic_fetch_add(&ap->sec_since_last_hit,
 508                                                    diff, __ATOMIC_RELAXED);
 509                                 /* If timeout passed add to aged-out list. */
 510                                 if (ap->sec_since_last_hit <= ap->timeout)
 511                                         continue;
 512                                 priv =
 513                                 rte_eth_devices[ap->port_id].data->dev_private;
 514                                 age_info = GET_PORT_AGE_INFO(priv);
 515                                 rte_spinlock_lock(&age_info->aged_sl);
 516                                 if (__atomic_compare_exchange_n(&ap->state,
 517                                                                 &expected,
 518                                                                 AGE_TMOUT,
 519                                                                 false,
 520                                                                __ATOMIC_RELAXED,
 521                                                             __ATOMIC_RELAXED)) {
 522                                         LIST_INSERT_HEAD(&age_info->aged_aso,
 523                                                          act, next);
 524                                         MLX5_AGE_SET(age_info,
 525                                                      MLX5_AGE_EVENT_NEW);
 526                                 }
 527                                 rte_spinlock_unlock(&age_info->aged_sl);
 528                         }
 529                 }
 530         }
 531         mlx5_age_event_prepare(sh);
 532 }
 533
 534 /**
 535  * Handle completions from WQEs sent to ASO SQ.
 536  *
 537  * @param[in] sh
 538  *   Shared device context.
 539  *
 540  * @return
 541  *   Number of CQEs handled.
 542  */
 543 static uint16_t
 544 mlx5_aso_completion_handle(struct mlx5_dev_ctx_shared *sh)
 545 {
 546         struct mlx5_aso_age_mng *mng = sh->aso_age_mng;
 547         struct mlx5_aso_sq *sq = &mng->aso_sq;
 548         struct mlx5_aso_cq *cq = &sq->cq;
 549         volatile struct mlx5_cqe *restrict cqe;
 550         const unsigned int cq_size = 1 << cq->log_desc_n;
 551         const unsigned int mask = cq_size - 1;
 552         uint32_t idx;
 553         uint32_t next_idx = cq->cq_ci & mask;
 554         const uint16_t max = (uint16_t)(sq->head - sq->tail);
 555         uint16_t i = 0;
 556         int ret;
 557         if (unlikely(!max))
 558                 return 0;
 559         do {
 560                 idx = next_idx;
 561                 next_idx = (cq->cq_ci + 1) & mask;
 562                 rte_prefetch0(&cq->cq_obj.cqes[next_idx]);
 563                 cqe = &cq->cq_obj.cqes[idx];
 564                 ret = check_cqe(cqe, cq_size, cq->cq_ci);
 565                 /*
 566                  * Be sure owner read is done before any other cookie field or
 567                  * opaque field.
 568                  */
 569                 rte_io_rmb();
 570                 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
 571                         if (likely(ret == MLX5_CQE_STATUS_HW_OWN))
 572                                 break;
 573                         mlx5_aso_cqe_err_handle(sq);
 574                 } else {
 575                         i += sq->elts[(sq->tail + i) & mask].burst_size;
 576                 }
 577                 cq->cq_ci++;
 578         } while (1);
 579         if (likely(i)) {
 580                 mlx5_aso_age_action_update(sh, i);
 581                 sq->tail += i;
 582                 rte_io_wmb();
 583                 cq->cq_obj.db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);
 584         }
 585         return i;
 586 }
 587
 588 /**
 589  * Periodically read CQEs and send WQEs to ASO SQ.
 590  *
 591  * @param[in] arg
 592  *   Shared device context containing the ASO SQ.
 593  */
 594 static void
 595 mlx5_flow_aso_alarm(void *arg)
 596 {
 597         struct mlx5_dev_ctx_shared *sh = arg;
 598         struct mlx5_aso_sq *sq = &sh->aso_age_mng->aso_sq;
 599         uint32_t us = 100u;
 600         uint16_t n;
 601
 602         rte_spinlock_lock(&sh->aso_age_mng->resize_sl);
 603         n = sh->aso_age_mng->next;
 604         rte_spinlock_unlock(&sh->aso_age_mng->resize_sl);
 605         mlx5_aso_completion_handle(sh);
 606         if (sq->next == n) {
 607                 /* End of loop: wait 1 second. */
 608                 us = US_PER_S;
 609                 sq->next = 0;
 610         }
 611         mlx5_aso_sq_enqueue_burst(sh->aso_age_mng, n);
 612         if (rte_eal_alarm_set(us, mlx5_flow_aso_alarm, sh))
 613                 DRV_LOG(ERR, "Cannot reinitialize aso alarm.");
 614 }
 615
 616 /**
 617  * API to start ASO access using ASO SQ.
 618  *
 619  * @param[in] sh
 620  *   Pointer to shared device context.
 621  *
 622  * @return
 623  *   0 on success, a negative errno value otherwise and rte_errno is set.
 624  */
 625 int
 626 mlx5_aso_flow_hit_queue_poll_start(struct mlx5_dev_ctx_shared *sh)
 627 {
 628         if (rte_eal_alarm_set(US_PER_S, mlx5_flow_aso_alarm, sh)) {
 629                 DRV_LOG(ERR, "Cannot reinitialize ASO age alarm.");
 630                 return -rte_errno;
 631         }
 632         return 0;
 633 }
 634
 635 /**
 636  * API to stop ASO access using ASO SQ.
 637  *
 638  * @param[in] sh
 639  *   Pointer to shared device context.
 640  *
 641  * @return
 642  *   0 on success, a negative errno value otherwise and rte_errno is set.
 643  */
 644 int
 645 mlx5_aso_flow_hit_queue_poll_stop(struct mlx5_dev_ctx_shared *sh)
 646 {
 647         int retries = 1024;
 648
 649         if (!sh->aso_age_mng->aso_sq.sq_obj.sq)
 650                 return -EINVAL;
 651         rte_errno = 0;
 652         while (--retries) {
 653                 rte_eal_alarm_cancel(mlx5_flow_aso_alarm, sh);
 654                 if (rte_errno != EINPROGRESS)
 655                         break;
 656                 rte_pause();
 657         }
 658         return -rte_errno;
 659 }
 660
 661 static uint16_t
 662 mlx5_aso_mtr_sq_enqueue_single(struct mlx5_aso_sq *sq,
 663                 struct mlx5_aso_mtr *aso_mtr)
 664 {
 665         volatile struct mlx5_aso_wqe *wqe = NULL;
 666         struct mlx5_flow_meter_info *fm = NULL;
 667         uint16_t size = 1 << sq->log_desc_n;
 668         uint16_t mask = size - 1;
 669         uint16_t res;
 670         uint32_t dseg_idx = 0;
 671         struct mlx5_aso_mtr_pool *pool = NULL;
 672
 673         rte_spinlock_lock(&sq->sqsl);
 674         res = size - (uint16_t)(sq->head - sq->tail);
 675         if (unlikely(!res)) {
 676                 DRV_LOG(ERR, "Fail: SQ is full and no free WQE to send");
 677                 rte_spinlock_unlock(&sq->sqsl);
 678                 return 0;
 679         }
 680         wqe = &sq->sq_obj.aso_wqes[sq->head & mask];
 681         rte_prefetch0(&sq->sq_obj.aso_wqes[(sq->head + 1) & mask]);
 682         /* Fill next WQE. */
 683         fm = &aso_mtr->fm;
 684         sq->elts[sq->head & mask].mtr = aso_mtr;
 685         pool = container_of(aso_mtr, struct mlx5_aso_mtr_pool,
 686                         mtrs[aso_mtr->offset]);
 687         wqe->general_cseg.misc = rte_cpu_to_be_32(pool->devx_obj->id +
 688                         (aso_mtr->offset >> 1));
 689         wqe->general_cseg.opcode = rte_cpu_to_be_32(MLX5_OPCODE_ACCESS_ASO |
 690                         (ASO_OPC_MOD_POLICER <<
 691                         WQE_CSEG_OPC_MOD_OFFSET) |
 692                         sq->pi << WQE_CSEG_WQE_INDEX_OFFSET);
 693         /* There are 2 meters in one ASO cache line. */
 694         dseg_idx = aso_mtr->offset & 0x1;
 695         wqe->aso_cseg.data_mask =
 696                 RTE_BE64(MLX5_IFC_FLOW_METER_PARAM_MASK << (32 * !dseg_idx));
 697         if (fm->is_enable) {
 698                 wqe->aso_dseg.mtrs[dseg_idx].cbs_cir =
 699                         fm->profile->srtcm_prm.cbs_cir;
 700                 wqe->aso_dseg.mtrs[dseg_idx].ebs_eir =
 701                         fm->profile->srtcm_prm.ebs_eir;
 702         } else {
 703                 wqe->aso_dseg.mtrs[dseg_idx].cbs_cir =
 704                         RTE_BE32(MLX5_IFC_FLOW_METER_DISABLE_CBS_CIR_VAL);
 705                 wqe->aso_dseg.mtrs[dseg_idx].ebs_eir = 0;
 706         }
 707         sq->head++;
 708         sq->pi += 2;/* Each WQE contains 2 WQEBB's. */
 709         rte_io_wmb();
 710         sq->sq_obj.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(sq->pi);
 711         rte_wmb();
 712         *sq->uar_addr = *(volatile uint64_t *)wqe; /* Assume 64 bit ARCH. */
 713         rte_wmb();
 714         rte_spinlock_unlock(&sq->sqsl);
 715         return 1;
 716 }
 717
 718 static void
 719 mlx5_aso_mtrs_status_update(struct mlx5_aso_sq *sq, uint16_t aso_mtrs_nums)
 720 {
 721         uint16_t size = 1 << sq->log_desc_n;
 722         uint16_t mask = size - 1;
 723         uint16_t i;
 724         struct mlx5_aso_mtr *aso_mtr = NULL;
 725         uint8_t exp_state = ASO_METER_WAIT;
 726
 727         for (i = 0; i < aso_mtrs_nums; ++i) {
 728                 aso_mtr = sq->elts[(sq->tail + i) & mask].mtr;
 729                 MLX5_ASSERT(aso_mtr);
 730                 (void)__atomic_compare_exchange_n(&aso_mtr->state,
 731                                 &exp_state, ASO_METER_READY,
 732                                 false, __ATOMIC_RELAXED, __ATOMIC_RELAXED);
 733         }
 734 }
 735
 736 static void
 737 mlx5_aso_mtr_completion_handle(struct mlx5_aso_sq *sq)
 738 {
 739         struct mlx5_aso_cq *cq = &sq->cq;
 740         volatile struct mlx5_cqe *restrict cqe;
 741         const unsigned int cq_size = 1 << cq->log_desc_n;
 742         const unsigned int mask = cq_size - 1;
 743         uint32_t idx;
 744         uint32_t next_idx = cq->cq_ci & mask;
 745         uint16_t max;
 746         uint16_t n = 0;
 747         int ret;
 748
 749         rte_spinlock_lock(&sq->sqsl);
 750         max = (uint16_t)(sq->head - sq->tail);
 751         if (unlikely(!max)) {
 752                 rte_spinlock_unlock(&sq->sqsl);
 753                 return;
 754         }
 755         do {
 756                 idx = next_idx;
 757                 next_idx = (cq->cq_ci + 1) & mask;
 758                 rte_prefetch0(&cq->cq_obj.cqes[next_idx]);
 759                 cqe = &cq->cq_obj.cqes[idx];
 760                 ret = check_cqe(cqe, cq_size, cq->cq_ci);
 761                 /*
 762                  * Be sure owner read is done before any other cookie field or
 763                  * opaque field.
 764                  */
 765                 rte_io_rmb();
 766                 if (ret != MLX5_CQE_STATUS_SW_OWN) {
 767                         if (likely(ret == MLX5_CQE_STATUS_HW_OWN))
 768                                 break;
 769                         mlx5_aso_cqe_err_handle(sq);
 770                 } else {
 771                         n++;
 772                 }
 773                 cq->cq_ci++;
 774         } while (1);
 775         if (likely(n)) {
 776                 mlx5_aso_mtrs_status_update(sq, n);
 777                 sq->tail += n;
 778                 rte_io_wmb();
 779                 cq->cq_obj.db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);
 780         }
 781         rte_spinlock_unlock(&sq->sqsl);
 782 }
 783
 784 /**
 785  * Update meter parameter by send WQE.
 786  *
 787  * @param[in] dev
 788  *   Pointer to Ethernet device.
 789  * @param[in] priv
 790  *   Pointer to mlx5 private data structure.
 791  * @param[in] fm
 792  *   Pointer to flow meter to be modified.
 793  *
 794  * @return
 795  *   0 on success, a negative errno value otherwise and rte_errno is set.
 796  */
 797 int
 798 mlx5_aso_meter_update_by_wqe(struct mlx5_dev_ctx_shared *sh,
 799                         struct mlx5_aso_mtr *mtr)
 800 {
 801         struct mlx5_aso_sq *sq = &sh->mtrmng->sq;
 802         uint32_t poll_wqe_times = MLX5_MTR_POLL_WQE_CQE_TIMES;
 803
 804         do {
 805                 mlx5_aso_mtr_completion_handle(sq);
 806                 if (mlx5_aso_mtr_sq_enqueue_single(sq, mtr))
 807                         return 0;
 808                 /* Waiting for wqe resource. */
 809                 rte_delay_us_sleep(MLX5_ASO_WQE_CQE_RESPONSE_DELAY);
 810         } while (--poll_wqe_times);
 811         DRV_LOG(ERR, "Fail to send WQE for ASO meter %d",
 812                         mtr->fm.meter_id);
 813         return -1;
 814 }
 815
 816 /**
 817  * Wait for meter to be ready.
 818  *
 819  * @param[in] dev
 820  *   Pointer to Ethernet device.
 821  * @param[in] priv
 822  *   Pointer to mlx5 private data structure.
 823  * @param[in] fm
 824  *   Pointer to flow meter to be modified.
 825  *
 826  * @return
 827  *   0 on success, a negative errno value otherwise and rte_errno is set.
 828  */
 829 int
 830 mlx5_aso_mtr_wait(struct mlx5_dev_ctx_shared *sh,
 831                         struct mlx5_aso_mtr *mtr)
 832 {
 833         struct mlx5_aso_sq *sq = &sh->mtrmng->sq;
 834         uint32_t poll_cqe_times = MLX5_MTR_POLL_WQE_CQE_TIMES;
 835
 836         if (__atomic_load_n(&mtr->state, __ATOMIC_RELAXED) ==
 837                                             ASO_METER_READY)
 838                 return 0;
 839         do {
 840                 mlx5_aso_mtr_completion_handle(sq);
 841                 if (__atomic_load_n(&mtr->state, __ATOMIC_RELAXED) ==
 842                                             ASO_METER_READY)
 843                         return 0;
 844                 /* Waiting for CQE ready. */
 845                 rte_delay_us_sleep(MLX5_ASO_WQE_CQE_RESPONSE_DELAY);
 846         } while (--poll_cqe_times);
 847         DRV_LOG(ERR, "Fail to poll CQE ready for ASO meter %d",
 848                         mtr->fm.meter_id);
 849         return -1;
 850 }